2 * QLogic qlcnic NIC Driver
3 * Copyright (c) 2009-2013 QLogic Corporation
5 * See LICENSE.qlcnic for copyright and licensing details.
11 /* Reset template definitions */
12 #define QLC_83XX_RESTART_TEMPLATE_SIZE 0x2000
13 #define QLC_83XX_RESET_TEMPLATE_ADDR 0x4F0000
14 #define QLC_83XX_RESET_SEQ_VERSION 0x0101
16 #define QLC_83XX_OPCODE_NOP 0x0000
17 #define QLC_83XX_OPCODE_WRITE_LIST 0x0001
18 #define QLC_83XX_OPCODE_READ_WRITE_LIST 0x0002
19 #define QLC_83XX_OPCODE_POLL_LIST 0x0004
20 #define QLC_83XX_OPCODE_POLL_WRITE_LIST 0x0008
21 #define QLC_83XX_OPCODE_READ_MODIFY_WRITE 0x0010
22 #define QLC_83XX_OPCODE_SEQ_PAUSE 0x0020
23 #define QLC_83XX_OPCODE_SEQ_END 0x0040
24 #define QLC_83XX_OPCODE_TMPL_END 0x0080
25 #define QLC_83XX_OPCODE_POLL_READ_LIST 0x0100
27 static int qlcnic_83xx_init_default_driver(struct qlcnic_adapter *adapter);
28 static int qlcnic_83xx_configure_opmode(struct qlcnic_adapter *adapter);
29 static int qlcnic_83xx_check_heartbeat(struct qlcnic_adapter *p_dev);
30 static int qlcnic_83xx_restart_hw(struct qlcnic_adapter *adapter);
33 struct qlc_83xx_reset_hdr {
44 /* Command entry header. */
45 struct qlc_83xx_entry_hdr {
52 /* Generic poll command */
53 struct qlc_83xx_poll {
58 /* Read modify write command */
69 /* Generic command with 2 DWORD */
70 struct qlc_83xx_entry {
75 /* Generic command with 4 DWORD */
76 struct qlc_83xx_quad_entry {
82 static const char *const qlc_83xx_idc_states[] = {
94 enum qlcnic_83xx_states {
95 QLC_83XX_IDC_DEV_UNKNOWN,
96 QLC_83XX_IDC_DEV_COLD,
97 QLC_83XX_IDC_DEV_INIT,
98 QLC_83XX_IDC_DEV_READY,
99 QLC_83XX_IDC_DEV_NEED_RESET,
100 QLC_83XX_IDC_DEV_NEED_QUISCENT,
101 QLC_83XX_IDC_DEV_FAILED,
102 QLC_83XX_IDC_DEV_QUISCENT
106 qlcnic_83xx_idc_check_driver_presence_reg(struct qlcnic_adapter *adapter)
110 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
117 static void qlcnic_83xx_idc_log_state_history(struct qlcnic_adapter *adapter)
120 cur = adapter->ahw->idc.curr_state;
121 prev = adapter->ahw->idc.prev_state;
123 dev_info(&adapter->pdev->dev,
124 "current state = %s, prev state = %s\n",
125 adapter->ahw->idc.name[cur],
126 adapter->ahw->idc.name[prev]);
129 static int qlcnic_83xx_idc_update_audit_reg(struct qlcnic_adapter *adapter,
136 if (qlcnic_83xx_lock_driver(adapter))
140 val = adapter->portnum & 0xf;
143 seconds = jiffies / HZ - adapter->ahw->idc.sec_counter;
145 seconds = jiffies / HZ;
148 QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_AUDIT, val);
149 adapter->ahw->idc.sec_counter = jiffies / HZ;
152 qlcnic_83xx_unlock_driver(adapter);
157 static void qlcnic_83xx_idc_update_minor_version(struct qlcnic_adapter *adapter)
161 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_MIN_VERSION);
162 val = val & ~(0x3 << (adapter->portnum * 2));
163 val = val | (QLC_83XX_IDC_MINOR_VERSION << (adapter->portnum * 2));
164 QLCWRX(adapter->ahw, QLC_83XX_IDC_MIN_VERSION, val);
167 static int qlcnic_83xx_idc_update_major_version(struct qlcnic_adapter *adapter,
173 if (qlcnic_83xx_lock_driver(adapter))
177 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_MAJ_VERSION);
179 val = val | QLC_83XX_IDC_MAJOR_VERSION;
180 QLCWRX(adapter->ahw, QLC_83XX_IDC_MAJ_VERSION, val);
183 qlcnic_83xx_unlock_driver(adapter);
189 qlcnic_83xx_idc_update_drv_presence_reg(struct qlcnic_adapter *adapter,
190 int status, int lock)
195 if (qlcnic_83xx_lock_driver(adapter))
199 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
202 val = val | (1 << adapter->portnum);
204 val = val & ~(1 << adapter->portnum);
206 QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE, val);
207 qlcnic_83xx_idc_update_minor_version(adapter);
210 qlcnic_83xx_unlock_driver(adapter);
215 static int qlcnic_83xx_idc_check_major_version(struct qlcnic_adapter *adapter)
220 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_MAJ_VERSION);
221 version = val & 0xFF;
223 if (version != QLC_83XX_IDC_MAJOR_VERSION) {
224 dev_info(&adapter->pdev->dev,
225 "%s:mismatch. version 0x%x, expected version 0x%x\n",
226 __func__, version, QLC_83XX_IDC_MAJOR_VERSION);
233 static int qlcnic_83xx_idc_clear_registers(struct qlcnic_adapter *adapter,
239 if (qlcnic_83xx_lock_driver(adapter))
243 QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_ACK, 0);
244 /* Clear gracefull reset bit */
245 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
246 val &= ~QLC_83XX_IDC_GRACEFULL_RESET;
247 QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val);
250 qlcnic_83xx_unlock_driver(adapter);
255 static int qlcnic_83xx_idc_update_drv_ack_reg(struct qlcnic_adapter *adapter,
261 if (qlcnic_83xx_lock_driver(adapter))
265 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_ACK);
267 val = val | (1 << adapter->portnum);
269 val = val & ~(1 << adapter->portnum);
270 QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_ACK, val);
273 qlcnic_83xx_unlock_driver(adapter);
278 static int qlcnic_83xx_idc_check_timeout(struct qlcnic_adapter *adapter,
283 seconds = jiffies / HZ - adapter->ahw->idc.sec_counter;
284 if (seconds <= time_limit)
291 * qlcnic_83xx_idc_check_reset_ack_reg
293 * @adapter: adapter structure
295 * Check ACK wait limit and clear the functions which failed to ACK
297 * Return 0 if all functions have acknowledged the reset request.
299 static int qlcnic_83xx_idc_check_reset_ack_reg(struct qlcnic_adapter *adapter)
302 u32 ack, presence, val;
304 timeout = QLC_83XX_IDC_RESET_TIMEOUT_SECS;
305 ack = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_ACK);
306 presence = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
307 dev_info(&adapter->pdev->dev,
308 "%s: ack = 0x%x, presence = 0x%x\n", __func__, ack, presence);
309 if (!((ack & presence) == presence)) {
310 if (qlcnic_83xx_idc_check_timeout(adapter, timeout)) {
311 /* Clear functions which failed to ACK */
312 dev_info(&adapter->pdev->dev,
313 "%s: ACK wait exceeds time limit\n", __func__);
314 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
315 val = val & ~(ack ^ presence);
316 if (qlcnic_83xx_lock_driver(adapter))
318 QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE, val);
319 dev_info(&adapter->pdev->dev,
320 "%s: updated drv presence reg = 0x%x\n",
322 qlcnic_83xx_unlock_driver(adapter);
329 dev_info(&adapter->pdev->dev,
330 "%s: Reset ACK received from all functions\n",
337 * qlcnic_83xx_idc_tx_soft_reset
339 * @adapter: adapter structure
341 * Handle context deletion and recreation request from transmit routine
343 * Returns -EBUSY or Success (0)
346 static int qlcnic_83xx_idc_tx_soft_reset(struct qlcnic_adapter *adapter)
348 struct net_device *netdev = adapter->netdev;
350 if (test_and_set_bit(__QLCNIC_RESETTING, &adapter->state))
353 netif_device_detach(netdev);
354 qlcnic_down(adapter, netdev);
355 qlcnic_up(adapter, netdev);
356 netif_device_attach(netdev);
357 clear_bit(__QLCNIC_RESETTING, &adapter->state);
358 dev_err(&adapter->pdev->dev, "%s:\n", __func__);
360 adapter->netdev->trans_start = jiffies;
366 * qlcnic_83xx_idc_detach_driver
368 * @adapter: adapter structure
369 * Detach net interface, stop TX and cleanup resources before the HW reset.
373 static void qlcnic_83xx_idc_detach_driver(struct qlcnic_adapter *adapter)
376 struct net_device *netdev = adapter->netdev;
378 netif_device_detach(netdev);
379 /* Disable mailbox interrupt */
380 QLCWRX(adapter->ahw, QLCNIC_MBX_INTR_ENBL, 0);
381 qlcnic_down(adapter, netdev);
382 for (i = 0; i < adapter->ahw->num_msix; i++) {
383 adapter->ahw->intr_tbl[i].id = i;
384 adapter->ahw->intr_tbl[i].enabled = 0;
385 adapter->ahw->intr_tbl[i].src = 0;
390 * qlcnic_83xx_idc_attach_driver
392 * @adapter: adapter structure
394 * Re-attach and re-enable net interface
398 static void qlcnic_83xx_idc_attach_driver(struct qlcnic_adapter *adapter)
400 struct net_device *netdev = adapter->netdev;
402 if (netif_running(netdev)) {
403 if (qlcnic_up(adapter, netdev))
405 qlcnic_restore_indev_addr(netdev, NETDEV_UP);
408 netif_device_attach(netdev);
409 if (netif_running(netdev)) {
410 netif_carrier_on(netdev);
411 netif_wake_queue(netdev);
415 static int qlcnic_83xx_idc_enter_failed_state(struct qlcnic_adapter *adapter,
419 if (qlcnic_83xx_lock_driver(adapter))
423 qlcnic_83xx_idc_clear_registers(adapter, 0);
424 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, QLC_83XX_IDC_DEV_FAILED);
426 qlcnic_83xx_unlock_driver(adapter);
428 qlcnic_83xx_idc_log_state_history(adapter);
429 dev_info(&adapter->pdev->dev, "Device will enter failed state\n");
434 static int qlcnic_83xx_idc_enter_init_state(struct qlcnic_adapter *adapter,
438 if (qlcnic_83xx_lock_driver(adapter))
442 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, QLC_83XX_IDC_DEV_INIT);
445 qlcnic_83xx_unlock_driver(adapter);
450 static int qlcnic_83xx_idc_enter_need_quiesce(struct qlcnic_adapter *adapter,
454 if (qlcnic_83xx_lock_driver(adapter))
458 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE,
459 QLC_83XX_IDC_DEV_NEED_QUISCENT);
462 qlcnic_83xx_unlock_driver(adapter);
468 qlcnic_83xx_idc_enter_need_reset_state(struct qlcnic_adapter *adapter, int lock)
471 if (qlcnic_83xx_lock_driver(adapter))
475 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE,
476 QLC_83XX_IDC_DEV_NEED_RESET);
479 qlcnic_83xx_unlock_driver(adapter);
484 static int qlcnic_83xx_idc_enter_ready_state(struct qlcnic_adapter *adapter,
488 if (qlcnic_83xx_lock_driver(adapter))
492 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, QLC_83XX_IDC_DEV_READY);
494 qlcnic_83xx_unlock_driver(adapter);
500 * qlcnic_83xx_idc_find_reset_owner_id
502 * @adapter: adapter structure
504 * NIC gets precedence over ISCSI and ISCSI has precedence over FCOE.
505 * Within the same class, function with lowest PCI ID assumes ownership
507 * Returns: reset owner id or failure indication (-EIO)
510 static int qlcnic_83xx_idc_find_reset_owner_id(struct qlcnic_adapter *adapter)
512 u32 reg, reg1, reg2, i, j, owner, class;
514 reg1 = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_PARTITION_INFO_1);
515 reg2 = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_PARTITION_INFO_2);
516 owner = QLCNIC_TYPE_NIC;
522 class = (((reg & (0xF << j * 4)) >> j * 4) & 0x3);
525 if (i == (QLC_83XX_IDC_MAX_FUNC_PER_PARTITION_INFO - 1)) {
532 if (i == (QLC_83XX_IDC_MAX_CNA_FUNCTIONS - 1)) {
533 if (owner == QLCNIC_TYPE_NIC)
534 owner = QLCNIC_TYPE_ISCSI;
535 else if (owner == QLCNIC_TYPE_ISCSI)
536 owner = QLCNIC_TYPE_FCOE;
537 else if (owner == QLCNIC_TYPE_FCOE)
543 } while (i++ < QLC_83XX_IDC_MAX_CNA_FUNCTIONS);
548 static int qlcnic_83xx_idc_restart_hw(struct qlcnic_adapter *adapter, int lock)
552 ret = qlcnic_83xx_restart_hw(adapter);
555 qlcnic_83xx_idc_enter_failed_state(adapter, lock);
557 qlcnic_83xx_idc_clear_registers(adapter, lock);
558 ret = qlcnic_83xx_idc_enter_ready_state(adapter, lock);
564 static int qlcnic_83xx_idc_check_fan_failure(struct qlcnic_adapter *adapter)
568 status = QLC_SHARED_REG_RD32(adapter, QLCNIC_PEG_HALT_STATUS1);
570 if (status & QLCNIC_RCODE_FATAL_ERROR) {
571 dev_err(&adapter->pdev->dev,
572 "peg halt status1=0x%x\n", status);
573 if (QLCNIC_FWERROR_CODE(status) == QLCNIC_FWERROR_FAN_FAILURE) {
574 dev_err(&adapter->pdev->dev,
575 "On board active cooling fan failed. "
576 "Device has been halted.\n");
577 dev_err(&adapter->pdev->dev,
578 "Replace the adapter.\n");
586 static int qlcnic_83xx_idc_reattach_driver(struct qlcnic_adapter *adapter)
588 /* register for NIC IDC AEN Events */
589 qlcnic_83xx_register_nic_idc_func(adapter, 1);
591 qlcnic_83xx_enable_mbx_intrpt(adapter);
593 if (qlcnic_83xx_configure_opmode(adapter)) {
594 qlcnic_83xx_idc_enter_failed_state(adapter, 1);
598 if (adapter->nic_ops->init_driver(adapter)) {
599 qlcnic_83xx_idc_enter_failed_state(adapter, 1);
603 qlcnic_83xx_idc_attach_driver(adapter);
608 static void qlcnic_83xx_idc_update_idc_params(struct qlcnic_adapter *adapter)
610 qlcnic_83xx_idc_update_drv_presence_reg(adapter, 1, 1);
611 clear_bit(__QLCNIC_RESETTING, &adapter->state);
612 set_bit(QLC_83XX_MBX_READY, &adapter->ahw->idc.status);
613 qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1);
614 set_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status);
615 adapter->ahw->idc.quiesce_req = 0;
616 adapter->ahw->idc.delay = QLC_83XX_IDC_FW_POLL_DELAY;
617 adapter->ahw->idc.err_code = 0;
618 adapter->ahw->idc.collect_dump = 0;
622 * qlcnic_83xx_idc_ready_state_entry
624 * @adapter: adapter structure
626 * Perform ready state initialization, this routine will get invoked only
627 * once from READY state.
629 * Returns: Error code or Success(0)
632 int qlcnic_83xx_idc_ready_state_entry(struct qlcnic_adapter *adapter)
634 struct qlcnic_hardware_context *ahw = adapter->ahw;
636 if (ahw->idc.prev_state != QLC_83XX_IDC_DEV_READY) {
637 qlcnic_83xx_idc_update_idc_params(adapter);
638 /* Re-attach the device if required */
639 if ((ahw->idc.prev_state == QLC_83XX_IDC_DEV_NEED_RESET) ||
640 (ahw->idc.prev_state == QLC_83XX_IDC_DEV_INIT)) {
641 if (qlcnic_83xx_idc_reattach_driver(adapter))
650 * qlcnic_83xx_idc_vnic_pf_entry
652 * @adapter: adapter structure
654 * Ensure vNIC mode privileged function starts only after vNIC mode is
655 * enabled by management function.
656 * If vNIC mode is ready, start initialization.
661 int qlcnic_83xx_idc_vnic_pf_entry(struct qlcnic_adapter *adapter)
664 struct qlcnic_hardware_context *ahw = adapter->ahw;
666 /* Privileged function waits till mgmt function enables VNIC mode */
667 state = QLCRDX(adapter->ahw, QLC_83XX_VNIC_STATE);
668 if (state != QLCNIC_DEV_NPAR_OPER) {
669 if (!ahw->idc.vnic_wait_limit--) {
670 qlcnic_83xx_idc_enter_failed_state(adapter, 1);
673 dev_info(&adapter->pdev->dev, "vNIC mode disabled\n");
677 /* Perform one time initialization from ready state */
678 if (ahw->idc.vnic_state != QLCNIC_DEV_NPAR_OPER) {
679 qlcnic_83xx_idc_update_idc_params(adapter);
681 /* If the previous state is UNKNOWN, device will be
682 already attached properly by Init routine*/
683 if (ahw->idc.prev_state != QLC_83XX_IDC_DEV_UNKNOWN) {
684 if (qlcnic_83xx_idc_reattach_driver(adapter))
687 adapter->ahw->idc.vnic_state = QLCNIC_DEV_NPAR_OPER;
688 dev_info(&adapter->pdev->dev, "vNIC mode enabled\n");
695 static int qlcnic_83xx_idc_unknown_state(struct qlcnic_adapter *adapter)
697 adapter->ahw->idc.err_code = -EIO;
698 dev_err(&adapter->pdev->dev,
699 "%s: Device in unknown state\n", __func__);
704 * qlcnic_83xx_idc_cold_state
706 * @adapter: adapter structure
708 * If HW is up and running device will enter READY state.
709 * If firmware image from host needs to be loaded, device is
710 * forced to start with the file firmware image.
712 * Returns: Error code or Success(0)
715 static int qlcnic_83xx_idc_cold_state_handler(struct qlcnic_adapter *adapter)
717 qlcnic_83xx_idc_update_drv_presence_reg(adapter, 1, 0);
718 qlcnic_83xx_idc_update_audit_reg(adapter, 1, 0);
720 if (qlcnic_load_fw_file) {
721 qlcnic_83xx_idc_restart_hw(adapter, 0);
723 if (qlcnic_83xx_check_hw_status(adapter)) {
724 qlcnic_83xx_idc_enter_failed_state(adapter, 0);
727 qlcnic_83xx_idc_enter_ready_state(adapter, 0);
734 * qlcnic_83xx_idc_init_state
736 * @adapter: adapter structure
738 * Reset owner will restart the device from this state.
739 * Device will enter failed state if it remains
740 * in this state for more than DEV_INIT time limit.
742 * Returns: Error code or Success(0)
745 static int qlcnic_83xx_idc_init_state(struct qlcnic_adapter *adapter)
747 int timeout, ret = 0;
750 timeout = QLC_83XX_IDC_INIT_TIMEOUT_SECS;
751 if (adapter->ahw->idc.prev_state == QLC_83XX_IDC_DEV_NEED_RESET) {
752 owner = qlcnic_83xx_idc_find_reset_owner_id(adapter);
753 if (adapter->ahw->pci_func == owner)
754 ret = qlcnic_83xx_idc_restart_hw(adapter, 1);
756 ret = qlcnic_83xx_idc_check_timeout(adapter, timeout);
764 * qlcnic_83xx_idc_ready_state
766 * @adapter: adapter structure
768 * Perform IDC protocol specicifed actions after monitoring device state and
771 * Returns: Error code or Success(0)
774 static int qlcnic_83xx_idc_ready_state(struct qlcnic_adapter *adapter)
777 struct qlcnic_hardware_context *ahw = adapter->ahw;
780 /* Perform NIC configuration based ready state entry actions */
781 if (ahw->idc.state_entry(adapter))
784 if (qlcnic_check_temp(adapter)) {
785 if (ahw->temp == QLCNIC_TEMP_PANIC) {
786 qlcnic_83xx_idc_check_fan_failure(adapter);
787 dev_err(&adapter->pdev->dev,
788 "Error: device temperature %d above limits\n",
790 clear_bit(QLC_83XX_MBX_READY, &ahw->idc.status);
791 set_bit(__QLCNIC_RESETTING, &adapter->state);
792 qlcnic_83xx_idc_detach_driver(adapter);
793 qlcnic_83xx_idc_enter_failed_state(adapter, 1);
798 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
799 ret = qlcnic_83xx_check_heartbeat(adapter);
801 adapter->flags |= QLCNIC_FW_HANG;
802 if (!(val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY)) {
803 clear_bit(QLC_83XX_MBX_READY, &ahw->idc.status);
804 set_bit(__QLCNIC_RESETTING, &adapter->state);
805 qlcnic_83xx_idc_enter_need_reset_state(adapter, 1);
810 if ((val & QLC_83XX_IDC_GRACEFULL_RESET) || ahw->idc.collect_dump) {
811 /* Move to need reset state and prepare for reset */
812 qlcnic_83xx_idc_enter_need_reset_state(adapter, 1);
816 /* Check for soft reset request */
817 if (ahw->reset_context &&
818 !(val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY)) {
819 qlcnic_83xx_idc_tx_soft_reset(adapter);
823 /* Move to need quiesce state if requested */
824 if (adapter->ahw->idc.quiesce_req) {
825 qlcnic_83xx_idc_enter_need_quiesce(adapter, 1);
826 qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1);
834 * qlcnic_83xx_idc_need_reset_state
836 * @adapter: adapter structure
838 * Device will remain in this state until:
839 * Reset request ACK's are recieved from all the functions
840 * Wait time exceeds max time limit
842 * Returns: Error code or Success(0)
845 static int qlcnic_83xx_idc_need_reset_state(struct qlcnic_adapter *adapter)
849 if (adapter->ahw->idc.prev_state != QLC_83XX_IDC_DEV_NEED_RESET) {
850 qlcnic_83xx_idc_update_drv_ack_reg(adapter, 1, 1);
851 qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1);
852 set_bit(__QLCNIC_RESETTING, &adapter->state);
853 clear_bit(QLC_83XX_MBX_READY, &adapter->ahw->idc.status);
854 if (adapter->ahw->nic_mode == QLC_83XX_VIRTUAL_NIC_MODE)
855 qlcnic_83xx_disable_vnic_mode(adapter, 1);
856 qlcnic_83xx_idc_detach_driver(adapter);
859 /* Check ACK from other functions */
860 ret = qlcnic_83xx_idc_check_reset_ack_reg(adapter);
862 dev_info(&adapter->pdev->dev,
863 "%s: Waiting for reset ACK\n", __func__);
867 /* Transit to INIT state and restart the HW */
868 qlcnic_83xx_idc_enter_init_state(adapter, 1);
873 static int qlcnic_83xx_idc_need_quiesce_state(struct qlcnic_adapter *adapter)
875 dev_err(&adapter->pdev->dev, "%s: TBD\n", __func__);
879 static int qlcnic_83xx_idc_failed_state(struct qlcnic_adapter *adapter)
881 dev_err(&adapter->pdev->dev, "%s: please restart!!\n", __func__);
882 adapter->ahw->idc.err_code = -EIO;
887 static int qlcnic_83xx_idc_quiesce_state(struct qlcnic_adapter *adapter)
889 dev_info(&adapter->pdev->dev, "%s: TBD\n", __func__);
893 static int qlcnic_83xx_idc_check_state_validity(struct qlcnic_adapter *adapter,
898 cur = adapter->ahw->idc.curr_state;
899 prev = adapter->ahw->idc.prev_state;
902 if ((next < QLC_83XX_IDC_DEV_COLD) ||
903 (next > QLC_83XX_IDC_DEV_QUISCENT)) {
904 dev_err(&adapter->pdev->dev,
905 "%s: curr %d, prev %d, next state %d is invalid\n",
906 __func__, cur, prev, state);
910 if ((cur == QLC_83XX_IDC_DEV_UNKNOWN) &&
911 (prev == QLC_83XX_IDC_DEV_UNKNOWN)) {
912 if ((next != QLC_83XX_IDC_DEV_COLD) &&
913 (next != QLC_83XX_IDC_DEV_READY)) {
914 dev_err(&adapter->pdev->dev,
915 "%s: failed, cur %d prev %d next %d\n",
916 __func__, cur, prev, next);
921 if (next == QLC_83XX_IDC_DEV_INIT) {
922 if ((prev != QLC_83XX_IDC_DEV_INIT) &&
923 (prev != QLC_83XX_IDC_DEV_COLD) &&
924 (prev != QLC_83XX_IDC_DEV_NEED_RESET)) {
925 dev_err(&adapter->pdev->dev,
926 "%s: failed, cur %d prev %d next %d\n",
927 __func__, cur, prev, next);
935 static void qlcnic_83xx_periodic_tasks(struct qlcnic_adapter *adapter)
937 if (adapter->fhash.fnum)
938 qlcnic_prune_lb_filters(adapter);
942 * qlcnic_83xx_idc_poll_dev_state
944 * @work: kernel work queue structure used to schedule the function
946 * Poll device state periodically and perform state specific
947 * actions defined by Inter Driver Communication (IDC) protocol.
952 void qlcnic_83xx_idc_poll_dev_state(struct work_struct *work)
954 struct qlcnic_adapter *adapter;
957 adapter = container_of(work, struct qlcnic_adapter, fw_work.work);
958 state = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_STATE);
960 if (qlcnic_83xx_idc_check_state_validity(adapter, state)) {
961 qlcnic_83xx_idc_log_state_history(adapter);
962 adapter->ahw->idc.curr_state = QLC_83XX_IDC_DEV_UNKNOWN;
964 adapter->ahw->idc.curr_state = state;
967 switch (adapter->ahw->idc.curr_state) {
968 case QLC_83XX_IDC_DEV_READY:
969 qlcnic_83xx_idc_ready_state(adapter);
971 case QLC_83XX_IDC_DEV_NEED_RESET:
972 qlcnic_83xx_idc_need_reset_state(adapter);
974 case QLC_83XX_IDC_DEV_NEED_QUISCENT:
975 qlcnic_83xx_idc_need_quiesce_state(adapter);
977 case QLC_83XX_IDC_DEV_FAILED:
978 qlcnic_83xx_idc_failed_state(adapter);
980 case QLC_83XX_IDC_DEV_INIT:
981 qlcnic_83xx_idc_init_state(adapter);
983 case QLC_83XX_IDC_DEV_QUISCENT:
984 qlcnic_83xx_idc_quiesce_state(adapter);
987 qlcnic_83xx_idc_unknown_state(adapter);
990 adapter->ahw->idc.prev_state = adapter->ahw->idc.curr_state;
991 qlcnic_83xx_periodic_tasks(adapter);
993 /* Re-schedule the function */
994 if (test_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status))
995 qlcnic_schedule_work(adapter, qlcnic_83xx_idc_poll_dev_state,
996 adapter->ahw->idc.delay);
999 static void qlcnic_83xx_setup_idc_parameters(struct qlcnic_adapter *adapter)
1001 u32 idc_params, val;
1003 if (qlcnic_83xx_lockless_flash_read32(adapter,
1004 QLC_83XX_IDC_FLASH_PARAM_ADDR,
1005 (u8 *)&idc_params, 1)) {
1006 dev_info(&adapter->pdev->dev,
1007 "%s:failed to get IDC params from flash\n", __func__);
1008 adapter->dev_init_timeo = QLC_83XX_IDC_INIT_TIMEOUT_SECS;
1009 adapter->reset_ack_timeo = QLC_83XX_IDC_RESET_TIMEOUT_SECS;
1011 adapter->dev_init_timeo = idc_params & 0xFFFF;
1012 adapter->reset_ack_timeo = ((idc_params >> 16) & 0xFFFF);
1015 adapter->ahw->idc.curr_state = QLC_83XX_IDC_DEV_UNKNOWN;
1016 adapter->ahw->idc.prev_state = QLC_83XX_IDC_DEV_UNKNOWN;
1017 adapter->ahw->idc.delay = QLC_83XX_IDC_FW_POLL_DELAY;
1018 adapter->ahw->idc.err_code = 0;
1019 adapter->ahw->idc.collect_dump = 0;
1020 adapter->ahw->idc.name = (char **)qlc_83xx_idc_states;
1022 clear_bit(__QLCNIC_RESETTING, &adapter->state);
1023 set_bit(QLC_83XX_MBX_READY, &adapter->ahw->idc.status);
1024 set_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status);
1026 /* Check if reset recovery is disabled */
1027 if (!qlcnic_auto_fw_reset) {
1028 /* Propagate do not reset request to other functions */
1029 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1030 val = val | QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY;
1031 QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val);
1036 qlcnic_83xx_idc_first_to_load_function_handler(struct qlcnic_adapter *adapter)
1040 if (qlcnic_83xx_lock_driver(adapter))
1043 /* Clear driver lock register */
1044 QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, 0);
1045 if (qlcnic_83xx_idc_update_major_version(adapter, 0)) {
1046 qlcnic_83xx_unlock_driver(adapter);
1050 state = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_STATE);
1051 if (qlcnic_83xx_idc_check_state_validity(adapter, state)) {
1052 qlcnic_83xx_unlock_driver(adapter);
1056 if (state != QLC_83XX_IDC_DEV_COLD && qlcnic_load_fw_file) {
1057 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE,
1058 QLC_83XX_IDC_DEV_COLD);
1059 state = QLC_83XX_IDC_DEV_COLD;
1062 adapter->ahw->idc.curr_state = state;
1063 /* First to load function should cold boot the device */
1064 if (state == QLC_83XX_IDC_DEV_COLD)
1065 qlcnic_83xx_idc_cold_state_handler(adapter);
1067 /* Check if reset recovery is enabled */
1068 if (qlcnic_auto_fw_reset) {
1069 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1070 val = val & ~QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY;
1071 QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val);
1074 qlcnic_83xx_unlock_driver(adapter);
1079 static int qlcnic_83xx_idc_init(struct qlcnic_adapter *adapter)
1083 qlcnic_83xx_setup_idc_parameters(adapter);
1085 if (qlcnic_83xx_get_reset_instruction_template(adapter))
1088 if (!qlcnic_83xx_idc_check_driver_presence_reg(adapter)) {
1089 if (qlcnic_83xx_idc_first_to_load_function_handler(adapter))
1092 if (qlcnic_83xx_idc_check_major_version(adapter))
1096 qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1);
1101 void qlcnic_83xx_idc_exit(struct qlcnic_adapter *adapter)
1106 while (test_and_set_bit(__QLCNIC_RESETTING, &adapter->state))
1107 usleep_range(10000, 11000);
1109 id = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
1112 if (id == adapter->portnum) {
1113 dev_err(&adapter->pdev->dev,
1114 "%s: wait for lock recovery.. %d\n", __func__, id);
1116 id = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
1120 /* Clear driver presence bit */
1121 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
1122 val = val & ~(1 << adapter->portnum);
1123 QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE, val);
1124 clear_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status);
1125 clear_bit(__QLCNIC_RESETTING, &adapter->state);
1127 cancel_delayed_work_sync(&adapter->fw_work);
1130 void qlcnic_83xx_idc_request_reset(struct qlcnic_adapter *adapter, u32 key)
1134 if (qlcnic_83xx_lock_driver(adapter)) {
1135 dev_err(&adapter->pdev->dev,
1136 "%s:failed, please retry\n", __func__);
1140 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1141 if ((val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY) ||
1142 !qlcnic_auto_fw_reset) {
1143 dev_err(&adapter->pdev->dev,
1144 "%s:failed, device in non reset mode\n", __func__);
1145 qlcnic_83xx_unlock_driver(adapter);
1149 if (key == QLCNIC_FORCE_FW_RESET) {
1150 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1151 val = val | QLC_83XX_IDC_GRACEFULL_RESET;
1152 QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val);
1153 } else if (key == QLCNIC_FORCE_FW_DUMP_KEY) {
1154 adapter->ahw->idc.collect_dump = 1;
1157 qlcnic_83xx_unlock_driver(adapter);
1161 static int qlcnic_83xx_copy_bootloader(struct qlcnic_adapter *adapter)
1168 src = QLC_83XX_BOOTLOADER_FLASH_ADDR;
1169 dest = QLCRDX(adapter->ahw, QLCNIC_BOOTLOADER_ADDR);
1170 size = QLCRDX(adapter->ahw, QLCNIC_BOOTLOADER_SIZE);
1172 /* alignment check */
1174 size = (size + 16) & ~0xF;
1176 p_cache = kzalloc(size, GFP_KERNEL);
1177 if (p_cache == NULL)
1180 ret = qlcnic_83xx_lockless_flash_read32(adapter, src, p_cache,
1181 size / sizeof(u32));
1186 /* 16 byte write to MS memory */
1187 ret = qlcnic_83xx_ms_mem_write128(adapter, dest, (u32 *)p_cache,
1198 static int qlcnic_83xx_copy_fw_file(struct qlcnic_adapter *adapter)
1206 dest = QLCRDX(adapter->ahw, QLCNIC_FW_IMAGE_ADDR);
1207 size = (adapter->ahw->fw_info.fw->size & ~0xF);
1208 p_cache = (u32 *)adapter->ahw->fw_info.fw->data;
1211 ret = qlcnic_83xx_ms_mem_write128(adapter, addr,
1212 (u32 *)p_cache, size / 16);
1214 dev_err(&adapter->pdev->dev, "MS memory write failed\n");
1215 release_firmware(adapter->ahw->fw_info.fw);
1216 adapter->ahw->fw_info.fw = NULL;
1220 /* alignment check */
1221 if (adapter->ahw->fw_info.fw->size & 0xF) {
1223 for (i = 0; i < (adapter->ahw->fw_info.fw->size & 0xF); i++)
1224 data[i] = adapter->ahw->fw_info.fw->data[size + i];
1227 ret = qlcnic_83xx_ms_mem_write128(adapter, addr,
1230 dev_err(&adapter->pdev->dev,
1231 "MS memory write failed\n");
1232 release_firmware(adapter->ahw->fw_info.fw);
1233 adapter->ahw->fw_info.fw = NULL;
1237 release_firmware(adapter->ahw->fw_info.fw);
1238 adapter->ahw->fw_info.fw = NULL;
1243 static void qlcnic_83xx_dump_pause_control_regs(struct qlcnic_adapter *adapter)
1246 u32 val = 0, val1 = 0, reg = 0;
1248 val = QLCRD32(adapter, QLC_83XX_SRE_SHIM_REG);
1249 dev_info(&adapter->pdev->dev, "SRE-Shim Ctrl:0x%x\n", val);
1251 for (j = 0; j < 2; j++) {
1253 dev_info(&adapter->pdev->dev,
1254 "Port 0 RxB Pause Threshold Regs[TC7..TC0]:");
1255 reg = QLC_83XX_PORT0_THRESHOLD;
1256 } else if (j == 1) {
1257 dev_info(&adapter->pdev->dev,
1258 "Port 1 RxB Pause Threshold Regs[TC7..TC0]:");
1259 reg = QLC_83XX_PORT1_THRESHOLD;
1261 for (i = 0; i < 8; i++) {
1262 val = QLCRD32(adapter, reg + (i * 0x4));
1263 dev_info(&adapter->pdev->dev, "0x%x ", val);
1265 dev_info(&adapter->pdev->dev, "\n");
1268 for (j = 0; j < 2; j++) {
1270 dev_info(&adapter->pdev->dev,
1271 "Port 0 RxB TC Max Cell Registers[4..1]:");
1272 reg = QLC_83XX_PORT0_TC_MC_REG;
1273 } else if (j == 1) {
1274 dev_info(&adapter->pdev->dev,
1275 "Port 1 RxB TC Max Cell Registers[4..1]:");
1276 reg = QLC_83XX_PORT1_TC_MC_REG;
1278 for (i = 0; i < 4; i++) {
1279 val = QLCRD32(adapter, reg + (i * 0x4));
1280 dev_info(&adapter->pdev->dev, "0x%x ", val);
1282 dev_info(&adapter->pdev->dev, "\n");
1285 for (j = 0; j < 2; j++) {
1287 dev_info(&adapter->pdev->dev,
1288 "Port 0 RxB Rx TC Stats[TC7..TC0]:");
1289 reg = QLC_83XX_PORT0_TC_STATS;
1290 } else if (j == 1) {
1291 dev_info(&adapter->pdev->dev,
1292 "Port 1 RxB Rx TC Stats[TC7..TC0]:");
1293 reg = QLC_83XX_PORT1_TC_STATS;
1295 for (i = 7; i >= 0; i--) {
1296 val = QLCRD32(adapter, reg);
1297 val &= ~(0x7 << 29); /* Reset bits 29 to 31 */
1298 QLCWR32(adapter, reg, (val | (i << 29)));
1299 val = QLCRD32(adapter, reg);
1300 dev_info(&adapter->pdev->dev, "0x%x ", val);
1302 dev_info(&adapter->pdev->dev, "\n");
1305 val = QLCRD32(adapter, QLC_83XX_PORT2_IFB_THRESHOLD);
1306 val1 = QLCRD32(adapter, QLC_83XX_PORT3_IFB_THRESHOLD);
1307 dev_info(&adapter->pdev->dev,
1308 "IFB-Pause Thresholds: Port 2:0x%x, Port 3:0x%x\n",
1313 static void qlcnic_83xx_disable_pause_frames(struct qlcnic_adapter *adapter)
1317 if (qlcnic_83xx_lock_driver(adapter)) {
1318 dev_err(&adapter->pdev->dev,
1319 "%s:failed to acquire driver lock\n", __func__);
1323 qlcnic_83xx_dump_pause_control_regs(adapter);
1324 QLCWR32(adapter, QLC_83XX_SRE_SHIM_REG, 0x0);
1326 for (j = 0; j < 2; j++) {
1328 reg = QLC_83XX_PORT0_THRESHOLD;
1330 reg = QLC_83XX_PORT1_THRESHOLD;
1332 for (i = 0; i < 8; i++)
1333 QLCWR32(adapter, reg + (i * 0x4), 0x0);
1336 for (j = 0; j < 2; j++) {
1338 reg = QLC_83XX_PORT0_TC_MC_REG;
1340 reg = QLC_83XX_PORT1_TC_MC_REG;
1342 for (i = 0; i < 4; i++)
1343 QLCWR32(adapter, reg + (i * 0x4), 0x03FF03FF);
1346 QLCWR32(adapter, QLC_83XX_PORT2_IFB_THRESHOLD, 0);
1347 QLCWR32(adapter, QLC_83XX_PORT3_IFB_THRESHOLD, 0);
1348 dev_info(&adapter->pdev->dev,
1349 "Disabled pause frames successfully on all ports\n");
1350 qlcnic_83xx_unlock_driver(adapter);
1353 static int qlcnic_83xx_check_heartbeat(struct qlcnic_adapter *p_dev)
1355 u32 heartbeat, peg_status;
1356 int retries, ret = -EIO;
1358 retries = QLCNIC_HEARTBEAT_CHECK_RETRY_COUNT;
1359 p_dev->heartbeat = QLC_SHARED_REG_RD32(p_dev,
1360 QLCNIC_PEG_ALIVE_COUNTER);
1363 msleep(QLCNIC_HEARTBEAT_PERIOD_MSECS);
1364 heartbeat = QLC_SHARED_REG_RD32(p_dev,
1365 QLCNIC_PEG_ALIVE_COUNTER);
1366 if (heartbeat != p_dev->heartbeat) {
1367 ret = QLCNIC_RCODE_SUCCESS;
1370 } while (--retries);
1373 dev_err(&p_dev->pdev->dev, "firmware hang detected\n");
1374 qlcnic_83xx_disable_pause_frames(p_dev);
1375 peg_status = QLC_SHARED_REG_RD32(p_dev,
1376 QLCNIC_PEG_HALT_STATUS1);
1377 dev_info(&p_dev->pdev->dev, "Dumping HW/FW registers\n"
1378 "PEG_HALT_STATUS1: 0x%x, PEG_HALT_STATUS2: 0x%x,\n"
1379 "PEG_NET_0_PC: 0x%x, PEG_NET_1_PC: 0x%x,\n"
1380 "PEG_NET_2_PC: 0x%x, PEG_NET_3_PC: 0x%x,\n"
1381 "PEG_NET_4_PC: 0x%x\n", peg_status,
1382 QLC_SHARED_REG_RD32(p_dev, QLCNIC_PEG_HALT_STATUS2),
1383 QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_0),
1384 QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_1),
1385 QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_2),
1386 QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_3),
1387 QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_4));
1389 if (QLCNIC_FWERROR_CODE(peg_status) == 0x67)
1390 dev_err(&p_dev->pdev->dev,
1391 "Device is being reset err code 0x00006700.\n");
1397 static int qlcnic_83xx_check_cmd_peg_status(struct qlcnic_adapter *p_dev)
1399 int retries = QLCNIC_CMDPEG_CHECK_RETRY_COUNT;
1403 val = QLC_SHARED_REG_RD32(p_dev, QLCNIC_CMDPEG_STATE);
1404 if (val == QLC_83XX_CMDPEG_COMPLETE)
1406 msleep(QLCNIC_CMDPEG_CHECK_DELAY);
1407 } while (--retries);
1409 dev_err(&p_dev->pdev->dev, "%s: failed, state = 0x%x\n", __func__, val);
1413 int qlcnic_83xx_check_hw_status(struct qlcnic_adapter *p_dev)
1417 err = qlcnic_83xx_check_cmd_peg_status(p_dev);
1421 err = qlcnic_83xx_check_heartbeat(p_dev);
1428 static int qlcnic_83xx_poll_reg(struct qlcnic_adapter *p_dev, u32 addr,
1429 int duration, u32 mask, u32 status)
1435 value = qlcnic_83xx_rd_reg_indirect(p_dev, addr);
1436 retries = duration / 10;
1439 if ((value & mask) != status) {
1441 msleep(duration / 10);
1442 value = qlcnic_83xx_rd_reg_indirect(p_dev, addr);
1447 } while (retries--);
1449 if (timeout_error) {
1450 p_dev->ahw->reset.seq_error++;
1451 dev_err(&p_dev->pdev->dev,
1452 "%s: Timeout Err, entry_num = %d\n",
1453 __func__, p_dev->ahw->reset.seq_index);
1454 dev_err(&p_dev->pdev->dev,
1455 "0x%08x 0x%08x 0x%08x\n",
1456 value, mask, status);
1459 return timeout_error;
1462 static int qlcnic_83xx_reset_template_checksum(struct qlcnic_adapter *p_dev)
1465 u16 *buff = (u16 *)p_dev->ahw->reset.buff;
1466 int count = p_dev->ahw->reset.hdr->size / sizeof(u16);
1472 sum = (sum & 0xFFFF) + (sum >> 16);
1477 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__);
1482 int qlcnic_83xx_get_reset_instruction_template(struct qlcnic_adapter *p_dev)
1486 struct qlcnic_hardware_context *ahw = p_dev->ahw;
1488 ahw->reset.seq_error = 0;
1489 ahw->reset.buff = kzalloc(QLC_83XX_RESTART_TEMPLATE_SIZE, GFP_KERNEL);
1490 if (p_dev->ahw->reset.buff == NULL)
1493 p_buff = p_dev->ahw->reset.buff;
1494 addr = QLC_83XX_RESET_TEMPLATE_ADDR;
1495 count = sizeof(struct qlc_83xx_reset_hdr) / sizeof(u32);
1497 /* Copy template header from flash */
1498 if (qlcnic_83xx_flash_read32(p_dev, addr, p_buff, count)) {
1499 dev_err(&p_dev->pdev->dev, "%s: flash read failed\n", __func__);
1502 ahw->reset.hdr = (struct qlc_83xx_reset_hdr *)ahw->reset.buff;
1503 addr = QLC_83XX_RESET_TEMPLATE_ADDR + ahw->reset.hdr->hdr_size;
1504 p_buff = ahw->reset.buff + ahw->reset.hdr->hdr_size;
1505 count = (ahw->reset.hdr->size - ahw->reset.hdr->hdr_size) / sizeof(u32);
1507 /* Copy rest of the template */
1508 if (qlcnic_83xx_flash_read32(p_dev, addr, p_buff, count)) {
1509 dev_err(&p_dev->pdev->dev, "%s: flash read failed\n", __func__);
1513 if (qlcnic_83xx_reset_template_checksum(p_dev))
1515 /* Get Stop, Start and Init command offsets */
1516 ahw->reset.init_offset = ahw->reset.buff + ahw->reset.hdr->init_offset;
1517 ahw->reset.start_offset = ahw->reset.buff +
1518 ahw->reset.hdr->start_offset;
1519 ahw->reset.stop_offset = ahw->reset.buff + ahw->reset.hdr->hdr_size;
1523 /* Read Write HW register command */
1524 static void qlcnic_83xx_read_write_crb_reg(struct qlcnic_adapter *p_dev,
1525 u32 raddr, u32 waddr)
1529 value = qlcnic_83xx_rd_reg_indirect(p_dev, raddr);
1530 qlcnic_83xx_wrt_reg_indirect(p_dev, waddr, value);
1533 /* Read Modify Write HW register command */
1534 static void qlcnic_83xx_rmw_crb_reg(struct qlcnic_adapter *p_dev,
1535 u32 raddr, u32 waddr,
1536 struct qlc_83xx_rmw *p_rmw_hdr)
1540 if (p_rmw_hdr->index_a)
1541 value = p_dev->ahw->reset.array[p_rmw_hdr->index_a];
1543 value = qlcnic_83xx_rd_reg_indirect(p_dev, raddr);
1545 value &= p_rmw_hdr->mask;
1546 value <<= p_rmw_hdr->shl;
1547 value >>= p_rmw_hdr->shr;
1548 value |= p_rmw_hdr->or_value;
1549 value ^= p_rmw_hdr->xor_value;
1550 qlcnic_83xx_wrt_reg_indirect(p_dev, waddr, value);
1553 /* Write HW register command */
1554 static void qlcnic_83xx_write_list(struct qlcnic_adapter *p_dev,
1555 struct qlc_83xx_entry_hdr *p_hdr)
1558 struct qlc_83xx_entry *entry;
1560 entry = (struct qlc_83xx_entry *)((char *)p_hdr +
1561 sizeof(struct qlc_83xx_entry_hdr));
1563 for (i = 0; i < p_hdr->count; i++, entry++) {
1564 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->arg1,
1567 udelay((u32)(p_hdr->delay));
1571 /* Read and Write instruction */
1572 static void qlcnic_83xx_read_write_list(struct qlcnic_adapter *p_dev,
1573 struct qlc_83xx_entry_hdr *p_hdr)
1576 struct qlc_83xx_entry *entry;
1578 entry = (struct qlc_83xx_entry *)((char *)p_hdr +
1579 sizeof(struct qlc_83xx_entry_hdr));
1581 for (i = 0; i < p_hdr->count; i++, entry++) {
1582 qlcnic_83xx_read_write_crb_reg(p_dev, entry->arg1,
1585 udelay((u32)(p_hdr->delay));
1589 /* Poll HW register command */
1590 static void qlcnic_83xx_poll_list(struct qlcnic_adapter *p_dev,
1591 struct qlc_83xx_entry_hdr *p_hdr)
1594 struct qlc_83xx_entry *entry;
1595 struct qlc_83xx_poll *poll;
1597 unsigned long arg1, arg2;
1599 poll = (struct qlc_83xx_poll *)((char *)p_hdr +
1600 sizeof(struct qlc_83xx_entry_hdr));
1602 entry = (struct qlc_83xx_entry *)((char *)poll +
1603 sizeof(struct qlc_83xx_poll));
1604 delay = (long)p_hdr->delay;
1607 for (i = 0; i < p_hdr->count; i++, entry++)
1608 qlcnic_83xx_poll_reg(p_dev, entry->arg1,
1612 for (i = 0; i < p_hdr->count; i++, entry++) {
1616 if (qlcnic_83xx_poll_reg(p_dev,
1620 qlcnic_83xx_rd_reg_indirect(p_dev,
1622 qlcnic_83xx_rd_reg_indirect(p_dev,
1630 /* Poll and write HW register command */
1631 static void qlcnic_83xx_poll_write_list(struct qlcnic_adapter *p_dev,
1632 struct qlc_83xx_entry_hdr *p_hdr)
1636 struct qlc_83xx_quad_entry *entry;
1637 struct qlc_83xx_poll *poll;
1639 poll = (struct qlc_83xx_poll *)((char *)p_hdr +
1640 sizeof(struct qlc_83xx_entry_hdr));
1641 entry = (struct qlc_83xx_quad_entry *)((char *)poll +
1642 sizeof(struct qlc_83xx_poll));
1643 delay = (long)p_hdr->delay;
1645 for (i = 0; i < p_hdr->count; i++, entry++) {
1646 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->dr_addr,
1648 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->ar_addr,
1651 qlcnic_83xx_poll_reg(p_dev, entry->ar_addr, delay,
1652 poll->mask, poll->status);
1656 /* Read Modify Write register command */
1657 static void qlcnic_83xx_read_modify_write(struct qlcnic_adapter *p_dev,
1658 struct qlc_83xx_entry_hdr *p_hdr)
1661 struct qlc_83xx_entry *entry;
1662 struct qlc_83xx_rmw *rmw_hdr;
1664 rmw_hdr = (struct qlc_83xx_rmw *)((char *)p_hdr +
1665 sizeof(struct qlc_83xx_entry_hdr));
1667 entry = (struct qlc_83xx_entry *)((char *)rmw_hdr +
1668 sizeof(struct qlc_83xx_rmw));
1670 for (i = 0; i < p_hdr->count; i++, entry++) {
1671 qlcnic_83xx_rmw_crb_reg(p_dev, entry->arg1,
1672 entry->arg2, rmw_hdr);
1674 udelay((u32)(p_hdr->delay));
1678 static void qlcnic_83xx_pause(struct qlc_83xx_entry_hdr *p_hdr)
1681 mdelay((u32)((long)p_hdr->delay));
1684 /* Read and poll register command */
1685 static void qlcnic_83xx_poll_read_list(struct qlcnic_adapter *p_dev,
1686 struct qlc_83xx_entry_hdr *p_hdr)
1690 struct qlc_83xx_quad_entry *entry;
1691 struct qlc_83xx_poll *poll;
1694 poll = (struct qlc_83xx_poll *)((char *)p_hdr +
1695 sizeof(struct qlc_83xx_entry_hdr));
1697 entry = (struct qlc_83xx_quad_entry *)((char *)poll +
1698 sizeof(struct qlc_83xx_poll));
1699 delay = (long)p_hdr->delay;
1701 for (i = 0; i < p_hdr->count; i++, entry++) {
1702 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->ar_addr,
1705 if (!qlcnic_83xx_poll_reg(p_dev, entry->ar_addr, delay,
1706 poll->mask, poll->status)){
1707 index = p_dev->ahw->reset.array_index;
1708 addr = entry->dr_addr;
1709 j = qlcnic_83xx_rd_reg_indirect(p_dev, addr);
1710 p_dev->ahw->reset.array[index++] = j;
1712 if (index == QLC_83XX_MAX_RESET_SEQ_ENTRIES)
1713 p_dev->ahw->reset.array_index = 1;
1719 static inline void qlcnic_83xx_seq_end(struct qlcnic_adapter *p_dev)
1721 p_dev->ahw->reset.seq_end = 1;
1724 static void qlcnic_83xx_template_end(struct qlcnic_adapter *p_dev)
1726 p_dev->ahw->reset.template_end = 1;
1727 if (p_dev->ahw->reset.seq_error == 0)
1728 dev_err(&p_dev->pdev->dev,
1729 "HW restart process completed successfully.\n");
1731 dev_err(&p_dev->pdev->dev,
1732 "HW restart completed with timeout errors.\n");
1736 * qlcnic_83xx_exec_template_cmd
1738 * @p_dev: adapter structure
1739 * @p_buff: Poiter to instruction template
1741 * Template provides instructions to stop, restart and initalize firmware.
1742 * These instructions are abstracted as a series of read, write and
1743 * poll operations on hardware registers. Register information and operation
1744 * specifics are not exposed to the driver. Driver reads the template from
1745 * flash and executes the instructions located at pre-defined offsets.
1749 static void qlcnic_83xx_exec_template_cmd(struct qlcnic_adapter *p_dev,
1753 struct qlc_83xx_entry_hdr *p_hdr;
1754 char *entry = p_buff;
1756 p_dev->ahw->reset.seq_end = 0;
1757 p_dev->ahw->reset.template_end = 0;
1758 entries = p_dev->ahw->reset.hdr->entries;
1759 index = p_dev->ahw->reset.seq_index;
1761 for (; (!p_dev->ahw->reset.seq_end) && (index < entries); index++) {
1762 p_hdr = (struct qlc_83xx_entry_hdr *)entry;
1764 switch (p_hdr->cmd) {
1765 case QLC_83XX_OPCODE_NOP:
1767 case QLC_83XX_OPCODE_WRITE_LIST:
1768 qlcnic_83xx_write_list(p_dev, p_hdr);
1770 case QLC_83XX_OPCODE_READ_WRITE_LIST:
1771 qlcnic_83xx_read_write_list(p_dev, p_hdr);
1773 case QLC_83XX_OPCODE_POLL_LIST:
1774 qlcnic_83xx_poll_list(p_dev, p_hdr);
1776 case QLC_83XX_OPCODE_POLL_WRITE_LIST:
1777 qlcnic_83xx_poll_write_list(p_dev, p_hdr);
1779 case QLC_83XX_OPCODE_READ_MODIFY_WRITE:
1780 qlcnic_83xx_read_modify_write(p_dev, p_hdr);
1782 case QLC_83XX_OPCODE_SEQ_PAUSE:
1783 qlcnic_83xx_pause(p_hdr);
1785 case QLC_83XX_OPCODE_SEQ_END:
1786 qlcnic_83xx_seq_end(p_dev);
1788 case QLC_83XX_OPCODE_TMPL_END:
1789 qlcnic_83xx_template_end(p_dev);
1791 case QLC_83XX_OPCODE_POLL_READ_LIST:
1792 qlcnic_83xx_poll_read_list(p_dev, p_hdr);
1795 dev_err(&p_dev->pdev->dev,
1796 "%s: Unknown opcode 0x%04x in template %d\n",
1797 __func__, p_hdr->cmd, index);
1800 entry += p_hdr->size;
1802 p_dev->ahw->reset.seq_index = index;
1805 static void qlcnic_83xx_stop_hw(struct qlcnic_adapter *p_dev)
1807 p_dev->ahw->reset.seq_index = 0;
1809 qlcnic_83xx_exec_template_cmd(p_dev, p_dev->ahw->reset.stop_offset);
1810 if (p_dev->ahw->reset.seq_end != 1)
1811 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__);
1814 static void qlcnic_83xx_start_hw(struct qlcnic_adapter *p_dev)
1816 qlcnic_83xx_exec_template_cmd(p_dev, p_dev->ahw->reset.start_offset);
1817 if (p_dev->ahw->reset.template_end != 1)
1818 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__);
1821 static void qlcnic_83xx_init_hw(struct qlcnic_adapter *p_dev)
1823 qlcnic_83xx_exec_template_cmd(p_dev, p_dev->ahw->reset.init_offset);
1824 if (p_dev->ahw->reset.seq_end != 1)
1825 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__);
1828 static int qlcnic_83xx_load_fw_image_from_host(struct qlcnic_adapter *adapter)
1832 if (request_firmware(&adapter->ahw->fw_info.fw,
1833 QLC_83XX_FW_FILE_NAME, &(adapter->pdev->dev))) {
1834 dev_err(&adapter->pdev->dev,
1835 "No file FW image, loading flash FW image.\n");
1836 QLC_SHARED_REG_WR32(adapter, QLCNIC_FW_IMG_VALID,
1837 QLC_83XX_BOOT_FROM_FLASH);
1839 if (qlcnic_83xx_copy_fw_file(adapter))
1841 QLC_SHARED_REG_WR32(adapter, QLCNIC_FW_IMG_VALID,
1842 QLC_83XX_BOOT_FROM_FILE);
1848 static int qlcnic_83xx_restart_hw(struct qlcnic_adapter *adapter)
1853 qlcnic_83xx_stop_hw(adapter);
1855 /* Collect FW register dump if required */
1856 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1857 if (!(val & QLC_83XX_IDC_GRACEFULL_RESET))
1858 qlcnic_dump_fw(adapter);
1859 qlcnic_83xx_init_hw(adapter);
1861 if (qlcnic_83xx_copy_bootloader(adapter))
1863 /* Boot either flash image or firmware image from host file system */
1864 if (qlcnic_load_fw_file) {
1865 if (qlcnic_83xx_load_fw_image_from_host(adapter))
1868 QLC_SHARED_REG_WR32(adapter, QLCNIC_FW_IMG_VALID,
1869 QLC_83XX_BOOT_FROM_FLASH);
1872 qlcnic_83xx_start_hw(adapter);
1873 if (qlcnic_83xx_check_hw_status(adapter))
1880 * qlcnic_83xx_config_default_opmode
1882 * @adapter: adapter structure
1884 * Configure default driver operating mode
1886 * Returns: Error code or Success(0)
1888 int qlcnic_83xx_config_default_opmode(struct qlcnic_adapter *adapter)
1891 struct qlcnic_hardware_context *ahw = adapter->ahw;
1893 qlcnic_get_func_no(adapter);
1894 op_mode = QLCRDX(ahw, QLC_83XX_DRV_OP_MODE);
1896 if (op_mode == QLC_83XX_DEFAULT_OPMODE) {
1897 adapter->nic_ops->init_driver = qlcnic_83xx_init_default_driver;
1898 ahw->idc.state_entry = qlcnic_83xx_idc_ready_state_entry;
1906 int qlcnic_83xx_get_nic_configuration(struct qlcnic_adapter *adapter)
1909 struct qlcnic_info nic_info;
1910 struct qlcnic_hardware_context *ahw = adapter->ahw;
1912 memset(&nic_info, 0, sizeof(struct qlcnic_info));
1913 err = qlcnic_get_nic_info(adapter, &nic_info, ahw->pci_func);
1917 ahw->physical_port = (u8) nic_info.phys_port;
1918 ahw->switch_mode = nic_info.switch_mode;
1919 ahw->max_tx_ques = nic_info.max_tx_ques;
1920 ahw->max_rx_ques = nic_info.max_rx_ques;
1921 ahw->capabilities = nic_info.capabilities;
1922 ahw->max_mac_filters = nic_info.max_mac_filters;
1923 ahw->max_mtu = nic_info.max_mtu;
1925 if (ahw->capabilities & BIT_23)
1926 ahw->nic_mode = QLC_83XX_VIRTUAL_NIC_MODE;
1928 ahw->nic_mode = QLC_83XX_DEFAULT_MODE;
1930 return ahw->nic_mode;
1933 static int qlcnic_83xx_configure_opmode(struct qlcnic_adapter *adapter)
1937 ret = qlcnic_83xx_get_nic_configuration(adapter);
1941 if (ret == QLC_83XX_VIRTUAL_NIC_MODE) {
1942 if (qlcnic_83xx_config_vnic_opmode(adapter))
1944 } else if (ret == QLC_83XX_DEFAULT_MODE) {
1945 if (qlcnic_83xx_config_default_opmode(adapter))
1952 static void qlcnic_83xx_config_buff_descriptors(struct qlcnic_adapter *adapter)
1954 struct qlcnic_hardware_context *ahw = adapter->ahw;
1956 if (ahw->port_type == QLCNIC_XGBE) {
1957 adapter->num_rxd = DEFAULT_RCV_DESCRIPTORS_10G;
1958 adapter->max_rxd = MAX_RCV_DESCRIPTORS_10G;
1959 adapter->num_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_10G;
1960 adapter->max_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_10G;
1962 } else if (ahw->port_type == QLCNIC_GBE) {
1963 adapter->num_rxd = DEFAULT_RCV_DESCRIPTORS_1G;
1964 adapter->num_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_1G;
1965 adapter->max_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_1G;
1966 adapter->max_rxd = MAX_RCV_DESCRIPTORS_1G;
1968 adapter->num_txd = MAX_CMD_DESCRIPTORS;
1969 adapter->max_rds_rings = MAX_RDS_RINGS;
1972 static int qlcnic_83xx_init_default_driver(struct qlcnic_adapter *adapter)
1976 qlcnic_83xx_get_minidump_template(adapter);
1977 if (qlcnic_83xx_get_port_info(adapter))
1980 qlcnic_83xx_config_buff_descriptors(adapter);
1981 adapter->ahw->msix_supported = !!qlcnic_use_msi_x;
1982 adapter->flags |= QLCNIC_ADAPTER_INITIALIZED;
1984 dev_info(&adapter->pdev->dev, "HAL Version: %d\n",
1985 adapter->ahw->fw_hal_version);
1990 #define IS_QLC_83XX_USED(a, b, c) (((1 << a->portnum) & b) || ((c >> 6) & 0x1))
1991 static void qlcnic_83xx_clear_function_resources(struct qlcnic_adapter *adapter)
1993 struct qlcnic_cmd_args cmd;
1994 u32 presence_mask, audit_mask;
1997 presence_mask = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
1998 audit_mask = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_AUDIT);
2000 if (IS_QLC_83XX_USED(adapter, presence_mask, audit_mask)) {
2001 qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_STOP_NIC_FUNC);
2002 cmd.req.arg[1] = BIT_31;
2003 status = qlcnic_issue_cmd(adapter, &cmd);
2005 dev_err(&adapter->pdev->dev,
2006 "Failed to clean up the function resources\n");
2007 qlcnic_free_mbx_args(&cmd);
2011 int qlcnic_83xx_init(struct qlcnic_adapter *adapter)
2013 struct qlcnic_hardware_context *ahw = adapter->ahw;
2015 if (qlcnic_83xx_check_hw_status(adapter))
2018 /* Initilaize 83xx mailbox spinlock */
2019 spin_lock_init(&ahw->mbx_lock);
2021 set_bit(QLC_83XX_MBX_READY, &adapter->ahw->idc.status);
2022 qlcnic_83xx_clear_function_resources(adapter);
2024 /* register for NIC IDC AEN Events */
2025 qlcnic_83xx_register_nic_idc_func(adapter, 1);
2027 if (!qlcnic_83xx_read_flash_descriptor_table(adapter))
2028 qlcnic_83xx_read_flash_mfg_id(adapter);
2030 if (qlcnic_83xx_idc_init(adapter))
2033 /* Configure default, SR-IOV or Virtual NIC mode of operation */
2034 if (qlcnic_83xx_configure_opmode(adapter))
2037 /* Perform operating mode specific initialization */
2038 if (adapter->nic_ops->init_driver(adapter))
2041 INIT_DELAYED_WORK(&adapter->idc_aen_work, qlcnic_83xx_idc_aen_work);
2043 /* Periodically monitor device status */
2044 qlcnic_83xx_idc_poll_dev_state(&adapter->fw_work.work);
2046 return adapter->ahw->idc.err_code;