drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c

   1 /*
   2  * QLogic qlcnic NIC Driver
   3  * Copyright (c) 2009-2013 QLogic Corporation
   4  *
   5  * See LICENSE.qlcnic for copyright and licensing details.
   6  */
   7
   8 #include "qlcnic.h"
   9 #include "qlcnic_hw.h"
  10
  11 /* Reset template definitions */
  12 #define QLC_83XX_RESTART_TEMPLATE_SIZE          0x2000
  13 #define QLC_83XX_RESET_TEMPLATE_ADDR            0x4F0000
  14 #define QLC_83XX_RESET_SEQ_VERSION              0x0101
  15
  16 #define QLC_83XX_OPCODE_NOP                     0x0000
  17 #define QLC_83XX_OPCODE_WRITE_LIST              0x0001
  18 #define QLC_83XX_OPCODE_READ_WRITE_LIST         0x0002
  19 #define QLC_83XX_OPCODE_POLL_LIST               0x0004
  20 #define QLC_83XX_OPCODE_POLL_WRITE_LIST         0x0008
  21 #define QLC_83XX_OPCODE_READ_MODIFY_WRITE       0x0010
  22 #define QLC_83XX_OPCODE_SEQ_PAUSE               0x0020
  23 #define QLC_83XX_OPCODE_SEQ_END                 0x0040
  24 #define QLC_83XX_OPCODE_TMPL_END                0x0080
  25 #define QLC_83XX_OPCODE_POLL_READ_LIST          0x0100
  26
  27 static int qlcnic_83xx_init_default_driver(struct qlcnic_adapter *adapter);
  28 static int qlcnic_83xx_configure_opmode(struct qlcnic_adapter *adapter);
  29 static int qlcnic_83xx_check_heartbeat(struct qlcnic_adapter *p_dev);
  30 static int qlcnic_83xx_restart_hw(struct qlcnic_adapter *adapter);
  31
  32 /* Template header */
  33 struct qlc_83xx_reset_hdr {
  34 #if defined(__LITTLE_ENDIAN)
  35         u16     version;
  36         u16     signature;
  37         u16     size;
  38         u16     entries;
  39         u16     hdr_size;
  40         u16     checksum;
  41         u16     init_offset;
  42         u16     start_offset;
  43 #elif defined(__BIG_ENDIAN)
  44         u16     signature;
  45         u16     version;
  46         u16     entries;
  47         u16     size;
  48         u16     checksum;
  49         u16     hdr_size;
  50         u16     start_offset;
  51         u16     init_offset;
  52 #endif
  53 } __packed;
  54
  55 /* Command entry header. */
  56 struct qlc_83xx_entry_hdr {
  57 #if defined(__LITTLE_ENDIAN)
  58         u16     cmd;
  59         u16     size;
  60         u16     count;
  61         u16     delay;
  62 #elif defined(__BIG_ENDIAN)
  63         u16     size;
  64         u16     cmd;
  65         u16     delay;
  66         u16     count;
  67 #endif
  68 } __packed;
  69
  70 /* Generic poll command */
  71 struct qlc_83xx_poll {
  72         u32     mask;
  73         u32     status;
  74 } __packed;
  75
  76 /* Read modify write command */
  77 struct qlc_83xx_rmw {
  78         u32     mask;
  79         u32     xor_value;
  80         u32     or_value;
  81 #if defined(__LITTLE_ENDIAN)
  82         u8      shl;
  83         u8      shr;
  84         u8      index_a;
  85         u8      rsvd;
  86 #elif defined(__BIG_ENDIAN)
  87         u8      rsvd;
  88         u8      index_a;
  89         u8      shr;
  90         u8      shl;
  91 #endif
  92 } __packed;
  93
  94 /* Generic command with 2 DWORD */
  95 struct qlc_83xx_entry {
  96         u32 arg1;
  97         u32 arg2;
  98 } __packed;
  99
 100 /* Generic command with 4 DWORD */
 101 struct qlc_83xx_quad_entry {
 102         u32 dr_addr;
 103         u32 dr_value;
 104         u32 ar_addr;
 105         u32 ar_value;
 106 } __packed;
 107 static const char *const qlc_83xx_idc_states[] = {
 108         "Unknown",
 109         "Cold",
 110         "Init",
 111         "Ready",
 112         "Need Reset",
 113         "Need Quiesce",
 114         "Failed",
 115         "Quiesce"
 116 };
 117
 118 /* Device States */
 119 enum qlcnic_83xx_states {
 120         QLC_83XX_IDC_DEV_UNKNOWN,
 121         QLC_83XX_IDC_DEV_COLD,
 122         QLC_83XX_IDC_DEV_INIT,
 123         QLC_83XX_IDC_DEV_READY,
 124         QLC_83XX_IDC_DEV_NEED_RESET,
 125         QLC_83XX_IDC_DEV_NEED_QUISCENT,
 126         QLC_83XX_IDC_DEV_FAILED,
 127         QLC_83XX_IDC_DEV_QUISCENT
 128 };
 129
 130 static int
 131 qlcnic_83xx_idc_check_driver_presence_reg(struct qlcnic_adapter *adapter)
 132 {
 133         u32 val;
 134
 135         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
 136         if ((val & 0xFFFF))
 137                 return 1;
 138         else
 139                 return 0;
 140 }
 141
 142 static void qlcnic_83xx_idc_log_state_history(struct qlcnic_adapter *adapter)
 143 {
 144         u32 cur, prev;
 145         cur = adapter->ahw->idc.curr_state;
 146         prev = adapter->ahw->idc.prev_state;
 147
 148         dev_info(&adapter->pdev->dev,
 149                  "current state  = %s,  prev state = %s\n",
 150                  adapter->ahw->idc.name[cur],
 151                  adapter->ahw->idc.name[prev]);
 152 }
 153
 154 static int qlcnic_83xx_idc_update_audit_reg(struct qlcnic_adapter *adapter,
 155                                             u8 mode, int lock)
 156 {
 157         u32 val;
 158         int seconds;
 159
 160         if (lock) {
 161                 if (qlcnic_83xx_lock_driver(adapter))
 162                         return -EBUSY;
 163         }
 164
 165         val = adapter->portnum & 0xf;
 166         val |= mode << 7;
 167         if (mode)
 168                 seconds = jiffies / HZ - adapter->ahw->idc.sec_counter;
 169         else
 170                 seconds = jiffies / HZ;
 171
 172         val |= seconds << 8;
 173         QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_AUDIT, val);
 174         adapter->ahw->idc.sec_counter = jiffies / HZ;
 175
 176         if (lock)
 177                 qlcnic_83xx_unlock_driver(adapter);
 178
 179         return 0;
 180 }
 181
 182 static void qlcnic_83xx_idc_update_minor_version(struct qlcnic_adapter *adapter)
 183 {
 184         u32 val;
 185
 186         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_MIN_VERSION);
 187         val = val & ~(0x3 << (adapter->portnum * 2));
 188         val = val | (QLC_83XX_IDC_MINOR_VERSION << (adapter->portnum * 2));
 189         QLCWRX(adapter->ahw, QLC_83XX_IDC_MIN_VERSION, val);
 190 }
 191
 192 static int qlcnic_83xx_idc_update_major_version(struct qlcnic_adapter *adapter,
 193                                                 int lock)
 194 {
 195         u32 val;
 196
 197         if (lock) {
 198                 if (qlcnic_83xx_lock_driver(adapter))
 199                         return -EBUSY;
 200         }
 201
 202         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_MAJ_VERSION);
 203         val = val & ~0xFF;
 204         val = val | QLC_83XX_IDC_MAJOR_VERSION;
 205         QLCWRX(adapter->ahw, QLC_83XX_IDC_MAJ_VERSION, val);
 206
 207         if (lock)
 208                 qlcnic_83xx_unlock_driver(adapter);
 209
 210         return 0;
 211 }
 212
 213 static int
 214 qlcnic_83xx_idc_update_drv_presence_reg(struct qlcnic_adapter *adapter,
 215                                         int status, int lock)
 216 {
 217         u32 val;
 218
 219         if (lock) {
 220                 if (qlcnic_83xx_lock_driver(adapter))
 221                         return -EBUSY;
 222         }
 223
 224         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
 225
 226         if (status)
 227                 val = val | (1 << adapter->portnum);
 228         else
 229                 val = val & ~(1 << adapter->portnum);
 230
 231         QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE, val);
 232         qlcnic_83xx_idc_update_minor_version(adapter);
 233
 234         if (lock)
 235                 qlcnic_83xx_unlock_driver(adapter);
 236
 237         return 0;
 238 }
 239
 240 static int qlcnic_83xx_idc_check_major_version(struct qlcnic_adapter *adapter)
 241 {
 242         u32 val;
 243         u8 version;
 244
 245         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_MAJ_VERSION);
 246         version = val & 0xFF;
 247
 248         if (version != QLC_83XX_IDC_MAJOR_VERSION) {
 249                 dev_info(&adapter->pdev->dev,
 250                          "%s:mismatch. version 0x%x, expected version 0x%x\n",
 251                          __func__, version, QLC_83XX_IDC_MAJOR_VERSION);
 252                 return -EIO;
 253         }
 254
 255         return 0;
 256 }
 257
 258 static int qlcnic_83xx_idc_clear_registers(struct qlcnic_adapter *adapter,
 259                                            int lock)
 260 {
 261         u32 val;
 262
 263         if (lock) {
 264                 if (qlcnic_83xx_lock_driver(adapter))
 265                         return -EBUSY;
 266         }
 267
 268         QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_ACK, 0);
 269         /* Clear gracefull reset bit */
 270         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
 271         val &= ~QLC_83XX_IDC_GRACEFULL_RESET;
 272         QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val);
 273
 274         if (lock)
 275                 qlcnic_83xx_unlock_driver(adapter);
 276
 277         return 0;
 278 }
 279
 280 static int qlcnic_83xx_idc_update_drv_ack_reg(struct qlcnic_adapter *adapter,
 281                                               int flag, int lock)
 282 {
 283         u32 val;
 284
 285         if (lock) {
 286                 if (qlcnic_83xx_lock_driver(adapter))
 287                         return -EBUSY;
 288         }
 289
 290         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_ACK);
 291         if (flag)
 292                 val = val | (1 << adapter->portnum);
 293         else
 294                 val = val & ~(1 << adapter->portnum);
 295         QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_ACK, val);
 296
 297         if (lock)
 298                 qlcnic_83xx_unlock_driver(adapter);
 299
 300         return 0;
 301 }
 302
 303 static int qlcnic_83xx_idc_check_timeout(struct qlcnic_adapter *adapter,
 304                                          int time_limit)
 305 {
 306         u64 seconds;
 307
 308         seconds = jiffies / HZ - adapter->ahw->idc.sec_counter;
 309         if (seconds <= time_limit)
 310                 return 0;
 311         else
 312                 return -EBUSY;
 313 }
 314
 315 /**
 316  * qlcnic_83xx_idc_check_reset_ack_reg
 317  *
 318  * @adapter: adapter structure
 319  *
 320  * Check ACK wait limit and clear the functions which failed to ACK
 321  *
 322  * Return 0 if all functions have acknowledged the reset request.
 323  **/
 324 static int qlcnic_83xx_idc_check_reset_ack_reg(struct qlcnic_adapter *adapter)
 325 {
 326         int timeout;
 327         u32 ack, presence, val;
 328
 329         timeout = QLC_83XX_IDC_RESET_TIMEOUT_SECS;
 330         ack = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_ACK);
 331         presence = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
 332         dev_info(&adapter->pdev->dev,
 333                  "%s: ack = 0x%x, presence = 0x%x\n", __func__, ack, presence);
 334         if (!((ack & presence) == presence)) {
 335                 if (qlcnic_83xx_idc_check_timeout(adapter, timeout)) {
 336                         /* Clear functions which failed to ACK */
 337                         dev_info(&adapter->pdev->dev,
 338                                  "%s: ACK wait exceeds time limit\n", __func__);
 339                         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
 340                         val = val & ~(ack ^ presence);
 341                         if (qlcnic_83xx_lock_driver(adapter))
 342                                 return -EBUSY;
 343                         QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE, val);
 344                         dev_info(&adapter->pdev->dev,
 345                                  "%s: updated drv presence reg = 0x%x\n",
 346                                  __func__, val);
 347                         qlcnic_83xx_unlock_driver(adapter);
 348                         return 0;
 349
 350                 } else {
 351                         return 1;
 352                 }
 353         } else {
 354                 dev_info(&adapter->pdev->dev,
 355                          "%s: Reset ACK received from all functions\n",
 356                          __func__);
 357                 return 0;
 358         }
 359 }
 360
 361 /**
 362  * qlcnic_83xx_idc_tx_soft_reset
 363  *
 364  * @adapter: adapter structure
 365  *
 366  * Handle context deletion and recreation request from transmit routine
 367  *
 368  * Returns -EBUSY  or Success (0)
 369  *
 370  **/
 371 static int qlcnic_83xx_idc_tx_soft_reset(struct qlcnic_adapter *adapter)
 372 {
 373         struct net_device *netdev = adapter->netdev;
 374
 375         if (test_and_set_bit(__QLCNIC_RESETTING, &adapter->state))
 376                 return -EBUSY;
 377
 378         netif_device_detach(netdev);
 379         qlcnic_down(adapter, netdev);
 380         qlcnic_up(adapter, netdev);
 381         netif_device_attach(netdev);
 382         clear_bit(__QLCNIC_RESETTING, &adapter->state);
 383         dev_err(&adapter->pdev->dev, "%s:\n", __func__);
 384
 385         adapter->netdev->trans_start = jiffies;
 386
 387         return 0;
 388 }
 389
 390 /**
 391  * qlcnic_83xx_idc_detach_driver
 392  *
 393  * @adapter: adapter structure
 394  * Detach net interface, stop TX and cleanup resources before the HW reset.
 395  * Returns: None
 396  *
 397  **/
 398 static void qlcnic_83xx_idc_detach_driver(struct qlcnic_adapter *adapter)
 399 {
 400         int i;
 401         struct net_device *netdev = adapter->netdev;
 402
 403         netif_device_detach(netdev);
 404         /* Disable mailbox interrupt */
 405         QLCWRX(adapter->ahw, QLCNIC_MBX_INTR_ENBL, 0);
 406         qlcnic_down(adapter, netdev);
 407         for (i = 0; i < adapter->ahw->num_msix; i++) {
 408                 adapter->ahw->intr_tbl[i].id = i;
 409                 adapter->ahw->intr_tbl[i].enabled = 0;
 410                 adapter->ahw->intr_tbl[i].src = 0;
 411         }
 412 }
 413
 414 /**
 415  * qlcnic_83xx_idc_attach_driver
 416  *
 417  * @adapter: adapter structure
 418  *
 419  * Re-attach and re-enable net interface
 420  * Returns: None
 421  *
 422  **/
 423 static void qlcnic_83xx_idc_attach_driver(struct qlcnic_adapter *adapter)
 424 {
 425         struct net_device *netdev = adapter->netdev;
 426
 427         if (netif_running(netdev)) {
 428                 if (qlcnic_up(adapter, netdev))
 429                         goto done;
 430                 qlcnic_restore_indev_addr(netdev, NETDEV_UP);
 431         }
 432 done:
 433         netif_device_attach(netdev);
 434         if (netif_running(netdev)) {
 435                 netif_carrier_on(netdev);
 436                 netif_wake_queue(netdev);
 437         }
 438 }
 439
 440 static int qlcnic_83xx_idc_enter_failed_state(struct qlcnic_adapter *adapter,
 441                                               int lock)
 442 {
 443         if (lock) {
 444                 if (qlcnic_83xx_lock_driver(adapter))
 445                         return -EBUSY;
 446         }
 447
 448         qlcnic_83xx_idc_clear_registers(adapter, 0);
 449         QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, QLC_83XX_IDC_DEV_FAILED);
 450         if (lock)
 451                 qlcnic_83xx_unlock_driver(adapter);
 452
 453         qlcnic_83xx_idc_log_state_history(adapter);
 454         dev_info(&adapter->pdev->dev, "Device will enter failed state\n");
 455
 456         return 0;
 457 }
 458
 459 static int qlcnic_83xx_idc_enter_init_state(struct qlcnic_adapter *adapter,
 460                                             int lock)
 461 {
 462         if (lock) {
 463                 if (qlcnic_83xx_lock_driver(adapter))
 464                         return -EBUSY;
 465         }
 466
 467         QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, QLC_83XX_IDC_DEV_INIT);
 468
 469         if (lock)
 470                 qlcnic_83xx_unlock_driver(adapter);
 471
 472         return 0;
 473 }
 474
 475 static int qlcnic_83xx_idc_enter_need_quiesce(struct qlcnic_adapter *adapter,
 476                                               int lock)
 477 {
 478         if (lock) {
 479                 if (qlcnic_83xx_lock_driver(adapter))
 480                         return -EBUSY;
 481         }
 482
 483         QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE,
 484                QLC_83XX_IDC_DEV_NEED_QUISCENT);
 485
 486         if (lock)
 487                 qlcnic_83xx_unlock_driver(adapter);
 488
 489         return 0;
 490 }
 491
 492 static int
 493 qlcnic_83xx_idc_enter_need_reset_state(struct qlcnic_adapter *adapter, int lock)
 494 {
 495         if (lock) {
 496                 if (qlcnic_83xx_lock_driver(adapter))
 497                         return -EBUSY;
 498         }
 499
 500         QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE,
 501                QLC_83XX_IDC_DEV_NEED_RESET);
 502
 503         if (lock)
 504                 qlcnic_83xx_unlock_driver(adapter);
 505
 506         return 0;
 507 }
 508
 509 static int qlcnic_83xx_idc_enter_ready_state(struct qlcnic_adapter *adapter,
 510                                              int lock)
 511 {
 512         if (lock) {
 513                 if (qlcnic_83xx_lock_driver(adapter))
 514                         return -EBUSY;
 515         }
 516
 517         QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, QLC_83XX_IDC_DEV_READY);
 518         if (lock)
 519                 qlcnic_83xx_unlock_driver(adapter);
 520
 521         return 0;
 522 }
 523
 524 /**
 525  * qlcnic_83xx_idc_find_reset_owner_id
 526  *
 527  * @adapter: adapter structure
 528  *
 529  * NIC gets precedence over ISCSI and ISCSI has precedence over FCOE.
 530  * Within the same class, function with lowest PCI ID assumes ownership
 531  *
 532  * Returns: reset owner id or failure indication (-EIO)
 533  *
 534  **/
 535 static int qlcnic_83xx_idc_find_reset_owner_id(struct qlcnic_adapter *adapter)
 536 {
 537         u32 reg, reg1, reg2, i, j, owner, class;
 538
 539         reg1 = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_PARTITION_INFO_1);
 540         reg2 = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_PARTITION_INFO_2);
 541         owner = QLCNIC_TYPE_NIC;
 542         i = 0;
 543         j = 0;
 544         reg = reg1;
 545
 546         do {
 547                 class = (((reg & (0xF << j * 4)) >> j * 4) & 0x3);
 548                 if (class == owner)
 549                         break;
 550                 if (i == (QLC_83XX_IDC_MAX_FUNC_PER_PARTITION_INFO - 1)) {
 551                         reg = reg2;
 552                         j = 0;
 553                 } else {
 554                         j++;
 555                 }
 556
 557                 if (i == (QLC_83XX_IDC_MAX_CNA_FUNCTIONS - 1)) {
 558                         if (owner == QLCNIC_TYPE_NIC)
 559                                 owner = QLCNIC_TYPE_ISCSI;
 560                         else if (owner == QLCNIC_TYPE_ISCSI)
 561                                 owner = QLCNIC_TYPE_FCOE;
 562                         else if (owner == QLCNIC_TYPE_FCOE)
 563                                 return -EIO;
 564                         reg = reg1;
 565                         j = 0;
 566                         i = 0;
 567                 }
 568         } while (i++ < QLC_83XX_IDC_MAX_CNA_FUNCTIONS);
 569
 570         return i;
 571 }
 572
 573 static int qlcnic_83xx_idc_restart_hw(struct qlcnic_adapter *adapter, int lock)
 574 {
 575         int ret = 0;
 576
 577         ret = qlcnic_83xx_restart_hw(adapter);
 578
 579         if (ret) {
 580                 qlcnic_83xx_idc_enter_failed_state(adapter, lock);
 581         } else {
 582                 qlcnic_83xx_idc_clear_registers(adapter, lock);
 583                 ret = qlcnic_83xx_idc_enter_ready_state(adapter, lock);
 584         }
 585
 586         return ret;
 587 }
 588
 589 static int qlcnic_83xx_idc_check_fan_failure(struct qlcnic_adapter *adapter)
 590 {
 591         u32 status;
 592
 593         status = QLC_SHARED_REG_RD32(adapter, QLCNIC_PEG_HALT_STATUS1);
 594
 595         if (status & QLCNIC_RCODE_FATAL_ERROR) {
 596                 dev_err(&adapter->pdev->dev,
 597                         "peg halt status1=0x%x\n", status);
 598                 if (QLCNIC_FWERROR_CODE(status) == QLCNIC_FWERROR_FAN_FAILURE) {
 599                         dev_err(&adapter->pdev->dev,
 600                                 "On board active cooling fan failed. "
 601                                 "Device has been halted.\n");
 602                         dev_err(&adapter->pdev->dev,
 603                                 "Replace the adapter.\n");
 604                         return -EIO;
 605                 }
 606         }
 607
 608         return 0;
 609 }
 610
 611 static int qlcnic_83xx_idc_reattach_driver(struct qlcnic_adapter *adapter)
 612 {
 613         /* register for NIC IDC AEN Events */
 614         qlcnic_83xx_register_nic_idc_func(adapter, 1);
 615
 616         qlcnic_83xx_enable_mbx_intrpt(adapter);
 617
 618         if (qlcnic_83xx_configure_opmode(adapter)) {
 619                 qlcnic_83xx_idc_enter_failed_state(adapter, 1);
 620                 return -EIO;
 621         }
 622
 623         if (adapter->nic_ops->init_driver(adapter)) {
 624                 qlcnic_83xx_idc_enter_failed_state(adapter, 1);
 625                 return -EIO;
 626         }
 627
 628         qlcnic_83xx_idc_attach_driver(adapter);
 629
 630         return 0;
 631 }
 632
 633 static void qlcnic_83xx_idc_update_idc_params(struct qlcnic_adapter *adapter)
 634 {
 635         qlcnic_83xx_idc_update_drv_presence_reg(adapter, 1, 1);
 636         clear_bit(__QLCNIC_RESETTING, &adapter->state);
 637         set_bit(QLC_83XX_MBX_READY, &adapter->ahw->idc.status);
 638         qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1);
 639         set_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status);
 640         adapter->ahw->idc.quiesce_req = 0;
 641         adapter->ahw->idc.delay = QLC_83XX_IDC_FW_POLL_DELAY;
 642         adapter->ahw->idc.err_code = 0;
 643         adapter->ahw->idc.collect_dump = 0;
 644 }
 645
 646 /**
 647  * qlcnic_83xx_idc_ready_state_entry
 648  *
 649  * @adapter: adapter structure
 650  *
 651  * Perform ready state initialization, this routine will get invoked only
 652  * once from READY state.
 653  *
 654  * Returns: Error code or Success(0)
 655  *
 656  **/
 657 int qlcnic_83xx_idc_ready_state_entry(struct qlcnic_adapter *adapter)
 658 {
 659         struct qlcnic_hardware_context *ahw = adapter->ahw;
 660
 661         if (ahw->idc.prev_state != QLC_83XX_IDC_DEV_READY) {
 662                 qlcnic_83xx_idc_update_idc_params(adapter);
 663                 /* Re-attach the device if required */
 664                 if ((ahw->idc.prev_state == QLC_83XX_IDC_DEV_NEED_RESET) ||
 665                     (ahw->idc.prev_state == QLC_83XX_IDC_DEV_INIT)) {
 666                         if (qlcnic_83xx_idc_reattach_driver(adapter))
 667                                 return -EIO;
 668                 }
 669         }
 670
 671         return 0;
 672 }
 673
 674 /**
 675  * qlcnic_83xx_idc_vnic_pf_entry
 676  *
 677  * @adapter: adapter structure
 678  *
 679  * Ensure vNIC mode privileged function starts only after vNIC mode is
 680  * enabled by management function.
 681  * If vNIC mode is ready, start initialization.
 682  *
 683  * Returns: -EIO or 0
 684  *
 685  **/
 686 int qlcnic_83xx_idc_vnic_pf_entry(struct qlcnic_adapter *adapter)
 687 {
 688         u32 state;
 689         struct qlcnic_hardware_context *ahw = adapter->ahw;
 690
 691         /* Privileged function waits till mgmt function enables VNIC mode */
 692         state = QLCRDX(adapter->ahw, QLC_83XX_VNIC_STATE);
 693         if (state != QLCNIC_DEV_NPAR_OPER) {
 694                 if (!ahw->idc.vnic_wait_limit--) {
 695                         qlcnic_83xx_idc_enter_failed_state(adapter, 1);
 696                         return -EIO;
 697                 }
 698                 dev_info(&adapter->pdev->dev, "vNIC mode disabled\n");
 699                 return -EIO;
 700
 701         } else {
 702                 /* Perform one time initialization from ready state */
 703                 if (ahw->idc.vnic_state != QLCNIC_DEV_NPAR_OPER) {
 704                         qlcnic_83xx_idc_update_idc_params(adapter);
 705
 706                         /* If the previous state is UNKNOWN, device will be
 707                            already attached properly by Init routine*/
 708                         if (ahw->idc.prev_state != QLC_83XX_IDC_DEV_UNKNOWN) {
 709                                 if (qlcnic_83xx_idc_reattach_driver(adapter))
 710                                         return -EIO;
 711                         }
 712                         adapter->ahw->idc.vnic_state =  QLCNIC_DEV_NPAR_OPER;
 713                         dev_info(&adapter->pdev->dev, "vNIC mode enabled\n");
 714                 }
 715         }
 716
 717         return 0;
 718 }
 719
 720 static int qlcnic_83xx_idc_unknown_state(struct qlcnic_adapter *adapter)
 721 {
 722         adapter->ahw->idc.err_code = -EIO;
 723         dev_err(&adapter->pdev->dev,
 724                 "%s: Device in unknown state\n", __func__);
 725         return 0;
 726 }
 727
 728 /**
 729  * qlcnic_83xx_idc_cold_state
 730  *
 731  * @adapter: adapter structure
 732  *
 733  * If HW is up and running device will enter READY state.
 734  * If firmware image from host needs to be loaded, device is
 735  * forced to start with the file firmware image.
 736  *
 737  * Returns: Error code or Success(0)
 738  *
 739  **/
 740 static int qlcnic_83xx_idc_cold_state_handler(struct qlcnic_adapter *adapter)
 741 {
 742         qlcnic_83xx_idc_update_drv_presence_reg(adapter, 1, 0);
 743         qlcnic_83xx_idc_update_audit_reg(adapter, 1, 0);
 744
 745         if (qlcnic_load_fw_file) {
 746                 qlcnic_83xx_idc_restart_hw(adapter, 0);
 747         } else {
 748                 if (qlcnic_83xx_check_hw_status(adapter)) {
 749                         qlcnic_83xx_idc_enter_failed_state(adapter, 0);
 750                         return -EIO;
 751                 } else {
 752                         qlcnic_83xx_idc_enter_ready_state(adapter, 0);
 753                 }
 754         }
 755         return 0;
 756 }
 757
 758 /**
 759  * qlcnic_83xx_idc_init_state
 760  *
 761  * @adapter: adapter structure
 762  *
 763  * Reset owner will restart the device from this state.
 764  * Device will enter failed state if it remains
 765  * in this state for more than DEV_INIT time limit.
 766  *
 767  * Returns: Error code or Success(0)
 768  *
 769  **/
 770 static int qlcnic_83xx_idc_init_state(struct qlcnic_adapter *adapter)
 771 {
 772         int timeout, ret = 0;
 773         u32 owner;
 774
 775         timeout = QLC_83XX_IDC_INIT_TIMEOUT_SECS;
 776         if (adapter->ahw->idc.prev_state == QLC_83XX_IDC_DEV_NEED_RESET) {
 777                 owner = qlcnic_83xx_idc_find_reset_owner_id(adapter);
 778                 if (adapter->ahw->pci_func == owner)
 779                         ret = qlcnic_83xx_idc_restart_hw(adapter, 1);
 780         } else {
 781                 ret = qlcnic_83xx_idc_check_timeout(adapter, timeout);
 782                 return ret;
 783         }
 784
 785         return ret;
 786 }
 787
 788 /**
 789  * qlcnic_83xx_idc_ready_state
 790  *
 791  * @adapter: adapter structure
 792  *
 793  * Perform IDC protocol specicifed actions after monitoring device state and
 794  * events.
 795  *
 796  * Returns: Error code or Success(0)
 797  *
 798  **/
 799 static int qlcnic_83xx_idc_ready_state(struct qlcnic_adapter *adapter)
 800 {
 801         u32 val;
 802         struct qlcnic_hardware_context *ahw = adapter->ahw;
 803         int ret = 0;
 804
 805         /* Perform NIC configuration based ready state entry actions */
 806         if (ahw->idc.state_entry(adapter))
 807                 return -EIO;
 808
 809         if (qlcnic_check_temp(adapter)) {
 810                 if (ahw->temp == QLCNIC_TEMP_PANIC) {
 811                         qlcnic_83xx_idc_check_fan_failure(adapter);
 812                         dev_err(&adapter->pdev->dev,
 813                                 "Error: device temperature %d above limits\n",
 814                                 adapter->ahw->temp);
 815                         clear_bit(QLC_83XX_MBX_READY, &ahw->idc.status);
 816                         set_bit(__QLCNIC_RESETTING, &adapter->state);
 817                         qlcnic_83xx_idc_detach_driver(adapter);
 818                         qlcnic_83xx_idc_enter_failed_state(adapter, 1);
 819                         return -EIO;
 820                 }
 821         }
 822
 823         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
 824         ret = qlcnic_83xx_check_heartbeat(adapter);
 825         if (ret) {
 826                 adapter->flags |= QLCNIC_FW_HANG;
 827                 if (!(val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY)) {
 828                         clear_bit(QLC_83XX_MBX_READY, &ahw->idc.status);
 829                         set_bit(__QLCNIC_RESETTING, &adapter->state);
 830                         qlcnic_83xx_idc_enter_need_reset_state(adapter, 1);
 831                 }
 832                 return -EIO;
 833         }
 834
 835         if ((val & QLC_83XX_IDC_GRACEFULL_RESET) || ahw->idc.collect_dump) {
 836                 /* Move to need reset state and prepare for reset */
 837                 qlcnic_83xx_idc_enter_need_reset_state(adapter, 1);
 838                 return ret;
 839         }
 840
 841         /* Check for soft reset request */
 842         if (ahw->reset_context &&
 843             !(val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY)) {
 844                 qlcnic_83xx_idc_tx_soft_reset(adapter);
 845                 return ret;
 846         }
 847
 848         /* Move to need quiesce state if requested */
 849         if (adapter->ahw->idc.quiesce_req) {
 850                 qlcnic_83xx_idc_enter_need_quiesce(adapter, 1);
 851                 qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1);
 852                 return ret;
 853         }
 854
 855         return ret;
 856 }
 857
 858 /**
 859  * qlcnic_83xx_idc_need_reset_state
 860  *
 861  * @adapter: adapter structure
 862  *
 863  * Device will remain in this state until:
 864  *      Reset request ACK's are recieved from all the functions
 865  *      Wait time exceeds max time limit
 866  *
 867  * Returns: Error code or Success(0)
 868  *
 869  **/
 870 static int qlcnic_83xx_idc_need_reset_state(struct qlcnic_adapter *adapter)
 871 {
 872         int ret = 0;
 873
 874         if (adapter->ahw->idc.prev_state != QLC_83XX_IDC_DEV_NEED_RESET) {
 875                 qlcnic_83xx_idc_update_drv_ack_reg(adapter, 1, 1);
 876                 qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1);
 877                 set_bit(__QLCNIC_RESETTING, &adapter->state);
 878                 clear_bit(QLC_83XX_MBX_READY, &adapter->ahw->idc.status);
 879                 if (adapter->ahw->nic_mode == QLC_83XX_VIRTUAL_NIC_MODE)
 880                         qlcnic_83xx_disable_vnic_mode(adapter, 1);
 881                 qlcnic_83xx_idc_detach_driver(adapter);
 882         }
 883
 884         /* Check ACK from other functions */
 885         ret = qlcnic_83xx_idc_check_reset_ack_reg(adapter);
 886         if (ret) {
 887                 dev_info(&adapter->pdev->dev,
 888                          "%s: Waiting for reset ACK\n", __func__);
 889                 return 0;
 890         }
 891
 892         /* Transit to INIT state and restart the HW */
 893         qlcnic_83xx_idc_enter_init_state(adapter, 1);
 894
 895         return ret;
 896 }
 897
 898 static int qlcnic_83xx_idc_need_quiesce_state(struct qlcnic_adapter *adapter)
 899 {
 900         dev_err(&adapter->pdev->dev, "%s: TBD\n", __func__);
 901         return 0;
 902 }
 903
 904 static int qlcnic_83xx_idc_failed_state(struct qlcnic_adapter *adapter)
 905 {
 906         dev_err(&adapter->pdev->dev, "%s: please restart!!\n", __func__);
 907         adapter->ahw->idc.err_code = -EIO;
 908
 909         return 0;
 910 }
 911
 912 static int qlcnic_83xx_idc_quiesce_state(struct qlcnic_adapter *adapter)
 913 {
 914         dev_info(&adapter->pdev->dev, "%s: TBD\n", __func__);
 915         return 0;
 916 }
 917
 918 static int qlcnic_83xx_idc_check_state_validity(struct qlcnic_adapter *adapter,
 919                                                 u32 state)
 920 {
 921         u32 cur, prev, next;
 922
 923         cur = adapter->ahw->idc.curr_state;
 924         prev = adapter->ahw->idc.prev_state;
 925         next = state;
 926
 927         if ((next < QLC_83XX_IDC_DEV_COLD) ||
 928             (next > QLC_83XX_IDC_DEV_QUISCENT)) {
 929                 dev_err(&adapter->pdev->dev,
 930                         "%s: curr %d, prev %d, next state %d is  invalid\n",
 931                         __func__, cur, prev, state);
 932                 return 1;
 933         }
 934
 935         if ((cur == QLC_83XX_IDC_DEV_UNKNOWN) &&
 936             (prev == QLC_83XX_IDC_DEV_UNKNOWN)) {
 937                 if ((next != QLC_83XX_IDC_DEV_COLD) &&
 938                     (next != QLC_83XX_IDC_DEV_READY)) {
 939                         dev_err(&adapter->pdev->dev,
 940                                 "%s: failed, cur %d prev %d next %d\n",
 941                                 __func__, cur, prev, next);
 942                         return 1;
 943                 }
 944         }
 945
 946         if (next == QLC_83XX_IDC_DEV_INIT) {
 947                 if ((prev != QLC_83XX_IDC_DEV_INIT) &&
 948                     (prev != QLC_83XX_IDC_DEV_COLD) &&
 949                     (prev != QLC_83XX_IDC_DEV_NEED_RESET)) {
 950                         dev_err(&adapter->pdev->dev,
 951                                 "%s: failed, cur %d prev %d next %d\n",
 952                                 __func__, cur, prev, next);
 953                         return 1;
 954                 }
 955         }
 956
 957         return 0;
 958 }
 959
 960 static void qlcnic_83xx_periodic_tasks(struct qlcnic_adapter *adapter)
 961 {
 962         if (adapter->fhash.fnum)
 963                 qlcnic_prune_lb_filters(adapter);
 964 }
 965
 966 /**
 967  * qlcnic_83xx_idc_poll_dev_state
 968  *
 969  * @work: kernel work queue structure used to schedule the function
 970  *
 971  * Poll device state periodically and perform state specific
 972  * actions defined by Inter Driver Communication (IDC) protocol.
 973  *
 974  * Returns: None
 975  *
 976  **/
 977 void qlcnic_83xx_idc_poll_dev_state(struct work_struct *work)
 978 {
 979         struct qlcnic_adapter *adapter;
 980         u32 state;
 981
 982         adapter = container_of(work, struct qlcnic_adapter, fw_work.work);
 983         state = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_STATE);
 984
 985         if (qlcnic_83xx_idc_check_state_validity(adapter, state)) {
 986                 qlcnic_83xx_idc_log_state_history(adapter);
 987                 adapter->ahw->idc.curr_state = QLC_83XX_IDC_DEV_UNKNOWN;
 988         } else {
 989                 adapter->ahw->idc.curr_state = state;
 990         }
 991
 992         switch (adapter->ahw->idc.curr_state) {
 993         case QLC_83XX_IDC_DEV_READY:
 994                 qlcnic_83xx_idc_ready_state(adapter);
 995                 break;
 996         case QLC_83XX_IDC_DEV_NEED_RESET:
 997                 qlcnic_83xx_idc_need_reset_state(adapter);
 998                 break;
 999         case QLC_83XX_IDC_DEV_NEED_QUISCENT:
1000                 qlcnic_83xx_idc_need_quiesce_state(adapter);
1001                 break;
1002         case QLC_83XX_IDC_DEV_FAILED:
1003                 qlcnic_83xx_idc_failed_state(adapter);
1004                 return;
1005         case QLC_83XX_IDC_DEV_INIT:
1006                 qlcnic_83xx_idc_init_state(adapter);
1007                 break;
1008         case QLC_83XX_IDC_DEV_QUISCENT:
1009                 qlcnic_83xx_idc_quiesce_state(adapter);
1010                 break;
1011         default:
1012                 qlcnic_83xx_idc_unknown_state(adapter);
1013                 return;
1014         }
1015         adapter->ahw->idc.prev_state = adapter->ahw->idc.curr_state;
1016         qlcnic_83xx_periodic_tasks(adapter);
1017
1018         /* Re-schedule the function */
1019         if (test_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status))
1020                 qlcnic_schedule_work(adapter, qlcnic_83xx_idc_poll_dev_state,
1021                                      adapter->ahw->idc.delay);
1022 }
1023
1024 static void qlcnic_83xx_setup_idc_parameters(struct qlcnic_adapter *adapter)
1025 {
1026         u32 idc_params, val;
1027
1028         if (qlcnic_83xx_lockless_flash_read32(adapter,
1029                                               QLC_83XX_IDC_FLASH_PARAM_ADDR,
1030                                               (u8 *)&idc_params, 1)) {
1031                 dev_info(&adapter->pdev->dev,
1032                          "%s:failed to get IDC params from flash\n", __func__);
1033                 adapter->dev_init_timeo = QLC_83XX_IDC_INIT_TIMEOUT_SECS;
1034                 adapter->reset_ack_timeo = QLC_83XX_IDC_RESET_TIMEOUT_SECS;
1035         } else {
1036                 adapter->dev_init_timeo = idc_params & 0xFFFF;
1037                 adapter->reset_ack_timeo = ((idc_params >> 16) & 0xFFFF);
1038         }
1039
1040         adapter->ahw->idc.curr_state = QLC_83XX_IDC_DEV_UNKNOWN;
1041         adapter->ahw->idc.prev_state = QLC_83XX_IDC_DEV_UNKNOWN;
1042         adapter->ahw->idc.delay = QLC_83XX_IDC_FW_POLL_DELAY;
1043         adapter->ahw->idc.err_code = 0;
1044         adapter->ahw->idc.collect_dump = 0;
1045         adapter->ahw->idc.name = (char **)qlc_83xx_idc_states;
1046
1047         clear_bit(__QLCNIC_RESETTING, &adapter->state);
1048         set_bit(QLC_83XX_MBX_READY, &adapter->ahw->idc.status);
1049         set_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status);
1050
1051         /* Check if reset recovery is disabled */
1052         if (!qlcnic_auto_fw_reset) {
1053                 /* Propagate do not reset request to other functions */
1054                 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1055                 val = val | QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY;
1056                 QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val);
1057         }
1058 }
1059
1060 static int
1061 qlcnic_83xx_idc_first_to_load_function_handler(struct qlcnic_adapter *adapter)
1062 {
1063         u32 state, val;
1064
1065         if (qlcnic_83xx_lock_driver(adapter))
1066                 return -EIO;
1067
1068         /* Clear driver lock register */
1069         QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, 0);
1070         if (qlcnic_83xx_idc_update_major_version(adapter, 0)) {
1071                 qlcnic_83xx_unlock_driver(adapter);
1072                 return -EIO;
1073         }
1074
1075         state = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_STATE);
1076         if (qlcnic_83xx_idc_check_state_validity(adapter, state)) {
1077                 qlcnic_83xx_unlock_driver(adapter);
1078                 return -EIO;
1079         }
1080
1081         if (state != QLC_83XX_IDC_DEV_COLD && qlcnic_load_fw_file) {
1082                 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE,
1083                        QLC_83XX_IDC_DEV_COLD);
1084                 state = QLC_83XX_IDC_DEV_COLD;
1085         }
1086
1087         adapter->ahw->idc.curr_state = state;
1088         /* First to load function should cold boot the device */
1089         if (state == QLC_83XX_IDC_DEV_COLD)
1090                 qlcnic_83xx_idc_cold_state_handler(adapter);
1091
1092         /* Check if reset recovery is enabled */
1093         if (qlcnic_auto_fw_reset) {
1094                 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1095                 val = val & ~QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY;
1096                 QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val);
1097         }
1098
1099         qlcnic_83xx_unlock_driver(adapter);
1100
1101         return 0;
1102 }
1103
1104 static int qlcnic_83xx_idc_init(struct qlcnic_adapter *adapter)
1105 {
1106         int ret = -EIO;
1107
1108         qlcnic_83xx_setup_idc_parameters(adapter);
1109
1110         if (qlcnic_83xx_get_reset_instruction_template(adapter))
1111                 return ret;
1112
1113         if (!qlcnic_83xx_idc_check_driver_presence_reg(adapter)) {
1114                 if (qlcnic_83xx_idc_first_to_load_function_handler(adapter))
1115                         return -EIO;
1116         } else {
1117                 if (qlcnic_83xx_idc_check_major_version(adapter))
1118                         return -EIO;
1119         }
1120
1121         qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1);
1122
1123         return 0;
1124 }
1125
1126 void qlcnic_83xx_idc_exit(struct qlcnic_adapter *adapter)
1127 {
1128         int id;
1129         u32 val;
1130
1131         while (test_and_set_bit(__QLCNIC_RESETTING, &adapter->state))
1132                 usleep_range(10000, 11000);
1133
1134         id = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
1135         id = id & 0xFF;
1136
1137         if (id == adapter->portnum) {
1138                 dev_err(&adapter->pdev->dev,
1139                         "%s: wait for lock recovery.. %d\n", __func__, id);
1140                 msleep(20);
1141                 id = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
1142                 id = id & 0xFF;
1143         }
1144
1145         /* Clear driver presence bit */
1146         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
1147         val = val & ~(1 << adapter->portnum);
1148         QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE, val);
1149         clear_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status);
1150         clear_bit(__QLCNIC_RESETTING, &adapter->state);
1151
1152         cancel_delayed_work_sync(&adapter->fw_work);
1153 }
1154
1155 void qlcnic_83xx_idc_request_reset(struct qlcnic_adapter *adapter, u32 key)
1156 {
1157         u32 val;
1158
1159         if (qlcnic_83xx_lock_driver(adapter)) {
1160                 dev_err(&adapter->pdev->dev,
1161                         "%s:failed, please retry\n", __func__);
1162                 return;
1163         }
1164
1165         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1166         if ((val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY) ||
1167             !qlcnic_auto_fw_reset) {
1168                 dev_err(&adapter->pdev->dev,
1169                         "%s:failed, device in non reset mode\n", __func__);
1170                 qlcnic_83xx_unlock_driver(adapter);
1171                 return;
1172         }
1173
1174         if (key == QLCNIC_FORCE_FW_RESET) {
1175                 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1176                 val = val | QLC_83XX_IDC_GRACEFULL_RESET;
1177                 QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val);
1178         } else if (key == QLCNIC_FORCE_FW_DUMP_KEY) {
1179                 adapter->ahw->idc.collect_dump = 1;
1180         }
1181
1182         qlcnic_83xx_unlock_driver(adapter);
1183         return;
1184 }
1185
1186 static int qlcnic_83xx_copy_bootloader(struct qlcnic_adapter *adapter)
1187 {
1188         u8 *p_cache;
1189         u32 src, size;
1190         u64 dest;
1191         int ret = -EIO;
1192
1193         src = QLC_83XX_BOOTLOADER_FLASH_ADDR;
1194         dest = QLCRDX(adapter->ahw, QLCNIC_BOOTLOADER_ADDR);
1195         size = QLCRDX(adapter->ahw, QLCNIC_BOOTLOADER_SIZE);
1196
1197         /* alignment check */
1198         if (size & 0xF)
1199                 size = (size + 16) & ~0xF;
1200
1201         p_cache = kzalloc(size, GFP_KERNEL);
1202         if (p_cache == NULL)
1203                 return -ENOMEM;
1204
1205         ret = qlcnic_83xx_lockless_flash_read32(adapter, src, p_cache,
1206                                                 size / sizeof(u32));
1207         if (ret) {
1208                 kfree(p_cache);
1209                 return ret;
1210         }
1211         /* 16 byte write to MS memory */
1212         ret = qlcnic_83xx_ms_mem_write128(adapter, dest, (u32 *)p_cache,
1213                                           size / 16);
1214         if (ret) {
1215                 kfree(p_cache);
1216                 return ret;
1217         }
1218         kfree(p_cache);
1219
1220         return ret;
1221 }
1222
1223 static int qlcnic_83xx_copy_fw_file(struct qlcnic_adapter *adapter)
1224 {
1225         u32 dest, *p_cache;
1226         u64 addr;
1227         u8 data[16];
1228         size_t size;
1229         int i, ret = -EIO;
1230
1231         dest = QLCRDX(adapter->ahw, QLCNIC_FW_IMAGE_ADDR);
1232         size = (adapter->ahw->fw_info.fw->size & ~0xF);
1233         p_cache = (u32 *)adapter->ahw->fw_info.fw->data;
1234         addr = (u64)dest;
1235
1236         ret = qlcnic_83xx_ms_mem_write128(adapter, addr,
1237                                           (u32 *)p_cache, size / 16);
1238         if (ret) {
1239                 dev_err(&adapter->pdev->dev, "MS memory write failed\n");
1240                 release_firmware(adapter->ahw->fw_info.fw);
1241                 adapter->ahw->fw_info.fw = NULL;
1242                 return -EIO;
1243         }
1244
1245         /* alignment check */
1246         if (adapter->ahw->fw_info.fw->size & 0xF) {
1247                 addr = dest + size;
1248                 for (i = 0; i < (adapter->ahw->fw_info.fw->size & 0xF); i++)
1249                         data[i] = adapter->ahw->fw_info.fw->data[size + i];
1250                 for (; i < 16; i++)
1251                         data[i] = 0;
1252                 ret = qlcnic_83xx_ms_mem_write128(adapter, addr,
1253                                                   (u32 *)data, 1);
1254                 if (ret) {
1255                         dev_err(&adapter->pdev->dev,
1256                                 "MS memory write failed\n");
1257                         release_firmware(adapter->ahw->fw_info.fw);
1258                         adapter->ahw->fw_info.fw = NULL;
1259                         return -EIO;
1260                 }
1261         }
1262         release_firmware(adapter->ahw->fw_info.fw);
1263         adapter->ahw->fw_info.fw = NULL;
1264
1265         return 0;
1266 }
1267
1268 static void qlcnic_83xx_dump_pause_control_regs(struct qlcnic_adapter *adapter)
1269 {
1270         int i, j;
1271         u32 val = 0, val1 = 0, reg = 0;
1272
1273         val = QLCRD32(adapter, QLC_83XX_SRE_SHIM_REG);
1274         dev_info(&adapter->pdev->dev, "SRE-Shim Ctrl:0x%x\n", val);
1275
1276         for (j = 0; j < 2; j++) {
1277                 if (j == 0) {
1278                         dev_info(&adapter->pdev->dev,
1279                                  "Port 0 RxB Pause Threshold Regs[TC7..TC0]:");
1280                         reg = QLC_83XX_PORT0_THRESHOLD;
1281                 } else if (j == 1) {
1282                         dev_info(&adapter->pdev->dev,
1283                                  "Port 1 RxB Pause Threshold Regs[TC7..TC0]:");
1284                         reg = QLC_83XX_PORT1_THRESHOLD;
1285                 }
1286                 for (i = 0; i < 8; i++) {
1287                         val = QLCRD32(adapter, reg + (i * 0x4));
1288                         dev_info(&adapter->pdev->dev, "0x%x  ", val);
1289                 }
1290                 dev_info(&adapter->pdev->dev, "\n");
1291         }
1292
1293         for (j = 0; j < 2; j++) {
1294                 if (j == 0) {
1295                         dev_info(&adapter->pdev->dev,
1296                                  "Port 0 RxB TC Max Cell Registers[4..1]:");
1297                         reg = QLC_83XX_PORT0_TC_MC_REG;
1298                 } else if (j == 1) {
1299                         dev_info(&adapter->pdev->dev,
1300                                  "Port 1 RxB TC Max Cell Registers[4..1]:");
1301                         reg = QLC_83XX_PORT1_TC_MC_REG;
1302                 }
1303                 for (i = 0; i < 4; i++) {
1304                         val = QLCRD32(adapter, reg + (i * 0x4));
1305                          dev_info(&adapter->pdev->dev, "0x%x  ", val);
1306                 }
1307                 dev_info(&adapter->pdev->dev, "\n");
1308         }
1309
1310         for (j = 0; j < 2; j++) {
1311                 if (j == 0) {
1312                         dev_info(&adapter->pdev->dev,
1313                                  "Port 0 RxB Rx TC Stats[TC7..TC0]:");
1314                         reg = QLC_83XX_PORT0_TC_STATS;
1315                 } else if (j == 1) {
1316                         dev_info(&adapter->pdev->dev,
1317                                  "Port 1 RxB Rx TC Stats[TC7..TC0]:");
1318                         reg = QLC_83XX_PORT1_TC_STATS;
1319                 }
1320                 for (i = 7; i >= 0; i--) {
1321                         val = QLCRD32(adapter, reg);
1322                         val &= ~(0x7 << 29);    /* Reset bits 29 to 31 */
1323                         QLCWR32(adapter, reg, (val | (i << 29)));
1324                         val = QLCRD32(adapter, reg);
1325                         dev_info(&adapter->pdev->dev, "0x%x  ", val);
1326                 }
1327                 dev_info(&adapter->pdev->dev, "\n");
1328         }
1329
1330         val = QLCRD32(adapter, QLC_83XX_PORT2_IFB_THRESHOLD);
1331         val1 = QLCRD32(adapter, QLC_83XX_PORT3_IFB_THRESHOLD);
1332         dev_info(&adapter->pdev->dev,
1333                  "IFB-Pause Thresholds: Port 2:0x%x, Port 3:0x%x\n",
1334                  val, val1);
1335 }
1336
1337
1338 static void qlcnic_83xx_disable_pause_frames(struct qlcnic_adapter *adapter)
1339 {
1340         u32 reg = 0, i, j;
1341
1342         if (qlcnic_83xx_lock_driver(adapter)) {
1343                 dev_err(&adapter->pdev->dev,
1344                         "%s:failed to acquire driver lock\n", __func__);
1345                 return;
1346         }
1347
1348         qlcnic_83xx_dump_pause_control_regs(adapter);
1349         QLCWR32(adapter, QLC_83XX_SRE_SHIM_REG, 0x0);
1350
1351         for (j = 0; j < 2; j++) {
1352                 if (j == 0)
1353                         reg = QLC_83XX_PORT0_THRESHOLD;
1354                 else if (j == 1)
1355                         reg = QLC_83XX_PORT1_THRESHOLD;
1356
1357                 for (i = 0; i < 8; i++)
1358                         QLCWR32(adapter, reg + (i * 0x4), 0x0);
1359         }
1360
1361         for (j = 0; j < 2; j++) {
1362                 if (j == 0)
1363                         reg = QLC_83XX_PORT0_TC_MC_REG;
1364                 else if (j == 1)
1365                         reg = QLC_83XX_PORT1_TC_MC_REG;
1366
1367                 for (i = 0; i < 4; i++)
1368                         QLCWR32(adapter, reg + (i * 0x4), 0x03FF03FF);
1369         }
1370
1371         QLCWR32(adapter, QLC_83XX_PORT2_IFB_THRESHOLD, 0);
1372         QLCWR32(adapter, QLC_83XX_PORT3_IFB_THRESHOLD, 0);
1373         dev_info(&adapter->pdev->dev,
1374                  "Disabled pause frames successfully on all ports\n");
1375         qlcnic_83xx_unlock_driver(adapter);
1376 }
1377
1378 static int qlcnic_83xx_check_heartbeat(struct qlcnic_adapter *p_dev)
1379 {
1380         u32 heartbeat, peg_status;
1381         int retries, ret = -EIO;
1382
1383         retries = QLCNIC_HEARTBEAT_CHECK_RETRY_COUNT;
1384         p_dev->heartbeat = QLC_SHARED_REG_RD32(p_dev,
1385                                                QLCNIC_PEG_ALIVE_COUNTER);
1386
1387         do {
1388                 msleep(QLCNIC_HEARTBEAT_PERIOD_MSECS);
1389                 heartbeat = QLC_SHARED_REG_RD32(p_dev,
1390                                                 QLCNIC_PEG_ALIVE_COUNTER);
1391                 if (heartbeat != p_dev->heartbeat) {
1392                         ret = QLCNIC_RCODE_SUCCESS;
1393                         break;
1394                 }
1395         } while (--retries);
1396
1397         if (ret) {
1398                 dev_err(&p_dev->pdev->dev, "firmware hang detected\n");
1399                 qlcnic_83xx_disable_pause_frames(p_dev);
1400                 peg_status = QLC_SHARED_REG_RD32(p_dev,
1401                                                  QLCNIC_PEG_HALT_STATUS1);
1402                 dev_info(&p_dev->pdev->dev, "Dumping HW/FW registers\n"
1403                          "PEG_HALT_STATUS1: 0x%x, PEG_HALT_STATUS2: 0x%x,\n"
1404                          "PEG_NET_0_PC: 0x%x, PEG_NET_1_PC: 0x%x,\n"
1405                          "PEG_NET_2_PC: 0x%x, PEG_NET_3_PC: 0x%x,\n"
1406                          "PEG_NET_4_PC: 0x%x\n", peg_status,
1407                          QLC_SHARED_REG_RD32(p_dev, QLCNIC_PEG_HALT_STATUS2),
1408                          QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_0),
1409                          QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_1),
1410                          QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_2),
1411                          QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_3),
1412                          QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_4));
1413
1414                 if (QLCNIC_FWERROR_CODE(peg_status) == 0x67)
1415                         dev_err(&p_dev->pdev->dev,
1416                                 "Device is being reset err code 0x00006700.\n");
1417         }
1418
1419         return ret;
1420 }
1421
1422 static int qlcnic_83xx_check_cmd_peg_status(struct qlcnic_adapter *p_dev)
1423 {
1424         int retries = QLCNIC_CMDPEG_CHECK_RETRY_COUNT;
1425         u32 val;
1426
1427         do {
1428                 val = QLC_SHARED_REG_RD32(p_dev, QLCNIC_CMDPEG_STATE);
1429                 if (val == QLC_83XX_CMDPEG_COMPLETE)
1430                         return 0;
1431                 msleep(QLCNIC_CMDPEG_CHECK_DELAY);
1432         } while (--retries);
1433
1434         dev_err(&p_dev->pdev->dev, "%s: failed, state = 0x%x\n", __func__, val);
1435         return -EIO;
1436 }
1437
1438 int qlcnic_83xx_check_hw_status(struct qlcnic_adapter *p_dev)
1439 {
1440         int err;
1441
1442         err = qlcnic_83xx_check_cmd_peg_status(p_dev);
1443         if (err)
1444                 return err;
1445
1446         err = qlcnic_83xx_check_heartbeat(p_dev);
1447         if (err)
1448                 return err;
1449
1450         return err;
1451 }
1452
1453 static int qlcnic_83xx_poll_reg(struct qlcnic_adapter *p_dev, u32 addr,
1454                                 int duration, u32 mask, u32 status)
1455 {
1456         u32 value;
1457         int timeout_error;
1458         u8 retries;
1459
1460         value = qlcnic_83xx_rd_reg_indirect(p_dev, addr);
1461         retries = duration / 10;
1462
1463         do {
1464                 if ((value & mask) != status) {
1465                         timeout_error = 1;
1466                         msleep(duration / 10);
1467                         value = qlcnic_83xx_rd_reg_indirect(p_dev, addr);
1468                 } else {
1469                         timeout_error = 0;
1470                         break;
1471                 }
1472         } while (retries--);
1473
1474         if (timeout_error) {
1475                 p_dev->ahw->reset.seq_error++;
1476                 dev_err(&p_dev->pdev->dev,
1477                         "%s: Timeout Err, entry_num = %d\n",
1478                         __func__, p_dev->ahw->reset.seq_index);
1479                 dev_err(&p_dev->pdev->dev,
1480                         "0x%08x 0x%08x 0x%08x\n",
1481                         value, mask, status);
1482         }
1483
1484         return timeout_error;
1485 }
1486
1487 static int qlcnic_83xx_reset_template_checksum(struct qlcnic_adapter *p_dev)
1488 {
1489         u32 sum = 0;
1490         u16 *buff = (u16 *)p_dev->ahw->reset.buff;
1491         int count = p_dev->ahw->reset.hdr->size / sizeof(u16);
1492
1493         while (count-- > 0)
1494                 sum += *buff++;
1495
1496         while (sum >> 16)
1497                 sum = (sum & 0xFFFF) + (sum >> 16);
1498
1499         if (~sum) {
1500                 return 0;
1501         } else {
1502                 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__);
1503                 return -1;
1504         }
1505 }
1506
1507 int qlcnic_83xx_get_reset_instruction_template(struct qlcnic_adapter *p_dev)
1508 {
1509         u8 *p_buff;
1510         u32 addr, count;
1511         struct qlcnic_hardware_context *ahw = p_dev->ahw;
1512
1513         ahw->reset.seq_error = 0;
1514         ahw->reset.buff = kzalloc(QLC_83XX_RESTART_TEMPLATE_SIZE, GFP_KERNEL);
1515         if (p_dev->ahw->reset.buff == NULL)
1516                 return -ENOMEM;
1517
1518         p_buff = p_dev->ahw->reset.buff;
1519         addr = QLC_83XX_RESET_TEMPLATE_ADDR;
1520         count = sizeof(struct qlc_83xx_reset_hdr) / sizeof(u32);
1521
1522         /* Copy template header from flash */
1523         if (qlcnic_83xx_flash_read32(p_dev, addr, p_buff, count)) {
1524                 dev_err(&p_dev->pdev->dev, "%s: flash read failed\n", __func__);
1525                 return -EIO;
1526         }
1527         ahw->reset.hdr = (struct qlc_83xx_reset_hdr *)ahw->reset.buff;
1528         addr = QLC_83XX_RESET_TEMPLATE_ADDR + ahw->reset.hdr->hdr_size;
1529         p_buff = ahw->reset.buff + ahw->reset.hdr->hdr_size;
1530         count = (ahw->reset.hdr->size - ahw->reset.hdr->hdr_size) / sizeof(u32);
1531
1532         /* Copy rest of the template */
1533         if (qlcnic_83xx_flash_read32(p_dev, addr, p_buff, count)) {
1534                 dev_err(&p_dev->pdev->dev, "%s: flash read failed\n", __func__);
1535                 return -EIO;
1536         }
1537
1538         if (qlcnic_83xx_reset_template_checksum(p_dev))
1539                 return -EIO;
1540         /* Get Stop, Start and Init command offsets */
1541         ahw->reset.init_offset = ahw->reset.buff + ahw->reset.hdr->init_offset;
1542         ahw->reset.start_offset = ahw->reset.buff +
1543                                   ahw->reset.hdr->start_offset;
1544         ahw->reset.stop_offset = ahw->reset.buff + ahw->reset.hdr->hdr_size;
1545         return 0;
1546 }
1547
1548 /* Read Write HW register command */
1549 static void qlcnic_83xx_read_write_crb_reg(struct qlcnic_adapter *p_dev,
1550                                            u32 raddr, u32 waddr)
1551 {
1552         int value;
1553
1554         value = qlcnic_83xx_rd_reg_indirect(p_dev, raddr);
1555         qlcnic_83xx_wrt_reg_indirect(p_dev, waddr, value);
1556 }
1557
1558 /* Read Modify Write HW register command */
1559 static void qlcnic_83xx_rmw_crb_reg(struct qlcnic_adapter *p_dev,
1560                                     u32 raddr, u32 waddr,
1561                                     struct qlc_83xx_rmw *p_rmw_hdr)
1562 {
1563         int value;
1564
1565         if (p_rmw_hdr->index_a)
1566                 value = p_dev->ahw->reset.array[p_rmw_hdr->index_a];
1567         else
1568                 value = qlcnic_83xx_rd_reg_indirect(p_dev, raddr);
1569
1570         value &= p_rmw_hdr->mask;
1571         value <<= p_rmw_hdr->shl;
1572         value >>= p_rmw_hdr->shr;
1573         value |= p_rmw_hdr->or_value;
1574         value ^= p_rmw_hdr->xor_value;
1575         qlcnic_83xx_wrt_reg_indirect(p_dev, waddr, value);
1576 }
1577
1578 /* Write HW register command */
1579 static void qlcnic_83xx_write_list(struct qlcnic_adapter *p_dev,
1580                                    struct qlc_83xx_entry_hdr *p_hdr)
1581 {
1582         int i;
1583         struct qlc_83xx_entry *entry;
1584
1585         entry = (struct qlc_83xx_entry *)((char *)p_hdr +
1586                                           sizeof(struct qlc_83xx_entry_hdr));
1587
1588         for (i = 0; i < p_hdr->count; i++, entry++) {
1589                 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->arg1,
1590                                              entry->arg2);
1591                 if (p_hdr->delay)
1592                         udelay((u32)(p_hdr->delay));
1593         }
1594 }
1595
1596 /* Read and Write instruction */
1597 static void qlcnic_83xx_read_write_list(struct qlcnic_adapter *p_dev,
1598                                         struct qlc_83xx_entry_hdr *p_hdr)
1599 {
1600         int i;
1601         struct qlc_83xx_entry *entry;
1602
1603         entry = (struct qlc_83xx_entry *)((char *)p_hdr +
1604                                           sizeof(struct qlc_83xx_entry_hdr));
1605
1606         for (i = 0; i < p_hdr->count; i++, entry++) {
1607                 qlcnic_83xx_read_write_crb_reg(p_dev, entry->arg1,
1608                                                entry->arg2);
1609                 if (p_hdr->delay)
1610                         udelay((u32)(p_hdr->delay));
1611         }
1612 }
1613
1614 /* Poll HW register command */
1615 static void qlcnic_83xx_poll_list(struct qlcnic_adapter *p_dev,
1616                                   struct qlc_83xx_entry_hdr *p_hdr)
1617 {
1618         long delay;
1619         struct qlc_83xx_entry *entry;
1620         struct qlc_83xx_poll *poll;
1621         int i;
1622         unsigned long arg1, arg2;
1623
1624         poll = (struct qlc_83xx_poll *)((char *)p_hdr +
1625                                         sizeof(struct qlc_83xx_entry_hdr));
1626
1627         entry = (struct qlc_83xx_entry *)((char *)poll +
1628                                           sizeof(struct qlc_83xx_poll));
1629         delay = (long)p_hdr->delay;
1630
1631         if (!delay) {
1632                 for (i = 0; i < p_hdr->count; i++, entry++)
1633                         qlcnic_83xx_poll_reg(p_dev, entry->arg1,
1634                                              delay, poll->mask,
1635                                              poll->status);
1636         } else {
1637                 for (i = 0; i < p_hdr->count; i++, entry++) {
1638                         arg1 = entry->arg1;
1639                         arg2 = entry->arg2;
1640                         if (delay) {
1641                                 if (qlcnic_83xx_poll_reg(p_dev,
1642                                                          arg1, delay,
1643                                                          poll->mask,
1644                                                          poll->status)){
1645                                         qlcnic_83xx_rd_reg_indirect(p_dev,
1646                                                                     arg1);
1647                                         qlcnic_83xx_rd_reg_indirect(p_dev,
1648                                                                     arg2);
1649                                 }
1650                         }
1651                 }
1652         }
1653 }
1654
1655 /* Poll and write HW register command */
1656 static void qlcnic_83xx_poll_write_list(struct qlcnic_adapter *p_dev,
1657                                         struct qlc_83xx_entry_hdr *p_hdr)
1658 {
1659         int i;
1660         long delay;
1661         struct qlc_83xx_quad_entry *entry;
1662         struct qlc_83xx_poll *poll;
1663
1664         poll = (struct qlc_83xx_poll *)((char *)p_hdr +
1665                                         sizeof(struct qlc_83xx_entry_hdr));
1666         entry = (struct qlc_83xx_quad_entry *)((char *)poll +
1667                                                sizeof(struct qlc_83xx_poll));
1668         delay = (long)p_hdr->delay;
1669
1670         for (i = 0; i < p_hdr->count; i++, entry++) {
1671                 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->dr_addr,
1672                                              entry->dr_value);
1673                 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->ar_addr,
1674                                              entry->ar_value);
1675                 if (delay)
1676                         qlcnic_83xx_poll_reg(p_dev, entry->ar_addr, delay,
1677                                              poll->mask, poll->status);
1678         }
1679 }
1680
1681 /* Read Modify Write register command */
1682 static void qlcnic_83xx_read_modify_write(struct qlcnic_adapter *p_dev,
1683                                           struct qlc_83xx_entry_hdr *p_hdr)
1684 {
1685         int i;
1686         struct qlc_83xx_entry *entry;
1687         struct qlc_83xx_rmw *rmw_hdr;
1688
1689         rmw_hdr = (struct qlc_83xx_rmw *)((char *)p_hdr +
1690                                           sizeof(struct qlc_83xx_entry_hdr));
1691
1692         entry = (struct qlc_83xx_entry *)((char *)rmw_hdr +
1693                                           sizeof(struct qlc_83xx_rmw));
1694
1695         for (i = 0; i < p_hdr->count; i++, entry++) {
1696                 qlcnic_83xx_rmw_crb_reg(p_dev, entry->arg1,
1697                                         entry->arg2, rmw_hdr);
1698                 if (p_hdr->delay)
1699                         udelay((u32)(p_hdr->delay));
1700         }
1701 }
1702
1703 static void qlcnic_83xx_pause(struct qlc_83xx_entry_hdr *p_hdr)
1704 {
1705         if (p_hdr->delay)
1706                 mdelay((u32)((long)p_hdr->delay));
1707 }
1708
1709 /* Read and poll register command */
1710 static void qlcnic_83xx_poll_read_list(struct qlcnic_adapter *p_dev,
1711                                        struct qlc_83xx_entry_hdr *p_hdr)
1712 {
1713         long delay;
1714         int index, i, j;
1715         struct qlc_83xx_quad_entry *entry;
1716         struct qlc_83xx_poll *poll;
1717         unsigned long addr;
1718
1719         poll = (struct qlc_83xx_poll *)((char *)p_hdr +
1720                                         sizeof(struct qlc_83xx_entry_hdr));
1721
1722         entry = (struct qlc_83xx_quad_entry *)((char *)poll +
1723                                                sizeof(struct qlc_83xx_poll));
1724         delay = (long)p_hdr->delay;
1725
1726         for (i = 0; i < p_hdr->count; i++, entry++) {
1727                 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->ar_addr,
1728                                              entry->ar_value);
1729                 if (delay) {
1730                         if (!qlcnic_83xx_poll_reg(p_dev, entry->ar_addr, delay,
1731                                                   poll->mask, poll->status)){
1732                                 index = p_dev->ahw->reset.array_index;
1733                                 addr = entry->dr_addr;
1734                                 j = qlcnic_83xx_rd_reg_indirect(p_dev, addr);
1735                                 p_dev->ahw->reset.array[index++] = j;
1736
1737                                 if (index == QLC_83XX_MAX_RESET_SEQ_ENTRIES)
1738                                         p_dev->ahw->reset.array_index = 1;
1739                         }
1740                 }
1741         }
1742 }
1743
1744 static inline void qlcnic_83xx_seq_end(struct qlcnic_adapter *p_dev)
1745 {
1746         p_dev->ahw->reset.seq_end = 1;
1747 }
1748
1749 static void qlcnic_83xx_template_end(struct qlcnic_adapter *p_dev)
1750 {
1751         p_dev->ahw->reset.template_end = 1;
1752         if (p_dev->ahw->reset.seq_error == 0)
1753                 dev_err(&p_dev->pdev->dev,
1754                         "HW restart process completed successfully.\n");
1755         else
1756                 dev_err(&p_dev->pdev->dev,
1757                         "HW restart completed with timeout errors.\n");
1758 }
1759
1760 /**
1761 * qlcnic_83xx_exec_template_cmd
1762 *
1763 * @p_dev: adapter structure
1764 * @p_buff: Poiter to instruction template
1765 *
1766 * Template provides instructions to stop, restart and initalize firmware.
1767 * These instructions are abstracted as a series of read, write and
1768 * poll operations on hardware registers. Register information and operation
1769 * specifics are not exposed to the driver. Driver reads the template from
1770 * flash and executes the instructions located at pre-defined offsets.
1771 *
1772 * Returns: None
1773 * */
1774 static void qlcnic_83xx_exec_template_cmd(struct qlcnic_adapter *p_dev,
1775                                           char *p_buff)
1776 {
1777         int index, entries;
1778         struct qlc_83xx_entry_hdr *p_hdr;
1779         char *entry = p_buff;
1780
1781         p_dev->ahw->reset.seq_end = 0;
1782         p_dev->ahw->reset.template_end = 0;
1783         entries = p_dev->ahw->reset.hdr->entries;
1784         index = p_dev->ahw->reset.seq_index;
1785
1786         for (; (!p_dev->ahw->reset.seq_end) && (index < entries); index++) {
1787                 p_hdr = (struct qlc_83xx_entry_hdr *)entry;
1788
1789                 switch (p_hdr->cmd) {
1790                 case QLC_83XX_OPCODE_NOP:
1791                         break;
1792                 case QLC_83XX_OPCODE_WRITE_LIST:
1793                         qlcnic_83xx_write_list(p_dev, p_hdr);
1794                         break;
1795                 case QLC_83XX_OPCODE_READ_WRITE_LIST:
1796                         qlcnic_83xx_read_write_list(p_dev, p_hdr);
1797                         break;
1798                 case QLC_83XX_OPCODE_POLL_LIST:
1799                         qlcnic_83xx_poll_list(p_dev, p_hdr);
1800                         break;
1801                 case QLC_83XX_OPCODE_POLL_WRITE_LIST:
1802                         qlcnic_83xx_poll_write_list(p_dev, p_hdr);
1803                         break;
1804                 case QLC_83XX_OPCODE_READ_MODIFY_WRITE:
1805                         qlcnic_83xx_read_modify_write(p_dev, p_hdr);
1806                         break;
1807                 case QLC_83XX_OPCODE_SEQ_PAUSE:
1808                         qlcnic_83xx_pause(p_hdr);
1809                         break;
1810                 case QLC_83XX_OPCODE_SEQ_END:
1811                         qlcnic_83xx_seq_end(p_dev);
1812                         break;
1813                 case QLC_83XX_OPCODE_TMPL_END:
1814                         qlcnic_83xx_template_end(p_dev);
1815                         break;
1816                 case QLC_83XX_OPCODE_POLL_READ_LIST:
1817                         qlcnic_83xx_poll_read_list(p_dev, p_hdr);
1818                         break;
1819                 default:
1820                         dev_err(&p_dev->pdev->dev,
1821                                 "%s: Unknown opcode 0x%04x in template %d\n",
1822                                 __func__, p_hdr->cmd, index);
1823                         break;
1824                 }
1825                 entry += p_hdr->size;
1826         }
1827         p_dev->ahw->reset.seq_index = index;
1828 }
1829
1830 static void qlcnic_83xx_stop_hw(struct qlcnic_adapter *p_dev)
1831 {
1832         p_dev->ahw->reset.seq_index = 0;
1833
1834         qlcnic_83xx_exec_template_cmd(p_dev, p_dev->ahw->reset.stop_offset);
1835         if (p_dev->ahw->reset.seq_end != 1)
1836                 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__);
1837 }
1838
1839 static void qlcnic_83xx_start_hw(struct qlcnic_adapter *p_dev)
1840 {
1841         qlcnic_83xx_exec_template_cmd(p_dev, p_dev->ahw->reset.start_offset);
1842         if (p_dev->ahw->reset.template_end != 1)
1843                 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__);
1844 }
1845
1846 static void qlcnic_83xx_init_hw(struct qlcnic_adapter *p_dev)
1847 {
1848         qlcnic_83xx_exec_template_cmd(p_dev, p_dev->ahw->reset.init_offset);
1849         if (p_dev->ahw->reset.seq_end != 1)
1850                 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__);
1851 }
1852
1853 static int qlcnic_83xx_load_fw_image_from_host(struct qlcnic_adapter *adapter)
1854 {
1855         int err = -EIO;
1856
1857         if (request_firmware(&adapter->ahw->fw_info.fw,
1858                              QLC_83XX_FW_FILE_NAME, &(adapter->pdev->dev))) {
1859                 dev_err(&adapter->pdev->dev,
1860                         "No file FW image, loading flash FW image.\n");
1861                 QLC_SHARED_REG_WR32(adapter, QLCNIC_FW_IMG_VALID,
1862                                     QLC_83XX_BOOT_FROM_FLASH);
1863         } else {
1864                 if (qlcnic_83xx_copy_fw_file(adapter))
1865                         return err;
1866                 QLC_SHARED_REG_WR32(adapter, QLCNIC_FW_IMG_VALID,
1867                                     QLC_83XX_BOOT_FROM_FILE);
1868         }
1869
1870         return 0;
1871 }
1872
1873 static int qlcnic_83xx_restart_hw(struct qlcnic_adapter *adapter)
1874 {
1875         u32 val;
1876         int err = -EIO;
1877
1878         qlcnic_83xx_stop_hw(adapter);
1879
1880         /* Collect FW register dump if required */
1881         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1882         if (!(val & QLC_83XX_IDC_GRACEFULL_RESET))
1883                 qlcnic_dump_fw(adapter);
1884         qlcnic_83xx_init_hw(adapter);
1885
1886         if (qlcnic_83xx_copy_bootloader(adapter))
1887                 return err;
1888         /* Boot either flash image or firmware image from host file system */
1889         if (qlcnic_load_fw_file) {
1890                 if (qlcnic_83xx_load_fw_image_from_host(adapter))
1891                         return err;
1892         } else {
1893                 QLC_SHARED_REG_WR32(adapter, QLCNIC_FW_IMG_VALID,
1894                                     QLC_83XX_BOOT_FROM_FLASH);
1895         }
1896
1897         qlcnic_83xx_start_hw(adapter);
1898         if (qlcnic_83xx_check_hw_status(adapter))
1899                 return -EIO;
1900
1901         return 0;
1902 }
1903
1904 /**
1905 * qlcnic_83xx_config_default_opmode
1906 *
1907 * @adapter: adapter structure
1908 *
1909 * Configure default driver operating mode
1910 *
1911 * Returns: Error code or Success(0)
1912 * */
1913 int qlcnic_83xx_config_default_opmode(struct qlcnic_adapter *adapter)
1914 {
1915         u32 op_mode;
1916         struct qlcnic_hardware_context *ahw = adapter->ahw;
1917
1918         qlcnic_get_func_no(adapter);
1919         op_mode = QLCRDX(ahw, QLC_83XX_DRV_OP_MODE);
1920
1921         if (op_mode == QLC_83XX_DEFAULT_OPMODE) {
1922                 adapter->nic_ops->init_driver = qlcnic_83xx_init_default_driver;
1923                 ahw->idc.state_entry = qlcnic_83xx_idc_ready_state_entry;
1924         } else {
1925                 return -EIO;
1926         }
1927
1928         return 0;
1929 }
1930
1931 int qlcnic_83xx_get_nic_configuration(struct qlcnic_adapter *adapter)
1932 {
1933         int err;
1934         struct qlcnic_info nic_info;
1935         struct qlcnic_hardware_context *ahw = adapter->ahw;
1936
1937         memset(&nic_info, 0, sizeof(struct qlcnic_info));
1938         err = qlcnic_get_nic_info(adapter, &nic_info, ahw->pci_func);
1939         if (err)
1940                 return -EIO;
1941
1942         ahw->physical_port = (u8) nic_info.phys_port;
1943         ahw->switch_mode = nic_info.switch_mode;
1944         ahw->max_tx_ques = nic_info.max_tx_ques;
1945         ahw->max_rx_ques = nic_info.max_rx_ques;
1946         ahw->capabilities = nic_info.capabilities;
1947         ahw->max_mac_filters = nic_info.max_mac_filters;
1948         ahw->max_mtu = nic_info.max_mtu;
1949
1950         if (ahw->capabilities & BIT_23)
1951                 ahw->nic_mode = QLC_83XX_VIRTUAL_NIC_MODE;
1952         else
1953                 ahw->nic_mode = QLC_83XX_DEFAULT_MODE;
1954
1955         return ahw->nic_mode;
1956 }
1957
1958 static int qlcnic_83xx_configure_opmode(struct qlcnic_adapter *adapter)
1959 {
1960         int ret;
1961
1962         ret = qlcnic_83xx_get_nic_configuration(adapter);
1963         if (ret == -EIO)
1964                 return -EIO;
1965
1966         if (ret == QLC_83XX_VIRTUAL_NIC_MODE) {
1967                 if (qlcnic_83xx_config_vnic_opmode(adapter))
1968                         return -EIO;
1969         } else if (ret == QLC_83XX_DEFAULT_MODE) {
1970                 if (qlcnic_83xx_config_default_opmode(adapter))
1971                         return -EIO;
1972         }
1973
1974         return 0;
1975 }
1976
1977 static void qlcnic_83xx_config_buff_descriptors(struct qlcnic_adapter *adapter)
1978 {
1979         struct qlcnic_hardware_context *ahw = adapter->ahw;
1980
1981         if (ahw->port_type == QLCNIC_XGBE) {
1982                 adapter->num_rxd = DEFAULT_RCV_DESCRIPTORS_10G;
1983                 adapter->max_rxd = MAX_RCV_DESCRIPTORS_10G;
1984                 adapter->num_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_10G;
1985                 adapter->max_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_10G;
1986
1987         } else if (ahw->port_type == QLCNIC_GBE) {
1988                 adapter->num_rxd = DEFAULT_RCV_DESCRIPTORS_1G;
1989                 adapter->num_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_1G;
1990                 adapter->max_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_1G;
1991                 adapter->max_rxd = MAX_RCV_DESCRIPTORS_1G;
1992         }
1993         adapter->num_txd = MAX_CMD_DESCRIPTORS;
1994         adapter->max_rds_rings = MAX_RDS_RINGS;
1995 }
1996
1997 static int qlcnic_83xx_init_default_driver(struct qlcnic_adapter *adapter)
1998 {
1999         int err = -EIO;
2000
2001         qlcnic_83xx_get_minidump_template(adapter);
2002         if (qlcnic_83xx_get_port_info(adapter))
2003                 return err;
2004
2005         qlcnic_83xx_config_buff_descriptors(adapter);
2006         adapter->ahw->msix_supported = !!qlcnic_use_msi_x;
2007         adapter->flags |= QLCNIC_ADAPTER_INITIALIZED;
2008
2009         dev_info(&adapter->pdev->dev, "HAL Version: %d\n",
2010                  adapter->ahw->fw_hal_version);
2011
2012         return 0;
2013 }
2014
2015 #define IS_QLC_83XX_USED(a, b, c) (((1 << a->portnum) & b) || ((c >> 6) & 0x1))
2016 static void qlcnic_83xx_clear_function_resources(struct qlcnic_adapter *adapter)
2017 {
2018         struct qlcnic_cmd_args cmd;
2019         u32 presence_mask, audit_mask;
2020         int status;
2021
2022         presence_mask = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
2023         audit_mask = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_AUDIT);
2024
2025         if (IS_QLC_83XX_USED(adapter, presence_mask, audit_mask)) {
2026                 qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_STOP_NIC_FUNC);
2027                 cmd.req.arg[1] = BIT_31;
2028                 status = qlcnic_issue_cmd(adapter, &cmd);
2029                 if (status)
2030                         dev_err(&adapter->pdev->dev,
2031                                 "Failed to clean up the function resources\n");
2032                 qlcnic_free_mbx_args(&cmd);
2033         }
2034 }
2035
2036 int qlcnic_83xx_init(struct qlcnic_adapter *adapter)
2037 {
2038         struct qlcnic_hardware_context *ahw = adapter->ahw;
2039
2040         if (qlcnic_83xx_check_hw_status(adapter))
2041                 return -EIO;
2042
2043         /* Initilaize 83xx mailbox spinlock */
2044         spin_lock_init(&ahw->mbx_lock);
2045
2046         set_bit(QLC_83XX_MBX_READY, &adapter->ahw->idc.status);
2047         qlcnic_83xx_clear_function_resources(adapter);
2048
2049         /* register for NIC IDC AEN Events */
2050         qlcnic_83xx_register_nic_idc_func(adapter, 1);
2051
2052         if (!qlcnic_83xx_read_flash_descriptor_table(adapter))
2053                 qlcnic_83xx_read_flash_mfg_id(adapter);
2054
2055         if (qlcnic_83xx_idc_init(adapter))
2056                 return -EIO;
2057
2058         /* Configure default, SR-IOV or Virtual NIC mode of operation */
2059         if (qlcnic_83xx_configure_opmode(adapter))
2060                 return -EIO;
2061
2062         /* Perform operating mode specific initialization */
2063         if (adapter->nic_ops->init_driver(adapter))
2064                 return -EIO;
2065
2066         INIT_DELAYED_WORK(&adapter->idc_aen_work, qlcnic_83xx_idc_aen_work);
2067
2068         /* Periodically monitor device status */
2069         qlcnic_83xx_idc_poll_dev_state(&adapter->fw_work.work);
2070
2071         return adapter->ahw->idc.err_code;
2072 }