2 * QLogic qlcnic NIC Driver
3 * Copyright (c) 2009-2013 QLogic Corporation
5 * See LICENSE.qlcnic for copyright and licensing details.
10 static const struct qlcnic_mailbox_metadata qlcnic_mbx_tbl[] = {
11 {QLCNIC_CMD_CREATE_RX_CTX, 4, 1},
12 {QLCNIC_CMD_DESTROY_RX_CTX, 2, 1},
13 {QLCNIC_CMD_CREATE_TX_CTX, 4, 1},
14 {QLCNIC_CMD_DESTROY_TX_CTX, 2, 1},
15 {QLCNIC_CMD_INTRPT_TEST, 4, 1},
16 {QLCNIC_CMD_SET_MTU, 4, 1},
17 {QLCNIC_CMD_READ_PHY, 4, 2},
18 {QLCNIC_CMD_WRITE_PHY, 5, 1},
19 {QLCNIC_CMD_READ_HW_REG, 4, 1},
20 {QLCNIC_CMD_GET_FLOW_CTL, 4, 2},
21 {QLCNIC_CMD_SET_FLOW_CTL, 4, 1},
22 {QLCNIC_CMD_READ_MAX_MTU, 4, 2},
23 {QLCNIC_CMD_READ_MAX_LRO, 4, 2},
24 {QLCNIC_CMD_MAC_ADDRESS, 4, 3},
25 {QLCNIC_CMD_GET_PCI_INFO, 4, 1},
26 {QLCNIC_CMD_GET_NIC_INFO, 4, 1},
27 {QLCNIC_CMD_SET_NIC_INFO, 4, 1},
28 {QLCNIC_CMD_GET_ESWITCH_CAPABILITY, 4, 3},
29 {QLCNIC_CMD_TOGGLE_ESWITCH, 4, 1},
30 {QLCNIC_CMD_GET_ESWITCH_STATUS, 4, 3},
31 {QLCNIC_CMD_SET_PORTMIRRORING, 4, 1},
32 {QLCNIC_CMD_CONFIGURE_ESWITCH, 4, 1},
33 {QLCNIC_CMD_GET_MAC_STATS, 4, 1},
34 {QLCNIC_CMD_GET_ESWITCH_PORT_CONFIG, 4, 3},
35 {QLCNIC_CMD_GET_ESWITCH_STATS, 4, 1},
36 {QLCNIC_CMD_CONFIG_PORT, 4, 1},
37 {QLCNIC_CMD_TEMP_SIZE, 4, 4},
38 {QLCNIC_CMD_GET_TEMP_HDR, 4, 1},
39 {QLCNIC_CMD_82XX_SET_DRV_VER, 4, 1},
40 {QLCNIC_CMD_GET_LED_STATUS, 4, 2},
41 {QLCNIC_CMD_MQ_TX_CONFIG_INTR, 2, 3},
42 {QLCNIC_CMD_DCB_QUERY_CAP, 1, 2},
43 {QLCNIC_CMD_DCB_QUERY_PARAM, 4, 1},
46 static inline u32 qlcnic_get_cmd_signature(struct qlcnic_hardware_context *ahw)
48 return (ahw->pci_func & 0xff) | ((ahw->fw_hal_version & 0xff) << 8) |
52 /* Allocate mailbox registers */
53 int qlcnic_82xx_alloc_mbx_args(struct qlcnic_cmd_args *mbx,
54 struct qlcnic_adapter *adapter, u32 type)
57 const struct qlcnic_mailbox_metadata *mbx_tbl;
59 mbx_tbl = qlcnic_mbx_tbl;
60 size = ARRAY_SIZE(qlcnic_mbx_tbl);
61 for (i = 0; i < size; i++) {
62 if (type == mbx_tbl[i].cmd) {
63 mbx->req.num = mbx_tbl[i].in_args;
64 mbx->rsp.num = mbx_tbl[i].out_args;
65 mbx->req.arg = kcalloc(mbx->req.num,
66 sizeof(u32), GFP_ATOMIC);
69 mbx->rsp.arg = kcalloc(mbx->rsp.num,
70 sizeof(u32), GFP_ATOMIC);
76 memset(mbx->req.arg, 0, sizeof(u32) * mbx->req.num);
77 memset(mbx->rsp.arg, 0, sizeof(u32) * mbx->rsp.num);
78 mbx->req.arg[0] = type;
85 /* Free up mailbox registers */
86 void qlcnic_free_mbx_args(struct qlcnic_cmd_args *cmd)
95 qlcnic_poll_rsp(struct qlcnic_adapter *adapter)
98 int timeout = 0, err = 0;
101 /* give atleast 1ms for firmware to respond */
104 if (++timeout > QLCNIC_OS_CRB_RETRY_COUNT)
105 return QLCNIC_CDRP_RSP_TIMEOUT;
107 rsp = QLCRD32(adapter, QLCNIC_CDRP_CRB_OFFSET, &err);
108 } while (!QLCNIC_CDRP_IS_RSP(rsp));
113 int qlcnic_82xx_issue_cmd(struct qlcnic_adapter *adapter,
114 struct qlcnic_cmd_args *cmd)
119 struct pci_dev *pdev = adapter->pdev;
120 struct qlcnic_hardware_context *ahw = adapter->ahw;
123 signature = qlcnic_get_cmd_signature(ahw);
125 /* Acquire semaphore before accessing CRB */
126 if (qlcnic_api_lock(adapter)) {
127 cmd->rsp.arg[0] = QLCNIC_RCODE_TIMEOUT;
128 return cmd->rsp.arg[0];
131 QLCWR32(adapter, QLCNIC_SIGN_CRB_OFFSET, signature);
132 for (i = 1; i < cmd->req.num; i++)
133 QLCWR32(adapter, QLCNIC_CDRP_ARG(i), cmd->req.arg[i]);
134 QLCWR32(adapter, QLCNIC_CDRP_CRB_OFFSET,
135 QLCNIC_CDRP_FORM_CMD(cmd->req.arg[0]));
136 rsp = qlcnic_poll_rsp(adapter);
138 if (rsp == QLCNIC_CDRP_RSP_TIMEOUT) {
139 dev_err(&pdev->dev, "command timeout, response = 0x%x\n", rsp);
140 cmd->rsp.arg[0] = QLCNIC_RCODE_TIMEOUT;
141 } else if (rsp == QLCNIC_CDRP_RSP_FAIL) {
142 cmd->rsp.arg[0] = QLCRD32(adapter, QLCNIC_CDRP_ARG(1), &err);
143 switch (cmd->rsp.arg[0]) {
144 case QLCNIC_RCODE_INVALID_ARGS:
145 fmt = "CDRP invalid args: [%d]\n";
147 case QLCNIC_RCODE_NOT_SUPPORTED:
148 case QLCNIC_RCODE_NOT_IMPL:
149 fmt = "CDRP command not supported: [%d]\n";
151 case QLCNIC_RCODE_NOT_PERMITTED:
152 fmt = "CDRP requested action not permitted: [%d]\n";
154 case QLCNIC_RCODE_INVALID:
155 fmt = "CDRP invalid or unknown cmd received: [%d]\n";
157 case QLCNIC_RCODE_TIMEOUT:
158 fmt = "CDRP command timeout: [%d]\n";
161 fmt = "CDRP command failed: [%d]\n";
164 dev_err(&pdev->dev, fmt, cmd->rsp.arg[0]);
165 qlcnic_dump_mbx(adapter, cmd);
166 } else if (rsp == QLCNIC_CDRP_RSP_OK)
167 cmd->rsp.arg[0] = QLCNIC_RCODE_SUCCESS;
169 for (i = 1; i < cmd->rsp.num; i++)
170 cmd->rsp.arg[i] = QLCRD32(adapter, QLCNIC_CDRP_ARG(i), &err);
172 /* Release semaphore */
173 qlcnic_api_unlock(adapter);
174 return cmd->rsp.arg[0];
177 int qlcnic_fw_cmd_set_drv_version(struct qlcnic_adapter *adapter, u32 fw_cmd)
179 struct qlcnic_cmd_args cmd;
180 u32 arg1, arg2, arg3;
184 memset(drv_string, 0, sizeof(drv_string));
185 snprintf(drv_string, sizeof(drv_string), "%d"".""%d"".""%d",
186 _QLCNIC_LINUX_MAJOR, _QLCNIC_LINUX_MINOR,
187 _QLCNIC_LINUX_SUBVERSION);
189 err = qlcnic_alloc_mbx_args(&cmd, adapter, fw_cmd);
193 memcpy(&arg1, drv_string, sizeof(u32));
194 memcpy(&arg2, drv_string + 4, sizeof(u32));
195 memcpy(&arg3, drv_string + 8, sizeof(u32));
197 cmd.req.arg[1] = arg1;
198 cmd.req.arg[2] = arg2;
199 cmd.req.arg[3] = arg3;
201 err = qlcnic_issue_cmd(adapter, &cmd);
203 dev_info(&adapter->pdev->dev,
204 "Failed to set driver version in firmware\n");
207 qlcnic_free_mbx_args(&cmd);
212 qlcnic_fw_cmd_set_mtu(struct qlcnic_adapter *adapter, int mtu)
215 struct qlcnic_cmd_args cmd;
216 struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
218 if (recv_ctx->state != QLCNIC_HOST_CTX_STATE_ACTIVE)
220 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_SET_MTU);
224 cmd.req.arg[1] = recv_ctx->context_id;
225 cmd.req.arg[2] = mtu;
227 err = qlcnic_issue_cmd(adapter, &cmd);
229 dev_err(&adapter->pdev->dev, "Failed to set mtu\n");
232 qlcnic_free_mbx_args(&cmd);
236 int qlcnic_82xx_fw_cmd_create_rx_ctx(struct qlcnic_adapter *adapter)
238 struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
239 struct qlcnic_hardware_context *ahw = adapter->ahw;
240 dma_addr_t hostrq_phys_addr, cardrsp_phys_addr;
241 struct net_device *netdev = adapter->netdev;
242 u32 temp_intr_crb_mode, temp_rds_crb_mode;
243 struct qlcnic_cardrsp_rds_ring *prsp_rds;
244 struct qlcnic_cardrsp_sds_ring *prsp_sds;
245 struct qlcnic_hostrq_rds_ring *prq_rds;
246 struct qlcnic_hostrq_sds_ring *prq_sds;
247 struct qlcnic_host_rds_ring *rds_ring;
248 struct qlcnic_host_sds_ring *sds_ring;
249 struct qlcnic_cardrsp_rx_ctx *prsp;
250 struct qlcnic_hostrq_rx_ctx *prq;
251 u8 i, nrds_rings, nsds_rings;
252 struct qlcnic_cmd_args cmd;
253 size_t rq_size, rsp_size;
254 u32 cap, reg, val, reg2;
260 nrds_rings = adapter->max_rds_rings;
261 nsds_rings = adapter->drv_sds_rings;
263 rq_size = SIZEOF_HOSTRQ_RX(struct qlcnic_hostrq_rx_ctx, nrds_rings,
265 rsp_size = SIZEOF_CARDRSP_RX(struct qlcnic_cardrsp_rx_ctx, nrds_rings,
268 addr = dma_alloc_coherent(&adapter->pdev->dev, rq_size,
269 &hostrq_phys_addr, GFP_KERNEL);
274 addr = dma_alloc_coherent(&adapter->pdev->dev, rsp_size,
275 &cardrsp_phys_addr, GFP_KERNEL);
282 prq->host_rsp_dma_addr = cpu_to_le64(cardrsp_phys_addr);
284 cap = (QLCNIC_CAP0_LEGACY_CONTEXT | QLCNIC_CAP0_LEGACY_MN
285 | QLCNIC_CAP0_VALIDOFF);
286 cap |= (QLCNIC_CAP0_JUMBO_CONTIGUOUS | QLCNIC_CAP0_LRO_CONTIGUOUS);
288 if (qlcnic_check_multi_tx(adapter) &&
289 !adapter->ahw->diag_test) {
290 cap |= QLCNIC_CAP0_TX_MULTI;
292 temp_u16 = offsetof(struct qlcnic_hostrq_rx_ctx, msix_handler);
293 prq->valid_field_offset = cpu_to_le16(temp_u16);
294 prq->txrx_sds_binding = nsds_rings - 1;
295 temp_intr_crb_mode = QLCNIC_HOST_INT_CRB_MODE_SHARED;
296 prq->host_int_crb_mode = cpu_to_le32(temp_intr_crb_mode);
297 temp_rds_crb_mode = QLCNIC_HOST_RDS_CRB_MODE_UNIQUE;
298 prq->host_rds_crb_mode = cpu_to_le32(temp_rds_crb_mode);
301 prq->capabilities[0] = cpu_to_le32(cap);
303 prq->num_rds_rings = cpu_to_le16(nrds_rings);
304 prq->num_sds_rings = cpu_to_le16(nsds_rings);
305 prq->rds_ring_offset = 0;
307 val = le32_to_cpu(prq->rds_ring_offset) +
308 (sizeof(struct qlcnic_hostrq_rds_ring) * nrds_rings);
309 prq->sds_ring_offset = cpu_to_le32(val);
311 prq_rds = (struct qlcnic_hostrq_rds_ring *)(prq->data +
312 le32_to_cpu(prq->rds_ring_offset));
314 for (i = 0; i < nrds_rings; i++) {
315 rds_ring = &recv_ctx->rds_rings[i];
316 rds_ring->producer = 0;
317 prq_rds[i].host_phys_addr = cpu_to_le64(rds_ring->phys_addr);
318 prq_rds[i].ring_size = cpu_to_le32(rds_ring->num_desc);
319 prq_rds[i].ring_kind = cpu_to_le32(i);
320 prq_rds[i].buff_size = cpu_to_le64(rds_ring->dma_size);
323 prq_sds = (struct qlcnic_hostrq_sds_ring *)(prq->data +
324 le32_to_cpu(prq->sds_ring_offset));
326 for (i = 0; i < nsds_rings; i++) {
327 sds_ring = &recv_ctx->sds_rings[i];
328 sds_ring->consumer = 0;
329 memset(sds_ring->desc_head, 0, STATUS_DESC_RINGSIZE(sds_ring));
330 prq_sds[i].host_phys_addr = cpu_to_le64(sds_ring->phys_addr);
331 prq_sds[i].ring_size = cpu_to_le32(sds_ring->num_desc);
332 if (qlcnic_check_multi_tx(adapter) &&
333 !adapter->ahw->diag_test)
334 prq_sds[i].msi_index = cpu_to_le16(ahw->intr_tbl[i].id);
336 prq_sds[i].msi_index = cpu_to_le16(i);
339 phys_addr = hostrq_phys_addr;
340 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CREATE_RX_CTX);
344 cmd.req.arg[1] = MSD(phys_addr);
345 cmd.req.arg[2] = LSD(phys_addr);
346 cmd.req.arg[3] = rq_size;
347 err = qlcnic_issue_cmd(adapter, &cmd);
349 dev_err(&adapter->pdev->dev,
350 "Failed to create rx ctx in firmware%d\n", err);
354 prsp_rds = ((struct qlcnic_cardrsp_rds_ring *)
355 &prsp->data[le32_to_cpu(prsp->rds_ring_offset)]);
357 for (i = 0; i < le16_to_cpu(prsp->num_rds_rings); i++) {
358 rds_ring = &recv_ctx->rds_rings[i];
359 reg = le32_to_cpu(prsp_rds[i].host_producer_crb);
360 rds_ring->crb_rcv_producer = ahw->pci_base0 + reg;
363 prsp_sds = ((struct qlcnic_cardrsp_sds_ring *)
364 &prsp->data[le32_to_cpu(prsp->sds_ring_offset)]);
366 for (i = 0; i < le16_to_cpu(prsp->num_sds_rings); i++) {
367 sds_ring = &recv_ctx->sds_rings[i];
368 reg = le32_to_cpu(prsp_sds[i].host_consumer_crb);
369 if (qlcnic_check_multi_tx(adapter) && !adapter->ahw->diag_test)
370 reg2 = ahw->intr_tbl[i].src;
372 reg2 = le32_to_cpu(prsp_sds[i].interrupt_crb);
374 sds_ring->crb_intr_mask = ahw->pci_base0 + reg2;
375 sds_ring->crb_sts_consumer = ahw->pci_base0 + reg;
378 recv_ctx->state = le32_to_cpu(prsp->host_ctx_state);
379 recv_ctx->context_id = le16_to_cpu(prsp->context_id);
380 recv_ctx->virt_port = prsp->virt_port;
382 netdev_info(netdev, "Rx Context[%d] Created, state 0x%x\n",
383 recv_ctx->context_id, recv_ctx->state);
384 qlcnic_free_mbx_args(&cmd);
387 dma_free_coherent(&adapter->pdev->dev, rsp_size, prsp,
390 dma_free_coherent(&adapter->pdev->dev, rq_size, prq, hostrq_phys_addr);
395 void qlcnic_82xx_fw_cmd_del_rx_ctx(struct qlcnic_adapter *adapter)
398 struct qlcnic_cmd_args cmd;
399 struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
401 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_DESTROY_RX_CTX);
405 cmd.req.arg[1] = recv_ctx->context_id;
406 err = qlcnic_issue_cmd(adapter, &cmd);
408 dev_err(&adapter->pdev->dev,
409 "Failed to destroy rx ctx in firmware\n");
411 recv_ctx->state = QLCNIC_HOST_CTX_STATE_FREED;
412 qlcnic_free_mbx_args(&cmd);
415 int qlcnic_82xx_fw_cmd_create_tx_ctx(struct qlcnic_adapter *adapter,
416 struct qlcnic_host_tx_ring *tx_ring,
419 struct qlcnic_hardware_context *ahw = adapter->ahw;
420 struct net_device *netdev = adapter->netdev;
421 struct qlcnic_hostrq_tx_ctx *prq;
422 struct qlcnic_hostrq_cds_ring *prq_cds;
423 struct qlcnic_cardrsp_tx_ctx *prsp;
424 struct qlcnic_cmd_args cmd;
425 u32 temp, intr_mask, temp_int_crb_mode;
426 dma_addr_t rq_phys_addr, rsp_phys_addr;
427 int temp_nsds_rings, index, err;
428 void *rq_addr, *rsp_addr;
429 size_t rq_size, rsp_size;
433 /* reset host resources */
434 tx_ring->producer = 0;
435 tx_ring->sw_consumer = 0;
436 *(tx_ring->hw_consumer) = 0;
438 rq_size = SIZEOF_HOSTRQ_TX(struct qlcnic_hostrq_tx_ctx);
439 rq_addr = dma_zalloc_coherent(&adapter->pdev->dev, rq_size,
440 &rq_phys_addr, GFP_KERNEL);
444 rsp_size = SIZEOF_CARDRSP_TX(struct qlcnic_cardrsp_tx_ctx);
445 rsp_addr = dma_zalloc_coherent(&adapter->pdev->dev, rsp_size,
446 &rsp_phys_addr, GFP_KERNEL);
455 prq->host_rsp_dma_addr = cpu_to_le64(rsp_phys_addr);
457 temp = (QLCNIC_CAP0_LEGACY_CONTEXT | QLCNIC_CAP0_LEGACY_MN |
459 if (qlcnic_check_multi_tx(adapter) && !adapter->ahw->diag_test)
460 temp |= QLCNIC_CAP0_TX_MULTI;
462 prq->capabilities[0] = cpu_to_le32(temp);
464 if (qlcnic_check_multi_tx(adapter) &&
465 !adapter->ahw->diag_test) {
466 temp_nsds_rings = adapter->drv_sds_rings;
467 index = temp_nsds_rings + ring;
468 msix_id = ahw->intr_tbl[index].id;
469 prq->msi_index = cpu_to_le16(msix_id);
471 temp_int_crb_mode = QLCNIC_HOST_INT_CRB_MODE_SHARED;
472 prq->host_int_crb_mode = cpu_to_le32(temp_int_crb_mode);
476 prq->interrupt_ctl = 0;
477 prq->cmd_cons_dma_addr = cpu_to_le64(tx_ring->hw_cons_phys_addr);
479 prq_cds = &prq->cds_ring;
481 prq_cds->host_phys_addr = cpu_to_le64(tx_ring->phys_addr);
482 prq_cds->ring_size = cpu_to_le32(tx_ring->num_desc);
484 phys_addr = rq_phys_addr;
486 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CREATE_TX_CTX);
490 cmd.req.arg[1] = MSD(phys_addr);
491 cmd.req.arg[2] = LSD(phys_addr);
492 cmd.req.arg[3] = rq_size;
493 err = qlcnic_issue_cmd(adapter, &cmd);
495 if (err == QLCNIC_RCODE_SUCCESS) {
496 tx_ring->state = le32_to_cpu(prsp->host_ctx_state);
497 temp = le32_to_cpu(prsp->cds_ring.host_producer_crb);
498 tx_ring->crb_cmd_producer = adapter->ahw->pci_base0 + temp;
499 tx_ring->ctx_id = le16_to_cpu(prsp->context_id);
500 if (qlcnic_check_multi_tx(adapter) &&
501 !adapter->ahw->diag_test &&
502 (adapter->flags & QLCNIC_MSIX_ENABLED)) {
503 index = adapter->drv_sds_rings + ring;
504 intr_mask = ahw->intr_tbl[index].src;
505 tx_ring->crb_intr_mask = ahw->pci_base0 + intr_mask;
508 netdev_info(netdev, "Tx Context[0x%x] Created, state 0x%x\n",
509 tx_ring->ctx_id, tx_ring->state);
511 netdev_err(netdev, "Failed to create tx ctx in firmware%d\n",
515 qlcnic_free_mbx_args(&cmd);
518 dma_free_coherent(&adapter->pdev->dev, rsp_size, rsp_addr,
521 dma_free_coherent(&adapter->pdev->dev, rq_size, rq_addr, rq_phys_addr);
526 void qlcnic_82xx_fw_cmd_del_tx_ctx(struct qlcnic_adapter *adapter,
527 struct qlcnic_host_tx_ring *tx_ring)
529 struct qlcnic_cmd_args cmd;
532 ret = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_DESTROY_TX_CTX);
536 cmd.req.arg[1] = tx_ring->ctx_id;
537 if (qlcnic_issue_cmd(adapter, &cmd))
538 dev_err(&adapter->pdev->dev,
539 "Failed to destroy tx ctx in firmware\n");
540 qlcnic_free_mbx_args(&cmd);
544 qlcnic_fw_cmd_set_port(struct qlcnic_adapter *adapter, u32 config)
547 struct qlcnic_cmd_args cmd;
549 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIG_PORT);
553 cmd.req.arg[1] = config;
554 err = qlcnic_issue_cmd(adapter, &cmd);
555 qlcnic_free_mbx_args(&cmd);
559 int qlcnic_alloc_hw_resources(struct qlcnic_adapter *adapter)
563 struct qlcnic_recv_context *recv_ctx;
564 struct qlcnic_host_rds_ring *rds_ring;
565 struct qlcnic_host_sds_ring *sds_ring;
566 struct qlcnic_host_tx_ring *tx_ring;
569 struct pci_dev *pdev = adapter->pdev;
571 recv_ctx = adapter->recv_ctx;
573 for (ring = 0; ring < adapter->drv_tx_rings; ring++) {
574 tx_ring = &adapter->tx_ring[ring];
575 ptr = (__le32 *)dma_alloc_coherent(&pdev->dev, sizeof(u32),
576 &tx_ring->hw_cons_phys_addr,
581 tx_ring->hw_consumer = ptr;
583 addr = dma_alloc_coherent(&pdev->dev, TX_DESC_RINGSIZE(tx_ring),
591 tx_ring->desc_head = addr;
594 for (ring = 0; ring < adapter->max_rds_rings; ring++) {
595 rds_ring = &recv_ctx->rds_rings[ring];
596 addr = dma_alloc_coherent(&adapter->pdev->dev,
597 RCV_DESC_RINGSIZE(rds_ring),
598 &rds_ring->phys_addr, GFP_KERNEL);
603 rds_ring->desc_head = addr;
607 for (ring = 0; ring < adapter->drv_sds_rings; ring++) {
608 sds_ring = &recv_ctx->sds_rings[ring];
610 addr = dma_alloc_coherent(&adapter->pdev->dev,
611 STATUS_DESC_RINGSIZE(sds_ring),
612 &sds_ring->phys_addr, GFP_KERNEL);
617 sds_ring->desc_head = addr;
623 qlcnic_free_hw_resources(adapter);
627 int qlcnic_fw_create_ctx(struct qlcnic_adapter *dev)
631 if (dev->flags & QLCNIC_NEED_FLR) {
632 pci_reset_function(dev->pdev);
633 dev->flags &= ~QLCNIC_NEED_FLR;
636 if (qlcnic_83xx_check(dev) && (dev->flags & QLCNIC_MSIX_ENABLED)) {
637 if (dev->ahw->diag_test != QLCNIC_LOOPBACK_TEST) {
638 err = qlcnic_83xx_config_intrpt(dev, 1);
644 if (qlcnic_82xx_check(dev) && (dev->flags & QLCNIC_MSIX_ENABLED) &&
645 qlcnic_check_multi_tx(dev) && !dev->ahw->diag_test) {
646 err = qlcnic_82xx_mq_intrpt(dev, 1);
651 err = qlcnic_fw_cmd_create_rx_ctx(dev);
655 for (ring = 0; ring < dev->drv_tx_rings; ring++) {
656 err = qlcnic_fw_cmd_create_tx_ctx(dev,
660 qlcnic_fw_cmd_del_rx_ctx(dev);
664 for (i = 0; i < ring; i++)
665 qlcnic_fw_cmd_del_tx_ctx(dev, &dev->tx_ring[i]);
671 set_bit(__QLCNIC_FW_ATTACHED, &dev->state);
676 if (qlcnic_82xx_check(dev) && (dev->flags & QLCNIC_MSIX_ENABLED) &&
677 qlcnic_check_multi_tx(dev) && !dev->ahw->diag_test)
678 qlcnic_82xx_config_intrpt(dev, 0);
680 if (qlcnic_83xx_check(dev) && (dev->flags & QLCNIC_MSIX_ENABLED)) {
681 if (dev->ahw->diag_test != QLCNIC_LOOPBACK_TEST)
682 qlcnic_83xx_config_intrpt(dev, 0);
688 void qlcnic_fw_destroy_ctx(struct qlcnic_adapter *adapter)
692 if (test_and_clear_bit(__QLCNIC_FW_ATTACHED, &adapter->state)) {
693 qlcnic_fw_cmd_del_rx_ctx(adapter);
694 for (ring = 0; ring < adapter->drv_tx_rings; ring++)
695 qlcnic_fw_cmd_del_tx_ctx(adapter,
696 &adapter->tx_ring[ring]);
698 if (qlcnic_82xx_check(adapter) &&
699 (adapter->flags & QLCNIC_MSIX_ENABLED) &&
700 qlcnic_check_multi_tx(adapter) &&
701 !adapter->ahw->diag_test)
702 qlcnic_82xx_config_intrpt(adapter, 0);
704 if (qlcnic_83xx_check(adapter) &&
705 (adapter->flags & QLCNIC_MSIX_ENABLED)) {
706 if (adapter->ahw->diag_test != QLCNIC_LOOPBACK_TEST)
707 qlcnic_83xx_config_intrpt(adapter, 0);
709 /* Allow dma queues to drain after context reset */
714 void qlcnic_free_hw_resources(struct qlcnic_adapter *adapter)
716 struct qlcnic_recv_context *recv_ctx;
717 struct qlcnic_host_rds_ring *rds_ring;
718 struct qlcnic_host_sds_ring *sds_ring;
719 struct qlcnic_host_tx_ring *tx_ring;
722 recv_ctx = adapter->recv_ctx;
724 for (ring = 0; ring < adapter->drv_tx_rings; ring++) {
725 tx_ring = &adapter->tx_ring[ring];
726 if (tx_ring->hw_consumer != NULL) {
727 dma_free_coherent(&adapter->pdev->dev, sizeof(u32),
728 tx_ring->hw_consumer,
729 tx_ring->hw_cons_phys_addr);
731 tx_ring->hw_consumer = NULL;
734 if (tx_ring->desc_head != NULL) {
735 dma_free_coherent(&adapter->pdev->dev,
736 TX_DESC_RINGSIZE(tx_ring),
739 tx_ring->desc_head = NULL;
743 for (ring = 0; ring < adapter->max_rds_rings; ring++) {
744 rds_ring = &recv_ctx->rds_rings[ring];
746 if (rds_ring->desc_head != NULL) {
747 dma_free_coherent(&adapter->pdev->dev,
748 RCV_DESC_RINGSIZE(rds_ring),
750 rds_ring->phys_addr);
751 rds_ring->desc_head = NULL;
755 for (ring = 0; ring < adapter->drv_sds_rings; ring++) {
756 sds_ring = &recv_ctx->sds_rings[ring];
758 if (sds_ring->desc_head != NULL) {
759 dma_free_coherent(&adapter->pdev->dev,
760 STATUS_DESC_RINGSIZE(sds_ring),
762 sds_ring->phys_addr);
763 sds_ring->desc_head = NULL;
768 int qlcnic_82xx_config_intrpt(struct qlcnic_adapter *adapter, u8 op_type)
770 struct qlcnic_hardware_context *ahw = adapter->ahw;
771 struct net_device *netdev = adapter->netdev;
772 struct qlcnic_cmd_args cmd;
776 for (i = 0; i < ahw->num_msix; i++) {
777 qlcnic_alloc_mbx_args(&cmd, adapter,
778 QLCNIC_CMD_MQ_TX_CONFIG_INTR);
779 type = op_type ? QLCNIC_INTRPT_ADD : QLCNIC_INTRPT_DEL;
780 val = type | (ahw->intr_tbl[i].type << 4);
781 if (ahw->intr_tbl[i].type == QLCNIC_INTRPT_MSIX)
782 val |= (ahw->intr_tbl[i].id << 16);
783 cmd.req.arg[1] = val;
784 err = qlcnic_issue_cmd(adapter, &cmd);
786 netdev_err(netdev, "Failed to %s interrupts %d\n",
787 op_type == QLCNIC_INTRPT_ADD ? "Add" :
789 qlcnic_free_mbx_args(&cmd);
792 val = cmd.rsp.arg[1];
795 "failed to configure interrupt for %d\n",
796 ahw->intr_tbl[i].id);
800 ahw->intr_tbl[i].id = MSW(val);
801 ahw->intr_tbl[i].enabled = 1;
802 ahw->intr_tbl[i].src = cmd.rsp.arg[2];
804 ahw->intr_tbl[i].id = i;
805 ahw->intr_tbl[i].enabled = 0;
806 ahw->intr_tbl[i].src = 0;
808 qlcnic_free_mbx_args(&cmd);
814 int qlcnic_82xx_get_mac_address(struct qlcnic_adapter *adapter, u8 *mac,
818 struct qlcnic_cmd_args cmd;
819 u32 mac_low, mac_high;
821 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_MAC_ADDRESS);
825 cmd.req.arg[1] = function | BIT_8;
826 err = qlcnic_issue_cmd(adapter, &cmd);
828 if (err == QLCNIC_RCODE_SUCCESS) {
829 mac_low = cmd.rsp.arg[1];
830 mac_high = cmd.rsp.arg[2];
832 for (i = 0; i < 2; i++)
833 mac[i] = (u8) (mac_high >> ((1 - i) * 8));
834 for (i = 2; i < 6; i++)
835 mac[i] = (u8) (mac_low >> ((5 - i) * 8));
837 dev_err(&adapter->pdev->dev,
838 "Failed to get mac address%d\n", err);
841 qlcnic_free_mbx_args(&cmd);
845 /* Get info of a NIC partition */
846 int qlcnic_82xx_get_nic_info(struct qlcnic_adapter *adapter,
847 struct qlcnic_info *npar_info, u8 func_id)
850 dma_addr_t nic_dma_t;
851 const struct qlcnic_info_le *nic_info;
853 struct qlcnic_cmd_args cmd;
854 size_t nic_size = sizeof(struct qlcnic_info_le);
856 nic_info_addr = dma_zalloc_coherent(&adapter->pdev->dev, nic_size,
857 &nic_dma_t, GFP_KERNEL);
861 nic_info = nic_info_addr;
863 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_NIC_INFO);
867 cmd.req.arg[1] = MSD(nic_dma_t);
868 cmd.req.arg[2] = LSD(nic_dma_t);
869 cmd.req.arg[3] = (func_id << 16 | nic_size);
870 err = qlcnic_issue_cmd(adapter, &cmd);
871 if (err != QLCNIC_RCODE_SUCCESS) {
872 dev_err(&adapter->pdev->dev,
873 "Failed to get nic info%d\n", err);
876 npar_info->pci_func = le16_to_cpu(nic_info->pci_func);
877 npar_info->op_mode = le16_to_cpu(nic_info->op_mode);
878 npar_info->min_tx_bw = le16_to_cpu(nic_info->min_tx_bw);
879 npar_info->max_tx_bw = le16_to_cpu(nic_info->max_tx_bw);
880 npar_info->phys_port = le16_to_cpu(nic_info->phys_port);
881 npar_info->switch_mode = le16_to_cpu(nic_info->switch_mode);
882 npar_info->max_tx_ques = le16_to_cpu(nic_info->max_tx_ques);
883 npar_info->max_rx_ques = le16_to_cpu(nic_info->max_rx_ques);
884 npar_info->capabilities = le32_to_cpu(nic_info->capabilities);
885 npar_info->max_mtu = le16_to_cpu(nic_info->max_mtu);
888 qlcnic_free_mbx_args(&cmd);
890 dma_free_coherent(&adapter->pdev->dev, nic_size, nic_info_addr,
896 /* Configure a NIC partition */
897 int qlcnic_82xx_set_nic_info(struct qlcnic_adapter *adapter,
898 struct qlcnic_info *nic)
901 dma_addr_t nic_dma_t;
903 struct qlcnic_cmd_args cmd;
904 struct qlcnic_info_le *nic_info;
905 size_t nic_size = sizeof(struct qlcnic_info_le);
907 if (adapter->ahw->op_mode != QLCNIC_MGMT_FUNC)
910 nic_info_addr = dma_zalloc_coherent(&adapter->pdev->dev, nic_size,
911 &nic_dma_t, GFP_KERNEL);
915 nic_info = nic_info_addr;
917 nic_info->pci_func = cpu_to_le16(nic->pci_func);
918 nic_info->op_mode = cpu_to_le16(nic->op_mode);
919 nic_info->phys_port = cpu_to_le16(nic->phys_port);
920 nic_info->switch_mode = cpu_to_le16(nic->switch_mode);
921 nic_info->capabilities = cpu_to_le32(nic->capabilities);
922 nic_info->max_mac_filters = nic->max_mac_filters;
923 nic_info->max_tx_ques = cpu_to_le16(nic->max_tx_ques);
924 nic_info->max_rx_ques = cpu_to_le16(nic->max_rx_ques);
925 nic_info->min_tx_bw = cpu_to_le16(nic->min_tx_bw);
926 nic_info->max_tx_bw = cpu_to_le16(nic->max_tx_bw);
928 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_SET_NIC_INFO);
932 cmd.req.arg[1] = MSD(nic_dma_t);
933 cmd.req.arg[2] = LSD(nic_dma_t);
934 cmd.req.arg[3] = ((nic->pci_func << 16) | nic_size);
935 err = qlcnic_issue_cmd(adapter, &cmd);
937 if (err != QLCNIC_RCODE_SUCCESS) {
938 dev_err(&adapter->pdev->dev,
939 "Failed to set nic info%d\n", err);
943 qlcnic_free_mbx_args(&cmd);
945 dma_free_coherent(&adapter->pdev->dev, nic_size, nic_info_addr,
951 /* Get PCI Info of a partition */
952 int qlcnic_82xx_get_pci_info(struct qlcnic_adapter *adapter,
953 struct qlcnic_pci_info *pci_info)
955 struct qlcnic_hardware_context *ahw = adapter->ahw;
956 size_t npar_size = sizeof(struct qlcnic_pci_info_le);
957 size_t pci_size = npar_size * ahw->max_vnic_func;
958 u16 nic = 0, fcoe = 0, iscsi = 0;
959 struct qlcnic_pci_info_le *npar;
960 struct qlcnic_cmd_args cmd;
961 dma_addr_t pci_info_dma_t;
965 pci_info_addr = dma_zalloc_coherent(&adapter->pdev->dev, pci_size,
966 &pci_info_dma_t, GFP_KERNEL);
970 npar = pci_info_addr;
971 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_PCI_INFO);
975 cmd.req.arg[1] = MSD(pci_info_dma_t);
976 cmd.req.arg[2] = LSD(pci_info_dma_t);
977 cmd.req.arg[3] = pci_size;
978 err = qlcnic_issue_cmd(adapter, &cmd);
980 ahw->total_nic_func = 0;
981 if (err == QLCNIC_RCODE_SUCCESS) {
982 for (i = 0; i < ahw->max_vnic_func; i++, npar++, pci_info++) {
983 pci_info->id = le16_to_cpu(npar->id);
984 pci_info->active = le16_to_cpu(npar->active);
985 if (!pci_info->active)
987 pci_info->type = le16_to_cpu(npar->type);
988 err = qlcnic_get_pci_func_type(adapter, pci_info->type,
989 &nic, &fcoe, &iscsi);
990 pci_info->default_port =
991 le16_to_cpu(npar->default_port);
992 pci_info->tx_min_bw =
993 le16_to_cpu(npar->tx_min_bw);
994 pci_info->tx_max_bw =
995 le16_to_cpu(npar->tx_max_bw);
996 memcpy(pci_info->mac, npar->mac, ETH_ALEN);
999 dev_err(&adapter->pdev->dev,
1000 "Failed to get PCI Info%d\n", err);
1004 ahw->total_nic_func = nic;
1005 ahw->total_pci_func = nic + fcoe + iscsi;
1006 if (ahw->total_nic_func == 0 || ahw->total_pci_func == 0) {
1007 dev_err(&adapter->pdev->dev,
1008 "%s: Invalid function count: total nic func[%x], total pci func[%x]\n",
1009 __func__, ahw->total_nic_func, ahw->total_pci_func);
1012 qlcnic_free_mbx_args(&cmd);
1014 dma_free_coherent(&adapter->pdev->dev, pci_size, pci_info_addr,
1020 /* Configure eSwitch for port mirroring */
1021 int qlcnic_config_port_mirroring(struct qlcnic_adapter *adapter, u8 id,
1022 u8 enable_mirroring, u8 pci_func)
1024 struct device *dev = &adapter->pdev->dev;
1025 struct qlcnic_cmd_args cmd;
1029 if (adapter->ahw->op_mode != QLCNIC_MGMT_FUNC ||
1030 !(adapter->eswitch[id].flags & QLCNIC_SWITCH_ENABLE)) {
1031 dev_err(&adapter->pdev->dev, "%s: Not a management function\n",
1036 arg1 = id | (enable_mirroring ? BIT_4 : 0);
1037 arg1 |= pci_func << 8;
1039 err = qlcnic_alloc_mbx_args(&cmd, adapter,
1040 QLCNIC_CMD_SET_PORTMIRRORING);
1044 cmd.req.arg[1] = arg1;
1045 err = qlcnic_issue_cmd(adapter, &cmd);
1047 if (err != QLCNIC_RCODE_SUCCESS)
1048 dev_err(dev, "Failed to configure port mirroring for vNIC function %d on eSwitch %d\n",
1051 dev_info(dev, "Configured port mirroring for vNIC function %d on eSwitch %d\n",
1053 qlcnic_free_mbx_args(&cmd);
1058 int qlcnic_get_port_stats(struct qlcnic_adapter *adapter, const u8 func,
1059 const u8 rx_tx, struct __qlcnic_esw_statistics *esw_stats) {
1061 size_t stats_size = sizeof(struct qlcnic_esw_stats_le);
1062 struct qlcnic_esw_stats_le *stats;
1063 dma_addr_t stats_dma_t;
1066 struct qlcnic_cmd_args cmd;
1069 if (esw_stats == NULL)
1072 if ((adapter->ahw->op_mode != QLCNIC_MGMT_FUNC) &&
1073 (func != adapter->ahw->pci_func)) {
1074 dev_err(&adapter->pdev->dev,
1075 "Not privilege to query stats for func=%d", func);
1079 stats_addr = dma_zalloc_coherent(&adapter->pdev->dev, stats_size,
1080 &stats_dma_t, GFP_KERNEL);
1084 arg1 = func | QLCNIC_STATS_VERSION << 8 | QLCNIC_STATS_PORT << 12;
1085 arg1 |= rx_tx << 15 | stats_size << 16;
1087 err = qlcnic_alloc_mbx_args(&cmd, adapter,
1088 QLCNIC_CMD_GET_ESWITCH_STATS);
1092 cmd.req.arg[1] = arg1;
1093 cmd.req.arg[2] = MSD(stats_dma_t);
1094 cmd.req.arg[3] = LSD(stats_dma_t);
1095 err = qlcnic_issue_cmd(adapter, &cmd);
1099 esw_stats->context_id = le16_to_cpu(stats->context_id);
1100 esw_stats->version = le16_to_cpu(stats->version);
1101 esw_stats->size = le16_to_cpu(stats->size);
1102 esw_stats->multicast_frames =
1103 le64_to_cpu(stats->multicast_frames);
1104 esw_stats->broadcast_frames =
1105 le64_to_cpu(stats->broadcast_frames);
1106 esw_stats->unicast_frames = le64_to_cpu(stats->unicast_frames);
1107 esw_stats->dropped_frames = le64_to_cpu(stats->dropped_frames);
1108 esw_stats->local_frames = le64_to_cpu(stats->local_frames);
1109 esw_stats->errors = le64_to_cpu(stats->errors);
1110 esw_stats->numbytes = le64_to_cpu(stats->numbytes);
1113 qlcnic_free_mbx_args(&cmd);
1115 dma_free_coherent(&adapter->pdev->dev, stats_size, stats_addr,
1121 /* This routine will retrieve the MAC statistics from firmware */
1122 int qlcnic_get_mac_stats(struct qlcnic_adapter *adapter,
1123 struct qlcnic_mac_statistics *mac_stats)
1125 struct qlcnic_mac_statistics_le *stats;
1126 struct qlcnic_cmd_args cmd;
1127 size_t stats_size = sizeof(struct qlcnic_mac_statistics_le);
1128 dma_addr_t stats_dma_t;
1132 if (mac_stats == NULL)
1135 stats_addr = dma_zalloc_coherent(&adapter->pdev->dev, stats_size,
1136 &stats_dma_t, GFP_KERNEL);
1140 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_MAC_STATS);
1144 cmd.req.arg[1] = stats_size << 16;
1145 cmd.req.arg[2] = MSD(stats_dma_t);
1146 cmd.req.arg[3] = LSD(stats_dma_t);
1147 err = qlcnic_issue_cmd(adapter, &cmd);
1150 mac_stats->mac_tx_frames = le64_to_cpu(stats->mac_tx_frames);
1151 mac_stats->mac_tx_bytes = le64_to_cpu(stats->mac_tx_bytes);
1152 mac_stats->mac_tx_mcast_pkts =
1153 le64_to_cpu(stats->mac_tx_mcast_pkts);
1154 mac_stats->mac_tx_bcast_pkts =
1155 le64_to_cpu(stats->mac_tx_bcast_pkts);
1156 mac_stats->mac_rx_frames = le64_to_cpu(stats->mac_rx_frames);
1157 mac_stats->mac_rx_bytes = le64_to_cpu(stats->mac_rx_bytes);
1158 mac_stats->mac_rx_mcast_pkts =
1159 le64_to_cpu(stats->mac_rx_mcast_pkts);
1160 mac_stats->mac_rx_length_error =
1161 le64_to_cpu(stats->mac_rx_length_error);
1162 mac_stats->mac_rx_length_small =
1163 le64_to_cpu(stats->mac_rx_length_small);
1164 mac_stats->mac_rx_length_large =
1165 le64_to_cpu(stats->mac_rx_length_large);
1166 mac_stats->mac_rx_jabber = le64_to_cpu(stats->mac_rx_jabber);
1167 mac_stats->mac_rx_dropped = le64_to_cpu(stats->mac_rx_dropped);
1168 mac_stats->mac_rx_crc_error = le64_to_cpu(stats->mac_rx_crc_error);
1170 dev_err(&adapter->pdev->dev,
1171 "%s: Get mac stats failed, err=%d.\n", __func__, err);
1174 qlcnic_free_mbx_args(&cmd);
1177 dma_free_coherent(&adapter->pdev->dev, stats_size, stats_addr,
1183 int qlcnic_get_eswitch_stats(struct qlcnic_adapter *adapter, const u8 eswitch,
1184 const u8 rx_tx, struct __qlcnic_esw_statistics *esw_stats) {
1186 struct __qlcnic_esw_statistics port_stats;
1190 if (esw_stats == NULL)
1192 if (adapter->ahw->op_mode != QLCNIC_MGMT_FUNC)
1194 if (adapter->npars == NULL)
1197 memset(esw_stats, 0, sizeof(u64));
1198 esw_stats->unicast_frames = QLCNIC_STATS_NOT_AVAIL;
1199 esw_stats->multicast_frames = QLCNIC_STATS_NOT_AVAIL;
1200 esw_stats->broadcast_frames = QLCNIC_STATS_NOT_AVAIL;
1201 esw_stats->dropped_frames = QLCNIC_STATS_NOT_AVAIL;
1202 esw_stats->errors = QLCNIC_STATS_NOT_AVAIL;
1203 esw_stats->local_frames = QLCNIC_STATS_NOT_AVAIL;
1204 esw_stats->numbytes = QLCNIC_STATS_NOT_AVAIL;
1205 esw_stats->context_id = eswitch;
1207 for (i = 0; i < adapter->ahw->total_nic_func; i++) {
1208 if (adapter->npars[i].phy_port != eswitch)
1211 memset(&port_stats, 0, sizeof(struct __qlcnic_esw_statistics));
1212 if (qlcnic_get_port_stats(adapter, adapter->npars[i].pci_func,
1213 rx_tx, &port_stats))
1216 esw_stats->size = port_stats.size;
1217 esw_stats->version = port_stats.version;
1218 QLCNIC_ADD_ESW_STATS(esw_stats->unicast_frames,
1219 port_stats.unicast_frames);
1220 QLCNIC_ADD_ESW_STATS(esw_stats->multicast_frames,
1221 port_stats.multicast_frames);
1222 QLCNIC_ADD_ESW_STATS(esw_stats->broadcast_frames,
1223 port_stats.broadcast_frames);
1224 QLCNIC_ADD_ESW_STATS(esw_stats->dropped_frames,
1225 port_stats.dropped_frames);
1226 QLCNIC_ADD_ESW_STATS(esw_stats->errors,
1228 QLCNIC_ADD_ESW_STATS(esw_stats->local_frames,
1229 port_stats.local_frames);
1230 QLCNIC_ADD_ESW_STATS(esw_stats->numbytes,
1231 port_stats.numbytes);
1237 int qlcnic_clear_esw_stats(struct qlcnic_adapter *adapter, const u8 func_esw,
1238 const u8 port, const u8 rx_tx)
1240 struct qlcnic_hardware_context *ahw = adapter->ahw;
1241 struct qlcnic_cmd_args cmd;
1245 if (ahw->op_mode != QLCNIC_MGMT_FUNC)
1248 if (func_esw == QLCNIC_STATS_PORT) {
1249 if (port >= ahw->max_vnic_func)
1251 } else if (func_esw == QLCNIC_STATS_ESWITCH) {
1252 if (port >= QLCNIC_NIU_MAX_XG_PORTS)
1258 if (rx_tx > QLCNIC_QUERY_TX_COUNTER)
1261 arg1 = port | QLCNIC_STATS_VERSION << 8 | func_esw << 12;
1262 arg1 |= BIT_14 | rx_tx << 15;
1264 err = qlcnic_alloc_mbx_args(&cmd, adapter,
1265 QLCNIC_CMD_GET_ESWITCH_STATS);
1269 cmd.req.arg[1] = arg1;
1270 err = qlcnic_issue_cmd(adapter, &cmd);
1271 qlcnic_free_mbx_args(&cmd);
1275 dev_err(&adapter->pdev->dev,
1276 "Invalid args func_esw %d port %d rx_ctx %d\n",
1277 func_esw, port, rx_tx);
1281 static int __qlcnic_get_eswitch_port_config(struct qlcnic_adapter *adapter,
1282 u32 *arg1, u32 *arg2)
1284 struct device *dev = &adapter->pdev->dev;
1285 struct qlcnic_cmd_args cmd;
1286 u8 pci_func = *arg1 >> 8;
1289 err = qlcnic_alloc_mbx_args(&cmd, adapter,
1290 QLCNIC_CMD_GET_ESWITCH_PORT_CONFIG);
1294 cmd.req.arg[1] = *arg1;
1295 err = qlcnic_issue_cmd(adapter, &cmd);
1296 *arg1 = cmd.rsp.arg[1];
1297 *arg2 = cmd.rsp.arg[2];
1298 qlcnic_free_mbx_args(&cmd);
1300 if (err == QLCNIC_RCODE_SUCCESS)
1301 dev_info(dev, "Get eSwitch port config for vNIC function %d\n",
1304 dev_err(dev, "Failed to get eswitch port config for vNIC function %d\n",
1308 /* Configure eSwitch port
1309 op_mode = 0 for setting default port behavior
1310 op_mode = 1 for setting vlan id
1311 op_mode = 2 for deleting vlan id
1312 op_type = 0 for vlan_id
1313 op_type = 1 for port vlan_id
1315 int qlcnic_config_switch_port(struct qlcnic_adapter *adapter,
1316 struct qlcnic_esw_func_cfg *esw_cfg)
1318 struct device *dev = &adapter->pdev->dev;
1319 struct qlcnic_cmd_args cmd;
1320 int err = -EIO, index;
1324 if (adapter->ahw->op_mode != QLCNIC_MGMT_FUNC) {
1325 dev_err(&adapter->pdev->dev, "%s: Not a management function\n",
1330 pci_func = esw_cfg->pci_func;
1331 index = qlcnic_is_valid_nic_func(adapter, pci_func);
1334 arg1 = (adapter->npars[index].phy_port & BIT_0);
1335 arg1 |= (pci_func << 8);
1337 if (__qlcnic_get_eswitch_port_config(adapter, &arg1, &arg2))
1339 arg1 &= ~(0x0ff << 8);
1340 arg1 |= (pci_func << 8);
1341 arg1 &= ~(BIT_2 | BIT_3);
1342 switch (esw_cfg->op_mode) {
1343 case QLCNIC_PORT_DEFAULTS:
1344 arg1 |= (BIT_4 | BIT_6 | BIT_7);
1345 arg2 |= (BIT_0 | BIT_1);
1346 if (adapter->ahw->capabilities & QLCNIC_FW_CAPABILITY_TSO)
1347 arg2 |= (BIT_2 | BIT_3);
1348 if (!(esw_cfg->discard_tagged))
1350 if (!(esw_cfg->promisc_mode))
1352 if (!(esw_cfg->mac_override))
1354 if (!(esw_cfg->mac_anti_spoof))
1356 if (!(esw_cfg->offload_flags & BIT_0))
1357 arg2 &= ~(BIT_1 | BIT_2 | BIT_3);
1358 if (!(esw_cfg->offload_flags & BIT_1))
1360 if (!(esw_cfg->offload_flags & BIT_2))
1363 case QLCNIC_ADD_VLAN:
1364 arg1 &= ~(0x0ffff << 16);
1365 arg1 |= (BIT_2 | BIT_5);
1366 arg1 |= (esw_cfg->vlan_id << 16);
1368 case QLCNIC_DEL_VLAN:
1369 arg1 |= (BIT_3 | BIT_5);
1370 arg1 &= ~(0x0ffff << 16);
1373 dev_err(&adapter->pdev->dev, "%s: Invalid opmode 0x%x\n",
1374 __func__, esw_cfg->op_mode);
1378 err = qlcnic_alloc_mbx_args(&cmd, adapter,
1379 QLCNIC_CMD_CONFIGURE_ESWITCH);
1383 cmd.req.arg[1] = arg1;
1384 cmd.req.arg[2] = arg2;
1385 err = qlcnic_issue_cmd(adapter, &cmd);
1386 qlcnic_free_mbx_args(&cmd);
1388 if (err != QLCNIC_RCODE_SUCCESS)
1389 dev_err(dev, "Failed to configure eswitch for vNIC function %d\n",
1392 dev_info(dev, "Configured eSwitch for vNIC function %d\n",
1399 qlcnic_get_eswitch_port_config(struct qlcnic_adapter *adapter,
1400 struct qlcnic_esw_func_cfg *esw_cfg)
1406 if (adapter->ahw->op_mode == QLCNIC_MGMT_FUNC) {
1407 index = qlcnic_is_valid_nic_func(adapter, esw_cfg->pci_func);
1410 phy_port = adapter->npars[index].phy_port;
1412 phy_port = adapter->ahw->physical_port;
1415 arg1 |= (esw_cfg->pci_func << 8);
1416 if (__qlcnic_get_eswitch_port_config(adapter, &arg1, &arg2))
1419 esw_cfg->discard_tagged = !!(arg1 & BIT_4);
1420 esw_cfg->host_vlan_tag = !!(arg1 & BIT_5);
1421 esw_cfg->promisc_mode = !!(arg1 & BIT_6);
1422 esw_cfg->mac_override = !!(arg1 & BIT_7);
1423 esw_cfg->vlan_id = LSW(arg1 >> 16);
1424 esw_cfg->mac_anti_spoof = (arg2 & 0x1);
1425 esw_cfg->offload_flags = ((arg2 >> 1) & 0x7);