drivers/net/ethernet/qlogic/qlcnic/qlcnic_hw.c

   1 /*
   2  * QLogic qlcnic NIC Driver
   3  * Copyright (c) 2009-2013 QLogic Corporation
   4  *
   5  * See LICENSE.qlcnic for copyright and licensing details.
   6  */
   7
   8 #include "qlcnic.h"
   9 #include "qlcnic_hdr.h"
  10
  11 #include <linux/slab.h>
  12 #include <net/ip.h>
  13 #include <linux/bitops.h>
  14
  15 #define MASK(n) ((1ULL<<(n))-1)
  16 #define OCM_WIN_P3P(addr) (addr & 0xffc0000)
  17
  18 #define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
  19
  20 #define CRB_BLK(off)    ((off >> 20) & 0x3f)
  21 #define CRB_SUBBLK(off) ((off >> 16) & 0xf)
  22 #define CRB_WINDOW_2M   (0x130060)
  23 #define CRB_HI(off)     ((crb_hub_agt[CRB_BLK(off)] << 20) | ((off) & 0xf0000))
  24 #define CRB_INDIRECT_2M (0x1e0000UL)
  25
  26 struct qlcnic_ms_reg_ctrl {
  27         u32 ocm_window;
  28         u32 control;
  29         u32 hi;
  30         u32 low;
  31         u32 rd[4];
  32         u32 wd[4];
  33         u64 off;
  34 };
  35
  36 #ifndef readq
  37 static inline u64 readq(void __iomem *addr)
  38 {
  39         return readl(addr) | (((u64) readl(addr + 4)) << 32LL);
  40 }
  41 #endif
  42
  43 #ifndef writeq
  44 static inline void writeq(u64 val, void __iomem *addr)
  45 {
  46         writel(((u32) (val)), (addr));
  47         writel(((u32) (val >> 32)), (addr + 4));
  48 }
  49 #endif
  50
  51 static struct crb_128M_2M_block_map
  52 crb_128M_2M_map[64] __cacheline_aligned_in_smp = {
  53     {{{0, 0,         0,         0} } },         /* 0: PCI */
  54     {{{1, 0x0100000, 0x0102000, 0x120000},      /* 1: PCIE */
  55           {1, 0x0110000, 0x0120000, 0x130000},
  56           {1, 0x0120000, 0x0122000, 0x124000},
  57           {1, 0x0130000, 0x0132000, 0x126000},
  58           {1, 0x0140000, 0x0142000, 0x128000},
  59           {1, 0x0150000, 0x0152000, 0x12a000},
  60           {1, 0x0160000, 0x0170000, 0x110000},
  61           {1, 0x0170000, 0x0172000, 0x12e000},
  62           {0, 0x0000000, 0x0000000, 0x000000},
  63           {0, 0x0000000, 0x0000000, 0x000000},
  64           {0, 0x0000000, 0x0000000, 0x000000},
  65           {0, 0x0000000, 0x0000000, 0x000000},
  66           {0, 0x0000000, 0x0000000, 0x000000},
  67           {0, 0x0000000, 0x0000000, 0x000000},
  68           {1, 0x01e0000, 0x01e0800, 0x122000},
  69           {0, 0x0000000, 0x0000000, 0x000000} } },
  70         {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */
  71     {{{0, 0,         0,         0} } },     /* 3: */
  72     {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */
  73     {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE   */
  74     {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU   */
  75     {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM    */
  76     {{{1, 0x0800000, 0x0802000, 0x170000},  /* 8: SQM0  */
  77       {0, 0x0000000, 0x0000000, 0x000000},
  78       {0, 0x0000000, 0x0000000, 0x000000},
  79       {0, 0x0000000, 0x0000000, 0x000000},
  80       {0, 0x0000000, 0x0000000, 0x000000},
  81       {0, 0x0000000, 0x0000000, 0x000000},
  82       {0, 0x0000000, 0x0000000, 0x000000},
  83       {0, 0x0000000, 0x0000000, 0x000000},
  84       {0, 0x0000000, 0x0000000, 0x000000},
  85       {0, 0x0000000, 0x0000000, 0x000000},
  86       {0, 0x0000000, 0x0000000, 0x000000},
  87       {0, 0x0000000, 0x0000000, 0x000000},
  88       {0, 0x0000000, 0x0000000, 0x000000},
  89       {0, 0x0000000, 0x0000000, 0x000000},
  90       {0, 0x0000000, 0x0000000, 0x000000},
  91       {1, 0x08f0000, 0x08f2000, 0x172000} } },
  92     {{{1, 0x0900000, 0x0902000, 0x174000},      /* 9: SQM1*/
  93       {0, 0x0000000, 0x0000000, 0x000000},
  94       {0, 0x0000000, 0x0000000, 0x000000},
  95       {0, 0x0000000, 0x0000000, 0x000000},
  96       {0, 0x0000000, 0x0000000, 0x000000},
  97       {0, 0x0000000, 0x0000000, 0x000000},
  98       {0, 0x0000000, 0x0000000, 0x000000},
  99       {0, 0x0000000, 0x0000000, 0x000000},
 100       {0, 0x0000000, 0x0000000, 0x000000},
 101       {0, 0x0000000, 0x0000000, 0x000000},
 102       {0, 0x0000000, 0x0000000, 0x000000},
 103       {0, 0x0000000, 0x0000000, 0x000000},
 104       {0, 0x0000000, 0x0000000, 0x000000},
 105       {0, 0x0000000, 0x0000000, 0x000000},
 106       {0, 0x0000000, 0x0000000, 0x000000},
 107       {1, 0x09f0000, 0x09f2000, 0x176000} } },
 108     {{{0, 0x0a00000, 0x0a02000, 0x178000},      /* 10: SQM2*/
 109       {0, 0x0000000, 0x0000000, 0x000000},
 110       {0, 0x0000000, 0x0000000, 0x000000},
 111       {0, 0x0000000, 0x0000000, 0x000000},
 112       {0, 0x0000000, 0x0000000, 0x000000},
 113       {0, 0x0000000, 0x0000000, 0x000000},
 114       {0, 0x0000000, 0x0000000, 0x000000},
 115       {0, 0x0000000, 0x0000000, 0x000000},
 116       {0, 0x0000000, 0x0000000, 0x000000},
 117       {0, 0x0000000, 0x0000000, 0x000000},
 118       {0, 0x0000000, 0x0000000, 0x000000},
 119       {0, 0x0000000, 0x0000000, 0x000000},
 120       {0, 0x0000000, 0x0000000, 0x000000},
 121       {0, 0x0000000, 0x0000000, 0x000000},
 122       {0, 0x0000000, 0x0000000, 0x000000},
 123       {1, 0x0af0000, 0x0af2000, 0x17a000} } },
 124     {{{0, 0x0b00000, 0x0b02000, 0x17c000},      /* 11: SQM3*/
 125       {0, 0x0000000, 0x0000000, 0x000000},
 126       {0, 0x0000000, 0x0000000, 0x000000},
 127       {0, 0x0000000, 0x0000000, 0x000000},
 128       {0, 0x0000000, 0x0000000, 0x000000},
 129       {0, 0x0000000, 0x0000000, 0x000000},
 130       {0, 0x0000000, 0x0000000, 0x000000},
 131       {0, 0x0000000, 0x0000000, 0x000000},
 132       {0, 0x0000000, 0x0000000, 0x000000},
 133       {0, 0x0000000, 0x0000000, 0x000000},
 134       {0, 0x0000000, 0x0000000, 0x000000},
 135       {0, 0x0000000, 0x0000000, 0x000000},
 136       {0, 0x0000000, 0x0000000, 0x000000},
 137       {0, 0x0000000, 0x0000000, 0x000000},
 138       {0, 0x0000000, 0x0000000, 0x000000},
 139       {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
 140         {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */
 141         {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */
 142         {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */
 143         {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */
 144         {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */
 145         {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */
 146         {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */
 147         {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */
 148         {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */
 149         {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */
 150         {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */
 151         {{{0, 0,         0,         0} } },     /* 23: */
 152         {{{0, 0,         0,         0} } },     /* 24: */
 153         {{{0, 0,         0,         0} } },     /* 25: */
 154         {{{0, 0,         0,         0} } },     /* 26: */
 155         {{{0, 0,         0,         0} } },     /* 27: */
 156         {{{0, 0,         0,         0} } },     /* 28: */
 157         {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */
 158     {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */
 159     {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */
 160         {{{0} } },                              /* 32: PCI */
 161         {{{1, 0x2100000, 0x2102000, 0x120000},  /* 33: PCIE */
 162           {1, 0x2110000, 0x2120000, 0x130000},
 163           {1, 0x2120000, 0x2122000, 0x124000},
 164           {1, 0x2130000, 0x2132000, 0x126000},
 165           {1, 0x2140000, 0x2142000, 0x128000},
 166           {1, 0x2150000, 0x2152000, 0x12a000},
 167           {1, 0x2160000, 0x2170000, 0x110000},
 168           {1, 0x2170000, 0x2172000, 0x12e000},
 169           {0, 0x0000000, 0x0000000, 0x000000},
 170           {0, 0x0000000, 0x0000000, 0x000000},
 171           {0, 0x0000000, 0x0000000, 0x000000},
 172           {0, 0x0000000, 0x0000000, 0x000000},
 173           {0, 0x0000000, 0x0000000, 0x000000},
 174           {0, 0x0000000, 0x0000000, 0x000000},
 175           {0, 0x0000000, 0x0000000, 0x000000},
 176           {0, 0x0000000, 0x0000000, 0x000000} } },
 177         {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */
 178         {{{0} } },                              /* 35: */
 179         {{{0} } },                              /* 36: */
 180         {{{0} } },                              /* 37: */
 181         {{{0} } },                              /* 38: */
 182         {{{0} } },                              /* 39: */
 183         {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */
 184         {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */
 185         {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */
 186         {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */
 187         {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */
 188         {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */
 189         {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */
 190         {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */
 191         {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */
 192         {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */
 193         {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */
 194         {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */
 195         {{{0} } },                              /* 52: */
 196         {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */
 197         {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */
 198         {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */
 199         {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */
 200         {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */
 201         {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */
 202         {{{0} } },                              /* 59: I2C0 */
 203         {{{0} } },                              /* 60: I2C1 */
 204         {{{1, 0x3d00000, 0x3d04000, 0x1d8000} } },/* 61: LPC */
 205         {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */
 206         {{{1, 0x3f00000, 0x3f01000, 0x168000} } }       /* 63: P2NR0 */
 207 };
 208
 209 /*
 210  * top 12 bits of crb internal address (hub, agent)
 211  */
 212 static const unsigned crb_hub_agt[64] = {
 213         0,
 214         QLCNIC_HW_CRB_HUB_AGT_ADR_PS,
 215         QLCNIC_HW_CRB_HUB_AGT_ADR_MN,
 216         QLCNIC_HW_CRB_HUB_AGT_ADR_MS,
 217         0,
 218         QLCNIC_HW_CRB_HUB_AGT_ADR_SRE,
 219         QLCNIC_HW_CRB_HUB_AGT_ADR_NIU,
 220         QLCNIC_HW_CRB_HUB_AGT_ADR_QMN,
 221         QLCNIC_HW_CRB_HUB_AGT_ADR_SQN0,
 222         QLCNIC_HW_CRB_HUB_AGT_ADR_SQN1,
 223         QLCNIC_HW_CRB_HUB_AGT_ADR_SQN2,
 224         QLCNIC_HW_CRB_HUB_AGT_ADR_SQN3,
 225         QLCNIC_HW_CRB_HUB_AGT_ADR_I2Q,
 226         QLCNIC_HW_CRB_HUB_AGT_ADR_TIMR,
 227         QLCNIC_HW_CRB_HUB_AGT_ADR_ROMUSB,
 228         QLCNIC_HW_CRB_HUB_AGT_ADR_PGN4,
 229         QLCNIC_HW_CRB_HUB_AGT_ADR_XDMA,
 230         QLCNIC_HW_CRB_HUB_AGT_ADR_PGN0,
 231         QLCNIC_HW_CRB_HUB_AGT_ADR_PGN1,
 232         QLCNIC_HW_CRB_HUB_AGT_ADR_PGN2,
 233         QLCNIC_HW_CRB_HUB_AGT_ADR_PGN3,
 234         QLCNIC_HW_CRB_HUB_AGT_ADR_PGND,
 235         QLCNIC_HW_CRB_HUB_AGT_ADR_PGNI,
 236         QLCNIC_HW_CRB_HUB_AGT_ADR_PGS0,
 237         QLCNIC_HW_CRB_HUB_AGT_ADR_PGS1,
 238         QLCNIC_HW_CRB_HUB_AGT_ADR_PGS2,
 239         QLCNIC_HW_CRB_HUB_AGT_ADR_PGS3,
 240         0,
 241         QLCNIC_HW_CRB_HUB_AGT_ADR_PGSI,
 242         QLCNIC_HW_CRB_HUB_AGT_ADR_SN,
 243         0,
 244         QLCNIC_HW_CRB_HUB_AGT_ADR_EG,
 245         0,
 246         QLCNIC_HW_CRB_HUB_AGT_ADR_PS,
 247         QLCNIC_HW_CRB_HUB_AGT_ADR_CAM,
 248         0,
 249         0,
 250         0,
 251         0,
 252         0,
 253         QLCNIC_HW_CRB_HUB_AGT_ADR_TIMR,
 254         0,
 255         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX1,
 256         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX2,
 257         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX3,
 258         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX4,
 259         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX5,
 260         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX6,
 261         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX7,
 262         QLCNIC_HW_CRB_HUB_AGT_ADR_XDMA,
 263         QLCNIC_HW_CRB_HUB_AGT_ADR_I2Q,
 264         QLCNIC_HW_CRB_HUB_AGT_ADR_ROMUSB,
 265         0,
 266         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX0,
 267         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX8,
 268         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX9,
 269         QLCNIC_HW_CRB_HUB_AGT_ADR_OCM0,
 270         0,
 271         QLCNIC_HW_CRB_HUB_AGT_ADR_SMB,
 272         QLCNIC_HW_CRB_HUB_AGT_ADR_I2C0,
 273         QLCNIC_HW_CRB_HUB_AGT_ADR_I2C1,
 274         0,
 275         QLCNIC_HW_CRB_HUB_AGT_ADR_PGNC,
 276         0,
 277 };
 278
 279 static const u32 msi_tgt_status[8] = {
 280         ISR_INT_TARGET_STATUS, ISR_INT_TARGET_STATUS_F1,
 281         ISR_INT_TARGET_STATUS_F2, ISR_INT_TARGET_STATUS_F3,
 282         ISR_INT_TARGET_STATUS_F4, ISR_INT_TARGET_STATUS_F5,
 283         ISR_INT_TARGET_STATUS_F6, ISR_INT_TARGET_STATUS_F7
 284 };
 285
 286 /*  PCI Windowing for DDR regions.  */
 287
 288 #define QLCNIC_PCIE_SEM_TIMEOUT 10000
 289
 290 static void qlcnic_read_window_reg(u32 addr, void __iomem *bar0, u32 *data)
 291 {
 292         u32 dest;
 293         void __iomem *val;
 294
 295         dest = addr & 0xFFFF0000;
 296         val = bar0 + QLCNIC_FW_DUMP_REG1;
 297         writel(dest, val);
 298         readl(val);
 299         val = bar0 + QLCNIC_FW_DUMP_REG2 + LSW(addr);
 300         *data = readl(val);
 301 }
 302
 303 static void qlcnic_write_window_reg(u32 addr, void __iomem *bar0, u32 data)
 304 {
 305         u32 dest;
 306         void __iomem *val;
 307
 308         dest = addr & 0xFFFF0000;
 309         val = bar0 + QLCNIC_FW_DUMP_REG1;
 310         writel(dest, val);
 311         readl(val);
 312         val = bar0 + QLCNIC_FW_DUMP_REG2 + LSW(addr);
 313         writel(data, val);
 314         readl(val);
 315 }
 316
 317 int
 318 qlcnic_pcie_sem_lock(struct qlcnic_adapter *adapter, int sem, u32 id_reg)
 319 {
 320         int timeout = 0;
 321         int err = 0;
 322         u32 done = 0;
 323
 324         while (!done) {
 325                 done = QLCRD32(adapter, QLCNIC_PCIE_REG(PCIE_SEM_LOCK(sem)),
 326                                &err);
 327                 if (done == 1)
 328                         break;
 329                 if (++timeout >= QLCNIC_PCIE_SEM_TIMEOUT) {
 330                         dev_err(&adapter->pdev->dev,
 331                                 "Failed to acquire sem=%d lock; holdby=%d\n",
 332                                 sem,
 333                                 id_reg ? QLCRD32(adapter, id_reg, &err) : -1);
 334                         return -EIO;
 335                 }
 336                 msleep(1);
 337         }
 338
 339         if (id_reg)
 340                 QLCWR32(adapter, id_reg, adapter->portnum);
 341
 342         return 0;
 343 }
 344
 345 void
 346 qlcnic_pcie_sem_unlock(struct qlcnic_adapter *adapter, int sem)
 347 {
 348         int err = 0;
 349
 350         QLCRD32(adapter, QLCNIC_PCIE_REG(PCIE_SEM_UNLOCK(sem)), &err);
 351 }
 352
 353 int qlcnic_ind_rd(struct qlcnic_adapter *adapter, u32 addr)
 354 {
 355         int err = 0;
 356         u32 data;
 357
 358         if (qlcnic_82xx_check(adapter))
 359                 qlcnic_read_window_reg(addr, adapter->ahw->pci_base0, &data);
 360         else {
 361                 data = QLCRD32(adapter, addr, &err);
 362                 if (err == -EIO)
 363                         return err;
 364         }
 365         return data;
 366 }
 367
 368 void qlcnic_ind_wr(struct qlcnic_adapter *adapter, u32 addr, u32 data)
 369 {
 370         if (qlcnic_82xx_check(adapter))
 371                 qlcnic_write_window_reg(addr, adapter->ahw->pci_base0, data);
 372         else
 373                 qlcnic_83xx_wrt_reg_indirect(adapter, addr, data);
 374 }
 375
 376 static int
 377 qlcnic_send_cmd_descs(struct qlcnic_adapter *adapter,
 378                 struct cmd_desc_type0 *cmd_desc_arr, int nr_desc)
 379 {
 380         u32 i, producer;
 381         struct qlcnic_cmd_buffer *pbuf;
 382         struct cmd_desc_type0 *cmd_desc;
 383         struct qlcnic_host_tx_ring *tx_ring;
 384
 385         i = 0;
 386
 387         if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state))
 388                 return -EIO;
 389
 390         tx_ring = &adapter->tx_ring[0];
 391         __netif_tx_lock_bh(tx_ring->txq);
 392
 393         producer = tx_ring->producer;
 394
 395         if (nr_desc >= qlcnic_tx_avail(tx_ring)) {
 396                 netif_tx_stop_queue(tx_ring->txq);
 397                 smp_mb();
 398                 if (qlcnic_tx_avail(tx_ring) > nr_desc) {
 399                         if (qlcnic_tx_avail(tx_ring) > TX_STOP_THRESH)
 400                                 netif_tx_wake_queue(tx_ring->txq);
 401                 } else {
 402                         adapter->stats.xmit_off++;
 403                         __netif_tx_unlock_bh(tx_ring->txq);
 404                         return -EBUSY;
 405                 }
 406         }
 407
 408         do {
 409                 cmd_desc = &cmd_desc_arr[i];
 410
 411                 pbuf = &tx_ring->cmd_buf_arr[producer];
 412                 pbuf->skb = NULL;
 413                 pbuf->frag_count = 0;
 414
 415                 memcpy(&tx_ring->desc_head[producer],
 416                        cmd_desc, sizeof(struct cmd_desc_type0));
 417
 418                 producer = get_next_index(producer, tx_ring->num_desc);
 419                 i++;
 420
 421         } while (i != nr_desc);
 422
 423         tx_ring->producer = producer;
 424
 425         qlcnic_update_cmd_producer(tx_ring);
 426
 427         __netif_tx_unlock_bh(tx_ring->txq);
 428
 429         return 0;
 430 }
 431
 432 int qlcnic_82xx_sre_macaddr_change(struct qlcnic_adapter *adapter, u8 *addr,
 433                                    u16 vlan_id, u8 op)
 434 {
 435         struct qlcnic_nic_req req;
 436         struct qlcnic_mac_req *mac_req;
 437         struct qlcnic_vlan_req *vlan_req;
 438         u64 word;
 439
 440         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 441         req.qhdr = cpu_to_le64(QLCNIC_REQUEST << 23);
 442
 443         word = QLCNIC_MAC_EVENT | ((u64)adapter->portnum << 16);
 444         req.req_hdr = cpu_to_le64(word);
 445
 446         mac_req = (struct qlcnic_mac_req *)&req.words[0];
 447         mac_req->op = op;
 448         memcpy(mac_req->mac_addr, addr, ETH_ALEN);
 449
 450         vlan_req = (struct qlcnic_vlan_req *)&req.words[1];
 451         vlan_req->vlan_id = cpu_to_le16(vlan_id);
 452
 453         return qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 454 }
 455
 456 int qlcnic_nic_del_mac(struct qlcnic_adapter *adapter, const u8 *addr)
 457 {
 458         struct qlcnic_mac_vlan_list *cur;
 459         struct list_head *head;
 460         int err = -EINVAL;
 461
 462         /* Delete MAC from the existing list */
 463         list_for_each(head, &adapter->mac_list) {
 464                 cur = list_entry(head, struct qlcnic_mac_vlan_list, list);
 465                 if (ether_addr_equal(addr, cur->mac_addr)) {
 466                         err = qlcnic_sre_macaddr_change(adapter, cur->mac_addr,
 467                                                         0, QLCNIC_MAC_DEL);
 468                         if (err)
 469                                 return err;
 470                         list_del(&cur->list);
 471                         kfree(cur);
 472                         return err;
 473                 }
 474         }
 475         return err;
 476 }
 477
 478 int qlcnic_nic_add_mac(struct qlcnic_adapter *adapter, const u8 *addr, u16 vlan)
 479 {
 480         struct qlcnic_mac_vlan_list *cur;
 481         struct list_head *head;
 482
 483         /* look up if already exists */
 484         list_for_each(head, &adapter->mac_list) {
 485                 cur = list_entry(head, struct qlcnic_mac_vlan_list, list);
 486                 if (ether_addr_equal(addr, cur->mac_addr) &&
 487                     cur->vlan_id == vlan)
 488                         return 0;
 489         }
 490
 491         cur = kzalloc(sizeof(*cur), GFP_ATOMIC);
 492         if (cur == NULL)
 493                 return -ENOMEM;
 494
 495         memcpy(cur->mac_addr, addr, ETH_ALEN);
 496
 497         if (qlcnic_sre_macaddr_change(adapter,
 498                                 cur->mac_addr, vlan, QLCNIC_MAC_ADD)) {
 499                 kfree(cur);
 500                 return -EIO;
 501         }
 502
 503         cur->vlan_id = vlan;
 504         list_add_tail(&cur->list, &adapter->mac_list);
 505         return 0;
 506 }
 507
 508 static void __qlcnic_set_multi(struct net_device *netdev, u16 vlan)
 509 {
 510         struct qlcnic_adapter *adapter = netdev_priv(netdev);
 511         struct qlcnic_hardware_context *ahw = adapter->ahw;
 512         struct netdev_hw_addr *ha;
 513         static const u8 bcast_addr[ETH_ALEN] = {
 514                 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
 515         };
 516         u32 mode = VPORT_MISS_MODE_DROP;
 517
 518         if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state))
 519                 return;
 520
 521         qlcnic_nic_add_mac(adapter, adapter->mac_addr, vlan);
 522         qlcnic_nic_add_mac(adapter, bcast_addr, vlan);
 523
 524         if (netdev->flags & IFF_PROMISC) {
 525                 if (!(adapter->flags & QLCNIC_PROMISC_DISABLED))
 526                         mode = VPORT_MISS_MODE_ACCEPT_ALL;
 527         } else if ((netdev->flags & IFF_ALLMULTI) ||
 528                    (netdev_mc_count(netdev) > ahw->max_mc_count)) {
 529                 mode = VPORT_MISS_MODE_ACCEPT_MULTI;
 530         } else if (!netdev_mc_empty(netdev)) {
 531                 netdev_for_each_mc_addr(ha, netdev)
 532                         qlcnic_nic_add_mac(adapter, ha->addr, vlan);
 533         }
 534
 535         /* configure unicast MAC address, if there is not sufficient space
 536          * to store all the unicast addresses then enable promiscuous mode
 537          */
 538         if (netdev_uc_count(netdev) > ahw->max_uc_count) {
 539                 mode = VPORT_MISS_MODE_ACCEPT_ALL;
 540         } else if (!netdev_uc_empty(netdev)) {
 541                 netdev_for_each_uc_addr(ha, netdev)
 542                         qlcnic_nic_add_mac(adapter, ha->addr, vlan);
 543         }
 544
 545         if (mode == VPORT_MISS_MODE_ACCEPT_ALL &&
 546             !adapter->fdb_mac_learn) {
 547                 qlcnic_alloc_lb_filters_mem(adapter);
 548                 adapter->drv_mac_learn = 1;
 549                 if (adapter->flags & QLCNIC_ESWITCH_ENABLED)
 550                         adapter->rx_mac_learn = 1;
 551         } else {
 552                 adapter->drv_mac_learn = 0;
 553                 adapter->rx_mac_learn = 0;
 554         }
 555
 556         qlcnic_nic_set_promisc(adapter, mode);
 557 }
 558
 559 void qlcnic_set_multi(struct net_device *netdev)
 560 {
 561         struct qlcnic_adapter *adapter = netdev_priv(netdev);
 562         struct qlcnic_mac_vlan_list *cur;
 563         struct netdev_hw_addr *ha;
 564         size_t temp;
 565
 566         if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state))
 567                 return;
 568         if (qlcnic_sriov_vf_check(adapter)) {
 569                 if (!netdev_mc_empty(netdev)) {
 570                         netdev_for_each_mc_addr(ha, netdev) {
 571                                 temp = sizeof(struct qlcnic_mac_vlan_list);
 572                                 cur = kzalloc(temp, GFP_ATOMIC);
 573                                 if (cur == NULL)
 574                                         break;
 575                                 memcpy(cur->mac_addr,
 576                                        ha->addr, ETH_ALEN);
 577                                 list_add_tail(&cur->list, &adapter->vf_mc_list);
 578                         }
 579                 }
 580                 qlcnic_sriov_vf_schedule_multi(adapter->netdev);
 581                 return;
 582         }
 583         __qlcnic_set_multi(netdev, 0);
 584 }
 585
 586 int qlcnic_82xx_nic_set_promisc(struct qlcnic_adapter *adapter, u32 mode)
 587 {
 588         struct qlcnic_nic_req req;
 589         u64 word;
 590
 591         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 592
 593         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 594
 595         word = QLCNIC_H2C_OPCODE_SET_MAC_RECEIVE_MODE |
 596                         ((u64)adapter->portnum << 16);
 597         req.req_hdr = cpu_to_le64(word);
 598
 599         req.words[0] = cpu_to_le64(mode);
 600
 601         return qlcnic_send_cmd_descs(adapter,
 602                                 (struct cmd_desc_type0 *)&req, 1);
 603 }
 604
 605 void qlcnic_82xx_free_mac_list(struct qlcnic_adapter *adapter)
 606 {
 607         struct list_head *head = &adapter->mac_list;
 608         struct qlcnic_mac_vlan_list *cur;
 609
 610         while (!list_empty(head)) {
 611                 cur = list_entry(head->next, struct qlcnic_mac_vlan_list, list);
 612                 qlcnic_sre_macaddr_change(adapter,
 613                                 cur->mac_addr, 0, QLCNIC_MAC_DEL);
 614                 list_del(&cur->list);
 615                 kfree(cur);
 616         }
 617 }
 618
 619 void qlcnic_prune_lb_filters(struct qlcnic_adapter *adapter)
 620 {
 621         struct qlcnic_filter *tmp_fil;
 622         struct hlist_node *n;
 623         struct hlist_head *head;
 624         int i;
 625         unsigned long time;
 626         u8 cmd;
 627
 628         for (i = 0; i < adapter->fhash.fbucket_size; i++) {
 629                 head = &(adapter->fhash.fhead[i]);
 630                 hlist_for_each_entry_safe(tmp_fil, n, head, fnode) {
 631                         cmd =  tmp_fil->vlan_id ? QLCNIC_MAC_VLAN_DEL :
 632                                                   QLCNIC_MAC_DEL;
 633                         time = tmp_fil->ftime;
 634                         if (jiffies > (QLCNIC_FILTER_AGE * HZ + time)) {
 635                                 qlcnic_sre_macaddr_change(adapter,
 636                                                           tmp_fil->faddr,
 637                                                           tmp_fil->vlan_id,
 638                                                           cmd);
 639                                 spin_lock_bh(&adapter->mac_learn_lock);
 640                                 adapter->fhash.fnum--;
 641                                 hlist_del(&tmp_fil->fnode);
 642                                 spin_unlock_bh(&adapter->mac_learn_lock);
 643                                 kfree(tmp_fil);
 644                         }
 645                 }
 646         }
 647         for (i = 0; i < adapter->rx_fhash.fbucket_size; i++) {
 648                 head = &(adapter->rx_fhash.fhead[i]);
 649
 650                 hlist_for_each_entry_safe(tmp_fil, n, head, fnode)
 651                 {
 652                         time = tmp_fil->ftime;
 653                         if (jiffies > (QLCNIC_FILTER_AGE * HZ + time)) {
 654                                 spin_lock_bh(&adapter->rx_mac_learn_lock);
 655                                 adapter->rx_fhash.fnum--;
 656                                 hlist_del(&tmp_fil->fnode);
 657                                 spin_unlock_bh(&adapter->rx_mac_learn_lock);
 658                                 kfree(tmp_fil);
 659                         }
 660                 }
 661         }
 662 }
 663
 664 void qlcnic_delete_lb_filters(struct qlcnic_adapter *adapter)
 665 {
 666         struct qlcnic_filter *tmp_fil;
 667         struct hlist_node *n;
 668         struct hlist_head *head;
 669         int i;
 670         u8 cmd;
 671
 672         for (i = 0; i < adapter->fhash.fbucket_size; i++) {
 673                 head = &(adapter->fhash.fhead[i]);
 674                 hlist_for_each_entry_safe(tmp_fil, n, head, fnode) {
 675                         cmd =  tmp_fil->vlan_id ? QLCNIC_MAC_VLAN_DEL :
 676                                                   QLCNIC_MAC_DEL;
 677                         qlcnic_sre_macaddr_change(adapter,
 678                                                   tmp_fil->faddr,
 679                                                   tmp_fil->vlan_id,
 680                                                   cmd);
 681                         spin_lock_bh(&adapter->mac_learn_lock);
 682                         adapter->fhash.fnum--;
 683                         hlist_del(&tmp_fil->fnode);
 684                         spin_unlock_bh(&adapter->mac_learn_lock);
 685                         kfree(tmp_fil);
 686                 }
 687         }
 688 }
 689
 690 static int qlcnic_set_fw_loopback(struct qlcnic_adapter *adapter, u8 flag)
 691 {
 692         struct qlcnic_nic_req req;
 693         int rv;
 694
 695         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 696
 697         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 698         req.req_hdr = cpu_to_le64(QLCNIC_H2C_OPCODE_CONFIG_LOOPBACK |
 699                 ((u64) adapter->portnum << 16) | ((u64) 0x1 << 32));
 700
 701         req.words[0] = cpu_to_le64(flag);
 702
 703         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 704         if (rv != 0)
 705                 dev_err(&adapter->pdev->dev, "%sting loopback mode failed\n",
 706                                 flag ? "Set" : "Reset");
 707         return rv;
 708 }
 709
 710 int qlcnic_82xx_set_lb_mode(struct qlcnic_adapter *adapter, u8 mode)
 711 {
 712         if (qlcnic_set_fw_loopback(adapter, mode))
 713                 return -EIO;
 714
 715         if (qlcnic_nic_set_promisc(adapter,
 716                                    VPORT_MISS_MODE_ACCEPT_ALL)) {
 717                 qlcnic_set_fw_loopback(adapter, 0);
 718                 return -EIO;
 719         }
 720
 721         msleep(1000);
 722         return 0;
 723 }
 724
 725 int qlcnic_82xx_clear_lb_mode(struct qlcnic_adapter *adapter, u8 mode)
 726 {
 727         struct net_device *netdev = adapter->netdev;
 728
 729         mode = VPORT_MISS_MODE_DROP;
 730         qlcnic_set_fw_loopback(adapter, 0);
 731
 732         if (netdev->flags & IFF_PROMISC)
 733                 mode = VPORT_MISS_MODE_ACCEPT_ALL;
 734         else if (netdev->flags & IFF_ALLMULTI)
 735                 mode = VPORT_MISS_MODE_ACCEPT_MULTI;
 736
 737         qlcnic_nic_set_promisc(adapter, mode);
 738         msleep(1000);
 739         return 0;
 740 }
 741
 742 int qlcnic_82xx_read_phys_port_id(struct qlcnic_adapter *adapter)
 743 {
 744         u8 mac[ETH_ALEN];
 745         int ret;
 746
 747         ret = qlcnic_get_mac_address(adapter, mac,
 748                                      adapter->ahw->physical_port);
 749         if (ret)
 750                 return ret;
 751
 752         memcpy(adapter->ahw->phys_port_id, mac, ETH_ALEN);
 753         adapter->flags |= QLCNIC_HAS_PHYS_PORT_ID;
 754
 755         return 0;
 756 }
 757
 758 /*
 759  * Send the interrupt coalescing parameter set by ethtool to the card.
 760  */
 761 void qlcnic_82xx_config_intr_coalesce(struct qlcnic_adapter *adapter)
 762 {
 763         struct qlcnic_nic_req req;
 764         int rv;
 765
 766         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 767
 768         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 769
 770         req.req_hdr = cpu_to_le64(QLCNIC_CONFIG_INTR_COALESCE |
 771                 ((u64) adapter->portnum << 16));
 772
 773         req.words[0] = cpu_to_le64(((u64) adapter->ahw->coal.flag) << 32);
 774         req.words[2] = cpu_to_le64(adapter->ahw->coal.rx_packets |
 775                         ((u64) adapter->ahw->coal.rx_time_us) << 16);
 776         req.words[5] = cpu_to_le64(adapter->ahw->coal.timer_out |
 777                         ((u64) adapter->ahw->coal.type) << 32 |
 778                         ((u64) adapter->ahw->coal.sts_ring_mask) << 40);
 779         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 780         if (rv != 0)
 781                 dev_err(&adapter->netdev->dev,
 782                         "Could not send interrupt coalescing parameters\n");
 783 }
 784
 785 #define QLCNIC_ENABLE_IPV4_LRO          BIT_0
 786 #define QLCNIC_ENABLE_IPV6_LRO          (BIT_1 | BIT_9)
 787
 788 int qlcnic_82xx_config_hw_lro(struct qlcnic_adapter *adapter, int enable)
 789 {
 790         struct qlcnic_nic_req req;
 791         u64 word;
 792         int rv;
 793
 794         if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state))
 795                 return 0;
 796
 797         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 798
 799         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 800
 801         word = QLCNIC_H2C_OPCODE_CONFIG_HW_LRO | ((u64)adapter->portnum << 16);
 802         req.req_hdr = cpu_to_le64(word);
 803
 804         word = 0;
 805         if (enable) {
 806                 word = QLCNIC_ENABLE_IPV4_LRO;
 807                 if (adapter->ahw->extra_capability[0] &
 808                     QLCNIC_FW_CAP2_HW_LRO_IPV6)
 809                         word |= QLCNIC_ENABLE_IPV6_LRO;
 810         }
 811
 812         req.words[0] = cpu_to_le64(word);
 813
 814         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 815         if (rv != 0)
 816                 dev_err(&adapter->netdev->dev,
 817                         "Could not send configure hw lro request\n");
 818
 819         return rv;
 820 }
 821
 822 int qlcnic_config_bridged_mode(struct qlcnic_adapter *adapter, u32 enable)
 823 {
 824         struct qlcnic_nic_req req;
 825         u64 word;
 826         int rv;
 827
 828         if (!!(adapter->flags & QLCNIC_BRIDGE_ENABLED) == enable)
 829                 return 0;
 830
 831         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 832
 833         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 834
 835         word = QLCNIC_H2C_OPCODE_CONFIG_BRIDGING |
 836                 ((u64)adapter->portnum << 16);
 837         req.req_hdr = cpu_to_le64(word);
 838
 839         req.words[0] = cpu_to_le64(enable);
 840
 841         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 842         if (rv != 0)
 843                 dev_err(&adapter->netdev->dev,
 844                         "Could not send configure bridge mode request\n");
 845
 846         adapter->flags ^= QLCNIC_BRIDGE_ENABLED;
 847
 848         return rv;
 849 }
 850
 851
 852 #define QLCNIC_RSS_HASHTYPE_IP_TCP      0x3
 853 #define QLCNIC_ENABLE_TYPE_C_RSS        BIT_10
 854 #define QLCNIC_RSS_FEATURE_FLAG (1ULL << 63)
 855 #define QLCNIC_RSS_IND_TABLE_MASK       0x7ULL
 856
 857 int qlcnic_82xx_config_rss(struct qlcnic_adapter *adapter, int enable)
 858 {
 859         struct qlcnic_nic_req req;
 860         u64 word;
 861         int i, rv;
 862
 863         static const u64 key[] = {
 864                 0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL,
 865                 0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL,
 866                 0x255b0ec26d5a56daULL
 867         };
 868
 869         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 870         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 871
 872         word = QLCNIC_H2C_OPCODE_CONFIG_RSS | ((u64)adapter->portnum << 16);
 873         req.req_hdr = cpu_to_le64(word);
 874
 875         /*
 876          * RSS request:
 877          * bits 3-0: hash_method
 878          *      5-4: hash_type_ipv4
 879          *      7-6: hash_type_ipv6
 880          *        8: enable
 881          *        9: use indirection table
 882          *       10: type-c rss
 883          *       11: udp rss
 884          *    47-12: reserved
 885          *    62-48: indirection table mask
 886          *       63: feature flag
 887          */
 888         word =  ((u64)(QLCNIC_RSS_HASHTYPE_IP_TCP & 0x3) << 4) |
 889                 ((u64)(QLCNIC_RSS_HASHTYPE_IP_TCP & 0x3) << 6) |
 890                 ((u64)(enable & 0x1) << 8) |
 891                 ((u64)QLCNIC_RSS_IND_TABLE_MASK << 48) |
 892                 (u64)QLCNIC_ENABLE_TYPE_C_RSS |
 893                 (u64)QLCNIC_RSS_FEATURE_FLAG;
 894
 895         req.words[0] = cpu_to_le64(word);
 896         for (i = 0; i < 5; i++)
 897                 req.words[i+1] = cpu_to_le64(key[i]);
 898
 899         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 900         if (rv != 0)
 901                 dev_err(&adapter->netdev->dev, "could not configure RSS\n");
 902
 903         return rv;
 904 }
 905
 906 void qlcnic_82xx_config_ipaddr(struct qlcnic_adapter *adapter,
 907                                __be32 ip, int cmd)
 908 {
 909         struct qlcnic_nic_req req;
 910         struct qlcnic_ipaddr *ipa;
 911         u64 word;
 912         int rv;
 913
 914         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 915         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 916
 917         word = QLCNIC_H2C_OPCODE_CONFIG_IPADDR | ((u64)adapter->portnum << 16);
 918         req.req_hdr = cpu_to_le64(word);
 919
 920         req.words[0] = cpu_to_le64(cmd);
 921         ipa = (struct qlcnic_ipaddr *)&req.words[1];
 922         ipa->ipv4 = ip;
 923
 924         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 925         if (rv != 0)
 926                 dev_err(&adapter->netdev->dev,
 927                                 "could not notify %s IP 0x%x reuqest\n",
 928                                 (cmd == QLCNIC_IP_UP) ? "Add" : "Remove", ip);
 929 }
 930
 931 int qlcnic_82xx_linkevent_request(struct qlcnic_adapter *adapter, int enable)
 932 {
 933         struct qlcnic_nic_req req;
 934         u64 word;
 935         int rv;
 936         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 937         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 938
 939         word = QLCNIC_H2C_OPCODE_GET_LINKEVENT | ((u64)adapter->portnum << 16);
 940         req.req_hdr = cpu_to_le64(word);
 941         req.words[0] = cpu_to_le64(enable | (enable << 8));
 942         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 943         if (rv != 0)
 944                 dev_err(&adapter->netdev->dev,
 945                                 "could not configure link notification\n");
 946
 947         return rv;
 948 }
 949
 950 static int qlcnic_send_lro_cleanup(struct qlcnic_adapter *adapter)
 951 {
 952         struct qlcnic_nic_req req;
 953         u64 word;
 954         int rv;
 955
 956         if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state))
 957                 return 0;
 958
 959         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 960         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 961
 962         word = QLCNIC_H2C_OPCODE_LRO_REQUEST |
 963                 ((u64)adapter->portnum << 16) |
 964                 ((u64)QLCNIC_LRO_REQUEST_CLEANUP << 56) ;
 965
 966         req.req_hdr = cpu_to_le64(word);
 967
 968         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 969         if (rv != 0)
 970                 dev_err(&adapter->netdev->dev,
 971                                  "could not cleanup lro flows\n");
 972
 973         return rv;
 974 }
 975
 976 /*
 977  * qlcnic_change_mtu - Change the Maximum Transfer Unit
 978  * @returns 0 on success, negative on failure
 979  */
 980
 981 int qlcnic_change_mtu(struct net_device *netdev, int mtu)
 982 {
 983         struct qlcnic_adapter *adapter = netdev_priv(netdev);
 984         int rc = 0;
 985
 986         if (mtu < P3P_MIN_MTU || mtu > P3P_MAX_MTU) {
 987                 dev_err(&adapter->netdev->dev, "%d bytes < mtu < %d bytes"
 988                         " not supported\n", P3P_MAX_MTU, P3P_MIN_MTU);
 989                 return -EINVAL;
 990         }
 991
 992         rc = qlcnic_fw_cmd_set_mtu(adapter, mtu);
 993
 994         if (!rc)
 995                 netdev->mtu = mtu;
 996
 997         return rc;
 998 }
 999
1000 static netdev_features_t qlcnic_process_flags(struct qlcnic_adapter *adapter,
1001                                               netdev_features_t features)
1002 {
1003         u32 offload_flags = adapter->offload_flags;
1004
1005         if (offload_flags & BIT_0) {
1006                 features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM |
1007                             NETIF_F_IPV6_CSUM;
1008                 adapter->rx_csum = 1;
1009                 if (QLCNIC_IS_TSO_CAPABLE(adapter)) {
1010                         if (!(offload_flags & BIT_1))
1011                                 features &= ~NETIF_F_TSO;
1012                         else
1013                                 features |= NETIF_F_TSO;
1014
1015                         if (!(offload_flags & BIT_2))
1016                                 features &= ~NETIF_F_TSO6;
1017                         else
1018                                 features |= NETIF_F_TSO6;
1019                 }
1020         } else {
1021                 features &= ~(NETIF_F_RXCSUM |
1022                               NETIF_F_IP_CSUM |
1023                               NETIF_F_IPV6_CSUM);
1024
1025                 if (QLCNIC_IS_TSO_CAPABLE(adapter))
1026                         features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
1027                 adapter->rx_csum = 0;
1028         }
1029
1030         return features;
1031 }
1032
1033 netdev_features_t qlcnic_fix_features(struct net_device *netdev,
1034         netdev_features_t features)
1035 {
1036         struct qlcnic_adapter *adapter = netdev_priv(netdev);
1037         netdev_features_t changed;
1038
1039         if (qlcnic_82xx_check(adapter) &&
1040             (adapter->flags & QLCNIC_ESWITCH_ENABLED)) {
1041                 if (adapter->flags & QLCNIC_APP_CHANGED_FLAGS) {
1042                         features = qlcnic_process_flags(adapter, features);
1043                 } else {
1044                         changed = features ^ netdev->features;
1045                         features ^= changed & (NETIF_F_RXCSUM |
1046                                                NETIF_F_IP_CSUM |
1047                                                NETIF_F_IPV6_CSUM |
1048                                                NETIF_F_TSO |
1049                                                NETIF_F_TSO6);
1050                 }
1051         }
1052
1053         if (!(features & NETIF_F_RXCSUM))
1054                 features &= ~NETIF_F_LRO;
1055
1056         return features;
1057 }
1058
1059
1060 int qlcnic_set_features(struct net_device *netdev, netdev_features_t features)
1061 {
1062         struct qlcnic_adapter *adapter = netdev_priv(netdev);
1063         netdev_features_t changed = netdev->features ^ features;
1064         int hw_lro = (features & NETIF_F_LRO) ? QLCNIC_LRO_ENABLED : 0;
1065
1066         if (!(changed & NETIF_F_LRO))
1067                 return 0;
1068
1069         netdev->features ^= NETIF_F_LRO;
1070
1071         if (qlcnic_config_hw_lro(adapter, hw_lro))
1072                 return -EIO;
1073
1074         if (!hw_lro && qlcnic_82xx_check(adapter)) {
1075                 if (qlcnic_send_lro_cleanup(adapter))
1076                         return -EIO;
1077         }
1078
1079         return 0;
1080 }
1081
1082 /*
1083  * Changes the CRB window to the specified window.
1084  */
1085  /* Returns < 0 if off is not valid,
1086  *       1 if window access is needed. 'off' is set to offset from
1087  *         CRB space in 128M pci map
1088  *       0 if no window access is needed. 'off' is set to 2M addr
1089  * In: 'off' is offset from base in 128M pci map
1090  */
1091 static int qlcnic_pci_get_crb_addr_2M(struct qlcnic_hardware_context *ahw,
1092                                       ulong off, void __iomem **addr)
1093 {
1094         const struct crb_128M_2M_sub_block_map *m;
1095
1096         if ((off >= QLCNIC_CRB_MAX) || (off < QLCNIC_PCI_CRBSPACE))
1097                 return -EINVAL;
1098
1099         off -= QLCNIC_PCI_CRBSPACE;
1100
1101         /*
1102          * Try direct map
1103          */
1104         m = &crb_128M_2M_map[CRB_BLK(off)].sub_block[CRB_SUBBLK(off)];
1105
1106         if (m->valid && (m->start_128M <= off) && (m->end_128M > off)) {
1107                 *addr = ahw->pci_base0 + m->start_2M +
1108                         (off - m->start_128M);
1109                 return 0;
1110         }
1111
1112         /*
1113          * Not in direct map, use crb window
1114          */
1115         *addr = ahw->pci_base0 + CRB_INDIRECT_2M + (off & MASK(16));
1116         return 1;
1117 }
1118
1119 /*
1120  * In: 'off' is offset from CRB space in 128M pci map
1121  * Out: 'off' is 2M pci map addr
1122  * side effect: lock crb window
1123  */
1124 static int
1125 qlcnic_pci_set_crbwindow_2M(struct qlcnic_adapter *adapter, ulong off)
1126 {
1127         u32 window;
1128         void __iomem *addr = adapter->ahw->pci_base0 + CRB_WINDOW_2M;
1129
1130         off -= QLCNIC_PCI_CRBSPACE;
1131
1132         window = CRB_HI(off);
1133         if (window == 0) {
1134                 dev_err(&adapter->pdev->dev, "Invalid offset 0x%lx\n", off);
1135                 return -EIO;
1136         }
1137
1138         writel(window, addr);
1139         if (readl(addr) != window) {
1140                 if (printk_ratelimit())
1141                         dev_warn(&adapter->pdev->dev,
1142                                 "failed to set CRB window to %d off 0x%lx\n",
1143                                 window, off);
1144                 return -EIO;
1145         }
1146         return 0;
1147 }
1148
1149 int qlcnic_82xx_hw_write_wx_2M(struct qlcnic_adapter *adapter, ulong off,
1150                                u32 data)
1151 {
1152         unsigned long flags;
1153         int rv;
1154         void __iomem *addr = NULL;
1155
1156         rv = qlcnic_pci_get_crb_addr_2M(adapter->ahw, off, &addr);
1157
1158         if (rv == 0) {
1159                 writel(data, addr);
1160                 return 0;
1161         }
1162
1163         if (rv > 0) {
1164                 /* indirect access */
1165                 write_lock_irqsave(&adapter->ahw->crb_lock, flags);
1166                 crb_win_lock(adapter);
1167                 rv = qlcnic_pci_set_crbwindow_2M(adapter, off);
1168                 if (!rv)
1169                         writel(data, addr);
1170                 crb_win_unlock(adapter);
1171                 write_unlock_irqrestore(&adapter->ahw->crb_lock, flags);
1172                 return rv;
1173         }
1174
1175         dev_err(&adapter->pdev->dev,
1176                         "%s: invalid offset: 0x%016lx\n", __func__, off);
1177         dump_stack();
1178         return -EIO;
1179 }
1180
1181 int qlcnic_82xx_hw_read_wx_2M(struct qlcnic_adapter *adapter, ulong off,
1182                               int *err)
1183 {
1184         unsigned long flags;
1185         int rv;
1186         u32 data = -1;
1187         void __iomem *addr = NULL;
1188
1189         rv = qlcnic_pci_get_crb_addr_2M(adapter->ahw, off, &addr);
1190
1191         if (rv == 0)
1192                 return readl(addr);
1193
1194         if (rv > 0) {
1195                 /* indirect access */
1196                 write_lock_irqsave(&adapter->ahw->crb_lock, flags);
1197                 crb_win_lock(adapter);
1198                 if (!qlcnic_pci_set_crbwindow_2M(adapter, off))
1199                         data = readl(addr);
1200                 crb_win_unlock(adapter);
1201                 write_unlock_irqrestore(&adapter->ahw->crb_lock, flags);
1202                 return data;
1203         }
1204
1205         dev_err(&adapter->pdev->dev,
1206                         "%s: invalid offset: 0x%016lx\n", __func__, off);
1207         dump_stack();
1208         return -1;
1209 }
1210
1211 void __iomem *qlcnic_get_ioaddr(struct qlcnic_hardware_context *ahw,
1212                                 u32 offset)
1213 {
1214         void __iomem *addr = NULL;
1215
1216         WARN_ON(qlcnic_pci_get_crb_addr_2M(ahw, offset, &addr));
1217
1218         return addr;
1219 }
1220
1221 static int qlcnic_pci_mem_access_direct(struct qlcnic_adapter *adapter,
1222                                         u32 window, u64 off, u64 *data, int op)
1223 {
1224         void __iomem *addr;
1225         u32 start;
1226
1227         mutex_lock(&adapter->ahw->mem_lock);
1228
1229         writel(window, adapter->ahw->ocm_win_crb);
1230         /* read back to flush */
1231         readl(adapter->ahw->ocm_win_crb);
1232         start = QLCNIC_PCI_OCM0_2M + off;
1233
1234         addr = adapter->ahw->pci_base0 + start;
1235
1236         if (op == 0)    /* read */
1237                 *data = readq(addr);
1238         else            /* write */
1239                 writeq(*data, addr);
1240
1241         /* Set window to 0 */
1242         writel(0, adapter->ahw->ocm_win_crb);
1243         readl(adapter->ahw->ocm_win_crb);
1244
1245         mutex_unlock(&adapter->ahw->mem_lock);
1246         return 0;
1247 }
1248
1249 static void
1250 qlcnic_pci_camqm_read_2M(struct qlcnic_adapter *adapter, u64 off, u64 *data)
1251 {
1252         void __iomem *addr = adapter->ahw->pci_base0 +
1253                 QLCNIC_PCI_CAMQM_2M_BASE + (off - QLCNIC_PCI_CAMQM);
1254
1255         mutex_lock(&adapter->ahw->mem_lock);
1256         *data = readq(addr);
1257         mutex_unlock(&adapter->ahw->mem_lock);
1258 }
1259
1260 static void
1261 qlcnic_pci_camqm_write_2M(struct qlcnic_adapter *adapter, u64 off, u64 data)
1262 {
1263         void __iomem *addr = adapter->ahw->pci_base0 +
1264                 QLCNIC_PCI_CAMQM_2M_BASE + (off - QLCNIC_PCI_CAMQM);
1265
1266         mutex_lock(&adapter->ahw->mem_lock);
1267         writeq(data, addr);
1268         mutex_unlock(&adapter->ahw->mem_lock);
1269 }
1270
1271
1272
1273 /* Set MS memory control data for different adapters */
1274 static void qlcnic_set_ms_controls(struct qlcnic_adapter *adapter, u64 off,
1275                                    struct qlcnic_ms_reg_ctrl *ms)
1276 {
1277         ms->control = QLCNIC_MS_CTRL;
1278         ms->low = QLCNIC_MS_ADDR_LO;
1279         ms->hi = QLCNIC_MS_ADDR_HI;
1280         if (off & 0xf) {
1281                 ms->wd[0] = QLCNIC_MS_WRTDATA_LO;
1282                 ms->rd[0] = QLCNIC_MS_RDDATA_LO;
1283                 ms->wd[1] = QLCNIC_MS_WRTDATA_HI;
1284                 ms->rd[1] = QLCNIC_MS_RDDATA_HI;
1285                 ms->wd[2] = QLCNIC_MS_WRTDATA_ULO;
1286                 ms->wd[3] = QLCNIC_MS_WRTDATA_UHI;
1287                 ms->rd[2] = QLCNIC_MS_RDDATA_ULO;
1288                 ms->rd[3] = QLCNIC_MS_RDDATA_UHI;
1289         } else {
1290                 ms->wd[0] = QLCNIC_MS_WRTDATA_ULO;
1291                 ms->rd[0] = QLCNIC_MS_RDDATA_ULO;
1292                 ms->wd[1] = QLCNIC_MS_WRTDATA_UHI;
1293                 ms->rd[1] = QLCNIC_MS_RDDATA_UHI;
1294                 ms->wd[2] = QLCNIC_MS_WRTDATA_LO;
1295                 ms->wd[3] = QLCNIC_MS_WRTDATA_HI;
1296                 ms->rd[2] = QLCNIC_MS_RDDATA_LO;
1297                 ms->rd[3] = QLCNIC_MS_RDDATA_HI;
1298         }
1299
1300         ms->ocm_window = OCM_WIN_P3P(off);
1301         ms->off = GET_MEM_OFFS_2M(off);
1302 }
1303
1304 int qlcnic_pci_mem_write_2M(struct qlcnic_adapter *adapter, u64 off, u64 data)
1305 {
1306         int j, ret = 0;
1307         u32 temp, off8;
1308         struct qlcnic_ms_reg_ctrl ms;
1309
1310         /* Only 64-bit aligned access */
1311         if (off & 7)
1312                 return -EIO;
1313
1314         memset(&ms, 0, sizeof(struct qlcnic_ms_reg_ctrl));
1315         if (!(ADDR_IN_RANGE(off, QLCNIC_ADDR_QDR_NET,
1316                             QLCNIC_ADDR_QDR_NET_MAX) ||
1317               ADDR_IN_RANGE(off, QLCNIC_ADDR_DDR_NET,
1318                             QLCNIC_ADDR_DDR_NET_MAX)))
1319                 return -EIO;
1320
1321         qlcnic_set_ms_controls(adapter, off, &ms);
1322
1323         if (ADDR_IN_RANGE(off, QLCNIC_ADDR_OCM0, QLCNIC_ADDR_OCM0_MAX))
1324                 return qlcnic_pci_mem_access_direct(adapter, ms.ocm_window,
1325                                                     ms.off, &data, 1);
1326
1327         off8 = off & ~0xf;
1328
1329         mutex_lock(&adapter->ahw->mem_lock);
1330
1331         qlcnic_ind_wr(adapter, ms.low, off8);
1332         qlcnic_ind_wr(adapter, ms.hi, 0);
1333
1334         qlcnic_ind_wr(adapter, ms.control, TA_CTL_ENABLE);
1335         qlcnic_ind_wr(adapter, ms.control, QLCNIC_TA_START_ENABLE);
1336
1337         for (j = 0; j < MAX_CTL_CHECK; j++) {
1338                 temp = qlcnic_ind_rd(adapter, ms.control);
1339                 if ((temp & TA_CTL_BUSY) == 0)
1340                         break;
1341         }
1342
1343         if (j >= MAX_CTL_CHECK) {
1344                 ret = -EIO;
1345                 goto done;
1346         }
1347
1348         /* This is the modify part of read-modify-write */
1349         qlcnic_ind_wr(adapter, ms.wd[0], qlcnic_ind_rd(adapter, ms.rd[0]));
1350         qlcnic_ind_wr(adapter, ms.wd[1], qlcnic_ind_rd(adapter, ms.rd[1]));
1351         /* This is the write part of read-modify-write */
1352         qlcnic_ind_wr(adapter, ms.wd[2], data & 0xffffffff);
1353         qlcnic_ind_wr(adapter, ms.wd[3], (data >> 32) & 0xffffffff);
1354
1355         qlcnic_ind_wr(adapter, ms.control, QLCNIC_TA_WRITE_ENABLE);
1356         qlcnic_ind_wr(adapter, ms.control, QLCNIC_TA_WRITE_START);
1357
1358         for (j = 0; j < MAX_CTL_CHECK; j++) {
1359                 temp = qlcnic_ind_rd(adapter, ms.control);
1360                 if ((temp & TA_CTL_BUSY) == 0)
1361                         break;
1362         }
1363
1364         if (j >= MAX_CTL_CHECK) {
1365                 if (printk_ratelimit())
1366                         dev_err(&adapter->pdev->dev,
1367                                         "failed to write through agent\n");
1368                 ret = -EIO;
1369         } else
1370                 ret = 0;
1371
1372 done:
1373         mutex_unlock(&adapter->ahw->mem_lock);
1374
1375         return ret;
1376 }
1377
1378 int qlcnic_pci_mem_read_2M(struct qlcnic_adapter *adapter, u64 off, u64 *data)
1379 {
1380         int j, ret;
1381         u32 temp, off8;
1382         u64 val;
1383         struct qlcnic_ms_reg_ctrl ms;
1384
1385         /* Only 64-bit aligned access */
1386         if (off & 7)
1387                 return -EIO;
1388         if (!(ADDR_IN_RANGE(off, QLCNIC_ADDR_QDR_NET,
1389                             QLCNIC_ADDR_QDR_NET_MAX) ||
1390               ADDR_IN_RANGE(off, QLCNIC_ADDR_DDR_NET,
1391                             QLCNIC_ADDR_DDR_NET_MAX)))
1392                 return -EIO;
1393
1394         memset(&ms, 0, sizeof(struct qlcnic_ms_reg_ctrl));
1395         qlcnic_set_ms_controls(adapter, off, &ms);
1396
1397         if (ADDR_IN_RANGE(off, QLCNIC_ADDR_OCM0, QLCNIC_ADDR_OCM0_MAX))
1398                 return qlcnic_pci_mem_access_direct(adapter, ms.ocm_window,
1399                                                     ms.off, data, 0);
1400
1401         mutex_lock(&adapter->ahw->mem_lock);
1402
1403         off8 = off & ~0xf;
1404
1405         qlcnic_ind_wr(adapter, ms.low, off8);
1406         qlcnic_ind_wr(adapter, ms.hi, 0);
1407
1408         qlcnic_ind_wr(adapter, ms.control, TA_CTL_ENABLE);
1409         qlcnic_ind_wr(adapter, ms.control, QLCNIC_TA_START_ENABLE);
1410
1411         for (j = 0; j < MAX_CTL_CHECK; j++) {
1412                 temp = qlcnic_ind_rd(adapter, ms.control);
1413                 if ((temp & TA_CTL_BUSY) == 0)
1414                         break;
1415         }
1416
1417         if (j >= MAX_CTL_CHECK) {
1418                 if (printk_ratelimit())
1419                         dev_err(&adapter->pdev->dev,
1420                                         "failed to read through agent\n");
1421                 ret = -EIO;
1422         } else {
1423
1424                 temp = qlcnic_ind_rd(adapter, ms.rd[3]);
1425                 val = (u64)temp << 32;
1426                 val |= qlcnic_ind_rd(adapter, ms.rd[2]);
1427                 *data = val;
1428                 ret = 0;
1429         }
1430
1431         mutex_unlock(&adapter->ahw->mem_lock);
1432
1433         return ret;
1434 }
1435
1436 int qlcnic_82xx_get_board_info(struct qlcnic_adapter *adapter)
1437 {
1438         int offset, board_type, magic, err = 0;
1439         struct pci_dev *pdev = adapter->pdev;
1440
1441         offset = QLCNIC_FW_MAGIC_OFFSET;
1442         if (qlcnic_rom_fast_read(adapter, offset, &magic))
1443                 return -EIO;
1444
1445         if (magic != QLCNIC_BDINFO_MAGIC) {
1446                 dev_err(&pdev->dev, "invalid board config, magic=%08x\n",
1447                         magic);
1448                 return -EIO;
1449         }
1450
1451         offset = QLCNIC_BRDTYPE_OFFSET;
1452         if (qlcnic_rom_fast_read(adapter, offset, &board_type))
1453                 return -EIO;
1454
1455         adapter->ahw->board_type = board_type;
1456
1457         if (board_type == QLCNIC_BRDTYPE_P3P_4_GB_MM) {
1458                 u32 gpio = QLCRD32(adapter, QLCNIC_ROMUSB_GLB_PAD_GPIO_I, &err);
1459                 if (err == -EIO)
1460                         return err;
1461                 if ((gpio & 0x8000) == 0)
1462                         board_type = QLCNIC_BRDTYPE_P3P_10G_TP;
1463         }
1464
1465         switch (board_type) {
1466         case QLCNIC_BRDTYPE_P3P_HMEZ:
1467         case QLCNIC_BRDTYPE_P3P_XG_LOM:
1468         case QLCNIC_BRDTYPE_P3P_10G_CX4:
1469         case QLCNIC_BRDTYPE_P3P_10G_CX4_LP:
1470         case QLCNIC_BRDTYPE_P3P_IMEZ:
1471         case QLCNIC_BRDTYPE_P3P_10G_SFP_PLUS:
1472         case QLCNIC_BRDTYPE_P3P_10G_SFP_CT:
1473         case QLCNIC_BRDTYPE_P3P_10G_SFP_QT:
1474         case QLCNIC_BRDTYPE_P3P_10G_XFP:
1475         case QLCNIC_BRDTYPE_P3P_10000_BASE_T:
1476                 adapter->ahw->port_type = QLCNIC_XGBE;
1477                 break;
1478         case QLCNIC_BRDTYPE_P3P_REF_QG:
1479         case QLCNIC_BRDTYPE_P3P_4_GB:
1480         case QLCNIC_BRDTYPE_P3P_4_GB_MM:
1481                 adapter->ahw->port_type = QLCNIC_GBE;
1482                 break;
1483         case QLCNIC_BRDTYPE_P3P_10G_TP:
1484                 adapter->ahw->port_type = (adapter->portnum < 2) ?
1485                         QLCNIC_XGBE : QLCNIC_GBE;
1486                 break;
1487         default:
1488                 dev_err(&pdev->dev, "unknown board type %x\n", board_type);
1489                 adapter->ahw->port_type = QLCNIC_XGBE;
1490                 break;
1491         }
1492
1493         return 0;
1494 }
1495
1496 static int
1497 qlcnic_wol_supported(struct qlcnic_adapter *adapter)
1498 {
1499         u32 wol_cfg;
1500         int err = 0;
1501
1502         wol_cfg = QLCRD32(adapter, QLCNIC_WOL_CONFIG_NV, &err);
1503         if (wol_cfg & (1UL << adapter->portnum)) {
1504                 wol_cfg = QLCRD32(adapter, QLCNIC_WOL_CONFIG, &err);
1505                 if (err == -EIO)
1506                         return err;
1507                 if (wol_cfg & (1 << adapter->portnum))
1508                         return 1;
1509         }
1510
1511         return 0;
1512 }
1513
1514 int qlcnic_82xx_config_led(struct qlcnic_adapter *adapter, u32 state, u32 rate)
1515 {
1516         struct qlcnic_nic_req   req;
1517         int rv;
1518         u64 word;
1519
1520         memset(&req, 0, sizeof(struct qlcnic_nic_req));
1521         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
1522
1523         word = QLCNIC_H2C_OPCODE_CONFIG_LED | ((u64)adapter->portnum << 16);
1524         req.req_hdr = cpu_to_le64(word);
1525
1526         req.words[0] = cpu_to_le64(((u64)rate << 32) | adapter->portnum);
1527         req.words[1] = cpu_to_le64(state);
1528
1529         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
1530         if (rv)
1531                 dev_err(&adapter->pdev->dev, "LED configuration failed.\n");
1532
1533         return rv;
1534 }
1535
1536 void qlcnic_82xx_get_beacon_state(struct qlcnic_adapter *adapter)
1537 {
1538         struct qlcnic_hardware_context *ahw = adapter->ahw;
1539         struct qlcnic_cmd_args cmd;
1540         u8 beacon_state;
1541         int err = 0;
1542
1543         if (ahw->extra_capability[0] & QLCNIC_FW_CAPABILITY_2_BEACON) {
1544                 err = qlcnic_alloc_mbx_args(&cmd, adapter,
1545                                             QLCNIC_CMD_GET_LED_STATUS);
1546                 if (!err) {
1547                         err = qlcnic_issue_cmd(adapter, &cmd);
1548                         if (err) {
1549                                 netdev_err(adapter->netdev,
1550                                            "Failed to get current beacon state, err=%d\n",
1551                                            err);
1552                         } else {
1553                                 beacon_state = cmd.rsp.arg[1];
1554                                 if (beacon_state == QLCNIC_BEACON_DISABLE)
1555                                         ahw->beacon_state = QLCNIC_BEACON_OFF;
1556                                 else if (beacon_state == QLCNIC_BEACON_EANBLE)
1557                                         ahw->beacon_state = QLCNIC_BEACON_ON;
1558                         }
1559                 }
1560                 qlcnic_free_mbx_args(&cmd);
1561         }
1562
1563         return;
1564 }
1565
1566 void qlcnic_82xx_get_func_no(struct qlcnic_adapter *adapter)
1567 {
1568         void __iomem *msix_base_addr;
1569         u32 func;
1570         u32 msix_base;
1571
1572         pci_read_config_dword(adapter->pdev, QLCNIC_MSIX_TABLE_OFFSET, &func);
1573         msix_base_addr = adapter->ahw->pci_base0 + QLCNIC_MSIX_BASE;
1574         msix_base = readl(msix_base_addr);
1575         func = (func - msix_base) / QLCNIC_MSIX_TBL_PGSIZE;
1576         adapter->ahw->pci_func = func;
1577 }
1578
1579 void qlcnic_82xx_read_crb(struct qlcnic_adapter *adapter, char *buf,
1580                           loff_t offset, size_t size)
1581 {
1582         int err = 0;
1583         u32 data;
1584         u64 qmdata;
1585
1586         if (ADDR_IN_RANGE(offset, QLCNIC_PCI_CAMQM, QLCNIC_PCI_CAMQM_END)) {
1587                 qlcnic_pci_camqm_read_2M(adapter, offset, &qmdata);
1588                 memcpy(buf, &qmdata, size);
1589         } else {
1590                 data = QLCRD32(adapter, offset, &err);
1591                 memcpy(buf, &data, size);
1592         }
1593 }
1594
1595 void qlcnic_82xx_write_crb(struct qlcnic_adapter *adapter, char *buf,
1596                            loff_t offset, size_t size)
1597 {
1598         u32 data;
1599         u64 qmdata;
1600
1601         if (ADDR_IN_RANGE(offset, QLCNIC_PCI_CAMQM, QLCNIC_PCI_CAMQM_END)) {
1602                 memcpy(&qmdata, buf, size);
1603                 qlcnic_pci_camqm_write_2M(adapter, offset, qmdata);
1604         } else {
1605                 memcpy(&data, buf, size);
1606                 QLCWR32(adapter, offset, data);
1607         }
1608 }
1609
1610 int qlcnic_82xx_api_lock(struct qlcnic_adapter *adapter)
1611 {
1612         return qlcnic_pcie_sem_lock(adapter, 5, 0);
1613 }
1614
1615 void qlcnic_82xx_api_unlock(struct qlcnic_adapter *adapter)
1616 {
1617         qlcnic_pcie_sem_unlock(adapter, 5);
1618 }
1619
1620 int qlcnic_82xx_shutdown(struct pci_dev *pdev)
1621 {
1622         struct qlcnic_adapter *adapter = pci_get_drvdata(pdev);
1623         struct net_device *netdev = adapter->netdev;
1624         int retval;
1625
1626         netif_device_detach(netdev);
1627
1628         qlcnic_cancel_idc_work(adapter);
1629
1630         if (netif_running(netdev))
1631                 qlcnic_down(adapter, netdev);
1632
1633         qlcnic_clr_all_drv_state(adapter, 0);
1634
1635         clear_bit(__QLCNIC_RESETTING, &adapter->state);
1636
1637         retval = pci_save_state(pdev);
1638         if (retval)
1639                 return retval;
1640
1641         if (qlcnic_wol_supported(adapter)) {
1642                 pci_enable_wake(pdev, PCI_D3cold, 1);
1643                 pci_enable_wake(pdev, PCI_D3hot, 1);
1644         }
1645
1646         return 0;
1647 }
1648
1649 int qlcnic_82xx_resume(struct qlcnic_adapter *adapter)
1650 {
1651         struct net_device *netdev = adapter->netdev;
1652         int err;
1653
1654         err = qlcnic_start_firmware(adapter);
1655         if (err) {
1656                 dev_err(&adapter->pdev->dev, "failed to start firmware\n");
1657                 return err;
1658         }
1659
1660         if (netif_running(netdev)) {
1661                 err = qlcnic_up(adapter, netdev);
1662                 if (!err)
1663                         qlcnic_restore_indev_addr(netdev, NETDEV_UP);
1664         }
1665
1666         netif_device_attach(netdev);
1667         qlcnic_schedule_work(adapter, qlcnic_fw_poll_work, FW_POLL_DELAY);
1668         return err;
1669 }