2 * QLogic qlcnic NIC Driver
3 * Copyright (c) 2009-2013 QLogic Corporation
5 * See LICENSE.qlcnic for copyright and licensing details.
9 #include "qlcnic_hdr.h"
10 #include "qlcnic_83xx_hw.h"
11 #include "qlcnic_hw.h"
15 #define QLC_83XX_MINIDUMP_FLASH 0x520000
16 #define QLC_83XX_OCM_INDEX 3
17 #define QLC_83XX_PCI_INDEX 0
19 static const u32 qlcnic_ms_read_data[] = {
20 0x410000A8, 0x410000AC, 0x410000B8, 0x410000BC
23 #define QLCNIC_DUMP_WCRB BIT_0
24 #define QLCNIC_DUMP_RWCRB BIT_1
25 #define QLCNIC_DUMP_ANDCRB BIT_2
26 #define QLCNIC_DUMP_ORCRB BIT_3
27 #define QLCNIC_DUMP_POLLCRB BIT_4
28 #define QLCNIC_DUMP_RD_SAVE BIT_5
29 #define QLCNIC_DUMP_WRT_SAVED BIT_6
30 #define QLCNIC_DUMP_MOD_SAVE_ST BIT_7
31 #define QLCNIC_DUMP_SKIP BIT_7
33 #define QLCNIC_DUMP_MASK_MAX 0xff
35 struct qlcnic_common_entry_hdr {
158 struct qlcnic_dump_entry {
159 struct qlcnic_common_entry_hdr hdr;
162 struct __cache cache;
168 struct __pollrdmwr pollrdmwr;
170 struct __pollrd pollrd;
174 enum qlcnic_minidump_opcode {
176 QLCNIC_DUMP_READ_CRB = 1,
177 QLCNIC_DUMP_READ_MUX = 2,
178 QLCNIC_DUMP_QUEUE = 3,
179 QLCNIC_DUMP_BRD_CONFIG = 4,
180 QLCNIC_DUMP_READ_OCM = 6,
181 QLCNIC_DUMP_PEG_REG = 7,
182 QLCNIC_DUMP_L1_DTAG = 8,
183 QLCNIC_DUMP_L1_ITAG = 9,
184 QLCNIC_DUMP_L1_DATA = 11,
185 QLCNIC_DUMP_L1_INST = 12,
186 QLCNIC_DUMP_L2_DTAG = 21,
187 QLCNIC_DUMP_L2_ITAG = 22,
188 QLCNIC_DUMP_L2_DATA = 23,
189 QLCNIC_DUMP_L2_INST = 24,
190 QLCNIC_DUMP_POLL_RD = 35,
191 QLCNIC_READ_MUX2 = 36,
192 QLCNIC_READ_POLLRDMWR = 37,
193 QLCNIC_DUMP_READ_ROM = 71,
194 QLCNIC_DUMP_READ_MEM = 72,
195 QLCNIC_DUMP_READ_CTRL = 98,
196 QLCNIC_DUMP_TLHDR = 99,
197 QLCNIC_DUMP_RDEND = 255
200 struct qlcnic_dump_operations {
201 enum qlcnic_minidump_opcode opcode;
202 u32 (*handler)(struct qlcnic_adapter *, struct qlcnic_dump_entry *,
206 static u32 qlcnic_dump_crb(struct qlcnic_adapter *adapter,
207 struct qlcnic_dump_entry *entry, __le32 *buffer)
211 struct __crb *crb = &entry->region.crb;
215 for (i = 0; i < crb->no_ops; i++) {
216 data = qlcnic_ind_rd(adapter, addr);
217 *buffer++ = cpu_to_le32(addr);
218 *buffer++ = cpu_to_le32(data);
221 return crb->no_ops * 2 * sizeof(u32);
224 static u32 qlcnic_dump_ctrl(struct qlcnic_adapter *adapter,
225 struct qlcnic_dump_entry *entry, __le32 *buffer)
227 int i, k, timeout = 0;
230 struct __ctrl *ctr = &entry->region.ctrl;
231 struct qlcnic_dump_template_hdr *t_hdr = adapter->ahw->fw_dump.tmpl_hdr;
234 no_ops = ctr->no_ops;
236 for (i = 0; i < no_ops; i++) {
238 for (k = 0; k < 8; k++) {
239 if (!(ctr->opcode & (1 << k)))
242 case QLCNIC_DUMP_WCRB:
243 qlcnic_ind_wr(adapter, addr, ctr->val1);
245 case QLCNIC_DUMP_RWCRB:
246 data = qlcnic_ind_rd(adapter, addr);
247 qlcnic_ind_wr(adapter, addr, data);
249 case QLCNIC_DUMP_ANDCRB:
250 data = qlcnic_ind_rd(adapter, addr);
251 qlcnic_ind_wr(adapter, addr,
254 case QLCNIC_DUMP_ORCRB:
255 data = qlcnic_ind_rd(adapter, addr);
256 qlcnic_ind_wr(adapter, addr,
259 case QLCNIC_DUMP_POLLCRB:
260 while (timeout <= ctr->timeout) {
261 data = qlcnic_ind_rd(adapter, addr);
262 if ((data & ctr->val2) == ctr->val1)
264 usleep_range(1000, 2000);
267 if (timeout > ctr->timeout) {
268 dev_info(&adapter->pdev->dev,
269 "Timed out, aborting poll CRB\n");
273 case QLCNIC_DUMP_RD_SAVE:
275 addr = t_hdr->saved_state[ctr->index_a];
276 data = qlcnic_ind_rd(adapter, addr);
277 t_hdr->saved_state[ctr->index_v] = data;
279 case QLCNIC_DUMP_WRT_SAVED:
281 data = t_hdr->saved_state[ctr->index_v];
285 addr = t_hdr->saved_state[ctr->index_a];
286 qlcnic_ind_wr(adapter, addr, data);
288 case QLCNIC_DUMP_MOD_SAVE_ST:
289 data = t_hdr->saved_state[ctr->index_v];
290 data <<= ctr->shl_val;
291 data >>= ctr->shr_val;
296 t_hdr->saved_state[ctr->index_v] = data;
299 dev_info(&adapter->pdev->dev,
309 static u32 qlcnic_dump_mux(struct qlcnic_adapter *adapter,
310 struct qlcnic_dump_entry *entry, __le32 *buffer)
314 struct __mux *mux = &entry->region.mux;
317 for (loop = 0; loop < mux->no_ops; loop++) {
318 qlcnic_ind_wr(adapter, mux->addr, val);
319 data = qlcnic_ind_rd(adapter, mux->read_addr);
320 *buffer++ = cpu_to_le32(val);
321 *buffer++ = cpu_to_le32(data);
322 val += mux->val_stride;
324 return 2 * mux->no_ops * sizeof(u32);
327 static u32 qlcnic_dump_que(struct qlcnic_adapter *adapter,
328 struct qlcnic_dump_entry *entry, __le32 *buffer)
331 u32 cnt, addr, data, que_id = 0;
332 struct __queue *que = &entry->region.que;
334 addr = que->read_addr;
335 cnt = que->read_addr_cnt;
337 for (loop = 0; loop < que->no_ops; loop++) {
338 qlcnic_ind_wr(adapter, que->sel_addr, que_id);
339 addr = que->read_addr;
340 for (i = 0; i < cnt; i++) {
341 data = qlcnic_ind_rd(adapter, addr);
342 *buffer++ = cpu_to_le32(data);
343 addr += que->read_addr_stride;
345 que_id += que->stride;
347 return que->no_ops * cnt * sizeof(u32);
350 static u32 qlcnic_dump_ocm(struct qlcnic_adapter *adapter,
351 struct qlcnic_dump_entry *entry, __le32 *buffer)
356 struct __ocm *ocm = &entry->region.ocm;
358 addr = adapter->ahw->pci_base0 + ocm->read_addr;
359 for (i = 0; i < ocm->no_ops; i++) {
361 *buffer++ = cpu_to_le32(data);
362 addr += ocm->read_addr_stride;
364 return ocm->no_ops * sizeof(u32);
367 static u32 qlcnic_read_rom(struct qlcnic_adapter *adapter,
368 struct qlcnic_dump_entry *entry, __le32 *buffer)
371 u32 fl_addr, size, val, lck_val, addr;
372 struct __mem *rom = &entry->region.mem;
375 size = rom->size / 4;
377 lck_val = QLC_SHARED_REG_RD32(adapter, QLCNIC_FLASH_LOCK);
378 if (!lck_val && count < MAX_CTL_CHECK) {
379 usleep_range(10000, 11000);
383 QLC_SHARED_REG_WR32(adapter, QLCNIC_FLASH_LOCK_OWNER,
384 adapter->ahw->pci_func);
385 for (i = 0; i < size; i++) {
386 addr = fl_addr & 0xFFFF0000;
387 qlcnic_ind_wr(adapter, FLASH_ROM_WINDOW, addr);
388 addr = LSW(fl_addr) + FLASH_ROM_DATA;
389 val = qlcnic_ind_rd(adapter, addr);
391 *buffer++ = cpu_to_le32(val);
393 QLC_SHARED_REG_RD32(adapter, QLCNIC_FLASH_UNLOCK);
397 static u32 qlcnic_dump_l1_cache(struct qlcnic_adapter *adapter,
398 struct qlcnic_dump_entry *entry, __le32 *buffer)
401 u32 cnt, val, data, addr;
402 struct __cache *l1 = &entry->region.cache;
404 val = l1->init_tag_val;
406 for (i = 0; i < l1->no_ops; i++) {
407 qlcnic_ind_wr(adapter, l1->addr, val);
408 qlcnic_ind_wr(adapter, l1->ctrl_addr, LSW(l1->ctrl_val));
409 addr = l1->read_addr;
410 cnt = l1->read_addr_num;
412 data = qlcnic_ind_rd(adapter, addr);
413 *buffer++ = cpu_to_le32(data);
414 addr += l1->read_addr_stride;
419 return l1->no_ops * l1->read_addr_num * sizeof(u32);
422 static u32 qlcnic_dump_l2_cache(struct qlcnic_adapter *adapter,
423 struct qlcnic_dump_entry *entry, __le32 *buffer)
426 u32 cnt, val, data, addr;
427 u8 poll_mask, poll_to, time_out = 0;
428 struct __cache *l2 = &entry->region.cache;
430 val = l2->init_tag_val;
431 poll_mask = LSB(MSW(l2->ctrl_val));
432 poll_to = MSB(MSW(l2->ctrl_val));
434 for (i = 0; i < l2->no_ops; i++) {
435 qlcnic_ind_wr(adapter, l2->addr, val);
436 if (LSW(l2->ctrl_val))
437 qlcnic_ind_wr(adapter, l2->ctrl_addr,
442 data = qlcnic_ind_rd(adapter, l2->ctrl_addr);
443 if (!(data & poll_mask))
445 usleep_range(1000, 2000);
447 } while (time_out <= poll_to);
449 if (time_out > poll_to) {
450 dev_err(&adapter->pdev->dev,
451 "Timeout exceeded in %s, aborting dump\n",
456 addr = l2->read_addr;
457 cnt = l2->read_addr_num;
459 data = qlcnic_ind_rd(adapter, addr);
460 *buffer++ = cpu_to_le32(data);
461 addr += l2->read_addr_stride;
466 return l2->no_ops * l2->read_addr_num * sizeof(u32);
469 static u32 qlcnic_read_memory(struct qlcnic_adapter *adapter,
470 struct qlcnic_dump_entry *entry, __le32 *buffer)
472 u32 addr, data, test, ret = 0;
474 struct __mem *mem = &entry->region.mem;
476 reg_read = mem->size;
478 /* check for data size of multiple of 16 and 16 byte alignment */
479 if ((addr & 0xf) || (reg_read%16)) {
480 dev_info(&adapter->pdev->dev,
481 "Unaligned memory addr:0x%x size:0x%x\n",
486 mutex_lock(&adapter->ahw->mem_lock);
488 while (reg_read != 0) {
489 qlcnic_ind_wr(adapter, QLCNIC_MS_ADDR_LO, addr);
490 qlcnic_ind_wr(adapter, QLCNIC_MS_ADDR_HI, 0);
491 qlcnic_ind_wr(adapter, QLCNIC_MS_CTRL, QLCNIC_TA_START_ENABLE);
493 for (i = 0; i < MAX_CTL_CHECK; i++) {
494 test = qlcnic_ind_rd(adapter, QLCNIC_MS_CTRL);
495 if (!(test & TA_CTL_BUSY))
498 if (i == MAX_CTL_CHECK) {
499 if (printk_ratelimit()) {
500 dev_err(&adapter->pdev->dev,
501 "failed to read through agent\n");
506 for (i = 0; i < 4; i++) {
507 data = qlcnic_ind_rd(adapter, qlcnic_ms_read_data[i]);
508 *buffer++ = cpu_to_le32(data);
515 mutex_unlock(&adapter->ahw->mem_lock);
519 static u32 qlcnic_dump_nop(struct qlcnic_adapter *adapter,
520 struct qlcnic_dump_entry *entry, __le32 *buffer)
522 entry->hdr.flags |= QLCNIC_DUMP_SKIP;
526 static int qlcnic_valid_dump_entry(struct device *dev,
527 struct qlcnic_dump_entry *entry, u32 size)
530 if (size != entry->hdr.cap_size) {
532 "Invalid entry, Type:%d\tMask:%d\tSize:%dCap_size:%d\n",
533 entry->hdr.type, entry->hdr.mask, size,
534 entry->hdr.cap_size);
540 static u32 qlcnic_read_pollrdmwr(struct qlcnic_adapter *adapter,
541 struct qlcnic_dump_entry *entry,
544 struct __pollrdmwr *poll = &entry->region.pollrdmwr;
545 u32 data, wait_count, poll_wait, temp;
547 poll_wait = poll->poll_wait;
549 qlcnic_ind_wr(adapter, poll->addr1, poll->val1);
552 while (wait_count < poll_wait) {
553 data = qlcnic_ind_rd(adapter, poll->addr1);
554 if ((data & poll->poll_mask) != 0)
559 if (wait_count == poll_wait) {
560 dev_err(&adapter->pdev->dev,
561 "Timeout exceeded in %s, aborting dump\n",
566 data = qlcnic_ind_rd(adapter, poll->addr2) & poll->mod_mask;
567 qlcnic_ind_wr(adapter, poll->addr2, data);
568 qlcnic_ind_wr(adapter, poll->addr1, poll->val2);
571 while (wait_count < poll_wait) {
572 temp = qlcnic_ind_rd(adapter, poll->addr1);
573 if ((temp & poll->poll_mask) != 0)
578 *buffer++ = cpu_to_le32(poll->addr2);
579 *buffer++ = cpu_to_le32(data);
581 return 2 * sizeof(u32);
585 static u32 qlcnic_read_pollrd(struct qlcnic_adapter *adapter,
586 struct qlcnic_dump_entry *entry, __le32 *buffer)
588 struct __pollrd *pollrd = &entry->region.pollrd;
589 u32 data, wait_count, poll_wait, sel_val;
592 poll_wait = pollrd->poll_wait;
593 sel_val = pollrd->sel_val;
595 for (i = 0; i < pollrd->no_ops; i++) {
596 qlcnic_ind_wr(adapter, pollrd->sel_addr, sel_val);
598 while (wait_count < poll_wait) {
599 data = qlcnic_ind_rd(adapter, pollrd->sel_addr);
600 if ((data & pollrd->poll_mask) != 0)
605 if (wait_count == poll_wait) {
606 dev_err(&adapter->pdev->dev,
607 "Timeout exceeded in %s, aborting dump\n",
612 data = qlcnic_ind_rd(adapter, pollrd->read_addr);
613 *buffer++ = cpu_to_le32(sel_val);
614 *buffer++ = cpu_to_le32(data);
615 sel_val += pollrd->sel_val_stride;
617 return pollrd->no_ops * (2 * sizeof(u32));
620 static u32 qlcnic_read_mux2(struct qlcnic_adapter *adapter,
621 struct qlcnic_dump_entry *entry, __le32 *buffer)
623 struct __mux2 *mux2 = &entry->region.mux2;
625 u32 t_sel_val, sel_val1, sel_val2;
628 sel_val1 = mux2->sel_val1;
629 sel_val2 = mux2->sel_val2;
631 for (i = 0; i < mux2->no_ops; i++) {
632 qlcnic_ind_wr(adapter, mux2->sel_addr1, sel_val1);
633 t_sel_val = sel_val1 & mux2->sel_val_mask;
634 qlcnic_ind_wr(adapter, mux2->sel_addr2, t_sel_val);
635 data = qlcnic_ind_rd(adapter, mux2->read_addr);
636 *buffer++ = cpu_to_le32(t_sel_val);
637 *buffer++ = cpu_to_le32(data);
638 qlcnic_ind_wr(adapter, mux2->sel_addr1, sel_val2);
639 t_sel_val = sel_val2 & mux2->sel_val_mask;
640 qlcnic_ind_wr(adapter, mux2->sel_addr2, t_sel_val);
641 data = qlcnic_ind_rd(adapter, mux2->read_addr);
642 *buffer++ = cpu_to_le32(t_sel_val);
643 *buffer++ = cpu_to_le32(data);
644 sel_val1 += mux2->sel_val_stride;
645 sel_val2 += mux2->sel_val_stride;
648 return mux2->no_ops * (4 * sizeof(u32));
651 static u32 qlcnic_83xx_dump_rom(struct qlcnic_adapter *adapter,
652 struct qlcnic_dump_entry *entry, __le32 *buffer)
655 struct __mem *rom = &entry->region.mem;
658 size = rom->size / 4;
660 if (!qlcnic_83xx_lockless_flash_read32(adapter, fl_addr,
667 static const struct qlcnic_dump_operations qlcnic_fw_dump_ops[] = {
668 {QLCNIC_DUMP_NOP, qlcnic_dump_nop},
669 {QLCNIC_DUMP_READ_CRB, qlcnic_dump_crb},
670 {QLCNIC_DUMP_READ_MUX, qlcnic_dump_mux},
671 {QLCNIC_DUMP_QUEUE, qlcnic_dump_que},
672 {QLCNIC_DUMP_BRD_CONFIG, qlcnic_read_rom},
673 {QLCNIC_DUMP_READ_OCM, qlcnic_dump_ocm},
674 {QLCNIC_DUMP_PEG_REG, qlcnic_dump_ctrl},
675 {QLCNIC_DUMP_L1_DTAG, qlcnic_dump_l1_cache},
676 {QLCNIC_DUMP_L1_ITAG, qlcnic_dump_l1_cache},
677 {QLCNIC_DUMP_L1_DATA, qlcnic_dump_l1_cache},
678 {QLCNIC_DUMP_L1_INST, qlcnic_dump_l1_cache},
679 {QLCNIC_DUMP_L2_DTAG, qlcnic_dump_l2_cache},
680 {QLCNIC_DUMP_L2_ITAG, qlcnic_dump_l2_cache},
681 {QLCNIC_DUMP_L2_DATA, qlcnic_dump_l2_cache},
682 {QLCNIC_DUMP_L2_INST, qlcnic_dump_l2_cache},
683 {QLCNIC_DUMP_READ_ROM, qlcnic_read_rom},
684 {QLCNIC_DUMP_READ_MEM, qlcnic_read_memory},
685 {QLCNIC_DUMP_READ_CTRL, qlcnic_dump_ctrl},
686 {QLCNIC_DUMP_TLHDR, qlcnic_dump_nop},
687 {QLCNIC_DUMP_RDEND, qlcnic_dump_nop},
690 static const struct qlcnic_dump_operations qlcnic_83xx_fw_dump_ops[] = {
691 {QLCNIC_DUMP_NOP, qlcnic_dump_nop},
692 {QLCNIC_DUMP_READ_CRB, qlcnic_dump_crb},
693 {QLCNIC_DUMP_READ_MUX, qlcnic_dump_mux},
694 {QLCNIC_DUMP_QUEUE, qlcnic_dump_que},
695 {QLCNIC_DUMP_BRD_CONFIG, qlcnic_83xx_dump_rom},
696 {QLCNIC_DUMP_READ_OCM, qlcnic_dump_ocm},
697 {QLCNIC_DUMP_PEG_REG, qlcnic_dump_ctrl},
698 {QLCNIC_DUMP_L1_DTAG, qlcnic_dump_l1_cache},
699 {QLCNIC_DUMP_L1_ITAG, qlcnic_dump_l1_cache},
700 {QLCNIC_DUMP_L1_DATA, qlcnic_dump_l1_cache},
701 {QLCNIC_DUMP_L1_INST, qlcnic_dump_l1_cache},
702 {QLCNIC_DUMP_L2_DTAG, qlcnic_dump_l2_cache},
703 {QLCNIC_DUMP_L2_ITAG, qlcnic_dump_l2_cache},
704 {QLCNIC_DUMP_L2_DATA, qlcnic_dump_l2_cache},
705 {QLCNIC_DUMP_L2_INST, qlcnic_dump_l2_cache},
706 {QLCNIC_DUMP_POLL_RD, qlcnic_read_pollrd},
707 {QLCNIC_READ_MUX2, qlcnic_read_mux2},
708 {QLCNIC_READ_POLLRDMWR, qlcnic_read_pollrdmwr},
709 {QLCNIC_DUMP_READ_ROM, qlcnic_83xx_dump_rom},
710 {QLCNIC_DUMP_READ_MEM, qlcnic_read_memory},
711 {QLCNIC_DUMP_READ_CTRL, qlcnic_dump_ctrl},
712 {QLCNIC_DUMP_TLHDR, qlcnic_dump_nop},
713 {QLCNIC_DUMP_RDEND, qlcnic_dump_nop},
716 static uint32_t qlcnic_temp_checksum(uint32_t *temp_buffer, u32 temp_size)
719 int count = temp_size / sizeof(uint32_t);
721 sum += *temp_buffer++;
723 sum = (sum & 0xFFFFFFFF) + (sum >> 32);
727 static int qlcnic_fw_flash_get_minidump_temp(struct qlcnic_adapter *adapter,
728 u8 *buffer, u32 size)
732 if (qlcnic_82xx_check(adapter))
735 if (qlcnic_83xx_lock_flash(adapter))
738 ret = qlcnic_83xx_lockless_flash_read32(adapter,
739 QLC_83XX_MINIDUMP_FLASH,
740 buffer, size / sizeof(u32));
742 qlcnic_83xx_unlock_flash(adapter);
748 qlcnic_fw_flash_get_minidump_temp_size(struct qlcnic_adapter *adapter,
749 struct qlcnic_cmd_args *cmd)
751 struct qlcnic_dump_template_hdr tmp_hdr;
752 u32 size = sizeof(struct qlcnic_dump_template_hdr) / sizeof(u32);
755 if (qlcnic_82xx_check(adapter))
758 if (qlcnic_83xx_lock_flash(adapter))
761 ret = qlcnic_83xx_lockless_flash_read32(adapter,
762 QLC_83XX_MINIDUMP_FLASH,
763 (u8 *)&tmp_hdr, size);
765 qlcnic_83xx_unlock_flash(adapter);
767 cmd->rsp.arg[2] = tmp_hdr.size;
768 cmd->rsp.arg[3] = tmp_hdr.version;
773 static int qlcnic_fw_get_minidump_temp_size(struct qlcnic_adapter *adapter,
774 u32 *version, u32 *temp_size,
778 struct qlcnic_cmd_args cmd;
780 if (qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_TEMP_SIZE))
783 err = qlcnic_issue_cmd(adapter, &cmd);
784 if (err != QLCNIC_RCODE_SUCCESS) {
785 if (qlcnic_fw_flash_get_minidump_temp_size(adapter, &cmd)) {
786 qlcnic_free_mbx_args(&cmd);
792 *temp_size = cmd.rsp.arg[2];
793 *version = cmd.rsp.arg[3];
794 qlcnic_free_mbx_args(&cmd);
802 static int __qlcnic_fw_cmd_get_minidump_temp(struct qlcnic_adapter *adapter,
803 u32 *buffer, u32 temp_size)
808 struct qlcnic_cmd_args cmd;
809 dma_addr_t tmp_addr_t = 0;
811 tmp_addr = dma_alloc_coherent(&adapter->pdev->dev, temp_size,
812 &tmp_addr_t, GFP_KERNEL);
816 if (qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_TEMP_HDR)) {
821 cmd.req.arg[1] = LSD(tmp_addr_t);
822 cmd.req.arg[2] = MSD(tmp_addr_t);
823 cmd.req.arg[3] = temp_size;
824 err = qlcnic_issue_cmd(adapter, &cmd);
827 if (err == QLCNIC_RCODE_SUCCESS) {
828 for (i = 0; i < temp_size / sizeof(u32); i++)
829 *buffer++ = __le32_to_cpu(*tmp_buf++);
832 qlcnic_free_mbx_args(&cmd);
835 dma_free_coherent(&adapter->pdev->dev, temp_size, tmp_addr, tmp_addr_t);
840 int qlcnic_fw_cmd_get_minidump_temp(struct qlcnic_adapter *adapter)
844 u32 version, csum, *tmp_buf;
845 struct qlcnic_hardware_context *ahw;
846 struct qlcnic_dump_template_hdr *tmpl_hdr;
847 u8 use_flash_temp = 0;
851 err = qlcnic_fw_get_minidump_temp_size(adapter, &version, &temp_size,
854 dev_err(&adapter->pdev->dev,
855 "Can't get template size %d\n", err);
859 ahw->fw_dump.tmpl_hdr = vzalloc(temp_size);
860 if (!ahw->fw_dump.tmpl_hdr)
863 tmp_buf = (u32 *)ahw->fw_dump.tmpl_hdr;
867 err = __qlcnic_fw_cmd_get_minidump_temp(adapter, tmp_buf, temp_size);
871 err = qlcnic_fw_flash_get_minidump_temp(adapter, (u8 *)tmp_buf,
875 dev_err(&adapter->pdev->dev,
876 "Failed to get minidump template header %d\n",
878 vfree(ahw->fw_dump.tmpl_hdr);
879 ahw->fw_dump.tmpl_hdr = NULL;
884 csum = qlcnic_temp_checksum((uint32_t *)tmp_buf, temp_size);
887 dev_err(&adapter->pdev->dev,
888 "Template header checksum validation failed\n");
889 vfree(ahw->fw_dump.tmpl_hdr);
890 ahw->fw_dump.tmpl_hdr = NULL;
894 tmpl_hdr = ahw->fw_dump.tmpl_hdr;
895 tmpl_hdr->drv_cap_mask = QLCNIC_DUMP_MASK_DEF;
896 ahw->fw_dump.enable = 1;
901 int qlcnic_dump_fw(struct qlcnic_adapter *adapter)
906 char *msg[] = {mesg, NULL};
907 int i, k, ops_cnt, ops_index, dump_size = 0;
908 u32 entry_offset, dump, no_entries, buf_offset = 0;
909 struct qlcnic_dump_entry *entry;
910 struct qlcnic_fw_dump *fw_dump = &adapter->ahw->fw_dump;
911 struct qlcnic_dump_template_hdr *tmpl_hdr = fw_dump->tmpl_hdr;
912 static const struct qlcnic_dump_operations *fw_dump_ops;
913 struct qlcnic_hardware_context *ahw;
917 if (!fw_dump->enable) {
918 dev_info(&adapter->pdev->dev, "Dump not enabled\n");
923 dev_info(&adapter->pdev->dev,
924 "Previous dump not cleared, not capturing dump\n");
928 netif_info(adapter->ahw, drv, adapter->netdev, "Take FW dump\n");
929 /* Calculate the size for dump data area only */
930 for (i = 2, k = 1; (i & QLCNIC_DUMP_MASK_MAX); i <<= 1, k++)
931 if (i & tmpl_hdr->drv_cap_mask)
932 dump_size += tmpl_hdr->cap_sizes[k];
936 fw_dump->data = vzalloc(dump_size);
940 buffer = fw_dump->data;
941 fw_dump->size = dump_size;
942 no_entries = tmpl_hdr->num_entries;
943 entry_offset = tmpl_hdr->offset;
944 tmpl_hdr->sys_info[0] = QLCNIC_DRIVER_VERSION;
945 tmpl_hdr->sys_info[1] = adapter->fw_version;
947 if (qlcnic_82xx_check(adapter)) {
948 ops_cnt = ARRAY_SIZE(qlcnic_fw_dump_ops);
949 fw_dump_ops = qlcnic_fw_dump_ops;
951 ops_cnt = ARRAY_SIZE(qlcnic_83xx_fw_dump_ops);
952 fw_dump_ops = qlcnic_83xx_fw_dump_ops;
953 ocm_window = tmpl_hdr->ocm_wnd_reg[adapter->ahw->pci_func];
954 tmpl_hdr->saved_state[QLC_83XX_OCM_INDEX] = ocm_window;
955 tmpl_hdr->saved_state[QLC_83XX_PCI_INDEX] = ahw->pci_func;
958 for (i = 0; i < no_entries; i++) {
959 entry = (void *)tmpl_hdr + entry_offset;
960 if (!(entry->hdr.mask & tmpl_hdr->drv_cap_mask)) {
961 entry->hdr.flags |= QLCNIC_DUMP_SKIP;
962 entry_offset += entry->hdr.offset;
966 /* Find the handler for this entry */
968 while (ops_index < ops_cnt) {
969 if (entry->hdr.type == fw_dump_ops[ops_index].opcode)
974 if (ops_index == ops_cnt) {
975 dev_info(&adapter->pdev->dev,
976 "Invalid entry type %d, exiting dump\n",
981 /* Collect dump for this entry */
982 dump = fw_dump_ops[ops_index].handler(adapter, entry, buffer);
983 if (!qlcnic_valid_dump_entry(&adapter->pdev->dev, entry, dump))
984 entry->hdr.flags |= QLCNIC_DUMP_SKIP;
985 buf_offset += entry->hdr.cap_size;
986 entry_offset += entry->hdr.offset;
987 buffer = fw_dump->data + buf_offset;
989 if (dump_size != buf_offset) {
990 dev_info(&adapter->pdev->dev,
991 "Captured(%d) and expected size(%d) do not match\n",
992 buf_offset, dump_size);
996 snprintf(mesg, sizeof(mesg), "FW_DUMP=%s",
997 adapter->netdev->name);
998 dev_info(&adapter->pdev->dev, "%s: Dump data, %d bytes captured\n",
999 adapter->netdev->name, fw_dump->size);
1000 /* Send a udev event to notify availability of FW dump */
1001 kobject_uevent_env(&adapter->pdev->dev.kobj, KOBJ_CHANGE, msg);
1005 vfree(fw_dump->data);
1009 void qlcnic_83xx_get_minidump_template(struct qlcnic_adapter *adapter)
1011 u32 prev_version, current_version;
1012 struct qlcnic_hardware_context *ahw = adapter->ahw;
1013 struct qlcnic_fw_dump *fw_dump = &ahw->fw_dump;
1014 struct pci_dev *pdev = adapter->pdev;
1016 prev_version = adapter->fw_version;
1017 current_version = qlcnic_83xx_get_fw_version(adapter);
1019 if (fw_dump->tmpl_hdr == NULL || current_version > prev_version) {
1020 if (fw_dump->tmpl_hdr)
1021 vfree(fw_dump->tmpl_hdr);
1022 if (!qlcnic_fw_cmd_get_minidump_temp(adapter))
1023 dev_info(&pdev->dev, "Supports FW dump capability\n");