drivers/net/ethernet/realtek/r8169.c

   1 /*
   2  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   3  *
   4  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   5  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   6  * Copyright (c) a lot of people too. Please respect their work.
   7  *
   8  * See MAINTAINERS file for support contact information.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/moduleparam.h>
  13 #include <linux/pci.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/delay.h>
  17 #include <linux/ethtool.h>
  18 #include <linux/mii.h>
  19 #include <linux/if_vlan.h>
  20 #include <linux/crc32.h>
  21 #include <linux/in.h>
  22 #include <linux/ip.h>
  23 #include <linux/tcp.h>
  24 #include <linux/init.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/pm_runtime.h>
  28 #include <linux/firmware.h>
  29 #include <linux/pci-aspm.h>
  30 #include <linux/prefetch.h>
  31
  32 #include <asm/io.h>
  33 #include <asm/irq.h>
  34
  35 #define RTL8169_VERSION "2.3LK-NAPI"
  36 #define MODULENAME "r8169"
  37 #define PFX MODULENAME ": "
  38
  39 #define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
  40 #define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
  41 #define FIRMWARE_8168E_1        "rtl_nic/rtl8168e-1.fw"
  42 #define FIRMWARE_8168E_2        "rtl_nic/rtl8168e-2.fw"
  43 #define FIRMWARE_8168E_3        "rtl_nic/rtl8168e-3.fw"
  44 #define FIRMWARE_8168F_1        "rtl_nic/rtl8168f-1.fw"
  45 #define FIRMWARE_8168F_2        "rtl_nic/rtl8168f-2.fw"
  46 #define FIRMWARE_8105E_1        "rtl_nic/rtl8105e-1.fw"
  47 #define FIRMWARE_8402_1         "rtl_nic/rtl8402-1.fw"
  48 #define FIRMWARE_8411_1         "rtl_nic/rtl8411-1.fw"
  49 #define FIRMWARE_8106E_1        "rtl_nic/rtl8106e-1.fw"
  50 #define FIRMWARE_8168G_1        "rtl_nic/rtl8168g-1.fw"
  51
  52 #ifdef RTL8169_DEBUG
  53 #define assert(expr) \
  54         if (!(expr)) {                                  \
  55                 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
  56                 #expr,__FILE__,__func__,__LINE__);              \
  57         }
  58 #define dprintk(fmt, args...) \
  59         do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
  60 #else
  61 #define assert(expr) do {} while (0)
  62 #define dprintk(fmt, args...)   do {} while (0)
  63 #endif /* RTL8169_DEBUG */
  64
  65 #define R8169_MSG_DEFAULT \
  66         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  67
  68 #define TX_SLOTS_AVAIL(tp) \
  69         (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
  70
  71 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
  72 #define TX_FRAGS_READY_FOR(tp,nr_frags) \
  73         (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
  74
  75 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  76    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  77 static const int multicast_filter_limit = 32;
  78
  79 #define MAX_READ_REQUEST_SHIFT  12
  80 #define TX_DMA_BURST    7       /* Maximum PCI burst, '7' is unlimited */
  81 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  82
  83 #define R8169_REGS_SIZE         256
  84 #define R8169_NAPI_WEIGHT       64
  85 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
  86 #define NUM_RX_DESC     256     /* Number of Rx descriptor registers */
  87 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  88 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  89
  90 #define RTL8169_TX_TIMEOUT      (6*HZ)
  91 #define RTL8169_PHY_TIMEOUT     (10*HZ)
  92
  93 /* write/read MMIO register */
  94 #define RTL_W8(reg, val8)       writeb ((val8), ioaddr + (reg))
  95 #define RTL_W16(reg, val16)     writew ((val16), ioaddr + (reg))
  96 #define RTL_W32(reg, val32)     writel ((val32), ioaddr + (reg))
  97 #define RTL_R8(reg)             readb (ioaddr + (reg))
  98 #define RTL_R16(reg)            readw (ioaddr + (reg))
  99 #define RTL_R32(reg)            readl (ioaddr + (reg))
 100
 101 enum mac_version {
 102         RTL_GIGA_MAC_VER_01 = 0,
 103         RTL_GIGA_MAC_VER_02,
 104         RTL_GIGA_MAC_VER_03,
 105         RTL_GIGA_MAC_VER_04,
 106         RTL_GIGA_MAC_VER_05,
 107         RTL_GIGA_MAC_VER_06,
 108         RTL_GIGA_MAC_VER_07,
 109         RTL_GIGA_MAC_VER_08,
 110         RTL_GIGA_MAC_VER_09,
 111         RTL_GIGA_MAC_VER_10,
 112         RTL_GIGA_MAC_VER_11,
 113         RTL_GIGA_MAC_VER_12,
 114         RTL_GIGA_MAC_VER_13,
 115         RTL_GIGA_MAC_VER_14,
 116         RTL_GIGA_MAC_VER_15,
 117         RTL_GIGA_MAC_VER_16,
 118         RTL_GIGA_MAC_VER_17,
 119         RTL_GIGA_MAC_VER_18,
 120         RTL_GIGA_MAC_VER_19,
 121         RTL_GIGA_MAC_VER_20,
 122         RTL_GIGA_MAC_VER_21,
 123         RTL_GIGA_MAC_VER_22,
 124         RTL_GIGA_MAC_VER_23,
 125         RTL_GIGA_MAC_VER_24,
 126         RTL_GIGA_MAC_VER_25,
 127         RTL_GIGA_MAC_VER_26,
 128         RTL_GIGA_MAC_VER_27,
 129         RTL_GIGA_MAC_VER_28,
 130         RTL_GIGA_MAC_VER_29,
 131         RTL_GIGA_MAC_VER_30,
 132         RTL_GIGA_MAC_VER_31,
 133         RTL_GIGA_MAC_VER_32,
 134         RTL_GIGA_MAC_VER_33,
 135         RTL_GIGA_MAC_VER_34,
 136         RTL_GIGA_MAC_VER_35,
 137         RTL_GIGA_MAC_VER_36,
 138         RTL_GIGA_MAC_VER_37,
 139         RTL_GIGA_MAC_VER_38,
 140         RTL_GIGA_MAC_VER_39,
 141         RTL_GIGA_MAC_VER_40,
 142         RTL_GIGA_MAC_VER_41,
 143         RTL_GIGA_MAC_NONE   = 0xff,
 144 };
 145
 146 enum rtl_tx_desc_version {
 147         RTL_TD_0        = 0,
 148         RTL_TD_1        = 1,
 149 };
 150
 151 #define JUMBO_1K        ETH_DATA_LEN
 152 #define JUMBO_4K        (4*1024 - ETH_HLEN - 2)
 153 #define JUMBO_6K        (6*1024 - ETH_HLEN - 2)
 154 #define JUMBO_7K        (7*1024 - ETH_HLEN - 2)
 155 #define JUMBO_9K        (9*1024 - ETH_HLEN - 2)
 156
 157 #define _R(NAME,TD,FW,SZ,B) {   \
 158         .name = NAME,           \
 159         .txd_version = TD,      \
 160         .fw_name = FW,          \
 161         .jumbo_max = SZ,        \
 162         .jumbo_tx_csum = B      \
 163 }
 164
 165 static const struct {
 166         const char *name;
 167         enum rtl_tx_desc_version txd_version;
 168         const char *fw_name;
 169         u16 jumbo_max;
 170         bool jumbo_tx_csum;
 171 } rtl_chip_infos[] = {
 172         /* PCI devices. */
 173         [RTL_GIGA_MAC_VER_01] =
 174                 _R("RTL8169",           RTL_TD_0, NULL, JUMBO_7K, true),
 175         [RTL_GIGA_MAC_VER_02] =
 176                 _R("RTL8169s",          RTL_TD_0, NULL, JUMBO_7K, true),
 177         [RTL_GIGA_MAC_VER_03] =
 178                 _R("RTL8110s",          RTL_TD_0, NULL, JUMBO_7K, true),
 179         [RTL_GIGA_MAC_VER_04] =
 180                 _R("RTL8169sb/8110sb",  RTL_TD_0, NULL, JUMBO_7K, true),
 181         [RTL_GIGA_MAC_VER_05] =
 182                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL, JUMBO_7K, true),
 183         [RTL_GIGA_MAC_VER_06] =
 184                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL, JUMBO_7K, true),
 185         /* PCI-E devices. */
 186         [RTL_GIGA_MAC_VER_07] =
 187                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 188         [RTL_GIGA_MAC_VER_08] =
 189                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 190         [RTL_GIGA_MAC_VER_09] =
 191                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 192         [RTL_GIGA_MAC_VER_10] =
 193                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 194         [RTL_GIGA_MAC_VER_11] =
 195                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K, false),
 196         [RTL_GIGA_MAC_VER_12] =
 197                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K, false),
 198         [RTL_GIGA_MAC_VER_13] =
 199                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 200         [RTL_GIGA_MAC_VER_14] =
 201                 _R("RTL8100e",          RTL_TD_0, NULL, JUMBO_1K, true),
 202         [RTL_GIGA_MAC_VER_15] =
 203                 _R("RTL8100e",          RTL_TD_0, NULL, JUMBO_1K, true),
 204         [RTL_GIGA_MAC_VER_16] =
 205                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 206         [RTL_GIGA_MAC_VER_17] =
 207                 _R("RTL8168b/8111b",    RTL_TD_1, NULL, JUMBO_4K, false),
 208         [RTL_GIGA_MAC_VER_18] =
 209                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 210         [RTL_GIGA_MAC_VER_19] =
 211                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 212         [RTL_GIGA_MAC_VER_20] =
 213                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 214         [RTL_GIGA_MAC_VER_21] =
 215                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 216         [RTL_GIGA_MAC_VER_22] =
 217                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 218         [RTL_GIGA_MAC_VER_23] =
 219                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 220         [RTL_GIGA_MAC_VER_24] =
 221                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 222         [RTL_GIGA_MAC_VER_25] =
 223                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_1,
 224                                                         JUMBO_9K, false),
 225         [RTL_GIGA_MAC_VER_26] =
 226                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_2,
 227                                                         JUMBO_9K, false),
 228         [RTL_GIGA_MAC_VER_27] =
 229                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 230         [RTL_GIGA_MAC_VER_28] =
 231                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 232         [RTL_GIGA_MAC_VER_29] =
 233                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1,
 234                                                         JUMBO_1K, true),
 235         [RTL_GIGA_MAC_VER_30] =
 236                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1,
 237                                                         JUMBO_1K, true),
 238         [RTL_GIGA_MAC_VER_31] =
 239                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 240         [RTL_GIGA_MAC_VER_32] =
 241                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_1,
 242                                                         JUMBO_9K, false),
 243         [RTL_GIGA_MAC_VER_33] =
 244                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_2,
 245                                                         JUMBO_9K, false),
 246         [RTL_GIGA_MAC_VER_34] =
 247                 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3,
 248                                                         JUMBO_9K, false),
 249         [RTL_GIGA_MAC_VER_35] =
 250                 _R("RTL8168f/8111f",    RTL_TD_1, FIRMWARE_8168F_1,
 251                                                         JUMBO_9K, false),
 252         [RTL_GIGA_MAC_VER_36] =
 253                 _R("RTL8168f/8111f",    RTL_TD_1, FIRMWARE_8168F_2,
 254                                                         JUMBO_9K, false),
 255         [RTL_GIGA_MAC_VER_37] =
 256                 _R("RTL8402",           RTL_TD_1, FIRMWARE_8402_1,
 257                                                         JUMBO_1K, true),
 258         [RTL_GIGA_MAC_VER_38] =
 259                 _R("RTL8411",           RTL_TD_1, FIRMWARE_8411_1,
 260                                                         JUMBO_9K, false),
 261         [RTL_GIGA_MAC_VER_39] =
 262                 _R("RTL8106e",          RTL_TD_1, FIRMWARE_8106E_1,
 263                                                         JUMBO_1K, true),
 264         [RTL_GIGA_MAC_VER_40] =
 265                 _R("RTL8168g/8111g",    RTL_TD_1, FIRMWARE_8168G_1,
 266                                                         JUMBO_9K, false),
 267         [RTL_GIGA_MAC_VER_41] =
 268                 _R("RTL8168g/8111g",    RTL_TD_1, NULL, JUMBO_9K, false),
 269 };
 270 #undef _R
 271
 272 enum cfg_version {
 273         RTL_CFG_0 = 0x00,
 274         RTL_CFG_1,
 275         RTL_CFG_2
 276 };
 277
 278 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
 279         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8129), 0, 0, RTL_CFG_0 },
 280         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8136), 0, 0, RTL_CFG_2 },
 281         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8167), 0, 0, RTL_CFG_0 },
 282         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8168), 0, 0, RTL_CFG_1 },
 283         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8169), 0, 0, RTL_CFG_0 },
 284         { PCI_VENDOR_ID_DLINK,                  0x4300,
 285                 PCI_VENDOR_ID_DLINK, 0x4b10,             0, 0, RTL_CFG_1 },
 286         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4300), 0, 0, RTL_CFG_0 },
 287         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4302), 0, 0, RTL_CFG_0 },
 288         { PCI_DEVICE(PCI_VENDOR_ID_AT,          0xc107), 0, 0, RTL_CFG_0 },
 289         { PCI_DEVICE(0x16ec,                    0x0116), 0, 0, RTL_CFG_0 },
 290         { PCI_VENDOR_ID_LINKSYS,                0x1032,
 291                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
 292         { 0x0001,                               0x8168,
 293                 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
 294         {0,},
 295 };
 296
 297 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 298
 299 static int rx_buf_sz = 16383;
 300 static int use_dac;
 301 static struct {
 302         u32 msg_enable;
 303 } debug = { -1 };
 304
 305 enum rtl_registers {
 306         MAC0            = 0,    /* Ethernet hardware address. */
 307         MAC4            = 4,
 308         MAR0            = 8,    /* Multicast filter. */
 309         CounterAddrLow          = 0x10,
 310         CounterAddrHigh         = 0x14,
 311         TxDescStartAddrLow      = 0x20,
 312         TxDescStartAddrHigh     = 0x24,
 313         TxHDescStartAddrLow     = 0x28,
 314         TxHDescStartAddrHigh    = 0x2c,
 315         FLASH           = 0x30,
 316         ERSR            = 0x36,
 317         ChipCmd         = 0x37,
 318         TxPoll          = 0x38,
 319         IntrMask        = 0x3c,
 320         IntrStatus      = 0x3e,
 321
 322         TxConfig        = 0x40,
 323 #define TXCFG_AUTO_FIFO                 (1 << 7)        /* 8111e-vl */
 324 #define TXCFG_EMPTY                     (1 << 11)       /* 8111e-vl */
 325
 326         RxConfig        = 0x44,
 327 #define RX128_INT_EN                    (1 << 15)       /* 8111c and later */
 328 #define RX_MULTI_EN                     (1 << 14)       /* 8111c only */
 329 #define RXCFG_FIFO_SHIFT                13
 330                                         /* No threshold before first PCI xfer */
 331 #define RX_FIFO_THRESH                  (7 << RXCFG_FIFO_SHIFT)
 332 #define RXCFG_DMA_SHIFT                 8
 333                                         /* Unlimited maximum PCI burst. */
 334 #define RX_DMA_BURST                    (7 << RXCFG_DMA_SHIFT)
 335
 336         RxMissed        = 0x4c,
 337         Cfg9346         = 0x50,
 338         Config0         = 0x51,
 339         Config1         = 0x52,
 340         Config2         = 0x53,
 341 #define PME_SIGNAL                      (1 << 5)        /* 8168c and later */
 342
 343         Config3         = 0x54,
 344         Config4         = 0x55,
 345         Config5         = 0x56,
 346         MultiIntr       = 0x5c,
 347         PHYAR           = 0x60,
 348         PHYstatus       = 0x6c,
 349         RxMaxSize       = 0xda,
 350         CPlusCmd        = 0xe0,
 351         IntrMitigate    = 0xe2,
 352         RxDescAddrLow   = 0xe4,
 353         RxDescAddrHigh  = 0xe8,
 354         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
 355
 356 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
 357
 358         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
 359
 360 #define TxPacketMax     (8064 >> 7)
 361 #define EarlySize       0x27
 362
 363         FuncEvent       = 0xf0,
 364         FuncEventMask   = 0xf4,
 365         FuncPresetState = 0xf8,
 366         FuncForceEvent  = 0xfc,
 367 };
 368
 369 enum rtl8110_registers {
 370         TBICSR                  = 0x64,
 371         TBI_ANAR                = 0x68,
 372         TBI_LPAR                = 0x6a,
 373 };
 374
 375 enum rtl8168_8101_registers {
 376         CSIDR                   = 0x64,
 377         CSIAR                   = 0x68,
 378 #define CSIAR_FLAG                      0x80000000
 379 #define CSIAR_WRITE_CMD                 0x80000000
 380 #define CSIAR_BYTE_ENABLE               0x0f
 381 #define CSIAR_BYTE_ENABLE_SHIFT         12
 382 #define CSIAR_ADDR_MASK                 0x0fff
 383 #define CSIAR_FUNC_CARD                 0x00000000
 384 #define CSIAR_FUNC_SDIO                 0x00010000
 385 #define CSIAR_FUNC_NIC                  0x00020000
 386         PMCH                    = 0x6f,
 387         EPHYAR                  = 0x80,
 388 #define EPHYAR_FLAG                     0x80000000
 389 #define EPHYAR_WRITE_CMD                0x80000000
 390 #define EPHYAR_REG_MASK                 0x1f
 391 #define EPHYAR_REG_SHIFT                16
 392 #define EPHYAR_DATA_MASK                0xffff
 393         DLLPR                   = 0xd0,
 394 #define PFM_EN                          (1 << 6)
 395         DBG_REG                 = 0xd1,
 396 #define FIX_NAK_1                       (1 << 4)
 397 #define FIX_NAK_2                       (1 << 3)
 398         TWSI                    = 0xd2,
 399         MCU                     = 0xd3,
 400 #define NOW_IS_OOB                      (1 << 7)
 401 #define TX_EMPTY                        (1 << 5)
 402 #define RX_EMPTY                        (1 << 4)
 403 #define RXTX_EMPTY                      (TX_EMPTY | RX_EMPTY)
 404 #define EN_NDP                          (1 << 3)
 405 #define EN_OOB_RESET                    (1 << 2)
 406 #define LINK_LIST_RDY                   (1 << 1)
 407         EFUSEAR                 = 0xdc,
 408 #define EFUSEAR_FLAG                    0x80000000
 409 #define EFUSEAR_WRITE_CMD               0x80000000
 410 #define EFUSEAR_READ_CMD                0x00000000
 411 #define EFUSEAR_REG_MASK                0x03ff
 412 #define EFUSEAR_REG_SHIFT               8
 413 #define EFUSEAR_DATA_MASK               0xff
 414 };
 415
 416 enum rtl8168_registers {
 417         LED_FREQ                = 0x1a,
 418         EEE_LED                 = 0x1b,
 419         ERIDR                   = 0x70,
 420         ERIAR                   = 0x74,
 421 #define ERIAR_FLAG                      0x80000000
 422 #define ERIAR_WRITE_CMD                 0x80000000
 423 #define ERIAR_READ_CMD                  0x00000000
 424 #define ERIAR_ADDR_BYTE_ALIGN           4
 425 #define ERIAR_TYPE_SHIFT                16
 426 #define ERIAR_EXGMAC                    (0x00 << ERIAR_TYPE_SHIFT)
 427 #define ERIAR_MSIX                      (0x01 << ERIAR_TYPE_SHIFT)
 428 #define ERIAR_ASF                       (0x02 << ERIAR_TYPE_SHIFT)
 429 #define ERIAR_MASK_SHIFT                12
 430 #define ERIAR_MASK_0001                 (0x1 << ERIAR_MASK_SHIFT)
 431 #define ERIAR_MASK_0011                 (0x3 << ERIAR_MASK_SHIFT)
 432 #define ERIAR_MASK_0101                 (0x5 << ERIAR_MASK_SHIFT)
 433 #define ERIAR_MASK_1111                 (0xf << ERIAR_MASK_SHIFT)
 434         EPHY_RXER_NUM           = 0x7c,
 435         OCPDR                   = 0xb0, /* OCP GPHY access */
 436 #define OCPDR_WRITE_CMD                 0x80000000
 437 #define OCPDR_READ_CMD                  0x00000000
 438 #define OCPDR_REG_MASK                  0x7f
 439 #define OCPDR_GPHY_REG_SHIFT            16
 440 #define OCPDR_DATA_MASK                 0xffff
 441         OCPAR                   = 0xb4,
 442 #define OCPAR_FLAG                      0x80000000
 443 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
 444 #define OCPAR_GPHY_READ_CMD             0x0000f060
 445         GPHY_OCP                = 0xb8,
 446         RDSAR1                  = 0xd0, /* 8168c only. Undocumented on 8168dp */
 447         MISC                    = 0xf0, /* 8168e only. */
 448 #define TXPLA_RST                       (1 << 29)
 449 #define DISABLE_LAN_EN                  (1 << 23) /* Enable GPIO pin */
 450 #define PWM_EN                          (1 << 22)
 451 #define RXDV_GATED_EN                   (1 << 19)
 452 #define EARLY_TALLY_EN                  (1 << 16)
 453 #define FORCE_CLK                       (1 << 15) /* force clock request */
 454 };
 455
 456 enum rtl_register_content {
 457         /* InterruptStatusBits */
 458         SYSErr          = 0x8000,
 459         PCSTimeout      = 0x4000,
 460         SWInt           = 0x0100,
 461         TxDescUnavail   = 0x0080,
 462         RxFIFOOver      = 0x0040,
 463         LinkChg         = 0x0020,
 464         RxOverflow      = 0x0010,
 465         TxErr           = 0x0008,
 466         TxOK            = 0x0004,
 467         RxErr           = 0x0002,
 468         RxOK            = 0x0001,
 469
 470         /* RxStatusDesc */
 471         RxBOVF  = (1 << 24),
 472         RxFOVF  = (1 << 23),
 473         RxRWT   = (1 << 22),
 474         RxRES   = (1 << 21),
 475         RxRUNT  = (1 << 20),
 476         RxCRC   = (1 << 19),
 477
 478         /* ChipCmdBits */
 479         StopReq         = 0x80,
 480         CmdReset        = 0x10,
 481         CmdRxEnb        = 0x08,
 482         CmdTxEnb        = 0x04,
 483         RxBufEmpty      = 0x01,
 484
 485         /* TXPoll register p.5 */
 486         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 487         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 488         FSWInt          = 0x01,         /* Forced software interrupt */
 489
 490         /* Cfg9346Bits */
 491         Cfg9346_Lock    = 0x00,
 492         Cfg9346_Unlock  = 0xc0,
 493
 494         /* rx_mode_bits */
 495         AcceptErr       = 0x20,
 496         AcceptRunt      = 0x10,
 497         AcceptBroadcast = 0x08,
 498         AcceptMulticast = 0x04,
 499         AcceptMyPhys    = 0x02,
 500         AcceptAllPhys   = 0x01,
 501 #define RX_CONFIG_ACCEPT_MASK           0x3f
 502
 503         /* TxConfigBits */
 504         TxInterFrameGapShift = 24,
 505         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 506
 507         /* Config1 register p.24 */
 508         LEDS1           = (1 << 7),
 509         LEDS0           = (1 << 6),
 510         Speed_down      = (1 << 4),
 511         MEMMAP          = (1 << 3),
 512         IOMAP           = (1 << 2),
 513         VPD             = (1 << 1),
 514         PMEnable        = (1 << 0),     /* Power Management Enable */
 515
 516         /* Config2 register p. 25 */
 517         ClkReqEn        = (1 << 7),     /* Clock Request Enable */
 518         MSIEnable       = (1 << 5),     /* 8169 only. Reserved in the 8168. */
 519         PCI_Clock_66MHz = 0x01,
 520         PCI_Clock_33MHz = 0x00,
 521
 522         /* Config3 register p.25 */
 523         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 524         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 525         Jumbo_En0       = (1 << 2),     /* 8168 only. Reserved in the 8168b */
 526         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
 527
 528         /* Config4 register */
 529         Jumbo_En1       = (1 << 1),     /* 8168 only. Reserved in the 8168b */
 530
 531         /* Config5 register p.27 */
 532         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 533         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 534         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 535         Spi_en          = (1 << 3),
 536         LanWake         = (1 << 1),     /* LanWake enable/disable */
 537         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 538         ASPM_en         = (1 << 0),     /* ASPM enable */
 539
 540         /* TBICSR p.28 */
 541         TBIReset        = 0x80000000,
 542         TBILoopback     = 0x40000000,
 543         TBINwEnable     = 0x20000000,
 544         TBINwRestart    = 0x10000000,
 545         TBILinkOk       = 0x02000000,
 546         TBINwComplete   = 0x01000000,
 547
 548         /* CPlusCmd p.31 */
 549         EnableBist      = (1 << 15),    // 8168 8101
 550         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
 551         Normal_mode     = (1 << 13),    // unused
 552         Force_half_dup  = (1 << 12),    // 8168 8101
 553         Force_rxflow_en = (1 << 11),    // 8168 8101
 554         Force_txflow_en = (1 << 10),    // 8168 8101
 555         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
 556         ASF             = (1 << 8),     // 8168 8101
 557         PktCntrDisable  = (1 << 7),     // 8168 8101
 558         Mac_dbgo_sel    = 0x001c,       // 8168
 559         RxVlan          = (1 << 6),
 560         RxChkSum        = (1 << 5),
 561         PCIDAC          = (1 << 4),
 562         PCIMulRW        = (1 << 3),
 563         INTT_0          = 0x0000,       // 8168
 564         INTT_1          = 0x0001,       // 8168
 565         INTT_2          = 0x0002,       // 8168
 566         INTT_3          = 0x0003,       // 8168
 567
 568         /* rtl8169_PHYstatus */
 569         TBI_Enable      = 0x80,
 570         TxFlowCtrl      = 0x40,
 571         RxFlowCtrl      = 0x20,
 572         _1000bpsF       = 0x10,
 573         _100bps         = 0x08,
 574         _10bps          = 0x04,
 575         LinkStatus      = 0x02,
 576         FullDup         = 0x01,
 577
 578         /* _TBICSRBit */
 579         TBILinkOK       = 0x02000000,
 580
 581         /* DumpCounterCommand */
 582         CounterDump     = 0x8,
 583 };
 584
 585 enum rtl_desc_bit {
 586         /* First doubleword. */
 587         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 588         RingEnd         = (1 << 30), /* End of descriptor ring */
 589         FirstFrag       = (1 << 29), /* First segment of a packet */
 590         LastFrag        = (1 << 28), /* Final segment of a packet */
 591 };
 592
 593 /* Generic case. */
 594 enum rtl_tx_desc_bit {
 595         /* First doubleword. */
 596         TD_LSO          = (1 << 27),            /* Large Send Offload */
 597 #define TD_MSS_MAX                      0x07ffu /* MSS value */
 598
 599         /* Second doubleword. */
 600         TxVlanTag       = (1 << 17),            /* Add VLAN tag */
 601 };
 602
 603 /* 8169, 8168b and 810x except 8102e. */
 604 enum rtl_tx_desc_bit_0 {
 605         /* First doubleword. */
 606 #define TD0_MSS_SHIFT                   16      /* MSS position (11 bits) */
 607         TD0_TCP_CS      = (1 << 16),            /* Calculate TCP/IP checksum */
 608         TD0_UDP_CS      = (1 << 17),            /* Calculate UDP/IP checksum */
 609         TD0_IP_CS       = (1 << 18),            /* Calculate IP checksum */
 610 };
 611
 612 /* 8102e, 8168c and beyond. */
 613 enum rtl_tx_desc_bit_1 {
 614         /* Second doubleword. */
 615 #define TD1_MSS_SHIFT                   18      /* MSS position (11 bits) */
 616         TD1_IP_CS       = (1 << 29),            /* Calculate IP checksum */
 617         TD1_TCP_CS      = (1 << 30),            /* Calculate TCP/IP checksum */
 618         TD1_UDP_CS      = (1 << 31),            /* Calculate UDP/IP checksum */
 619 };
 620
 621 static const struct rtl_tx_desc_info {
 622         struct {
 623                 u32 udp;
 624                 u32 tcp;
 625         } checksum;
 626         u16 mss_shift;
 627         u16 opts_offset;
 628 } tx_desc_info [] = {
 629         [RTL_TD_0] = {
 630                 .checksum = {
 631                         .udp    = TD0_IP_CS | TD0_UDP_CS,
 632                         .tcp    = TD0_IP_CS | TD0_TCP_CS
 633                 },
 634                 .mss_shift      = TD0_MSS_SHIFT,
 635                 .opts_offset    = 0
 636         },
 637         [RTL_TD_1] = {
 638                 .checksum = {
 639                         .udp    = TD1_IP_CS | TD1_UDP_CS,
 640                         .tcp    = TD1_IP_CS | TD1_TCP_CS
 641                 },
 642                 .mss_shift      = TD1_MSS_SHIFT,
 643                 .opts_offset    = 1
 644         }
 645 };
 646
 647 enum rtl_rx_desc_bit {
 648         /* Rx private */
 649         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 650         PID0            = (1 << 17), /* Protocol ID bit 2/2 */
 651
 652 #define RxProtoUDP      (PID1)
 653 #define RxProtoTCP      (PID0)
 654 #define RxProtoIP       (PID1 | PID0)
 655 #define RxProtoMask     RxProtoIP
 656
 657         IPFail          = (1 << 16), /* IP checksum failed */
 658         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 659         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 660         RxVlanTag       = (1 << 16), /* VLAN tag available */
 661 };
 662
 663 #define RsvdMask        0x3fffc000
 664
 665 struct TxDesc {
 666         __le32 opts1;
 667         __le32 opts2;
 668         __le64 addr;
 669 };
 670
 671 struct RxDesc {
 672         __le32 opts1;
 673         __le32 opts2;
 674         __le64 addr;
 675 };
 676
 677 struct ring_info {
 678         struct sk_buff  *skb;
 679         u32             len;
 680         u8              __pad[sizeof(void *) - sizeof(u32)];
 681 };
 682
 683 enum features {
 684         RTL_FEATURE_WOL         = (1 << 0),
 685         RTL_FEATURE_MSI         = (1 << 1),
 686         RTL_FEATURE_GMII        = (1 << 2),
 687 };
 688
 689 struct rtl8169_counters {
 690         __le64  tx_packets;
 691         __le64  rx_packets;
 692         __le64  tx_errors;
 693         __le32  rx_errors;
 694         __le16  rx_missed;
 695         __le16  align_errors;
 696         __le32  tx_one_collision;
 697         __le32  tx_multi_collision;
 698         __le64  rx_unicast;
 699         __le64  rx_broadcast;
 700         __le32  rx_multicast;
 701         __le16  tx_aborted;
 702         __le16  tx_underun;
 703 };
 704
 705 enum rtl_flag {
 706         RTL_FLAG_TASK_ENABLED,
 707         RTL_FLAG_TASK_SLOW_PENDING,
 708         RTL_FLAG_TASK_RESET_PENDING,
 709         RTL_FLAG_TASK_PHY_PENDING,
 710         RTL_FLAG_MAX
 711 };
 712
 713 struct rtl8169_stats {
 714         u64                     packets;
 715         u64                     bytes;
 716         struct u64_stats_sync   syncp;
 717 };
 718
 719 struct rtl8169_private {
 720         void __iomem *mmio_addr;        /* memory map physical address */
 721         struct pci_dev *pci_dev;
 722         struct net_device *dev;
 723         struct napi_struct napi;
 724         u32 msg_enable;
 725         u16 txd_version;
 726         u16 mac_version;
 727         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 728         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 729         u32 dirty_rx;
 730         u32 dirty_tx;
 731         struct rtl8169_stats rx_stats;
 732         struct rtl8169_stats tx_stats;
 733         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 734         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 735         dma_addr_t TxPhyAddr;
 736         dma_addr_t RxPhyAddr;
 737         void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
 738         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 739         struct timer_list timer;
 740         u16 cp_cmd;
 741
 742         u16 event_slow;
 743
 744         struct mdio_ops {
 745                 void (*write)(struct rtl8169_private *, int, int);
 746                 int (*read)(struct rtl8169_private *, int);
 747         } mdio_ops;
 748
 749         struct pll_power_ops {
 750                 void (*down)(struct rtl8169_private *);
 751                 void (*up)(struct rtl8169_private *);
 752         } pll_power_ops;
 753
 754         struct jumbo_ops {
 755                 void (*enable)(struct rtl8169_private *);
 756                 void (*disable)(struct rtl8169_private *);
 757         } jumbo_ops;
 758
 759         struct csi_ops {
 760                 void (*write)(struct rtl8169_private *, int, int);
 761                 u32 (*read)(struct rtl8169_private *, int);
 762         } csi_ops;
 763
 764         int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
 765         int (*get_settings)(struct net_device *, struct ethtool_cmd *);
 766         void (*phy_reset_enable)(struct rtl8169_private *tp);
 767         void (*hw_start)(struct net_device *);
 768         unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
 769         unsigned int (*link_ok)(void __iomem *);
 770         int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
 771
 772         struct {
 773                 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
 774                 struct mutex mutex;
 775                 struct work_struct work;
 776         } wk;
 777
 778         unsigned features;
 779
 780         struct mii_if_info mii;
 781         struct rtl8169_counters counters;
 782         u32 saved_wolopts;
 783         u32 opts1_mask;
 784
 785         struct rtl_fw {
 786                 const struct firmware *fw;
 787
 788 #define RTL_VER_SIZE            32
 789
 790                 char version[RTL_VER_SIZE];
 791
 792                 struct rtl_fw_phy_action {
 793                         __le32 *code;
 794                         size_t size;
 795                 } phy_action;
 796         } *rtl_fw;
 797 #define RTL_FIRMWARE_UNKNOWN    ERR_PTR(-EAGAIN)
 798
 799         u32 ocp_base;
 800 };
 801
 802 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 803 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 804 module_param(use_dac, int, 0);
 805 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
 806 module_param_named(debug, debug.msg_enable, int, 0);
 807 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
 808 MODULE_LICENSE("GPL");
 809 MODULE_VERSION(RTL8169_VERSION);
 810 MODULE_FIRMWARE(FIRMWARE_8168D_1);
 811 MODULE_FIRMWARE(FIRMWARE_8168D_2);
 812 MODULE_FIRMWARE(FIRMWARE_8168E_1);
 813 MODULE_FIRMWARE(FIRMWARE_8168E_2);
 814 MODULE_FIRMWARE(FIRMWARE_8168E_3);
 815 MODULE_FIRMWARE(FIRMWARE_8105E_1);
 816 MODULE_FIRMWARE(FIRMWARE_8168F_1);
 817 MODULE_FIRMWARE(FIRMWARE_8168F_2);
 818 MODULE_FIRMWARE(FIRMWARE_8402_1);
 819 MODULE_FIRMWARE(FIRMWARE_8411_1);
 820 MODULE_FIRMWARE(FIRMWARE_8106E_1);
 821 MODULE_FIRMWARE(FIRMWARE_8168G_1);
 822
 823 static void rtl_lock_work(struct rtl8169_private *tp)
 824 {
 825         mutex_lock(&tp->wk.mutex);
 826 }
 827
 828 static void rtl_unlock_work(struct rtl8169_private *tp)
 829 {
 830         mutex_unlock(&tp->wk.mutex);
 831 }
 832
 833 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
 834 {
 835         pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL,
 836                                            PCI_EXP_DEVCTL_READRQ, force);
 837 }
 838
 839 struct rtl_cond {
 840         bool (*check)(struct rtl8169_private *);
 841         const char *msg;
 842 };
 843
 844 static void rtl_udelay(unsigned int d)
 845 {
 846         udelay(d);
 847 }
 848
 849 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
 850                           void (*delay)(unsigned int), unsigned int d, int n,
 851                           bool high)
 852 {
 853         int i;
 854
 855         for (i = 0; i < n; i++) {
 856                 delay(d);
 857                 if (c->check(tp) == high)
 858                         return true;
 859         }
 860         netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
 861                   c->msg, !high, n, d);
 862         return false;
 863 }
 864
 865 static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
 866                                       const struct rtl_cond *c,
 867                                       unsigned int d, int n)
 868 {
 869         return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
 870 }
 871
 872 static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
 873                                      const struct rtl_cond *c,
 874                                      unsigned int d, int n)
 875 {
 876         return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
 877 }
 878
 879 static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
 880                                       const struct rtl_cond *c,
 881                                       unsigned int d, int n)
 882 {
 883         return rtl_loop_wait(tp, c, msleep, d, n, true);
 884 }
 885
 886 static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
 887                                      const struct rtl_cond *c,
 888                                      unsigned int d, int n)
 889 {
 890         return rtl_loop_wait(tp, c, msleep, d, n, false);
 891 }
 892
 893 #define DECLARE_RTL_COND(name)                          \
 894 static bool name ## _check(struct rtl8169_private *);   \
 895                                                         \
 896 static const struct rtl_cond name = {                   \
 897         .check  = name ## _check,                       \
 898         .msg    = #name                                 \
 899 };                                                      \
 900                                                         \
 901 static bool name ## _check(struct rtl8169_private *tp)
 902
 903 DECLARE_RTL_COND(rtl_ocpar_cond)
 904 {
 905         void __iomem *ioaddr = tp->mmio_addr;
 906
 907         return RTL_R32(OCPAR) & OCPAR_FLAG;
 908 }
 909
 910 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
 911 {
 912         void __iomem *ioaddr = tp->mmio_addr;
 913
 914         RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
 915
 916         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
 917                 RTL_R32(OCPDR) : ~0;
 918 }
 919
 920 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
 921 {
 922         void __iomem *ioaddr = tp->mmio_addr;
 923
 924         RTL_W32(OCPDR, data);
 925         RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
 926
 927         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
 928 }
 929
 930 DECLARE_RTL_COND(rtl_eriar_cond)
 931 {
 932         void __iomem *ioaddr = tp->mmio_addr;
 933
 934         return RTL_R32(ERIAR) & ERIAR_FLAG;
 935 }
 936
 937 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
 938 {
 939         void __iomem *ioaddr = tp->mmio_addr;
 940
 941         RTL_W8(ERIDR, cmd);
 942         RTL_W32(ERIAR, 0x800010e8);
 943         msleep(2);
 944
 945         if (!rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 5))
 946                 return;
 947
 948         ocp_write(tp, 0x1, 0x30, 0x00000001);
 949 }
 950
 951 #define OOB_CMD_RESET           0x00
 952 #define OOB_CMD_DRIVER_START    0x05
 953 #define OOB_CMD_DRIVER_STOP     0x06
 954
 955 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
 956 {
 957         return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
 958 }
 959
 960 DECLARE_RTL_COND(rtl_ocp_read_cond)
 961 {
 962         u16 reg;
 963
 964         reg = rtl8168_get_ocp_reg(tp);
 965
 966         return ocp_read(tp, 0x0f, reg) & 0x00000800;
 967 }
 968
 969 static void rtl8168_driver_start(struct rtl8169_private *tp)
 970 {
 971         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
 972
 973         rtl_msleep_loop_wait_high(tp, &rtl_ocp_read_cond, 10, 10);
 974 }
 975
 976 static void rtl8168_driver_stop(struct rtl8169_private *tp)
 977 {
 978         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
 979
 980         rtl_msleep_loop_wait_low(tp, &rtl_ocp_read_cond, 10, 10);
 981 }
 982
 983 static int r8168dp_check_dash(struct rtl8169_private *tp)
 984 {
 985         u16 reg = rtl8168_get_ocp_reg(tp);
 986
 987         return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
 988 }
 989
 990 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
 991 {
 992         if (reg & 0xffff0001) {
 993                 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
 994                 return true;
 995         }
 996         return false;
 997 }
 998
 999 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
1000 {
1001         void __iomem *ioaddr = tp->mmio_addr;
1002
1003         return RTL_R32(GPHY_OCP) & OCPAR_FLAG;
1004 }
1005
1006 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
1007 {
1008         void __iomem *ioaddr = tp->mmio_addr;
1009
1010         if (rtl_ocp_reg_failure(tp, reg))
1011                 return;
1012
1013         RTL_W32(GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
1014
1015         rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
1016 }
1017
1018 static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
1019 {
1020         void __iomem *ioaddr = tp->mmio_addr;
1021
1022         if (rtl_ocp_reg_failure(tp, reg))
1023                 return 0;
1024
1025         RTL_W32(GPHY_OCP, reg << 15);
1026
1027         return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
1028                 (RTL_R32(GPHY_OCP) & 0xffff) : ~0;
1029 }
1030
1031 static void rtl_w1w0_phy_ocp(struct rtl8169_private *tp, int reg, int p, int m)
1032 {
1033         int val;
1034
1035         val = r8168_phy_ocp_read(tp, reg);
1036         r8168_phy_ocp_write(tp, reg, (val | p) & ~m);
1037 }
1038
1039 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
1040 {
1041         void __iomem *ioaddr = tp->mmio_addr;
1042
1043         if (rtl_ocp_reg_failure(tp, reg))
1044                 return;
1045
1046         RTL_W32(OCPDR, OCPAR_FLAG | (reg << 15) | data);
1047 }
1048
1049 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
1050 {
1051         void __iomem *ioaddr = tp->mmio_addr;
1052
1053         if (rtl_ocp_reg_failure(tp, reg))
1054                 return 0;
1055
1056         RTL_W32(OCPDR, reg << 15);
1057
1058         return RTL_R32(OCPDR);
1059 }
1060
1061 #define OCP_STD_PHY_BASE        0xa400
1062
1063 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
1064 {
1065         if (reg == 0x1f) {
1066                 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
1067                 return;
1068         }
1069
1070         if (tp->ocp_base != OCP_STD_PHY_BASE)
1071                 reg -= 0x10;
1072
1073         r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
1074 }
1075
1076 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
1077 {
1078         if (tp->ocp_base != OCP_STD_PHY_BASE)
1079                 reg -= 0x10;
1080
1081         return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
1082 }
1083
1084 DECLARE_RTL_COND(rtl_phyar_cond)
1085 {
1086         void __iomem *ioaddr = tp->mmio_addr;
1087
1088         return RTL_R32(PHYAR) & 0x80000000;
1089 }
1090
1091 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
1092 {
1093         void __iomem *ioaddr = tp->mmio_addr;
1094
1095         RTL_W32(PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
1096
1097         rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
1098         /*
1099          * According to hardware specs a 20us delay is required after write
1100          * complete indication, but before sending next command.
1101          */
1102         udelay(20);
1103 }
1104
1105 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
1106 {
1107         void __iomem *ioaddr = tp->mmio_addr;
1108         int value;
1109
1110         RTL_W32(PHYAR, 0x0 | (reg & 0x1f) << 16);
1111
1112         value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
1113                 RTL_R32(PHYAR) & 0xffff : ~0;
1114
1115         /*
1116          * According to hardware specs a 20us delay is required after read
1117          * complete indication, but before sending next command.
1118          */
1119         udelay(20);
1120
1121         return value;
1122 }
1123
1124 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
1125 {
1126         void __iomem *ioaddr = tp->mmio_addr;
1127
1128         RTL_W32(OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
1129         RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
1130         RTL_W32(EPHY_RXER_NUM, 0);
1131
1132         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
1133 }
1134
1135 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
1136 {
1137         r8168dp_1_mdio_access(tp, reg,
1138                               OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
1139 }
1140
1141 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
1142 {
1143         void __iomem *ioaddr = tp->mmio_addr;
1144
1145         r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
1146
1147         mdelay(1);
1148         RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
1149         RTL_W32(EPHY_RXER_NUM, 0);
1150
1151         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
1152                 RTL_R32(OCPDR) & OCPDR_DATA_MASK : ~0;
1153 }
1154
1155 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
1156
1157 static void r8168dp_2_mdio_start(void __iomem *ioaddr)
1158 {
1159         RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
1160 }
1161
1162 static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
1163 {
1164         RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
1165 }
1166
1167 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
1168 {
1169         void __iomem *ioaddr = tp->mmio_addr;
1170
1171         r8168dp_2_mdio_start(ioaddr);
1172
1173         r8169_mdio_write(tp, reg, value);
1174
1175         r8168dp_2_mdio_stop(ioaddr);
1176 }
1177
1178 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
1179 {
1180         void __iomem *ioaddr = tp->mmio_addr;
1181         int value;
1182
1183         r8168dp_2_mdio_start(ioaddr);
1184
1185         value = r8169_mdio_read(tp, reg);
1186
1187         r8168dp_2_mdio_stop(ioaddr);
1188
1189         return value;
1190 }
1191
1192 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
1193 {
1194         tp->mdio_ops.write(tp, location, val);
1195 }
1196
1197 static int rtl_readphy(struct rtl8169_private *tp, int location)
1198 {
1199         return tp->mdio_ops.read(tp, location);
1200 }
1201
1202 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1203 {
1204         rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1205 }
1206
1207 static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1208 {
1209         int val;
1210
1211         val = rtl_readphy(tp, reg_addr);
1212         rtl_writephy(tp, reg_addr, (val | p) & ~m);
1213 }
1214
1215 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
1216                            int val)
1217 {
1218         struct rtl8169_private *tp = netdev_priv(dev);
1219
1220         rtl_writephy(tp, location, val);
1221 }
1222
1223 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1224 {
1225         struct rtl8169_private *tp = netdev_priv(dev);
1226
1227         return rtl_readphy(tp, location);
1228 }
1229
1230 DECLARE_RTL_COND(rtl_ephyar_cond)
1231 {
1232         void __iomem *ioaddr = tp->mmio_addr;
1233
1234         return RTL_R32(EPHYAR) & EPHYAR_FLAG;
1235 }
1236
1237 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1238 {
1239         void __iomem *ioaddr = tp->mmio_addr;
1240
1241         RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1242                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1243
1244         rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1245
1246         udelay(10);
1247 }
1248
1249 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1250 {
1251         void __iomem *ioaddr = tp->mmio_addr;
1252
1253         RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1254
1255         return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1256                 RTL_R32(EPHYAR) & EPHYAR_DATA_MASK : ~0;
1257 }
1258
1259 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1260                           u32 val, int type)
1261 {
1262         void __iomem *ioaddr = tp->mmio_addr;
1263
1264         BUG_ON((addr & 3) || (mask == 0));
1265         RTL_W32(ERIDR, val);
1266         RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1267
1268         rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
1269 }
1270
1271 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
1272 {
1273         void __iomem *ioaddr = tp->mmio_addr;
1274
1275         RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1276
1277         return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1278                 RTL_R32(ERIDR) : ~0;
1279 }
1280
1281 static void rtl_w1w0_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1282                          u32 m, int type)
1283 {
1284         u32 val;
1285
1286         val = rtl_eri_read(tp, addr, type);
1287         rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
1288 }
1289
1290 struct exgmac_reg {
1291         u16 addr;
1292         u16 mask;
1293         u32 val;
1294 };
1295
1296 static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
1297                                    const struct exgmac_reg *r, int len)
1298 {
1299         while (len-- > 0) {
1300                 rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1301                 r++;
1302         }
1303 }
1304
1305 DECLARE_RTL_COND(rtl_efusear_cond)
1306 {
1307         void __iomem *ioaddr = tp->mmio_addr;
1308
1309         return RTL_R32(EFUSEAR) & EFUSEAR_FLAG;
1310 }
1311
1312 static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1313 {
1314         void __iomem *ioaddr = tp->mmio_addr;
1315
1316         RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1317
1318         return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1319                 RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1320 }
1321
1322 static u16 rtl_get_events(struct rtl8169_private *tp)
1323 {
1324         void __iomem *ioaddr = tp->mmio_addr;
1325
1326         return RTL_R16(IntrStatus);
1327 }
1328
1329 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1330 {
1331         void __iomem *ioaddr = tp->mmio_addr;
1332
1333         RTL_W16(IntrStatus, bits);
1334         mmiowb();
1335 }
1336
1337 static void rtl_irq_disable(struct rtl8169_private *tp)
1338 {
1339         void __iomem *ioaddr = tp->mmio_addr;
1340
1341         RTL_W16(IntrMask, 0);
1342         mmiowb();
1343 }
1344
1345 static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1346 {
1347         void __iomem *ioaddr = tp->mmio_addr;
1348
1349         RTL_W16(IntrMask, bits);
1350 }
1351
1352 #define RTL_EVENT_NAPI_RX       (RxOK | RxErr)
1353 #define RTL_EVENT_NAPI_TX       (TxOK | TxErr)
1354 #define RTL_EVENT_NAPI          (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1355
1356 static void rtl_irq_enable_all(struct rtl8169_private *tp)
1357 {
1358         rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1359 }
1360
1361 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1362 {
1363         void __iomem *ioaddr = tp->mmio_addr;
1364
1365         rtl_irq_disable(tp);
1366         rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
1367         RTL_R8(ChipCmd);
1368 }
1369
1370 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1371 {
1372         void __iomem *ioaddr = tp->mmio_addr;
1373
1374         return RTL_R32(TBICSR) & TBIReset;
1375 }
1376
1377 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1378 {
1379         return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1380 }
1381
1382 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1383 {
1384         return RTL_R32(TBICSR) & TBILinkOk;
1385 }
1386
1387 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1388 {
1389         return RTL_R8(PHYstatus) & LinkStatus;
1390 }
1391
1392 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1393 {
1394         void __iomem *ioaddr = tp->mmio_addr;
1395
1396         RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1397 }
1398
1399 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1400 {
1401         unsigned int val;
1402
1403         val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1404         rtl_writephy(tp, MII_BMCR, val & 0xffff);
1405 }
1406
1407 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1408 {
1409         void __iomem *ioaddr = tp->mmio_addr;
1410         struct net_device *dev = tp->dev;
1411
1412         if (!netif_running(dev))
1413                 return;
1414
1415         if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1416             tp->mac_version == RTL_GIGA_MAC_VER_38) {
1417                 if (RTL_R8(PHYstatus) & _1000bpsF) {
1418                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1419                                       ERIAR_EXGMAC);
1420                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1421                                       ERIAR_EXGMAC);
1422                 } else if (RTL_R8(PHYstatus) & _100bps) {
1423                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1424                                       ERIAR_EXGMAC);
1425                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1426                                       ERIAR_EXGMAC);
1427                 } else {
1428                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1429                                       ERIAR_EXGMAC);
1430                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1431                                       ERIAR_EXGMAC);
1432                 }
1433                 /* Reset packet filter */
1434                 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1435                              ERIAR_EXGMAC);
1436                 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1437                              ERIAR_EXGMAC);
1438         } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1439                    tp->mac_version == RTL_GIGA_MAC_VER_36) {
1440                 if (RTL_R8(PHYstatus) & _1000bpsF) {
1441                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1442                                       ERIAR_EXGMAC);
1443                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1444                                       ERIAR_EXGMAC);
1445                 } else {
1446                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1447                                       ERIAR_EXGMAC);
1448                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1449                                       ERIAR_EXGMAC);
1450                 }
1451         } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1452                 if (RTL_R8(PHYstatus) & _10bps) {
1453                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,
1454                                       ERIAR_EXGMAC);
1455                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,
1456                                       ERIAR_EXGMAC);
1457                 } else {
1458                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,
1459                                       ERIAR_EXGMAC);
1460                 }
1461         }
1462 }
1463
1464 static void __rtl8169_check_link_status(struct net_device *dev,
1465                                         struct rtl8169_private *tp,
1466                                         void __iomem *ioaddr, bool pm)
1467 {
1468         if (tp->link_ok(ioaddr)) {
1469                 rtl_link_chg_patch(tp);
1470                 /* This is to cancel a scheduled suspend if there's one. */
1471                 if (pm)
1472                         pm_request_resume(&tp->pci_dev->dev);
1473                 netif_carrier_on(dev);
1474                 if (net_ratelimit())
1475                         netif_info(tp, ifup, dev, "link up\n");
1476         } else {
1477                 netif_carrier_off(dev);
1478                 netif_info(tp, ifdown, dev, "link down\n");
1479                 if (pm)
1480                         pm_schedule_suspend(&tp->pci_dev->dev, 5000);
1481         }
1482 }
1483
1484 static void rtl8169_check_link_status(struct net_device *dev,
1485                                       struct rtl8169_private *tp,
1486                                       void __iomem *ioaddr)
1487 {
1488         __rtl8169_check_link_status(dev, tp, ioaddr, false);
1489 }
1490
1491 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1492
1493 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1494 {
1495         void __iomem *ioaddr = tp->mmio_addr;
1496         u8 options;
1497         u32 wolopts = 0;
1498
1499         options = RTL_R8(Config1);
1500         if (!(options & PMEnable))
1501                 return 0;
1502
1503         options = RTL_R8(Config3);
1504         if (options & LinkUp)
1505                 wolopts |= WAKE_PHY;
1506         if (options & MagicPacket)
1507                 wolopts |= WAKE_MAGIC;
1508
1509         options = RTL_R8(Config5);
1510         if (options & UWF)
1511                 wolopts |= WAKE_UCAST;
1512         if (options & BWF)
1513                 wolopts |= WAKE_BCAST;
1514         if (options & MWF)
1515                 wolopts |= WAKE_MCAST;
1516
1517         return wolopts;
1518 }
1519
1520 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1521 {
1522         struct rtl8169_private *tp = netdev_priv(dev);
1523
1524         rtl_lock_work(tp);
1525
1526         wol->supported = WAKE_ANY;
1527         wol->wolopts = __rtl8169_get_wol(tp);
1528
1529         rtl_unlock_work(tp);
1530 }
1531
1532 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1533 {
1534         void __iomem *ioaddr = tp->mmio_addr;
1535         unsigned int i;
1536         static const struct {
1537                 u32 opt;
1538                 u16 reg;
1539                 u8  mask;
1540         } cfg[] = {
1541                 { WAKE_PHY,   Config3, LinkUp },
1542                 { WAKE_MAGIC, Config3, MagicPacket },
1543                 { WAKE_UCAST, Config5, UWF },
1544                 { WAKE_BCAST, Config5, BWF },
1545                 { WAKE_MCAST, Config5, MWF },
1546                 { WAKE_ANY,   Config5, LanWake }
1547         };
1548         u8 options;
1549
1550         RTL_W8(Cfg9346, Cfg9346_Unlock);
1551
1552         for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1553                 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
1554                 if (wolopts & cfg[i].opt)
1555                         options |= cfg[i].mask;
1556                 RTL_W8(cfg[i].reg, options);
1557         }
1558
1559         switch (tp->mac_version) {
1560         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1561                 options = RTL_R8(Config1) & ~PMEnable;
1562                 if (wolopts)
1563                         options |= PMEnable;
1564                 RTL_W8(Config1, options);
1565                 break;
1566         default:
1567                 options = RTL_R8(Config2) & ~PME_SIGNAL;
1568                 if (wolopts)
1569                         options |= PME_SIGNAL;
1570                 RTL_W8(Config2, options);
1571                 break;
1572         }
1573
1574         RTL_W8(Cfg9346, Cfg9346_Lock);
1575 }
1576
1577 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1578 {
1579         struct rtl8169_private *tp = netdev_priv(dev);
1580
1581         rtl_lock_work(tp);
1582
1583         if (wol->wolopts)
1584                 tp->features |= RTL_FEATURE_WOL;
1585         else
1586                 tp->features &= ~RTL_FEATURE_WOL;
1587         __rtl8169_set_wol(tp, wol->wolopts);
1588
1589         rtl_unlock_work(tp);
1590
1591         device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1592
1593         return 0;
1594 }
1595
1596 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1597 {
1598         return rtl_chip_infos[tp->mac_version].fw_name;
1599 }
1600
1601 static void rtl8169_get_drvinfo(struct net_device *dev,
1602                                 struct ethtool_drvinfo *info)
1603 {
1604         struct rtl8169_private *tp = netdev_priv(dev);
1605         struct rtl_fw *rtl_fw = tp->rtl_fw;
1606
1607         strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1608         strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
1609         strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1610         BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1611         if (!IS_ERR_OR_NULL(rtl_fw))
1612                 strlcpy(info->fw_version, rtl_fw->version,
1613                         sizeof(info->fw_version));
1614 }
1615
1616 static int rtl8169_get_regs_len(struct net_device *dev)
1617 {
1618         return R8169_REGS_SIZE;
1619 }
1620
1621 static int rtl8169_set_speed_tbi(struct net_device *dev,
1622                                  u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1623 {
1624         struct rtl8169_private *tp = netdev_priv(dev);
1625         void __iomem *ioaddr = tp->mmio_addr;
1626         int ret = 0;
1627         u32 reg;
1628
1629         reg = RTL_R32(TBICSR);
1630         if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1631             (duplex == DUPLEX_FULL)) {
1632                 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1633         } else if (autoneg == AUTONEG_ENABLE)
1634                 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1635         else {
1636                 netif_warn(tp, link, dev,
1637                            "incorrect speed setting refused in TBI mode\n");
1638                 ret = -EOPNOTSUPP;
1639         }
1640
1641         return ret;
1642 }
1643
1644 static int rtl8169_set_speed_xmii(struct net_device *dev,
1645                                   u8 autoneg, u16 speed, u8 duplex, u32 adv)
1646 {
1647         struct rtl8169_private *tp = netdev_priv(dev);
1648         int giga_ctrl, bmcr;
1649         int rc = -EINVAL;
1650
1651         rtl_writephy(tp, 0x1f, 0x0000);
1652
1653         if (autoneg == AUTONEG_ENABLE) {
1654                 int auto_nego;
1655
1656                 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1657                 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1658                                 ADVERTISE_100HALF | ADVERTISE_100FULL);
1659
1660                 if (adv & ADVERTISED_10baseT_Half)
1661                         auto_nego |= ADVERTISE_10HALF;
1662                 if (adv & ADVERTISED_10baseT_Full)
1663                         auto_nego |= ADVERTISE_10FULL;
1664                 if (adv & ADVERTISED_100baseT_Half)
1665                         auto_nego |= ADVERTISE_100HALF;
1666                 if (adv & ADVERTISED_100baseT_Full)
1667                         auto_nego |= ADVERTISE_100FULL;
1668
1669                 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1670
1671                 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1672                 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1673
1674                 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1675                 if (tp->mii.supports_gmii) {
1676                         if (adv & ADVERTISED_1000baseT_Half)
1677                                 giga_ctrl |= ADVERTISE_1000HALF;
1678                         if (adv & ADVERTISED_1000baseT_Full)
1679                                 giga_ctrl |= ADVERTISE_1000FULL;
1680                 } else if (adv & (ADVERTISED_1000baseT_Half |
1681                                   ADVERTISED_1000baseT_Full)) {
1682                         netif_info(tp, link, dev,
1683                                    "PHY does not support 1000Mbps\n");
1684                         goto out;
1685                 }
1686
1687                 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1688
1689                 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1690                 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1691         } else {
1692                 giga_ctrl = 0;
1693
1694                 if (speed == SPEED_10)
1695                         bmcr = 0;
1696                 else if (speed == SPEED_100)
1697                         bmcr = BMCR_SPEED100;
1698                 else
1699                         goto out;
1700
1701                 if (duplex == DUPLEX_FULL)
1702                         bmcr |= BMCR_FULLDPLX;
1703         }
1704
1705         rtl_writephy(tp, MII_BMCR, bmcr);
1706
1707         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1708             tp->mac_version == RTL_GIGA_MAC_VER_03) {
1709                 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1710                         rtl_writephy(tp, 0x17, 0x2138);
1711                         rtl_writephy(tp, 0x0e, 0x0260);
1712                 } else {
1713                         rtl_writephy(tp, 0x17, 0x2108);
1714                         rtl_writephy(tp, 0x0e, 0x0000);
1715                 }
1716         }
1717
1718         rc = 0;
1719 out:
1720         return rc;
1721 }
1722
1723 static int rtl8169_set_speed(struct net_device *dev,
1724                              u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1725 {
1726         struct rtl8169_private *tp = netdev_priv(dev);
1727         int ret;
1728
1729         ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
1730         if (ret < 0)
1731                 goto out;
1732
1733         if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1734             (advertising & ADVERTISED_1000baseT_Full)) {
1735                 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1736         }
1737 out:
1738         return ret;
1739 }
1740
1741 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1742 {
1743         struct rtl8169_private *tp = netdev_priv(dev);
1744         int ret;
1745
1746         del_timer_sync(&tp->timer);
1747
1748         rtl_lock_work(tp);
1749         ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
1750                                 cmd->duplex, cmd->advertising);
1751         rtl_unlock_work(tp);
1752
1753         return ret;
1754 }
1755
1756 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1757         netdev_features_t features)
1758 {
1759         struct rtl8169_private *tp = netdev_priv(dev);
1760
1761         if (dev->mtu > TD_MSS_MAX)
1762                 features &= ~NETIF_F_ALL_TSO;
1763
1764         if (dev->mtu > JUMBO_1K &&
1765             !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
1766                 features &= ~NETIF_F_IP_CSUM;
1767
1768         return features;
1769 }
1770
1771 static void __rtl8169_set_features(struct net_device *dev,
1772                                    netdev_features_t features)
1773 {
1774         struct rtl8169_private *tp = netdev_priv(dev);
1775         netdev_features_t changed = features ^ dev->features;
1776         void __iomem *ioaddr = tp->mmio_addr;
1777
1778         if (!(changed & (NETIF_F_RXALL | NETIF_F_RXCSUM | NETIF_F_HW_VLAN_RX)))
1779                 return;
1780
1781         if (changed & (NETIF_F_RXCSUM | NETIF_F_HW_VLAN_RX)) {
1782                 if (features & NETIF_F_RXCSUM)
1783                         tp->cp_cmd |= RxChkSum;
1784                 else
1785                         tp->cp_cmd &= ~RxChkSum;
1786
1787                 if (dev->features & NETIF_F_HW_VLAN_RX)
1788                         tp->cp_cmd |= RxVlan;
1789                 else
1790                         tp->cp_cmd &= ~RxVlan;
1791
1792                 RTL_W16(CPlusCmd, tp->cp_cmd);
1793                 RTL_R16(CPlusCmd);
1794         }
1795         if (changed & NETIF_F_RXALL) {
1796                 int tmp = (RTL_R32(RxConfig) & ~(AcceptErr | AcceptRunt));
1797                 if (features & NETIF_F_RXALL)
1798                         tmp |= (AcceptErr | AcceptRunt);
1799                 RTL_W32(RxConfig, tmp);
1800         }
1801 }
1802
1803 static int rtl8169_set_features(struct net_device *dev,
1804                                 netdev_features_t features)
1805 {
1806         struct rtl8169_private *tp = netdev_priv(dev);
1807
1808         rtl_lock_work(tp);
1809         __rtl8169_set_features(dev, features);
1810         rtl_unlock_work(tp);
1811
1812         return 0;
1813 }
1814
1815
1816 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1817 {
1818         return (vlan_tx_tag_present(skb)) ?
1819                 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1820 }
1821
1822 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1823 {
1824         u32 opts2 = le32_to_cpu(desc->opts2);
1825
1826         if (opts2 & RxVlanTag)
1827                 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
1828 }
1829
1830 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1831 {
1832         struct rtl8169_private *tp = netdev_priv(dev);
1833         void __iomem *ioaddr = tp->mmio_addr;
1834         u32 status;
1835
1836         cmd->supported =
1837                 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1838         cmd->port = PORT_FIBRE;
1839         cmd->transceiver = XCVR_INTERNAL;
1840
1841         status = RTL_R32(TBICSR);
1842         cmd->advertising = (status & TBINwEnable) ?  ADVERTISED_Autoneg : 0;
1843         cmd->autoneg = !!(status & TBINwEnable);
1844
1845         ethtool_cmd_speed_set(cmd, SPEED_1000);
1846         cmd->duplex = DUPLEX_FULL; /* Always set */
1847
1848         return 0;
1849 }
1850
1851 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1852 {
1853         struct rtl8169_private *tp = netdev_priv(dev);
1854
1855         return mii_ethtool_gset(&tp->mii, cmd);
1856 }
1857
1858 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1859 {
1860         struct rtl8169_private *tp = netdev_priv(dev);
1861         int rc;
1862
1863         rtl_lock_work(tp);
1864         rc = tp->get_settings(dev, cmd);
1865         rtl_unlock_work(tp);
1866
1867         return rc;
1868 }
1869
1870 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1871                              void *p)
1872 {
1873         struct rtl8169_private *tp = netdev_priv(dev);
1874
1875         if (regs->len > R8169_REGS_SIZE)
1876                 regs->len = R8169_REGS_SIZE;
1877
1878         rtl_lock_work(tp);
1879         memcpy_fromio(p, tp->mmio_addr, regs->len);
1880         rtl_unlock_work(tp);
1881 }
1882
1883 static u32 rtl8169_get_msglevel(struct net_device *dev)
1884 {
1885         struct rtl8169_private *tp = netdev_priv(dev);
1886
1887         return tp->msg_enable;
1888 }
1889
1890 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1891 {
1892         struct rtl8169_private *tp = netdev_priv(dev);
1893
1894         tp->msg_enable = value;
1895 }
1896
1897 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1898         "tx_packets",
1899         "rx_packets",
1900         "tx_errors",
1901         "rx_errors",
1902         "rx_missed",
1903         "align_errors",
1904         "tx_single_collisions",
1905         "tx_multi_collisions",
1906         "unicast",
1907         "broadcast",
1908         "multicast",
1909         "tx_aborted",
1910         "tx_underrun",
1911 };
1912
1913 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1914 {
1915         switch (sset) {
1916         case ETH_SS_STATS:
1917                 return ARRAY_SIZE(rtl8169_gstrings);
1918         default:
1919                 return -EOPNOTSUPP;
1920         }
1921 }
1922
1923 DECLARE_RTL_COND(rtl_counters_cond)
1924 {
1925         void __iomem *ioaddr = tp->mmio_addr;
1926
1927         return RTL_R32(CounterAddrLow) & CounterDump;
1928 }
1929
1930 static void rtl8169_update_counters(struct net_device *dev)
1931 {
1932         struct rtl8169_private *tp = netdev_priv(dev);
1933         void __iomem *ioaddr = tp->mmio_addr;
1934         struct device *d = &tp->pci_dev->dev;
1935         struct rtl8169_counters *counters;
1936         dma_addr_t paddr;
1937         u32 cmd;
1938
1939         /*
1940          * Some chips are unable to dump tally counters when the receiver
1941          * is disabled.
1942          */
1943         if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1944                 return;
1945
1946         counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
1947         if (!counters)
1948                 return;
1949
1950         RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1951         cmd = (u64)paddr & DMA_BIT_MASK(32);
1952         RTL_W32(CounterAddrLow, cmd);
1953         RTL_W32(CounterAddrLow, cmd | CounterDump);
1954
1955         if (rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000))
1956                 memcpy(&tp->counters, counters, sizeof(*counters));
1957
1958         RTL_W32(CounterAddrLow, 0);
1959         RTL_W32(CounterAddrHigh, 0);
1960
1961         dma_free_coherent(d, sizeof(*counters), counters, paddr);
1962 }
1963
1964 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1965                                       struct ethtool_stats *stats, u64 *data)
1966 {
1967         struct rtl8169_private *tp = netdev_priv(dev);
1968
1969         ASSERT_RTNL();
1970
1971         rtl8169_update_counters(dev);
1972
1973         data[0] = le64_to_cpu(tp->counters.tx_packets);
1974         data[1] = le64_to_cpu(tp->counters.rx_packets);
1975         data[2] = le64_to_cpu(tp->counters.tx_errors);
1976         data[3] = le32_to_cpu(tp->counters.rx_errors);
1977         data[4] = le16_to_cpu(tp->counters.rx_missed);
1978         data[5] = le16_to_cpu(tp->counters.align_errors);
1979         data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1980         data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1981         data[8] = le64_to_cpu(tp->counters.rx_unicast);
1982         data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1983         data[10] = le32_to_cpu(tp->counters.rx_multicast);
1984         data[11] = le16_to_cpu(tp->counters.tx_aborted);
1985         data[12] = le16_to_cpu(tp->counters.tx_underun);
1986 }
1987
1988 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1989 {
1990         switch(stringset) {
1991         case ETH_SS_STATS:
1992                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1993                 break;
1994         }
1995 }
1996
1997 static const struct ethtool_ops rtl8169_ethtool_ops = {
1998         .get_drvinfo            = rtl8169_get_drvinfo,
1999         .get_regs_len           = rtl8169_get_regs_len,
2000         .get_link               = ethtool_op_get_link,
2001         .get_settings           = rtl8169_get_settings,
2002         .set_settings           = rtl8169_set_settings,
2003         .get_msglevel           = rtl8169_get_msglevel,
2004         .set_msglevel           = rtl8169_set_msglevel,
2005         .get_regs               = rtl8169_get_regs,
2006         .get_wol                = rtl8169_get_wol,
2007         .set_wol                = rtl8169_set_wol,
2008         .get_strings            = rtl8169_get_strings,
2009         .get_sset_count         = rtl8169_get_sset_count,
2010         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
2011         .get_ts_info            = ethtool_op_get_ts_info,
2012 };
2013
2014 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
2015                                     struct net_device *dev, u8 default_version)
2016 {
2017         void __iomem *ioaddr = tp->mmio_addr;
2018         /*
2019          * The driver currently handles the 8168Bf and the 8168Be identically
2020          * but they can be identified more specifically through the test below
2021          * if needed:
2022          *
2023          * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2024          *
2025          * Same thing for the 8101Eb and the 8101Ec:
2026          *
2027          * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2028          */
2029         static const struct rtl_mac_info {
2030                 u32 mask;
2031                 u32 val;
2032                 int mac_version;
2033         } mac_info[] = {
2034                 /* 8168G family. */
2035                 { 0x7cf00000, 0x4c100000,       RTL_GIGA_MAC_VER_41 },
2036                 { 0x7cf00000, 0x4c000000,       RTL_GIGA_MAC_VER_40 },
2037
2038                 /* 8168F family. */
2039                 { 0x7c800000, 0x48800000,       RTL_GIGA_MAC_VER_38 },
2040                 { 0x7cf00000, 0x48100000,       RTL_GIGA_MAC_VER_36 },
2041                 { 0x7cf00000, 0x48000000,       RTL_GIGA_MAC_VER_35 },
2042
2043                 /* 8168E family. */
2044                 { 0x7c800000, 0x2c800000,       RTL_GIGA_MAC_VER_34 },
2045                 { 0x7cf00000, 0x2c200000,       RTL_GIGA_MAC_VER_33 },
2046                 { 0x7cf00000, 0x2c100000,       RTL_GIGA_MAC_VER_32 },
2047                 { 0x7c800000, 0x2c000000,       RTL_GIGA_MAC_VER_33 },
2048
2049                 /* 8168D family. */
2050                 { 0x7cf00000, 0x28300000,       RTL_GIGA_MAC_VER_26 },
2051                 { 0x7cf00000, 0x28100000,       RTL_GIGA_MAC_VER_25 },
2052                 { 0x7c800000, 0x28000000,       RTL_GIGA_MAC_VER_26 },
2053
2054                 /* 8168DP family. */
2055                 { 0x7cf00000, 0x28800000,       RTL_GIGA_MAC_VER_27 },
2056                 { 0x7cf00000, 0x28a00000,       RTL_GIGA_MAC_VER_28 },
2057                 { 0x7cf00000, 0x28b00000,       RTL_GIGA_MAC_VER_31 },
2058
2059                 /* 8168C family. */
2060                 { 0x7cf00000, 0x3cb00000,       RTL_GIGA_MAC_VER_24 },
2061                 { 0x7cf00000, 0x3c900000,       RTL_GIGA_MAC_VER_23 },
2062                 { 0x7cf00000, 0x3c800000,       RTL_GIGA_MAC_VER_18 },
2063                 { 0x7c800000, 0x3c800000,       RTL_GIGA_MAC_VER_24 },
2064                 { 0x7cf00000, 0x3c000000,       RTL_GIGA_MAC_VER_19 },
2065                 { 0x7cf00000, 0x3c200000,       RTL_GIGA_MAC_VER_20 },
2066                 { 0x7cf00000, 0x3c300000,       RTL_GIGA_MAC_VER_21 },
2067                 { 0x7cf00000, 0x3c400000,       RTL_GIGA_MAC_VER_22 },
2068                 { 0x7c800000, 0x3c000000,       RTL_GIGA_MAC_VER_22 },
2069
2070                 /* 8168B family. */
2071                 { 0x7cf00000, 0x38000000,       RTL_GIGA_MAC_VER_12 },
2072                 { 0x7cf00000, 0x38500000,       RTL_GIGA_MAC_VER_17 },
2073                 { 0x7c800000, 0x38000000,       RTL_GIGA_MAC_VER_17 },
2074                 { 0x7c800000, 0x30000000,       RTL_GIGA_MAC_VER_11 },
2075
2076                 /* 8101 family. */
2077                 { 0x7cf00000, 0x44900000,       RTL_GIGA_MAC_VER_39 },
2078                 { 0x7c800000, 0x44800000,       RTL_GIGA_MAC_VER_39 },
2079                 { 0x7c800000, 0x44000000,       RTL_GIGA_MAC_VER_37 },
2080                 { 0x7cf00000, 0x40b00000,       RTL_GIGA_MAC_VER_30 },
2081                 { 0x7cf00000, 0x40a00000,       RTL_GIGA_MAC_VER_30 },
2082                 { 0x7cf00000, 0x40900000,       RTL_GIGA_MAC_VER_29 },
2083                 { 0x7c800000, 0x40800000,       RTL_GIGA_MAC_VER_30 },
2084                 { 0x7cf00000, 0x34a00000,       RTL_GIGA_MAC_VER_09 },
2085                 { 0x7cf00000, 0x24a00000,       RTL_GIGA_MAC_VER_09 },
2086                 { 0x7cf00000, 0x34900000,       RTL_GIGA_MAC_VER_08 },
2087                 { 0x7cf00000, 0x24900000,       RTL_GIGA_MAC_VER_08 },
2088                 { 0x7cf00000, 0x34800000,       RTL_GIGA_MAC_VER_07 },
2089                 { 0x7cf00000, 0x24800000,       RTL_GIGA_MAC_VER_07 },
2090                 { 0x7cf00000, 0x34000000,       RTL_GIGA_MAC_VER_13 },
2091                 { 0x7cf00000, 0x34300000,       RTL_GIGA_MAC_VER_10 },
2092                 { 0x7cf00000, 0x34200000,       RTL_GIGA_MAC_VER_16 },
2093                 { 0x7c800000, 0x34800000,       RTL_GIGA_MAC_VER_09 },
2094                 { 0x7c800000, 0x24800000,       RTL_GIGA_MAC_VER_09 },
2095                 { 0x7c800000, 0x34000000,       RTL_GIGA_MAC_VER_16 },
2096                 /* FIXME: where did these entries come from ? -- FR */
2097                 { 0xfc800000, 0x38800000,       RTL_GIGA_MAC_VER_15 },
2098                 { 0xfc800000, 0x30800000,       RTL_GIGA_MAC_VER_14 },
2099
2100                 /* 8110 family. */
2101                 { 0xfc800000, 0x98000000,       RTL_GIGA_MAC_VER_06 },
2102                 { 0xfc800000, 0x18000000,       RTL_GIGA_MAC_VER_05 },
2103                 { 0xfc800000, 0x10000000,       RTL_GIGA_MAC_VER_04 },
2104                 { 0xfc800000, 0x04000000,       RTL_GIGA_MAC_VER_03 },
2105                 { 0xfc800000, 0x00800000,       RTL_GIGA_MAC_VER_02 },
2106                 { 0xfc800000, 0x00000000,       RTL_GIGA_MAC_VER_01 },
2107
2108                 /* Catch-all */
2109                 { 0x00000000, 0x00000000,       RTL_GIGA_MAC_NONE   }
2110         };
2111         const struct rtl_mac_info *p = mac_info;
2112         u32 reg;
2113
2114         reg = RTL_R32(TxConfig);
2115         while ((reg & p->mask) != p->val)
2116                 p++;
2117         tp->mac_version = p->mac_version;
2118
2119         if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2120                 netif_notice(tp, probe, dev,
2121                              "unknown MAC, using family default\n");
2122                 tp->mac_version = default_version;
2123         }
2124 }
2125
2126 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
2127 {
2128         dprintk("mac_version = 0x%02x\n", tp->mac_version);
2129 }
2130
2131 struct phy_reg {
2132         u16 reg;
2133         u16 val;
2134 };
2135
2136 static void rtl_writephy_batch(struct rtl8169_private *tp,
2137                                const struct phy_reg *regs, int len)
2138 {
2139         while (len-- > 0) {
2140                 rtl_writephy(tp, regs->reg, regs->val);
2141                 regs++;
2142         }
2143 }
2144
2145 #define PHY_READ                0x00000000
2146 #define PHY_DATA_OR             0x10000000
2147 #define PHY_DATA_AND            0x20000000
2148 #define PHY_BJMPN               0x30000000
2149 #define PHY_READ_EFUSE          0x40000000
2150 #define PHY_READ_MAC_BYTE       0x50000000
2151 #define PHY_WRITE_MAC_BYTE      0x60000000
2152 #define PHY_CLEAR_READCOUNT     0x70000000
2153 #define PHY_WRITE               0x80000000
2154 #define PHY_READCOUNT_EQ_SKIP   0x90000000
2155 #define PHY_COMP_EQ_SKIPN       0xa0000000
2156 #define PHY_COMP_NEQ_SKIPN      0xb0000000
2157 #define PHY_WRITE_PREVIOUS      0xc0000000
2158 #define PHY_SKIPN               0xd0000000
2159 #define PHY_DELAY_MS            0xe0000000
2160 #define PHY_WRITE_ERI_WORD      0xf0000000
2161
2162 struct fw_info {
2163         u32     magic;
2164         char    version[RTL_VER_SIZE];
2165         __le32  fw_start;
2166         __le32  fw_len;
2167         u8      chksum;
2168 } __packed;
2169
2170 #define FW_OPCODE_SIZE  sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2171
2172 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2173 {
2174         const struct firmware *fw = rtl_fw->fw;
2175         struct fw_info *fw_info = (struct fw_info *)fw->data;
2176         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2177         char *version = rtl_fw->version;
2178         bool rc = false;
2179
2180         if (fw->size < FW_OPCODE_SIZE)
2181                 goto out;
2182
2183         if (!fw_info->magic) {
2184                 size_t i, size, start;
2185                 u8 checksum = 0;
2186
2187                 if (fw->size < sizeof(*fw_info))
2188                         goto out;
2189
2190                 for (i = 0; i < fw->size; i++)
2191                         checksum += fw->data[i];
2192                 if (checksum != 0)
2193                         goto out;
2194
2195                 start = le32_to_cpu(fw_info->fw_start);
2196                 if (start > fw->size)
2197                         goto out;
2198
2199                 size = le32_to_cpu(fw_info->fw_len);
2200                 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2201                         goto out;
2202
2203                 memcpy(version, fw_info->version, RTL_VER_SIZE);
2204
2205                 pa->code = (__le32 *)(fw->data + start);
2206                 pa->size = size;
2207         } else {
2208                 if (fw->size % FW_OPCODE_SIZE)
2209                         goto out;
2210
2211                 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2212
2213                 pa->code = (__le32 *)fw->data;
2214                 pa->size = fw->size / FW_OPCODE_SIZE;
2215         }
2216         version[RTL_VER_SIZE - 1] = 0;
2217
2218         rc = true;
2219 out:
2220         return rc;
2221 }
2222
2223 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2224                            struct rtl_fw_phy_action *pa)
2225 {
2226         bool rc = false;
2227         size_t index;
2228
2229         for (index = 0; index < pa->size; index++) {
2230                 u32 action = le32_to_cpu(pa->code[index]);
2231                 u32 regno = (action & 0x0fff0000) >> 16;
2232
2233                 switch(action & 0xf0000000) {
2234                 case PHY_READ:
2235                 case PHY_DATA_OR:
2236                 case PHY_DATA_AND:
2237                 case PHY_READ_EFUSE:
2238                 case PHY_CLEAR_READCOUNT:
2239                 case PHY_WRITE:
2240                 case PHY_WRITE_PREVIOUS:
2241                 case PHY_DELAY_MS:
2242                         break;
2243
2244                 case PHY_BJMPN:
2245                         if (regno > index) {
2246                                 netif_err(tp, ifup, tp->dev,
2247                                           "Out of range of firmware\n");
2248                                 goto out;
2249                         }
2250                         break;
2251                 case PHY_READCOUNT_EQ_SKIP:
2252                         if (index + 2 >= pa->size) {
2253                                 netif_err(tp, ifup, tp->dev,
2254                                           "Out of range of firmware\n");
2255                                 goto out;
2256                         }
2257                         break;
2258                 case PHY_COMP_EQ_SKIPN:
2259                 case PHY_COMP_NEQ_SKIPN:
2260                 case PHY_SKIPN:
2261                         if (index + 1 + regno >= pa->size) {
2262                                 netif_err(tp, ifup, tp->dev,
2263                                           "Out of range of firmware\n");
2264                                 goto out;
2265                         }
2266                         break;
2267
2268                 case PHY_READ_MAC_BYTE:
2269                 case PHY_WRITE_MAC_BYTE:
2270                 case PHY_WRITE_ERI_WORD:
2271                 default:
2272                         netif_err(tp, ifup, tp->dev,
2273                                   "Invalid action 0x%08x\n", action);
2274                         goto out;
2275                 }
2276         }
2277         rc = true;
2278 out:
2279         return rc;
2280 }
2281
2282 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2283 {
2284         struct net_device *dev = tp->dev;
2285         int rc = -EINVAL;
2286
2287         if (!rtl_fw_format_ok(tp, rtl_fw)) {
2288                 netif_err(tp, ifup, dev, "invalid firwmare\n");
2289                 goto out;
2290         }
2291
2292         if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2293                 rc = 0;
2294 out:
2295         return rc;
2296 }
2297
2298 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2299 {
2300         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2301         u32 predata, count;
2302         size_t index;
2303
2304         predata = count = 0;
2305
2306         for (index = 0; index < pa->size; ) {
2307                 u32 action = le32_to_cpu(pa->code[index]);
2308                 u32 data = action & 0x0000ffff;
2309                 u32 regno = (action & 0x0fff0000) >> 16;
2310
2311                 if (!action)
2312                         break;
2313
2314                 switch(action & 0xf0000000) {
2315                 case PHY_READ:
2316                         predata = rtl_readphy(tp, regno);
2317                         count++;
2318                         index++;
2319                         break;
2320                 case PHY_DATA_OR:
2321                         predata |= data;
2322                         index++;
2323                         break;
2324                 case PHY_DATA_AND:
2325                         predata &= data;
2326                         index++;
2327                         break;
2328                 case PHY_BJMPN:
2329                         index -= regno;
2330                         break;
2331                 case PHY_READ_EFUSE:
2332                         predata = rtl8168d_efuse_read(tp, regno);
2333                         index++;
2334                         break;
2335                 case PHY_CLEAR_READCOUNT:
2336                         count = 0;
2337                         index++;
2338                         break;
2339                 case PHY_WRITE:
2340                         rtl_writephy(tp, regno, data);
2341                         index++;
2342                         break;
2343                 case PHY_READCOUNT_EQ_SKIP:
2344                         index += (count == data) ? 2 : 1;
2345                         break;
2346                 case PHY_COMP_EQ_SKIPN:
2347                         if (predata == data)
2348                                 index += regno;
2349                         index++;
2350                         break;
2351                 case PHY_COMP_NEQ_SKIPN:
2352                         if (predata != data)
2353                                 index += regno;
2354                         index++;
2355                         break;
2356                 case PHY_WRITE_PREVIOUS:
2357                         rtl_writephy(tp, regno, predata);
2358                         index++;
2359                         break;
2360                 case PHY_SKIPN:
2361                         index += regno + 1;
2362                         break;
2363                 case PHY_DELAY_MS:
2364                         mdelay(data);
2365                         index++;
2366                         break;
2367
2368                 case PHY_READ_MAC_BYTE:
2369                 case PHY_WRITE_MAC_BYTE:
2370                 case PHY_WRITE_ERI_WORD:
2371                 default:
2372                         BUG();
2373                 }
2374         }
2375 }
2376
2377 static void rtl_release_firmware(struct rtl8169_private *tp)
2378 {
2379         if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2380                 release_firmware(tp->rtl_fw->fw);
2381                 kfree(tp->rtl_fw);
2382         }
2383         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
2384 }
2385
2386 static void rtl_apply_firmware(struct rtl8169_private *tp)
2387 {
2388         struct rtl_fw *rtl_fw = tp->rtl_fw;
2389
2390         /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2391         if (!IS_ERR_OR_NULL(rtl_fw))
2392                 rtl_phy_write_fw(tp, rtl_fw);
2393 }
2394
2395 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2396 {
2397         if (rtl_readphy(tp, reg) != val)
2398                 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2399         else
2400                 rtl_apply_firmware(tp);
2401 }
2402
2403 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2404 {
2405         static const struct phy_reg phy_reg_init[] = {
2406                 { 0x1f, 0x0001 },
2407                 { 0x06, 0x006e },
2408                 { 0x08, 0x0708 },
2409                 { 0x15, 0x4000 },
2410                 { 0x18, 0x65c7 },
2411
2412                 { 0x1f, 0x0001 },
2413                 { 0x03, 0x00a1 },
2414                 { 0x02, 0x0008 },
2415                 { 0x01, 0x0120 },
2416                 { 0x00, 0x1000 },
2417                 { 0x04, 0x0800 },
2418                 { 0x04, 0x0000 },
2419
2420                 { 0x03, 0xff41 },
2421                 { 0x02, 0xdf60 },
2422                 { 0x01, 0x0140 },
2423                 { 0x00, 0x0077 },
2424                 { 0x04, 0x7800 },
2425                 { 0x04, 0x7000 },
2426
2427                 { 0x03, 0x802f },
2428                 { 0x02, 0x4f02 },
2429                 { 0x01, 0x0409 },
2430                 { 0x00, 0xf0f9 },
2431                 { 0x04, 0x9800 },
2432                 { 0x04, 0x9000 },
2433
2434                 { 0x03, 0xdf01 },
2435                 { 0x02, 0xdf20 },
2436                 { 0x01, 0xff95 },
2437                 { 0x00, 0xba00 },
2438                 { 0x04, 0xa800 },
2439                 { 0x04, 0xa000 },
2440
2441                 { 0x03, 0xff41 },
2442                 { 0x02, 0xdf20 },
2443                 { 0x01, 0x0140 },
2444                 { 0x00, 0x00bb },
2445                 { 0x04, 0xb800 },
2446                 { 0x04, 0xb000 },
2447
2448                 { 0x03, 0xdf41 },
2449                 { 0x02, 0xdc60 },
2450                 { 0x01, 0x6340 },
2451                 { 0x00, 0x007d },
2452                 { 0x04, 0xd800 },
2453                 { 0x04, 0xd000 },
2454
2455                 { 0x03, 0xdf01 },
2456                 { 0x02, 0xdf20 },
2457                 { 0x01, 0x100a },
2458                 { 0x00, 0xa0ff },
2459                 { 0x04, 0xf800 },
2460                 { 0x04, 0xf000 },
2461
2462                 { 0x1f, 0x0000 },
2463                 { 0x0b, 0x0000 },
2464                 { 0x00, 0x9200 }
2465         };
2466
2467         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2468 }
2469
2470 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2471 {
2472         static const struct phy_reg phy_reg_init[] = {
2473                 { 0x1f, 0x0002 },
2474                 { 0x01, 0x90d0 },
2475                 { 0x1f, 0x0000 }
2476         };
2477
2478         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2479 }
2480
2481 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2482 {
2483         struct pci_dev *pdev = tp->pci_dev;
2484
2485         if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2486             (pdev->subsystem_device != 0xe000))
2487                 return;
2488
2489         rtl_writephy(tp, 0x1f, 0x0001);
2490         rtl_writephy(tp, 0x10, 0xf01b);
2491         rtl_writephy(tp, 0x1f, 0x0000);
2492 }
2493
2494 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2495 {
2496         static const struct phy_reg phy_reg_init[] = {
2497                 { 0x1f, 0x0001 },
2498                 { 0x04, 0x0000 },
2499                 { 0x03, 0x00a1 },
2500                 { 0x02, 0x0008 },
2501                 { 0x01, 0x0120 },
2502                 { 0x00, 0x1000 },
2503                 { 0x04, 0x0800 },
2504                 { 0x04, 0x9000 },
2505                 { 0x03, 0x802f },
2506                 { 0x02, 0x4f02 },
2507                 { 0x01, 0x0409 },
2508                 { 0x00, 0xf099 },
2509                 { 0x04, 0x9800 },
2510                 { 0x04, 0xa000 },
2511                 { 0x03, 0xdf01 },
2512                 { 0x02, 0xdf20 },
2513                 { 0x01, 0xff95 },
2514                 { 0x00, 0xba00 },
2515                 { 0x04, 0xa800 },
2516                 { 0x04, 0xf000 },
2517                 { 0x03, 0xdf01 },
2518                 { 0x02, 0xdf20 },
2519                 { 0x01, 0x101a },
2520                 { 0x00, 0xa0ff },
2521                 { 0x04, 0xf800 },
2522                 { 0x04, 0x0000 },
2523                 { 0x1f, 0x0000 },
2524
2525                 { 0x1f, 0x0001 },
2526                 { 0x10, 0xf41b },
2527                 { 0x14, 0xfb54 },
2528                 { 0x18, 0xf5c7 },
2529                 { 0x1f, 0x0000 },
2530
2531                 { 0x1f, 0x0001 },
2532                 { 0x17, 0x0cc0 },
2533                 { 0x1f, 0x0000 }
2534         };
2535
2536         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2537
2538         rtl8169scd_hw_phy_config_quirk(tp);
2539 }
2540
2541 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2542 {
2543         static const struct phy_reg phy_reg_init[] = {
2544                 { 0x1f, 0x0001 },
2545                 { 0x04, 0x0000 },
2546                 { 0x03, 0x00a1 },
2547                 { 0x02, 0x0008 },
2548                 { 0x01, 0x0120 },
2549                 { 0x00, 0x1000 },
2550                 { 0x04, 0x0800 },
2551                 { 0x04, 0x9000 },
2552                 { 0x03, 0x802f },
2553                 { 0x02, 0x4f02 },
2554                 { 0x01, 0x0409 },
2555                 { 0x00, 0xf099 },
2556                 { 0x04, 0x9800 },
2557                 { 0x04, 0xa000 },
2558                 { 0x03, 0xdf01 },
2559                 { 0x02, 0xdf20 },
2560                 { 0x01, 0xff95 },
2561                 { 0x00, 0xba00 },
2562                 { 0x04, 0xa800 },
2563                 { 0x04, 0xf000 },
2564                 { 0x03, 0xdf01 },
2565                 { 0x02, 0xdf20 },
2566                 { 0x01, 0x101a },
2567                 { 0x00, 0xa0ff },
2568                 { 0x04, 0xf800 },
2569                 { 0x04, 0x0000 },
2570                 { 0x1f, 0x0000 },
2571
2572                 { 0x1f, 0x0001 },
2573                 { 0x0b, 0x8480 },
2574                 { 0x1f, 0x0000 },
2575
2576                 { 0x1f, 0x0001 },
2577                 { 0x18, 0x67c7 },
2578                 { 0x04, 0x2000 },
2579                 { 0x03, 0x002f },
2580                 { 0x02, 0x4360 },
2581                 { 0x01, 0x0109 },
2582                 { 0x00, 0x3022 },
2583                 { 0x04, 0x2800 },
2584                 { 0x1f, 0x0000 },
2585
2586                 { 0x1f, 0x0001 },
2587                 { 0x17, 0x0cc0 },
2588                 { 0x1f, 0x0000 }
2589         };
2590
2591         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2592 }
2593
2594 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2595 {
2596         static const struct phy_reg phy_reg_init[] = {
2597                 { 0x10, 0xf41b },
2598                 { 0x1f, 0x0000 }
2599         };
2600
2601         rtl_writephy(tp, 0x1f, 0x0001);
2602         rtl_patchphy(tp, 0x16, 1 << 0);
2603
2604         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2605 }
2606
2607 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2608 {
2609         static const struct phy_reg phy_reg_init[] = {
2610                 { 0x1f, 0x0001 },
2611                 { 0x10, 0xf41b },
2612                 { 0x1f, 0x0000 }
2613         };
2614
2615         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2616 }
2617
2618 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2619 {
2620         static const struct phy_reg phy_reg_init[] = {
2621                 { 0x1f, 0x0000 },
2622                 { 0x1d, 0x0f00 },
2623                 { 0x1f, 0x0002 },
2624                 { 0x0c, 0x1ec8 },
2625                 { 0x1f, 0x0000 }
2626         };
2627
2628         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2629 }
2630
2631 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2632 {
2633         static const struct phy_reg phy_reg_init[] = {
2634                 { 0x1f, 0x0001 },
2635                 { 0x1d, 0x3d98 },
2636                 { 0x1f, 0x0000 }
2637         };
2638
2639         rtl_writephy(tp, 0x1f, 0x0000);
2640         rtl_patchphy(tp, 0x14, 1 << 5);
2641         rtl_patchphy(tp, 0x0d, 1 << 5);
2642
2643         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2644 }
2645
2646 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2647 {
2648         static const struct phy_reg phy_reg_init[] = {
2649                 { 0x1f, 0x0001 },
2650                 { 0x12, 0x2300 },
2651                 { 0x1f, 0x0002 },
2652                 { 0x00, 0x88d4 },
2653                 { 0x01, 0x82b1 },
2654                 { 0x03, 0x7002 },
2655                 { 0x08, 0x9e30 },
2656                 { 0x09, 0x01f0 },
2657                 { 0x0a, 0x5500 },
2658                 { 0x0c, 0x00c8 },
2659                 { 0x1f, 0x0003 },
2660                 { 0x12, 0xc096 },
2661                 { 0x16, 0x000a },
2662                 { 0x1f, 0x0000 },
2663                 { 0x1f, 0x0000 },
2664                 { 0x09, 0x2000 },
2665                 { 0x09, 0x0000 }
2666         };
2667
2668         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2669
2670         rtl_patchphy(tp, 0x14, 1 << 5);
2671         rtl_patchphy(tp, 0x0d, 1 << 5);
2672         rtl_writephy(tp, 0x1f, 0x0000);
2673 }
2674
2675 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2676 {
2677         static const struct phy_reg phy_reg_init[] = {
2678                 { 0x1f, 0x0001 },
2679                 { 0x12, 0x2300 },
2680                 { 0x03, 0x802f },
2681                 { 0x02, 0x4f02 },
2682                 { 0x01, 0x0409 },
2683                 { 0x00, 0xf099 },
2684                 { 0x04, 0x9800 },
2685                 { 0x04, 0x9000 },
2686                 { 0x1d, 0x3d98 },
2687                 { 0x1f, 0x0002 },
2688                 { 0x0c, 0x7eb8 },
2689                 { 0x06, 0x0761 },
2690                 { 0x1f, 0x0003 },
2691                 { 0x16, 0x0f0a },
2692                 { 0x1f, 0x0000 }
2693         };
2694
2695         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2696
2697         rtl_patchphy(tp, 0x16, 1 << 0);
2698         rtl_patchphy(tp, 0x14, 1 << 5);
2699         rtl_patchphy(tp, 0x0d, 1 << 5);
2700         rtl_writephy(tp, 0x1f, 0x0000);
2701 }
2702
2703 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2704 {
2705         static const struct phy_reg phy_reg_init[] = {
2706                 { 0x1f, 0x0001 },
2707                 { 0x12, 0x2300 },
2708                 { 0x1d, 0x3d98 },
2709                 { 0x1f, 0x0002 },
2710                 { 0x0c, 0x7eb8 },
2711                 { 0x06, 0x5461 },
2712                 { 0x1f, 0x0003 },
2713                 { 0x16, 0x0f0a },
2714                 { 0x1f, 0x0000 }
2715         };
2716
2717         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2718
2719         rtl_patchphy(tp, 0x16, 1 << 0);
2720         rtl_patchphy(tp, 0x14, 1 << 5);
2721         rtl_patchphy(tp, 0x0d, 1 << 5);
2722         rtl_writephy(tp, 0x1f, 0x0000);
2723 }
2724
2725 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2726 {
2727         rtl8168c_3_hw_phy_config(tp);
2728 }
2729
2730 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2731 {
2732         static const struct phy_reg phy_reg_init_0[] = {
2733                 /* Channel Estimation */
2734                 { 0x1f, 0x0001 },
2735                 { 0x06, 0x4064 },
2736                 { 0x07, 0x2863 },
2737                 { 0x08, 0x059c },
2738                 { 0x09, 0x26b4 },
2739                 { 0x0a, 0x6a19 },
2740                 { 0x0b, 0xdcc8 },
2741                 { 0x10, 0xf06d },
2742                 { 0x14, 0x7f68 },
2743                 { 0x18, 0x7fd9 },
2744                 { 0x1c, 0xf0ff },
2745                 { 0x1d, 0x3d9c },
2746                 { 0x1f, 0x0003 },
2747                 { 0x12, 0xf49f },
2748                 { 0x13, 0x070b },
2749                 { 0x1a, 0x05ad },
2750                 { 0x14, 0x94c0 },
2751
2752                 /*
2753                  * Tx Error Issue
2754                  * Enhance line driver power
2755                  */
2756                 { 0x1f, 0x0002 },
2757                 { 0x06, 0x5561 },
2758                 { 0x1f, 0x0005 },
2759                 { 0x05, 0x8332 },
2760                 { 0x06, 0x5561 },
2761
2762                 /*
2763                  * Can not link to 1Gbps with bad cable
2764                  * Decrease SNR threshold form 21.07dB to 19.04dB
2765                  */
2766                 { 0x1f, 0x0001 },
2767                 { 0x17, 0x0cc0 },
2768
2769                 { 0x1f, 0x0000 },
2770                 { 0x0d, 0xf880 }
2771         };
2772
2773         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2774
2775         /*
2776          * Rx Error Issue
2777          * Fine Tune Switching regulator parameter
2778          */
2779         rtl_writephy(tp, 0x1f, 0x0002);
2780         rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2781         rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
2782
2783         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2784                 static const struct phy_reg phy_reg_init[] = {
2785                         { 0x1f, 0x0002 },
2786                         { 0x05, 0x669a },
2787                         { 0x1f, 0x0005 },
2788                         { 0x05, 0x8330 },
2789                         { 0x06, 0x669a },
2790                         { 0x1f, 0x0002 }
2791                 };
2792                 int val;
2793
2794                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2795
2796                 val = rtl_readphy(tp, 0x0d);
2797
2798                 if ((val & 0x00ff) != 0x006c) {
2799                         static const u32 set[] = {
2800                                 0x0065, 0x0066, 0x0067, 0x0068,
2801                                 0x0069, 0x006a, 0x006b, 0x006c
2802                         };
2803                         int i;
2804
2805                         rtl_writephy(tp, 0x1f, 0x0002);
2806
2807                         val &= 0xff00;
2808                         for (i = 0; i < ARRAY_SIZE(set); i++)
2809                                 rtl_writephy(tp, 0x0d, val | set[i]);
2810                 }
2811         } else {
2812                 static const struct phy_reg phy_reg_init[] = {
2813                         { 0x1f, 0x0002 },
2814                         { 0x05, 0x6662 },
2815                         { 0x1f, 0x0005 },
2816                         { 0x05, 0x8330 },
2817                         { 0x06, 0x6662 }
2818                 };
2819
2820                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2821         }
2822
2823         /* RSET couple improve */
2824         rtl_writephy(tp, 0x1f, 0x0002);
2825         rtl_patchphy(tp, 0x0d, 0x0300);
2826         rtl_patchphy(tp, 0x0f, 0x0010);
2827
2828         /* Fine tune PLL performance */
2829         rtl_writephy(tp, 0x1f, 0x0002);
2830         rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2831         rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2832
2833         rtl_writephy(tp, 0x1f, 0x0005);
2834         rtl_writephy(tp, 0x05, 0x001b);
2835
2836         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2837
2838         rtl_writephy(tp, 0x1f, 0x0000);
2839 }
2840
2841 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2842 {
2843         static const struct phy_reg phy_reg_init_0[] = {
2844                 /* Channel Estimation */
2845                 { 0x1f, 0x0001 },
2846                 { 0x06, 0x4064 },
2847                 { 0x07, 0x2863 },
2848                 { 0x08, 0x059c },
2849                 { 0x09, 0x26b4 },
2850                 { 0x0a, 0x6a19 },
2851                 { 0x0b, 0xdcc8 },
2852                 { 0x10, 0xf06d },
2853                 { 0x14, 0x7f68 },
2854                 { 0x18, 0x7fd9 },
2855                 { 0x1c, 0xf0ff },
2856                 { 0x1d, 0x3d9c },
2857                 { 0x1f, 0x0003 },
2858                 { 0x12, 0xf49f },
2859                 { 0x13, 0x070b },
2860                 { 0x1a, 0x05ad },
2861                 { 0x14, 0x94c0 },
2862
2863                 /*
2864                  * Tx Error Issue
2865                  * Enhance line driver power
2866                  */
2867                 { 0x1f, 0x0002 },
2868                 { 0x06, 0x5561 },
2869                 { 0x1f, 0x0005 },
2870                 { 0x05, 0x8332 },
2871                 { 0x06, 0x5561 },
2872
2873                 /*
2874                  * Can not link to 1Gbps with bad cable
2875                  * Decrease SNR threshold form 21.07dB to 19.04dB
2876                  */
2877                 { 0x1f, 0x0001 },
2878                 { 0x17, 0x0cc0 },
2879
2880                 { 0x1f, 0x0000 },
2881                 { 0x0d, 0xf880 }
2882         };
2883
2884         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2885
2886         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2887                 static const struct phy_reg phy_reg_init[] = {
2888                         { 0x1f, 0x0002 },
2889                         { 0x05, 0x669a },
2890                         { 0x1f, 0x0005 },
2891                         { 0x05, 0x8330 },
2892                         { 0x06, 0x669a },
2893
2894                         { 0x1f, 0x0002 }
2895                 };
2896                 int val;
2897
2898                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2899
2900                 val = rtl_readphy(tp, 0x0d);
2901                 if ((val & 0x00ff) != 0x006c) {
2902                         static const u32 set[] = {
2903                                 0x0065, 0x0066, 0x0067, 0x0068,
2904                                 0x0069, 0x006a, 0x006b, 0x006c
2905                         };
2906                         int i;
2907
2908                         rtl_writephy(tp, 0x1f, 0x0002);
2909
2910                         val &= 0xff00;
2911                         for (i = 0; i < ARRAY_SIZE(set); i++)
2912                                 rtl_writephy(tp, 0x0d, val | set[i]);
2913                 }
2914         } else {
2915                 static const struct phy_reg phy_reg_init[] = {
2916                         { 0x1f, 0x0002 },
2917                         { 0x05, 0x2642 },
2918                         { 0x1f, 0x0005 },
2919                         { 0x05, 0x8330 },
2920                         { 0x06, 0x2642 }
2921                 };
2922
2923                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2924         }
2925
2926         /* Fine tune PLL performance */
2927         rtl_writephy(tp, 0x1f, 0x0002);
2928         rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2929         rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2930
2931         /* Switching regulator Slew rate */
2932         rtl_writephy(tp, 0x1f, 0x0002);
2933         rtl_patchphy(tp, 0x0f, 0x0017);
2934
2935         rtl_writephy(tp, 0x1f, 0x0005);
2936         rtl_writephy(tp, 0x05, 0x001b);
2937
2938         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
2939
2940         rtl_writephy(tp, 0x1f, 0x0000);
2941 }
2942
2943 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
2944 {
2945         static const struct phy_reg phy_reg_init[] = {
2946                 { 0x1f, 0x0002 },
2947                 { 0x10, 0x0008 },
2948                 { 0x0d, 0x006c },
2949
2950                 { 0x1f, 0x0000 },
2951                 { 0x0d, 0xf880 },
2952
2953                 { 0x1f, 0x0001 },
2954                 { 0x17, 0x0cc0 },
2955
2956                 { 0x1f, 0x0001 },
2957                 { 0x0b, 0xa4d8 },
2958                 { 0x09, 0x281c },
2959                 { 0x07, 0x2883 },
2960                 { 0x0a, 0x6b35 },
2961                 { 0x1d, 0x3da4 },
2962                 { 0x1c, 0xeffd },
2963                 { 0x14, 0x7f52 },
2964                 { 0x18, 0x7fc6 },
2965                 { 0x08, 0x0601 },
2966                 { 0x06, 0x4063 },
2967                 { 0x10, 0xf074 },
2968                 { 0x1f, 0x0003 },
2969                 { 0x13, 0x0789 },
2970                 { 0x12, 0xf4bd },
2971                 { 0x1a, 0x04fd },
2972                 { 0x14, 0x84b0 },
2973                 { 0x1f, 0x0000 },
2974                 { 0x00, 0x9200 },
2975
2976                 { 0x1f, 0x0005 },
2977                 { 0x01, 0x0340 },
2978                 { 0x1f, 0x0001 },
2979                 { 0x04, 0x4000 },
2980                 { 0x03, 0x1d21 },
2981                 { 0x02, 0x0c32 },
2982                 { 0x01, 0x0200 },
2983                 { 0x00, 0x5554 },
2984                 { 0x04, 0x4800 },
2985                 { 0x04, 0x4000 },
2986                 { 0x04, 0xf000 },
2987                 { 0x03, 0xdf01 },
2988                 { 0x02, 0xdf20 },
2989                 { 0x01, 0x101a },
2990                 { 0x00, 0xa0ff },
2991                 { 0x04, 0xf800 },
2992                 { 0x04, 0xf000 },
2993                 { 0x1f, 0x0000 },
2994
2995                 { 0x1f, 0x0007 },
2996                 { 0x1e, 0x0023 },
2997                 { 0x16, 0x0000 },
2998                 { 0x1f, 0x0000 }
2999         };
3000
3001         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3002 }
3003
3004 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
3005 {
3006         static const struct phy_reg phy_reg_init[] = {
3007                 { 0x1f, 0x0001 },
3008                 { 0x17, 0x0cc0 },
3009
3010                 { 0x1f, 0x0007 },
3011                 { 0x1e, 0x002d },
3012                 { 0x18, 0x0040 },
3013                 { 0x1f, 0x0000 }
3014         };
3015
3016         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3017         rtl_patchphy(tp, 0x0d, 1 << 5);
3018 }
3019
3020 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
3021 {
3022         static const struct phy_reg phy_reg_init[] = {
3023                 /* Enable Delay cap */
3024                 { 0x1f, 0x0005 },
3025                 { 0x05, 0x8b80 },
3026                 { 0x06, 0xc896 },
3027                 { 0x1f, 0x0000 },
3028
3029                 /* Channel estimation fine tune */
3030                 { 0x1f, 0x0001 },
3031                 { 0x0b, 0x6c20 },
3032                 { 0x07, 0x2872 },
3033                 { 0x1c, 0xefff },
3034                 { 0x1f, 0x0003 },
3035                 { 0x14, 0x6420 },
3036                 { 0x1f, 0x0000 },
3037
3038                 /* Update PFM & 10M TX idle timer */
3039                 { 0x1f, 0x0007 },
3040                 { 0x1e, 0x002f },
3041                 { 0x15, 0x1919 },
3042                 { 0x1f, 0x0000 },
3043
3044                 { 0x1f, 0x0007 },
3045                 { 0x1e, 0x00ac },
3046                 { 0x18, 0x0006 },
3047                 { 0x1f, 0x0000 }
3048         };
3049
3050         rtl_apply_firmware(tp);
3051
3052         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3053
3054         /* DCO enable for 10M IDLE Power */
3055         rtl_writephy(tp, 0x1f, 0x0007);
3056         rtl_writephy(tp, 0x1e, 0x0023);
3057         rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
3058         rtl_writephy(tp, 0x1f, 0x0000);
3059
3060         /* For impedance matching */
3061         rtl_writephy(tp, 0x1f, 0x0002);
3062         rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
3063         rtl_writephy(tp, 0x1f, 0x0000);
3064
3065         /* PHY auto speed down */
3066         rtl_writephy(tp, 0x1f, 0x0007);
3067         rtl_writephy(tp, 0x1e, 0x002d);
3068         rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
3069         rtl_writephy(tp, 0x1f, 0x0000);
3070         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3071
3072         rtl_writephy(tp, 0x1f, 0x0005);
3073         rtl_writephy(tp, 0x05, 0x8b86);
3074         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3075         rtl_writephy(tp, 0x1f, 0x0000);
3076
3077         rtl_writephy(tp, 0x1f, 0x0005);
3078         rtl_writephy(tp, 0x05, 0x8b85);
3079         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3080         rtl_writephy(tp, 0x1f, 0x0007);
3081         rtl_writephy(tp, 0x1e, 0x0020);
3082         rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
3083         rtl_writephy(tp, 0x1f, 0x0006);
3084         rtl_writephy(tp, 0x00, 0x5a00);
3085         rtl_writephy(tp, 0x1f, 0x0000);
3086         rtl_writephy(tp, 0x0d, 0x0007);
3087         rtl_writephy(tp, 0x0e, 0x003c);
3088         rtl_writephy(tp, 0x0d, 0x4007);
3089         rtl_writephy(tp, 0x0e, 0x0000);
3090         rtl_writephy(tp, 0x0d, 0x0000);
3091 }
3092
3093 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3094 {
3095         const u16 w[] = {
3096                 addr[0] | (addr[1] << 8),
3097                 addr[2] | (addr[3] << 8),
3098                 addr[4] | (addr[5] << 8)
3099         };
3100         const struct exgmac_reg e[] = {
3101                 { .addr = 0xe0, ERIAR_MASK_1111, .val = w[0] | (w[1] << 16) },
3102                 { .addr = 0xe4, ERIAR_MASK_1111, .val = w[2] },
3103                 { .addr = 0xf0, ERIAR_MASK_1111, .val = w[0] << 16 },
3104                 { .addr = 0xf4, ERIAR_MASK_1111, .val = w[1] | (w[2] << 16) }
3105         };
3106
3107         rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e));
3108 }
3109
3110 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3111 {
3112         static const struct phy_reg phy_reg_init[] = {
3113                 /* Enable Delay cap */
3114                 { 0x1f, 0x0004 },
3115                 { 0x1f, 0x0007 },
3116                 { 0x1e, 0x00ac },
3117                 { 0x18, 0x0006 },
3118                 { 0x1f, 0x0002 },
3119                 { 0x1f, 0x0000 },
3120                 { 0x1f, 0x0000 },
3121
3122                 /* Channel estimation fine tune */
3123                 { 0x1f, 0x0003 },
3124                 { 0x09, 0xa20f },
3125                 { 0x1f, 0x0000 },
3126                 { 0x1f, 0x0000 },
3127
3128                 /* Green Setting */
3129                 { 0x1f, 0x0005 },
3130                 { 0x05, 0x8b5b },
3131                 { 0x06, 0x9222 },
3132                 { 0x05, 0x8b6d },
3133                 { 0x06, 0x8000 },
3134                 { 0x05, 0x8b76 },
3135                 { 0x06, 0x8000 },
3136                 { 0x1f, 0x0000 }
3137         };
3138
3139         rtl_apply_firmware(tp);
3140
3141         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3142
3143         /* For 4-corner performance improve */
3144         rtl_writephy(tp, 0x1f, 0x0005);
3145         rtl_writephy(tp, 0x05, 0x8b80);
3146         rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
3147         rtl_writephy(tp, 0x1f, 0x0000);
3148
3149         /* PHY auto speed down */
3150         rtl_writephy(tp, 0x1f, 0x0004);
3151         rtl_writephy(tp, 0x1f, 0x0007);
3152         rtl_writephy(tp, 0x1e, 0x002d);
3153         rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3154         rtl_writephy(tp, 0x1f, 0x0002);
3155         rtl_writephy(tp, 0x1f, 0x0000);
3156         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3157
3158         /* improve 10M EEE waveform */
3159         rtl_writephy(tp, 0x1f, 0x0005);
3160         rtl_writephy(tp, 0x05, 0x8b86);
3161         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3162         rtl_writephy(tp, 0x1f, 0x0000);
3163
3164         /* Improve 2-pair detection performance */
3165         rtl_writephy(tp, 0x1f, 0x0005);
3166         rtl_writephy(tp, 0x05, 0x8b85);
3167         rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3168         rtl_writephy(tp, 0x1f, 0x0000);
3169
3170         /* EEE setting */
3171         rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003, ERIAR_EXGMAC);
3172         rtl_writephy(tp, 0x1f, 0x0005);
3173         rtl_writephy(tp, 0x05, 0x8b85);
3174         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3175         rtl_writephy(tp, 0x1f, 0x0004);
3176         rtl_writephy(tp, 0x1f, 0x0007);
3177         rtl_writephy(tp, 0x1e, 0x0020);
3178         rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
3179         rtl_writephy(tp, 0x1f, 0x0002);
3180         rtl_writephy(tp, 0x1f, 0x0000);
3181         rtl_writephy(tp, 0x0d, 0x0007);
3182         rtl_writephy(tp, 0x0e, 0x003c);
3183         rtl_writephy(tp, 0x0d, 0x4007);
3184         rtl_writephy(tp, 0x0e, 0x0000);
3185         rtl_writephy(tp, 0x0d, 0x0000);
3186
3187         /* Green feature */
3188         rtl_writephy(tp, 0x1f, 0x0003);
3189         rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
3190         rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
3191         rtl_writephy(tp, 0x1f, 0x0000);
3192
3193         /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3194         rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
3195 }
3196
3197 static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3198 {
3199         /* For 4-corner performance improve */
3200         rtl_writephy(tp, 0x1f, 0x0005);
3201         rtl_writephy(tp, 0x05, 0x8b80);
3202         rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000);
3203         rtl_writephy(tp, 0x1f, 0x0000);
3204
3205         /* PHY auto speed down */
3206         rtl_writephy(tp, 0x1f, 0x0007);
3207         rtl_writephy(tp, 0x1e, 0x002d);
3208         rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3209         rtl_writephy(tp, 0x1f, 0x0000);
3210         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3211
3212         /* Improve 10M EEE waveform */
3213         rtl_writephy(tp, 0x1f, 0x0005);
3214         rtl_writephy(tp, 0x05, 0x8b86);
3215         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3216         rtl_writephy(tp, 0x1f, 0x0000);
3217 }
3218
3219 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3220 {
3221         static const struct phy_reg phy_reg_init[] = {
3222                 /* Channel estimation fine tune */
3223                 { 0x1f, 0x0003 },
3224                 { 0x09, 0xa20f },
3225                 { 0x1f, 0x0000 },
3226
3227                 /* Modify green table for giga & fnet */
3228                 { 0x1f, 0x0005 },
3229                 { 0x05, 0x8b55 },
3230                 { 0x06, 0x0000 },
3231                 { 0x05, 0x8b5e },
3232                 { 0x06, 0x0000 },
3233                 { 0x05, 0x8b67 },
3234                 { 0x06, 0x0000 },
3235                 { 0x05, 0x8b70 },
3236                 { 0x06, 0x0000 },
3237                 { 0x1f, 0x0000 },
3238                 { 0x1f, 0x0007 },
3239                 { 0x1e, 0x0078 },
3240                 { 0x17, 0x0000 },
3241                 { 0x19, 0x00fb },
3242                 { 0x1f, 0x0000 },
3243
3244                 /* Modify green table for 10M */
3245                 { 0x1f, 0x0005 },
3246                 { 0x05, 0x8b79 },
3247                 { 0x06, 0xaa00 },
3248                 { 0x1f, 0x0000 },
3249
3250                 /* Disable hiimpedance detection (RTCT) */
3251                 { 0x1f, 0x0003 },
3252                 { 0x01, 0x328a },
3253                 { 0x1f, 0x0000 }
3254         };
3255
3256         rtl_apply_firmware(tp);
3257
3258         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3259
3260         rtl8168f_hw_phy_config(tp);
3261
3262         /* Improve 2-pair detection performance */
3263         rtl_writephy(tp, 0x1f, 0x0005);
3264         rtl_writephy(tp, 0x05, 0x8b85);
3265         rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3266         rtl_writephy(tp, 0x1f, 0x0000);
3267 }
3268
3269 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3270 {
3271         rtl_apply_firmware(tp);
3272
3273         rtl8168f_hw_phy_config(tp);
3274 }
3275
3276 static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3277 {
3278         static const struct phy_reg phy_reg_init[] = {
3279                 /* Channel estimation fine tune */
3280                 { 0x1f, 0x0003 },
3281                 { 0x09, 0xa20f },
3282                 { 0x1f, 0x0000 },
3283
3284                 /* Modify green table for giga & fnet */
3285                 { 0x1f, 0x0005 },
3286                 { 0x05, 0x8b55 },
3287                 { 0x06, 0x0000 },
3288                 { 0x05, 0x8b5e },
3289                 { 0x06, 0x0000 },
3290                 { 0x05, 0x8b67 },
3291                 { 0x06, 0x0000 },
3292                 { 0x05, 0x8b70 },
3293                 { 0x06, 0x0000 },
3294                 { 0x1f, 0x0000 },
3295                 { 0x1f, 0x0007 },
3296                 { 0x1e, 0x0078 },
3297                 { 0x17, 0x0000 },
3298                 { 0x19, 0x00aa },
3299                 { 0x1f, 0x0000 },
3300
3301                 /* Modify green table for 10M */
3302                 { 0x1f, 0x0005 },
3303                 { 0x05, 0x8b79 },
3304                 { 0x06, 0xaa00 },
3305                 { 0x1f, 0x0000 },
3306
3307                 /* Disable hiimpedance detection (RTCT) */
3308                 { 0x1f, 0x0003 },
3309                 { 0x01, 0x328a },
3310                 { 0x1f, 0x0000 }
3311         };
3312
3313
3314         rtl_apply_firmware(tp);
3315
3316         rtl8168f_hw_phy_config(tp);
3317
3318         /* Improve 2-pair detection performance */
3319         rtl_writephy(tp, 0x1f, 0x0005);
3320         rtl_writephy(tp, 0x05, 0x8b85);
3321         rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3322         rtl_writephy(tp, 0x1f, 0x0000);
3323
3324         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3325
3326         /* Modify green table for giga */
3327         rtl_writephy(tp, 0x1f, 0x0005);
3328         rtl_writephy(tp, 0x05, 0x8b54);
3329         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0800);
3330         rtl_writephy(tp, 0x05, 0x8b5d);
3331         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0800);
3332         rtl_writephy(tp, 0x05, 0x8a7c);
3333         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3334         rtl_writephy(tp, 0x05, 0x8a7f);
3335         rtl_w1w0_phy(tp, 0x06, 0x0100, 0x0000);
3336         rtl_writephy(tp, 0x05, 0x8a82);
3337         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3338         rtl_writephy(tp, 0x05, 0x8a85);
3339         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3340         rtl_writephy(tp, 0x05, 0x8a88);
3341         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3342         rtl_writephy(tp, 0x1f, 0x0000);
3343
3344         /* uc same-seed solution */
3345         rtl_writephy(tp, 0x1f, 0x0005);
3346         rtl_writephy(tp, 0x05, 0x8b85);
3347         rtl_w1w0_phy(tp, 0x06, 0x8000, 0x0000);
3348         rtl_writephy(tp, 0x1f, 0x0000);
3349
3350         /* eee setting */
3351         rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC);
3352         rtl_writephy(tp, 0x1f, 0x0005);
3353         rtl_writephy(tp, 0x05, 0x8b85);
3354         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3355         rtl_writephy(tp, 0x1f, 0x0004);
3356         rtl_writephy(tp, 0x1f, 0x0007);
3357         rtl_writephy(tp, 0x1e, 0x0020);
3358         rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
3359         rtl_writephy(tp, 0x1f, 0x0000);
3360         rtl_writephy(tp, 0x0d, 0x0007);
3361         rtl_writephy(tp, 0x0e, 0x003c);
3362         rtl_writephy(tp, 0x0d, 0x4007);
3363         rtl_writephy(tp, 0x0e, 0x0000);
3364         rtl_writephy(tp, 0x0d, 0x0000);
3365
3366         /* Green feature */
3367         rtl_writephy(tp, 0x1f, 0x0003);
3368         rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
3369         rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
3370         rtl_writephy(tp, 0x1f, 0x0000);
3371 }
3372
3373 static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3374 {
3375         static const u16 mac_ocp_patch[] = {
3376                 0xe008, 0xe01b, 0xe01d, 0xe01f,
3377                 0xe021, 0xe023, 0xe025, 0xe027,
3378                 0x49d2, 0xf10d, 0x766c, 0x49e2,
3379                 0xf00a, 0x1ec0, 0x8ee1, 0xc60a,
3380
3381                 0x77c0, 0x4870, 0x9fc0, 0x1ea0,
3382                 0xc707, 0x8ee1, 0x9d6c, 0xc603,
3383                 0xbe00, 0xb416, 0x0076, 0xe86c,
3384                 0xc602, 0xbe00, 0x0000, 0xc602,
3385
3386                 0xbe00, 0x0000, 0xc602, 0xbe00,
3387                 0x0000, 0xc602, 0xbe00, 0x0000,
3388                 0xc602, 0xbe00, 0x0000, 0xc602,
3389                 0xbe00, 0x0000, 0xc602, 0xbe00,
3390
3391                 0x0000, 0x0000, 0x0000, 0x0000
3392         };
3393         u32 i;
3394
3395         /* Patch code for GPHY reset */
3396         for (i = 0; i < ARRAY_SIZE(mac_ocp_patch); i++)
3397                 r8168_mac_ocp_write(tp, 0xf800 + 2*i, mac_ocp_patch[i]);
3398         r8168_mac_ocp_write(tp, 0xfc26, 0x8000);
3399         r8168_mac_ocp_write(tp, 0xfc28, 0x0075);
3400
3401         rtl_apply_firmware(tp);
3402
3403         if (r8168_phy_ocp_read(tp, 0xa460) & 0x0100)
3404                 rtl_w1w0_phy_ocp(tp, 0xbcc4, 0x0000, 0x8000);
3405         else
3406                 rtl_w1w0_phy_ocp(tp, 0xbcc4, 0x8000, 0x0000);
3407
3408         if (r8168_phy_ocp_read(tp, 0xa466) & 0x0100)
3409                 rtl_w1w0_phy_ocp(tp, 0xc41a, 0x0002, 0x0000);
3410         else
3411                 rtl_w1w0_phy_ocp(tp, 0xbcc4, 0x0000, 0x0002);
3412
3413         rtl_w1w0_phy_ocp(tp, 0xa442, 0x000c, 0x0000);
3414         rtl_w1w0_phy_ocp(tp, 0xa4b2, 0x0004, 0x0000);
3415
3416         r8168_phy_ocp_write(tp, 0xa436, 0x8012);
3417         rtl_w1w0_phy_ocp(tp, 0xa438, 0x8000, 0x0000);
3418
3419         rtl_w1w0_phy_ocp(tp, 0xc422, 0x4000, 0x2000);
3420 }
3421
3422 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
3423 {
3424         static const struct phy_reg phy_reg_init[] = {
3425                 { 0x1f, 0x0003 },
3426                 { 0x08, 0x441d },
3427                 { 0x01, 0x9100 },
3428                 { 0x1f, 0x0000 }
3429         };
3430
3431         rtl_writephy(tp, 0x1f, 0x0000);
3432         rtl_patchphy(tp, 0x11, 1 << 12);
3433         rtl_patchphy(tp, 0x19, 1 << 13);
3434         rtl_patchphy(tp, 0x10, 1 << 15);
3435
3436         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3437 }
3438
3439 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3440 {
3441         static const struct phy_reg phy_reg_init[] = {
3442                 { 0x1f, 0x0005 },
3443                 { 0x1a, 0x0000 },
3444                 { 0x1f, 0x0000 },
3445
3446                 { 0x1f, 0x0004 },
3447                 { 0x1c, 0x0000 },
3448                 { 0x1f, 0x0000 },
3449
3450                 { 0x1f, 0x0001 },
3451                 { 0x15, 0x7701 },
3452                 { 0x1f, 0x0000 }
3453         };
3454
3455         /* Disable ALDPS before ram code */
3456         rtl_writephy(tp, 0x1f, 0x0000);
3457         rtl_writephy(tp, 0x18, 0x0310);
3458         msleep(100);
3459
3460         rtl_apply_firmware(tp);
3461
3462         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3463 }
3464
3465 static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
3466 {
3467         /* Disable ALDPS before setting firmware */
3468         rtl_writephy(tp, 0x1f, 0x0000);
3469         rtl_writephy(tp, 0x18, 0x0310);
3470         msleep(20);
3471
3472         rtl_apply_firmware(tp);
3473
3474         /* EEE setting */
3475         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3476         rtl_writephy(tp, 0x1f, 0x0004);
3477         rtl_writephy(tp, 0x10, 0x401f);
3478         rtl_writephy(tp, 0x19, 0x7030);
3479         rtl_writephy(tp, 0x1f, 0x0000);
3480 }
3481
3482 static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
3483 {
3484         static const struct phy_reg phy_reg_init[] = {
3485                 { 0x1f, 0x0004 },
3486                 { 0x10, 0xc07f },
3487                 { 0x19, 0x7030 },
3488                 { 0x1f, 0x0000 }
3489         };
3490
3491         /* Disable ALDPS before ram code */
3492         rtl_writephy(tp, 0x1f, 0x0000);
3493         rtl_writephy(tp, 0x18, 0x0310);
3494         msleep(100);
3495
3496         rtl_apply_firmware(tp);
3497
3498         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3499         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3500
3501         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3502 }
3503
3504 static void rtl_hw_phy_config(struct net_device *dev)
3505 {
3506         struct rtl8169_private *tp = netdev_priv(dev);
3507
3508         rtl8169_print_mac_version(tp);
3509
3510         switch (tp->mac_version) {
3511         case RTL_GIGA_MAC_VER_01:
3512                 break;
3513         case RTL_GIGA_MAC_VER_02:
3514         case RTL_GIGA_MAC_VER_03:
3515                 rtl8169s_hw_phy_config(tp);
3516                 break;
3517         case RTL_GIGA_MAC_VER_04:
3518                 rtl8169sb_hw_phy_config(tp);
3519                 break;
3520         case RTL_GIGA_MAC_VER_05:
3521                 rtl8169scd_hw_phy_config(tp);
3522                 break;
3523         case RTL_GIGA_MAC_VER_06:
3524                 rtl8169sce_hw_phy_config(tp);
3525                 break;
3526         case RTL_GIGA_MAC_VER_07:
3527         case RTL_GIGA_MAC_VER_08:
3528         case RTL_GIGA_MAC_VER_09:
3529                 rtl8102e_hw_phy_config(tp);
3530                 break;
3531         case RTL_GIGA_MAC_VER_11:
3532                 rtl8168bb_hw_phy_config(tp);
3533                 break;
3534         case RTL_GIGA_MAC_VER_12:
3535                 rtl8168bef_hw_phy_config(tp);
3536                 break;
3537         case RTL_GIGA_MAC_VER_17:
3538                 rtl8168bef_hw_phy_config(tp);
3539                 break;
3540         case RTL_GIGA_MAC_VER_18:
3541                 rtl8168cp_1_hw_phy_config(tp);
3542                 break;
3543         case RTL_GIGA_MAC_VER_19:
3544                 rtl8168c_1_hw_phy_config(tp);
3545                 break;
3546         case RTL_GIGA_MAC_VER_20:
3547                 rtl8168c_2_hw_phy_config(tp);
3548                 break;
3549         case RTL_GIGA_MAC_VER_21:
3550                 rtl8168c_3_hw_phy_config(tp);
3551                 break;
3552         case RTL_GIGA_MAC_VER_22:
3553                 rtl8168c_4_hw_phy_config(tp);
3554                 break;
3555         case RTL_GIGA_MAC_VER_23:
3556         case RTL_GIGA_MAC_VER_24:
3557                 rtl8168cp_2_hw_phy_config(tp);
3558                 break;
3559         case RTL_GIGA_MAC_VER_25:
3560                 rtl8168d_1_hw_phy_config(tp);
3561                 break;
3562         case RTL_GIGA_MAC_VER_26:
3563                 rtl8168d_2_hw_phy_config(tp);
3564                 break;
3565         case RTL_GIGA_MAC_VER_27:
3566                 rtl8168d_3_hw_phy_config(tp);
3567                 break;
3568         case RTL_GIGA_MAC_VER_28:
3569                 rtl8168d_4_hw_phy_config(tp);
3570                 break;
3571         case RTL_GIGA_MAC_VER_29:
3572         case RTL_GIGA_MAC_VER_30:
3573                 rtl8105e_hw_phy_config(tp);
3574                 break;
3575         case RTL_GIGA_MAC_VER_31:
3576                 /* None. */
3577                 break;
3578         case RTL_GIGA_MAC_VER_32:
3579         case RTL_GIGA_MAC_VER_33:
3580                 rtl8168e_1_hw_phy_config(tp);
3581                 break;
3582         case RTL_GIGA_MAC_VER_34:
3583                 rtl8168e_2_hw_phy_config(tp);
3584                 break;
3585         case RTL_GIGA_MAC_VER_35:
3586                 rtl8168f_1_hw_phy_config(tp);
3587                 break;
3588         case RTL_GIGA_MAC_VER_36:
3589                 rtl8168f_2_hw_phy_config(tp);
3590                 break;
3591
3592         case RTL_GIGA_MAC_VER_37:
3593                 rtl8402_hw_phy_config(tp);
3594                 break;
3595
3596         case RTL_GIGA_MAC_VER_38:
3597                 rtl8411_hw_phy_config(tp);
3598                 break;
3599
3600         case RTL_GIGA_MAC_VER_39:
3601                 rtl8106e_hw_phy_config(tp);
3602                 break;
3603
3604         case RTL_GIGA_MAC_VER_40:
3605                 rtl8168g_1_hw_phy_config(tp);
3606                 break;
3607
3608         case RTL_GIGA_MAC_VER_41:
3609         default:
3610                 break;
3611         }
3612 }
3613
3614 static void rtl_phy_work(struct rtl8169_private *tp)
3615 {
3616         struct timer_list *timer = &tp->timer;
3617         void __iomem *ioaddr = tp->mmio_addr;
3618         unsigned long timeout = RTL8169_PHY_TIMEOUT;
3619
3620         assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
3621
3622         if (tp->phy_reset_pending(tp)) {
3623                 /*
3624                  * A busy loop could burn quite a few cycles on nowadays CPU.
3625                  * Let's delay the execution of the timer for a few ticks.
3626                  */
3627                 timeout = HZ/10;
3628                 goto out_mod_timer;
3629         }
3630
3631         if (tp->link_ok(ioaddr))
3632                 return;
3633
3634         netif_warn(tp, link, tp->dev, "PHY reset until link up\n");
3635
3636         tp->phy_reset_enable(tp);
3637
3638 out_mod_timer:
3639         mod_timer(timer, jiffies + timeout);
3640 }
3641
3642 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
3643 {
3644         if (!test_and_set_bit(flag, tp->wk.flags))
3645                 schedule_work(&tp->wk.work);
3646 }
3647
3648 static void rtl8169_phy_timer(unsigned long __opaque)
3649 {
3650         struct net_device *dev = (struct net_device *)__opaque;
3651         struct rtl8169_private *tp = netdev_priv(dev);
3652
3653         rtl_schedule_task(tp, RTL_FLAG_TASK_PHY_PENDING);
3654 }
3655
3656 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
3657                                   void __iomem *ioaddr)
3658 {
3659         iounmap(ioaddr);
3660         pci_release_regions(pdev);
3661         pci_clear_mwi(pdev);
3662         pci_disable_device(pdev);
3663         free_netdev(dev);
3664 }
3665
3666 DECLARE_RTL_COND(rtl_phy_reset_cond)
3667 {
3668         return tp->phy_reset_pending(tp);
3669 }
3670
3671 static void rtl8169_phy_reset(struct net_device *dev,
3672                               struct rtl8169_private *tp)
3673 {
3674         tp->phy_reset_enable(tp);
3675         rtl_msleep_loop_wait_low(tp, &rtl_phy_reset_cond, 1, 100);
3676 }
3677
3678 static bool rtl_tbi_enabled(struct rtl8169_private *tp)
3679 {
3680         void __iomem *ioaddr = tp->mmio_addr;
3681
3682         return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
3683             (RTL_R8(PHYstatus) & TBI_Enable);
3684 }
3685
3686 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
3687 {
3688         void __iomem *ioaddr = tp->mmio_addr;
3689
3690         rtl_hw_phy_config(dev);
3691
3692         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
3693                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3694                 RTL_W8(0x82, 0x01);
3695         }
3696
3697         pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
3698
3699         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3700                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
3701
3702         if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
3703                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3704                 RTL_W8(0x82, 0x01);
3705                 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
3706                 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
3707         }
3708
3709         rtl8169_phy_reset(dev, tp);
3710
3711         rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
3712                           ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3713                           ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
3714                           (tp->mii.supports_gmii ?
3715                            ADVERTISED_1000baseT_Half |
3716                            ADVERTISED_1000baseT_Full : 0));
3717
3718         if (rtl_tbi_enabled(tp))
3719                 netif_info(tp, link, dev, "TBI auto-negotiating\n");
3720 }
3721
3722 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
3723 {
3724         void __iomem *ioaddr = tp->mmio_addr;
3725
3726         rtl_lock_work(tp);
3727
3728         RTL_W8(Cfg9346, Cfg9346_Unlock);
3729
3730         RTL_W32(MAC4, addr[4] | addr[5] << 8);
3731         RTL_R32(MAC4);
3732
3733         RTL_W32(MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
3734         RTL_R32(MAC0);
3735
3736         if (tp->mac_version == RTL_GIGA_MAC_VER_34)
3737                 rtl_rar_exgmac_set(tp, addr);
3738
3739         RTL_W8(Cfg9346, Cfg9346_Lock);
3740
3741         rtl_unlock_work(tp);
3742 }
3743
3744 static int rtl_set_mac_address(struct net_device *dev, void *p)
3745 {
3746         struct rtl8169_private *tp = netdev_priv(dev);
3747         struct sockaddr *addr = p;
3748
3749         if (!is_valid_ether_addr(addr->sa_data))
3750                 return -EADDRNOTAVAIL;
3751
3752         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3753
3754         rtl_rar_set(tp, dev->dev_addr);
3755
3756         return 0;
3757 }
3758
3759 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3760 {
3761         struct rtl8169_private *tp = netdev_priv(dev);
3762         struct mii_ioctl_data *data = if_mii(ifr);
3763
3764         return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
3765 }
3766
3767 static int rtl_xmii_ioctl(struct rtl8169_private *tp,
3768                           struct mii_ioctl_data *data, int cmd)
3769 {
3770         switch (cmd) {
3771         case SIOCGMIIPHY:
3772                 data->phy_id = 32; /* Internal PHY */
3773                 return 0;
3774
3775         case SIOCGMIIREG:
3776                 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
3777                 return 0;
3778
3779         case SIOCSMIIREG:
3780                 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
3781                 return 0;
3782         }
3783         return -EOPNOTSUPP;
3784 }
3785
3786 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
3787 {
3788         return -EOPNOTSUPP;
3789 }
3790
3791 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
3792 {
3793         if (tp->features & RTL_FEATURE_MSI) {
3794                 pci_disable_msi(pdev);
3795                 tp->features &= ~RTL_FEATURE_MSI;
3796         }
3797 }
3798
3799 static void rtl_init_mdio_ops(struct rtl8169_private *tp)
3800 {
3801         struct mdio_ops *ops = &tp->mdio_ops;
3802
3803         switch (tp->mac_version) {
3804         case RTL_GIGA_MAC_VER_27:
3805                 ops->write      = r8168dp_1_mdio_write;
3806                 ops->read       = r8168dp_1_mdio_read;
3807                 break;
3808         case RTL_GIGA_MAC_VER_28:
3809         case RTL_GIGA_MAC_VER_31:
3810                 ops->write      = r8168dp_2_mdio_write;
3811                 ops->read       = r8168dp_2_mdio_read;
3812                 break;
3813         case RTL_GIGA_MAC_VER_40:
3814         case RTL_GIGA_MAC_VER_41:
3815                 ops->write      = r8168g_mdio_write;
3816                 ops->read       = r8168g_mdio_read;
3817                 break;
3818         default:
3819                 ops->write      = r8169_mdio_write;
3820                 ops->read       = r8169_mdio_read;
3821                 break;
3822         }
3823 }
3824
3825 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
3826 {
3827         void __iomem *ioaddr = tp->mmio_addr;
3828
3829         switch (tp->mac_version) {
3830         case RTL_GIGA_MAC_VER_25:
3831         case RTL_GIGA_MAC_VER_26:
3832         case RTL_GIGA_MAC_VER_29:
3833         case RTL_GIGA_MAC_VER_30:
3834         case RTL_GIGA_MAC_VER_32:
3835         case RTL_GIGA_MAC_VER_33:
3836         case RTL_GIGA_MAC_VER_34:
3837         case RTL_GIGA_MAC_VER_37:
3838         case RTL_GIGA_MAC_VER_38:
3839         case RTL_GIGA_MAC_VER_39:
3840         case RTL_GIGA_MAC_VER_40:
3841         case RTL_GIGA_MAC_VER_41:
3842                 RTL_W32(RxConfig, RTL_R32(RxConfig) |
3843                         AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
3844                 break;
3845         default:
3846                 break;
3847         }
3848 }
3849
3850 static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
3851 {
3852         if (!(__rtl8169_get_wol(tp) & WAKE_ANY))
3853                 return false;
3854
3855         rtl_writephy(tp, 0x1f, 0x0000);
3856         rtl_writephy(tp, MII_BMCR, 0x0000);
3857
3858         rtl_wol_suspend_quirk(tp);
3859
3860         return true;
3861 }
3862
3863 static void r810x_phy_power_down(struct rtl8169_private *tp)
3864 {
3865         rtl_writephy(tp, 0x1f, 0x0000);
3866         rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3867 }
3868
3869 static void r810x_phy_power_up(struct rtl8169_private *tp)
3870 {
3871         rtl_writephy(tp, 0x1f, 0x0000);
3872         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3873 }
3874
3875 static void r810x_pll_power_down(struct rtl8169_private *tp)
3876 {
3877         void __iomem *ioaddr = tp->mmio_addr;
3878
3879         if (rtl_wol_pll_power_down(tp))
3880                 return;
3881
3882         r810x_phy_power_down(tp);
3883
3884         switch (tp->mac_version) {
3885         case RTL_GIGA_MAC_VER_07:
3886         case RTL_GIGA_MAC_VER_08:
3887         case RTL_GIGA_MAC_VER_09:
3888         case RTL_GIGA_MAC_VER_10:
3889         case RTL_GIGA_MAC_VER_13:
3890         case RTL_GIGA_MAC_VER_16:
3891                 break;
3892         default:
3893                 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
3894                 break;
3895         }
3896 }
3897
3898 static void r810x_pll_power_up(struct rtl8169_private *tp)
3899 {
3900         void __iomem *ioaddr = tp->mmio_addr;
3901
3902         r810x_phy_power_up(tp);
3903
3904         switch (tp->mac_version) {
3905         case RTL_GIGA_MAC_VER_07:
3906         case RTL_GIGA_MAC_VER_08:
3907         case RTL_GIGA_MAC_VER_09:
3908         case RTL_GIGA_MAC_VER_10:
3909         case RTL_GIGA_MAC_VER_13:
3910         case RTL_GIGA_MAC_VER_16:
3911                 break;
3912         default:
3913                 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
3914                 break;
3915         }
3916 }
3917
3918 static void r8168_phy_power_up(struct rtl8169_private *tp)
3919 {
3920         rtl_writephy(tp, 0x1f, 0x0000);
3921         switch (tp->mac_version) {
3922         case RTL_GIGA_MAC_VER_11:
3923         case RTL_GIGA_MAC_VER_12:
3924         case RTL_GIGA_MAC_VER_17:
3925         case RTL_GIGA_MAC_VER_18:
3926         case RTL_GIGA_MAC_VER_19:
3927         case RTL_GIGA_MAC_VER_20:
3928         case RTL_GIGA_MAC_VER_21:
3929         case RTL_GIGA_MAC_VER_22:
3930         case RTL_GIGA_MAC_VER_23:
3931         case RTL_GIGA_MAC_VER_24:
3932         case RTL_GIGA_MAC_VER_25:
3933         case RTL_GIGA_MAC_VER_26:
3934         case RTL_GIGA_MAC_VER_27:
3935         case RTL_GIGA_MAC_VER_28:
3936         case RTL_GIGA_MAC_VER_31:
3937                 rtl_writephy(tp, 0x0e, 0x0000);
3938                 break;
3939         default:
3940                 break;
3941         }
3942         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3943 }
3944
3945 static void r8168_phy_power_down(struct rtl8169_private *tp)
3946 {
3947         rtl_writephy(tp, 0x1f, 0x0000);
3948         switch (tp->mac_version) {
3949         case RTL_GIGA_MAC_VER_32:
3950         case RTL_GIGA_MAC_VER_33:
3951                 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
3952                 break;
3953
3954         case RTL_GIGA_MAC_VER_11:
3955         case RTL_GIGA_MAC_VER_12:
3956         case RTL_GIGA_MAC_VER_17:
3957         case RTL_GIGA_MAC_VER_18:
3958         case RTL_GIGA_MAC_VER_19:
3959         case RTL_GIGA_MAC_VER_20:
3960         case RTL_GIGA_MAC_VER_21:
3961         case RTL_GIGA_MAC_VER_22:
3962         case RTL_GIGA_MAC_VER_23:
3963         case RTL_GIGA_MAC_VER_24:
3964         case RTL_GIGA_MAC_VER_25:
3965         case RTL_GIGA_MAC_VER_26:
3966         case RTL_GIGA_MAC_VER_27:
3967         case RTL_GIGA_MAC_VER_28:
3968         case RTL_GIGA_MAC_VER_31:
3969                 rtl_writephy(tp, 0x0e, 0x0200);
3970         default:
3971                 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3972                 break;
3973         }
3974 }
3975
3976 static void r8168_pll_power_down(struct rtl8169_private *tp)
3977 {
3978         void __iomem *ioaddr = tp->mmio_addr;
3979
3980         if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3981              tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3982              tp->mac_version == RTL_GIGA_MAC_VER_31) &&
3983             r8168dp_check_dash(tp)) {
3984                 return;
3985         }
3986
3987         if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
3988              tp->mac_version == RTL_GIGA_MAC_VER_24) &&
3989             (RTL_R16(CPlusCmd) & ASF)) {
3990                 return;
3991         }
3992
3993         if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3994             tp->mac_version == RTL_GIGA_MAC_VER_33)
3995                 rtl_ephy_write(tp, 0x19, 0xff64);
3996
3997         if (rtl_wol_pll_power_down(tp))
3998                 return;
3999
4000         r8168_phy_power_down(tp);
4001
4002         switch (tp->mac_version) {
4003         case RTL_GIGA_MAC_VER_25:
4004         case RTL_GIGA_MAC_VER_26:
4005         case RTL_GIGA_MAC_VER_27:
4006         case RTL_GIGA_MAC_VER_28:
4007         case RTL_GIGA_MAC_VER_31:
4008         case RTL_GIGA_MAC_VER_32:
4009         case RTL_GIGA_MAC_VER_33:
4010                 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
4011                 break;
4012         }
4013 }
4014
4015 static void r8168_pll_power_up(struct rtl8169_private *tp)
4016 {
4017         void __iomem *ioaddr = tp->mmio_addr;
4018
4019         switch (tp->mac_version) {
4020         case RTL_GIGA_MAC_VER_25:
4021         case RTL_GIGA_MAC_VER_26:
4022         case RTL_GIGA_MAC_VER_27:
4023         case RTL_GIGA_MAC_VER_28:
4024         case RTL_GIGA_MAC_VER_31:
4025         case RTL_GIGA_MAC_VER_32:
4026         case RTL_GIGA_MAC_VER_33:
4027                 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
4028                 break;
4029         }
4030
4031         r8168_phy_power_up(tp);
4032 }
4033
4034 static void rtl_generic_op(struct rtl8169_private *tp,
4035                            void (*op)(struct rtl8169_private *))
4036 {
4037         if (op)
4038                 op(tp);
4039 }
4040
4041 static void rtl_pll_power_down(struct rtl8169_private *tp)
4042 {
4043         rtl_generic_op(tp, tp->pll_power_ops.down);
4044 }
4045
4046 static void rtl_pll_power_up(struct rtl8169_private *tp)
4047 {
4048         rtl_generic_op(tp, tp->pll_power_ops.up);
4049 }
4050
4051 static void rtl_init_pll_power_ops(struct rtl8169_private *tp)
4052 {
4053         struct pll_power_ops *ops = &tp->pll_power_ops;
4054
4055         switch (tp->mac_version) {
4056         case RTL_GIGA_MAC_VER_07:
4057         case RTL_GIGA_MAC_VER_08:
4058         case RTL_GIGA_MAC_VER_09:
4059         case RTL_GIGA_MAC_VER_10:
4060         case RTL_GIGA_MAC_VER_16:
4061         case RTL_GIGA_MAC_VER_29:
4062         case RTL_GIGA_MAC_VER_30:
4063         case RTL_GIGA_MAC_VER_37:
4064         case RTL_GIGA_MAC_VER_39:
4065                 ops->down       = r810x_pll_power_down;
4066                 ops->up         = r810x_pll_power_up;
4067                 break;
4068
4069         case RTL_GIGA_MAC_VER_11:
4070         case RTL_GIGA_MAC_VER_12:
4071         case RTL_GIGA_MAC_VER_17:
4072         case RTL_GIGA_MAC_VER_18:
4073         case RTL_GIGA_MAC_VER_19:
4074         case RTL_GIGA_MAC_VER_20:
4075         case RTL_GIGA_MAC_VER_21:
4076         case RTL_GIGA_MAC_VER_22:
4077         case RTL_GIGA_MAC_VER_23:
4078         case RTL_GIGA_MAC_VER_24:
4079         case RTL_GIGA_MAC_VER_25:
4080         case RTL_GIGA_MAC_VER_26:
4081         case RTL_GIGA_MAC_VER_27:
4082         case RTL_GIGA_MAC_VER_28:
4083         case RTL_GIGA_MAC_VER_31:
4084         case RTL_GIGA_MAC_VER_32:
4085         case RTL_GIGA_MAC_VER_33:
4086         case RTL_GIGA_MAC_VER_34:
4087         case RTL_GIGA_MAC_VER_35:
4088         case RTL_GIGA_MAC_VER_36:
4089         case RTL_GIGA_MAC_VER_38:
4090         case RTL_GIGA_MAC_VER_40:
4091         case RTL_GIGA_MAC_VER_41:
4092                 ops->down       = r8168_pll_power_down;
4093                 ops->up         = r8168_pll_power_up;
4094                 break;
4095
4096         default:
4097                 ops->down       = NULL;
4098                 ops->up         = NULL;
4099                 break;
4100         }
4101 }
4102
4103 static void rtl_init_rxcfg(struct rtl8169_private *tp)
4104 {
4105         void __iomem *ioaddr = tp->mmio_addr;
4106
4107         switch (tp->mac_version) {
4108         case RTL_GIGA_MAC_VER_01:
4109         case RTL_GIGA_MAC_VER_02:
4110         case RTL_GIGA_MAC_VER_03:
4111         case RTL_GIGA_MAC_VER_04:
4112         case RTL_GIGA_MAC_VER_05:
4113         case RTL_GIGA_MAC_VER_06:
4114         case RTL_GIGA_MAC_VER_10:
4115         case RTL_GIGA_MAC_VER_11:
4116         case RTL_GIGA_MAC_VER_12:
4117         case RTL_GIGA_MAC_VER_13:
4118         case RTL_GIGA_MAC_VER_14:
4119         case RTL_GIGA_MAC_VER_15:
4120         case RTL_GIGA_MAC_VER_16:
4121         case RTL_GIGA_MAC_VER_17:
4122                 RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
4123                 break;
4124         case RTL_GIGA_MAC_VER_18:
4125         case RTL_GIGA_MAC_VER_19:
4126         case RTL_GIGA_MAC_VER_20:
4127         case RTL_GIGA_MAC_VER_21:
4128         case RTL_GIGA_MAC_VER_22:
4129         case RTL_GIGA_MAC_VER_23:
4130         case RTL_GIGA_MAC_VER_24:
4131         case RTL_GIGA_MAC_VER_34:
4132                 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
4133                 break;
4134         default:
4135                 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
4136                 break;
4137         }
4138 }
4139
4140 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4141 {
4142         tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
4143 }
4144
4145 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
4146 {
4147         void __iomem *ioaddr = tp->mmio_addr;
4148
4149         RTL_W8(Cfg9346, Cfg9346_Unlock);
4150         rtl_generic_op(tp, tp->jumbo_ops.enable);
4151         RTL_W8(Cfg9346, Cfg9346_Lock);
4152 }
4153
4154 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
4155 {
4156         void __iomem *ioaddr = tp->mmio_addr;
4157
4158         RTL_W8(Cfg9346, Cfg9346_Unlock);
4159         rtl_generic_op(tp, tp->jumbo_ops.disable);
4160         RTL_W8(Cfg9346, Cfg9346_Lock);
4161 }
4162
4163 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
4164 {
4165         void __iomem *ioaddr = tp->mmio_addr;
4166
4167         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4168         RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
4169         rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
4170 }
4171
4172 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
4173 {
4174         void __iomem *ioaddr = tp->mmio_addr;
4175
4176         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4177         RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
4178         rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
4179 }
4180
4181 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
4182 {
4183         void __iomem *ioaddr = tp->mmio_addr;
4184
4185         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4186 }
4187
4188 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
4189 {
4190         void __iomem *ioaddr = tp->mmio_addr;
4191
4192         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4193 }
4194
4195 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
4196 {
4197         void __iomem *ioaddr = tp->mmio_addr;
4198
4199         RTL_W8(MaxTxPacketSize, 0x3f);
4200         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4201         RTL_W8(Config4, RTL_R8(Config4) | 0x01);
4202         rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
4203 }
4204
4205 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
4206 {
4207         void __iomem *ioaddr = tp->mmio_addr;
4208
4209         RTL_W8(MaxTxPacketSize, 0x0c);
4210         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4211         RTL_W8(Config4, RTL_R8(Config4) & ~0x01);
4212         rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
4213 }
4214
4215 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
4216 {
4217         rtl_tx_performance_tweak(tp->pci_dev,
4218                 (0x2 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4219 }
4220
4221 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
4222 {
4223         rtl_tx_performance_tweak(tp->pci_dev,
4224                 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4225 }
4226
4227 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
4228 {
4229         void __iomem *ioaddr = tp->mmio_addr;
4230
4231         r8168b_0_hw_jumbo_enable(tp);
4232
4233         RTL_W8(Config4, RTL_R8(Config4) | (1 << 0));
4234 }
4235
4236 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
4237 {
4238         void __iomem *ioaddr = tp->mmio_addr;
4239
4240         r8168b_0_hw_jumbo_disable(tp);
4241
4242         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
4243 }
4244
4245 static void rtl_init_jumbo_ops(struct rtl8169_private *tp)
4246 {
4247         struct jumbo_ops *ops = &tp->jumbo_ops;
4248
4249         switch (tp->mac_version) {
4250         case RTL_GIGA_MAC_VER_11:
4251                 ops->disable    = r8168b_0_hw_jumbo_disable;
4252                 ops->enable     = r8168b_0_hw_jumbo_enable;
4253                 break;
4254         case RTL_GIGA_MAC_VER_12:
4255         case RTL_GIGA_MAC_VER_17:
4256                 ops->disable    = r8168b_1_hw_jumbo_disable;
4257                 ops->enable     = r8168b_1_hw_jumbo_enable;
4258                 break;
4259         case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
4260         case RTL_GIGA_MAC_VER_19:
4261         case RTL_GIGA_MAC_VER_20:
4262         case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
4263         case RTL_GIGA_MAC_VER_22:
4264         case RTL_GIGA_MAC_VER_23:
4265         case RTL_GIGA_MAC_VER_24:
4266         case RTL_GIGA_MAC_VER_25:
4267         case RTL_GIGA_MAC_VER_26:
4268                 ops->disable    = r8168c_hw_jumbo_disable;
4269                 ops->enable     = r8168c_hw_jumbo_enable;
4270                 break;
4271         case RTL_GIGA_MAC_VER_27:
4272         case RTL_GIGA_MAC_VER_28:
4273                 ops->disable    = r8168dp_hw_jumbo_disable;
4274                 ops->enable     = r8168dp_hw_jumbo_enable;
4275                 break;
4276         case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
4277         case RTL_GIGA_MAC_VER_32:
4278         case RTL_GIGA_MAC_VER_33:
4279         case RTL_GIGA_MAC_VER_34:
4280                 ops->disable    = r8168e_hw_jumbo_disable;
4281                 ops->enable     = r8168e_hw_jumbo_enable;
4282                 break;
4283
4284         /*
4285          * No action needed for jumbo frames with 8169.
4286          * No jumbo for 810x at all.
4287          */
4288         case RTL_GIGA_MAC_VER_40:
4289         case RTL_GIGA_MAC_VER_41:
4290         default:
4291                 ops->disable    = NULL;
4292                 ops->enable     = NULL;
4293                 break;
4294         }
4295 }
4296
4297 DECLARE_RTL_COND(rtl_chipcmd_cond)
4298 {
4299         void __iomem *ioaddr = tp->mmio_addr;
4300
4301         return RTL_R8(ChipCmd) & CmdReset;
4302 }
4303
4304 static void rtl_hw_reset(struct rtl8169_private *tp)
4305 {
4306         void __iomem *ioaddr = tp->mmio_addr;
4307
4308         RTL_W8(ChipCmd, CmdReset);
4309
4310         rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
4311 }
4312
4313 static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
4314 {
4315         struct rtl_fw *rtl_fw;
4316         const char *name;
4317         int rc = -ENOMEM;
4318
4319         name = rtl_lookup_firmware_name(tp);
4320         if (!name)
4321                 goto out_no_firmware;
4322
4323         rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
4324         if (!rtl_fw)
4325                 goto err_warn;
4326
4327         rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
4328         if (rc < 0)
4329                 goto err_free;
4330
4331         rc = rtl_check_firmware(tp, rtl_fw);
4332         if (rc < 0)
4333                 goto err_release_firmware;
4334
4335         tp->rtl_fw = rtl_fw;
4336 out:
4337         return;
4338
4339 err_release_firmware:
4340         release_firmware(rtl_fw->fw);
4341 err_free:
4342         kfree(rtl_fw);
4343 err_warn:
4344         netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
4345                    name, rc);
4346 out_no_firmware:
4347         tp->rtl_fw = NULL;
4348         goto out;
4349 }
4350
4351 static void rtl_request_firmware(struct rtl8169_private *tp)
4352 {
4353         if (IS_ERR(tp->rtl_fw))
4354                 rtl_request_uncached_firmware(tp);
4355 }
4356
4357 static void rtl_rx_close(struct rtl8169_private *tp)
4358 {
4359         void __iomem *ioaddr = tp->mmio_addr;
4360
4361         RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
4362 }
4363
4364 DECLARE_RTL_COND(rtl_npq_cond)
4365 {
4366         void __iomem *ioaddr = tp->mmio_addr;
4367
4368         return RTL_R8(TxPoll) & NPQ;
4369 }
4370
4371 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
4372 {
4373         void __iomem *ioaddr = tp->mmio_addr;
4374
4375         return RTL_R32(TxConfig) & TXCFG_EMPTY;
4376 }
4377
4378 static void rtl8169_hw_reset(struct rtl8169_private *tp)
4379 {
4380         void __iomem *ioaddr = tp->mmio_addr;
4381
4382         /* Disable interrupts */
4383         rtl8169_irq_mask_and_ack(tp);
4384
4385         rtl_rx_close(tp);
4386
4387         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4388             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4389             tp->mac_version == RTL_GIGA_MAC_VER_31) {
4390                 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
4391         } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
4392                    tp->mac_version == RTL_GIGA_MAC_VER_35 ||
4393                    tp->mac_version == RTL_GIGA_MAC_VER_36 ||
4394                    tp->mac_version == RTL_GIGA_MAC_VER_37 ||
4395                    tp->mac_version == RTL_GIGA_MAC_VER_40 ||
4396                    tp->mac_version == RTL_GIGA_MAC_VER_41 ||
4397                    tp->mac_version == RTL_GIGA_MAC_VER_38) {
4398                 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
4399                 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
4400         } else {
4401                 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
4402                 udelay(100);
4403         }
4404
4405         rtl_hw_reset(tp);
4406 }
4407
4408 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
4409 {
4410         void __iomem *ioaddr = tp->mmio_addr;
4411
4412         /* Set DMA burst size and Interframe Gap Time */
4413         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4414                 (InterFrameGap << TxInterFrameGapShift));
4415 }
4416
4417 static void rtl_hw_start(struct net_device *dev)
4418 {
4419         struct rtl8169_private *tp = netdev_priv(dev);
4420
4421         tp->hw_start(dev);
4422
4423         rtl_irq_enable_all(tp);
4424 }
4425
4426 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
4427                                          void __iomem *ioaddr)
4428 {
4429         /*
4430          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4431          * register to be written before TxDescAddrLow to work.
4432          * Switching from MMIO to I/O access fixes the issue as well.
4433          */
4434         RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4435         RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4436         RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4437         RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
4438 }
4439
4440 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
4441 {
4442         u16 cmd;
4443
4444         cmd = RTL_R16(CPlusCmd);
4445         RTL_W16(CPlusCmd, cmd);
4446         return cmd;
4447 }
4448
4449 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
4450 {
4451         /* Low hurts. Let's disable the filtering. */
4452         RTL_W16(RxMaxSize, rx_buf_sz + 1);
4453 }
4454
4455 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
4456 {
4457         static const struct rtl_cfg2_info {
4458                 u32 mac_version;
4459                 u32 clk;
4460                 u32 val;
4461         } cfg2_info [] = {
4462                 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
4463                 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
4464                 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
4465                 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
4466         };
4467         const struct rtl_cfg2_info *p = cfg2_info;
4468         unsigned int i;
4469         u32 clk;
4470
4471         clk = RTL_R8(Config2) & PCI_Clock_66MHz;
4472         for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
4473                 if ((p->mac_version == mac_version) && (p->clk == clk)) {
4474                         RTL_W32(0x7c, p->val);
4475                         break;
4476                 }
4477         }
4478 }
4479
4480 static void rtl_set_rx_mode(struct net_device *dev)
4481 {
4482         struct rtl8169_private *tp = netdev_priv(dev);
4483         void __iomem *ioaddr = tp->mmio_addr;
4484         u32 mc_filter[2];       /* Multicast hash filter */
4485         int rx_mode;
4486         u32 tmp = 0;
4487
4488         if (dev->flags & IFF_PROMISC) {
4489                 /* Unconditionally log net taps. */
4490                 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4491                 rx_mode =
4492                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4493                     AcceptAllPhys;
4494                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4495         } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4496                    (dev->flags & IFF_ALLMULTI)) {
4497                 /* Too many to filter perfectly -- accept all multicasts. */
4498                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4499                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4500         } else {
4501                 struct netdev_hw_addr *ha;
4502
4503                 rx_mode = AcceptBroadcast | AcceptMyPhys;
4504                 mc_filter[1] = mc_filter[0] = 0;
4505                 netdev_for_each_mc_addr(ha, dev) {
4506                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4507                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4508                         rx_mode |= AcceptMulticast;
4509                 }
4510         }
4511
4512         if (dev->features & NETIF_F_RXALL)
4513                 rx_mode |= (AcceptErr | AcceptRunt);
4514
4515         tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
4516
4517         if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4518                 u32 data = mc_filter[0];
4519
4520                 mc_filter[0] = swab32(mc_filter[1]);
4521                 mc_filter[1] = swab32(data);
4522         }
4523
4524         if (tp->mac_version == RTL_GIGA_MAC_VER_35)
4525                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4526
4527         RTL_W32(MAR0 + 4, mc_filter[1]);
4528         RTL_W32(MAR0 + 0, mc_filter[0]);
4529
4530         RTL_W32(RxConfig, tmp);
4531 }
4532
4533 static void rtl_hw_start_8169(struct net_device *dev)
4534 {
4535         struct rtl8169_private *tp = netdev_priv(dev);
4536         void __iomem *ioaddr = tp->mmio_addr;
4537         struct pci_dev *pdev = tp->pci_dev;
4538
4539         if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
4540                 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
4541                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
4542         }
4543
4544         RTL_W8(Cfg9346, Cfg9346_Unlock);
4545         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4546             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4547             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4548             tp->mac_version == RTL_GIGA_MAC_VER_04)
4549                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4550
4551         rtl_init_rxcfg(tp);
4552
4553         RTL_W8(EarlyTxThres, NoEarlyTx);
4554
4555         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4556
4557         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4558             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4559             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4560             tp->mac_version == RTL_GIGA_MAC_VER_04)
4561                 rtl_set_rx_tx_config_registers(tp);
4562
4563         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
4564
4565         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4566             tp->mac_version == RTL_GIGA_MAC_VER_03) {
4567                 dprintk("Set MAC Reg C+CR Offset 0xE0. "
4568                         "Bit-3 and bit-14 MUST be 1\n");
4569                 tp->cp_cmd |= (1 << 14);
4570         }
4571
4572         RTL_W16(CPlusCmd, tp->cp_cmd);
4573
4574         rtl8169_set_magic_reg(ioaddr, tp->mac_version);
4575
4576         /*
4577          * Undocumented corner. Supposedly:
4578          * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4579          */
4580         RTL_W16(IntrMitigate, 0x0000);
4581
4582         rtl_set_rx_tx_desc_registers(tp, ioaddr);
4583
4584         if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
4585             tp->mac_version != RTL_GIGA_MAC_VER_02 &&
4586             tp->mac_version != RTL_GIGA_MAC_VER_03 &&
4587             tp->mac_version != RTL_GIGA_MAC_VER_04) {
4588                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4589                 rtl_set_rx_tx_config_registers(tp);
4590         }
4591
4592         RTL_W8(Cfg9346, Cfg9346_Lock);
4593
4594         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4595         RTL_R8(IntrMask);
4596
4597         RTL_W32(RxMissed, 0);
4598
4599         rtl_set_rx_mode(dev);
4600
4601         /* no early-rx interrupts */
4602         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
4603 }
4604
4605 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
4606 {
4607         if (tp->csi_ops.write)
4608                 tp->csi_ops.write(tp, addr, value);
4609 }
4610
4611 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
4612 {
4613         return tp->csi_ops.read ? tp->csi_ops.read(tp, addr) : ~0;
4614 }
4615
4616 static void rtl_csi_access_enable(struct rtl8169_private *tp, u32 bits)
4617 {
4618         u32 csi;
4619
4620         csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
4621         rtl_csi_write(tp, 0x070c, csi | bits);
4622 }
4623
4624 static void rtl_csi_access_enable_1(struct rtl8169_private *tp)
4625 {
4626         rtl_csi_access_enable(tp, 0x17000000);
4627 }
4628
4629 static void rtl_csi_access_enable_2(struct rtl8169_private *tp)
4630 {
4631         rtl_csi_access_enable(tp, 0x27000000);
4632 }
4633
4634 DECLARE_RTL_COND(rtl_csiar_cond)
4635 {
4636         void __iomem *ioaddr = tp->mmio_addr;
4637
4638         return RTL_R32(CSIAR) & CSIAR_FLAG;
4639 }
4640
4641 static void r8169_csi_write(struct rtl8169_private *tp, int addr, int value)
4642 {
4643         void __iomem *ioaddr = tp->mmio_addr;
4644
4645         RTL_W32(CSIDR, value);
4646         RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4647                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
4648
4649         rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
4650 }
4651
4652 static u32 r8169_csi_read(struct rtl8169_private *tp, int addr)
4653 {
4654         void __iomem *ioaddr = tp->mmio_addr;
4655
4656         RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
4657                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
4658
4659         return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4660                 RTL_R32(CSIDR) : ~0;
4661 }
4662
4663 static void r8402_csi_write(struct rtl8169_private *tp, int addr, int value)
4664 {
4665         void __iomem *ioaddr = tp->mmio_addr;
4666
4667         RTL_W32(CSIDR, value);
4668         RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4669                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
4670                 CSIAR_FUNC_NIC);
4671
4672         rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
4673 }
4674
4675 static u32 r8402_csi_read(struct rtl8169_private *tp, int addr)
4676 {
4677         void __iomem *ioaddr = tp->mmio_addr;
4678
4679         RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC |
4680                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
4681
4682         return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4683                 RTL_R32(CSIDR) : ~0;
4684 }
4685
4686 static void rtl_init_csi_ops(struct rtl8169_private *tp)
4687 {
4688         struct csi_ops *ops = &tp->csi_ops;
4689
4690         switch (tp->mac_version) {
4691         case RTL_GIGA_MAC_VER_01:
4692         case RTL_GIGA_MAC_VER_02:
4693         case RTL_GIGA_MAC_VER_03:
4694         case RTL_GIGA_MAC_VER_04:
4695         case RTL_GIGA_MAC_VER_05:
4696         case RTL_GIGA_MAC_VER_06:
4697         case RTL_GIGA_MAC_VER_10:
4698         case RTL_GIGA_MAC_VER_11:
4699         case RTL_GIGA_MAC_VER_12:
4700         case RTL_GIGA_MAC_VER_13:
4701         case RTL_GIGA_MAC_VER_14:
4702         case RTL_GIGA_MAC_VER_15:
4703         case RTL_GIGA_MAC_VER_16:
4704         case RTL_GIGA_MAC_VER_17:
4705                 ops->write      = NULL;
4706                 ops->read       = NULL;
4707                 break;
4708
4709         case RTL_GIGA_MAC_VER_37:
4710         case RTL_GIGA_MAC_VER_38:
4711                 ops->write      = r8402_csi_write;
4712                 ops->read       = r8402_csi_read;
4713                 break;
4714
4715         default:
4716                 ops->write      = r8169_csi_write;
4717                 ops->read       = r8169_csi_read;
4718                 break;
4719         }
4720 }
4721
4722 struct ephy_info {
4723         unsigned int offset;
4724         u16 mask;
4725         u16 bits;
4726 };
4727
4728 static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e,
4729                           int len)
4730 {
4731         u16 w;
4732
4733         while (len-- > 0) {
4734                 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
4735                 rtl_ephy_write(tp, e->offset, w);
4736                 e++;
4737         }
4738 }
4739
4740 static void rtl_disable_clock_request(struct pci_dev *pdev)
4741 {
4742         pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL,
4743                                    PCI_EXP_LNKCTL_CLKREQ_EN);
4744 }
4745
4746 static void rtl_enable_clock_request(struct pci_dev *pdev)
4747 {
4748         pcie_capability_set_word(pdev, PCI_EXP_LNKCTL,
4749                                  PCI_EXP_LNKCTL_CLKREQ_EN);
4750 }
4751
4752 #define R8168_CPCMD_QUIRK_MASK (\
4753         EnableBist | \
4754         Mac_dbgo_oe | \
4755         Force_half_dup | \
4756         Force_rxflow_en | \
4757         Force_txflow_en | \
4758         Cxpl_dbg_sel | \
4759         ASF | \
4760         PktCntrDisable | \
4761         Mac_dbgo_sel)
4762
4763 static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
4764 {
4765         void __iomem *ioaddr = tp->mmio_addr;
4766         struct pci_dev *pdev = tp->pci_dev;
4767
4768         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4769
4770         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4771
4772         rtl_tx_performance_tweak(pdev,
4773                 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4774 }
4775
4776 static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
4777 {
4778         void __iomem *ioaddr = tp->mmio_addr;
4779
4780         rtl_hw_start_8168bb(tp);
4781
4782         RTL_W8(MaxTxPacketSize, TxPacketMax);
4783
4784         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
4785 }
4786
4787 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
4788 {
4789         void __iomem *ioaddr = tp->mmio_addr;
4790         struct pci_dev *pdev = tp->pci_dev;
4791
4792         RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
4793
4794         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4795
4796         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4797
4798         rtl_disable_clock_request(pdev);
4799
4800         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4801 }
4802
4803 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
4804 {
4805         static const struct ephy_info e_info_8168cp[] = {
4806                 { 0x01, 0,      0x0001 },
4807                 { 0x02, 0x0800, 0x1000 },
4808                 { 0x03, 0,      0x0042 },
4809                 { 0x06, 0x0080, 0x0000 },
4810                 { 0x07, 0,      0x2000 }
4811         };
4812
4813         rtl_csi_access_enable_2(tp);
4814
4815         rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
4816
4817         __rtl_hw_start_8168cp(tp);
4818 }
4819
4820 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
4821 {
4822         void __iomem *ioaddr = tp->mmio_addr;
4823         struct pci_dev *pdev = tp->pci_dev;
4824
4825         rtl_csi_access_enable_2(tp);
4826
4827         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4828
4829         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4830
4831         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4832 }
4833
4834 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
4835 {
4836         void __iomem *ioaddr = tp->mmio_addr;
4837         struct pci_dev *pdev = tp->pci_dev;
4838
4839         rtl_csi_access_enable_2(tp);
4840
4841         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4842
4843         /* Magic. */
4844         RTL_W8(DBG_REG, 0x20);
4845
4846         RTL_W8(MaxTxPacketSize, TxPacketMax);
4847
4848         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4849
4850         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4851 }
4852
4853 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
4854 {
4855         void __iomem *ioaddr = tp->mmio_addr;
4856         static const struct ephy_info e_info_8168c_1[] = {
4857                 { 0x02, 0x0800, 0x1000 },
4858                 { 0x03, 0,      0x0002 },
4859                 { 0x06, 0x0080, 0x0000 }
4860         };
4861
4862         rtl_csi_access_enable_2(tp);
4863
4864         RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4865
4866         rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
4867
4868         __rtl_hw_start_8168cp(tp);
4869 }
4870
4871 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
4872 {
4873         static const struct ephy_info e_info_8168c_2[] = {
4874                 { 0x01, 0,      0x0001 },
4875                 { 0x03, 0x0400, 0x0220 }
4876         };
4877
4878         rtl_csi_access_enable_2(tp);
4879
4880         rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
4881
4882         __rtl_hw_start_8168cp(tp);
4883 }
4884
4885 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
4886 {
4887         rtl_hw_start_8168c_2(tp);
4888 }
4889
4890 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
4891 {
4892         rtl_csi_access_enable_2(tp);
4893
4894         __rtl_hw_start_8168cp(tp);
4895 }
4896
4897 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
4898 {
4899         void __iomem *ioaddr = tp->mmio_addr;
4900         struct pci_dev *pdev = tp->pci_dev;
4901
4902         rtl_csi_access_enable_2(tp);
4903
4904         rtl_disable_clock_request(pdev);
4905
4906         RTL_W8(MaxTxPacketSize, TxPacketMax);
4907
4908         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4909
4910         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4911 }
4912
4913 static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
4914 {
4915         void __iomem *ioaddr = tp->mmio_addr;
4916         struct pci_dev *pdev = tp->pci_dev;
4917
4918         rtl_csi_access_enable_1(tp);
4919
4920         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4921
4922         RTL_W8(MaxTxPacketSize, TxPacketMax);
4923
4924         rtl_disable_clock_request(pdev);
4925 }
4926
4927 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
4928 {
4929         void __iomem *ioaddr = tp->mmio_addr;
4930         struct pci_dev *pdev = tp->pci_dev;
4931         static const struct ephy_info e_info_8168d_4[] = {
4932                 { 0x0b, ~0,     0x48 },
4933                 { 0x19, 0x20,   0x50 },
4934                 { 0x0c, ~0,     0x20 }
4935         };
4936         int i;
4937
4938         rtl_csi_access_enable_1(tp);
4939
4940         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4941
4942         RTL_W8(MaxTxPacketSize, TxPacketMax);
4943
4944         for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
4945                 const struct ephy_info *e = e_info_8168d_4 + i;
4946                 u16 w;
4947
4948                 w = rtl_ephy_read(tp, e->offset);
4949                 rtl_ephy_write(tp, 0x03, (w & e->mask) | e->bits);
4950         }
4951
4952         rtl_enable_clock_request(pdev);
4953 }
4954
4955 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
4956 {
4957         void __iomem *ioaddr = tp->mmio_addr;
4958         struct pci_dev *pdev = tp->pci_dev;
4959         static const struct ephy_info e_info_8168e_1[] = {
4960                 { 0x00, 0x0200, 0x0100 },
4961                 { 0x00, 0x0000, 0x0004 },
4962                 { 0x06, 0x0002, 0x0001 },
4963                 { 0x06, 0x0000, 0x0030 },
4964                 { 0x07, 0x0000, 0x2000 },
4965                 { 0x00, 0x0000, 0x0020 },
4966                 { 0x03, 0x5800, 0x2000 },
4967                 { 0x03, 0x0000, 0x0001 },
4968                 { 0x01, 0x0800, 0x1000 },
4969                 { 0x07, 0x0000, 0x4000 },
4970                 { 0x1e, 0x0000, 0x2000 },
4971                 { 0x19, 0xffff, 0xfe6c },
4972                 { 0x0a, 0x0000, 0x0040 }
4973         };
4974
4975         rtl_csi_access_enable_2(tp);
4976
4977         rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
4978
4979         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4980
4981         RTL_W8(MaxTxPacketSize, TxPacketMax);
4982
4983         rtl_disable_clock_request(pdev);
4984
4985         /* Reset tx FIFO pointer */
4986         RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
4987         RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
4988
4989         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4990 }
4991
4992 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
4993 {
4994         void __iomem *ioaddr = tp->mmio_addr;
4995         struct pci_dev *pdev = tp->pci_dev;
4996         static const struct ephy_info e_info_8168e_2[] = {
4997                 { 0x09, 0x0000, 0x0080 },
4998                 { 0x19, 0x0000, 0x0224 }
4999         };
5000
5001         rtl_csi_access_enable_1(tp);
5002
5003         rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
5004
5005         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5006
5007         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5008         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5009         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5010         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5011         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5012         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
5013         rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5014         rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5015
5016         RTL_W8(MaxTxPacketSize, EarlySize);
5017
5018         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5019         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5020
5021         /* Adjust EEE LED frequency */
5022         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5023
5024         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5025         RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
5026         RTL_W8(Config5, (RTL_R8(Config5) & ~Spi_en) | ASPM_en);
5027         RTL_W8(Config2, RTL_R8(Config2) | ClkReqEn);
5028 }
5029
5030 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
5031 {
5032         void __iomem *ioaddr = tp->mmio_addr;
5033         struct pci_dev *pdev = tp->pci_dev;
5034
5035         rtl_csi_access_enable_2(tp);
5036
5037         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5038
5039         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5040         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5041         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5042         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5043         rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5044         rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5045         rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5046         rtl_w1w0_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5047         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5048         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
5049
5050         RTL_W8(MaxTxPacketSize, EarlySize);
5051
5052         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5053         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5054         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5055         RTL_W32(MISC, RTL_R32(MISC) | PWM_EN | FORCE_CLK);
5056         RTL_W8(Config5, (RTL_R8(Config5) & ~Spi_en) | ASPM_en);
5057         RTL_W8(Config2, RTL_R8(Config2) | ClkReqEn);
5058 }
5059
5060 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
5061 {
5062         void __iomem *ioaddr = tp->mmio_addr;
5063         static const struct ephy_info e_info_8168f_1[] = {
5064                 { 0x06, 0x00c0, 0x0020 },
5065                 { 0x08, 0x0001, 0x0002 },
5066                 { 0x09, 0x0000, 0x0080 },
5067                 { 0x19, 0x0000, 0x0224 }
5068         };
5069
5070         rtl_hw_start_8168f(tp);
5071
5072         rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5073
5074         rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5075
5076         /* Adjust EEE LED frequency */
5077         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5078 }
5079
5080 static void rtl_hw_start_8411(struct rtl8169_private *tp)
5081 {
5082         static const struct ephy_info e_info_8168f_1[] = {
5083                 { 0x06, 0x00c0, 0x0020 },
5084                 { 0x0f, 0xffff, 0x5200 },
5085                 { 0x1e, 0x0000, 0x4000 },
5086                 { 0x19, 0x0000, 0x0224 }
5087         };
5088
5089         rtl_hw_start_8168f(tp);
5090
5091         rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5092
5093         rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC);
5094 }
5095
5096 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
5097 {
5098         void __iomem *ioaddr = tp->mmio_addr;
5099         struct pci_dev *pdev = tp->pci_dev;
5100
5101         rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC);
5102         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5103         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5104         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5105
5106         rtl_csi_access_enable_1(tp);
5107
5108         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5109
5110         rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5111         rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5112
5113         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5114         RTL_W32(MISC, (RTL_R32(MISC) | FORCE_CLK) & ~RXDV_GATED_EN);
5115         RTL_W8(MaxTxPacketSize, EarlySize);
5116         RTL_W8(Config5, RTL_R8(Config5) | ASPM_en);
5117         RTL_W8(Config2, RTL_R8(Config2) | ClkReqEn);
5118
5119         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5120         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5121
5122         /* Adjust EEE LED frequency */
5123         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5124
5125         rtl_w1w0_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x02, ERIAR_EXGMAC);
5126 }
5127
5128 static void rtl_hw_start_8168(struct net_device *dev)
5129 {
5130         struct rtl8169_private *tp = netdev_priv(dev);
5131         void __iomem *ioaddr = tp->mmio_addr;
5132
5133         RTL_W8(Cfg9346, Cfg9346_Unlock);
5134
5135         RTL_W8(MaxTxPacketSize, TxPacketMax);
5136
5137         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
5138
5139         tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
5140
5141         RTL_W16(CPlusCmd, tp->cp_cmd);
5142
5143         RTL_W16(IntrMitigate, 0x5151);
5144
5145         /* Work around for RxFIFO overflow. */
5146         if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
5147                 tp->event_slow |= RxFIFOOver | PCSTimeout;
5148                 tp->event_slow &= ~RxOverflow;
5149         }
5150
5151         rtl_set_rx_tx_desc_registers(tp, ioaddr);
5152
5153         rtl_set_rx_mode(dev);
5154
5155         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
5156                 (InterFrameGap << TxInterFrameGapShift));
5157
5158         RTL_R8(IntrMask);
5159
5160         switch (tp->mac_version) {
5161         case RTL_GIGA_MAC_VER_11:
5162                 rtl_hw_start_8168bb(tp);
5163                 break;
5164
5165         case RTL_GIGA_MAC_VER_12:
5166         case RTL_GIGA_MAC_VER_17:
5167                 rtl_hw_start_8168bef(tp);
5168                 break;
5169
5170         case RTL_GIGA_MAC_VER_18:
5171                 rtl_hw_start_8168cp_1(tp);
5172                 break;
5173
5174         case RTL_GIGA_MAC_VER_19:
5175                 rtl_hw_start_8168c_1(tp);
5176                 break;
5177
5178         case RTL_GIGA_MAC_VER_20:
5179                 rtl_hw_start_8168c_2(tp);
5180                 break;
5181
5182         case RTL_GIGA_MAC_VER_21:
5183                 rtl_hw_start_8168c_3(tp);
5184                 break;
5185
5186         case RTL_GIGA_MAC_VER_22:
5187                 rtl_hw_start_8168c_4(tp);
5188                 break;
5189
5190         case RTL_GIGA_MAC_VER_23:
5191                 rtl_hw_start_8168cp_2(tp);
5192                 break;
5193
5194         case RTL_GIGA_MAC_VER_24:
5195                 rtl_hw_start_8168cp_3(tp);
5196                 break;
5197
5198         case RTL_GIGA_MAC_VER_25:
5199         case RTL_GIGA_MAC_VER_26:
5200         case RTL_GIGA_MAC_VER_27:
5201                 rtl_hw_start_8168d(tp);
5202                 break;
5203
5204         case RTL_GIGA_MAC_VER_28:
5205                 rtl_hw_start_8168d_4(tp);
5206                 break;
5207
5208         case RTL_GIGA_MAC_VER_31:
5209                 rtl_hw_start_8168dp(tp);
5210                 break;
5211
5212         case RTL_GIGA_MAC_VER_32:
5213         case RTL_GIGA_MAC_VER_33:
5214                 rtl_hw_start_8168e_1(tp);
5215                 break;
5216         case RTL_GIGA_MAC_VER_34:
5217                 rtl_hw_start_8168e_2(tp);
5218                 break;
5219
5220         case RTL_GIGA_MAC_VER_35:
5221         case RTL_GIGA_MAC_VER_36:
5222                 rtl_hw_start_8168f_1(tp);
5223                 break;
5224
5225         case RTL_GIGA_MAC_VER_38:
5226                 rtl_hw_start_8411(tp);
5227                 break;
5228
5229         case RTL_GIGA_MAC_VER_40:
5230         case RTL_GIGA_MAC_VER_41:
5231                 rtl_hw_start_8168g_1(tp);
5232                 break;
5233
5234         default:
5235                 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
5236                         dev->name, tp->mac_version);
5237                 break;
5238         }
5239
5240         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5241
5242         RTL_W8(Cfg9346, Cfg9346_Lock);
5243
5244         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
5245 }
5246
5247 #define R810X_CPCMD_QUIRK_MASK (\
5248         EnableBist | \
5249         Mac_dbgo_oe | \
5250         Force_half_dup | \
5251         Force_rxflow_en | \
5252         Force_txflow_en | \
5253         Cxpl_dbg_sel | \
5254         ASF | \
5255         PktCntrDisable | \
5256         Mac_dbgo_sel)
5257
5258 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
5259 {
5260         void __iomem *ioaddr = tp->mmio_addr;
5261         struct pci_dev *pdev = tp->pci_dev;
5262         static const struct ephy_info e_info_8102e_1[] = {
5263                 { 0x01, 0, 0x6e65 },
5264                 { 0x02, 0, 0x091f },
5265                 { 0x03, 0, 0xc2f9 },
5266                 { 0x06, 0, 0xafb5 },
5267                 { 0x07, 0, 0x0e00 },
5268                 { 0x19, 0, 0xec80 },
5269                 { 0x01, 0, 0x2e65 },
5270                 { 0x01, 0, 0x6e65 }
5271         };
5272         u8 cfg1;
5273
5274         rtl_csi_access_enable_2(tp);
5275
5276         RTL_W8(DBG_REG, FIX_NAK_1);
5277
5278         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5279
5280         RTL_W8(Config1,
5281                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
5282         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5283
5284         cfg1 = RTL_R8(Config1);
5285         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
5286                 RTL_W8(Config1, cfg1 & ~LEDS0);
5287
5288         rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
5289 }
5290
5291 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
5292 {
5293         void __iomem *ioaddr = tp->mmio_addr;
5294         struct pci_dev *pdev = tp->pci_dev;
5295
5296         rtl_csi_access_enable_2(tp);
5297
5298         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5299
5300         RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
5301         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5302 }
5303
5304 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
5305 {
5306         rtl_hw_start_8102e_2(tp);
5307
5308         rtl_ephy_write(tp, 0x03, 0xc2f9);
5309 }
5310
5311 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
5312 {
5313         void __iomem *ioaddr = tp->mmio_addr;
5314         static const struct ephy_info e_info_8105e_1[] = {
5315                 { 0x07, 0, 0x4000 },
5316                 { 0x19, 0, 0x0200 },
5317                 { 0x19, 0, 0x0020 },
5318                 { 0x1e, 0, 0x2000 },
5319                 { 0x03, 0, 0x0001 },
5320                 { 0x19, 0, 0x0100 },
5321                 { 0x19, 0, 0x0004 },
5322                 { 0x0a, 0, 0x0020 }
5323         };
5324
5325         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5326         RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5327
5328         /* Disable Early Tally Counter */
5329         RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
5330
5331         RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
5332         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5333         RTL_W8(Config5, RTL_R8(Config5) | ASPM_en);
5334         RTL_W8(Config2, RTL_R8(Config2) | ClkReqEn);
5335         RTL_W32(MISC, RTL_R32(MISC) | FORCE_CLK);
5336
5337         rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
5338 }
5339
5340 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
5341 {
5342         rtl_hw_start_8105e_1(tp);
5343         rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
5344 }
5345
5346 static void rtl_hw_start_8402(struct rtl8169_private *tp)
5347 {
5348         void __iomem *ioaddr = tp->mmio_addr;
5349         static const struct ephy_info e_info_8402[] = {
5350                 { 0x19, 0xffff, 0xff64 },
5351                 { 0x1e, 0, 0x4000 }
5352         };
5353
5354         rtl_csi_access_enable_2(tp);
5355
5356         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5357         RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5358
5359         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5360         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5361         RTL_W8(Config5, RTL_R8(Config5) | ASPM_en);
5362         RTL_W8(Config2, RTL_R8(Config2) | ClkReqEn);
5363         RTL_W32(MISC, RTL_R32(MISC) | FORCE_CLK);
5364
5365         rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402));
5366
5367         rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
5368
5369         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
5370         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
5371         rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5372         rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5373         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5374         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5375         rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC);
5376 }
5377
5378 static void rtl_hw_start_8106(struct rtl8169_private *tp)
5379 {
5380         void __iomem *ioaddr = tp->mmio_addr;
5381
5382         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5383         RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5384
5385         RTL_W32(MISC,
5386                 (RTL_R32(MISC) | DISABLE_LAN_EN | FORCE_CLK) & ~EARLY_TALLY_EN);
5387         RTL_W8(Config5, RTL_R8(Config5) | ASPM_en);
5388         RTL_W8(Config2, RTL_R8(Config2) | ClkReqEn);
5389         RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
5390         RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
5391 }
5392
5393 static void rtl_hw_start_8101(struct net_device *dev)
5394 {
5395         struct rtl8169_private *tp = netdev_priv(dev);
5396         void __iomem *ioaddr = tp->mmio_addr;
5397         struct pci_dev *pdev = tp->pci_dev;
5398
5399         if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
5400                 tp->event_slow &= ~RxFIFOOver;
5401
5402         if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
5403             tp->mac_version == RTL_GIGA_MAC_VER_16)
5404                 pcie_capability_set_word(pdev, PCI_EXP_DEVCTL,
5405                                          PCI_EXP_DEVCTL_NOSNOOP_EN);
5406
5407         RTL_W8(Cfg9346, Cfg9346_Unlock);
5408
5409         switch (tp->mac_version) {
5410         case RTL_GIGA_MAC_VER_07:
5411                 rtl_hw_start_8102e_1(tp);
5412                 break;
5413
5414         case RTL_GIGA_MAC_VER_08:
5415                 rtl_hw_start_8102e_3(tp);
5416                 break;
5417
5418         case RTL_GIGA_MAC_VER_09:
5419                 rtl_hw_start_8102e_2(tp);
5420                 break;
5421
5422         case RTL_GIGA_MAC_VER_29:
5423                 rtl_hw_start_8105e_1(tp);
5424                 break;
5425         case RTL_GIGA_MAC_VER_30:
5426                 rtl_hw_start_8105e_2(tp);
5427                 break;
5428
5429         case RTL_GIGA_MAC_VER_37:
5430                 rtl_hw_start_8402(tp);
5431                 break;
5432
5433         case RTL_GIGA_MAC_VER_39:
5434                 rtl_hw_start_8106(tp);
5435                 break;
5436         }
5437
5438         RTL_W8(Cfg9346, Cfg9346_Lock);
5439
5440         RTL_W8(MaxTxPacketSize, TxPacketMax);
5441
5442         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
5443
5444         tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
5445         RTL_W16(CPlusCmd, tp->cp_cmd);
5446
5447         RTL_W16(IntrMitigate, 0x0000);
5448
5449         rtl_set_rx_tx_desc_registers(tp, ioaddr);
5450
5451         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5452         rtl_set_rx_tx_config_registers(tp);
5453
5454         RTL_R8(IntrMask);
5455
5456         rtl_set_rx_mode(dev);
5457
5458         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
5459 }
5460
5461 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
5462 {
5463         struct rtl8169_private *tp = netdev_priv(dev);
5464
5465         if (new_mtu < ETH_ZLEN ||
5466             new_mtu > rtl_chip_infos[tp->mac_version].jumbo_max)
5467                 return -EINVAL;
5468
5469         if (new_mtu > ETH_DATA_LEN)
5470                 rtl_hw_jumbo_enable(tp);
5471         else
5472                 rtl_hw_jumbo_disable(tp);
5473
5474         dev->mtu = new_mtu;
5475         netdev_update_features(dev);
5476
5477         return 0;
5478 }
5479
5480 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
5481 {
5482         desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
5483         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
5484 }
5485
5486 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
5487                                      void **data_buff, struct RxDesc *desc)
5488 {
5489         dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
5490                          DMA_FROM_DEVICE);
5491
5492         kfree(*data_buff);
5493         *data_buff = NULL;
5494         rtl8169_make_unusable_by_asic(desc);
5495 }
5496
5497 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
5498 {
5499         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
5500
5501         desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
5502 }
5503
5504 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
5505                                        u32 rx_buf_sz)
5506 {
5507         desc->addr = cpu_to_le64(mapping);
5508         wmb();
5509         rtl8169_mark_to_asic(desc, rx_buf_sz);
5510 }
5511
5512 static inline void *rtl8169_align(void *data)
5513 {
5514         return (void *)ALIGN((long)data, 16);
5515 }
5516
5517 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
5518                                              struct RxDesc *desc)
5519 {
5520         void *data;
5521         dma_addr_t mapping;
5522         struct device *d = &tp->pci_dev->dev;
5523         struct net_device *dev = tp->dev;
5524         int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
5525
5526         data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
5527         if (!data)
5528                 return NULL;
5529
5530         if (rtl8169_align(data) != data) {
5531                 kfree(data);
5532                 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
5533                 if (!data)
5534                         return NULL;
5535         }
5536
5537         mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
5538                                  DMA_FROM_DEVICE);
5539         if (unlikely(dma_mapping_error(d, mapping))) {
5540                 if (net_ratelimit())
5541                         netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
5542                 goto err_out;
5543         }
5544
5545         rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
5546         return data;
5547
5548 err_out:
5549         kfree(data);
5550         return NULL;
5551 }
5552
5553 static void rtl8169_rx_clear(struct rtl8169_private *tp)
5554 {
5555         unsigned int i;
5556
5557         for (i = 0; i < NUM_RX_DESC; i++) {
5558                 if (tp->Rx_databuff[i]) {
5559                         rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
5560                                             tp->RxDescArray + i);
5561                 }
5562         }
5563 }
5564
5565 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
5566 {
5567         desc->opts1 |= cpu_to_le32(RingEnd);
5568 }
5569
5570 static int rtl8169_rx_fill(struct rtl8169_private *tp)
5571 {
5572         unsigned int i;
5573
5574         for (i = 0; i < NUM_RX_DESC; i++) {
5575                 void *data;
5576
5577                 if (tp->Rx_databuff[i])
5578                         continue;
5579
5580                 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
5581                 if (!data) {
5582                         rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
5583                         goto err_out;
5584                 }
5585                 tp->Rx_databuff[i] = data;
5586         }
5587
5588         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
5589         return 0;
5590
5591 err_out:
5592         rtl8169_rx_clear(tp);
5593         return -ENOMEM;
5594 }
5595
5596 static int rtl8169_init_ring(struct net_device *dev)
5597 {
5598         struct rtl8169_private *tp = netdev_priv(dev);
5599
5600         rtl8169_init_ring_indexes(tp);
5601
5602         memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
5603         memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
5604
5605         return rtl8169_rx_fill(tp);
5606 }
5607
5608 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
5609                                  struct TxDesc *desc)
5610 {
5611         unsigned int len = tx_skb->len;
5612
5613         dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
5614
5615         desc->opts1 = 0x00;
5616         desc->opts2 = 0x00;
5617         desc->addr = 0x00;
5618         tx_skb->len = 0;
5619 }
5620
5621 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
5622                                    unsigned int n)
5623 {
5624         unsigned int i;
5625
5626         for (i = 0; i < n; i++) {
5627                 unsigned int entry = (start + i) % NUM_TX_DESC;
5628                 struct ring_info *tx_skb = tp->tx_skb + entry;
5629                 unsigned int len = tx_skb->len;
5630
5631                 if (len) {
5632                         struct sk_buff *skb = tx_skb->skb;
5633
5634                         rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
5635                                              tp->TxDescArray + entry);
5636                         if (skb) {
5637                                 tp->dev->stats.tx_dropped++;
5638                                 dev_kfree_skb(skb);
5639                                 tx_skb->skb = NULL;
5640                         }
5641                 }
5642         }
5643 }
5644
5645 static void rtl8169_tx_clear(struct rtl8169_private *tp)
5646 {
5647         rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
5648         tp->cur_tx = tp->dirty_tx = 0;
5649 }
5650
5651 static void rtl_reset_work(struct rtl8169_private *tp)
5652 {
5653         struct net_device *dev = tp->dev;
5654         int i;
5655
5656         napi_disable(&tp->napi);
5657         netif_stop_queue(dev);
5658         synchronize_sched();
5659
5660         rtl8169_hw_reset(tp);
5661
5662         for (i = 0; i < NUM_RX_DESC; i++)
5663                 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
5664
5665         rtl8169_tx_clear(tp);
5666         rtl8169_init_ring_indexes(tp);
5667
5668         napi_enable(&tp->napi);
5669         rtl_hw_start(dev);
5670         netif_wake_queue(dev);
5671         rtl8169_check_link_status(dev, tp, tp->mmio_addr);
5672 }
5673
5674 static void rtl8169_tx_timeout(struct net_device *dev)
5675 {
5676         struct rtl8169_private *tp = netdev_priv(dev);
5677
5678         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5679 }
5680
5681 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
5682                               u32 *opts)
5683 {
5684         struct skb_shared_info *info = skb_shinfo(skb);
5685         unsigned int cur_frag, entry;
5686         struct TxDesc * uninitialized_var(txd);
5687         struct device *d = &tp->pci_dev->dev;
5688
5689         entry = tp->cur_tx;
5690         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
5691                 const skb_frag_t *frag = info->frags + cur_frag;
5692                 dma_addr_t mapping;
5693                 u32 status, len;
5694                 void *addr;
5695
5696                 entry = (entry + 1) % NUM_TX_DESC;
5697
5698                 txd = tp->TxDescArray + entry;
5699                 len = skb_frag_size(frag);
5700                 addr = skb_frag_address(frag);
5701                 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
5702                 if (unlikely(dma_mapping_error(d, mapping))) {
5703                         if (net_ratelimit())
5704                                 netif_err(tp, drv, tp->dev,
5705                                           "Failed to map TX fragments DMA!\n");
5706                         goto err_out;
5707                 }
5708
5709                 /* Anti gcc 2.95.3 bugware (sic) */
5710                 status = opts[0] | len |
5711                         (RingEnd * !((entry + 1) % NUM_TX_DESC));
5712
5713                 txd->opts1 = cpu_to_le32(status);
5714                 txd->opts2 = cpu_to_le32(opts[1]);
5715                 txd->addr = cpu_to_le64(mapping);
5716
5717                 tp->tx_skb[entry].len = len;
5718         }
5719
5720         if (cur_frag) {
5721                 tp->tx_skb[entry].skb = skb;
5722                 txd->opts1 |= cpu_to_le32(LastFrag);
5723         }
5724
5725         return cur_frag;
5726
5727 err_out:
5728         rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5729         return -EIO;
5730 }
5731
5732 static inline void rtl8169_tso_csum(struct rtl8169_private *tp,
5733                                     struct sk_buff *skb, u32 *opts)
5734 {
5735         const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version;
5736         u32 mss = skb_shinfo(skb)->gso_size;
5737         int offset = info->opts_offset;
5738
5739         if (mss) {
5740                 opts[0] |= TD_LSO;
5741                 opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift;
5742         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5743                 const struct iphdr *ip = ip_hdr(skb);
5744
5745                 if (ip->protocol == IPPROTO_TCP)
5746                         opts[offset] |= info->checksum.tcp;
5747                 else if (ip->protocol == IPPROTO_UDP)
5748                         opts[offset] |= info->checksum.udp;
5749                 else
5750                         WARN_ON_ONCE(1);
5751         }
5752 }
5753
5754 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5755                                       struct net_device *dev)
5756 {
5757         struct rtl8169_private *tp = netdev_priv(dev);
5758         unsigned int entry = tp->cur_tx % NUM_TX_DESC;
5759         struct TxDesc *txd = tp->TxDescArray + entry;
5760         void __iomem *ioaddr = tp->mmio_addr;
5761         struct device *d = &tp->pci_dev->dev;
5762         dma_addr_t mapping;
5763         u32 status, len;
5764         u32 opts[2];
5765         int frags;
5766
5767         if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
5768                 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
5769                 goto err_stop_0;
5770         }
5771
5772         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
5773                 goto err_stop_0;
5774
5775         len = skb_headlen(skb);
5776         mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
5777         if (unlikely(dma_mapping_error(d, mapping))) {
5778                 if (net_ratelimit())
5779                         netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
5780                 goto err_dma_0;
5781         }
5782
5783         tp->tx_skb[entry].len = len;
5784         txd->addr = cpu_to_le64(mapping);
5785
5786         opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb));
5787         opts[0] = DescOwn;
5788
5789         rtl8169_tso_csum(tp, skb, opts);
5790
5791         frags = rtl8169_xmit_frags(tp, skb, opts);
5792         if (frags < 0)
5793                 goto err_dma_1;
5794         else if (frags)
5795                 opts[0] |= FirstFrag;
5796         else {
5797                 opts[0] |= FirstFrag | LastFrag;
5798                 tp->tx_skb[entry].skb = skb;
5799         }
5800
5801         txd->opts2 = cpu_to_le32(opts[1]);
5802
5803         skb_tx_timestamp(skb);
5804
5805         wmb();
5806
5807         /* Anti gcc 2.95.3 bugware (sic) */
5808         status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
5809         txd->opts1 = cpu_to_le32(status);
5810
5811         tp->cur_tx += frags + 1;
5812
5813         wmb();
5814
5815         RTL_W8(TxPoll, NPQ);
5816
5817         mmiowb();
5818
5819         if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
5820                 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
5821                  * not miss a ring update when it notices a stopped queue.
5822                  */
5823                 smp_wmb();
5824                 netif_stop_queue(dev);
5825                 /* Sync with rtl_tx:
5826                  * - publish queue status and cur_tx ring index (write barrier)
5827                  * - refresh dirty_tx ring index (read barrier).
5828                  * May the current thread have a pessimistic view of the ring
5829                  * status and forget to wake up queue, a racing rtl_tx thread
5830                  * can't.
5831                  */
5832                 smp_mb();
5833                 if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
5834                         netif_wake_queue(dev);
5835         }
5836
5837         return NETDEV_TX_OK;
5838
5839 err_dma_1:
5840         rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
5841 err_dma_0:
5842         dev_kfree_skb(skb);
5843         dev->stats.tx_dropped++;
5844         return NETDEV_TX_OK;
5845
5846 err_stop_0:
5847         netif_stop_queue(dev);
5848         dev->stats.tx_dropped++;
5849         return NETDEV_TX_BUSY;
5850 }
5851
5852 static void rtl8169_pcierr_interrupt(struct net_device *dev)
5853 {
5854         struct rtl8169_private *tp = netdev_priv(dev);
5855         struct pci_dev *pdev = tp->pci_dev;
5856         u16 pci_status, pci_cmd;
5857
5858         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
5859         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
5860
5861         netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
5862                   pci_cmd, pci_status);
5863
5864         /*
5865          * The recovery sequence below admits a very elaborated explanation:
5866          * - it seems to work;
5867          * - I did not see what else could be done;
5868          * - it makes iop3xx happy.
5869          *
5870          * Feel free to adjust to your needs.
5871          */
5872         if (pdev->broken_parity_status)
5873                 pci_cmd &= ~PCI_COMMAND_PARITY;
5874         else
5875                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
5876
5877         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
5878
5879         pci_write_config_word(pdev, PCI_STATUS,
5880                 pci_status & (PCI_STATUS_DETECTED_PARITY |
5881                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
5882                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
5883
5884         /* The infamous DAC f*ckup only happens at boot time */
5885         if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
5886                 void __iomem *ioaddr = tp->mmio_addr;
5887
5888                 netif_info(tp, intr, dev, "disabling PCI DAC\n");
5889                 tp->cp_cmd &= ~PCIDAC;
5890                 RTL_W16(CPlusCmd, tp->cp_cmd);
5891                 dev->features &= ~NETIF_F_HIGHDMA;
5892         }
5893
5894         rtl8169_hw_reset(tp);
5895
5896         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5897 }
5898
5899 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
5900 {
5901         unsigned int dirty_tx, tx_left;
5902
5903         dirty_tx = tp->dirty_tx;
5904         smp_rmb();
5905         tx_left = tp->cur_tx - dirty_tx;
5906
5907         while (tx_left > 0) {
5908                 unsigned int entry = dirty_tx % NUM_TX_DESC;
5909                 struct ring_info *tx_skb = tp->tx_skb + entry;
5910                 u32 status;
5911
5912                 rmb();
5913                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
5914                 if (status & DescOwn)
5915                         break;
5916
5917                 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
5918                                      tp->TxDescArray + entry);
5919                 if (status & LastFrag) {
5920                         u64_stats_update_begin(&tp->tx_stats.syncp);
5921                         tp->tx_stats.packets++;
5922                         tp->tx_stats.bytes += tx_skb->skb->len;
5923                         u64_stats_update_end(&tp->tx_stats.syncp);
5924                         dev_kfree_skb(tx_skb->skb);
5925                         tx_skb->skb = NULL;
5926                 }
5927                 dirty_tx++;
5928                 tx_left--;
5929         }
5930
5931         if (tp->dirty_tx != dirty_tx) {
5932                 tp->dirty_tx = dirty_tx;
5933                 /* Sync with rtl8169_start_xmit:
5934                  * - publish dirty_tx ring index (write barrier)
5935                  * - refresh cur_tx ring index and queue status (read barrier)
5936                  * May the current thread miss the stopped queue condition,
5937                  * a racing xmit thread can only have a right view of the
5938                  * ring status.
5939                  */
5940                 smp_mb();
5941                 if (netif_queue_stopped(dev) &&
5942                     TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
5943                         netif_wake_queue(dev);
5944                 }
5945                 /*
5946                  * 8168 hack: TxPoll requests are lost when the Tx packets are
5947                  * too close. Let's kick an extra TxPoll request when a burst
5948                  * of start_xmit activity is detected (if it is not detected,
5949                  * it is slow enough). -- FR
5950                  */
5951                 if (tp->cur_tx != dirty_tx) {
5952                         void __iomem *ioaddr = tp->mmio_addr;
5953
5954                         RTL_W8(TxPoll, NPQ);
5955                 }
5956         }
5957 }
5958
5959 static inline int rtl8169_fragmented_frame(u32 status)
5960 {
5961         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
5962 }
5963
5964 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
5965 {
5966         u32 status = opts1 & RxProtoMask;
5967
5968         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
5969             ((status == RxProtoUDP) && !(opts1 & UDPFail)))
5970                 skb->ip_summed = CHECKSUM_UNNECESSARY;
5971         else
5972                 skb_checksum_none_assert(skb);
5973 }
5974
5975 static struct sk_buff *rtl8169_try_rx_copy(void *data,
5976                                            struct rtl8169_private *tp,
5977                                            int pkt_size,
5978                                            dma_addr_t addr)
5979 {
5980         struct sk_buff *skb;
5981         struct device *d = &tp->pci_dev->dev;
5982
5983         data = rtl8169_align(data);
5984         dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
5985         prefetch(data);
5986         skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
5987         if (skb)
5988                 memcpy(skb->data, data, pkt_size);
5989         dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
5990
5991         return skb;
5992 }
5993
5994 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
5995 {
5996         unsigned int cur_rx, rx_left;
5997         unsigned int count;
5998
5999         cur_rx = tp->cur_rx;
6000         rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
6001         rx_left = min(rx_left, budget);
6002
6003         for (; rx_left > 0; rx_left--, cur_rx++) {
6004                 unsigned int entry = cur_rx % NUM_RX_DESC;
6005                 struct RxDesc *desc = tp->RxDescArray + entry;
6006                 u32 status;
6007
6008                 rmb();
6009                 status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
6010
6011                 if (status & DescOwn)
6012                         break;
6013                 if (unlikely(status & RxRES)) {
6014                         netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
6015                                    status);
6016                         dev->stats.rx_errors++;
6017                         if (status & (RxRWT | RxRUNT))
6018                                 dev->stats.rx_length_errors++;
6019                         if (status & RxCRC)
6020                                 dev->stats.rx_crc_errors++;
6021                         if (status & RxFOVF) {
6022                                 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6023                                 dev->stats.rx_fifo_errors++;
6024                         }
6025                         if ((status & (RxRUNT | RxCRC)) &&
6026                             !(status & (RxRWT | RxFOVF)) &&
6027                             (dev->features & NETIF_F_RXALL))
6028                                 goto process_pkt;
6029                 } else {
6030                         struct sk_buff *skb;
6031                         dma_addr_t addr;
6032                         int pkt_size;
6033
6034 process_pkt:
6035                         addr = le64_to_cpu(desc->addr);
6036                         if (likely(!(dev->features & NETIF_F_RXFCS)))
6037                                 pkt_size = (status & 0x00003fff) - 4;
6038                         else
6039                                 pkt_size = status & 0x00003fff;
6040
6041                         /*
6042                          * The driver does not support incoming fragmented
6043                          * frames. They are seen as a symptom of over-mtu
6044                          * sized frames.
6045                          */
6046                         if (unlikely(rtl8169_fragmented_frame(status))) {
6047                                 dev->stats.rx_dropped++;
6048                                 dev->stats.rx_length_errors++;
6049                                 goto release_descriptor;
6050                         }
6051
6052                         skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
6053                                                   tp, pkt_size, addr);
6054                         if (!skb) {
6055                                 dev->stats.rx_dropped++;
6056                                 goto release_descriptor;
6057                         }
6058
6059                         rtl8169_rx_csum(skb, status);
6060                         skb_put(skb, pkt_size);
6061                         skb->protocol = eth_type_trans(skb, dev);
6062
6063                         rtl8169_rx_vlan_tag(desc, skb);
6064
6065                         napi_gro_receive(&tp->napi, skb);
6066
6067                         u64_stats_update_begin(&tp->rx_stats.syncp);
6068                         tp->rx_stats.packets++;
6069                         tp->rx_stats.bytes += pkt_size;
6070                         u64_stats_update_end(&tp->rx_stats.syncp);
6071                 }
6072 release_descriptor:
6073                 desc->opts2 = 0;
6074                 wmb();
6075                 rtl8169_mark_to_asic(desc, rx_buf_sz);
6076         }
6077
6078         count = cur_rx - tp->cur_rx;
6079         tp->cur_rx = cur_rx;
6080
6081         tp->dirty_rx += count;
6082
6083         return count;
6084 }
6085
6086 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
6087 {
6088         struct net_device *dev = dev_instance;
6089         struct rtl8169_private *tp = netdev_priv(dev);
6090         int handled = 0;
6091         u16 status;
6092
6093         status = rtl_get_events(tp);
6094         if (status && status != 0xffff) {
6095                 status &= RTL_EVENT_NAPI | tp->event_slow;
6096                 if (status) {
6097                         handled = 1;
6098
6099                         rtl_irq_disable(tp);
6100                         napi_schedule(&tp->napi);
6101                 }
6102         }
6103         return IRQ_RETVAL(handled);
6104 }
6105
6106 /*
6107  * Workqueue context.
6108  */
6109 static void rtl_slow_event_work(struct rtl8169_private *tp)
6110 {
6111         struct net_device *dev = tp->dev;
6112         u16 status;
6113
6114         status = rtl_get_events(tp) & tp->event_slow;
6115         rtl_ack_events(tp, status);
6116
6117         if (unlikely(status & RxFIFOOver)) {
6118                 switch (tp->mac_version) {
6119                 /* Work around for rx fifo overflow */
6120                 case RTL_GIGA_MAC_VER_11:
6121                         netif_stop_queue(dev);
6122                         /* XXX - Hack alert. See rtl_task(). */
6123                         set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
6124                 default:
6125                         break;
6126                 }
6127         }
6128
6129         if (unlikely(status & SYSErr))
6130                 rtl8169_pcierr_interrupt(dev);
6131
6132         if (status & LinkChg)
6133                 __rtl8169_check_link_status(dev, tp, tp->mmio_addr, true);
6134
6135         rtl_irq_enable_all(tp);
6136 }
6137
6138 static void rtl_task(struct work_struct *work)
6139 {
6140         static const struct {
6141                 int bitnr;
6142                 void (*action)(struct rtl8169_private *);
6143         } rtl_work[] = {
6144                 /* XXX - keep rtl_slow_event_work() as first element. */
6145                 { RTL_FLAG_TASK_SLOW_PENDING,   rtl_slow_event_work },
6146                 { RTL_FLAG_TASK_RESET_PENDING,  rtl_reset_work },
6147                 { RTL_FLAG_TASK_PHY_PENDING,    rtl_phy_work }
6148         };
6149         struct rtl8169_private *tp =
6150                 container_of(work, struct rtl8169_private, wk.work);
6151         struct net_device *dev = tp->dev;
6152         int i;
6153
6154         rtl_lock_work(tp);
6155
6156         if (!netif_running(dev) ||
6157             !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
6158                 goto out_unlock;
6159
6160         for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
6161                 bool pending;
6162
6163                 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
6164                 if (pending)
6165                         rtl_work[i].action(tp);
6166         }
6167
6168 out_unlock:
6169         rtl_unlock_work(tp);
6170 }
6171
6172 static int rtl8169_poll(struct napi_struct *napi, int budget)
6173 {
6174         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
6175         struct net_device *dev = tp->dev;
6176         u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
6177         int work_done= 0;
6178         u16 status;
6179
6180         status = rtl_get_events(tp);
6181         rtl_ack_events(tp, status & ~tp->event_slow);
6182
6183         if (status & RTL_EVENT_NAPI_RX)
6184                 work_done = rtl_rx(dev, tp, (u32) budget);
6185
6186         if (status & RTL_EVENT_NAPI_TX)
6187                 rtl_tx(dev, tp);
6188
6189         if (status & tp->event_slow) {
6190                 enable_mask &= ~tp->event_slow;
6191
6192                 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
6193         }
6194
6195         if (work_done < budget) {
6196                 napi_complete(napi);
6197
6198                 rtl_irq_enable(tp, enable_mask);
6199                 mmiowb();
6200         }
6201
6202         return work_done;
6203 }
6204
6205 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
6206 {
6207         struct rtl8169_private *tp = netdev_priv(dev);
6208
6209         if (tp->mac_version > RTL_GIGA_MAC_VER_06)
6210                 return;
6211
6212         dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
6213         RTL_W32(RxMissed, 0);
6214 }
6215
6216 static void rtl8169_down(struct net_device *dev)
6217 {
6218         struct rtl8169_private *tp = netdev_priv(dev);
6219         void __iomem *ioaddr = tp->mmio_addr;
6220
6221         del_timer_sync(&tp->timer);
6222
6223         napi_disable(&tp->napi);
6224         netif_stop_queue(dev);
6225
6226         rtl8169_hw_reset(tp);
6227         /*
6228          * At this point device interrupts can not be enabled in any function,
6229          * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
6230          * and napi is disabled (rtl8169_poll).
6231          */
6232         rtl8169_rx_missed(dev, ioaddr);
6233
6234         /* Give a racing hard_start_xmit a few cycles to complete. */
6235         synchronize_sched();
6236
6237         rtl8169_tx_clear(tp);
6238
6239         rtl8169_rx_clear(tp);
6240
6241         rtl_pll_power_down(tp);
6242 }
6243
6244 static int rtl8169_close(struct net_device *dev)
6245 {
6246         struct rtl8169_private *tp = netdev_priv(dev);
6247         struct pci_dev *pdev = tp->pci_dev;
6248
6249         pm_runtime_get_sync(&pdev->dev);
6250
6251         /* Update counters before going down */
6252         rtl8169_update_counters(dev);
6253
6254         rtl_lock_work(tp);
6255         clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6256
6257         rtl8169_down(dev);
6258         rtl_unlock_work(tp);
6259
6260         free_irq(pdev->irq, dev);
6261
6262         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6263                           tp->RxPhyAddr);
6264         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6265                           tp->TxPhyAddr);
6266         tp->TxDescArray = NULL;
6267         tp->RxDescArray = NULL;
6268
6269         pm_runtime_put_sync(&pdev->dev);
6270
6271         return 0;
6272 }
6273
6274 #ifdef CONFIG_NET_POLL_CONTROLLER
6275 static void rtl8169_netpoll(struct net_device *dev)
6276 {
6277         struct rtl8169_private *tp = netdev_priv(dev);
6278
6279         rtl8169_interrupt(tp->pci_dev->irq, dev);
6280 }
6281 #endif
6282
6283 static int rtl_open(struct net_device *dev)
6284 {
6285         struct rtl8169_private *tp = netdev_priv(dev);
6286         void __iomem *ioaddr = tp->mmio_addr;
6287         struct pci_dev *pdev = tp->pci_dev;
6288         int retval = -ENOMEM;
6289
6290         pm_runtime_get_sync(&pdev->dev);
6291
6292         /*
6293          * Rx and Tx descriptors needs 256 bytes alignment.
6294          * dma_alloc_coherent provides more.
6295          */
6296         tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
6297                                              &tp->TxPhyAddr, GFP_KERNEL);
6298         if (!tp->TxDescArray)
6299                 goto err_pm_runtime_put;
6300
6301         tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
6302                                              &tp->RxPhyAddr, GFP_KERNEL);
6303         if (!tp->RxDescArray)
6304                 goto err_free_tx_0;
6305
6306         retval = rtl8169_init_ring(dev);
6307         if (retval < 0)
6308                 goto err_free_rx_1;
6309
6310         INIT_WORK(&tp->wk.work, rtl_task);
6311
6312         smp_mb();
6313
6314         rtl_request_firmware(tp);
6315
6316         retval = request_irq(pdev->irq, rtl8169_interrupt,
6317                              (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
6318                              dev->name, dev);
6319         if (retval < 0)
6320                 goto err_release_fw_2;
6321
6322         rtl_lock_work(tp);
6323
6324         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6325
6326         napi_enable(&tp->napi);
6327
6328         rtl8169_init_phy(dev, tp);
6329
6330         __rtl8169_set_features(dev, dev->features);
6331
6332         rtl_pll_power_up(tp);
6333
6334         rtl_hw_start(dev);
6335
6336         netif_start_queue(dev);
6337
6338         rtl_unlock_work(tp);
6339
6340         tp->saved_wolopts = 0;
6341         pm_runtime_put_noidle(&pdev->dev);
6342
6343         rtl8169_check_link_status(dev, tp, ioaddr);
6344 out:
6345         return retval;
6346
6347 err_release_fw_2:
6348         rtl_release_firmware(tp);
6349         rtl8169_rx_clear(tp);
6350 err_free_rx_1:
6351         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6352                           tp->RxPhyAddr);
6353         tp->RxDescArray = NULL;
6354 err_free_tx_0:
6355         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6356                           tp->TxPhyAddr);
6357         tp->TxDescArray = NULL;
6358 err_pm_runtime_put:
6359         pm_runtime_put_noidle(&pdev->dev);
6360         goto out;
6361 }
6362
6363 static struct rtnl_link_stats64 *
6364 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
6365 {
6366         struct rtl8169_private *tp = netdev_priv(dev);
6367         void __iomem *ioaddr = tp->mmio_addr;
6368         unsigned int start;
6369
6370         if (netif_running(dev))
6371                 rtl8169_rx_missed(dev, ioaddr);
6372
6373         do {
6374                 start = u64_stats_fetch_begin_bh(&tp->rx_stats.syncp);
6375                 stats->rx_packets = tp->rx_stats.packets;
6376                 stats->rx_bytes = tp->rx_stats.bytes;
6377         } while (u64_stats_fetch_retry_bh(&tp->rx_stats.syncp, start));
6378
6379
6380         do {
6381                 start = u64_stats_fetch_begin_bh(&tp->tx_stats.syncp);
6382                 stats->tx_packets = tp->tx_stats.packets;
6383                 stats->tx_bytes = tp->tx_stats.bytes;
6384         } while (u64_stats_fetch_retry_bh(&tp->tx_stats.syncp, start));
6385
6386         stats->rx_dropped       = dev->stats.rx_dropped;
6387         stats->tx_dropped       = dev->stats.tx_dropped;
6388         stats->rx_length_errors = dev->stats.rx_length_errors;
6389         stats->rx_errors        = dev->stats.rx_errors;
6390         stats->rx_crc_errors    = dev->stats.rx_crc_errors;
6391         stats->rx_fifo_errors   = dev->stats.rx_fifo_errors;
6392         stats->rx_missed_errors = dev->stats.rx_missed_errors;
6393
6394         return stats;
6395 }
6396
6397 static void rtl8169_net_suspend(struct net_device *dev)
6398 {
6399         struct rtl8169_private *tp = netdev_priv(dev);
6400
6401         if (!netif_running(dev))
6402                 return;
6403
6404         netif_device_detach(dev);
6405         netif_stop_queue(dev);
6406
6407         rtl_lock_work(tp);
6408         napi_disable(&tp->napi);
6409         clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6410         rtl_unlock_work(tp);
6411
6412         rtl_pll_power_down(tp);
6413 }
6414
6415 #ifdef CONFIG_PM
6416
6417 static int rtl8169_suspend(struct device *device)
6418 {
6419         struct pci_dev *pdev = to_pci_dev(device);
6420         struct net_device *dev = pci_get_drvdata(pdev);
6421
6422         rtl8169_net_suspend(dev);
6423
6424         return 0;
6425 }
6426
6427 static void __rtl8169_resume(struct net_device *dev)
6428 {
6429         struct rtl8169_private *tp = netdev_priv(dev);
6430
6431         netif_device_attach(dev);
6432
6433         rtl_pll_power_up(tp);
6434
6435         rtl_lock_work(tp);
6436         napi_enable(&tp->napi);
6437         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6438         rtl_unlock_work(tp);
6439
6440         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6441 }
6442
6443 static int rtl8169_resume(struct device *device)
6444 {
6445         struct pci_dev *pdev = to_pci_dev(device);
6446         struct net_device *dev = pci_get_drvdata(pdev);
6447         struct rtl8169_private *tp = netdev_priv(dev);
6448
6449         rtl8169_init_phy(dev, tp);
6450
6451         if (netif_running(dev))
6452                 __rtl8169_resume(dev);
6453
6454         return 0;
6455 }
6456
6457 static int rtl8169_runtime_suspend(struct device *device)
6458 {
6459         struct pci_dev *pdev = to_pci_dev(device);
6460         struct net_device *dev = pci_get_drvdata(pdev);
6461         struct rtl8169_private *tp = netdev_priv(dev);
6462
6463         if (!tp->TxDescArray)
6464                 return 0;
6465
6466         rtl_lock_work(tp);
6467         tp->saved_wolopts = __rtl8169_get_wol(tp);
6468         __rtl8169_set_wol(tp, WAKE_ANY);
6469         rtl_unlock_work(tp);
6470
6471         rtl8169_net_suspend(dev);
6472
6473         return 0;
6474 }
6475
6476 static int rtl8169_runtime_resume(struct device *device)
6477 {
6478         struct pci_dev *pdev = to_pci_dev(device);
6479         struct net_device *dev = pci_get_drvdata(pdev);
6480         struct rtl8169_private *tp = netdev_priv(dev);
6481
6482         if (!tp->TxDescArray)
6483                 return 0;
6484
6485         rtl_lock_work(tp);
6486         __rtl8169_set_wol(tp, tp->saved_wolopts);
6487         tp->saved_wolopts = 0;
6488         rtl_unlock_work(tp);
6489
6490         rtl8169_init_phy(dev, tp);
6491
6492         __rtl8169_resume(dev);
6493
6494         return 0;
6495 }
6496
6497 static int rtl8169_runtime_idle(struct device *device)
6498 {
6499         struct pci_dev *pdev = to_pci_dev(device);
6500         struct net_device *dev = pci_get_drvdata(pdev);
6501         struct rtl8169_private *tp = netdev_priv(dev);
6502
6503         return tp->TxDescArray ? -EBUSY : 0;
6504 }
6505
6506 static const struct dev_pm_ops rtl8169_pm_ops = {
6507         .suspend                = rtl8169_suspend,
6508         .resume                 = rtl8169_resume,
6509         .freeze                 = rtl8169_suspend,
6510         .thaw                   = rtl8169_resume,
6511         .poweroff               = rtl8169_suspend,
6512         .restore                = rtl8169_resume,
6513         .runtime_suspend        = rtl8169_runtime_suspend,
6514         .runtime_resume         = rtl8169_runtime_resume,
6515         .runtime_idle           = rtl8169_runtime_idle,
6516 };
6517
6518 #define RTL8169_PM_OPS  (&rtl8169_pm_ops)
6519
6520 #else /* !CONFIG_PM */
6521
6522 #define RTL8169_PM_OPS  NULL
6523
6524 #endif /* !CONFIG_PM */
6525
6526 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
6527 {
6528         void __iomem *ioaddr = tp->mmio_addr;
6529
6530         /* WoL fails with 8168b when the receiver is disabled. */
6531         switch (tp->mac_version) {
6532         case RTL_GIGA_MAC_VER_11:
6533         case RTL_GIGA_MAC_VER_12:
6534         case RTL_GIGA_MAC_VER_17:
6535                 pci_clear_master(tp->pci_dev);
6536
6537                 RTL_W8(ChipCmd, CmdRxEnb);
6538                 /* PCI commit */
6539                 RTL_R8(ChipCmd);
6540                 break;
6541         default:
6542                 break;
6543         }
6544 }
6545
6546 static void rtl_shutdown(struct pci_dev *pdev)
6547 {
6548         struct net_device *dev = pci_get_drvdata(pdev);
6549         struct rtl8169_private *tp = netdev_priv(dev);
6550         struct device *d = &pdev->dev;
6551
6552         pm_runtime_get_sync(d);
6553
6554         rtl8169_net_suspend(dev);
6555
6556         /* Restore original MAC address */
6557         rtl_rar_set(tp, dev->perm_addr);
6558
6559         rtl8169_hw_reset(tp);
6560
6561         if (system_state == SYSTEM_POWER_OFF) {
6562                 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
6563                         rtl_wol_suspend_quirk(tp);
6564                         rtl_wol_shutdown_quirk(tp);
6565                 }
6566
6567                 pci_wake_from_d3(pdev, true);
6568                 pci_set_power_state(pdev, PCI_D3hot);
6569         }
6570
6571         pm_runtime_put_noidle(d);
6572 }
6573
6574 static void rtl_remove_one(struct pci_dev *pdev)
6575 {
6576         struct net_device *dev = pci_get_drvdata(pdev);
6577         struct rtl8169_private *tp = netdev_priv(dev);
6578
6579         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
6580             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
6581             tp->mac_version == RTL_GIGA_MAC_VER_31) {
6582                 rtl8168_driver_stop(tp);
6583         }
6584
6585         cancel_work_sync(&tp->wk.work);
6586
6587         netif_napi_del(&tp->napi);
6588
6589         unregister_netdev(dev);
6590
6591         rtl_release_firmware(tp);
6592
6593         if (pci_dev_run_wake(pdev))
6594                 pm_runtime_get_noresume(&pdev->dev);
6595
6596         /* restore original MAC address */
6597         rtl_rar_set(tp, dev->perm_addr);
6598
6599         rtl_disable_msi(pdev, tp);
6600         rtl8169_release_board(pdev, dev, tp->mmio_addr);
6601         pci_set_drvdata(pdev, NULL);
6602 }
6603
6604 static const struct net_device_ops rtl_netdev_ops = {
6605         .ndo_open               = rtl_open,
6606         .ndo_stop               = rtl8169_close,
6607         .ndo_get_stats64        = rtl8169_get_stats64,
6608         .ndo_start_xmit         = rtl8169_start_xmit,
6609         .ndo_tx_timeout         = rtl8169_tx_timeout,
6610         .ndo_validate_addr      = eth_validate_addr,
6611         .ndo_change_mtu         = rtl8169_change_mtu,
6612         .ndo_fix_features       = rtl8169_fix_features,
6613         .ndo_set_features       = rtl8169_set_features,
6614         .ndo_set_mac_address    = rtl_set_mac_address,
6615         .ndo_do_ioctl           = rtl8169_ioctl,
6616         .ndo_set_rx_mode        = rtl_set_rx_mode,
6617 #ifdef CONFIG_NET_POLL_CONTROLLER
6618         .ndo_poll_controller    = rtl8169_netpoll,
6619 #endif
6620
6621 };
6622
6623 static const struct rtl_cfg_info {
6624         void (*hw_start)(struct net_device *);
6625         unsigned int region;
6626         unsigned int align;
6627         u16 event_slow;
6628         unsigned features;
6629         u8 default_ver;
6630 } rtl_cfg_infos [] = {
6631         [RTL_CFG_0] = {
6632                 .hw_start       = rtl_hw_start_8169,
6633                 .region         = 1,
6634                 .align          = 0,
6635                 .event_slow     = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
6636                 .features       = RTL_FEATURE_GMII,
6637                 .default_ver    = RTL_GIGA_MAC_VER_01,
6638         },
6639         [RTL_CFG_1] = {
6640                 .hw_start       = rtl_hw_start_8168,
6641                 .region         = 2,
6642                 .align          = 8,
6643                 .event_slow     = SYSErr | LinkChg | RxOverflow,
6644                 .features       = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
6645                 .default_ver    = RTL_GIGA_MAC_VER_11,
6646         },
6647         [RTL_CFG_2] = {
6648                 .hw_start       = rtl_hw_start_8101,
6649                 .region         = 2,
6650                 .align          = 8,
6651                 .event_slow     = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
6652                                   PCSTimeout,
6653                 .features       = RTL_FEATURE_MSI,
6654                 .default_ver    = RTL_GIGA_MAC_VER_13,
6655         }
6656 };
6657
6658 /* Cfg9346_Unlock assumed. */
6659 static unsigned rtl_try_msi(struct rtl8169_private *tp,
6660                             const struct rtl_cfg_info *cfg)
6661 {
6662         void __iomem *ioaddr = tp->mmio_addr;
6663         unsigned msi = 0;
6664         u8 cfg2;
6665
6666         cfg2 = RTL_R8(Config2) & ~MSIEnable;
6667         if (cfg->features & RTL_FEATURE_MSI) {
6668                 if (pci_enable_msi(tp->pci_dev)) {
6669                         netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n");
6670                 } else {
6671                         cfg2 |= MSIEnable;
6672                         msi = RTL_FEATURE_MSI;
6673                 }
6674         }
6675         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
6676                 RTL_W8(Config2, cfg2);
6677         return msi;
6678 }
6679
6680 DECLARE_RTL_COND(rtl_link_list_ready_cond)
6681 {
6682         void __iomem *ioaddr = tp->mmio_addr;
6683
6684         return RTL_R8(MCU) & LINK_LIST_RDY;
6685 }
6686
6687 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
6688 {
6689         void __iomem *ioaddr = tp->mmio_addr;
6690
6691         return (RTL_R8(MCU) & RXTX_EMPTY) == RXTX_EMPTY;
6692 }
6693
6694 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
6695 {
6696         void __iomem *ioaddr = tp->mmio_addr;
6697         u32 data;
6698
6699         tp->ocp_base = OCP_STD_PHY_BASE;
6700
6701         RTL_W32(MISC, RTL_R32(MISC) | RXDV_GATED_EN);
6702
6703         if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
6704                 return;
6705
6706         if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
6707                 return;
6708
6709         RTL_W8(ChipCmd, RTL_R8(ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
6710         msleep(1);
6711         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
6712
6713         data = r8168_mac_ocp_read(tp, 0xe8de);
6714         data &= ~(1 << 14);
6715         r8168_mac_ocp_write(tp, 0xe8de, data);
6716
6717         if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
6718                 return;
6719
6720         data = r8168_mac_ocp_read(tp, 0xe8de);
6721         data |= (1 << 15);
6722         r8168_mac_ocp_write(tp, 0xe8de, data);
6723
6724         if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
6725                 return;
6726 }
6727
6728 static void rtl_hw_initialize(struct rtl8169_private *tp)
6729 {
6730         switch (tp->mac_version) {
6731         case RTL_GIGA_MAC_VER_40:
6732         case RTL_GIGA_MAC_VER_41:
6733                 rtl_hw_init_8168g(tp);
6734                 break;
6735
6736         default:
6737                 break;
6738         }
6739 }
6740
6741 static int
6742 rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
6743 {
6744         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
6745         const unsigned int region = cfg->region;
6746         struct rtl8169_private *tp;
6747         struct mii_if_info *mii;
6748         struct net_device *dev;
6749         void __iomem *ioaddr;
6750         int chipset, i;
6751         int rc;
6752
6753         if (netif_msg_drv(&debug)) {
6754                 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
6755                        MODULENAME, RTL8169_VERSION);
6756         }
6757
6758         dev = alloc_etherdev(sizeof (*tp));
6759         if (!dev) {
6760                 rc = -ENOMEM;
6761                 goto out;
6762         }
6763
6764         SET_NETDEV_DEV(dev, &pdev->dev);
6765         dev->netdev_ops = &rtl_netdev_ops;
6766         tp = netdev_priv(dev);
6767         tp->dev = dev;
6768         tp->pci_dev = pdev;
6769         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
6770
6771         mii = &tp->mii;
6772         mii->dev = dev;
6773         mii->mdio_read = rtl_mdio_read;
6774         mii->mdio_write = rtl_mdio_write;
6775         mii->phy_id_mask = 0x1f;
6776         mii->reg_num_mask = 0x1f;
6777         mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
6778
6779         /* disable ASPM completely as that cause random device stop working
6780          * problems as well as full system hangs for some PCIe devices users */
6781         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
6782                                      PCIE_LINK_STATE_CLKPM);
6783
6784         /* enable device (incl. PCI PM wakeup and hotplug setup) */
6785         rc = pci_enable_device(pdev);
6786         if (rc < 0) {
6787                 netif_err(tp, probe, dev, "enable failure\n");
6788                 goto err_out_free_dev_1;
6789         }
6790
6791         if (pci_set_mwi(pdev) < 0)
6792                 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
6793
6794         /* make sure PCI base addr 1 is MMIO */
6795         if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
6796                 netif_err(tp, probe, dev,
6797                           "region #%d not an MMIO resource, aborting\n",
6798                           region);
6799                 rc = -ENODEV;
6800                 goto err_out_mwi_2;
6801         }
6802
6803         /* check for weird/broken PCI region reporting */
6804         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
6805                 netif_err(tp, probe, dev,
6806                           "Invalid PCI region size(s), aborting\n");
6807                 rc = -ENODEV;
6808                 goto err_out_mwi_2;
6809         }
6810
6811         rc = pci_request_regions(pdev, MODULENAME);
6812         if (rc < 0) {
6813                 netif_err(tp, probe, dev, "could not request regions\n");
6814                 goto err_out_mwi_2;
6815         }
6816
6817         tp->cp_cmd = RxChkSum;
6818
6819         if ((sizeof(dma_addr_t) > 4) &&
6820             !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
6821                 tp->cp_cmd |= PCIDAC;
6822                 dev->features |= NETIF_F_HIGHDMA;
6823         } else {
6824                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
6825                 if (rc < 0) {
6826                         netif_err(tp, probe, dev, "DMA configuration failed\n");
6827                         goto err_out_free_res_3;
6828                 }
6829         }
6830
6831         /* ioremap MMIO region */
6832         ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
6833         if (!ioaddr) {
6834                 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
6835                 rc = -EIO;
6836                 goto err_out_free_res_3;
6837         }
6838         tp->mmio_addr = ioaddr;
6839
6840         if (!pci_is_pcie(pdev))
6841                 netif_info(tp, probe, dev, "not PCI Express\n");
6842
6843         /* Identify chip attached to board */
6844         rtl8169_get_mac_version(tp, dev, cfg->default_ver);
6845
6846         rtl_init_rxcfg(tp);
6847
6848         rtl_irq_disable(tp);
6849
6850         rtl_hw_initialize(tp);
6851
6852         rtl_hw_reset(tp);
6853
6854         rtl_ack_events(tp, 0xffff);
6855
6856         pci_set_master(pdev);
6857
6858         /*
6859          * Pretend we are using VLANs; This bypasses a nasty bug where
6860          * Interrupts stop flowing on high load on 8110SCd controllers.
6861          */
6862         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
6863                 tp->cp_cmd |= RxVlan;
6864
6865         rtl_init_mdio_ops(tp);
6866         rtl_init_pll_power_ops(tp);
6867         rtl_init_jumbo_ops(tp);
6868         rtl_init_csi_ops(tp);
6869
6870         rtl8169_print_mac_version(tp);
6871
6872         chipset = tp->mac_version;
6873         tp->txd_version = rtl_chip_infos[chipset].txd_version;
6874
6875         RTL_W8(Cfg9346, Cfg9346_Unlock);
6876         RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
6877         RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
6878         if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
6879                 tp->features |= RTL_FEATURE_WOL;
6880         if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
6881                 tp->features |= RTL_FEATURE_WOL;
6882         tp->features |= rtl_try_msi(tp, cfg);
6883         RTL_W8(Cfg9346, Cfg9346_Lock);
6884
6885         if (rtl_tbi_enabled(tp)) {
6886                 tp->set_speed = rtl8169_set_speed_tbi;
6887                 tp->get_settings = rtl8169_gset_tbi;
6888                 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
6889                 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
6890                 tp->link_ok = rtl8169_tbi_link_ok;
6891                 tp->do_ioctl = rtl_tbi_ioctl;
6892         } else {
6893                 tp->set_speed = rtl8169_set_speed_xmii;
6894                 tp->get_settings = rtl8169_gset_xmii;
6895                 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
6896                 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
6897                 tp->link_ok = rtl8169_xmii_link_ok;
6898                 tp->do_ioctl = rtl_xmii_ioctl;
6899         }
6900
6901         mutex_init(&tp->wk.mutex);
6902
6903         /* Get MAC address */
6904         for (i = 0; i < ETH_ALEN; i++)
6905                 dev->dev_addr[i] = RTL_R8(MAC0 + i);
6906         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
6907
6908         SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
6909         dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
6910
6911         netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
6912
6913         /* don't enable SG, IP_CSUM and TSO by default - it might not work
6914          * properly for all devices */
6915         dev->features |= NETIF_F_RXCSUM |
6916                 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
6917
6918         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
6919                 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
6920         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
6921                 NETIF_F_HIGHDMA;
6922
6923         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
6924                 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
6925                 dev->hw_features &= ~NETIF_F_HW_VLAN_RX;
6926
6927         dev->hw_features |= NETIF_F_RXALL;
6928         dev->hw_features |= NETIF_F_RXFCS;
6929
6930         tp->hw_start = cfg->hw_start;
6931         tp->event_slow = cfg->event_slow;
6932
6933         tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
6934                 ~(RxBOVF | RxFOVF) : ~0;
6935
6936         init_timer(&tp->timer);
6937         tp->timer.data = (unsigned long) dev;
6938         tp->timer.function = rtl8169_phy_timer;
6939
6940         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
6941
6942         rc = register_netdev(dev);
6943         if (rc < 0)
6944                 goto err_out_msi_4;
6945
6946         pci_set_drvdata(pdev, dev);
6947
6948         netif_info(tp, probe, dev, "%s at 0x%p, %pM, XID %08x IRQ %d\n",
6949                    rtl_chip_infos[chipset].name, ioaddr, dev->dev_addr,
6950                    (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), pdev->irq);
6951         if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
6952                 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
6953                            "tx checksumming: %s]\n",
6954                            rtl_chip_infos[chipset].jumbo_max,
6955                            rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko");
6956         }
6957
6958         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
6959             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
6960             tp->mac_version == RTL_GIGA_MAC_VER_31) {
6961                 rtl8168_driver_start(tp);
6962         }
6963
6964         device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
6965
6966         if (pci_dev_run_wake(pdev))
6967                 pm_runtime_put_noidle(&pdev->dev);
6968
6969         netif_carrier_off(dev);
6970
6971 out:
6972         return rc;
6973
6974 err_out_msi_4:
6975         netif_napi_del(&tp->napi);
6976         rtl_disable_msi(pdev, tp);
6977         iounmap(ioaddr);
6978 err_out_free_res_3:
6979         pci_release_regions(pdev);
6980 err_out_mwi_2:
6981         pci_clear_mwi(pdev);
6982         pci_disable_device(pdev);
6983 err_out_free_dev_1:
6984         free_netdev(dev);
6985         goto out;
6986 }
6987
6988 static struct pci_driver rtl8169_pci_driver = {
6989         .name           = MODULENAME,
6990         .id_table       = rtl8169_pci_tbl,
6991         .probe          = rtl_init_one,
6992         .remove         = rtl_remove_one,
6993         .shutdown       = rtl_shutdown,
6994         .driver.pm      = RTL8169_PM_OPS,
6995 };
6996
6997 module_pci_driver(rtl8169_pci_driver);