drivers/net/ethernet/realtek/r8169.c

   1 /*
   2  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   3  *
   4  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   5  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   6  * Copyright (c) a lot of people too. Please respect their work.
   7  *
   8  * See MAINTAINERS file for support contact information.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/moduleparam.h>
  13 #include <linux/pci.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/delay.h>
  17 #include <linux/ethtool.h>
  18 #include <linux/mii.h>
  19 #include <linux/if_vlan.h>
  20 #include <linux/crc32.h>
  21 #include <linux/in.h>
  22 #include <linux/ip.h>
  23 #include <linux/tcp.h>
  24 #include <linux/init.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/pm_runtime.h>
  28 #include <linux/firmware.h>
  29 #include <linux/pci-aspm.h>
  30 #include <linux/prefetch.h>
  31
  32 #include <asm/system.h>
  33 #include <asm/io.h>
  34 #include <asm/irq.h>
  35
  36 #define RTL8169_VERSION "2.3LK-NAPI"
  37 #define MODULENAME "r8169"
  38 #define PFX MODULENAME ": "
  39
  40 #define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
  41 #define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
  42 #define FIRMWARE_8168E_1        "rtl_nic/rtl8168e-1.fw"
  43 #define FIRMWARE_8168E_2        "rtl_nic/rtl8168e-2.fw"
  44 #define FIRMWARE_8168E_3        "rtl_nic/rtl8168e-3.fw"
  45 #define FIRMWARE_8168F_1        "rtl_nic/rtl8168f-1.fw"
  46 #define FIRMWARE_8168F_2        "rtl_nic/rtl8168f-2.fw"
  47 #define FIRMWARE_8105E_1        "rtl_nic/rtl8105e-1.fw"
  48
  49 #ifdef RTL8169_DEBUG
  50 #define assert(expr) \
  51         if (!(expr)) {                                  \
  52                 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
  53                 #expr,__FILE__,__func__,__LINE__);              \
  54         }
  55 #define dprintk(fmt, args...) \
  56         do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
  57 #else
  58 #define assert(expr) do {} while (0)
  59 #define dprintk(fmt, args...)   do {} while (0)
  60 #endif /* RTL8169_DEBUG */
  61
  62 #define R8169_MSG_DEFAULT \
  63         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  64
  65 #define TX_BUFFS_AVAIL(tp) \
  66         (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
  67
  68 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  69    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  70 static const int multicast_filter_limit = 32;
  71
  72 /* MAC address length */
  73 #define MAC_ADDR_LEN    6
  74
  75 #define MAX_READ_REQUEST_SHIFT  12
  76 #define TX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
  77 #define SafeMtu         0x1c20  /* ... actually life sucks beyond ~7k */
  78 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  79
  80 #define R8169_REGS_SIZE         256
  81 #define R8169_NAPI_WEIGHT       64
  82 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
  83 #define NUM_RX_DESC     256     /* Number of Rx descriptor registers */
  84 #define RX_BUF_SIZE     1536    /* Rx Buffer size */
  85 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  86 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  87
  88 #define RTL8169_TX_TIMEOUT      (6*HZ)
  89 #define RTL8169_PHY_TIMEOUT     (10*HZ)
  90
  91 #define RTL_EEPROM_SIG          cpu_to_le32(0x8129)
  92 #define RTL_EEPROM_SIG_MASK     cpu_to_le32(0xffff)
  93 #define RTL_EEPROM_SIG_ADDR     0x0000
  94
  95 /* write/read MMIO register */
  96 #define RTL_W8(reg, val8)       writeb ((val8), ioaddr + (reg))
  97 #define RTL_W16(reg, val16)     writew ((val16), ioaddr + (reg))
  98 #define RTL_W32(reg, val32)     writel ((val32), ioaddr + (reg))
  99 #define RTL_R8(reg)             readb (ioaddr + (reg))
 100 #define RTL_R16(reg)            readw (ioaddr + (reg))
 101 #define RTL_R32(reg)            readl (ioaddr + (reg))
 102
 103 enum mac_version {
 104         RTL_GIGA_MAC_VER_01 = 0,
 105         RTL_GIGA_MAC_VER_02,
 106         RTL_GIGA_MAC_VER_03,
 107         RTL_GIGA_MAC_VER_04,
 108         RTL_GIGA_MAC_VER_05,
 109         RTL_GIGA_MAC_VER_06,
 110         RTL_GIGA_MAC_VER_07,
 111         RTL_GIGA_MAC_VER_08,
 112         RTL_GIGA_MAC_VER_09,
 113         RTL_GIGA_MAC_VER_10,
 114         RTL_GIGA_MAC_VER_11,
 115         RTL_GIGA_MAC_VER_12,
 116         RTL_GIGA_MAC_VER_13,
 117         RTL_GIGA_MAC_VER_14,
 118         RTL_GIGA_MAC_VER_15,
 119         RTL_GIGA_MAC_VER_16,
 120         RTL_GIGA_MAC_VER_17,
 121         RTL_GIGA_MAC_VER_18,
 122         RTL_GIGA_MAC_VER_19,
 123         RTL_GIGA_MAC_VER_20,
 124         RTL_GIGA_MAC_VER_21,
 125         RTL_GIGA_MAC_VER_22,
 126         RTL_GIGA_MAC_VER_23,
 127         RTL_GIGA_MAC_VER_24,
 128         RTL_GIGA_MAC_VER_25,
 129         RTL_GIGA_MAC_VER_26,
 130         RTL_GIGA_MAC_VER_27,
 131         RTL_GIGA_MAC_VER_28,
 132         RTL_GIGA_MAC_VER_29,
 133         RTL_GIGA_MAC_VER_30,
 134         RTL_GIGA_MAC_VER_31,
 135         RTL_GIGA_MAC_VER_32,
 136         RTL_GIGA_MAC_VER_33,
 137         RTL_GIGA_MAC_VER_34,
 138         RTL_GIGA_MAC_VER_35,
 139         RTL_GIGA_MAC_VER_36,
 140         RTL_GIGA_MAC_NONE   = 0xff,
 141 };
 142
 143 enum rtl_tx_desc_version {
 144         RTL_TD_0        = 0,
 145         RTL_TD_1        = 1,
 146 };
 147
 148 #define _R(NAME,TD,FW) \
 149         { .name = NAME, .txd_version = TD, .fw_name = FW }
 150
 151 static const struct {
 152         const char *name;
 153         enum rtl_tx_desc_version txd_version;
 154         const char *fw_name;
 155 } rtl_chip_infos[] = {
 156         /* PCI devices. */
 157         [RTL_GIGA_MAC_VER_01] =
 158                 _R("RTL8169",           RTL_TD_0, NULL),
 159         [RTL_GIGA_MAC_VER_02] =
 160                 _R("RTL8169s",          RTL_TD_0, NULL),
 161         [RTL_GIGA_MAC_VER_03] =
 162                 _R("RTL8110s",          RTL_TD_0, NULL),
 163         [RTL_GIGA_MAC_VER_04] =
 164                 _R("RTL8169sb/8110sb",  RTL_TD_0, NULL),
 165         [RTL_GIGA_MAC_VER_05] =
 166                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL),
 167         [RTL_GIGA_MAC_VER_06] =
 168                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL),
 169         /* PCI-E devices. */
 170         [RTL_GIGA_MAC_VER_07] =
 171                 _R("RTL8102e",          RTL_TD_1, NULL),
 172         [RTL_GIGA_MAC_VER_08] =
 173                 _R("RTL8102e",          RTL_TD_1, NULL),
 174         [RTL_GIGA_MAC_VER_09] =
 175                 _R("RTL8102e",          RTL_TD_1, NULL),
 176         [RTL_GIGA_MAC_VER_10] =
 177                 _R("RTL8101e",          RTL_TD_0, NULL),
 178         [RTL_GIGA_MAC_VER_11] =
 179                 _R("RTL8168b/8111b",    RTL_TD_0, NULL),
 180         [RTL_GIGA_MAC_VER_12] =
 181                 _R("RTL8168b/8111b",    RTL_TD_0, NULL),
 182         [RTL_GIGA_MAC_VER_13] =
 183                 _R("RTL8101e",          RTL_TD_0, NULL),
 184         [RTL_GIGA_MAC_VER_14] =
 185                 _R("RTL8100e",          RTL_TD_0, NULL),
 186         [RTL_GIGA_MAC_VER_15] =
 187                 _R("RTL8100e",          RTL_TD_0, NULL),
 188         [RTL_GIGA_MAC_VER_16] =
 189                 _R("RTL8101e",          RTL_TD_0, NULL),
 190         [RTL_GIGA_MAC_VER_17] =
 191                 _R("RTL8168b/8111b",    RTL_TD_0, NULL),
 192         [RTL_GIGA_MAC_VER_18] =
 193                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL),
 194         [RTL_GIGA_MAC_VER_19] =
 195                 _R("RTL8168c/8111c",    RTL_TD_1, NULL),
 196         [RTL_GIGA_MAC_VER_20] =
 197                 _R("RTL8168c/8111c",    RTL_TD_1, NULL),
 198         [RTL_GIGA_MAC_VER_21] =
 199                 _R("RTL8168c/8111c",    RTL_TD_1, NULL),
 200         [RTL_GIGA_MAC_VER_22] =
 201                 _R("RTL8168c/8111c",    RTL_TD_1, NULL),
 202         [RTL_GIGA_MAC_VER_23] =
 203                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL),
 204         [RTL_GIGA_MAC_VER_24] =
 205                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL),
 206         [RTL_GIGA_MAC_VER_25] =
 207                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_1),
 208         [RTL_GIGA_MAC_VER_26] =
 209                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_2),
 210         [RTL_GIGA_MAC_VER_27] =
 211                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL),
 212         [RTL_GIGA_MAC_VER_28] =
 213                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL),
 214         [RTL_GIGA_MAC_VER_29] =
 215                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1),
 216         [RTL_GIGA_MAC_VER_30] =
 217                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1),
 218         [RTL_GIGA_MAC_VER_31] =
 219                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL),
 220         [RTL_GIGA_MAC_VER_32] =
 221                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_1),
 222         [RTL_GIGA_MAC_VER_33] =
 223                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_2),
 224         [RTL_GIGA_MAC_VER_34] =
 225                 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3),
 226         [RTL_GIGA_MAC_VER_35] =
 227                 _R("RTL8168f/8111f",    RTL_TD_1, FIRMWARE_8168F_1),
 228         [RTL_GIGA_MAC_VER_36] =
 229                 _R("RTL8168f/8111f",    RTL_TD_1, FIRMWARE_8168F_2)
 230 };
 231 #undef _R
 232
 233 enum cfg_version {
 234         RTL_CFG_0 = 0x00,
 235         RTL_CFG_1,
 236         RTL_CFG_2
 237 };
 238
 239 static void rtl_hw_start_8169(struct net_device *);
 240 static void rtl_hw_start_8168(struct net_device *);
 241 static void rtl_hw_start_8101(struct net_device *);
 242
 243 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
 244         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8129), 0, 0, RTL_CFG_0 },
 245         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8136), 0, 0, RTL_CFG_2 },
 246         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8167), 0, 0, RTL_CFG_0 },
 247         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8168), 0, 0, RTL_CFG_1 },
 248         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8169), 0, 0, RTL_CFG_0 },
 249         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4300), 0, 0, RTL_CFG_0 },
 250         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4302), 0, 0, RTL_CFG_0 },
 251         { PCI_DEVICE(PCI_VENDOR_ID_AT,          0xc107), 0, 0, RTL_CFG_0 },
 252         { PCI_DEVICE(0x16ec,                    0x0116), 0, 0, RTL_CFG_0 },
 253         { PCI_VENDOR_ID_LINKSYS,                0x1032,
 254                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
 255         { 0x0001,                               0x8168,
 256                 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
 257         {0,},
 258 };
 259
 260 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 261
 262 static int rx_buf_sz = 16383;
 263 static int use_dac;
 264 static struct {
 265         u32 msg_enable;
 266 } debug = { -1 };
 267
 268 enum rtl_registers {
 269         MAC0            = 0,    /* Ethernet hardware address. */
 270         MAC4            = 4,
 271         MAR0            = 8,    /* Multicast filter. */
 272         CounterAddrLow          = 0x10,
 273         CounterAddrHigh         = 0x14,
 274         TxDescStartAddrLow      = 0x20,
 275         TxDescStartAddrHigh     = 0x24,
 276         TxHDescStartAddrLow     = 0x28,
 277         TxHDescStartAddrHigh    = 0x2c,
 278         FLASH           = 0x30,
 279         ERSR            = 0x36,
 280         ChipCmd         = 0x37,
 281         TxPoll          = 0x38,
 282         IntrMask        = 0x3c,
 283         IntrStatus      = 0x3e,
 284
 285         TxConfig        = 0x40,
 286 #define TXCFG_AUTO_FIFO                 (1 << 7)        /* 8111e-vl */
 287 #define TXCFG_EMPTY                     (1 << 11)       /* 8111e-vl */
 288
 289         RxConfig        = 0x44,
 290 #define RX128_INT_EN                    (1 << 15)       /* 8111c and later */
 291 #define RX_MULTI_EN                     (1 << 14)       /* 8111c only */
 292 #define RXCFG_FIFO_SHIFT                13
 293                                         /* No threshold before first PCI xfer */
 294 #define RX_FIFO_THRESH                  (7 << RXCFG_FIFO_SHIFT)
 295 #define RXCFG_DMA_SHIFT                 8
 296                                         /* Unlimited maximum PCI burst. */
 297 #define RX_DMA_BURST                    (7 << RXCFG_DMA_SHIFT)
 298
 299         RxMissed        = 0x4c,
 300         Cfg9346         = 0x50,
 301         Config0         = 0x51,
 302         Config1         = 0x52,
 303         Config2         = 0x53,
 304         Config3         = 0x54,
 305         Config4         = 0x55,
 306         Config5         = 0x56,
 307         MultiIntr       = 0x5c,
 308         PHYAR           = 0x60,
 309         PHYstatus       = 0x6c,
 310         RxMaxSize       = 0xda,
 311         CPlusCmd        = 0xe0,
 312         IntrMitigate    = 0xe2,
 313         RxDescAddrLow   = 0xe4,
 314         RxDescAddrHigh  = 0xe8,
 315         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
 316
 317 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
 318
 319         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
 320
 321 #define TxPacketMax     (8064 >> 7)
 322 #define EarlySize       0x27
 323
 324         FuncEvent       = 0xf0,
 325         FuncEventMask   = 0xf4,
 326         FuncPresetState = 0xf8,
 327         FuncForceEvent  = 0xfc,
 328 };
 329
 330 enum rtl8110_registers {
 331         TBICSR                  = 0x64,
 332         TBI_ANAR                = 0x68,
 333         TBI_LPAR                = 0x6a,
 334 };
 335
 336 enum rtl8168_8101_registers {
 337         CSIDR                   = 0x64,
 338         CSIAR                   = 0x68,
 339 #define CSIAR_FLAG                      0x80000000
 340 #define CSIAR_WRITE_CMD                 0x80000000
 341 #define CSIAR_BYTE_ENABLE               0x0f
 342 #define CSIAR_BYTE_ENABLE_SHIFT         12
 343 #define CSIAR_ADDR_MASK                 0x0fff
 344         PMCH                    = 0x6f,
 345         EPHYAR                  = 0x80,
 346 #define EPHYAR_FLAG                     0x80000000
 347 #define EPHYAR_WRITE_CMD                0x80000000
 348 #define EPHYAR_REG_MASK                 0x1f
 349 #define EPHYAR_REG_SHIFT                16
 350 #define EPHYAR_DATA_MASK                0xffff
 351         DLLPR                   = 0xd0,
 352 #define PFM_EN                          (1 << 6)
 353         DBG_REG                 = 0xd1,
 354 #define FIX_NAK_1                       (1 << 4)
 355 #define FIX_NAK_2                       (1 << 3)
 356         TWSI                    = 0xd2,
 357         MCU                     = 0xd3,
 358 #define NOW_IS_OOB                      (1 << 7)
 359 #define EN_NDP                          (1 << 3)
 360 #define EN_OOB_RESET                    (1 << 2)
 361         EFUSEAR                 = 0xdc,
 362 #define EFUSEAR_FLAG                    0x80000000
 363 #define EFUSEAR_WRITE_CMD               0x80000000
 364 #define EFUSEAR_READ_CMD                0x00000000
 365 #define EFUSEAR_REG_MASK                0x03ff
 366 #define EFUSEAR_REG_SHIFT               8
 367 #define EFUSEAR_DATA_MASK               0xff
 368 };
 369
 370 enum rtl8168_registers {
 371         LED_FREQ                = 0x1a,
 372         EEE_LED                 = 0x1b,
 373         ERIDR                   = 0x70,
 374         ERIAR                   = 0x74,
 375 #define ERIAR_FLAG                      0x80000000
 376 #define ERIAR_WRITE_CMD                 0x80000000
 377 #define ERIAR_READ_CMD                  0x00000000
 378 #define ERIAR_ADDR_BYTE_ALIGN           4
 379 #define ERIAR_TYPE_SHIFT                16
 380 #define ERIAR_EXGMAC                    (0x00 << ERIAR_TYPE_SHIFT)
 381 #define ERIAR_MSIX                      (0x01 << ERIAR_TYPE_SHIFT)
 382 #define ERIAR_ASF                       (0x02 << ERIAR_TYPE_SHIFT)
 383 #define ERIAR_MASK_SHIFT                12
 384 #define ERIAR_MASK_0001                 (0x1 << ERIAR_MASK_SHIFT)
 385 #define ERIAR_MASK_0011                 (0x3 << ERIAR_MASK_SHIFT)
 386 #define ERIAR_MASK_1111                 (0xf << ERIAR_MASK_SHIFT)
 387         EPHY_RXER_NUM           = 0x7c,
 388         OCPDR                   = 0xb0, /* OCP GPHY access */
 389 #define OCPDR_WRITE_CMD                 0x80000000
 390 #define OCPDR_READ_CMD                  0x00000000
 391 #define OCPDR_REG_MASK                  0x7f
 392 #define OCPDR_GPHY_REG_SHIFT            16
 393 #define OCPDR_DATA_MASK                 0xffff
 394         OCPAR                   = 0xb4,
 395 #define OCPAR_FLAG                      0x80000000
 396 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
 397 #define OCPAR_GPHY_READ_CMD             0x0000f060
 398         RDSAR1                  = 0xd0, /* 8168c only. Undocumented on 8168dp */
 399         MISC                    = 0xf0, /* 8168e only. */
 400 #define TXPLA_RST                       (1 << 29)
 401 #define PWM_EN                          (1 << 22)
 402 };
 403
 404 enum rtl_register_content {
 405         /* InterruptStatusBits */
 406         SYSErr          = 0x8000,
 407         PCSTimeout      = 0x4000,
 408         SWInt           = 0x0100,
 409         TxDescUnavail   = 0x0080,
 410         RxFIFOOver      = 0x0040,
 411         LinkChg         = 0x0020,
 412         RxOverflow      = 0x0010,
 413         TxErr           = 0x0008,
 414         TxOK            = 0x0004,
 415         RxErr           = 0x0002,
 416         RxOK            = 0x0001,
 417
 418         /* RxStatusDesc */
 419         RxBOVF  = (1 << 24),
 420         RxFOVF  = (1 << 23),
 421         RxRWT   = (1 << 22),
 422         RxRES   = (1 << 21),
 423         RxRUNT  = (1 << 20),
 424         RxCRC   = (1 << 19),
 425
 426         /* ChipCmdBits */
 427         StopReq         = 0x80,
 428         CmdReset        = 0x10,
 429         CmdRxEnb        = 0x08,
 430         CmdTxEnb        = 0x04,
 431         RxBufEmpty      = 0x01,
 432
 433         /* TXPoll register p.5 */
 434         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 435         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 436         FSWInt          = 0x01,         /* Forced software interrupt */
 437
 438         /* Cfg9346Bits */
 439         Cfg9346_Lock    = 0x00,
 440         Cfg9346_Unlock  = 0xc0,
 441
 442         /* rx_mode_bits */
 443         AcceptErr       = 0x20,
 444         AcceptRunt      = 0x10,
 445         AcceptBroadcast = 0x08,
 446         AcceptMulticast = 0x04,
 447         AcceptMyPhys    = 0x02,
 448         AcceptAllPhys   = 0x01,
 449 #define RX_CONFIG_ACCEPT_MASK           0x3f
 450
 451         /* TxConfigBits */
 452         TxInterFrameGapShift = 24,
 453         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 454
 455         /* Config1 register p.24 */
 456         LEDS1           = (1 << 7),
 457         LEDS0           = (1 << 6),
 458         MSIEnable       = (1 << 5),     /* Enable Message Signaled Interrupt */
 459         Speed_down      = (1 << 4),
 460         MEMMAP          = (1 << 3),
 461         IOMAP           = (1 << 2),
 462         VPD             = (1 << 1),
 463         PMEnable        = (1 << 0),     /* Power Management Enable */
 464
 465         /* Config2 register p. 25 */
 466         PCI_Clock_66MHz = 0x01,
 467         PCI_Clock_33MHz = 0x00,
 468
 469         /* Config3 register p.25 */
 470         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 471         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 472         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
 473
 474         /* Config5 register p.27 */
 475         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 476         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 477         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 478         Spi_en          = (1 << 3),
 479         LanWake         = (1 << 1),     /* LanWake enable/disable */
 480         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 481
 482         /* TBICSR p.28 */
 483         TBIReset        = 0x80000000,
 484         TBILoopback     = 0x40000000,
 485         TBINwEnable     = 0x20000000,
 486         TBINwRestart    = 0x10000000,
 487         TBILinkOk       = 0x02000000,
 488         TBINwComplete   = 0x01000000,
 489
 490         /* CPlusCmd p.31 */
 491         EnableBist      = (1 << 15),    // 8168 8101
 492         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
 493         Normal_mode     = (1 << 13),    // unused
 494         Force_half_dup  = (1 << 12),    // 8168 8101
 495         Force_rxflow_en = (1 << 11),    // 8168 8101
 496         Force_txflow_en = (1 << 10),    // 8168 8101
 497         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
 498         ASF             = (1 << 8),     // 8168 8101
 499         PktCntrDisable  = (1 << 7),     // 8168 8101
 500         Mac_dbgo_sel    = 0x001c,       // 8168
 501         RxVlan          = (1 << 6),
 502         RxChkSum        = (1 << 5),
 503         PCIDAC          = (1 << 4),
 504         PCIMulRW        = (1 << 3),
 505         INTT_0          = 0x0000,       // 8168
 506         INTT_1          = 0x0001,       // 8168
 507         INTT_2          = 0x0002,       // 8168
 508         INTT_3          = 0x0003,       // 8168
 509
 510         /* rtl8169_PHYstatus */
 511         TBI_Enable      = 0x80,
 512         TxFlowCtrl      = 0x40,
 513         RxFlowCtrl      = 0x20,
 514         _1000bpsF       = 0x10,
 515         _100bps         = 0x08,
 516         _10bps          = 0x04,
 517         LinkStatus      = 0x02,
 518         FullDup         = 0x01,
 519
 520         /* _TBICSRBit */
 521         TBILinkOK       = 0x02000000,
 522
 523         /* DumpCounterCommand */
 524         CounterDump     = 0x8,
 525 };
 526
 527 enum rtl_desc_bit {
 528         /* First doubleword. */
 529         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 530         RingEnd         = (1 << 30), /* End of descriptor ring */
 531         FirstFrag       = (1 << 29), /* First segment of a packet */
 532         LastFrag        = (1 << 28), /* Final segment of a packet */
 533 };
 534
 535 /* Generic case. */
 536 enum rtl_tx_desc_bit {
 537         /* First doubleword. */
 538         TD_LSO          = (1 << 27),            /* Large Send Offload */
 539 #define TD_MSS_MAX                      0x07ffu /* MSS value */
 540
 541         /* Second doubleword. */
 542         TxVlanTag       = (1 << 17),            /* Add VLAN tag */
 543 };
 544
 545 /* 8169, 8168b and 810x except 8102e. */
 546 enum rtl_tx_desc_bit_0 {
 547         /* First doubleword. */
 548 #define TD0_MSS_SHIFT                   16      /* MSS position (11 bits) */
 549         TD0_TCP_CS      = (1 << 16),            /* Calculate TCP/IP checksum */
 550         TD0_UDP_CS      = (1 << 17),            /* Calculate UDP/IP checksum */
 551         TD0_IP_CS       = (1 << 18),            /* Calculate IP checksum */
 552 };
 553
 554 /* 8102e, 8168c and beyond. */
 555 enum rtl_tx_desc_bit_1 {
 556         /* Second doubleword. */
 557 #define TD1_MSS_SHIFT                   18      /* MSS position (11 bits) */
 558         TD1_IP_CS       = (1 << 29),            /* Calculate IP checksum */
 559         TD1_TCP_CS      = (1 << 30),            /* Calculate TCP/IP checksum */
 560         TD1_UDP_CS      = (1 << 31),            /* Calculate UDP/IP checksum */
 561 };
 562
 563 static const struct rtl_tx_desc_info {
 564         struct {
 565                 u32 udp;
 566                 u32 tcp;
 567         } checksum;
 568         u16 mss_shift;
 569         u16 opts_offset;
 570 } tx_desc_info [] = {
 571         [RTL_TD_0] = {
 572                 .checksum = {
 573                         .udp    = TD0_IP_CS | TD0_UDP_CS,
 574                         .tcp    = TD0_IP_CS | TD0_TCP_CS
 575                 },
 576                 .mss_shift      = TD0_MSS_SHIFT,
 577                 .opts_offset    = 0
 578         },
 579         [RTL_TD_1] = {
 580                 .checksum = {
 581                         .udp    = TD1_IP_CS | TD1_UDP_CS,
 582                         .tcp    = TD1_IP_CS | TD1_TCP_CS
 583                 },
 584                 .mss_shift      = TD1_MSS_SHIFT,
 585                 .opts_offset    = 1
 586         }
 587 };
 588
 589 enum rtl_rx_desc_bit {
 590         /* Rx private */
 591         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 592         PID0            = (1 << 17), /* Protocol ID bit 2/2 */
 593
 594 #define RxProtoUDP      (PID1)
 595 #define RxProtoTCP      (PID0)
 596 #define RxProtoIP       (PID1 | PID0)
 597 #define RxProtoMask     RxProtoIP
 598
 599         IPFail          = (1 << 16), /* IP checksum failed */
 600         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 601         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 602         RxVlanTag       = (1 << 16), /* VLAN tag available */
 603 };
 604
 605 #define RsvdMask        0x3fffc000
 606
 607 struct TxDesc {
 608         __le32 opts1;
 609         __le32 opts2;
 610         __le64 addr;
 611 };
 612
 613 struct RxDesc {
 614         __le32 opts1;
 615         __le32 opts2;
 616         __le64 addr;
 617 };
 618
 619 struct ring_info {
 620         struct sk_buff  *skb;
 621         u32             len;
 622         u8              __pad[sizeof(void *) - sizeof(u32)];
 623 };
 624
 625 enum features {
 626         RTL_FEATURE_WOL         = (1 << 0),
 627         RTL_FEATURE_MSI         = (1 << 1),
 628         RTL_FEATURE_GMII        = (1 << 2),
 629 };
 630
 631 struct rtl8169_counters {
 632         __le64  tx_packets;
 633         __le64  rx_packets;
 634         __le64  tx_errors;
 635         __le32  rx_errors;
 636         __le16  rx_missed;
 637         __le16  align_errors;
 638         __le32  tx_one_collision;
 639         __le32  tx_multi_collision;
 640         __le64  rx_unicast;
 641         __le64  rx_broadcast;
 642         __le32  rx_multicast;
 643         __le16  tx_aborted;
 644         __le16  tx_underun;
 645 };
 646
 647 struct rtl8169_private {
 648         void __iomem *mmio_addr;        /* memory map physical address */
 649         struct pci_dev *pci_dev;
 650         struct net_device *dev;
 651         struct napi_struct napi;
 652         spinlock_t lock;
 653         u32 msg_enable;
 654         u16 txd_version;
 655         u16 mac_version;
 656         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 657         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 658         u32 dirty_rx;
 659         u32 dirty_tx;
 660         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 661         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 662         dma_addr_t TxPhyAddr;
 663         dma_addr_t RxPhyAddr;
 664         void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
 665         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 666         struct timer_list timer;
 667         u16 cp_cmd;
 668         u16 intr_event;
 669         u16 napi_event;
 670         u16 intr_mask;
 671
 672         struct mdio_ops {
 673                 void (*write)(void __iomem *, int, int);
 674                 int (*read)(void __iomem *, int);
 675         } mdio_ops;
 676
 677         struct pll_power_ops {
 678                 void (*down)(struct rtl8169_private *);
 679                 void (*up)(struct rtl8169_private *);
 680         } pll_power_ops;
 681
 682         int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
 683         int (*get_settings)(struct net_device *, struct ethtool_cmd *);
 684         void (*phy_reset_enable)(struct rtl8169_private *tp);
 685         void (*hw_start)(struct net_device *);
 686         unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
 687         unsigned int (*link_ok)(void __iomem *);
 688         int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
 689         struct delayed_work task;
 690         unsigned features;
 691
 692         struct mii_if_info mii;
 693         struct rtl8169_counters counters;
 694         u32 saved_wolopts;
 695         u32 opts1_mask;
 696
 697         struct rtl_fw {
 698                 const struct firmware *fw;
 699
 700 #define RTL_VER_SIZE            32
 701
 702                 char version[RTL_VER_SIZE];
 703
 704                 struct rtl_fw_phy_action {
 705                         __le32 *code;
 706                         size_t size;
 707                 } phy_action;
 708         } *rtl_fw;
 709 #define RTL_FIRMWARE_UNKNOWN    ERR_PTR(-EAGAIN)
 710 };
 711
 712 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 713 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 714 module_param(use_dac, int, 0);
 715 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
 716 module_param_named(debug, debug.msg_enable, int, 0);
 717 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
 718 MODULE_LICENSE("GPL");
 719 MODULE_VERSION(RTL8169_VERSION);
 720 MODULE_FIRMWARE(FIRMWARE_8168D_1);
 721 MODULE_FIRMWARE(FIRMWARE_8168D_2);
 722 MODULE_FIRMWARE(FIRMWARE_8168E_1);
 723 MODULE_FIRMWARE(FIRMWARE_8168E_2);
 724 MODULE_FIRMWARE(FIRMWARE_8168E_3);
 725 MODULE_FIRMWARE(FIRMWARE_8105E_1);
 726 MODULE_FIRMWARE(FIRMWARE_8168F_1);
 727 MODULE_FIRMWARE(FIRMWARE_8168F_2);
 728
 729 static int rtl8169_open(struct net_device *dev);
 730 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
 731                                       struct net_device *dev);
 732 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
 733 static int rtl8169_init_ring(struct net_device *dev);
 734 static void rtl_hw_start(struct net_device *dev);
 735 static int rtl8169_close(struct net_device *dev);
 736 static void rtl_set_rx_mode(struct net_device *dev);
 737 static void rtl8169_tx_timeout(struct net_device *dev);
 738 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
 739 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
 740                                 void __iomem *, u32 budget);
 741 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
 742 static void rtl8169_down(struct net_device *dev);
 743 static void rtl8169_rx_clear(struct rtl8169_private *tp);
 744 static int rtl8169_poll(struct napi_struct *napi, int budget);
 745
 746 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
 747 {
 748         void __iomem *ioaddr = tp->mmio_addr;
 749         int i;
 750
 751         RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
 752         for (i = 0; i < 20; i++) {
 753                 udelay(100);
 754                 if (RTL_R32(OCPAR) & OCPAR_FLAG)
 755                         break;
 756         }
 757         return RTL_R32(OCPDR);
 758 }
 759
 760 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
 761 {
 762         void __iomem *ioaddr = tp->mmio_addr;
 763         int i;
 764
 765         RTL_W32(OCPDR, data);
 766         RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
 767         for (i = 0; i < 20; i++) {
 768                 udelay(100);
 769                 if ((RTL_R32(OCPAR) & OCPAR_FLAG) == 0)
 770                         break;
 771         }
 772 }
 773
 774 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
 775 {
 776         void __iomem *ioaddr = tp->mmio_addr;
 777         int i;
 778
 779         RTL_W8(ERIDR, cmd);
 780         RTL_W32(ERIAR, 0x800010e8);
 781         msleep(2);
 782         for (i = 0; i < 5; i++) {
 783                 udelay(100);
 784                 if (!(RTL_R32(ERIAR) & ERIAR_FLAG))
 785                         break;
 786         }
 787
 788         ocp_write(tp, 0x1, 0x30, 0x00000001);
 789 }
 790
 791 #define OOB_CMD_RESET           0x00
 792 #define OOB_CMD_DRIVER_START    0x05
 793 #define OOB_CMD_DRIVER_STOP     0x06
 794
 795 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
 796 {
 797         return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
 798 }
 799
 800 static void rtl8168_driver_start(struct rtl8169_private *tp)
 801 {
 802         u16 reg;
 803         int i;
 804
 805         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
 806
 807         reg = rtl8168_get_ocp_reg(tp);
 808
 809         for (i = 0; i < 10; i++) {
 810                 msleep(10);
 811                 if (ocp_read(tp, 0x0f, reg) & 0x00000800)
 812                         break;
 813         }
 814 }
 815
 816 static void rtl8168_driver_stop(struct rtl8169_private *tp)
 817 {
 818         u16 reg;
 819         int i;
 820
 821         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
 822
 823         reg = rtl8168_get_ocp_reg(tp);
 824
 825         for (i = 0; i < 10; i++) {
 826                 msleep(10);
 827                 if ((ocp_read(tp, 0x0f, reg) & 0x00000800) == 0)
 828                         break;
 829         }
 830 }
 831
 832 static int r8168dp_check_dash(struct rtl8169_private *tp)
 833 {
 834         u16 reg = rtl8168_get_ocp_reg(tp);
 835
 836         return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
 837 }
 838
 839 static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 840 {
 841         int i;
 842
 843         RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
 844
 845         for (i = 20; i > 0; i--) {
 846                 /*
 847                  * Check if the RTL8169 has completed writing to the specified
 848                  * MII register.
 849                  */
 850                 if (!(RTL_R32(PHYAR) & 0x80000000))
 851                         break;
 852                 udelay(25);
 853         }
 854         /*
 855          * According to hardware specs a 20us delay is required after write
 856          * complete indication, but before sending next command.
 857          */
 858         udelay(20);
 859 }
 860
 861 static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr)
 862 {
 863         int i, value = -1;
 864
 865         RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
 866
 867         for (i = 20; i > 0; i--) {
 868                 /*
 869                  * Check if the RTL8169 has completed retrieving data from
 870                  * the specified MII register.
 871                  */
 872                 if (RTL_R32(PHYAR) & 0x80000000) {
 873                         value = RTL_R32(PHYAR) & 0xffff;
 874                         break;
 875                 }
 876                 udelay(25);
 877         }
 878         /*
 879          * According to hardware specs a 20us delay is required after read
 880          * complete indication, but before sending next command.
 881          */
 882         udelay(20);
 883
 884         return value;
 885 }
 886
 887 static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data)
 888 {
 889         int i;
 890
 891         RTL_W32(OCPDR, data |
 892                 ((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
 893         RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
 894         RTL_W32(EPHY_RXER_NUM, 0);
 895
 896         for (i = 0; i < 100; i++) {
 897                 mdelay(1);
 898                 if (!(RTL_R32(OCPAR) & OCPAR_FLAG))
 899                         break;
 900         }
 901 }
 902
 903 static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 904 {
 905         r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD |
 906                 (value & OCPDR_DATA_MASK));
 907 }
 908
 909 static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr)
 910 {
 911         int i;
 912
 913         r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD);
 914
 915         mdelay(1);
 916         RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
 917         RTL_W32(EPHY_RXER_NUM, 0);
 918
 919         for (i = 0; i < 100; i++) {
 920                 mdelay(1);
 921                 if (RTL_R32(OCPAR) & OCPAR_FLAG)
 922                         break;
 923         }
 924
 925         return RTL_R32(OCPDR) & OCPDR_DATA_MASK;
 926 }
 927
 928 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
 929
 930 static void r8168dp_2_mdio_start(void __iomem *ioaddr)
 931 {
 932         RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
 933 }
 934
 935 static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
 936 {
 937         RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
 938 }
 939
 940 static void r8168dp_2_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 941 {
 942         r8168dp_2_mdio_start(ioaddr);
 943
 944         r8169_mdio_write(ioaddr, reg_addr, value);
 945
 946         r8168dp_2_mdio_stop(ioaddr);
 947 }
 948
 949 static int r8168dp_2_mdio_read(void __iomem *ioaddr, int reg_addr)
 950 {
 951         int value;
 952
 953         r8168dp_2_mdio_start(ioaddr);
 954
 955         value = r8169_mdio_read(ioaddr, reg_addr);
 956
 957         r8168dp_2_mdio_stop(ioaddr);
 958
 959         return value;
 960 }
 961
 962 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
 963 {
 964         tp->mdio_ops.write(tp->mmio_addr, location, val);
 965 }
 966
 967 static int rtl_readphy(struct rtl8169_private *tp, int location)
 968 {
 969         return tp->mdio_ops.read(tp->mmio_addr, location);
 970 }
 971
 972 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
 973 {
 974         rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
 975 }
 976
 977 static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
 978 {
 979         int val;
 980
 981         val = rtl_readphy(tp, reg_addr);
 982         rtl_writephy(tp, reg_addr, (val | p) & ~m);
 983 }
 984
 985 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
 986                            int val)
 987 {
 988         struct rtl8169_private *tp = netdev_priv(dev);
 989
 990         rtl_writephy(tp, location, val);
 991 }
 992
 993 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
 994 {
 995         struct rtl8169_private *tp = netdev_priv(dev);
 996
 997         return rtl_readphy(tp, location);
 998 }
 999
1000 static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
1001 {
1002         unsigned int i;
1003
1004         RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1005                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1006
1007         for (i = 0; i < 100; i++) {
1008                 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
1009                         break;
1010                 udelay(10);
1011         }
1012 }
1013
1014 static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
1015 {
1016         u16 value = 0xffff;
1017         unsigned int i;
1018
1019         RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1020
1021         for (i = 0; i < 100; i++) {
1022                 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
1023                         value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
1024                         break;
1025                 }
1026                 udelay(10);
1027         }
1028
1029         return value;
1030 }
1031
1032 static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
1033 {
1034         unsigned int i;
1035
1036         RTL_W32(CSIDR, value);
1037         RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
1038                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1039
1040         for (i = 0; i < 100; i++) {
1041                 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
1042                         break;
1043                 udelay(10);
1044         }
1045 }
1046
1047 static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
1048 {
1049         u32 value = ~0x00;
1050         unsigned int i;
1051
1052         RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
1053                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1054
1055         for (i = 0; i < 100; i++) {
1056                 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
1057                         value = RTL_R32(CSIDR);
1058                         break;
1059                 }
1060                 udelay(10);
1061         }
1062
1063         return value;
1064 }
1065
1066 static
1067 void rtl_eri_write(void __iomem *ioaddr, int addr, u32 mask, u32 val, int type)
1068 {
1069         unsigned int i;
1070
1071         BUG_ON((addr & 3) || (mask == 0));
1072         RTL_W32(ERIDR, val);
1073         RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1074
1075         for (i = 0; i < 100; i++) {
1076                 if (!(RTL_R32(ERIAR) & ERIAR_FLAG))
1077                         break;
1078                 udelay(100);
1079         }
1080 }
1081
1082 static u32 rtl_eri_read(void __iomem *ioaddr, int addr, int type)
1083 {
1084         u32 value = ~0x00;
1085         unsigned int i;
1086
1087         RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1088
1089         for (i = 0; i < 100; i++) {
1090                 if (RTL_R32(ERIAR) & ERIAR_FLAG) {
1091                         value = RTL_R32(ERIDR);
1092                         break;
1093                 }
1094                 udelay(100);
1095         }
1096
1097         return value;
1098 }
1099
1100 static void
1101 rtl_w1w0_eri(void __iomem *ioaddr, int addr, u32 mask, u32 p, u32 m, int type)
1102 {
1103         u32 val;
1104
1105         val = rtl_eri_read(ioaddr, addr, type);
1106         rtl_eri_write(ioaddr, addr, mask, (val & ~m) | p, type);
1107 }
1108
1109 struct exgmac_reg {
1110         u16 addr;
1111         u16 mask;
1112         u32 val;
1113 };
1114
1115 static void rtl_write_exgmac_batch(void __iomem *ioaddr,
1116                                    const struct exgmac_reg *r, int len)
1117 {
1118         while (len-- > 0) {
1119                 rtl_eri_write(ioaddr, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1120                 r++;
1121         }
1122 }
1123
1124 static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
1125 {
1126         u8 value = 0xff;
1127         unsigned int i;
1128
1129         RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1130
1131         for (i = 0; i < 300; i++) {
1132                 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
1133                         value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
1134                         break;
1135                 }
1136                 udelay(100);
1137         }
1138
1139         return value;
1140 }
1141
1142 static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
1143 {
1144         RTL_W16(IntrMask, 0x0000);
1145
1146         RTL_W16(IntrStatus, 0xffff);
1147 }
1148
1149 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1150 {
1151         void __iomem *ioaddr = tp->mmio_addr;
1152
1153         return RTL_R32(TBICSR) & TBIReset;
1154 }
1155
1156 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1157 {
1158         return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1159 }
1160
1161 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1162 {
1163         return RTL_R32(TBICSR) & TBILinkOk;
1164 }
1165
1166 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1167 {
1168         return RTL_R8(PHYstatus) & LinkStatus;
1169 }
1170
1171 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1172 {
1173         void __iomem *ioaddr = tp->mmio_addr;
1174
1175         RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1176 }
1177
1178 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1179 {
1180         unsigned int val;
1181
1182         val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1183         rtl_writephy(tp, MII_BMCR, val & 0xffff);
1184 }
1185
1186 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1187 {
1188         void __iomem *ioaddr = tp->mmio_addr;
1189         struct net_device *dev = tp->dev;
1190
1191         if (!netif_running(dev))
1192                 return;
1193
1194         if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
1195                 if (RTL_R8(PHYstatus) & _1000bpsF) {
1196                         rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1197                                       0x00000011, ERIAR_EXGMAC);
1198                         rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1199                                       0x00000005, ERIAR_EXGMAC);
1200                 } else if (RTL_R8(PHYstatus) & _100bps) {
1201                         rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1202                                       0x0000001f, ERIAR_EXGMAC);
1203                         rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1204                                       0x00000005, ERIAR_EXGMAC);
1205                 } else {
1206                         rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1207                                       0x0000001f, ERIAR_EXGMAC);
1208                         rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1209                                       0x0000003f, ERIAR_EXGMAC);
1210                 }
1211                 /* Reset packet filter */
1212                 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1213                              ERIAR_EXGMAC);
1214                 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1215                              ERIAR_EXGMAC);
1216         } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1217                    tp->mac_version == RTL_GIGA_MAC_VER_36) {
1218                 if (RTL_R8(PHYstatus) & _1000bpsF) {
1219                         rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1220                                       0x00000011, ERIAR_EXGMAC);
1221                         rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1222                                       0x00000005, ERIAR_EXGMAC);
1223                 } else {
1224                         rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1225                                       0x0000001f, ERIAR_EXGMAC);
1226                         rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1227                                       0x0000003f, ERIAR_EXGMAC);
1228                 }
1229         }
1230 }
1231
1232 static void __rtl8169_check_link_status(struct net_device *dev,
1233                                         struct rtl8169_private *tp,
1234                                         void __iomem *ioaddr, bool pm)
1235 {
1236         unsigned long flags;
1237
1238         spin_lock_irqsave(&tp->lock, flags);
1239         if (tp->link_ok(ioaddr)) {
1240                 rtl_link_chg_patch(tp);
1241                 /* This is to cancel a scheduled suspend if there's one. */
1242                 if (pm)
1243                         pm_request_resume(&tp->pci_dev->dev);
1244                 netif_carrier_on(dev);
1245                 if (net_ratelimit())
1246                         netif_info(tp, ifup, dev, "link up\n");
1247         } else {
1248                 netif_carrier_off(dev);
1249                 netif_info(tp, ifdown, dev, "link down\n");
1250                 if (pm)
1251                         pm_schedule_suspend(&tp->pci_dev->dev, 100);
1252         }
1253         spin_unlock_irqrestore(&tp->lock, flags);
1254 }
1255
1256 static void rtl8169_check_link_status(struct net_device *dev,
1257                                       struct rtl8169_private *tp,
1258                                       void __iomem *ioaddr)
1259 {
1260         __rtl8169_check_link_status(dev, tp, ioaddr, false);
1261 }
1262
1263 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1264
1265 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1266 {
1267         void __iomem *ioaddr = tp->mmio_addr;
1268         u8 options;
1269         u32 wolopts = 0;
1270
1271         options = RTL_R8(Config1);
1272         if (!(options & PMEnable))
1273                 return 0;
1274
1275         options = RTL_R8(Config3);
1276         if (options & LinkUp)
1277                 wolopts |= WAKE_PHY;
1278         if (options & MagicPacket)
1279                 wolopts |= WAKE_MAGIC;
1280
1281         options = RTL_R8(Config5);
1282         if (options & UWF)
1283                 wolopts |= WAKE_UCAST;
1284         if (options & BWF)
1285                 wolopts |= WAKE_BCAST;
1286         if (options & MWF)
1287                 wolopts |= WAKE_MCAST;
1288
1289         return wolopts;
1290 }
1291
1292 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1293 {
1294         struct rtl8169_private *tp = netdev_priv(dev);
1295
1296         spin_lock_irq(&tp->lock);
1297
1298         wol->supported = WAKE_ANY;
1299         wol->wolopts = __rtl8169_get_wol(tp);
1300
1301         spin_unlock_irq(&tp->lock);
1302 }
1303
1304 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1305 {
1306         void __iomem *ioaddr = tp->mmio_addr;
1307         unsigned int i;
1308         static const struct {
1309                 u32 opt;
1310                 u16 reg;
1311                 u8  mask;
1312         } cfg[] = {
1313                 { WAKE_ANY,   Config1, PMEnable },
1314                 { WAKE_PHY,   Config3, LinkUp },
1315                 { WAKE_MAGIC, Config3, MagicPacket },
1316                 { WAKE_UCAST, Config5, UWF },
1317                 { WAKE_BCAST, Config5, BWF },
1318                 { WAKE_MCAST, Config5, MWF },
1319                 { WAKE_ANY,   Config5, LanWake }
1320         };
1321
1322         RTL_W8(Cfg9346, Cfg9346_Unlock);
1323
1324         for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1325                 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
1326                 if (wolopts & cfg[i].opt)
1327                         options |= cfg[i].mask;
1328                 RTL_W8(cfg[i].reg, options);
1329         }
1330
1331         RTL_W8(Cfg9346, Cfg9346_Lock);
1332 }
1333
1334 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1335 {
1336         struct rtl8169_private *tp = netdev_priv(dev);
1337
1338         spin_lock_irq(&tp->lock);
1339
1340         if (wol->wolopts)
1341                 tp->features |= RTL_FEATURE_WOL;
1342         else
1343                 tp->features &= ~RTL_FEATURE_WOL;
1344         __rtl8169_set_wol(tp, wol->wolopts);
1345         spin_unlock_irq(&tp->lock);
1346
1347         device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1348
1349         return 0;
1350 }
1351
1352 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1353 {
1354         return rtl_chip_infos[tp->mac_version].fw_name;
1355 }
1356
1357 static void rtl8169_get_drvinfo(struct net_device *dev,
1358                                 struct ethtool_drvinfo *info)
1359 {
1360         struct rtl8169_private *tp = netdev_priv(dev);
1361         struct rtl_fw *rtl_fw = tp->rtl_fw;
1362
1363         strcpy(info->driver, MODULENAME);
1364         strcpy(info->version, RTL8169_VERSION);
1365         strcpy(info->bus_info, pci_name(tp->pci_dev));
1366         BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1367         strcpy(info->fw_version, IS_ERR_OR_NULL(rtl_fw) ? "N/A" :
1368                rtl_fw->version);
1369 }
1370
1371 static int rtl8169_get_regs_len(struct net_device *dev)
1372 {
1373         return R8169_REGS_SIZE;
1374 }
1375
1376 static int rtl8169_set_speed_tbi(struct net_device *dev,
1377                                  u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1378 {
1379         struct rtl8169_private *tp = netdev_priv(dev);
1380         void __iomem *ioaddr = tp->mmio_addr;
1381         int ret = 0;
1382         u32 reg;
1383
1384         reg = RTL_R32(TBICSR);
1385         if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1386             (duplex == DUPLEX_FULL)) {
1387                 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1388         } else if (autoneg == AUTONEG_ENABLE)
1389                 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1390         else {
1391                 netif_warn(tp, link, dev,
1392                            "incorrect speed setting refused in TBI mode\n");
1393                 ret = -EOPNOTSUPP;
1394         }
1395
1396         return ret;
1397 }
1398
1399 static int rtl8169_set_speed_xmii(struct net_device *dev,
1400                                   u8 autoneg, u16 speed, u8 duplex, u32 adv)
1401 {
1402         struct rtl8169_private *tp = netdev_priv(dev);
1403         int giga_ctrl, bmcr;
1404         int rc = -EINVAL;
1405
1406         rtl_writephy(tp, 0x1f, 0x0000);
1407
1408         if (autoneg == AUTONEG_ENABLE) {
1409                 int auto_nego;
1410
1411                 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1412                 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1413                                 ADVERTISE_100HALF | ADVERTISE_100FULL);
1414
1415                 if (adv & ADVERTISED_10baseT_Half)
1416                         auto_nego |= ADVERTISE_10HALF;
1417                 if (adv & ADVERTISED_10baseT_Full)
1418                         auto_nego |= ADVERTISE_10FULL;
1419                 if (adv & ADVERTISED_100baseT_Half)
1420                         auto_nego |= ADVERTISE_100HALF;
1421                 if (adv & ADVERTISED_100baseT_Full)
1422                         auto_nego |= ADVERTISE_100FULL;
1423
1424                 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1425
1426                 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1427                 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1428
1429                 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1430                 if (tp->mii.supports_gmii) {
1431                         if (adv & ADVERTISED_1000baseT_Half)
1432                                 giga_ctrl |= ADVERTISE_1000HALF;
1433                         if (adv & ADVERTISED_1000baseT_Full)
1434                                 giga_ctrl |= ADVERTISE_1000FULL;
1435                 } else if (adv & (ADVERTISED_1000baseT_Half |
1436                                   ADVERTISED_1000baseT_Full)) {
1437                         netif_info(tp, link, dev,
1438                                    "PHY does not support 1000Mbps\n");
1439                         goto out;
1440                 }
1441
1442                 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1443
1444                 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1445                 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1446         } else {
1447                 giga_ctrl = 0;
1448
1449                 if (speed == SPEED_10)
1450                         bmcr = 0;
1451                 else if (speed == SPEED_100)
1452                         bmcr = BMCR_SPEED100;
1453                 else
1454                         goto out;
1455
1456                 if (duplex == DUPLEX_FULL)
1457                         bmcr |= BMCR_FULLDPLX;
1458         }
1459
1460         rtl_writephy(tp, MII_BMCR, bmcr);
1461
1462         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1463             tp->mac_version == RTL_GIGA_MAC_VER_03) {
1464                 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1465                         rtl_writephy(tp, 0x17, 0x2138);
1466                         rtl_writephy(tp, 0x0e, 0x0260);
1467                 } else {
1468                         rtl_writephy(tp, 0x17, 0x2108);
1469                         rtl_writephy(tp, 0x0e, 0x0000);
1470                 }
1471         }
1472
1473         rc = 0;
1474 out:
1475         return rc;
1476 }
1477
1478 static int rtl8169_set_speed(struct net_device *dev,
1479                              u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1480 {
1481         struct rtl8169_private *tp = netdev_priv(dev);
1482         int ret;
1483
1484         ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
1485         if (ret < 0)
1486                 goto out;
1487
1488         if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1489             (advertising & ADVERTISED_1000baseT_Full)) {
1490                 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1491         }
1492 out:
1493         return ret;
1494 }
1495
1496 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1497 {
1498         struct rtl8169_private *tp = netdev_priv(dev);
1499         unsigned long flags;
1500         int ret;
1501
1502         del_timer_sync(&tp->timer);
1503
1504         spin_lock_irqsave(&tp->lock, flags);
1505         ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
1506                                 cmd->duplex, cmd->advertising);
1507         spin_unlock_irqrestore(&tp->lock, flags);
1508
1509         return ret;
1510 }
1511
1512 static u32 rtl8169_fix_features(struct net_device *dev, u32 features)
1513 {
1514         if (dev->mtu > TD_MSS_MAX)
1515                 features &= ~NETIF_F_ALL_TSO;
1516
1517         return features;
1518 }
1519
1520 static int rtl8169_set_features(struct net_device *dev, u32 features)
1521 {
1522         struct rtl8169_private *tp = netdev_priv(dev);
1523         void __iomem *ioaddr = tp->mmio_addr;
1524         unsigned long flags;
1525
1526         spin_lock_irqsave(&tp->lock, flags);
1527
1528         if (features & NETIF_F_RXCSUM)
1529                 tp->cp_cmd |= RxChkSum;
1530         else
1531                 tp->cp_cmd &= ~RxChkSum;
1532
1533         if (dev->features & NETIF_F_HW_VLAN_RX)
1534                 tp->cp_cmd |= RxVlan;
1535         else
1536                 tp->cp_cmd &= ~RxVlan;
1537
1538         RTL_W16(CPlusCmd, tp->cp_cmd);
1539         RTL_R16(CPlusCmd);
1540
1541         spin_unlock_irqrestore(&tp->lock, flags);
1542
1543         return 0;
1544 }
1545
1546 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1547                                       struct sk_buff *skb)
1548 {
1549         return (vlan_tx_tag_present(skb)) ?
1550                 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1551 }
1552
1553 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1554 {
1555         u32 opts2 = le32_to_cpu(desc->opts2);
1556
1557         if (opts2 & RxVlanTag)
1558                 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
1559
1560         desc->opts2 = 0;
1561 }
1562
1563 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1564 {
1565         struct rtl8169_private *tp = netdev_priv(dev);
1566         void __iomem *ioaddr = tp->mmio_addr;
1567         u32 status;
1568
1569         cmd->supported =
1570                 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1571         cmd->port = PORT_FIBRE;
1572         cmd->transceiver = XCVR_INTERNAL;
1573
1574         status = RTL_R32(TBICSR);
1575         cmd->advertising = (status & TBINwEnable) ?  ADVERTISED_Autoneg : 0;
1576         cmd->autoneg = !!(status & TBINwEnable);
1577
1578         ethtool_cmd_speed_set(cmd, SPEED_1000);
1579         cmd->duplex = DUPLEX_FULL; /* Always set */
1580
1581         return 0;
1582 }
1583
1584 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1585 {
1586         struct rtl8169_private *tp = netdev_priv(dev);
1587
1588         return mii_ethtool_gset(&tp->mii, cmd);
1589 }
1590
1591 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1592 {
1593         struct rtl8169_private *tp = netdev_priv(dev);
1594         unsigned long flags;
1595         int rc;
1596
1597         spin_lock_irqsave(&tp->lock, flags);
1598
1599         rc = tp->get_settings(dev, cmd);
1600
1601         spin_unlock_irqrestore(&tp->lock, flags);
1602         return rc;
1603 }
1604
1605 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1606                              void *p)
1607 {
1608         struct rtl8169_private *tp = netdev_priv(dev);
1609         unsigned long flags;
1610
1611         if (regs->len > R8169_REGS_SIZE)
1612                 regs->len = R8169_REGS_SIZE;
1613
1614         spin_lock_irqsave(&tp->lock, flags);
1615         memcpy_fromio(p, tp->mmio_addr, regs->len);
1616         spin_unlock_irqrestore(&tp->lock, flags);
1617 }
1618
1619 static u32 rtl8169_get_msglevel(struct net_device *dev)
1620 {
1621         struct rtl8169_private *tp = netdev_priv(dev);
1622
1623         return tp->msg_enable;
1624 }
1625
1626 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1627 {
1628         struct rtl8169_private *tp = netdev_priv(dev);
1629
1630         tp->msg_enable = value;
1631 }
1632
1633 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1634         "tx_packets",
1635         "rx_packets",
1636         "tx_errors",
1637         "rx_errors",
1638         "rx_missed",
1639         "align_errors",
1640         "tx_single_collisions",
1641         "tx_multi_collisions",
1642         "unicast",
1643         "broadcast",
1644         "multicast",
1645         "tx_aborted",
1646         "tx_underrun",
1647 };
1648
1649 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1650 {
1651         switch (sset) {
1652         case ETH_SS_STATS:
1653                 return ARRAY_SIZE(rtl8169_gstrings);
1654         default:
1655                 return -EOPNOTSUPP;
1656         }
1657 }
1658
1659 static void rtl8169_update_counters(struct net_device *dev)
1660 {
1661         struct rtl8169_private *tp = netdev_priv(dev);
1662         void __iomem *ioaddr = tp->mmio_addr;
1663         struct device *d = &tp->pci_dev->dev;
1664         struct rtl8169_counters *counters;
1665         dma_addr_t paddr;
1666         u32 cmd;
1667         int wait = 1000;
1668
1669         /*
1670          * Some chips are unable to dump tally counters when the receiver
1671          * is disabled.
1672          */
1673         if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1674                 return;
1675
1676         counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
1677         if (!counters)
1678                 return;
1679
1680         RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1681         cmd = (u64)paddr & DMA_BIT_MASK(32);
1682         RTL_W32(CounterAddrLow, cmd);
1683         RTL_W32(CounterAddrLow, cmd | CounterDump);
1684
1685         while (wait--) {
1686                 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1687                         memcpy(&tp->counters, counters, sizeof(*counters));
1688                         break;
1689                 }
1690                 udelay(10);
1691         }
1692
1693         RTL_W32(CounterAddrLow, 0);
1694         RTL_W32(CounterAddrHigh, 0);
1695
1696         dma_free_coherent(d, sizeof(*counters), counters, paddr);
1697 }
1698
1699 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1700                                       struct ethtool_stats *stats, u64 *data)
1701 {
1702         struct rtl8169_private *tp = netdev_priv(dev);
1703
1704         ASSERT_RTNL();
1705
1706         rtl8169_update_counters(dev);
1707
1708         data[0] = le64_to_cpu(tp->counters.tx_packets);
1709         data[1] = le64_to_cpu(tp->counters.rx_packets);
1710         data[2] = le64_to_cpu(tp->counters.tx_errors);
1711         data[3] = le32_to_cpu(tp->counters.rx_errors);
1712         data[4] = le16_to_cpu(tp->counters.rx_missed);
1713         data[5] = le16_to_cpu(tp->counters.align_errors);
1714         data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1715         data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1716         data[8] = le64_to_cpu(tp->counters.rx_unicast);
1717         data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1718         data[10] = le32_to_cpu(tp->counters.rx_multicast);
1719         data[11] = le16_to_cpu(tp->counters.tx_aborted);
1720         data[12] = le16_to_cpu(tp->counters.tx_underun);
1721 }
1722
1723 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1724 {
1725         switch(stringset) {
1726         case ETH_SS_STATS:
1727                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1728                 break;
1729         }
1730 }
1731
1732 static const struct ethtool_ops rtl8169_ethtool_ops = {
1733         .get_drvinfo            = rtl8169_get_drvinfo,
1734         .get_regs_len           = rtl8169_get_regs_len,
1735         .get_link               = ethtool_op_get_link,
1736         .get_settings           = rtl8169_get_settings,
1737         .set_settings           = rtl8169_set_settings,
1738         .get_msglevel           = rtl8169_get_msglevel,
1739         .set_msglevel           = rtl8169_set_msglevel,
1740         .get_regs               = rtl8169_get_regs,
1741         .get_wol                = rtl8169_get_wol,
1742         .set_wol                = rtl8169_set_wol,
1743         .get_strings            = rtl8169_get_strings,
1744         .get_sset_count         = rtl8169_get_sset_count,
1745         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
1746 };
1747
1748 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1749                                     struct net_device *dev, u8 default_version)
1750 {
1751         void __iomem *ioaddr = tp->mmio_addr;
1752         /*
1753          * The driver currently handles the 8168Bf and the 8168Be identically
1754          * but they can be identified more specifically through the test below
1755          * if needed:
1756          *
1757          * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1758          *
1759          * Same thing for the 8101Eb and the 8101Ec:
1760          *
1761          * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1762          */
1763         static const struct rtl_mac_info {
1764                 u32 mask;
1765                 u32 val;
1766                 int mac_version;
1767         } mac_info[] = {
1768                 /* 8168F family. */
1769                 { 0x7cf00000, 0x48100000,       RTL_GIGA_MAC_VER_36 },
1770                 { 0x7cf00000, 0x48000000,       RTL_GIGA_MAC_VER_35 },
1771
1772                 /* 8168E family. */
1773                 { 0x7c800000, 0x2c800000,       RTL_GIGA_MAC_VER_34 },
1774                 { 0x7cf00000, 0x2c200000,       RTL_GIGA_MAC_VER_33 },
1775                 { 0x7cf00000, 0x2c100000,       RTL_GIGA_MAC_VER_32 },
1776                 { 0x7c800000, 0x2c000000,       RTL_GIGA_MAC_VER_33 },
1777
1778                 /* 8168D family. */
1779                 { 0x7cf00000, 0x28300000,       RTL_GIGA_MAC_VER_26 },
1780                 { 0x7cf00000, 0x28100000,       RTL_GIGA_MAC_VER_25 },
1781                 { 0x7c800000, 0x28000000,       RTL_GIGA_MAC_VER_26 },
1782
1783                 /* 8168DP family. */
1784                 { 0x7cf00000, 0x28800000,       RTL_GIGA_MAC_VER_27 },
1785                 { 0x7cf00000, 0x28a00000,       RTL_GIGA_MAC_VER_28 },
1786                 { 0x7cf00000, 0x28b00000,       RTL_GIGA_MAC_VER_31 },
1787
1788                 /* 8168C family. */
1789                 { 0x7cf00000, 0x3cb00000,       RTL_GIGA_MAC_VER_24 },
1790                 { 0x7cf00000, 0x3c900000,       RTL_GIGA_MAC_VER_23 },
1791                 { 0x7cf00000, 0x3c800000,       RTL_GIGA_MAC_VER_18 },
1792                 { 0x7c800000, 0x3c800000,       RTL_GIGA_MAC_VER_24 },
1793                 { 0x7cf00000, 0x3c000000,       RTL_GIGA_MAC_VER_19 },
1794                 { 0x7cf00000, 0x3c200000,       RTL_GIGA_MAC_VER_20 },
1795                 { 0x7cf00000, 0x3c300000,       RTL_GIGA_MAC_VER_21 },
1796                 { 0x7cf00000, 0x3c400000,       RTL_GIGA_MAC_VER_22 },
1797                 { 0x7c800000, 0x3c000000,       RTL_GIGA_MAC_VER_22 },
1798
1799                 /* 8168B family. */
1800                 { 0x7cf00000, 0x38000000,       RTL_GIGA_MAC_VER_12 },
1801                 { 0x7cf00000, 0x38500000,       RTL_GIGA_MAC_VER_17 },
1802                 { 0x7c800000, 0x38000000,       RTL_GIGA_MAC_VER_17 },
1803                 { 0x7c800000, 0x30000000,       RTL_GIGA_MAC_VER_11 },
1804
1805                 /* 8101 family. */
1806                 { 0x7cf00000, 0x40b00000,       RTL_GIGA_MAC_VER_30 },
1807                 { 0x7cf00000, 0x40a00000,       RTL_GIGA_MAC_VER_30 },
1808                 { 0x7cf00000, 0x40900000,       RTL_GIGA_MAC_VER_29 },
1809                 { 0x7c800000, 0x40800000,       RTL_GIGA_MAC_VER_30 },
1810                 { 0x7cf00000, 0x34a00000,       RTL_GIGA_MAC_VER_09 },
1811                 { 0x7cf00000, 0x24a00000,       RTL_GIGA_MAC_VER_09 },
1812                 { 0x7cf00000, 0x34900000,       RTL_GIGA_MAC_VER_08 },
1813                 { 0x7cf00000, 0x24900000,       RTL_GIGA_MAC_VER_08 },
1814                 { 0x7cf00000, 0x34800000,       RTL_GIGA_MAC_VER_07 },
1815                 { 0x7cf00000, 0x24800000,       RTL_GIGA_MAC_VER_07 },
1816                 { 0x7cf00000, 0x34000000,       RTL_GIGA_MAC_VER_13 },
1817                 { 0x7cf00000, 0x34300000,       RTL_GIGA_MAC_VER_10 },
1818                 { 0x7cf00000, 0x34200000,       RTL_GIGA_MAC_VER_16 },
1819                 { 0x7c800000, 0x34800000,       RTL_GIGA_MAC_VER_09 },
1820                 { 0x7c800000, 0x24800000,       RTL_GIGA_MAC_VER_09 },
1821                 { 0x7c800000, 0x34000000,       RTL_GIGA_MAC_VER_16 },
1822                 /* FIXME: where did these entries come from ? -- FR */
1823                 { 0xfc800000, 0x38800000,       RTL_GIGA_MAC_VER_15 },
1824                 { 0xfc800000, 0x30800000,       RTL_GIGA_MAC_VER_14 },
1825
1826                 /* 8110 family. */
1827                 { 0xfc800000, 0x98000000,       RTL_GIGA_MAC_VER_06 },
1828                 { 0xfc800000, 0x18000000,       RTL_GIGA_MAC_VER_05 },
1829                 { 0xfc800000, 0x10000000,       RTL_GIGA_MAC_VER_04 },
1830                 { 0xfc800000, 0x04000000,       RTL_GIGA_MAC_VER_03 },
1831                 { 0xfc800000, 0x00800000,       RTL_GIGA_MAC_VER_02 },
1832                 { 0xfc800000, 0x00000000,       RTL_GIGA_MAC_VER_01 },
1833
1834                 /* Catch-all */
1835                 { 0x00000000, 0x00000000,       RTL_GIGA_MAC_NONE   }
1836         };
1837         const struct rtl_mac_info *p = mac_info;
1838         u32 reg;
1839
1840         reg = RTL_R32(TxConfig);
1841         while ((reg & p->mask) != p->val)
1842                 p++;
1843         tp->mac_version = p->mac_version;
1844
1845         if (tp->mac_version == RTL_GIGA_MAC_NONE) {
1846                 netif_notice(tp, probe, dev,
1847                              "unknown MAC, using family default\n");
1848                 tp->mac_version = default_version;
1849         }
1850 }
1851
1852 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1853 {
1854         dprintk("mac_version = 0x%02x\n", tp->mac_version);
1855 }
1856
1857 struct phy_reg {
1858         u16 reg;
1859         u16 val;
1860 };
1861
1862 static void rtl_writephy_batch(struct rtl8169_private *tp,
1863                                const struct phy_reg *regs, int len)
1864 {
1865         while (len-- > 0) {
1866                 rtl_writephy(tp, regs->reg, regs->val);
1867                 regs++;
1868         }
1869 }
1870
1871 #define PHY_READ                0x00000000
1872 #define PHY_DATA_OR             0x10000000
1873 #define PHY_DATA_AND            0x20000000
1874 #define PHY_BJMPN               0x30000000
1875 #define PHY_READ_EFUSE          0x40000000
1876 #define PHY_READ_MAC_BYTE       0x50000000
1877 #define PHY_WRITE_MAC_BYTE      0x60000000
1878 #define PHY_CLEAR_READCOUNT     0x70000000
1879 #define PHY_WRITE               0x80000000
1880 #define PHY_READCOUNT_EQ_SKIP   0x90000000
1881 #define PHY_COMP_EQ_SKIPN       0xa0000000
1882 #define PHY_COMP_NEQ_SKIPN      0xb0000000
1883 #define PHY_WRITE_PREVIOUS      0xc0000000
1884 #define PHY_SKIPN               0xd0000000
1885 #define PHY_DELAY_MS            0xe0000000
1886 #define PHY_WRITE_ERI_WORD      0xf0000000
1887
1888 struct fw_info {
1889         u32     magic;
1890         char    version[RTL_VER_SIZE];
1891         __le32  fw_start;
1892         __le32  fw_len;
1893         u8      chksum;
1894 } __packed;
1895
1896 #define FW_OPCODE_SIZE  sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
1897
1898 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
1899 {
1900         const struct firmware *fw = rtl_fw->fw;
1901         struct fw_info *fw_info = (struct fw_info *)fw->data;
1902         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
1903         char *version = rtl_fw->version;
1904         bool rc = false;
1905
1906         if (fw->size < FW_OPCODE_SIZE)
1907                 goto out;
1908
1909         if (!fw_info->magic) {
1910                 size_t i, size, start;
1911                 u8 checksum = 0;
1912
1913                 if (fw->size < sizeof(*fw_info))
1914                         goto out;
1915
1916                 for (i = 0; i < fw->size; i++)
1917                         checksum += fw->data[i];
1918                 if (checksum != 0)
1919                         goto out;
1920
1921                 start = le32_to_cpu(fw_info->fw_start);
1922                 if (start > fw->size)
1923                         goto out;
1924
1925                 size = le32_to_cpu(fw_info->fw_len);
1926                 if (size > (fw->size - start) / FW_OPCODE_SIZE)
1927                         goto out;
1928
1929                 memcpy(version, fw_info->version, RTL_VER_SIZE);
1930
1931                 pa->code = (__le32 *)(fw->data + start);
1932                 pa->size = size;
1933         } else {
1934                 if (fw->size % FW_OPCODE_SIZE)
1935                         goto out;
1936
1937                 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
1938
1939                 pa->code = (__le32 *)fw->data;
1940                 pa->size = fw->size / FW_OPCODE_SIZE;
1941         }
1942         version[RTL_VER_SIZE - 1] = 0;
1943
1944         rc = true;
1945 out:
1946         return rc;
1947 }
1948
1949 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
1950                            struct rtl_fw_phy_action *pa)
1951 {
1952         bool rc = false;
1953         size_t index;
1954
1955         for (index = 0; index < pa->size; index++) {
1956                 u32 action = le32_to_cpu(pa->code[index]);
1957                 u32 regno = (action & 0x0fff0000) >> 16;
1958
1959                 switch(action & 0xf0000000) {
1960                 case PHY_READ:
1961                 case PHY_DATA_OR:
1962                 case PHY_DATA_AND:
1963                 case PHY_READ_EFUSE:
1964                 case PHY_CLEAR_READCOUNT:
1965                 case PHY_WRITE:
1966                 case PHY_WRITE_PREVIOUS:
1967                 case PHY_DELAY_MS:
1968                         break;
1969
1970                 case PHY_BJMPN:
1971                         if (regno > index) {
1972                                 netif_err(tp, ifup, tp->dev,
1973                                           "Out of range of firmware\n");
1974                                 goto out;
1975                         }
1976                         break;
1977                 case PHY_READCOUNT_EQ_SKIP:
1978                         if (index + 2 >= pa->size) {
1979                                 netif_err(tp, ifup, tp->dev,
1980                                           "Out of range of firmware\n");
1981                                 goto out;
1982                         }
1983                         break;
1984                 case PHY_COMP_EQ_SKIPN:
1985                 case PHY_COMP_NEQ_SKIPN:
1986                 case PHY_SKIPN:
1987                         if (index + 1 + regno >= pa->size) {
1988                                 netif_err(tp, ifup, tp->dev,
1989                                           "Out of range of firmware\n");
1990                                 goto out;
1991                         }
1992                         break;
1993
1994                 case PHY_READ_MAC_BYTE:
1995                 case PHY_WRITE_MAC_BYTE:
1996                 case PHY_WRITE_ERI_WORD:
1997                 default:
1998                         netif_err(tp, ifup, tp->dev,
1999                                   "Invalid action 0x%08x\n", action);
2000                         goto out;
2001                 }
2002         }
2003         rc = true;
2004 out:
2005         return rc;
2006 }
2007
2008 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2009 {
2010         struct net_device *dev = tp->dev;
2011         int rc = -EINVAL;
2012
2013         if (!rtl_fw_format_ok(tp, rtl_fw)) {
2014                 netif_err(tp, ifup, dev, "invalid firwmare\n");
2015                 goto out;
2016         }
2017
2018         if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2019                 rc = 0;
2020 out:
2021         return rc;
2022 }
2023
2024 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2025 {
2026         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2027         u32 predata, count;
2028         size_t index;
2029
2030         predata = count = 0;
2031
2032         for (index = 0; index < pa->size; ) {
2033                 u32 action = le32_to_cpu(pa->code[index]);
2034                 u32 data = action & 0x0000ffff;
2035                 u32 regno = (action & 0x0fff0000) >> 16;
2036
2037                 if (!action)
2038                         break;
2039
2040                 switch(action & 0xf0000000) {
2041                 case PHY_READ:
2042                         predata = rtl_readphy(tp, regno);
2043                         count++;
2044                         index++;
2045                         break;
2046                 case PHY_DATA_OR:
2047                         predata |= data;
2048                         index++;
2049                         break;
2050                 case PHY_DATA_AND:
2051                         predata &= data;
2052                         index++;
2053                         break;
2054                 case PHY_BJMPN:
2055                         index -= regno;
2056                         break;
2057                 case PHY_READ_EFUSE:
2058                         predata = rtl8168d_efuse_read(tp->mmio_addr, regno);
2059                         index++;
2060                         break;
2061                 case PHY_CLEAR_READCOUNT:
2062                         count = 0;
2063                         index++;
2064                         break;
2065                 case PHY_WRITE:
2066                         rtl_writephy(tp, regno, data);
2067                         index++;
2068                         break;
2069                 case PHY_READCOUNT_EQ_SKIP:
2070                         index += (count == data) ? 2 : 1;
2071                         break;
2072                 case PHY_COMP_EQ_SKIPN:
2073                         if (predata == data)
2074                                 index += regno;
2075                         index++;
2076                         break;
2077                 case PHY_COMP_NEQ_SKIPN:
2078                         if (predata != data)
2079                                 index += regno;
2080                         index++;
2081                         break;
2082                 case PHY_WRITE_PREVIOUS:
2083                         rtl_writephy(tp, regno, predata);
2084                         index++;
2085                         break;
2086                 case PHY_SKIPN:
2087                         index += regno + 1;
2088                         break;
2089                 case PHY_DELAY_MS:
2090                         mdelay(data);
2091                         index++;
2092                         break;
2093
2094                 case PHY_READ_MAC_BYTE:
2095                 case PHY_WRITE_MAC_BYTE:
2096                 case PHY_WRITE_ERI_WORD:
2097                 default:
2098                         BUG();
2099                 }
2100         }
2101 }
2102
2103 static void rtl_release_firmware(struct rtl8169_private *tp)
2104 {
2105         if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2106                 release_firmware(tp->rtl_fw->fw);
2107                 kfree(tp->rtl_fw);
2108         }
2109         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
2110 }
2111
2112 static void rtl_apply_firmware(struct rtl8169_private *tp)
2113 {
2114         struct rtl_fw *rtl_fw = tp->rtl_fw;
2115
2116         /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2117         if (!IS_ERR_OR_NULL(rtl_fw))
2118                 rtl_phy_write_fw(tp, rtl_fw);
2119 }
2120
2121 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2122 {
2123         if (rtl_readphy(tp, reg) != val)
2124                 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2125         else
2126                 rtl_apply_firmware(tp);
2127 }
2128
2129 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2130 {
2131         static const struct phy_reg phy_reg_init[] = {
2132                 { 0x1f, 0x0001 },
2133                 { 0x06, 0x006e },
2134                 { 0x08, 0x0708 },
2135                 { 0x15, 0x4000 },
2136                 { 0x18, 0x65c7 },
2137
2138                 { 0x1f, 0x0001 },
2139                 { 0x03, 0x00a1 },
2140                 { 0x02, 0x0008 },
2141                 { 0x01, 0x0120 },
2142                 { 0x00, 0x1000 },
2143                 { 0x04, 0x0800 },
2144                 { 0x04, 0x0000 },
2145
2146                 { 0x03, 0xff41 },
2147                 { 0x02, 0xdf60 },
2148                 { 0x01, 0x0140 },
2149                 { 0x00, 0x0077 },
2150                 { 0x04, 0x7800 },
2151                 { 0x04, 0x7000 },
2152
2153                 { 0x03, 0x802f },
2154                 { 0x02, 0x4f02 },
2155                 { 0x01, 0x0409 },
2156                 { 0x00, 0xf0f9 },
2157                 { 0x04, 0x9800 },
2158                 { 0x04, 0x9000 },
2159
2160                 { 0x03, 0xdf01 },
2161                 { 0x02, 0xdf20 },
2162                 { 0x01, 0xff95 },
2163                 { 0x00, 0xba00 },
2164                 { 0x04, 0xa800 },
2165                 { 0x04, 0xa000 },
2166
2167                 { 0x03, 0xff41 },
2168                 { 0x02, 0xdf20 },
2169                 { 0x01, 0x0140 },
2170                 { 0x00, 0x00bb },
2171                 { 0x04, 0xb800 },
2172                 { 0x04, 0xb000 },
2173
2174                 { 0x03, 0xdf41 },
2175                 { 0x02, 0xdc60 },
2176                 { 0x01, 0x6340 },
2177                 { 0x00, 0x007d },
2178                 { 0x04, 0xd800 },
2179                 { 0x04, 0xd000 },
2180
2181                 { 0x03, 0xdf01 },
2182                 { 0x02, 0xdf20 },
2183                 { 0x01, 0x100a },
2184                 { 0x00, 0xa0ff },
2185                 { 0x04, 0xf800 },
2186                 { 0x04, 0xf000 },
2187
2188                 { 0x1f, 0x0000 },
2189                 { 0x0b, 0x0000 },
2190                 { 0x00, 0x9200 }
2191         };
2192
2193         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2194 }
2195
2196 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2197 {
2198         static const struct phy_reg phy_reg_init[] = {
2199                 { 0x1f, 0x0002 },
2200                 { 0x01, 0x90d0 },
2201                 { 0x1f, 0x0000 }
2202         };
2203
2204         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2205 }
2206
2207 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2208 {
2209         struct pci_dev *pdev = tp->pci_dev;
2210
2211         if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2212             (pdev->subsystem_device != 0xe000))
2213                 return;
2214
2215         rtl_writephy(tp, 0x1f, 0x0001);
2216         rtl_writephy(tp, 0x10, 0xf01b);
2217         rtl_writephy(tp, 0x1f, 0x0000);
2218 }
2219
2220 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2221 {
2222         static const struct phy_reg phy_reg_init[] = {
2223                 { 0x1f, 0x0001 },
2224                 { 0x04, 0x0000 },
2225                 { 0x03, 0x00a1 },
2226                 { 0x02, 0x0008 },
2227                 { 0x01, 0x0120 },
2228                 { 0x00, 0x1000 },
2229                 { 0x04, 0x0800 },
2230                 { 0x04, 0x9000 },
2231                 { 0x03, 0x802f },
2232                 { 0x02, 0x4f02 },
2233                 { 0x01, 0x0409 },
2234                 { 0x00, 0xf099 },
2235                 { 0x04, 0x9800 },
2236                 { 0x04, 0xa000 },
2237                 { 0x03, 0xdf01 },
2238                 { 0x02, 0xdf20 },
2239                 { 0x01, 0xff95 },
2240                 { 0x00, 0xba00 },
2241                 { 0x04, 0xa800 },
2242                 { 0x04, 0xf000 },
2243                 { 0x03, 0xdf01 },
2244                 { 0x02, 0xdf20 },
2245                 { 0x01, 0x101a },
2246                 { 0x00, 0xa0ff },
2247                 { 0x04, 0xf800 },
2248                 { 0x04, 0x0000 },
2249                 { 0x1f, 0x0000 },
2250
2251                 { 0x1f, 0x0001 },
2252                 { 0x10, 0xf41b },
2253                 { 0x14, 0xfb54 },
2254                 { 0x18, 0xf5c7 },
2255                 { 0x1f, 0x0000 },
2256
2257                 { 0x1f, 0x0001 },
2258                 { 0x17, 0x0cc0 },
2259                 { 0x1f, 0x0000 }
2260         };
2261
2262         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2263
2264         rtl8169scd_hw_phy_config_quirk(tp);
2265 }
2266
2267 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2268 {
2269         static const struct phy_reg phy_reg_init[] = {
2270                 { 0x1f, 0x0001 },
2271                 { 0x04, 0x0000 },
2272                 { 0x03, 0x00a1 },
2273                 { 0x02, 0x0008 },
2274                 { 0x01, 0x0120 },
2275                 { 0x00, 0x1000 },
2276                 { 0x04, 0x0800 },
2277                 { 0x04, 0x9000 },
2278                 { 0x03, 0x802f },
2279                 { 0x02, 0x4f02 },
2280                 { 0x01, 0x0409 },
2281                 { 0x00, 0xf099 },
2282                 { 0x04, 0x9800 },
2283                 { 0x04, 0xa000 },
2284                 { 0x03, 0xdf01 },
2285                 { 0x02, 0xdf20 },
2286                 { 0x01, 0xff95 },
2287                 { 0x00, 0xba00 },
2288                 { 0x04, 0xa800 },
2289                 { 0x04, 0xf000 },
2290                 { 0x03, 0xdf01 },
2291                 { 0x02, 0xdf20 },
2292                 { 0x01, 0x101a },
2293                 { 0x00, 0xa0ff },
2294                 { 0x04, 0xf800 },
2295                 { 0x04, 0x0000 },
2296                 { 0x1f, 0x0000 },
2297
2298                 { 0x1f, 0x0001 },
2299                 { 0x0b, 0x8480 },
2300                 { 0x1f, 0x0000 },
2301
2302                 { 0x1f, 0x0001 },
2303                 { 0x18, 0x67c7 },
2304                 { 0x04, 0x2000 },
2305                 { 0x03, 0x002f },
2306                 { 0x02, 0x4360 },
2307                 { 0x01, 0x0109 },
2308                 { 0x00, 0x3022 },
2309                 { 0x04, 0x2800 },
2310                 { 0x1f, 0x0000 },
2311
2312                 { 0x1f, 0x0001 },
2313                 { 0x17, 0x0cc0 },
2314                 { 0x1f, 0x0000 }
2315         };
2316
2317         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2318 }
2319
2320 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2321 {
2322         static const struct phy_reg phy_reg_init[] = {
2323                 { 0x10, 0xf41b },
2324                 { 0x1f, 0x0000 }
2325         };
2326
2327         rtl_writephy(tp, 0x1f, 0x0001);
2328         rtl_patchphy(tp, 0x16, 1 << 0);
2329
2330         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2331 }
2332
2333 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2334 {
2335         static const struct phy_reg phy_reg_init[] = {
2336                 { 0x1f, 0x0001 },
2337                 { 0x10, 0xf41b },
2338                 { 0x1f, 0x0000 }
2339         };
2340
2341         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2342 }
2343
2344 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2345 {
2346         static const struct phy_reg phy_reg_init[] = {
2347                 { 0x1f, 0x0000 },
2348                 { 0x1d, 0x0f00 },
2349                 { 0x1f, 0x0002 },
2350                 { 0x0c, 0x1ec8 },
2351                 { 0x1f, 0x0000 }
2352         };
2353
2354         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2355 }
2356
2357 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2358 {
2359         static const struct phy_reg phy_reg_init[] = {
2360                 { 0x1f, 0x0001 },
2361                 { 0x1d, 0x3d98 },
2362                 { 0x1f, 0x0000 }
2363         };
2364
2365         rtl_writephy(tp, 0x1f, 0x0000);
2366         rtl_patchphy(tp, 0x14, 1 << 5);
2367         rtl_patchphy(tp, 0x0d, 1 << 5);
2368
2369         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2370 }
2371
2372 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2373 {
2374         static const struct phy_reg phy_reg_init[] = {
2375                 { 0x1f, 0x0001 },
2376                 { 0x12, 0x2300 },
2377                 { 0x1f, 0x0002 },
2378                 { 0x00, 0x88d4 },
2379                 { 0x01, 0x82b1 },
2380                 { 0x03, 0x7002 },
2381                 { 0x08, 0x9e30 },
2382                 { 0x09, 0x01f0 },
2383                 { 0x0a, 0x5500 },
2384                 { 0x0c, 0x00c8 },
2385                 { 0x1f, 0x0003 },
2386                 { 0x12, 0xc096 },
2387                 { 0x16, 0x000a },
2388                 { 0x1f, 0x0000 },
2389                 { 0x1f, 0x0000 },
2390                 { 0x09, 0x2000 },
2391                 { 0x09, 0x0000 }
2392         };
2393
2394         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2395
2396         rtl_patchphy(tp, 0x14, 1 << 5);
2397         rtl_patchphy(tp, 0x0d, 1 << 5);
2398         rtl_writephy(tp, 0x1f, 0x0000);
2399 }
2400
2401 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2402 {
2403         static const struct phy_reg phy_reg_init[] = {
2404                 { 0x1f, 0x0001 },
2405                 { 0x12, 0x2300 },
2406                 { 0x03, 0x802f },
2407                 { 0x02, 0x4f02 },
2408                 { 0x01, 0x0409 },
2409                 { 0x00, 0xf099 },
2410                 { 0x04, 0x9800 },
2411                 { 0x04, 0x9000 },
2412                 { 0x1d, 0x3d98 },
2413                 { 0x1f, 0x0002 },
2414                 { 0x0c, 0x7eb8 },
2415                 { 0x06, 0x0761 },
2416                 { 0x1f, 0x0003 },
2417                 { 0x16, 0x0f0a },
2418                 { 0x1f, 0x0000 }
2419         };
2420
2421         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2422
2423         rtl_patchphy(tp, 0x16, 1 << 0);
2424         rtl_patchphy(tp, 0x14, 1 << 5);
2425         rtl_patchphy(tp, 0x0d, 1 << 5);
2426         rtl_writephy(tp, 0x1f, 0x0000);
2427 }
2428
2429 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2430 {
2431         static const struct phy_reg phy_reg_init[] = {
2432                 { 0x1f, 0x0001 },
2433                 { 0x12, 0x2300 },
2434                 { 0x1d, 0x3d98 },
2435                 { 0x1f, 0x0002 },
2436                 { 0x0c, 0x7eb8 },
2437                 { 0x06, 0x5461 },
2438                 { 0x1f, 0x0003 },
2439                 { 0x16, 0x0f0a },
2440                 { 0x1f, 0x0000 }
2441         };
2442
2443         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2444
2445         rtl_patchphy(tp, 0x16, 1 << 0);
2446         rtl_patchphy(tp, 0x14, 1 << 5);
2447         rtl_patchphy(tp, 0x0d, 1 << 5);
2448         rtl_writephy(tp, 0x1f, 0x0000);
2449 }
2450
2451 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2452 {
2453         rtl8168c_3_hw_phy_config(tp);
2454 }
2455
2456 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2457 {
2458         static const struct phy_reg phy_reg_init_0[] = {
2459                 /* Channel Estimation */
2460                 { 0x1f, 0x0001 },
2461                 { 0x06, 0x4064 },
2462                 { 0x07, 0x2863 },
2463                 { 0x08, 0x059c },
2464                 { 0x09, 0x26b4 },
2465                 { 0x0a, 0x6a19 },
2466                 { 0x0b, 0xdcc8 },
2467                 { 0x10, 0xf06d },
2468                 { 0x14, 0x7f68 },
2469                 { 0x18, 0x7fd9 },
2470                 { 0x1c, 0xf0ff },
2471                 { 0x1d, 0x3d9c },
2472                 { 0x1f, 0x0003 },
2473                 { 0x12, 0xf49f },
2474                 { 0x13, 0x070b },
2475                 { 0x1a, 0x05ad },
2476                 { 0x14, 0x94c0 },
2477
2478                 /*
2479                  * Tx Error Issue
2480                  * Enhance line driver power
2481                  */
2482                 { 0x1f, 0x0002 },
2483                 { 0x06, 0x5561 },
2484                 { 0x1f, 0x0005 },
2485                 { 0x05, 0x8332 },
2486                 { 0x06, 0x5561 },
2487
2488                 /*
2489                  * Can not link to 1Gbps with bad cable
2490                  * Decrease SNR threshold form 21.07dB to 19.04dB
2491                  */
2492                 { 0x1f, 0x0001 },
2493                 { 0x17, 0x0cc0 },
2494
2495                 { 0x1f, 0x0000 },
2496                 { 0x0d, 0xf880 }
2497         };
2498         void __iomem *ioaddr = tp->mmio_addr;
2499
2500         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2501
2502         /*
2503          * Rx Error Issue
2504          * Fine Tune Switching regulator parameter
2505          */
2506         rtl_writephy(tp, 0x1f, 0x0002);
2507         rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2508         rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
2509
2510         if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2511                 static const struct phy_reg phy_reg_init[] = {
2512                         { 0x1f, 0x0002 },
2513                         { 0x05, 0x669a },
2514                         { 0x1f, 0x0005 },
2515                         { 0x05, 0x8330 },
2516                         { 0x06, 0x669a },
2517                         { 0x1f, 0x0002 }
2518                 };
2519                 int val;
2520
2521                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2522
2523                 val = rtl_readphy(tp, 0x0d);
2524
2525                 if ((val & 0x00ff) != 0x006c) {
2526                         static const u32 set[] = {
2527                                 0x0065, 0x0066, 0x0067, 0x0068,
2528                                 0x0069, 0x006a, 0x006b, 0x006c
2529                         };
2530                         int i;
2531
2532                         rtl_writephy(tp, 0x1f, 0x0002);
2533
2534                         val &= 0xff00;
2535                         for (i = 0; i < ARRAY_SIZE(set); i++)
2536                                 rtl_writephy(tp, 0x0d, val | set[i]);
2537                 }
2538         } else {
2539                 static const struct phy_reg phy_reg_init[] = {
2540                         { 0x1f, 0x0002 },
2541                         { 0x05, 0x6662 },
2542                         { 0x1f, 0x0005 },
2543                         { 0x05, 0x8330 },
2544                         { 0x06, 0x6662 }
2545                 };
2546
2547                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2548         }
2549
2550         /* RSET couple improve */
2551         rtl_writephy(tp, 0x1f, 0x0002);
2552         rtl_patchphy(tp, 0x0d, 0x0300);
2553         rtl_patchphy(tp, 0x0f, 0x0010);
2554
2555         /* Fine tune PLL performance */
2556         rtl_writephy(tp, 0x1f, 0x0002);
2557         rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2558         rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2559
2560         rtl_writephy(tp, 0x1f, 0x0005);
2561         rtl_writephy(tp, 0x05, 0x001b);
2562
2563         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2564
2565         rtl_writephy(tp, 0x1f, 0x0000);
2566 }
2567
2568 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2569 {
2570         static const struct phy_reg phy_reg_init_0[] = {
2571                 /* Channel Estimation */
2572                 { 0x1f, 0x0001 },
2573                 { 0x06, 0x4064 },
2574                 { 0x07, 0x2863 },
2575                 { 0x08, 0x059c },
2576                 { 0x09, 0x26b4 },
2577                 { 0x0a, 0x6a19 },
2578                 { 0x0b, 0xdcc8 },
2579                 { 0x10, 0xf06d },
2580                 { 0x14, 0x7f68 },
2581                 { 0x18, 0x7fd9 },
2582                 { 0x1c, 0xf0ff },
2583                 { 0x1d, 0x3d9c },
2584                 { 0x1f, 0x0003 },
2585                 { 0x12, 0xf49f },
2586                 { 0x13, 0x070b },
2587                 { 0x1a, 0x05ad },
2588                 { 0x14, 0x94c0 },
2589
2590                 /*
2591                  * Tx Error Issue
2592                  * Enhance line driver power
2593                  */
2594                 { 0x1f, 0x0002 },
2595                 { 0x06, 0x5561 },
2596                 { 0x1f, 0x0005 },
2597                 { 0x05, 0x8332 },
2598                 { 0x06, 0x5561 },
2599
2600                 /*
2601                  * Can not link to 1Gbps with bad cable
2602                  * Decrease SNR threshold form 21.07dB to 19.04dB
2603                  */
2604                 { 0x1f, 0x0001 },
2605                 { 0x17, 0x0cc0 },
2606
2607                 { 0x1f, 0x0000 },
2608                 { 0x0d, 0xf880 }
2609         };
2610         void __iomem *ioaddr = tp->mmio_addr;
2611
2612         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2613
2614         if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2615                 static const struct phy_reg phy_reg_init[] = {
2616                         { 0x1f, 0x0002 },
2617                         { 0x05, 0x669a },
2618                         { 0x1f, 0x0005 },
2619                         { 0x05, 0x8330 },
2620                         { 0x06, 0x669a },
2621
2622                         { 0x1f, 0x0002 }
2623                 };
2624                 int val;
2625
2626                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2627
2628                 val = rtl_readphy(tp, 0x0d);
2629                 if ((val & 0x00ff) != 0x006c) {
2630                         static const u32 set[] = {
2631                                 0x0065, 0x0066, 0x0067, 0x0068,
2632                                 0x0069, 0x006a, 0x006b, 0x006c
2633                         };
2634                         int i;
2635
2636                         rtl_writephy(tp, 0x1f, 0x0002);
2637
2638                         val &= 0xff00;
2639                         for (i = 0; i < ARRAY_SIZE(set); i++)
2640                                 rtl_writephy(tp, 0x0d, val | set[i]);
2641                 }
2642         } else {
2643                 static const struct phy_reg phy_reg_init[] = {
2644                         { 0x1f, 0x0002 },
2645                         { 0x05, 0x2642 },
2646                         { 0x1f, 0x0005 },
2647                         { 0x05, 0x8330 },
2648                         { 0x06, 0x2642 }
2649                 };
2650
2651                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2652         }
2653
2654         /* Fine tune PLL performance */
2655         rtl_writephy(tp, 0x1f, 0x0002);
2656         rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2657         rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2658
2659         /* Switching regulator Slew rate */
2660         rtl_writephy(tp, 0x1f, 0x0002);
2661         rtl_patchphy(tp, 0x0f, 0x0017);
2662
2663         rtl_writephy(tp, 0x1f, 0x0005);
2664         rtl_writephy(tp, 0x05, 0x001b);
2665
2666         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
2667
2668         rtl_writephy(tp, 0x1f, 0x0000);
2669 }
2670
2671 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
2672 {
2673         static const struct phy_reg phy_reg_init[] = {
2674                 { 0x1f, 0x0002 },
2675                 { 0x10, 0x0008 },
2676                 { 0x0d, 0x006c },
2677
2678                 { 0x1f, 0x0000 },
2679                 { 0x0d, 0xf880 },
2680
2681                 { 0x1f, 0x0001 },
2682                 { 0x17, 0x0cc0 },
2683
2684                 { 0x1f, 0x0001 },
2685                 { 0x0b, 0xa4d8 },
2686                 { 0x09, 0x281c },
2687                 { 0x07, 0x2883 },
2688                 { 0x0a, 0x6b35 },
2689                 { 0x1d, 0x3da4 },
2690                 { 0x1c, 0xeffd },
2691                 { 0x14, 0x7f52 },
2692                 { 0x18, 0x7fc6 },
2693                 { 0x08, 0x0601 },
2694                 { 0x06, 0x4063 },
2695                 { 0x10, 0xf074 },
2696                 { 0x1f, 0x0003 },
2697                 { 0x13, 0x0789 },
2698                 { 0x12, 0xf4bd },
2699                 { 0x1a, 0x04fd },
2700                 { 0x14, 0x84b0 },
2701                 { 0x1f, 0x0000 },
2702                 { 0x00, 0x9200 },
2703
2704                 { 0x1f, 0x0005 },
2705                 { 0x01, 0x0340 },
2706                 { 0x1f, 0x0001 },
2707                 { 0x04, 0x4000 },
2708                 { 0x03, 0x1d21 },
2709                 { 0x02, 0x0c32 },
2710                 { 0x01, 0x0200 },
2711                 { 0x00, 0x5554 },
2712                 { 0x04, 0x4800 },
2713                 { 0x04, 0x4000 },
2714                 { 0x04, 0xf000 },
2715                 { 0x03, 0xdf01 },
2716                 { 0x02, 0xdf20 },
2717                 { 0x01, 0x101a },
2718                 { 0x00, 0xa0ff },
2719                 { 0x04, 0xf800 },
2720                 { 0x04, 0xf000 },
2721                 { 0x1f, 0x0000 },
2722
2723                 { 0x1f, 0x0007 },
2724                 { 0x1e, 0x0023 },
2725                 { 0x16, 0x0000 },
2726                 { 0x1f, 0x0000 }
2727         };
2728
2729         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2730 }
2731
2732 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2733 {
2734         static const struct phy_reg phy_reg_init[] = {
2735                 { 0x1f, 0x0001 },
2736                 { 0x17, 0x0cc0 },
2737
2738                 { 0x1f, 0x0007 },
2739                 { 0x1e, 0x002d },
2740                 { 0x18, 0x0040 },
2741                 { 0x1f, 0x0000 }
2742         };
2743
2744         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2745         rtl_patchphy(tp, 0x0d, 1 << 5);
2746 }
2747
2748 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
2749 {
2750         static const struct phy_reg phy_reg_init[] = {
2751                 /* Enable Delay cap */
2752                 { 0x1f, 0x0005 },
2753                 { 0x05, 0x8b80 },
2754                 { 0x06, 0xc896 },
2755                 { 0x1f, 0x0000 },
2756
2757                 /* Channel estimation fine tune */
2758                 { 0x1f, 0x0001 },
2759                 { 0x0b, 0x6c20 },
2760                 { 0x07, 0x2872 },
2761                 { 0x1c, 0xefff },
2762                 { 0x1f, 0x0003 },
2763                 { 0x14, 0x6420 },
2764                 { 0x1f, 0x0000 },
2765
2766                 /* Update PFM & 10M TX idle timer */
2767                 { 0x1f, 0x0007 },
2768                 { 0x1e, 0x002f },
2769                 { 0x15, 0x1919 },
2770                 { 0x1f, 0x0000 },
2771
2772                 { 0x1f, 0x0007 },
2773                 { 0x1e, 0x00ac },
2774                 { 0x18, 0x0006 },
2775                 { 0x1f, 0x0000 }
2776         };
2777
2778         rtl_apply_firmware(tp);
2779
2780         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2781
2782         /* DCO enable for 10M IDLE Power */
2783         rtl_writephy(tp, 0x1f, 0x0007);
2784         rtl_writephy(tp, 0x1e, 0x0023);
2785         rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2786         rtl_writephy(tp, 0x1f, 0x0000);
2787
2788         /* For impedance matching */
2789         rtl_writephy(tp, 0x1f, 0x0002);
2790         rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
2791         rtl_writephy(tp, 0x1f, 0x0000);
2792
2793         /* PHY auto speed down */
2794         rtl_writephy(tp, 0x1f, 0x0007);
2795         rtl_writephy(tp, 0x1e, 0x002d);
2796         rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
2797         rtl_writephy(tp, 0x1f, 0x0000);
2798         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2799
2800         rtl_writephy(tp, 0x1f, 0x0005);
2801         rtl_writephy(tp, 0x05, 0x8b86);
2802         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2803         rtl_writephy(tp, 0x1f, 0x0000);
2804
2805         rtl_writephy(tp, 0x1f, 0x0005);
2806         rtl_writephy(tp, 0x05, 0x8b85);
2807         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
2808         rtl_writephy(tp, 0x1f, 0x0007);
2809         rtl_writephy(tp, 0x1e, 0x0020);
2810         rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
2811         rtl_writephy(tp, 0x1f, 0x0006);
2812         rtl_writephy(tp, 0x00, 0x5a00);
2813         rtl_writephy(tp, 0x1f, 0x0000);
2814         rtl_writephy(tp, 0x0d, 0x0007);
2815         rtl_writephy(tp, 0x0e, 0x003c);
2816         rtl_writephy(tp, 0x0d, 0x4007);
2817         rtl_writephy(tp, 0x0e, 0x0000);
2818         rtl_writephy(tp, 0x0d, 0x0000);
2819 }
2820
2821 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
2822 {
2823         static const struct phy_reg phy_reg_init[] = {
2824                 /* Enable Delay cap */
2825                 { 0x1f, 0x0004 },
2826                 { 0x1f, 0x0007 },
2827                 { 0x1e, 0x00ac },
2828                 { 0x18, 0x0006 },
2829                 { 0x1f, 0x0002 },
2830                 { 0x1f, 0x0000 },
2831                 { 0x1f, 0x0000 },
2832
2833                 /* Channel estimation fine tune */
2834                 { 0x1f, 0x0003 },
2835                 { 0x09, 0xa20f },
2836                 { 0x1f, 0x0000 },
2837                 { 0x1f, 0x0000 },
2838
2839                 /* Green Setting */
2840                 { 0x1f, 0x0005 },
2841                 { 0x05, 0x8b5b },
2842                 { 0x06, 0x9222 },
2843                 { 0x05, 0x8b6d },
2844                 { 0x06, 0x8000 },
2845                 { 0x05, 0x8b76 },
2846                 { 0x06, 0x8000 },
2847                 { 0x1f, 0x0000 }
2848         };
2849
2850         rtl_apply_firmware(tp);
2851
2852         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2853
2854         /* For 4-corner performance improve */
2855         rtl_writephy(tp, 0x1f, 0x0005);
2856         rtl_writephy(tp, 0x05, 0x8b80);
2857         rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2858         rtl_writephy(tp, 0x1f, 0x0000);
2859
2860         /* PHY auto speed down */
2861         rtl_writephy(tp, 0x1f, 0x0004);
2862         rtl_writephy(tp, 0x1f, 0x0007);
2863         rtl_writephy(tp, 0x1e, 0x002d);
2864         rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
2865         rtl_writephy(tp, 0x1f, 0x0002);
2866         rtl_writephy(tp, 0x1f, 0x0000);
2867         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2868
2869         /* improve 10M EEE waveform */
2870         rtl_writephy(tp, 0x1f, 0x0005);
2871         rtl_writephy(tp, 0x05, 0x8b86);
2872         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2873         rtl_writephy(tp, 0x1f, 0x0000);
2874
2875         /* Improve 2-pair detection performance */
2876         rtl_writephy(tp, 0x1f, 0x0005);
2877         rtl_writephy(tp, 0x05, 0x8b85);
2878         rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
2879         rtl_writephy(tp, 0x1f, 0x0000);
2880
2881         /* EEE setting */
2882         rtl_w1w0_eri(tp->mmio_addr, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003,
2883                      ERIAR_EXGMAC);
2884         rtl_writephy(tp, 0x1f, 0x0005);
2885         rtl_writephy(tp, 0x05, 0x8b85);
2886         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
2887         rtl_writephy(tp, 0x1f, 0x0004);
2888         rtl_writephy(tp, 0x1f, 0x0007);
2889         rtl_writephy(tp, 0x1e, 0x0020);
2890         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
2891         rtl_writephy(tp, 0x1f, 0x0002);
2892         rtl_writephy(tp, 0x1f, 0x0000);
2893         rtl_writephy(tp, 0x0d, 0x0007);
2894         rtl_writephy(tp, 0x0e, 0x003c);
2895         rtl_writephy(tp, 0x0d, 0x4007);
2896         rtl_writephy(tp, 0x0e, 0x0000);
2897         rtl_writephy(tp, 0x0d, 0x0000);
2898
2899         /* Green feature */
2900         rtl_writephy(tp, 0x1f, 0x0003);
2901         rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
2902         rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
2903         rtl_writephy(tp, 0x1f, 0x0000);
2904 }
2905
2906 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
2907 {
2908         static const struct phy_reg phy_reg_init[] = {
2909                 /* Channel estimation fine tune */
2910                 { 0x1f, 0x0003 },
2911                 { 0x09, 0xa20f },
2912                 { 0x1f, 0x0000 },
2913
2914                 /* Modify green table for giga & fnet */
2915                 { 0x1f, 0x0005 },
2916                 { 0x05, 0x8b55 },
2917                 { 0x06, 0x0000 },
2918                 { 0x05, 0x8b5e },
2919                 { 0x06, 0x0000 },
2920                 { 0x05, 0x8b67 },
2921                 { 0x06, 0x0000 },
2922                 { 0x05, 0x8b70 },
2923                 { 0x06, 0x0000 },
2924                 { 0x1f, 0x0000 },
2925                 { 0x1f, 0x0007 },
2926                 { 0x1e, 0x0078 },
2927                 { 0x17, 0x0000 },
2928                 { 0x19, 0x00fb },
2929                 { 0x1f, 0x0000 },
2930
2931                 /* Modify green table for 10M */
2932                 { 0x1f, 0x0005 },
2933                 { 0x05, 0x8b79 },
2934                 { 0x06, 0xaa00 },
2935                 { 0x1f, 0x0000 },
2936
2937                 /* Disable hiimpedance detection (RTCT) */
2938                 { 0x1f, 0x0003 },
2939                 { 0x01, 0x328a },
2940                 { 0x1f, 0x0000 }
2941         };
2942
2943         rtl_apply_firmware(tp);
2944
2945         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2946
2947         /* For 4-corner performance improve */
2948         rtl_writephy(tp, 0x1f, 0x0005);
2949         rtl_writephy(tp, 0x05, 0x8b80);
2950         rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000);
2951         rtl_writephy(tp, 0x1f, 0x0000);
2952
2953         /* PHY auto speed down */
2954         rtl_writephy(tp, 0x1f, 0x0007);
2955         rtl_writephy(tp, 0x1e, 0x002d);
2956         rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
2957         rtl_writephy(tp, 0x1f, 0x0000);
2958         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2959
2960         /* Improve 10M EEE waveform */
2961         rtl_writephy(tp, 0x1f, 0x0005);
2962         rtl_writephy(tp, 0x05, 0x8b86);
2963         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2964         rtl_writephy(tp, 0x1f, 0x0000);
2965
2966         /* Improve 2-pair detection performance */
2967         rtl_writephy(tp, 0x1f, 0x0005);
2968         rtl_writephy(tp, 0x05, 0x8b85);
2969         rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
2970         rtl_writephy(tp, 0x1f, 0x0000);
2971 }
2972
2973 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
2974 {
2975         rtl_apply_firmware(tp);
2976
2977         /* For 4-corner performance improve */
2978         rtl_writephy(tp, 0x1f, 0x0005);
2979         rtl_writephy(tp, 0x05, 0x8b80);
2980         rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000);
2981         rtl_writephy(tp, 0x1f, 0x0000);
2982
2983         /* PHY auto speed down */
2984         rtl_writephy(tp, 0x1f, 0x0007);
2985         rtl_writephy(tp, 0x1e, 0x002d);
2986         rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
2987         rtl_writephy(tp, 0x1f, 0x0000);
2988         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2989
2990         /* Improve 10M EEE waveform */
2991         rtl_writephy(tp, 0x1f, 0x0005);
2992         rtl_writephy(tp, 0x05, 0x8b86);
2993         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2994         rtl_writephy(tp, 0x1f, 0x0000);
2995 }
2996
2997 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
2998 {
2999         static const struct phy_reg phy_reg_init[] = {
3000                 { 0x1f, 0x0003 },
3001                 { 0x08, 0x441d },
3002                 { 0x01, 0x9100 },
3003                 { 0x1f, 0x0000 }
3004         };
3005
3006         rtl_writephy(tp, 0x1f, 0x0000);
3007         rtl_patchphy(tp, 0x11, 1 << 12);
3008         rtl_patchphy(tp, 0x19, 1 << 13);
3009         rtl_patchphy(tp, 0x10, 1 << 15);
3010
3011         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3012 }
3013
3014 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3015 {
3016         static const struct phy_reg phy_reg_init[] = {
3017                 { 0x1f, 0x0005 },
3018                 { 0x1a, 0x0000 },
3019                 { 0x1f, 0x0000 },
3020
3021                 { 0x1f, 0x0004 },
3022                 { 0x1c, 0x0000 },
3023                 { 0x1f, 0x0000 },
3024
3025                 { 0x1f, 0x0001 },
3026                 { 0x15, 0x7701 },
3027                 { 0x1f, 0x0000 }
3028         };
3029
3030         /* Disable ALDPS before ram code */
3031         rtl_writephy(tp, 0x1f, 0x0000);
3032         rtl_writephy(tp, 0x18, 0x0310);
3033         msleep(100);
3034
3035         rtl_apply_firmware(tp);
3036
3037         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3038 }
3039
3040 static void rtl_hw_phy_config(struct net_device *dev)
3041 {
3042         struct rtl8169_private *tp = netdev_priv(dev);
3043
3044         rtl8169_print_mac_version(tp);
3045
3046         switch (tp->mac_version) {
3047         case RTL_GIGA_MAC_VER_01:
3048                 break;
3049         case RTL_GIGA_MAC_VER_02:
3050         case RTL_GIGA_MAC_VER_03:
3051                 rtl8169s_hw_phy_config(tp);
3052                 break;
3053         case RTL_GIGA_MAC_VER_04:
3054                 rtl8169sb_hw_phy_config(tp);
3055                 break;
3056         case RTL_GIGA_MAC_VER_05:
3057                 rtl8169scd_hw_phy_config(tp);
3058                 break;
3059         case RTL_GIGA_MAC_VER_06:
3060                 rtl8169sce_hw_phy_config(tp);
3061                 break;
3062         case RTL_GIGA_MAC_VER_07:
3063         case RTL_GIGA_MAC_VER_08:
3064         case RTL_GIGA_MAC_VER_09:
3065                 rtl8102e_hw_phy_config(tp);
3066                 break;
3067         case RTL_GIGA_MAC_VER_11:
3068                 rtl8168bb_hw_phy_config(tp);
3069                 break;
3070         case RTL_GIGA_MAC_VER_12:
3071                 rtl8168bef_hw_phy_config(tp);
3072                 break;
3073         case RTL_GIGA_MAC_VER_17:
3074                 rtl8168bef_hw_phy_config(tp);
3075                 break;
3076         case RTL_GIGA_MAC_VER_18:
3077                 rtl8168cp_1_hw_phy_config(tp);
3078                 break;
3079         case RTL_GIGA_MAC_VER_19:
3080                 rtl8168c_1_hw_phy_config(tp);
3081                 break;
3082         case RTL_GIGA_MAC_VER_20:
3083                 rtl8168c_2_hw_phy_config(tp);
3084                 break;
3085         case RTL_GIGA_MAC_VER_21:
3086                 rtl8168c_3_hw_phy_config(tp);
3087                 break;
3088         case RTL_GIGA_MAC_VER_22:
3089                 rtl8168c_4_hw_phy_config(tp);
3090                 break;
3091         case RTL_GIGA_MAC_VER_23:
3092         case RTL_GIGA_MAC_VER_24:
3093                 rtl8168cp_2_hw_phy_config(tp);
3094                 break;
3095         case RTL_GIGA_MAC_VER_25:
3096                 rtl8168d_1_hw_phy_config(tp);
3097                 break;
3098         case RTL_GIGA_MAC_VER_26:
3099                 rtl8168d_2_hw_phy_config(tp);
3100                 break;
3101         case RTL_GIGA_MAC_VER_27:
3102                 rtl8168d_3_hw_phy_config(tp);
3103                 break;
3104         case RTL_GIGA_MAC_VER_28:
3105                 rtl8168d_4_hw_phy_config(tp);
3106                 break;
3107         case RTL_GIGA_MAC_VER_29:
3108         case RTL_GIGA_MAC_VER_30:
3109                 rtl8105e_hw_phy_config(tp);
3110                 break;
3111         case RTL_GIGA_MAC_VER_31:
3112                 /* None. */
3113                 break;
3114         case RTL_GIGA_MAC_VER_32:
3115         case RTL_GIGA_MAC_VER_33:
3116                 rtl8168e_1_hw_phy_config(tp);
3117                 break;
3118         case RTL_GIGA_MAC_VER_34:
3119                 rtl8168e_2_hw_phy_config(tp);
3120                 break;
3121         case RTL_GIGA_MAC_VER_35:
3122                 rtl8168f_1_hw_phy_config(tp);
3123                 break;
3124         case RTL_GIGA_MAC_VER_36:
3125                 rtl8168f_2_hw_phy_config(tp);
3126                 break;
3127
3128         default:
3129                 break;
3130         }
3131 }
3132
3133 static void rtl8169_phy_timer(unsigned long __opaque)
3134 {
3135         struct net_device *dev = (struct net_device *)__opaque;
3136         struct rtl8169_private *tp = netdev_priv(dev);
3137         struct timer_list *timer = &tp->timer;
3138         void __iomem *ioaddr = tp->mmio_addr;
3139         unsigned long timeout = RTL8169_PHY_TIMEOUT;
3140
3141         assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
3142
3143         spin_lock_irq(&tp->lock);
3144
3145         if (tp->phy_reset_pending(tp)) {
3146                 /*
3147                  * A busy loop could burn quite a few cycles on nowadays CPU.
3148                  * Let's delay the execution of the timer for a few ticks.
3149                  */
3150                 timeout = HZ/10;
3151                 goto out_mod_timer;
3152         }
3153
3154         if (tp->link_ok(ioaddr))
3155                 goto out_unlock;
3156
3157         netif_warn(tp, link, dev, "PHY reset until link up\n");
3158
3159         tp->phy_reset_enable(tp);
3160
3161 out_mod_timer:
3162         mod_timer(timer, jiffies + timeout);
3163 out_unlock:
3164         spin_unlock_irq(&tp->lock);
3165 }
3166
3167 #ifdef CONFIG_NET_POLL_CONTROLLER
3168 /*
3169  * Polling 'interrupt' - used by things like netconsole to send skbs
3170  * without having to re-enable interrupts. It's not called while
3171  * the interrupt routine is executing.
3172  */
3173 static void rtl8169_netpoll(struct net_device *dev)
3174 {
3175         struct rtl8169_private *tp = netdev_priv(dev);
3176         struct pci_dev *pdev = tp->pci_dev;
3177
3178         disable_irq(pdev->irq);
3179         rtl8169_interrupt(pdev->irq, dev);
3180         enable_irq(pdev->irq);
3181 }
3182 #endif
3183
3184 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
3185                                   void __iomem *ioaddr)
3186 {
3187         iounmap(ioaddr);
3188         pci_release_regions(pdev);
3189         pci_clear_mwi(pdev);
3190         pci_disable_device(pdev);
3191         free_netdev(dev);
3192 }
3193
3194 static void rtl8169_phy_reset(struct net_device *dev,
3195                               struct rtl8169_private *tp)
3196 {
3197         unsigned int i;
3198
3199         tp->phy_reset_enable(tp);
3200         for (i = 0; i < 100; i++) {
3201                 if (!tp->phy_reset_pending(tp))
3202                         return;
3203                 msleep(1);
3204         }
3205         netif_err(tp, link, dev, "PHY reset failed\n");
3206 }
3207
3208 static bool rtl_tbi_enabled(struct rtl8169_private *tp)
3209 {
3210         void __iomem *ioaddr = tp->mmio_addr;
3211
3212         return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
3213             (RTL_R8(PHYstatus) & TBI_Enable);
3214 }
3215
3216 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
3217 {
3218         void __iomem *ioaddr = tp->mmio_addr;
3219
3220         rtl_hw_phy_config(dev);
3221
3222         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
3223                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3224                 RTL_W8(0x82, 0x01);
3225         }
3226
3227         pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
3228
3229         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3230                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
3231
3232         if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
3233                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3234                 RTL_W8(0x82, 0x01);
3235                 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
3236                 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
3237         }
3238
3239         rtl8169_phy_reset(dev, tp);
3240
3241         rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
3242                           ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3243                           ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
3244                           (tp->mii.supports_gmii ?
3245                            ADVERTISED_1000baseT_Half |
3246                            ADVERTISED_1000baseT_Full : 0));
3247
3248         if (rtl_tbi_enabled(tp))
3249                 netif_info(tp, link, dev, "TBI auto-negotiating\n");
3250 }
3251
3252 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
3253 {
3254         void __iomem *ioaddr = tp->mmio_addr;
3255         u32 high;
3256         u32 low;
3257
3258         low  = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
3259         high = addr[4] | (addr[5] << 8);
3260
3261         spin_lock_irq(&tp->lock);
3262
3263         RTL_W8(Cfg9346, Cfg9346_Unlock);
3264
3265         RTL_W32(MAC4, high);
3266         RTL_R32(MAC4);
3267
3268         RTL_W32(MAC0, low);
3269         RTL_R32(MAC0);
3270
3271         if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
3272                 const struct exgmac_reg e[] = {
3273                         { .addr = 0xe0, ERIAR_MASK_1111, .val = low },
3274                         { .addr = 0xe4, ERIAR_MASK_1111, .val = high },
3275                         { .addr = 0xf0, ERIAR_MASK_1111, .val = low << 16 },
3276                         { .addr = 0xf4, ERIAR_MASK_1111, .val = high << 16 |
3277                                                                 low  >> 16 },
3278                 };
3279
3280                 rtl_write_exgmac_batch(ioaddr, e, ARRAY_SIZE(e));
3281         }
3282
3283         RTL_W8(Cfg9346, Cfg9346_Lock);
3284
3285         spin_unlock_irq(&tp->lock);
3286 }
3287
3288 static int rtl_set_mac_address(struct net_device *dev, void *p)
3289 {
3290         struct rtl8169_private *tp = netdev_priv(dev);
3291         struct sockaddr *addr = p;
3292
3293         if (!is_valid_ether_addr(addr->sa_data))
3294                 return -EADDRNOTAVAIL;
3295
3296         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3297
3298         rtl_rar_set(tp, dev->dev_addr);
3299
3300         return 0;
3301 }
3302
3303 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3304 {
3305         struct rtl8169_private *tp = netdev_priv(dev);
3306         struct mii_ioctl_data *data = if_mii(ifr);
3307
3308         return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
3309 }
3310
3311 static int rtl_xmii_ioctl(struct rtl8169_private *tp,
3312                           struct mii_ioctl_data *data, int cmd)
3313 {
3314         switch (cmd) {
3315         case SIOCGMIIPHY:
3316                 data->phy_id = 32; /* Internal PHY */
3317                 return 0;
3318
3319         case SIOCGMIIREG:
3320                 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
3321                 return 0;
3322
3323         case SIOCSMIIREG:
3324                 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
3325                 return 0;
3326         }
3327         return -EOPNOTSUPP;
3328 }
3329
3330 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
3331 {
3332         return -EOPNOTSUPP;
3333 }
3334
3335 static const struct rtl_cfg_info {
3336         void (*hw_start)(struct net_device *);
3337         unsigned int region;
3338         unsigned int align;
3339         u16 intr_event;
3340         u16 napi_event;
3341         unsigned features;
3342         u8 default_ver;
3343 } rtl_cfg_infos [] = {
3344         [RTL_CFG_0] = {
3345                 .hw_start       = rtl_hw_start_8169,
3346                 .region         = 1,
3347                 .align          = 0,
3348                 .intr_event     = SYSErr | LinkChg | RxOverflow |
3349                                   RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
3350                 .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
3351                 .features       = RTL_FEATURE_GMII,
3352                 .default_ver    = RTL_GIGA_MAC_VER_01,
3353         },
3354         [RTL_CFG_1] = {
3355                 .hw_start       = rtl_hw_start_8168,
3356                 .region         = 2,
3357                 .align          = 8,
3358                 .intr_event     = SYSErr | LinkChg | RxOverflow |
3359                                   TxErr | TxOK | RxOK | RxErr,
3360                 .napi_event     = TxErr | TxOK | RxOK | RxOverflow,
3361                 .features       = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
3362                 .default_ver    = RTL_GIGA_MAC_VER_11,
3363         },
3364         [RTL_CFG_2] = {
3365                 .hw_start       = rtl_hw_start_8101,
3366                 .region         = 2,
3367                 .align          = 8,
3368                 .intr_event     = SYSErr | LinkChg | RxOverflow | PCSTimeout |
3369                                   RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
3370                 .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
3371                 .features       = RTL_FEATURE_MSI,
3372                 .default_ver    = RTL_GIGA_MAC_VER_13,
3373         }
3374 };
3375
3376 /* Cfg9346_Unlock assumed. */
3377 static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
3378                             const struct rtl_cfg_info *cfg)
3379 {
3380         unsigned msi = 0;
3381         u8 cfg2;
3382
3383         cfg2 = RTL_R8(Config2) & ~MSIEnable;
3384         if (cfg->features & RTL_FEATURE_MSI) {
3385                 if (pci_enable_msi(pdev)) {
3386                         dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
3387                 } else {
3388                         cfg2 |= MSIEnable;
3389                         msi = RTL_FEATURE_MSI;
3390                 }
3391         }
3392         RTL_W8(Config2, cfg2);
3393         return msi;
3394 }
3395
3396 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
3397 {
3398         if (tp->features & RTL_FEATURE_MSI) {
3399                 pci_disable_msi(pdev);
3400                 tp->features &= ~RTL_FEATURE_MSI;
3401         }
3402 }
3403
3404 static const struct net_device_ops rtl8169_netdev_ops = {
3405         .ndo_open               = rtl8169_open,
3406         .ndo_stop               = rtl8169_close,
3407         .ndo_get_stats          = rtl8169_get_stats,
3408         .ndo_start_xmit         = rtl8169_start_xmit,
3409         .ndo_tx_timeout         = rtl8169_tx_timeout,
3410         .ndo_validate_addr      = eth_validate_addr,
3411         .ndo_change_mtu         = rtl8169_change_mtu,
3412         .ndo_fix_features       = rtl8169_fix_features,
3413         .ndo_set_features       = rtl8169_set_features,
3414         .ndo_set_mac_address    = rtl_set_mac_address,
3415         .ndo_do_ioctl           = rtl8169_ioctl,
3416         .ndo_set_rx_mode        = rtl_set_rx_mode,
3417 #ifdef CONFIG_NET_POLL_CONTROLLER
3418         .ndo_poll_controller    = rtl8169_netpoll,
3419 #endif
3420
3421 };
3422
3423 static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp)
3424 {
3425         struct mdio_ops *ops = &tp->mdio_ops;
3426
3427         switch (tp->mac_version) {
3428         case RTL_GIGA_MAC_VER_27:
3429                 ops->write      = r8168dp_1_mdio_write;
3430                 ops->read       = r8168dp_1_mdio_read;
3431                 break;
3432         case RTL_GIGA_MAC_VER_28:
3433         case RTL_GIGA_MAC_VER_31:
3434                 ops->write      = r8168dp_2_mdio_write;
3435                 ops->read       = r8168dp_2_mdio_read;
3436                 break;
3437         default:
3438                 ops->write      = r8169_mdio_write;
3439                 ops->read       = r8169_mdio_read;
3440                 break;
3441         }
3442 }
3443
3444 static void r810x_phy_power_down(struct rtl8169_private *tp)
3445 {
3446         rtl_writephy(tp, 0x1f, 0x0000);
3447         rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3448 }
3449
3450 static void r810x_phy_power_up(struct rtl8169_private *tp)
3451 {
3452         rtl_writephy(tp, 0x1f, 0x0000);
3453         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3454 }
3455
3456 static void r810x_pll_power_down(struct rtl8169_private *tp)
3457 {
3458         void __iomem *ioaddr = tp->mmio_addr;
3459
3460         if (__rtl8169_get_wol(tp) & WAKE_ANY) {
3461                 rtl_writephy(tp, 0x1f, 0x0000);
3462                 rtl_writephy(tp, MII_BMCR, 0x0000);
3463
3464                 if (tp->mac_version == RTL_GIGA_MAC_VER_29 ||
3465                     tp->mac_version == RTL_GIGA_MAC_VER_30)
3466                         RTL_W32(RxConfig, RTL_R32(RxConfig) | AcceptBroadcast |
3467                                 AcceptMulticast | AcceptMyPhys);
3468                 return;
3469         }
3470
3471         r810x_phy_power_down(tp);
3472 }
3473
3474 static void r810x_pll_power_up(struct rtl8169_private *tp)
3475 {
3476         r810x_phy_power_up(tp);
3477 }
3478
3479 static void r8168_phy_power_up(struct rtl8169_private *tp)
3480 {
3481         rtl_writephy(tp, 0x1f, 0x0000);
3482         switch (tp->mac_version) {
3483         case RTL_GIGA_MAC_VER_11:
3484         case RTL_GIGA_MAC_VER_12:
3485         case RTL_GIGA_MAC_VER_17:
3486         case RTL_GIGA_MAC_VER_18:
3487         case RTL_GIGA_MAC_VER_19:
3488         case RTL_GIGA_MAC_VER_20:
3489         case RTL_GIGA_MAC_VER_21:
3490         case RTL_GIGA_MAC_VER_22:
3491         case RTL_GIGA_MAC_VER_23:
3492         case RTL_GIGA_MAC_VER_24:
3493         case RTL_GIGA_MAC_VER_25:
3494         case RTL_GIGA_MAC_VER_26:
3495         case RTL_GIGA_MAC_VER_27:
3496         case RTL_GIGA_MAC_VER_28:
3497         case RTL_GIGA_MAC_VER_31:
3498                 rtl_writephy(tp, 0x0e, 0x0000);
3499                 break;
3500         default:
3501                 break;
3502         }
3503         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3504 }
3505
3506 static void r8168_phy_power_down(struct rtl8169_private *tp)
3507 {
3508         rtl_writephy(tp, 0x1f, 0x0000);
3509         switch (tp->mac_version) {
3510         case RTL_GIGA_MAC_VER_32:
3511         case RTL_GIGA_MAC_VER_33:
3512                 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
3513                 break;
3514
3515         case RTL_GIGA_MAC_VER_11:
3516         case RTL_GIGA_MAC_VER_12:
3517         case RTL_GIGA_MAC_VER_17:
3518         case RTL_GIGA_MAC_VER_18:
3519         case RTL_GIGA_MAC_VER_19:
3520         case RTL_GIGA_MAC_VER_20:
3521         case RTL_GIGA_MAC_VER_21:
3522         case RTL_GIGA_MAC_VER_22:
3523         case RTL_GIGA_MAC_VER_23:
3524         case RTL_GIGA_MAC_VER_24:
3525         case RTL_GIGA_MAC_VER_25:
3526         case RTL_GIGA_MAC_VER_26:
3527         case RTL_GIGA_MAC_VER_27:
3528         case RTL_GIGA_MAC_VER_28:
3529         case RTL_GIGA_MAC_VER_31:
3530                 rtl_writephy(tp, 0x0e, 0x0200);
3531         default:
3532                 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3533                 break;
3534         }
3535 }
3536
3537 static void r8168_pll_power_down(struct rtl8169_private *tp)
3538 {
3539         void __iomem *ioaddr = tp->mmio_addr;
3540
3541         if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3542              tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3543              tp->mac_version == RTL_GIGA_MAC_VER_31) &&
3544             r8168dp_check_dash(tp)) {
3545                 return;
3546         }
3547
3548         if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
3549              tp->mac_version == RTL_GIGA_MAC_VER_24) &&
3550             (RTL_R16(CPlusCmd) & ASF)) {
3551                 return;
3552         }
3553
3554         if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3555             tp->mac_version == RTL_GIGA_MAC_VER_33)
3556                 rtl_ephy_write(ioaddr, 0x19, 0xff64);
3557
3558         if (__rtl8169_get_wol(tp) & WAKE_ANY) {
3559                 rtl_writephy(tp, 0x1f, 0x0000);
3560                 rtl_writephy(tp, MII_BMCR, 0x0000);
3561
3562                 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3563                     tp->mac_version == RTL_GIGA_MAC_VER_33 ||
3564                     tp->mac_version == RTL_GIGA_MAC_VER_34)
3565                         RTL_W32(RxConfig, RTL_R32(RxConfig) | AcceptBroadcast |
3566                                 AcceptMulticast | AcceptMyPhys);
3567                 return;
3568         }
3569
3570         r8168_phy_power_down(tp);
3571
3572         switch (tp->mac_version) {
3573         case RTL_GIGA_MAC_VER_25:
3574         case RTL_GIGA_MAC_VER_26:
3575         case RTL_GIGA_MAC_VER_27:
3576         case RTL_GIGA_MAC_VER_28:
3577         case RTL_GIGA_MAC_VER_31:
3578         case RTL_GIGA_MAC_VER_32:
3579         case RTL_GIGA_MAC_VER_33:
3580                 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
3581                 break;
3582         }
3583 }
3584
3585 static void r8168_pll_power_up(struct rtl8169_private *tp)
3586 {
3587         void __iomem *ioaddr = tp->mmio_addr;
3588
3589         if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3590              tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3591              tp->mac_version == RTL_GIGA_MAC_VER_31) &&
3592             r8168dp_check_dash(tp)) {
3593                 return;
3594         }
3595
3596         switch (tp->mac_version) {
3597         case RTL_GIGA_MAC_VER_25:
3598         case RTL_GIGA_MAC_VER_26:
3599         case RTL_GIGA_MAC_VER_27:
3600         case RTL_GIGA_MAC_VER_28:
3601         case RTL_GIGA_MAC_VER_31:
3602         case RTL_GIGA_MAC_VER_32:
3603         case RTL_GIGA_MAC_VER_33:
3604                 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
3605                 break;
3606         }
3607
3608         r8168_phy_power_up(tp);
3609 }
3610
3611 static void rtl_pll_power_op(struct rtl8169_private *tp,
3612                              void (*op)(struct rtl8169_private *))
3613 {
3614         if (op)
3615                 op(tp);
3616 }
3617
3618 static void rtl_pll_power_down(struct rtl8169_private *tp)
3619 {
3620         rtl_pll_power_op(tp, tp->pll_power_ops.down);
3621 }
3622
3623 static void rtl_pll_power_up(struct rtl8169_private *tp)
3624 {
3625         rtl_pll_power_op(tp, tp->pll_power_ops.up);
3626 }
3627
3628 static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
3629 {
3630         struct pll_power_ops *ops = &tp->pll_power_ops;
3631
3632         switch (tp->mac_version) {
3633         case RTL_GIGA_MAC_VER_07:
3634         case RTL_GIGA_MAC_VER_08:
3635         case RTL_GIGA_MAC_VER_09:
3636         case RTL_GIGA_MAC_VER_10:
3637         case RTL_GIGA_MAC_VER_16:
3638         case RTL_GIGA_MAC_VER_29:
3639         case RTL_GIGA_MAC_VER_30:
3640                 ops->down       = r810x_pll_power_down;
3641                 ops->up         = r810x_pll_power_up;
3642                 break;
3643
3644         case RTL_GIGA_MAC_VER_11:
3645         case RTL_GIGA_MAC_VER_12:
3646         case RTL_GIGA_MAC_VER_17:
3647         case RTL_GIGA_MAC_VER_18:
3648         case RTL_GIGA_MAC_VER_19:
3649         case RTL_GIGA_MAC_VER_20:
3650         case RTL_GIGA_MAC_VER_21:
3651         case RTL_GIGA_MAC_VER_22:
3652         case RTL_GIGA_MAC_VER_23:
3653         case RTL_GIGA_MAC_VER_24:
3654         case RTL_GIGA_MAC_VER_25:
3655         case RTL_GIGA_MAC_VER_26:
3656         case RTL_GIGA_MAC_VER_27:
3657         case RTL_GIGA_MAC_VER_28:
3658         case RTL_GIGA_MAC_VER_31:
3659         case RTL_GIGA_MAC_VER_32:
3660         case RTL_GIGA_MAC_VER_33:
3661         case RTL_GIGA_MAC_VER_34:
3662         case RTL_GIGA_MAC_VER_35:
3663         case RTL_GIGA_MAC_VER_36:
3664                 ops->down       = r8168_pll_power_down;
3665                 ops->up         = r8168_pll_power_up;
3666                 break;
3667
3668         default:
3669                 ops->down       = NULL;
3670                 ops->up         = NULL;
3671                 break;
3672         }
3673 }
3674
3675 static void rtl_init_rxcfg(struct rtl8169_private *tp)
3676 {
3677         void __iomem *ioaddr = tp->mmio_addr;
3678
3679         switch (tp->mac_version) {
3680         case RTL_GIGA_MAC_VER_01:
3681         case RTL_GIGA_MAC_VER_02:
3682         case RTL_GIGA_MAC_VER_03:
3683         case RTL_GIGA_MAC_VER_04:
3684         case RTL_GIGA_MAC_VER_05:
3685         case RTL_GIGA_MAC_VER_06:
3686         case RTL_GIGA_MAC_VER_10:
3687         case RTL_GIGA_MAC_VER_11:
3688         case RTL_GIGA_MAC_VER_12:
3689         case RTL_GIGA_MAC_VER_13:
3690         case RTL_GIGA_MAC_VER_14:
3691         case RTL_GIGA_MAC_VER_15:
3692         case RTL_GIGA_MAC_VER_16:
3693         case RTL_GIGA_MAC_VER_17:
3694                 RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
3695                 break;
3696         case RTL_GIGA_MAC_VER_18:
3697         case RTL_GIGA_MAC_VER_19:
3698         case RTL_GIGA_MAC_VER_20:
3699         case RTL_GIGA_MAC_VER_21:
3700         case RTL_GIGA_MAC_VER_22:
3701         case RTL_GIGA_MAC_VER_23:
3702         case RTL_GIGA_MAC_VER_24:
3703                 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
3704                 break;
3705         default:
3706                 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
3707                 break;
3708         }
3709 }
3710
3711 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
3712 {
3713         tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
3714 }
3715
3716 static void rtl_hw_reset(struct rtl8169_private *tp)
3717 {
3718         void __iomem *ioaddr = tp->mmio_addr;
3719         int i;
3720
3721         /* Soft reset the chip. */
3722         RTL_W8(ChipCmd, CmdReset);
3723
3724         /* Check that the chip has finished the reset. */
3725         for (i = 0; i < 100; i++) {
3726                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3727                         break;
3728                 udelay(100);
3729         }
3730
3731         rtl8169_init_ring_indexes(tp);
3732 }
3733
3734 static int __devinit
3735 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
3736 {
3737         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
3738         const unsigned int region = cfg->region;
3739         struct rtl8169_private *tp;
3740         struct mii_if_info *mii;
3741         struct net_device *dev;
3742         void __iomem *ioaddr;
3743         int chipset, i;
3744         int rc;
3745
3746         if (netif_msg_drv(&debug)) {
3747                 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
3748                        MODULENAME, RTL8169_VERSION);
3749         }
3750
3751         dev = alloc_etherdev(sizeof (*tp));
3752         if (!dev) {
3753                 if (netif_msg_drv(&debug))
3754                         dev_err(&pdev->dev, "unable to alloc new ethernet\n");
3755                 rc = -ENOMEM;
3756                 goto out;
3757         }
3758
3759         SET_NETDEV_DEV(dev, &pdev->dev);
3760         dev->netdev_ops = &rtl8169_netdev_ops;
3761         tp = netdev_priv(dev);
3762         tp->dev = dev;
3763         tp->pci_dev = pdev;
3764         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
3765
3766         mii = &tp->mii;
3767         mii->dev = dev;
3768         mii->mdio_read = rtl_mdio_read;
3769         mii->mdio_write = rtl_mdio_write;
3770         mii->phy_id_mask = 0x1f;
3771         mii->reg_num_mask = 0x1f;
3772         mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
3773
3774         /* disable ASPM completely as that cause random device stop working
3775          * problems as well as full system hangs for some PCIe devices users */
3776         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
3777                                      PCIE_LINK_STATE_CLKPM);
3778
3779         /* enable device (incl. PCI PM wakeup and hotplug setup) */
3780         rc = pci_enable_device(pdev);
3781         if (rc < 0) {
3782                 netif_err(tp, probe, dev, "enable failure\n");
3783                 goto err_out_free_dev_1;
3784         }
3785
3786         if (pci_set_mwi(pdev) < 0)
3787                 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
3788
3789         /* make sure PCI base addr 1 is MMIO */
3790         if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
3791                 netif_err(tp, probe, dev,
3792                           "region #%d not an MMIO resource, aborting\n",
3793                           region);
3794                 rc = -ENODEV;
3795                 goto err_out_mwi_2;
3796         }
3797
3798         /* check for weird/broken PCI region reporting */
3799         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
3800                 netif_err(tp, probe, dev,
3801                           "Invalid PCI region size(s), aborting\n");
3802                 rc = -ENODEV;
3803                 goto err_out_mwi_2;
3804         }
3805
3806         rc = pci_request_regions(pdev, MODULENAME);
3807         if (rc < 0) {
3808                 netif_err(tp, probe, dev, "could not request regions\n");
3809                 goto err_out_mwi_2;
3810         }
3811
3812         tp->cp_cmd = RxChkSum;
3813
3814         if ((sizeof(dma_addr_t) > 4) &&
3815             !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
3816                 tp->cp_cmd |= PCIDAC;
3817                 dev->features |= NETIF_F_HIGHDMA;
3818         } else {
3819                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3820                 if (rc < 0) {
3821                         netif_err(tp, probe, dev, "DMA configuration failed\n");
3822                         goto err_out_free_res_3;
3823                 }
3824         }
3825
3826         /* ioremap MMIO region */
3827         ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
3828         if (!ioaddr) {
3829                 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
3830                 rc = -EIO;
3831                 goto err_out_free_res_3;
3832         }
3833         tp->mmio_addr = ioaddr;
3834
3835         if (!pci_is_pcie(pdev))
3836                 netif_info(tp, probe, dev, "not PCI Express\n");
3837
3838         /* Identify chip attached to board */
3839         rtl8169_get_mac_version(tp, dev, cfg->default_ver);
3840
3841         rtl_init_rxcfg(tp);
3842
3843         RTL_W16(IntrMask, 0x0000);
3844
3845         rtl_hw_reset(tp);
3846
3847         RTL_W16(IntrStatus, 0xffff);
3848
3849         pci_set_master(pdev);
3850
3851         /*
3852          * Pretend we are using VLANs; This bypasses a nasty bug where
3853          * Interrupts stop flowing on high load on 8110SCd controllers.
3854          */
3855         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3856                 tp->cp_cmd |= RxVlan;
3857
3858         rtl_init_mdio_ops(tp);
3859         rtl_init_pll_power_ops(tp);
3860
3861         rtl8169_print_mac_version(tp);
3862
3863         chipset = tp->mac_version;
3864         tp->txd_version = rtl_chip_infos[chipset].txd_version;
3865
3866         RTL_W8(Cfg9346, Cfg9346_Unlock);
3867         RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
3868         RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
3869         if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
3870                 tp->features |= RTL_FEATURE_WOL;
3871         if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
3872                 tp->features |= RTL_FEATURE_WOL;
3873         tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
3874         RTL_W8(Cfg9346, Cfg9346_Lock);
3875
3876         if (rtl_tbi_enabled(tp)) {
3877                 tp->set_speed = rtl8169_set_speed_tbi;
3878                 tp->get_settings = rtl8169_gset_tbi;
3879                 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
3880                 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
3881                 tp->link_ok = rtl8169_tbi_link_ok;
3882                 tp->do_ioctl = rtl_tbi_ioctl;
3883         } else {
3884                 tp->set_speed = rtl8169_set_speed_xmii;
3885                 tp->get_settings = rtl8169_gset_xmii;
3886                 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
3887                 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
3888                 tp->link_ok = rtl8169_xmii_link_ok;
3889                 tp->do_ioctl = rtl_xmii_ioctl;
3890         }
3891
3892         spin_lock_init(&tp->lock);
3893
3894         /* Get MAC address */
3895         for (i = 0; i < MAC_ADDR_LEN; i++)
3896                 dev->dev_addr[i] = RTL_R8(MAC0 + i);
3897         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3898
3899         SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
3900         dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3901         dev->irq = pdev->irq;
3902         dev->base_addr = (unsigned long) ioaddr;
3903
3904         netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
3905
3906         /* don't enable SG, IP_CSUM and TSO by default - it might not work
3907          * properly for all devices */
3908         dev->features |= NETIF_F_RXCSUM |
3909                 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3910
3911         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
3912                 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3913         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
3914                 NETIF_F_HIGHDMA;
3915
3916         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3917                 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
3918                 dev->hw_features &= ~NETIF_F_HW_VLAN_RX;
3919
3920         tp->intr_mask = 0xffff;
3921         tp->hw_start = cfg->hw_start;
3922         tp->intr_event = cfg->intr_event;
3923         tp->napi_event = cfg->napi_event;
3924
3925         tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
3926                 ~(RxBOVF | RxFOVF) : ~0;
3927
3928         init_timer(&tp->timer);
3929         tp->timer.data = (unsigned long) dev;
3930         tp->timer.function = rtl8169_phy_timer;
3931
3932         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
3933
3934         rc = register_netdev(dev);
3935         if (rc < 0)
3936                 goto err_out_msi_4;
3937
3938         pci_set_drvdata(pdev, dev);
3939
3940         netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
3941                    rtl_chip_infos[chipset].name, dev->base_addr, dev->dev_addr,
3942                    (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq);
3943
3944         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3945             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3946             tp->mac_version == RTL_GIGA_MAC_VER_31) {
3947                 rtl8168_driver_start(tp);
3948         }
3949
3950         device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
3951
3952         if (pci_dev_run_wake(pdev))
3953                 pm_runtime_put_noidle(&pdev->dev);
3954
3955         netif_carrier_off(dev);
3956
3957 out:
3958         return rc;
3959
3960 err_out_msi_4:
3961         rtl_disable_msi(pdev, tp);
3962         iounmap(ioaddr);
3963 err_out_free_res_3:
3964         pci_release_regions(pdev);
3965 err_out_mwi_2:
3966         pci_clear_mwi(pdev);
3967         pci_disable_device(pdev);
3968 err_out_free_dev_1:
3969         free_netdev(dev);
3970         goto out;
3971 }
3972
3973 static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
3974 {
3975         struct net_device *dev = pci_get_drvdata(pdev);
3976         struct rtl8169_private *tp = netdev_priv(dev);
3977
3978         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3979             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3980             tp->mac_version == RTL_GIGA_MAC_VER_31) {
3981                 rtl8168_driver_stop(tp);
3982         }
3983
3984         cancel_delayed_work_sync(&tp->task);
3985
3986         unregister_netdev(dev);
3987
3988         rtl_release_firmware(tp);
3989
3990         if (pci_dev_run_wake(pdev))
3991                 pm_runtime_get_noresume(&pdev->dev);
3992
3993         /* restore original MAC address */
3994         rtl_rar_set(tp, dev->perm_addr);
3995
3996         rtl_disable_msi(pdev, tp);
3997         rtl8169_release_board(pdev, dev, tp->mmio_addr);
3998         pci_set_drvdata(pdev, NULL);
3999 }
4000
4001 static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
4002 {
4003         struct rtl_fw *rtl_fw;
4004         const char *name;
4005         int rc = -ENOMEM;
4006
4007         name = rtl_lookup_firmware_name(tp);
4008         if (!name)
4009                 goto out_no_firmware;
4010
4011         rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
4012         if (!rtl_fw)
4013                 goto err_warn;
4014
4015         rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
4016         if (rc < 0)
4017                 goto err_free;
4018
4019         rc = rtl_check_firmware(tp, rtl_fw);
4020         if (rc < 0)
4021                 goto err_release_firmware;
4022
4023         tp->rtl_fw = rtl_fw;
4024 out:
4025         return;
4026
4027 err_release_firmware:
4028         release_firmware(rtl_fw->fw);
4029 err_free:
4030         kfree(rtl_fw);
4031 err_warn:
4032         netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
4033                    name, rc);
4034 out_no_firmware:
4035         tp->rtl_fw = NULL;
4036         goto out;
4037 }
4038
4039 static void rtl_request_firmware(struct rtl8169_private *tp)
4040 {
4041         if (IS_ERR(tp->rtl_fw))
4042                 rtl_request_uncached_firmware(tp);
4043 }
4044
4045 static int rtl8169_open(struct net_device *dev)
4046 {
4047         struct rtl8169_private *tp = netdev_priv(dev);
4048         void __iomem *ioaddr = tp->mmio_addr;
4049         struct pci_dev *pdev = tp->pci_dev;
4050         int retval = -ENOMEM;
4051
4052         pm_runtime_get_sync(&pdev->dev);
4053
4054         /*
4055          * Rx and Tx desscriptors needs 256 bytes alignment.
4056          * dma_alloc_coherent provides more.
4057          */
4058         tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
4059                                              &tp->TxPhyAddr, GFP_KERNEL);
4060         if (!tp->TxDescArray)
4061                 goto err_pm_runtime_put;
4062
4063         tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
4064                                              &tp->RxPhyAddr, GFP_KERNEL);
4065         if (!tp->RxDescArray)
4066                 goto err_free_tx_0;
4067
4068         retval = rtl8169_init_ring(dev);
4069         if (retval < 0)
4070                 goto err_free_rx_1;
4071
4072         INIT_DELAYED_WORK(&tp->task, NULL);
4073
4074         smp_mb();
4075
4076         rtl_request_firmware(tp);
4077
4078         retval = request_irq(dev->irq, rtl8169_interrupt,
4079                              (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
4080                              dev->name, dev);
4081         if (retval < 0)
4082                 goto err_release_fw_2;
4083
4084         napi_enable(&tp->napi);
4085
4086         rtl8169_init_phy(dev, tp);
4087
4088         rtl8169_set_features(dev, dev->features);
4089
4090         rtl_pll_power_up(tp);
4091
4092         rtl_hw_start(dev);
4093
4094         tp->saved_wolopts = 0;
4095         pm_runtime_put_noidle(&pdev->dev);
4096
4097         rtl8169_check_link_status(dev, tp, ioaddr);
4098 out:
4099         return retval;
4100
4101 err_release_fw_2:
4102         rtl_release_firmware(tp);
4103         rtl8169_rx_clear(tp);
4104 err_free_rx_1:
4105         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
4106                           tp->RxPhyAddr);
4107         tp->RxDescArray = NULL;
4108 err_free_tx_0:
4109         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
4110                           tp->TxPhyAddr);
4111         tp->TxDescArray = NULL;
4112 err_pm_runtime_put:
4113         pm_runtime_put_noidle(&pdev->dev);
4114         goto out;
4115 }
4116
4117 static void rtl_rx_close(struct rtl8169_private *tp)
4118 {
4119         void __iomem *ioaddr = tp->mmio_addr;
4120
4121         RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
4122 }
4123
4124 static void rtl8169_hw_reset(struct rtl8169_private *tp)
4125 {
4126         void __iomem *ioaddr = tp->mmio_addr;
4127
4128         /* Disable interrupts */
4129         rtl8169_irq_mask_and_ack(ioaddr);
4130
4131         rtl_rx_close(tp);
4132
4133         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4134             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4135             tp->mac_version == RTL_GIGA_MAC_VER_31) {
4136                 while (RTL_R8(TxPoll) & NPQ)
4137                         udelay(20);
4138         } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
4139                    tp->mac_version == RTL_GIGA_MAC_VER_35 ||
4140                    tp->mac_version == RTL_GIGA_MAC_VER_36) {
4141                 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
4142                 while (!(RTL_R32(TxConfig) & TXCFG_EMPTY))
4143                         udelay(100);
4144         } else {
4145                 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
4146                 udelay(100);
4147         }
4148
4149         rtl_hw_reset(tp);
4150 }
4151
4152 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
4153 {
4154         void __iomem *ioaddr = tp->mmio_addr;
4155
4156         /* Set DMA burst size and Interframe Gap Time */
4157         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4158                 (InterFrameGap << TxInterFrameGapShift));
4159 }
4160
4161 static void rtl_hw_start(struct net_device *dev)
4162 {
4163         struct rtl8169_private *tp = netdev_priv(dev);
4164
4165         tp->hw_start(dev);
4166
4167         netif_start_queue(dev);
4168 }
4169
4170 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
4171                                          void __iomem *ioaddr)
4172 {
4173         /*
4174          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4175          * register to be written before TxDescAddrLow to work.
4176          * Switching from MMIO to I/O access fixes the issue as well.
4177          */
4178         RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4179         RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4180         RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4181         RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
4182 }
4183
4184 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
4185 {
4186         u16 cmd;
4187
4188         cmd = RTL_R16(CPlusCmd);
4189         RTL_W16(CPlusCmd, cmd);
4190         return cmd;
4191 }
4192
4193 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
4194 {
4195         /* Low hurts. Let's disable the filtering. */
4196         RTL_W16(RxMaxSize, rx_buf_sz + 1);
4197 }
4198
4199 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
4200 {
4201         static const struct rtl_cfg2_info {
4202                 u32 mac_version;
4203                 u32 clk;
4204                 u32 val;
4205         } cfg2_info [] = {
4206                 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
4207                 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
4208                 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
4209                 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
4210         };
4211         const struct rtl_cfg2_info *p = cfg2_info;
4212         unsigned int i;
4213         u32 clk;
4214
4215         clk = RTL_R8(Config2) & PCI_Clock_66MHz;
4216         for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
4217                 if ((p->mac_version == mac_version) && (p->clk == clk)) {
4218                         RTL_W32(0x7c, p->val);
4219                         break;
4220                 }
4221         }
4222 }
4223
4224 static void rtl_hw_start_8169(struct net_device *dev)
4225 {
4226         struct rtl8169_private *tp = netdev_priv(dev);
4227         void __iomem *ioaddr = tp->mmio_addr;
4228         struct pci_dev *pdev = tp->pci_dev;
4229
4230         if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
4231                 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
4232                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
4233         }
4234
4235         RTL_W8(Cfg9346, Cfg9346_Unlock);
4236         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4237             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4238             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4239             tp->mac_version == RTL_GIGA_MAC_VER_04)
4240                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4241
4242         rtl_init_rxcfg(tp);
4243
4244         RTL_W8(EarlyTxThres, NoEarlyTx);
4245
4246         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4247
4248         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4249             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4250             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4251             tp->mac_version == RTL_GIGA_MAC_VER_04)
4252                 rtl_set_rx_tx_config_registers(tp);
4253
4254         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
4255
4256         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4257             tp->mac_version == RTL_GIGA_MAC_VER_03) {
4258                 dprintk("Set MAC Reg C+CR Offset 0xE0. "
4259                         "Bit-3 and bit-14 MUST be 1\n");
4260                 tp->cp_cmd |= (1 << 14);
4261         }
4262
4263         RTL_W16(CPlusCmd, tp->cp_cmd);
4264
4265         rtl8169_set_magic_reg(ioaddr, tp->mac_version);
4266
4267         /*
4268          * Undocumented corner. Supposedly:
4269          * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4270          */
4271         RTL_W16(IntrMitigate, 0x0000);
4272
4273         rtl_set_rx_tx_desc_registers(tp, ioaddr);
4274
4275         if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
4276             tp->mac_version != RTL_GIGA_MAC_VER_02 &&
4277             tp->mac_version != RTL_GIGA_MAC_VER_03 &&
4278             tp->mac_version != RTL_GIGA_MAC_VER_04) {
4279                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4280                 rtl_set_rx_tx_config_registers(tp);
4281         }
4282
4283         RTL_W8(Cfg9346, Cfg9346_Lock);
4284
4285         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4286         RTL_R8(IntrMask);
4287
4288         RTL_W32(RxMissed, 0);
4289
4290         rtl_set_rx_mode(dev);
4291
4292         /* no early-rx interrupts */
4293         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
4294
4295         /* Enable all known interrupts by setting the interrupt mask. */
4296         RTL_W16(IntrMask, tp->intr_event);
4297 }
4298
4299 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
4300 {
4301         int cap = pci_pcie_cap(pdev);
4302
4303         if (cap) {
4304                 u16 ctl;
4305
4306                 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
4307                 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
4308                 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
4309         }
4310 }
4311
4312 static void rtl_csi_access_enable(void __iomem *ioaddr, u32 bits)
4313 {
4314         u32 csi;
4315
4316         csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
4317         rtl_csi_write(ioaddr, 0x070c, csi | bits);
4318 }
4319
4320 static void rtl_csi_access_enable_1(void __iomem *ioaddr)
4321 {
4322         rtl_csi_access_enable(ioaddr, 0x17000000);
4323 }
4324
4325 static void rtl_csi_access_enable_2(void __iomem *ioaddr)
4326 {
4327         rtl_csi_access_enable(ioaddr, 0x27000000);
4328 }
4329
4330 struct ephy_info {
4331         unsigned int offset;
4332         u16 mask;
4333         u16 bits;
4334 };
4335
4336 static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
4337 {
4338         u16 w;
4339
4340         while (len-- > 0) {
4341                 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
4342                 rtl_ephy_write(ioaddr, e->offset, w);
4343                 e++;
4344         }
4345 }
4346
4347 static void rtl_disable_clock_request(struct pci_dev *pdev)
4348 {
4349         int cap = pci_pcie_cap(pdev);
4350
4351         if (cap) {
4352                 u16 ctl;
4353
4354                 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
4355                 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
4356                 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
4357         }
4358 }
4359
4360 static void rtl_enable_clock_request(struct pci_dev *pdev)
4361 {
4362         int cap = pci_pcie_cap(pdev);
4363
4364         if (cap) {
4365                 u16 ctl;
4366
4367                 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
4368                 ctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
4369                 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
4370         }
4371 }
4372
4373 #define R8168_CPCMD_QUIRK_MASK (\
4374         EnableBist | \
4375         Mac_dbgo_oe | \
4376         Force_half_dup | \
4377         Force_rxflow_en | \
4378         Force_txflow_en | \
4379         Cxpl_dbg_sel | \
4380         ASF | \
4381         PktCntrDisable | \
4382         Mac_dbgo_sel)
4383
4384 static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
4385 {
4386         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4387
4388         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4389
4390         rtl_tx_performance_tweak(pdev,
4391                 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4392 }
4393
4394 static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
4395 {
4396         rtl_hw_start_8168bb(ioaddr, pdev);
4397
4398         RTL_W8(MaxTxPacketSize, TxPacketMax);
4399
4400         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
4401 }
4402
4403 static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
4404 {
4405         RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
4406
4407         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4408
4409         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4410
4411         rtl_disable_clock_request(pdev);
4412
4413         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4414 }
4415
4416 static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
4417 {
4418         static const struct ephy_info e_info_8168cp[] = {
4419                 { 0x01, 0,      0x0001 },
4420                 { 0x02, 0x0800, 0x1000 },
4421                 { 0x03, 0,      0x0042 },
4422                 { 0x06, 0x0080, 0x0000 },
4423                 { 0x07, 0,      0x2000 }
4424         };
4425
4426         rtl_csi_access_enable_2(ioaddr);
4427
4428         rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
4429
4430         __rtl_hw_start_8168cp(ioaddr, pdev);
4431 }
4432
4433 static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
4434 {
4435         rtl_csi_access_enable_2(ioaddr);
4436
4437         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4438
4439         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4440
4441         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4442 }
4443
4444 static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
4445 {
4446         rtl_csi_access_enable_2(ioaddr);
4447
4448         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4449
4450         /* Magic. */
4451         RTL_W8(DBG_REG, 0x20);
4452
4453         RTL_W8(MaxTxPacketSize, TxPacketMax);
4454
4455         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4456
4457         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4458 }
4459
4460 static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
4461 {
4462         static const struct ephy_info e_info_8168c_1[] = {
4463                 { 0x02, 0x0800, 0x1000 },
4464                 { 0x03, 0,      0x0002 },
4465                 { 0x06, 0x0080, 0x0000 }
4466         };
4467
4468         rtl_csi_access_enable_2(ioaddr);
4469
4470         RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4471
4472         rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
4473
4474         __rtl_hw_start_8168cp(ioaddr, pdev);
4475 }
4476
4477 static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
4478 {
4479         static const struct ephy_info e_info_8168c_2[] = {
4480                 { 0x01, 0,      0x0001 },
4481                 { 0x03, 0x0400, 0x0220 }
4482         };
4483
4484         rtl_csi_access_enable_2(ioaddr);
4485
4486         rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
4487
4488         __rtl_hw_start_8168cp(ioaddr, pdev);
4489 }
4490
4491 static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
4492 {
4493         rtl_hw_start_8168c_2(ioaddr, pdev);
4494 }
4495
4496 static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
4497 {
4498         rtl_csi_access_enable_2(ioaddr);
4499
4500         __rtl_hw_start_8168cp(ioaddr, pdev);
4501 }
4502
4503 static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
4504 {
4505         rtl_csi_access_enable_2(ioaddr);
4506
4507         rtl_disable_clock_request(pdev);
4508
4509         RTL_W8(MaxTxPacketSize, TxPacketMax);
4510
4511         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4512
4513         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4514 }
4515
4516 static void rtl_hw_start_8168dp(void __iomem *ioaddr, struct pci_dev *pdev)
4517 {
4518         rtl_csi_access_enable_1(ioaddr);
4519
4520         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4521
4522         RTL_W8(MaxTxPacketSize, TxPacketMax);
4523
4524         rtl_disable_clock_request(pdev);
4525 }
4526
4527 static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev)
4528 {
4529         static const struct ephy_info e_info_8168d_4[] = {
4530                 { 0x0b, ~0,     0x48 },
4531                 { 0x19, 0x20,   0x50 },
4532                 { 0x0c, ~0,     0x20 }
4533         };
4534         int i;
4535
4536         rtl_csi_access_enable_1(ioaddr);
4537
4538         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4539
4540         RTL_W8(MaxTxPacketSize, TxPacketMax);
4541
4542         for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
4543                 const struct ephy_info *e = e_info_8168d_4 + i;
4544                 u16 w;
4545
4546                 w = rtl_ephy_read(ioaddr, e->offset);
4547                 rtl_ephy_write(ioaddr, 0x03, (w & e->mask) | e->bits);
4548         }
4549
4550         rtl_enable_clock_request(pdev);
4551 }
4552
4553 static void rtl_hw_start_8168e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4554 {
4555         static const struct ephy_info e_info_8168e_1[] = {
4556                 { 0x00, 0x0200, 0x0100 },
4557                 { 0x00, 0x0000, 0x0004 },
4558                 { 0x06, 0x0002, 0x0001 },
4559                 { 0x06, 0x0000, 0x0030 },
4560                 { 0x07, 0x0000, 0x2000 },
4561                 { 0x00, 0x0000, 0x0020 },
4562                 { 0x03, 0x5800, 0x2000 },
4563                 { 0x03, 0x0000, 0x0001 },
4564                 { 0x01, 0x0800, 0x1000 },
4565                 { 0x07, 0x0000, 0x4000 },
4566                 { 0x1e, 0x0000, 0x2000 },
4567                 { 0x19, 0xffff, 0xfe6c },
4568                 { 0x0a, 0x0000, 0x0040 }
4569         };
4570
4571         rtl_csi_access_enable_2(ioaddr);
4572
4573         rtl_ephy_init(ioaddr, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
4574
4575         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4576
4577         RTL_W8(MaxTxPacketSize, TxPacketMax);
4578
4579         rtl_disable_clock_request(pdev);
4580
4581         /* Reset tx FIFO pointer */
4582         RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
4583         RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
4584
4585         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4586 }
4587
4588 static void rtl_hw_start_8168e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4589 {
4590         static const struct ephy_info e_info_8168e_2[] = {
4591                 { 0x09, 0x0000, 0x0080 },
4592                 { 0x19, 0x0000, 0x0224 }
4593         };
4594
4595         rtl_csi_access_enable_1(ioaddr);
4596
4597         rtl_ephy_init(ioaddr, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
4598
4599         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4600
4601         rtl_eri_write(ioaddr, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4602         rtl_eri_write(ioaddr, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4603         rtl_eri_write(ioaddr, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
4604         rtl_eri_write(ioaddr, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
4605         rtl_eri_write(ioaddr, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
4606         rtl_eri_write(ioaddr, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
4607         rtl_w1w0_eri(ioaddr, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4608         rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00,
4609                      ERIAR_EXGMAC);
4610
4611         RTL_W8(MaxTxPacketSize, EarlySize);
4612
4613         rtl_disable_clock_request(pdev);
4614
4615         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
4616         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
4617
4618         /* Adjust EEE LED frequency */
4619         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
4620
4621         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4622         RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
4623         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4624 }
4625
4626 static void rtl_hw_start_8168f_1(void __iomem *ioaddr, struct pci_dev *pdev)
4627 {
4628         static const struct ephy_info e_info_8168f_1[] = {
4629                 { 0x06, 0x00c0, 0x0020 },
4630                 { 0x08, 0x0001, 0x0002 },
4631                 { 0x09, 0x0000, 0x0080 },
4632                 { 0x19, 0x0000, 0x0224 }
4633         };
4634
4635         rtl_csi_access_enable_1(ioaddr);
4636
4637         rtl_ephy_init(ioaddr, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
4638
4639         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4640
4641         rtl_eri_write(ioaddr, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4642         rtl_eri_write(ioaddr, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4643         rtl_eri_write(ioaddr, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
4644         rtl_eri_write(ioaddr, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
4645         rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
4646         rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
4647         rtl_w1w0_eri(ioaddr, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4648         rtl_w1w0_eri(ioaddr, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4649         rtl_eri_write(ioaddr, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
4650         rtl_eri_write(ioaddr, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
4651         rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00,
4652                      ERIAR_EXGMAC);
4653
4654         RTL_W8(MaxTxPacketSize, EarlySize);
4655
4656         rtl_disable_clock_request(pdev);
4657
4658         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
4659         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
4660
4661         /* Adjust EEE LED frequency */
4662         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
4663
4664         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4665         RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
4666         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4667 }
4668
4669 static void rtl_hw_start_8168(struct net_device *dev)
4670 {
4671         struct rtl8169_private *tp = netdev_priv(dev);
4672         void __iomem *ioaddr = tp->mmio_addr;
4673         struct pci_dev *pdev = tp->pci_dev;
4674
4675         RTL_W8(Cfg9346, Cfg9346_Unlock);
4676
4677         RTL_W8(MaxTxPacketSize, TxPacketMax);
4678
4679         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4680
4681         tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
4682
4683         RTL_W16(CPlusCmd, tp->cp_cmd);
4684
4685         RTL_W16(IntrMitigate, 0x5151);
4686
4687         /* Work around for RxFIFO overflow. */
4688         if (tp->mac_version == RTL_GIGA_MAC_VER_11 ||
4689             tp->mac_version == RTL_GIGA_MAC_VER_22) {
4690                 tp->intr_event |= RxFIFOOver | PCSTimeout;
4691                 tp->intr_event &= ~RxOverflow;
4692         }
4693
4694         rtl_set_rx_tx_desc_registers(tp, ioaddr);
4695
4696         rtl_set_rx_mode(dev);
4697
4698         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4699                 (InterFrameGap << TxInterFrameGapShift));
4700
4701         RTL_R8(IntrMask);
4702
4703         switch (tp->mac_version) {
4704         case RTL_GIGA_MAC_VER_11:
4705                 rtl_hw_start_8168bb(ioaddr, pdev);
4706                 break;
4707
4708         case RTL_GIGA_MAC_VER_12:
4709         case RTL_GIGA_MAC_VER_17:
4710                 rtl_hw_start_8168bef(ioaddr, pdev);
4711                 break;
4712
4713         case RTL_GIGA_MAC_VER_18:
4714                 rtl_hw_start_8168cp_1(ioaddr, pdev);
4715                 break;
4716
4717         case RTL_GIGA_MAC_VER_19:
4718                 rtl_hw_start_8168c_1(ioaddr, pdev);
4719                 break;
4720
4721         case RTL_GIGA_MAC_VER_20:
4722                 rtl_hw_start_8168c_2(ioaddr, pdev);
4723                 break;
4724
4725         case RTL_GIGA_MAC_VER_21:
4726                 rtl_hw_start_8168c_3(ioaddr, pdev);
4727                 break;
4728
4729         case RTL_GIGA_MAC_VER_22:
4730                 rtl_hw_start_8168c_4(ioaddr, pdev);
4731                 break;
4732
4733         case RTL_GIGA_MAC_VER_23:
4734                 rtl_hw_start_8168cp_2(ioaddr, pdev);
4735                 break;
4736
4737         case RTL_GIGA_MAC_VER_24:
4738                 rtl_hw_start_8168cp_3(ioaddr, pdev);
4739                 break;
4740
4741         case RTL_GIGA_MAC_VER_25:
4742         case RTL_GIGA_MAC_VER_26:
4743         case RTL_GIGA_MAC_VER_27:
4744                 rtl_hw_start_8168d(ioaddr, pdev);
4745                 break;
4746
4747         case RTL_GIGA_MAC_VER_28:
4748                 rtl_hw_start_8168d_4(ioaddr, pdev);
4749                 break;
4750
4751         case RTL_GIGA_MAC_VER_31:
4752                 rtl_hw_start_8168dp(ioaddr, pdev);
4753                 break;
4754
4755         case RTL_GIGA_MAC_VER_32:
4756         case RTL_GIGA_MAC_VER_33:
4757                 rtl_hw_start_8168e_1(ioaddr, pdev);
4758                 break;
4759         case RTL_GIGA_MAC_VER_34:
4760                 rtl_hw_start_8168e_2(ioaddr, pdev);
4761                 break;
4762
4763         case RTL_GIGA_MAC_VER_35:
4764         case RTL_GIGA_MAC_VER_36:
4765                 rtl_hw_start_8168f_1(ioaddr, pdev);
4766                 break;
4767
4768         default:
4769                 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
4770                         dev->name, tp->mac_version);
4771                 break;
4772         }
4773
4774         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4775
4776         RTL_W8(Cfg9346, Cfg9346_Lock);
4777
4778         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
4779
4780         RTL_W16(IntrMask, tp->intr_event);
4781 }
4782
4783 #define R810X_CPCMD_QUIRK_MASK (\
4784         EnableBist | \
4785         Mac_dbgo_oe | \
4786         Force_half_dup | \
4787         Force_rxflow_en | \
4788         Force_txflow_en | \
4789         Cxpl_dbg_sel | \
4790         ASF | \
4791         PktCntrDisable | \
4792         Mac_dbgo_sel)
4793
4794 static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4795 {
4796         static const struct ephy_info e_info_8102e_1[] = {
4797                 { 0x01, 0, 0x6e65 },
4798                 { 0x02, 0, 0x091f },
4799                 { 0x03, 0, 0xc2f9 },
4800                 { 0x06, 0, 0xafb5 },
4801                 { 0x07, 0, 0x0e00 },
4802                 { 0x19, 0, 0xec80 },
4803                 { 0x01, 0, 0x2e65 },
4804                 { 0x01, 0, 0x6e65 }
4805         };
4806         u8 cfg1;
4807
4808         rtl_csi_access_enable_2(ioaddr);
4809
4810         RTL_W8(DBG_REG, FIX_NAK_1);
4811
4812         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4813
4814         RTL_W8(Config1,
4815                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
4816         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4817
4818         cfg1 = RTL_R8(Config1);
4819         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
4820                 RTL_W8(Config1, cfg1 & ~LEDS0);
4821
4822         rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
4823 }
4824
4825 static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4826 {
4827         rtl_csi_access_enable_2(ioaddr);
4828
4829         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4830
4831         RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
4832         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4833 }
4834
4835 static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
4836 {
4837         rtl_hw_start_8102e_2(ioaddr, pdev);
4838
4839         rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
4840 }
4841
4842 static void rtl_hw_start_8105e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4843 {
4844         static const struct ephy_info e_info_8105e_1[] = {
4845                 { 0x07, 0, 0x4000 },
4846                 { 0x19, 0, 0x0200 },
4847                 { 0x19, 0, 0x0020 },
4848                 { 0x1e, 0, 0x2000 },
4849                 { 0x03, 0, 0x0001 },
4850                 { 0x19, 0, 0x0100 },
4851                 { 0x19, 0, 0x0004 },
4852                 { 0x0a, 0, 0x0020 }
4853         };
4854
4855         /* Force LAN exit from ASPM if Rx/Tx are not idle */
4856         RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
4857
4858         /* Disable Early Tally Counter */
4859         RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
4860
4861         RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
4862         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4863
4864         rtl_ephy_init(ioaddr, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
4865 }
4866
4867 static void rtl_hw_start_8105e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4868 {
4869         rtl_hw_start_8105e_1(ioaddr, pdev);
4870         rtl_ephy_write(ioaddr, 0x1e, rtl_ephy_read(ioaddr, 0x1e) | 0x8000);
4871 }
4872
4873 static void rtl_hw_start_8101(struct net_device *dev)
4874 {
4875         struct rtl8169_private *tp = netdev_priv(dev);
4876         void __iomem *ioaddr = tp->mmio_addr;
4877         struct pci_dev *pdev = tp->pci_dev;
4878
4879         if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
4880             tp->mac_version == RTL_GIGA_MAC_VER_16) {
4881                 int cap = pci_pcie_cap(pdev);
4882
4883                 if (cap) {
4884                         pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
4885                                               PCI_EXP_DEVCTL_NOSNOOP_EN);
4886                 }
4887         }
4888
4889         RTL_W8(Cfg9346, Cfg9346_Unlock);
4890
4891         switch (tp->mac_version) {
4892         case RTL_GIGA_MAC_VER_07:
4893                 rtl_hw_start_8102e_1(ioaddr, pdev);
4894                 break;
4895
4896         case RTL_GIGA_MAC_VER_08:
4897                 rtl_hw_start_8102e_3(ioaddr, pdev);
4898                 break;
4899
4900         case RTL_GIGA_MAC_VER_09:
4901                 rtl_hw_start_8102e_2(ioaddr, pdev);
4902                 break;
4903
4904         case RTL_GIGA_MAC_VER_29:
4905                 rtl_hw_start_8105e_1(ioaddr, pdev);
4906                 break;
4907         case RTL_GIGA_MAC_VER_30:
4908                 rtl_hw_start_8105e_2(ioaddr, pdev);
4909                 break;
4910         }
4911
4912         RTL_W8(Cfg9346, Cfg9346_Lock);
4913
4914         RTL_W8(MaxTxPacketSize, TxPacketMax);
4915
4916         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4917
4918         tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
4919         RTL_W16(CPlusCmd, tp->cp_cmd);
4920
4921         RTL_W16(IntrMitigate, 0x0000);
4922
4923         rtl_set_rx_tx_desc_registers(tp, ioaddr);
4924
4925         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4926         rtl_set_rx_tx_config_registers(tp);
4927
4928         RTL_R8(IntrMask);
4929
4930         rtl_set_rx_mode(dev);
4931
4932         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
4933
4934         RTL_W16(IntrMask, tp->intr_event);
4935 }
4936
4937 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
4938 {
4939         if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
4940                 return -EINVAL;
4941
4942         dev->mtu = new_mtu;
4943         netdev_update_features(dev);
4944
4945         return 0;
4946 }
4947
4948 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
4949 {
4950         desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
4951         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
4952 }
4953
4954 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
4955                                      void **data_buff, struct RxDesc *desc)
4956 {
4957         dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
4958                          DMA_FROM_DEVICE);
4959
4960         kfree(*data_buff);
4961         *data_buff = NULL;
4962         rtl8169_make_unusable_by_asic(desc);
4963 }
4964
4965 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
4966 {
4967         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
4968
4969         desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
4970 }
4971
4972 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
4973                                        u32 rx_buf_sz)
4974 {
4975         desc->addr = cpu_to_le64(mapping);
4976         wmb();
4977         rtl8169_mark_to_asic(desc, rx_buf_sz);
4978 }
4979
4980 static inline void *rtl8169_align(void *data)
4981 {
4982         return (void *)ALIGN((long)data, 16);
4983 }
4984
4985 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
4986                                              struct RxDesc *desc)
4987 {
4988         void *data;
4989         dma_addr_t mapping;
4990         struct device *d = &tp->pci_dev->dev;
4991         struct net_device *dev = tp->dev;
4992         int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
4993
4994         data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
4995         if (!data)
4996                 return NULL;
4997
4998         if (rtl8169_align(data) != data) {
4999                 kfree(data);
5000                 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
5001                 if (!data)
5002                         return NULL;
5003         }
5004
5005         mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
5006                                  DMA_FROM_DEVICE);
5007         if (unlikely(dma_mapping_error(d, mapping))) {
5008                 if (net_ratelimit())
5009                         netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
5010                 goto err_out;
5011         }
5012
5013         rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
5014         return data;
5015
5016 err_out:
5017         kfree(data);
5018         return NULL;
5019 }
5020
5021 static void rtl8169_rx_clear(struct rtl8169_private *tp)
5022 {
5023         unsigned int i;
5024
5025         for (i = 0; i < NUM_RX_DESC; i++) {
5026                 if (tp->Rx_databuff[i]) {
5027                         rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
5028                                             tp->RxDescArray + i);
5029                 }
5030         }
5031 }
5032
5033 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
5034 {
5035         desc->opts1 |= cpu_to_le32(RingEnd);
5036 }
5037
5038 static int rtl8169_rx_fill(struct rtl8169_private *tp)
5039 {
5040         unsigned int i;
5041
5042         for (i = 0; i < NUM_RX_DESC; i++) {
5043                 void *data;
5044
5045                 if (tp->Rx_databuff[i])
5046                         continue;
5047
5048                 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
5049                 if (!data) {
5050                         rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
5051                         goto err_out;
5052                 }
5053                 tp->Rx_databuff[i] = data;
5054         }
5055
5056         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
5057         return 0;
5058
5059 err_out:
5060         rtl8169_rx_clear(tp);
5061         return -ENOMEM;
5062 }
5063
5064 static int rtl8169_init_ring(struct net_device *dev)
5065 {
5066         struct rtl8169_private *tp = netdev_priv(dev);
5067
5068         rtl8169_init_ring_indexes(tp);
5069
5070         memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
5071         memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
5072
5073         return rtl8169_rx_fill(tp);
5074 }
5075
5076 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
5077                                  struct TxDesc *desc)
5078 {
5079         unsigned int len = tx_skb->len;
5080
5081         dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
5082
5083         desc->opts1 = 0x00;
5084         desc->opts2 = 0x00;
5085         desc->addr = 0x00;
5086         tx_skb->len = 0;
5087 }
5088
5089 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
5090                                    unsigned int n)
5091 {
5092         unsigned int i;
5093
5094         for (i = 0; i < n; i++) {
5095                 unsigned int entry = (start + i) % NUM_TX_DESC;
5096                 struct ring_info *tx_skb = tp->tx_skb + entry;
5097                 unsigned int len = tx_skb->len;
5098
5099                 if (len) {
5100                         struct sk_buff *skb = tx_skb->skb;
5101
5102                         rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
5103                                              tp->TxDescArray + entry);
5104                         if (skb) {
5105                                 tp->dev->stats.tx_dropped++;
5106                                 dev_kfree_skb(skb);
5107                                 tx_skb->skb = NULL;
5108                         }
5109                 }
5110         }
5111 }
5112
5113 static void rtl8169_tx_clear(struct rtl8169_private *tp)
5114 {
5115         rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
5116         tp->cur_tx = tp->dirty_tx = 0;
5117 }
5118
5119 static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
5120 {
5121         struct rtl8169_private *tp = netdev_priv(dev);
5122
5123         PREPARE_DELAYED_WORK(&tp->task, task);
5124         schedule_delayed_work(&tp->task, 4);
5125 }
5126
5127 static void rtl8169_wait_for_quiescence(struct net_device *dev)
5128 {
5129         struct rtl8169_private *tp = netdev_priv(dev);
5130         void __iomem *ioaddr = tp->mmio_addr;
5131
5132         synchronize_irq(dev->irq);
5133
5134         /* Wait for any pending NAPI task to complete */
5135         napi_disable(&tp->napi);
5136
5137         rtl8169_irq_mask_and_ack(ioaddr);
5138
5139         tp->intr_mask = 0xffff;
5140         RTL_W16(IntrMask, tp->intr_event);
5141         napi_enable(&tp->napi);
5142 }
5143
5144 static void rtl8169_reinit_task(struct work_struct *work)
5145 {
5146         struct rtl8169_private *tp =
5147                 container_of(work, struct rtl8169_private, task.work);
5148         struct net_device *dev = tp->dev;
5149         int ret;
5150
5151         rtnl_lock();
5152
5153         if (!netif_running(dev))
5154                 goto out_unlock;
5155
5156         rtl8169_wait_for_quiescence(dev);
5157         rtl8169_close(dev);
5158
5159         ret = rtl8169_open(dev);
5160         if (unlikely(ret < 0)) {
5161                 if (net_ratelimit())
5162                         netif_err(tp, drv, dev,
5163                                   "reinit failure (status = %d). Rescheduling\n",
5164                                   ret);
5165                 rtl8169_schedule_work(dev, rtl8169_reinit_task);
5166         }
5167
5168 out_unlock:
5169         rtnl_unlock();
5170 }
5171
5172 static void rtl8169_reset_task(struct work_struct *work)
5173 {
5174         struct rtl8169_private *tp =
5175                 container_of(work, struct rtl8169_private, task.work);
5176         struct net_device *dev = tp->dev;
5177         int i;
5178
5179         rtnl_lock();
5180
5181         if (!netif_running(dev))
5182                 goto out_unlock;
5183
5184         rtl8169_wait_for_quiescence(dev);
5185
5186         for (i = 0; i < NUM_RX_DESC; i++)
5187                 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
5188
5189         rtl8169_tx_clear(tp);
5190
5191         rtl8169_hw_reset(tp);
5192         rtl_hw_start(dev);
5193         netif_wake_queue(dev);
5194         rtl8169_check_link_status(dev, tp, tp->mmio_addr);
5195
5196 out_unlock:
5197         rtnl_unlock();
5198 }
5199
5200 static void rtl8169_tx_timeout(struct net_device *dev)
5201 {
5202         struct rtl8169_private *tp = netdev_priv(dev);
5203
5204         rtl8169_hw_reset(tp);
5205
5206         /* Let's wait a bit while any (async) irq lands on */
5207         rtl8169_schedule_work(dev, rtl8169_reset_task);
5208 }
5209
5210 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
5211                               u32 *opts)
5212 {
5213         struct skb_shared_info *info = skb_shinfo(skb);
5214         unsigned int cur_frag, entry;
5215         struct TxDesc * uninitialized_var(txd);
5216         struct device *d = &tp->pci_dev->dev;
5217
5218         entry = tp->cur_tx;
5219         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
5220                 skb_frag_t *frag = info->frags + cur_frag;
5221                 dma_addr_t mapping;
5222                 u32 status, len;
5223                 void *addr;
5224
5225                 entry = (entry + 1) % NUM_TX_DESC;
5226
5227                 txd = tp->TxDescArray + entry;
5228                 len = frag->size;
5229                 addr = skb_frag_address(frag);
5230                 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
5231                 if (unlikely(dma_mapping_error(d, mapping))) {
5232                         if (net_ratelimit())
5233                                 netif_err(tp, drv, tp->dev,
5234                                           "Failed to map TX fragments DMA!\n");
5235                         goto err_out;
5236                 }
5237
5238                 /* Anti gcc 2.95.3 bugware (sic) */
5239                 status = opts[0] | len |
5240                         (RingEnd * !((entry + 1) % NUM_TX_DESC));
5241
5242                 txd->opts1 = cpu_to_le32(status);
5243                 txd->opts2 = cpu_to_le32(opts[1]);
5244                 txd->addr = cpu_to_le64(mapping);
5245
5246                 tp->tx_skb[entry].len = len;
5247         }
5248
5249         if (cur_frag) {
5250                 tp->tx_skb[entry].skb = skb;
5251                 txd->opts1 |= cpu_to_le32(LastFrag);
5252         }
5253
5254         return cur_frag;
5255
5256 err_out:
5257         rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5258         return -EIO;
5259 }
5260
5261 static inline void rtl8169_tso_csum(struct rtl8169_private *tp,
5262                                     struct sk_buff *skb, u32 *opts)
5263 {
5264         const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version;
5265         u32 mss = skb_shinfo(skb)->gso_size;
5266         int offset = info->opts_offset;
5267
5268         if (mss) {
5269                 opts[0] |= TD_LSO;
5270                 opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift;
5271         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5272                 const struct iphdr *ip = ip_hdr(skb);
5273
5274                 if (ip->protocol == IPPROTO_TCP)
5275                         opts[offset] |= info->checksum.tcp;
5276                 else if (ip->protocol == IPPROTO_UDP)
5277                         opts[offset] |= info->checksum.udp;
5278                 else
5279                         WARN_ON_ONCE(1);
5280         }
5281 }
5282
5283 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5284                                       struct net_device *dev)
5285 {
5286         struct rtl8169_private *tp = netdev_priv(dev);
5287         unsigned int entry = tp->cur_tx % NUM_TX_DESC;
5288         struct TxDesc *txd = tp->TxDescArray + entry;
5289         void __iomem *ioaddr = tp->mmio_addr;
5290         struct device *d = &tp->pci_dev->dev;
5291         dma_addr_t mapping;
5292         u32 status, len;
5293         u32 opts[2];
5294         int frags;
5295
5296         if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
5297                 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
5298                 goto err_stop_0;
5299         }
5300
5301         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
5302                 goto err_stop_0;
5303
5304         len = skb_headlen(skb);
5305         mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
5306         if (unlikely(dma_mapping_error(d, mapping))) {
5307                 if (net_ratelimit())
5308                         netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
5309                 goto err_dma_0;
5310         }
5311
5312         tp->tx_skb[entry].len = len;
5313         txd->addr = cpu_to_le64(mapping);
5314
5315         opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
5316         opts[0] = DescOwn;
5317
5318         rtl8169_tso_csum(tp, skb, opts);
5319
5320         frags = rtl8169_xmit_frags(tp, skb, opts);
5321         if (frags < 0)
5322                 goto err_dma_1;
5323         else if (frags)
5324                 opts[0] |= FirstFrag;
5325         else {
5326                 opts[0] |= FirstFrag | LastFrag;
5327                 tp->tx_skb[entry].skb = skb;
5328         }
5329
5330         txd->opts2 = cpu_to_le32(opts[1]);
5331
5332         wmb();
5333
5334         /* Anti gcc 2.95.3 bugware (sic) */
5335         status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
5336         txd->opts1 = cpu_to_le32(status);
5337
5338         tp->cur_tx += frags + 1;
5339
5340         wmb();
5341
5342         RTL_W8(TxPoll, NPQ);
5343
5344         if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
5345                 netif_stop_queue(dev);
5346                 smp_rmb();
5347                 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
5348                         netif_wake_queue(dev);
5349         }
5350
5351         return NETDEV_TX_OK;
5352
5353 err_dma_1:
5354         rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
5355 err_dma_0:
5356         dev_kfree_skb(skb);
5357         dev->stats.tx_dropped++;
5358         return NETDEV_TX_OK;
5359
5360 err_stop_0:
5361         netif_stop_queue(dev);
5362         dev->stats.tx_dropped++;
5363         return NETDEV_TX_BUSY;
5364 }
5365
5366 static void rtl8169_pcierr_interrupt(struct net_device *dev)
5367 {
5368         struct rtl8169_private *tp = netdev_priv(dev);
5369         struct pci_dev *pdev = tp->pci_dev;
5370         u16 pci_status, pci_cmd;
5371
5372         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
5373         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
5374
5375         netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
5376                   pci_cmd, pci_status);
5377
5378         /*
5379          * The recovery sequence below admits a very elaborated explanation:
5380          * - it seems to work;
5381          * - I did not see what else could be done;
5382          * - it makes iop3xx happy.
5383          *
5384          * Feel free to adjust to your needs.
5385          */
5386         if (pdev->broken_parity_status)
5387                 pci_cmd &= ~PCI_COMMAND_PARITY;
5388         else
5389                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
5390
5391         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
5392
5393         pci_write_config_word(pdev, PCI_STATUS,
5394                 pci_status & (PCI_STATUS_DETECTED_PARITY |
5395                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
5396                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
5397
5398         /* The infamous DAC f*ckup only happens at boot time */
5399         if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
5400                 void __iomem *ioaddr = tp->mmio_addr;
5401
5402                 netif_info(tp, intr, dev, "disabling PCI DAC\n");
5403                 tp->cp_cmd &= ~PCIDAC;
5404                 RTL_W16(CPlusCmd, tp->cp_cmd);
5405                 dev->features &= ~NETIF_F_HIGHDMA;
5406         }
5407
5408         rtl8169_hw_reset(tp);
5409
5410         rtl8169_schedule_work(dev, rtl8169_reinit_task);
5411 }
5412
5413 static void rtl8169_tx_interrupt(struct net_device *dev,
5414                                  struct rtl8169_private *tp,
5415                                  void __iomem *ioaddr)
5416 {
5417         unsigned int dirty_tx, tx_left;
5418
5419         dirty_tx = tp->dirty_tx;
5420         smp_rmb();
5421         tx_left = tp->cur_tx - dirty_tx;
5422
5423         while (tx_left > 0) {
5424                 unsigned int entry = dirty_tx % NUM_TX_DESC;
5425                 struct ring_info *tx_skb = tp->tx_skb + entry;
5426                 u32 status;
5427
5428                 rmb();
5429                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
5430                 if (status & DescOwn)
5431                         break;
5432
5433                 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
5434                                      tp->TxDescArray + entry);
5435                 if (status & LastFrag) {
5436                         dev->stats.tx_packets++;
5437                         dev->stats.tx_bytes += tx_skb->skb->len;
5438                         dev_kfree_skb(tx_skb->skb);
5439                         tx_skb->skb = NULL;
5440                 }
5441                 dirty_tx++;
5442                 tx_left--;
5443         }
5444
5445         if (tp->dirty_tx != dirty_tx) {
5446                 tp->dirty_tx = dirty_tx;
5447                 smp_wmb();
5448                 if (netif_queue_stopped(dev) &&
5449                     (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
5450                         netif_wake_queue(dev);
5451                 }
5452                 /*
5453                  * 8168 hack: TxPoll requests are lost when the Tx packets are
5454                  * too close. Let's kick an extra TxPoll request when a burst
5455                  * of start_xmit activity is detected (if it is not detected,
5456                  * it is slow enough). -- FR
5457                  */
5458                 smp_rmb();
5459                 if (tp->cur_tx != dirty_tx)
5460                         RTL_W8(TxPoll, NPQ);
5461         }
5462 }
5463
5464 static inline int rtl8169_fragmented_frame(u32 status)
5465 {
5466         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
5467 }
5468
5469 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
5470 {
5471         u32 status = opts1 & RxProtoMask;
5472
5473         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
5474             ((status == RxProtoUDP) && !(opts1 & UDPFail)))
5475                 skb->ip_summed = CHECKSUM_UNNECESSARY;
5476         else
5477                 skb_checksum_none_assert(skb);
5478 }
5479
5480 static struct sk_buff *rtl8169_try_rx_copy(void *data,
5481                                            struct rtl8169_private *tp,
5482                                            int pkt_size,
5483                                            dma_addr_t addr)
5484 {
5485         struct sk_buff *skb;
5486         struct device *d = &tp->pci_dev->dev;
5487
5488         data = rtl8169_align(data);
5489         dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
5490         prefetch(data);
5491         skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
5492         if (skb)
5493                 memcpy(skb->data, data, pkt_size);
5494         dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
5495
5496         return skb;
5497 }
5498
5499 static int rtl8169_rx_interrupt(struct net_device *dev,
5500                                 struct rtl8169_private *tp,
5501                                 void __iomem *ioaddr, u32 budget)
5502 {
5503         unsigned int cur_rx, rx_left;
5504         unsigned int count;
5505
5506         cur_rx = tp->cur_rx;
5507         rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
5508         rx_left = min(rx_left, budget);
5509
5510         for (; rx_left > 0; rx_left--, cur_rx++) {
5511                 unsigned int entry = cur_rx % NUM_RX_DESC;
5512                 struct RxDesc *desc = tp->RxDescArray + entry;
5513                 u32 status;
5514
5515                 rmb();
5516                 status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
5517
5518                 if (status & DescOwn)
5519                         break;
5520                 if (unlikely(status & RxRES)) {
5521                         netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
5522                                    status);
5523                         dev->stats.rx_errors++;
5524                         if (status & (RxRWT | RxRUNT))
5525                                 dev->stats.rx_length_errors++;
5526                         if (status & RxCRC)
5527                                 dev->stats.rx_crc_errors++;
5528                         if (status & RxFOVF) {
5529                                 rtl8169_schedule_work(dev, rtl8169_reset_task);
5530                                 dev->stats.rx_fifo_errors++;
5531                         }
5532                         rtl8169_mark_to_asic(desc, rx_buf_sz);
5533                 } else {
5534                         struct sk_buff *skb;
5535                         dma_addr_t addr = le64_to_cpu(desc->addr);
5536                         int pkt_size = (status & 0x00001FFF) - 4;
5537
5538                         /*
5539                          * The driver does not support incoming fragmented
5540                          * frames. They are seen as a symptom of over-mtu
5541                          * sized frames.
5542                          */
5543                         if (unlikely(rtl8169_fragmented_frame(status))) {
5544                                 dev->stats.rx_dropped++;
5545                                 dev->stats.rx_length_errors++;
5546                                 rtl8169_mark_to_asic(desc, rx_buf_sz);
5547                                 continue;
5548                         }
5549
5550                         skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
5551                                                   tp, pkt_size, addr);
5552                         rtl8169_mark_to_asic(desc, rx_buf_sz);
5553                         if (!skb) {
5554                                 dev->stats.rx_dropped++;
5555                                 continue;
5556                         }
5557
5558                         rtl8169_rx_csum(skb, status);
5559                         skb_put(skb, pkt_size);
5560                         skb->protocol = eth_type_trans(skb, dev);
5561
5562                         rtl8169_rx_vlan_tag(desc, skb);
5563
5564                         napi_gro_receive(&tp->napi, skb);
5565
5566                         dev->stats.rx_bytes += pkt_size;
5567                         dev->stats.rx_packets++;
5568                 }
5569
5570                 /* Work around for AMD plateform. */
5571                 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
5572                     (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
5573                         desc->opts2 = 0;
5574                         cur_rx++;
5575                 }
5576         }
5577
5578         count = cur_rx - tp->cur_rx;
5579         tp->cur_rx = cur_rx;
5580
5581         tp->dirty_rx += count;
5582
5583         return count;
5584 }
5585
5586 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
5587 {
5588         struct net_device *dev = dev_instance;
5589         struct rtl8169_private *tp = netdev_priv(dev);
5590         void __iomem *ioaddr = tp->mmio_addr;
5591         int handled = 0;
5592         int status;
5593
5594         /* loop handling interrupts until we have no new ones or
5595          * we hit a invalid/hotplug case.
5596          */
5597         status = RTL_R16(IntrStatus);
5598         while (status && status != 0xffff) {
5599                 handled = 1;
5600
5601                 /* Handle all of the error cases first. These will reset
5602                  * the chip, so just exit the loop.
5603                  */
5604                 if (unlikely(!netif_running(dev))) {
5605                         rtl8169_hw_reset(tp);
5606                         break;
5607                 }
5608
5609                 if (unlikely(status & RxFIFOOver)) {
5610                         switch (tp->mac_version) {
5611                         /* Work around for rx fifo overflow */
5612                         case RTL_GIGA_MAC_VER_11:
5613                         case RTL_GIGA_MAC_VER_22:
5614                         case RTL_GIGA_MAC_VER_26:
5615                                 netif_stop_queue(dev);
5616                                 rtl8169_tx_timeout(dev);
5617                                 goto done;
5618                         /* Testers needed. */
5619                         case RTL_GIGA_MAC_VER_17:
5620                         case RTL_GIGA_MAC_VER_19:
5621                         case RTL_GIGA_MAC_VER_20:
5622                         case RTL_GIGA_MAC_VER_21:
5623                         case RTL_GIGA_MAC_VER_23:
5624                         case RTL_GIGA_MAC_VER_24:
5625                         case RTL_GIGA_MAC_VER_27:
5626                         case RTL_GIGA_MAC_VER_28:
5627                         case RTL_GIGA_MAC_VER_31:
5628                         /* Experimental science. Pktgen proof. */
5629                         case RTL_GIGA_MAC_VER_12:
5630                         case RTL_GIGA_MAC_VER_25:
5631                                 if (status == RxFIFOOver)
5632                                         goto done;
5633                                 break;
5634                         default:
5635                                 break;
5636                         }
5637                 }
5638
5639                 if (unlikely(status & SYSErr)) {
5640                         rtl8169_pcierr_interrupt(dev);
5641                         break;
5642                 }
5643
5644                 if (status & LinkChg)
5645                         __rtl8169_check_link_status(dev, tp, ioaddr, true);
5646
5647                 /* We need to see the lastest version of tp->intr_mask to
5648                  * avoid ignoring an MSI interrupt and having to wait for
5649                  * another event which may never come.
5650                  */
5651                 smp_rmb();
5652                 if (status & tp->intr_mask & tp->napi_event) {
5653                         RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
5654                         tp->intr_mask = ~tp->napi_event;
5655
5656                         if (likely(napi_schedule_prep(&tp->napi)))
5657                                 __napi_schedule(&tp->napi);
5658                         else
5659                                 netif_info(tp, intr, dev,
5660                                            "interrupt %04x in poll\n", status);
5661                 }
5662
5663                 /* We only get a new MSI interrupt when all active irq
5664                  * sources on the chip have been acknowledged. So, ack
5665                  * everything we've seen and check if new sources have become
5666                  * active to avoid blocking all interrupts from the chip.
5667                  */
5668                 RTL_W16(IntrStatus,
5669                         (status & RxFIFOOver) ? (status | RxOverflow) : status);
5670                 status = RTL_R16(IntrStatus);
5671         }
5672 done:
5673         return IRQ_RETVAL(handled);
5674 }
5675
5676 static int rtl8169_poll(struct napi_struct *napi, int budget)
5677 {
5678         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
5679         struct net_device *dev = tp->dev;
5680         void __iomem *ioaddr = tp->mmio_addr;
5681         int work_done;
5682
5683         work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
5684         rtl8169_tx_interrupt(dev, tp, ioaddr);
5685
5686         if (work_done < budget) {
5687                 napi_complete(napi);
5688
5689                 /* We need for force the visibility of tp->intr_mask
5690                  * for other CPUs, as we can loose an MSI interrupt
5691                  * and potentially wait for a retransmit timeout if we don't.
5692                  * The posted write to IntrMask is safe, as it will
5693                  * eventually make it to the chip and we won't loose anything
5694                  * until it does.
5695                  */
5696                 tp->intr_mask = 0xffff;
5697                 wmb();
5698                 RTL_W16(IntrMask, tp->intr_event);
5699         }
5700
5701         return work_done;
5702 }
5703
5704 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
5705 {
5706         struct rtl8169_private *tp = netdev_priv(dev);
5707
5708         if (tp->mac_version > RTL_GIGA_MAC_VER_06)
5709                 return;
5710
5711         dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
5712         RTL_W32(RxMissed, 0);
5713 }
5714
5715 static void rtl8169_down(struct net_device *dev)
5716 {
5717         struct rtl8169_private *tp = netdev_priv(dev);
5718         void __iomem *ioaddr = tp->mmio_addr;
5719
5720         del_timer_sync(&tp->timer);
5721
5722         netif_stop_queue(dev);
5723
5724         napi_disable(&tp->napi);
5725
5726         spin_lock_irq(&tp->lock);
5727
5728         rtl8169_hw_reset(tp);
5729         /*
5730          * At this point device interrupts can not be enabled in any function,
5731          * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task,
5732          * rtl8169_reinit_task) and napi is disabled (rtl8169_poll).
5733          */
5734         rtl8169_rx_missed(dev, ioaddr);
5735
5736         spin_unlock_irq(&tp->lock);
5737
5738         synchronize_irq(dev->irq);
5739
5740         /* Give a racing hard_start_xmit a few cycles to complete. */
5741         synchronize_sched();  /* FIXME: should this be synchronize_irq()? */
5742
5743         rtl8169_tx_clear(tp);
5744
5745         rtl8169_rx_clear(tp);
5746
5747         rtl_pll_power_down(tp);
5748 }
5749
5750 static int rtl8169_close(struct net_device *dev)
5751 {
5752         struct rtl8169_private *tp = netdev_priv(dev);
5753         struct pci_dev *pdev = tp->pci_dev;
5754
5755         pm_runtime_get_sync(&pdev->dev);
5756
5757         /* Update counters before going down */
5758         rtl8169_update_counters(dev);
5759
5760         rtl8169_down(dev);
5761
5762         free_irq(dev->irq, dev);
5763
5764         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
5765                           tp->RxPhyAddr);
5766         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
5767                           tp->TxPhyAddr);
5768         tp->TxDescArray = NULL;
5769         tp->RxDescArray = NULL;
5770
5771         pm_runtime_put_sync(&pdev->dev);
5772
5773         return 0;
5774 }
5775
5776 static void rtl_set_rx_mode(struct net_device *dev)
5777 {
5778         struct rtl8169_private *tp = netdev_priv(dev);
5779         void __iomem *ioaddr = tp->mmio_addr;
5780         unsigned long flags;
5781         u32 mc_filter[2];       /* Multicast hash filter */
5782         int rx_mode;
5783         u32 tmp = 0;
5784
5785         if (dev->flags & IFF_PROMISC) {
5786                 /* Unconditionally log net taps. */
5787                 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
5788                 rx_mode =
5789                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
5790                     AcceptAllPhys;
5791                 mc_filter[1] = mc_filter[0] = 0xffffffff;
5792         } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
5793                    (dev->flags & IFF_ALLMULTI)) {
5794                 /* Too many to filter perfectly -- accept all multicasts. */
5795                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
5796                 mc_filter[1] = mc_filter[0] = 0xffffffff;
5797         } else {
5798                 struct netdev_hw_addr *ha;
5799
5800                 rx_mode = AcceptBroadcast | AcceptMyPhys;
5801                 mc_filter[1] = mc_filter[0] = 0;
5802                 netdev_for_each_mc_addr(ha, dev) {
5803                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
5804                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
5805                         rx_mode |= AcceptMulticast;
5806                 }
5807         }
5808
5809         spin_lock_irqsave(&tp->lock, flags);
5810
5811         tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
5812
5813         if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
5814                 u32 data = mc_filter[0];
5815
5816                 mc_filter[0] = swab32(mc_filter[1]);
5817                 mc_filter[1] = swab32(data);
5818         }
5819
5820         RTL_W32(MAR0 + 4, mc_filter[1]);
5821         RTL_W32(MAR0 + 0, mc_filter[0]);
5822
5823         RTL_W32(RxConfig, tmp);
5824
5825         spin_unlock_irqrestore(&tp->lock, flags);
5826 }
5827
5828 /**
5829  *  rtl8169_get_stats - Get rtl8169 read/write statistics
5830  *  @dev: The Ethernet Device to get statistics for
5831  *
5832  *  Get TX/RX statistics for rtl8169
5833  */
5834 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
5835 {
5836         struct rtl8169_private *tp = netdev_priv(dev);
5837         void __iomem *ioaddr = tp->mmio_addr;
5838         unsigned long flags;
5839
5840         if (netif_running(dev)) {
5841                 spin_lock_irqsave(&tp->lock, flags);
5842                 rtl8169_rx_missed(dev, ioaddr);
5843                 spin_unlock_irqrestore(&tp->lock, flags);
5844         }
5845
5846         return &dev->stats;
5847 }
5848
5849 static void rtl8169_net_suspend(struct net_device *dev)
5850 {
5851         struct rtl8169_private *tp = netdev_priv(dev);
5852
5853         if (!netif_running(dev))
5854                 return;
5855
5856         rtl_pll_power_down(tp);
5857
5858         netif_device_detach(dev);
5859         netif_stop_queue(dev);
5860 }
5861
5862 #ifdef CONFIG_PM
5863
5864 static int rtl8169_suspend(struct device *device)
5865 {
5866         struct pci_dev *pdev = to_pci_dev(device);
5867         struct net_device *dev = pci_get_drvdata(pdev);
5868
5869         rtl8169_net_suspend(dev);
5870
5871         return 0;
5872 }
5873
5874 static void __rtl8169_resume(struct net_device *dev)
5875 {
5876         struct rtl8169_private *tp = netdev_priv(dev);
5877
5878         netif_device_attach(dev);
5879
5880         rtl_pll_power_up(tp);
5881
5882         rtl8169_schedule_work(dev, rtl8169_reset_task);
5883 }
5884
5885 static int rtl8169_resume(struct device *device)
5886 {
5887         struct pci_dev *pdev = to_pci_dev(device);
5888         struct net_device *dev = pci_get_drvdata(pdev);
5889         struct rtl8169_private *tp = netdev_priv(dev);
5890
5891         rtl8169_init_phy(dev, tp);
5892
5893         if (netif_running(dev))
5894                 __rtl8169_resume(dev);
5895
5896         return 0;
5897 }
5898
5899 static int rtl8169_runtime_suspend(struct device *device)
5900 {
5901         struct pci_dev *pdev = to_pci_dev(device);
5902         struct net_device *dev = pci_get_drvdata(pdev);
5903         struct rtl8169_private *tp = netdev_priv(dev);
5904
5905         if (!tp->TxDescArray)
5906                 return 0;
5907
5908         spin_lock_irq(&tp->lock);
5909         tp->saved_wolopts = __rtl8169_get_wol(tp);
5910         __rtl8169_set_wol(tp, WAKE_ANY);
5911         spin_unlock_irq(&tp->lock);
5912
5913         rtl8169_net_suspend(dev);
5914
5915         return 0;
5916 }
5917
5918 static int rtl8169_runtime_resume(struct device *device)
5919 {
5920         struct pci_dev *pdev = to_pci_dev(device);
5921         struct net_device *dev = pci_get_drvdata(pdev);
5922         struct rtl8169_private *tp = netdev_priv(dev);
5923
5924         if (!tp->TxDescArray)
5925                 return 0;
5926
5927         spin_lock_irq(&tp->lock);
5928         __rtl8169_set_wol(tp, tp->saved_wolopts);
5929         tp->saved_wolopts = 0;
5930         spin_unlock_irq(&tp->lock);
5931
5932         rtl8169_init_phy(dev, tp);
5933
5934         __rtl8169_resume(dev);
5935
5936         return 0;
5937 }
5938
5939 static int rtl8169_runtime_idle(struct device *device)
5940 {
5941         struct pci_dev *pdev = to_pci_dev(device);
5942         struct net_device *dev = pci_get_drvdata(pdev);
5943         struct rtl8169_private *tp = netdev_priv(dev);
5944
5945         return tp->TxDescArray ? -EBUSY : 0;
5946 }
5947
5948 static const struct dev_pm_ops rtl8169_pm_ops = {
5949         .suspend                = rtl8169_suspend,
5950         .resume                 = rtl8169_resume,
5951         .freeze                 = rtl8169_suspend,
5952         .thaw                   = rtl8169_resume,
5953         .poweroff               = rtl8169_suspend,
5954         .restore                = rtl8169_resume,
5955         .runtime_suspend        = rtl8169_runtime_suspend,
5956         .runtime_resume         = rtl8169_runtime_resume,
5957         .runtime_idle           = rtl8169_runtime_idle,
5958 };
5959
5960 #define RTL8169_PM_OPS  (&rtl8169_pm_ops)
5961
5962 #else /* !CONFIG_PM */
5963
5964 #define RTL8169_PM_OPS  NULL
5965
5966 #endif /* !CONFIG_PM */
5967
5968 static void rtl_shutdown(struct pci_dev *pdev)
5969 {
5970         struct net_device *dev = pci_get_drvdata(pdev);
5971         struct rtl8169_private *tp = netdev_priv(dev);
5972         void __iomem *ioaddr = tp->mmio_addr;
5973
5974         rtl8169_net_suspend(dev);
5975
5976         /* Restore original MAC address */
5977         rtl_rar_set(tp, dev->perm_addr);
5978
5979         spin_lock_irq(&tp->lock);
5980
5981         rtl8169_hw_reset(tp);
5982
5983         spin_unlock_irq(&tp->lock);
5984
5985         if (system_state == SYSTEM_POWER_OFF) {
5986                 /* WoL fails with 8168b when the receiver is disabled. */
5987                 if ((tp->mac_version == RTL_GIGA_MAC_VER_11 ||
5988                      tp->mac_version == RTL_GIGA_MAC_VER_12 ||
5989                      tp->mac_version == RTL_GIGA_MAC_VER_17) &&
5990                     (tp->features & RTL_FEATURE_WOL)) {
5991                         pci_clear_master(pdev);
5992
5993                         RTL_W8(ChipCmd, CmdRxEnb);
5994                         /* PCI commit */
5995                         RTL_R8(ChipCmd);
5996                 }
5997
5998                 pci_wake_from_d3(pdev, true);
5999                 pci_set_power_state(pdev, PCI_D3hot);
6000         }
6001 }
6002
6003 static struct pci_driver rtl8169_pci_driver = {
6004         .name           = MODULENAME,
6005         .id_table       = rtl8169_pci_tbl,
6006         .probe          = rtl8169_init_one,
6007         .remove         = __devexit_p(rtl8169_remove_one),
6008         .shutdown       = rtl_shutdown,
6009         .driver.pm      = RTL8169_PM_OPS,
6010 };
6011
6012 static int __init rtl8169_init_module(void)
6013 {
6014         return pci_register_driver(&rtl8169_pci_driver);
6015 }
6016
6017 static void __exit rtl8169_cleanup_module(void)
6018 {
6019         pci_unregister_driver(&rtl8169_pci_driver);
6020 }
6021
6022 module_init(rtl8169_init_module);
6023 module_exit(rtl8169_cleanup_module);