drivers/net/ethernet/realtek/r8169.c

   1 /*
   2  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   3  *
   4  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   5  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   6  * Copyright (c) a lot of people too. Please respect their work.
   7  *
   8  * See MAINTAINERS file for support contact information.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/moduleparam.h>
  13 #include <linux/pci.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/delay.h>
  17 #include <linux/ethtool.h>
  18 #include <linux/mii.h>
  19 #include <linux/if_vlan.h>
  20 #include <linux/crc32.h>
  21 #include <linux/in.h>
  22 #include <linux/ip.h>
  23 #include <linux/tcp.h>
  24 #include <linux/init.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/pm_runtime.h>
  28 #include <linux/firmware.h>
  29 #include <linux/pci-aspm.h>
  30 #include <linux/prefetch.h>
  31
  32 #include <asm/io.h>
  33 #include <asm/irq.h>
  34
  35 #define RTL8169_VERSION "2.3LK-NAPI"
  36 #define MODULENAME "r8169"
  37 #define PFX MODULENAME ": "
  38
  39 #define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
  40 #define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
  41 #define FIRMWARE_8168E_1        "rtl_nic/rtl8168e-1.fw"
  42 #define FIRMWARE_8168E_2        "rtl_nic/rtl8168e-2.fw"
  43 #define FIRMWARE_8168E_3        "rtl_nic/rtl8168e-3.fw"
  44 #define FIRMWARE_8168F_1        "rtl_nic/rtl8168f-1.fw"
  45 #define FIRMWARE_8168F_2        "rtl_nic/rtl8168f-2.fw"
  46 #define FIRMWARE_8105E_1        "rtl_nic/rtl8105e-1.fw"
  47
  48 #ifdef RTL8169_DEBUG
  49 #define assert(expr) \
  50         if (!(expr)) {                                  \
  51                 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
  52                 #expr,__FILE__,__func__,__LINE__);              \
  53         }
  54 #define dprintk(fmt, args...) \
  55         do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
  56 #else
  57 #define assert(expr) do {} while (0)
  58 #define dprintk(fmt, args...)   do {} while (0)
  59 #endif /* RTL8169_DEBUG */
  60
  61 #define R8169_MSG_DEFAULT \
  62         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  63
  64 #define TX_BUFFS_AVAIL(tp) \
  65         (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
  66
  67 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  68    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  69 static const int multicast_filter_limit = 32;
  70
  71 #define MAX_READ_REQUEST_SHIFT  12
  72 #define TX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
  73 #define SafeMtu         0x1c20  /* ... actually life sucks beyond ~7k */
  74 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  75
  76 #define R8169_REGS_SIZE         256
  77 #define R8169_NAPI_WEIGHT       64
  78 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
  79 #define NUM_RX_DESC     256     /* Number of Rx descriptor registers */
  80 #define RX_BUF_SIZE     1536    /* Rx Buffer size */
  81 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  82 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  83
  84 #define RTL8169_TX_TIMEOUT      (6*HZ)
  85 #define RTL8169_PHY_TIMEOUT     (10*HZ)
  86
  87 #define RTL_EEPROM_SIG          cpu_to_le32(0x8129)
  88 #define RTL_EEPROM_SIG_MASK     cpu_to_le32(0xffff)
  89 #define RTL_EEPROM_SIG_ADDR     0x0000
  90
  91 /* write/read MMIO register */
  92 #define RTL_W8(reg, val8)       writeb ((val8), ioaddr + (reg))
  93 #define RTL_W16(reg, val16)     writew ((val16), ioaddr + (reg))
  94 #define RTL_W32(reg, val32)     writel ((val32), ioaddr + (reg))
  95 #define RTL_R8(reg)             readb (ioaddr + (reg))
  96 #define RTL_R16(reg)            readw (ioaddr + (reg))
  97 #define RTL_R32(reg)            readl (ioaddr + (reg))
  98
  99 enum mac_version {
 100         RTL_GIGA_MAC_VER_01 = 0,
 101         RTL_GIGA_MAC_VER_02,
 102         RTL_GIGA_MAC_VER_03,
 103         RTL_GIGA_MAC_VER_04,
 104         RTL_GIGA_MAC_VER_05,
 105         RTL_GIGA_MAC_VER_06,
 106         RTL_GIGA_MAC_VER_07,
 107         RTL_GIGA_MAC_VER_08,
 108         RTL_GIGA_MAC_VER_09,
 109         RTL_GIGA_MAC_VER_10,
 110         RTL_GIGA_MAC_VER_11,
 111         RTL_GIGA_MAC_VER_12,
 112         RTL_GIGA_MAC_VER_13,
 113         RTL_GIGA_MAC_VER_14,
 114         RTL_GIGA_MAC_VER_15,
 115         RTL_GIGA_MAC_VER_16,
 116         RTL_GIGA_MAC_VER_17,
 117         RTL_GIGA_MAC_VER_18,
 118         RTL_GIGA_MAC_VER_19,
 119         RTL_GIGA_MAC_VER_20,
 120         RTL_GIGA_MAC_VER_21,
 121         RTL_GIGA_MAC_VER_22,
 122         RTL_GIGA_MAC_VER_23,
 123         RTL_GIGA_MAC_VER_24,
 124         RTL_GIGA_MAC_VER_25,
 125         RTL_GIGA_MAC_VER_26,
 126         RTL_GIGA_MAC_VER_27,
 127         RTL_GIGA_MAC_VER_28,
 128         RTL_GIGA_MAC_VER_29,
 129         RTL_GIGA_MAC_VER_30,
 130         RTL_GIGA_MAC_VER_31,
 131         RTL_GIGA_MAC_VER_32,
 132         RTL_GIGA_MAC_VER_33,
 133         RTL_GIGA_MAC_VER_34,
 134         RTL_GIGA_MAC_VER_35,
 135         RTL_GIGA_MAC_VER_36,
 136         RTL_GIGA_MAC_NONE   = 0xff,
 137 };
 138
 139 enum rtl_tx_desc_version {
 140         RTL_TD_0        = 0,
 141         RTL_TD_1        = 1,
 142 };
 143
 144 #define JUMBO_1K        ETH_DATA_LEN
 145 #define JUMBO_4K        (4*1024 - ETH_HLEN - 2)
 146 #define JUMBO_6K        (6*1024 - ETH_HLEN - 2)
 147 #define JUMBO_7K        (7*1024 - ETH_HLEN - 2)
 148 #define JUMBO_9K        (9*1024 - ETH_HLEN - 2)
 149
 150 #define _R(NAME,TD,FW,SZ,B) {   \
 151         .name = NAME,           \
 152         .txd_version = TD,      \
 153         .fw_name = FW,          \
 154         .jumbo_max = SZ,        \
 155         .jumbo_tx_csum = B      \
 156 }
 157
 158 static const struct {
 159         const char *name;
 160         enum rtl_tx_desc_version txd_version;
 161         const char *fw_name;
 162         u16 jumbo_max;
 163         bool jumbo_tx_csum;
 164 } rtl_chip_infos[] = {
 165         /* PCI devices. */
 166         [RTL_GIGA_MAC_VER_01] =
 167                 _R("RTL8169",           RTL_TD_0, NULL, JUMBO_7K, true),
 168         [RTL_GIGA_MAC_VER_02] =
 169                 _R("RTL8169s",          RTL_TD_0, NULL, JUMBO_7K, true),
 170         [RTL_GIGA_MAC_VER_03] =
 171                 _R("RTL8110s",          RTL_TD_0, NULL, JUMBO_7K, true),
 172         [RTL_GIGA_MAC_VER_04] =
 173                 _R("RTL8169sb/8110sb",  RTL_TD_0, NULL, JUMBO_7K, true),
 174         [RTL_GIGA_MAC_VER_05] =
 175                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL, JUMBO_7K, true),
 176         [RTL_GIGA_MAC_VER_06] =
 177                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL, JUMBO_7K, true),
 178         /* PCI-E devices. */
 179         [RTL_GIGA_MAC_VER_07] =
 180                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 181         [RTL_GIGA_MAC_VER_08] =
 182                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 183         [RTL_GIGA_MAC_VER_09] =
 184                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 185         [RTL_GIGA_MAC_VER_10] =
 186                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 187         [RTL_GIGA_MAC_VER_11] =
 188                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K, false),
 189         [RTL_GIGA_MAC_VER_12] =
 190                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K, false),
 191         [RTL_GIGA_MAC_VER_13] =
 192                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 193         [RTL_GIGA_MAC_VER_14] =
 194                 _R("RTL8100e",          RTL_TD_0, NULL, JUMBO_1K, true),
 195         [RTL_GIGA_MAC_VER_15] =
 196                 _R("RTL8100e",          RTL_TD_0, NULL, JUMBO_1K, true),
 197         [RTL_GIGA_MAC_VER_16] =
 198                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 199         [RTL_GIGA_MAC_VER_17] =
 200                 _R("RTL8168b/8111b",    RTL_TD_1, NULL, JUMBO_4K, false),
 201         [RTL_GIGA_MAC_VER_18] =
 202                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 203         [RTL_GIGA_MAC_VER_19] =
 204                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 205         [RTL_GIGA_MAC_VER_20] =
 206                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 207         [RTL_GIGA_MAC_VER_21] =
 208                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 209         [RTL_GIGA_MAC_VER_22] =
 210                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 211         [RTL_GIGA_MAC_VER_23] =
 212                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 213         [RTL_GIGA_MAC_VER_24] =
 214                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 215         [RTL_GIGA_MAC_VER_25] =
 216                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_1,
 217                                                         JUMBO_9K, false),
 218         [RTL_GIGA_MAC_VER_26] =
 219                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_2,
 220                                                         JUMBO_9K, false),
 221         [RTL_GIGA_MAC_VER_27] =
 222                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 223         [RTL_GIGA_MAC_VER_28] =
 224                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 225         [RTL_GIGA_MAC_VER_29] =
 226                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1,
 227                                                         JUMBO_1K, true),
 228         [RTL_GIGA_MAC_VER_30] =
 229                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1,
 230                                                         JUMBO_1K, true),
 231         [RTL_GIGA_MAC_VER_31] =
 232                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 233         [RTL_GIGA_MAC_VER_32] =
 234                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_1,
 235                                                         JUMBO_9K, false),
 236         [RTL_GIGA_MAC_VER_33] =
 237                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_2,
 238                                                         JUMBO_9K, false),
 239         [RTL_GIGA_MAC_VER_34] =
 240                 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3,
 241                                                         JUMBO_9K, false),
 242         [RTL_GIGA_MAC_VER_35] =
 243                 _R("RTL8168f/8111f",    RTL_TD_1, FIRMWARE_8168F_1,
 244                                                         JUMBO_9K, false),
 245         [RTL_GIGA_MAC_VER_36] =
 246                 _R("RTL8168f/8111f",    RTL_TD_1, FIRMWARE_8168F_2,
 247                                                         JUMBO_9K, false),
 248 };
 249 #undef _R
 250
 251 enum cfg_version {
 252         RTL_CFG_0 = 0x00,
 253         RTL_CFG_1,
 254         RTL_CFG_2
 255 };
 256
 257 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
 258         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8129), 0, 0, RTL_CFG_0 },
 259         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8136), 0, 0, RTL_CFG_2 },
 260         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8167), 0, 0, RTL_CFG_0 },
 261         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8168), 0, 0, RTL_CFG_1 },
 262         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8169), 0, 0, RTL_CFG_0 },
 263         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4300), 0, 0, RTL_CFG_0 },
 264         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4302), 0, 0, RTL_CFG_0 },
 265         { PCI_DEVICE(PCI_VENDOR_ID_AT,          0xc107), 0, 0, RTL_CFG_0 },
 266         { PCI_DEVICE(0x16ec,                    0x0116), 0, 0, RTL_CFG_0 },
 267         { PCI_VENDOR_ID_LINKSYS,                0x1032,
 268                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
 269         { 0x0001,                               0x8168,
 270                 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
 271         {0,},
 272 };
 273
 274 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 275
 276 static int rx_buf_sz = 16383;
 277 static int use_dac;
 278 static struct {
 279         u32 msg_enable;
 280 } debug = { -1 };
 281
 282 enum rtl_registers {
 283         MAC0            = 0,    /* Ethernet hardware address. */
 284         MAC4            = 4,
 285         MAR0            = 8,    /* Multicast filter. */
 286         CounterAddrLow          = 0x10,
 287         CounterAddrHigh         = 0x14,
 288         TxDescStartAddrLow      = 0x20,
 289         TxDescStartAddrHigh     = 0x24,
 290         TxHDescStartAddrLow     = 0x28,
 291         TxHDescStartAddrHigh    = 0x2c,
 292         FLASH           = 0x30,
 293         ERSR            = 0x36,
 294         ChipCmd         = 0x37,
 295         TxPoll          = 0x38,
 296         IntrMask        = 0x3c,
 297         IntrStatus      = 0x3e,
 298
 299         TxConfig        = 0x40,
 300 #define TXCFG_AUTO_FIFO                 (1 << 7)        /* 8111e-vl */
 301 #define TXCFG_EMPTY                     (1 << 11)       /* 8111e-vl */
 302
 303         RxConfig        = 0x44,
 304 #define RX128_INT_EN                    (1 << 15)       /* 8111c and later */
 305 #define RX_MULTI_EN                     (1 << 14)       /* 8111c only */
 306 #define RXCFG_FIFO_SHIFT                13
 307                                         /* No threshold before first PCI xfer */
 308 #define RX_FIFO_THRESH                  (7 << RXCFG_FIFO_SHIFT)
 309 #define RXCFG_DMA_SHIFT                 8
 310                                         /* Unlimited maximum PCI burst. */
 311 #define RX_DMA_BURST                    (7 << RXCFG_DMA_SHIFT)
 312
 313         RxMissed        = 0x4c,
 314         Cfg9346         = 0x50,
 315         Config0         = 0x51,
 316         Config1         = 0x52,
 317         Config2         = 0x53,
 318         Config3         = 0x54,
 319         Config4         = 0x55,
 320         Config5         = 0x56,
 321         MultiIntr       = 0x5c,
 322         PHYAR           = 0x60,
 323         PHYstatus       = 0x6c,
 324         RxMaxSize       = 0xda,
 325         CPlusCmd        = 0xe0,
 326         IntrMitigate    = 0xe2,
 327         RxDescAddrLow   = 0xe4,
 328         RxDescAddrHigh  = 0xe8,
 329         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
 330
 331 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
 332
 333         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
 334
 335 #define TxPacketMax     (8064 >> 7)
 336 #define EarlySize       0x27
 337
 338         FuncEvent       = 0xf0,
 339         FuncEventMask   = 0xf4,
 340         FuncPresetState = 0xf8,
 341         FuncForceEvent  = 0xfc,
 342 };
 343
 344 enum rtl8110_registers {
 345         TBICSR                  = 0x64,
 346         TBI_ANAR                = 0x68,
 347         TBI_LPAR                = 0x6a,
 348 };
 349
 350 enum rtl8168_8101_registers {
 351         CSIDR                   = 0x64,
 352         CSIAR                   = 0x68,
 353 #define CSIAR_FLAG                      0x80000000
 354 #define CSIAR_WRITE_CMD                 0x80000000
 355 #define CSIAR_BYTE_ENABLE               0x0f
 356 #define CSIAR_BYTE_ENABLE_SHIFT         12
 357 #define CSIAR_ADDR_MASK                 0x0fff
 358         PMCH                    = 0x6f,
 359         EPHYAR                  = 0x80,
 360 #define EPHYAR_FLAG                     0x80000000
 361 #define EPHYAR_WRITE_CMD                0x80000000
 362 #define EPHYAR_REG_MASK                 0x1f
 363 #define EPHYAR_REG_SHIFT                16
 364 #define EPHYAR_DATA_MASK                0xffff
 365         DLLPR                   = 0xd0,
 366 #define PFM_EN                          (1 << 6)
 367         DBG_REG                 = 0xd1,
 368 #define FIX_NAK_1                       (1 << 4)
 369 #define FIX_NAK_2                       (1 << 3)
 370         TWSI                    = 0xd2,
 371         MCU                     = 0xd3,
 372 #define NOW_IS_OOB                      (1 << 7)
 373 #define EN_NDP                          (1 << 3)
 374 #define EN_OOB_RESET                    (1 << 2)
 375         EFUSEAR                 = 0xdc,
 376 #define EFUSEAR_FLAG                    0x80000000
 377 #define EFUSEAR_WRITE_CMD               0x80000000
 378 #define EFUSEAR_READ_CMD                0x00000000
 379 #define EFUSEAR_REG_MASK                0x03ff
 380 #define EFUSEAR_REG_SHIFT               8
 381 #define EFUSEAR_DATA_MASK               0xff
 382 };
 383
 384 enum rtl8168_registers {
 385         LED_FREQ                = 0x1a,
 386         EEE_LED                 = 0x1b,
 387         ERIDR                   = 0x70,
 388         ERIAR                   = 0x74,
 389 #define ERIAR_FLAG                      0x80000000
 390 #define ERIAR_WRITE_CMD                 0x80000000
 391 #define ERIAR_READ_CMD                  0x00000000
 392 #define ERIAR_ADDR_BYTE_ALIGN           4
 393 #define ERIAR_TYPE_SHIFT                16
 394 #define ERIAR_EXGMAC                    (0x00 << ERIAR_TYPE_SHIFT)
 395 #define ERIAR_MSIX                      (0x01 << ERIAR_TYPE_SHIFT)
 396 #define ERIAR_ASF                       (0x02 << ERIAR_TYPE_SHIFT)
 397 #define ERIAR_MASK_SHIFT                12
 398 #define ERIAR_MASK_0001                 (0x1 << ERIAR_MASK_SHIFT)
 399 #define ERIAR_MASK_0011                 (0x3 << ERIAR_MASK_SHIFT)
 400 #define ERIAR_MASK_1111                 (0xf << ERIAR_MASK_SHIFT)
 401         EPHY_RXER_NUM           = 0x7c,
 402         OCPDR                   = 0xb0, /* OCP GPHY access */
 403 #define OCPDR_WRITE_CMD                 0x80000000
 404 #define OCPDR_READ_CMD                  0x00000000
 405 #define OCPDR_REG_MASK                  0x7f
 406 #define OCPDR_GPHY_REG_SHIFT            16
 407 #define OCPDR_DATA_MASK                 0xffff
 408         OCPAR                   = 0xb4,
 409 #define OCPAR_FLAG                      0x80000000
 410 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
 411 #define OCPAR_GPHY_READ_CMD             0x0000f060
 412         RDSAR1                  = 0xd0, /* 8168c only. Undocumented on 8168dp */
 413         MISC                    = 0xf0, /* 8168e only. */
 414 #define TXPLA_RST                       (1 << 29)
 415 #define PWM_EN                          (1 << 22)
 416 };
 417
 418 enum rtl_register_content {
 419         /* InterruptStatusBits */
 420         SYSErr          = 0x8000,
 421         PCSTimeout      = 0x4000,
 422         SWInt           = 0x0100,
 423         TxDescUnavail   = 0x0080,
 424         RxFIFOOver      = 0x0040,
 425         LinkChg         = 0x0020,
 426         RxOverflow      = 0x0010,
 427         TxErr           = 0x0008,
 428         TxOK            = 0x0004,
 429         RxErr           = 0x0002,
 430         RxOK            = 0x0001,
 431
 432         /* RxStatusDesc */
 433         RxBOVF  = (1 << 24),
 434         RxFOVF  = (1 << 23),
 435         RxRWT   = (1 << 22),
 436         RxRES   = (1 << 21),
 437         RxRUNT  = (1 << 20),
 438         RxCRC   = (1 << 19),
 439
 440         /* ChipCmdBits */
 441         StopReq         = 0x80,
 442         CmdReset        = 0x10,
 443         CmdRxEnb        = 0x08,
 444         CmdTxEnb        = 0x04,
 445         RxBufEmpty      = 0x01,
 446
 447         /* TXPoll register p.5 */
 448         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 449         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 450         FSWInt          = 0x01,         /* Forced software interrupt */
 451
 452         /* Cfg9346Bits */
 453         Cfg9346_Lock    = 0x00,
 454         Cfg9346_Unlock  = 0xc0,
 455
 456         /* rx_mode_bits */
 457         AcceptErr       = 0x20,
 458         AcceptRunt      = 0x10,
 459         AcceptBroadcast = 0x08,
 460         AcceptMulticast = 0x04,
 461         AcceptMyPhys    = 0x02,
 462         AcceptAllPhys   = 0x01,
 463 #define RX_CONFIG_ACCEPT_MASK           0x3f
 464
 465         /* TxConfigBits */
 466         TxInterFrameGapShift = 24,
 467         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 468
 469         /* Config1 register p.24 */
 470         LEDS1           = (1 << 7),
 471         LEDS0           = (1 << 6),
 472         Speed_down      = (1 << 4),
 473         MEMMAP          = (1 << 3),
 474         IOMAP           = (1 << 2),
 475         VPD             = (1 << 1),
 476         PMEnable        = (1 << 0),     /* Power Management Enable */
 477
 478         /* Config2 register p. 25 */
 479         MSIEnable       = (1 << 5),     /* 8169 only. Reserved in the 8168. */
 480         PCI_Clock_66MHz = 0x01,
 481         PCI_Clock_33MHz = 0x00,
 482
 483         /* Config3 register p.25 */
 484         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 485         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 486         Jumbo_En0       = (1 << 2),     /* 8168 only. Reserved in the 8168b */
 487         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
 488
 489         /* Config4 register */
 490         Jumbo_En1       = (1 << 1),     /* 8168 only. Reserved in the 8168b */
 491
 492         /* Config5 register p.27 */
 493         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 494         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 495         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 496         Spi_en          = (1 << 3),
 497         LanWake         = (1 << 1),     /* LanWake enable/disable */
 498         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 499
 500         /* TBICSR p.28 */
 501         TBIReset        = 0x80000000,
 502         TBILoopback     = 0x40000000,
 503         TBINwEnable     = 0x20000000,
 504         TBINwRestart    = 0x10000000,
 505         TBILinkOk       = 0x02000000,
 506         TBINwComplete   = 0x01000000,
 507
 508         /* CPlusCmd p.31 */
 509         EnableBist      = (1 << 15),    // 8168 8101
 510         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
 511         Normal_mode     = (1 << 13),    // unused
 512         Force_half_dup  = (1 << 12),    // 8168 8101
 513         Force_rxflow_en = (1 << 11),    // 8168 8101
 514         Force_txflow_en = (1 << 10),    // 8168 8101
 515         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
 516         ASF             = (1 << 8),     // 8168 8101
 517         PktCntrDisable  = (1 << 7),     // 8168 8101
 518         Mac_dbgo_sel    = 0x001c,       // 8168
 519         RxVlan          = (1 << 6),
 520         RxChkSum        = (1 << 5),
 521         PCIDAC          = (1 << 4),
 522         PCIMulRW        = (1 << 3),
 523         INTT_0          = 0x0000,       // 8168
 524         INTT_1          = 0x0001,       // 8168
 525         INTT_2          = 0x0002,       // 8168
 526         INTT_3          = 0x0003,       // 8168
 527
 528         /* rtl8169_PHYstatus */
 529         TBI_Enable      = 0x80,
 530         TxFlowCtrl      = 0x40,
 531         RxFlowCtrl      = 0x20,
 532         _1000bpsF       = 0x10,
 533         _100bps         = 0x08,
 534         _10bps          = 0x04,
 535         LinkStatus      = 0x02,
 536         FullDup         = 0x01,
 537
 538         /* _TBICSRBit */
 539         TBILinkOK       = 0x02000000,
 540
 541         /* DumpCounterCommand */
 542         CounterDump     = 0x8,
 543 };
 544
 545 enum rtl_desc_bit {
 546         /* First doubleword. */
 547         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 548         RingEnd         = (1 << 30), /* End of descriptor ring */
 549         FirstFrag       = (1 << 29), /* First segment of a packet */
 550         LastFrag        = (1 << 28), /* Final segment of a packet */
 551 };
 552
 553 /* Generic case. */
 554 enum rtl_tx_desc_bit {
 555         /* First doubleword. */
 556         TD_LSO          = (1 << 27),            /* Large Send Offload */
 557 #define TD_MSS_MAX                      0x07ffu /* MSS value */
 558
 559         /* Second doubleword. */
 560         TxVlanTag       = (1 << 17),            /* Add VLAN tag */
 561 };
 562
 563 /* 8169, 8168b and 810x except 8102e. */
 564 enum rtl_tx_desc_bit_0 {
 565         /* First doubleword. */
 566 #define TD0_MSS_SHIFT                   16      /* MSS position (11 bits) */
 567         TD0_TCP_CS      = (1 << 16),            /* Calculate TCP/IP checksum */
 568         TD0_UDP_CS      = (1 << 17),            /* Calculate UDP/IP checksum */
 569         TD0_IP_CS       = (1 << 18),            /* Calculate IP checksum */
 570 };
 571
 572 /* 8102e, 8168c and beyond. */
 573 enum rtl_tx_desc_bit_1 {
 574         /* Second doubleword. */
 575 #define TD1_MSS_SHIFT                   18      /* MSS position (11 bits) */
 576         TD1_IP_CS       = (1 << 29),            /* Calculate IP checksum */
 577         TD1_TCP_CS      = (1 << 30),            /* Calculate TCP/IP checksum */
 578         TD1_UDP_CS      = (1 << 31),            /* Calculate UDP/IP checksum */
 579 };
 580
 581 static const struct rtl_tx_desc_info {
 582         struct {
 583                 u32 udp;
 584                 u32 tcp;
 585         } checksum;
 586         u16 mss_shift;
 587         u16 opts_offset;
 588 } tx_desc_info [] = {
 589         [RTL_TD_0] = {
 590                 .checksum = {
 591                         .udp    = TD0_IP_CS | TD0_UDP_CS,
 592                         .tcp    = TD0_IP_CS | TD0_TCP_CS
 593                 },
 594                 .mss_shift      = TD0_MSS_SHIFT,
 595                 .opts_offset    = 0
 596         },
 597         [RTL_TD_1] = {
 598                 .checksum = {
 599                         .udp    = TD1_IP_CS | TD1_UDP_CS,
 600                         .tcp    = TD1_IP_CS | TD1_TCP_CS
 601                 },
 602                 .mss_shift      = TD1_MSS_SHIFT,
 603                 .opts_offset    = 1
 604         }
 605 };
 606
 607 enum rtl_rx_desc_bit {
 608         /* Rx private */
 609         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 610         PID0            = (1 << 17), /* Protocol ID bit 2/2 */
 611
 612 #define RxProtoUDP      (PID1)
 613 #define RxProtoTCP      (PID0)
 614 #define RxProtoIP       (PID1 | PID0)
 615 #define RxProtoMask     RxProtoIP
 616
 617         IPFail          = (1 << 16), /* IP checksum failed */
 618         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 619         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 620         RxVlanTag       = (1 << 16), /* VLAN tag available */
 621 };
 622
 623 #define RsvdMask        0x3fffc000
 624
 625 struct TxDesc {
 626         __le32 opts1;
 627         __le32 opts2;
 628         __le64 addr;
 629 };
 630
 631 struct RxDesc {
 632         __le32 opts1;
 633         __le32 opts2;
 634         __le64 addr;
 635 };
 636
 637 struct ring_info {
 638         struct sk_buff  *skb;
 639         u32             len;
 640         u8              __pad[sizeof(void *) - sizeof(u32)];
 641 };
 642
 643 enum features {
 644         RTL_FEATURE_WOL         = (1 << 0),
 645         RTL_FEATURE_MSI         = (1 << 1),
 646         RTL_FEATURE_GMII        = (1 << 2),
 647 };
 648
 649 struct rtl8169_counters {
 650         __le64  tx_packets;
 651         __le64  rx_packets;
 652         __le64  tx_errors;
 653         __le32  rx_errors;
 654         __le16  rx_missed;
 655         __le16  align_errors;
 656         __le32  tx_one_collision;
 657         __le32  tx_multi_collision;
 658         __le64  rx_unicast;
 659         __le64  rx_broadcast;
 660         __le32  rx_multicast;
 661         __le16  tx_aborted;
 662         __le16  tx_underun;
 663 };
 664
 665 enum rtl_flag {
 666         RTL_FLAG_TASK_ENABLED,
 667         RTL_FLAG_TASK_SLOW_PENDING,
 668         RTL_FLAG_TASK_RESET_PENDING,
 669         RTL_FLAG_TASK_PHY_PENDING,
 670         RTL_FLAG_MAX
 671 };
 672
 673 struct rtl8169_stats {
 674         u64                     packets;
 675         u64                     bytes;
 676         struct u64_stats_sync   syncp;
 677 };
 678
 679 struct rtl8169_private {
 680         void __iomem *mmio_addr;        /* memory map physical address */
 681         struct pci_dev *pci_dev;
 682         struct net_device *dev;
 683         struct napi_struct napi;
 684         u32 msg_enable;
 685         u16 txd_version;
 686         u16 mac_version;
 687         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 688         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 689         u32 dirty_rx;
 690         u32 dirty_tx;
 691         struct rtl8169_stats rx_stats;
 692         struct rtl8169_stats tx_stats;
 693         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 694         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 695         dma_addr_t TxPhyAddr;
 696         dma_addr_t RxPhyAddr;
 697         void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
 698         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 699         struct timer_list timer;
 700         u16 cp_cmd;
 701
 702         u16 event_slow;
 703
 704         struct mdio_ops {
 705                 void (*write)(void __iomem *, int, int);
 706                 int (*read)(void __iomem *, int);
 707         } mdio_ops;
 708
 709         struct pll_power_ops {
 710                 void (*down)(struct rtl8169_private *);
 711                 void (*up)(struct rtl8169_private *);
 712         } pll_power_ops;
 713
 714         struct jumbo_ops {
 715                 void (*enable)(struct rtl8169_private *);
 716                 void (*disable)(struct rtl8169_private *);
 717         } jumbo_ops;
 718
 719         int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
 720         int (*get_settings)(struct net_device *, struct ethtool_cmd *);
 721         void (*phy_reset_enable)(struct rtl8169_private *tp);
 722         void (*hw_start)(struct net_device *);
 723         unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
 724         unsigned int (*link_ok)(void __iomem *);
 725         int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
 726
 727         struct {
 728                 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
 729                 struct mutex mutex;
 730                 struct work_struct work;
 731         } wk;
 732
 733         unsigned features;
 734
 735         struct mii_if_info mii;
 736         struct rtl8169_counters counters;
 737         u32 saved_wolopts;
 738         u32 opts1_mask;
 739
 740         struct rtl_fw {
 741                 const struct firmware *fw;
 742
 743 #define RTL_VER_SIZE            32
 744
 745                 char version[RTL_VER_SIZE];
 746
 747                 struct rtl_fw_phy_action {
 748                         __le32 *code;
 749                         size_t size;
 750                 } phy_action;
 751         } *rtl_fw;
 752 #define RTL_FIRMWARE_UNKNOWN    ERR_PTR(-EAGAIN)
 753 };
 754
 755 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 756 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 757 module_param(use_dac, int, 0);
 758 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
 759 module_param_named(debug, debug.msg_enable, int, 0);
 760 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
 761 MODULE_LICENSE("GPL");
 762 MODULE_VERSION(RTL8169_VERSION);
 763 MODULE_FIRMWARE(FIRMWARE_8168D_1);
 764 MODULE_FIRMWARE(FIRMWARE_8168D_2);
 765 MODULE_FIRMWARE(FIRMWARE_8168E_1);
 766 MODULE_FIRMWARE(FIRMWARE_8168E_2);
 767 MODULE_FIRMWARE(FIRMWARE_8168E_3);
 768 MODULE_FIRMWARE(FIRMWARE_8105E_1);
 769 MODULE_FIRMWARE(FIRMWARE_8168F_1);
 770 MODULE_FIRMWARE(FIRMWARE_8168F_2);
 771
 772 static void rtl_lock_work(struct rtl8169_private *tp)
 773 {
 774         mutex_lock(&tp->wk.mutex);
 775 }
 776
 777 static void rtl_unlock_work(struct rtl8169_private *tp)
 778 {
 779         mutex_unlock(&tp->wk.mutex);
 780 }
 781
 782 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
 783 {
 784         int cap = pci_pcie_cap(pdev);
 785
 786         if (cap) {
 787                 u16 ctl;
 788
 789                 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
 790                 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
 791                 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
 792         }
 793 }
 794
 795 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
 796 {
 797         void __iomem *ioaddr = tp->mmio_addr;
 798         int i;
 799
 800         RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
 801         for (i = 0; i < 20; i++) {
 802                 udelay(100);
 803                 if (RTL_R32(OCPAR) & OCPAR_FLAG)
 804                         break;
 805         }
 806         return RTL_R32(OCPDR);
 807 }
 808
 809 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
 810 {
 811         void __iomem *ioaddr = tp->mmio_addr;
 812         int i;
 813
 814         RTL_W32(OCPDR, data);
 815         RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
 816         for (i = 0; i < 20; i++) {
 817                 udelay(100);
 818                 if ((RTL_R32(OCPAR) & OCPAR_FLAG) == 0)
 819                         break;
 820         }
 821 }
 822
 823 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
 824 {
 825         void __iomem *ioaddr = tp->mmio_addr;
 826         int i;
 827
 828         RTL_W8(ERIDR, cmd);
 829         RTL_W32(ERIAR, 0x800010e8);
 830         msleep(2);
 831         for (i = 0; i < 5; i++) {
 832                 udelay(100);
 833                 if (!(RTL_R32(ERIAR) & ERIAR_FLAG))
 834                         break;
 835         }
 836
 837         ocp_write(tp, 0x1, 0x30, 0x00000001);
 838 }
 839
 840 #define OOB_CMD_RESET           0x00
 841 #define OOB_CMD_DRIVER_START    0x05
 842 #define OOB_CMD_DRIVER_STOP     0x06
 843
 844 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
 845 {
 846         return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
 847 }
 848
 849 static void rtl8168_driver_start(struct rtl8169_private *tp)
 850 {
 851         u16 reg;
 852         int i;
 853
 854         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
 855
 856         reg = rtl8168_get_ocp_reg(tp);
 857
 858         for (i = 0; i < 10; i++) {
 859                 msleep(10);
 860                 if (ocp_read(tp, 0x0f, reg) & 0x00000800)
 861                         break;
 862         }
 863 }
 864
 865 static void rtl8168_driver_stop(struct rtl8169_private *tp)
 866 {
 867         u16 reg;
 868         int i;
 869
 870         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
 871
 872         reg = rtl8168_get_ocp_reg(tp);
 873
 874         for (i = 0; i < 10; i++) {
 875                 msleep(10);
 876                 if ((ocp_read(tp, 0x0f, reg) & 0x00000800) == 0)
 877                         break;
 878         }
 879 }
 880
 881 static int r8168dp_check_dash(struct rtl8169_private *tp)
 882 {
 883         u16 reg = rtl8168_get_ocp_reg(tp);
 884
 885         return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
 886 }
 887
 888 static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 889 {
 890         int i;
 891
 892         RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
 893
 894         for (i = 20; i > 0; i--) {
 895                 /*
 896                  * Check if the RTL8169 has completed writing to the specified
 897                  * MII register.
 898                  */
 899                 if (!(RTL_R32(PHYAR) & 0x80000000))
 900                         break;
 901                 udelay(25);
 902         }
 903         /*
 904          * According to hardware specs a 20us delay is required after write
 905          * complete indication, but before sending next command.
 906          */
 907         udelay(20);
 908 }
 909
 910 static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr)
 911 {
 912         int i, value = -1;
 913
 914         RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
 915
 916         for (i = 20; i > 0; i--) {
 917                 /*
 918                  * Check if the RTL8169 has completed retrieving data from
 919                  * the specified MII register.
 920                  */
 921                 if (RTL_R32(PHYAR) & 0x80000000) {
 922                         value = RTL_R32(PHYAR) & 0xffff;
 923                         break;
 924                 }
 925                 udelay(25);
 926         }
 927         /*
 928          * According to hardware specs a 20us delay is required after read
 929          * complete indication, but before sending next command.
 930          */
 931         udelay(20);
 932
 933         return value;
 934 }
 935
 936 static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data)
 937 {
 938         int i;
 939
 940         RTL_W32(OCPDR, data |
 941                 ((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
 942         RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
 943         RTL_W32(EPHY_RXER_NUM, 0);
 944
 945         for (i = 0; i < 100; i++) {
 946                 mdelay(1);
 947                 if (!(RTL_R32(OCPAR) & OCPAR_FLAG))
 948                         break;
 949         }
 950 }
 951
 952 static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 953 {
 954         r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD |
 955                 (value & OCPDR_DATA_MASK));
 956 }
 957
 958 static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr)
 959 {
 960         int i;
 961
 962         r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD);
 963
 964         mdelay(1);
 965         RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
 966         RTL_W32(EPHY_RXER_NUM, 0);
 967
 968         for (i = 0; i < 100; i++) {
 969                 mdelay(1);
 970                 if (RTL_R32(OCPAR) & OCPAR_FLAG)
 971                         break;
 972         }
 973
 974         return RTL_R32(OCPDR) & OCPDR_DATA_MASK;
 975 }
 976
 977 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
 978
 979 static void r8168dp_2_mdio_start(void __iomem *ioaddr)
 980 {
 981         RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
 982 }
 983
 984 static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
 985 {
 986         RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
 987 }
 988
 989 static void r8168dp_2_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 990 {
 991         r8168dp_2_mdio_start(ioaddr);
 992
 993         r8169_mdio_write(ioaddr, reg_addr, value);
 994
 995         r8168dp_2_mdio_stop(ioaddr);
 996 }
 997
 998 static int r8168dp_2_mdio_read(void __iomem *ioaddr, int reg_addr)
 999 {
1000         int value;
1001
1002         r8168dp_2_mdio_start(ioaddr);
1003
1004         value = r8169_mdio_read(ioaddr, reg_addr);
1005
1006         r8168dp_2_mdio_stop(ioaddr);
1007
1008         return value;
1009 }
1010
1011 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
1012 {
1013         tp->mdio_ops.write(tp->mmio_addr, location, val);
1014 }
1015
1016 static int rtl_readphy(struct rtl8169_private *tp, int location)
1017 {
1018         return tp->mdio_ops.read(tp->mmio_addr, location);
1019 }
1020
1021 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1022 {
1023         rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1024 }
1025
1026 static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1027 {
1028         int val;
1029
1030         val = rtl_readphy(tp, reg_addr);
1031         rtl_writephy(tp, reg_addr, (val | p) & ~m);
1032 }
1033
1034 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
1035                            int val)
1036 {
1037         struct rtl8169_private *tp = netdev_priv(dev);
1038
1039         rtl_writephy(tp, location, val);
1040 }
1041
1042 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1043 {
1044         struct rtl8169_private *tp = netdev_priv(dev);
1045
1046         return rtl_readphy(tp, location);
1047 }
1048
1049 static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
1050 {
1051         unsigned int i;
1052
1053         RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1054                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1055
1056         for (i = 0; i < 100; i++) {
1057                 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
1058                         break;
1059                 udelay(10);
1060         }
1061 }
1062
1063 static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
1064 {
1065         u16 value = 0xffff;
1066         unsigned int i;
1067
1068         RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1069
1070         for (i = 0; i < 100; i++) {
1071                 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
1072                         value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
1073                         break;
1074                 }
1075                 udelay(10);
1076         }
1077
1078         return value;
1079 }
1080
1081 static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
1082 {
1083         unsigned int i;
1084
1085         RTL_W32(CSIDR, value);
1086         RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
1087                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1088
1089         for (i = 0; i < 100; i++) {
1090                 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
1091                         break;
1092                 udelay(10);
1093         }
1094 }
1095
1096 static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
1097 {
1098         u32 value = ~0x00;
1099         unsigned int i;
1100
1101         RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
1102                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1103
1104         for (i = 0; i < 100; i++) {
1105                 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
1106                         value = RTL_R32(CSIDR);
1107                         break;
1108                 }
1109                 udelay(10);
1110         }
1111
1112         return value;
1113 }
1114
1115 static
1116 void rtl_eri_write(void __iomem *ioaddr, int addr, u32 mask, u32 val, int type)
1117 {
1118         unsigned int i;
1119
1120         BUG_ON((addr & 3) || (mask == 0));
1121         RTL_W32(ERIDR, val);
1122         RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1123
1124         for (i = 0; i < 100; i++) {
1125                 if (!(RTL_R32(ERIAR) & ERIAR_FLAG))
1126                         break;
1127                 udelay(100);
1128         }
1129 }
1130
1131 static u32 rtl_eri_read(void __iomem *ioaddr, int addr, int type)
1132 {
1133         u32 value = ~0x00;
1134         unsigned int i;
1135
1136         RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1137
1138         for (i = 0; i < 100; i++) {
1139                 if (RTL_R32(ERIAR) & ERIAR_FLAG) {
1140                         value = RTL_R32(ERIDR);
1141                         break;
1142                 }
1143                 udelay(100);
1144         }
1145
1146         return value;
1147 }
1148
1149 static void
1150 rtl_w1w0_eri(void __iomem *ioaddr, int addr, u32 mask, u32 p, u32 m, int type)
1151 {
1152         u32 val;
1153
1154         val = rtl_eri_read(ioaddr, addr, type);
1155         rtl_eri_write(ioaddr, addr, mask, (val & ~m) | p, type);
1156 }
1157
1158 struct exgmac_reg {
1159         u16 addr;
1160         u16 mask;
1161         u32 val;
1162 };
1163
1164 static void rtl_write_exgmac_batch(void __iomem *ioaddr,
1165                                    const struct exgmac_reg *r, int len)
1166 {
1167         while (len-- > 0) {
1168                 rtl_eri_write(ioaddr, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1169                 r++;
1170         }
1171 }
1172
1173 static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
1174 {
1175         u8 value = 0xff;
1176         unsigned int i;
1177
1178         RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1179
1180         for (i = 0; i < 300; i++) {
1181                 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
1182                         value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
1183                         break;
1184                 }
1185                 udelay(100);
1186         }
1187
1188         return value;
1189 }
1190
1191 static u16 rtl_get_events(struct rtl8169_private *tp)
1192 {
1193         void __iomem *ioaddr = tp->mmio_addr;
1194
1195         return RTL_R16(IntrStatus);
1196 }
1197
1198 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1199 {
1200         void __iomem *ioaddr = tp->mmio_addr;
1201
1202         RTL_W16(IntrStatus, bits);
1203         mmiowb();
1204 }
1205
1206 static void rtl_irq_disable(struct rtl8169_private *tp)
1207 {
1208         void __iomem *ioaddr = tp->mmio_addr;
1209
1210         RTL_W16(IntrMask, 0);
1211         mmiowb();
1212 }
1213
1214 static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1215 {
1216         void __iomem *ioaddr = tp->mmio_addr;
1217
1218         RTL_W16(IntrMask, bits);
1219 }
1220
1221 #define RTL_EVENT_NAPI_RX       (RxOK | RxErr)
1222 #define RTL_EVENT_NAPI_TX       (TxOK | TxErr)
1223 #define RTL_EVENT_NAPI          (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1224
1225 static void rtl_irq_enable_all(struct rtl8169_private *tp)
1226 {
1227         rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1228 }
1229
1230 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1231 {
1232         void __iomem *ioaddr = tp->mmio_addr;
1233
1234         rtl_irq_disable(tp);
1235         rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
1236         RTL_R8(ChipCmd);
1237 }
1238
1239 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1240 {
1241         void __iomem *ioaddr = tp->mmio_addr;
1242
1243         return RTL_R32(TBICSR) & TBIReset;
1244 }
1245
1246 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1247 {
1248         return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1249 }
1250
1251 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1252 {
1253         return RTL_R32(TBICSR) & TBILinkOk;
1254 }
1255
1256 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1257 {
1258         return RTL_R8(PHYstatus) & LinkStatus;
1259 }
1260
1261 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1262 {
1263         void __iomem *ioaddr = tp->mmio_addr;
1264
1265         RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1266 }
1267
1268 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1269 {
1270         unsigned int val;
1271
1272         val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1273         rtl_writephy(tp, MII_BMCR, val & 0xffff);
1274 }
1275
1276 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1277 {
1278         void __iomem *ioaddr = tp->mmio_addr;
1279         struct net_device *dev = tp->dev;
1280
1281         if (!netif_running(dev))
1282                 return;
1283
1284         if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
1285                 if (RTL_R8(PHYstatus) & _1000bpsF) {
1286                         rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1287                                       0x00000011, ERIAR_EXGMAC);
1288                         rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1289                                       0x00000005, ERIAR_EXGMAC);
1290                 } else if (RTL_R8(PHYstatus) & _100bps) {
1291                         rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1292                                       0x0000001f, ERIAR_EXGMAC);
1293                         rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1294                                       0x00000005, ERIAR_EXGMAC);
1295                 } else {
1296                         rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1297                                       0x0000001f, ERIAR_EXGMAC);
1298                         rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1299                                       0x0000003f, ERIAR_EXGMAC);
1300                 }
1301                 /* Reset packet filter */
1302                 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1303                              ERIAR_EXGMAC);
1304                 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1305                              ERIAR_EXGMAC);
1306         } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1307                    tp->mac_version == RTL_GIGA_MAC_VER_36) {
1308                 if (RTL_R8(PHYstatus) & _1000bpsF) {
1309                         rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1310                                       0x00000011, ERIAR_EXGMAC);
1311                         rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1312                                       0x00000005, ERIAR_EXGMAC);
1313                 } else {
1314                         rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1315                                       0x0000001f, ERIAR_EXGMAC);
1316                         rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1317                                       0x0000003f, ERIAR_EXGMAC);
1318                 }
1319         }
1320 }
1321
1322 static void __rtl8169_check_link_status(struct net_device *dev,
1323                                         struct rtl8169_private *tp,
1324                                         void __iomem *ioaddr, bool pm)
1325 {
1326         if (tp->link_ok(ioaddr)) {
1327                 rtl_link_chg_patch(tp);
1328                 /* This is to cancel a scheduled suspend if there's one. */
1329                 if (pm)
1330                         pm_request_resume(&tp->pci_dev->dev);
1331                 netif_carrier_on(dev);
1332                 if (net_ratelimit())
1333                         netif_info(tp, ifup, dev, "link up\n");
1334         } else {
1335                 netif_carrier_off(dev);
1336                 netif_info(tp, ifdown, dev, "link down\n");
1337                 if (pm)
1338                         pm_schedule_suspend(&tp->pci_dev->dev, 5000);
1339         }
1340 }
1341
1342 static void rtl8169_check_link_status(struct net_device *dev,
1343                                       struct rtl8169_private *tp,
1344                                       void __iomem *ioaddr)
1345 {
1346         __rtl8169_check_link_status(dev, tp, ioaddr, false);
1347 }
1348
1349 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1350
1351 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1352 {
1353         void __iomem *ioaddr = tp->mmio_addr;
1354         u8 options;
1355         u32 wolopts = 0;
1356
1357         options = RTL_R8(Config1);
1358         if (!(options & PMEnable))
1359                 return 0;
1360
1361         options = RTL_R8(Config3);
1362         if (options & LinkUp)
1363                 wolopts |= WAKE_PHY;
1364         if (options & MagicPacket)
1365                 wolopts |= WAKE_MAGIC;
1366
1367         options = RTL_R8(Config5);
1368         if (options & UWF)
1369                 wolopts |= WAKE_UCAST;
1370         if (options & BWF)
1371                 wolopts |= WAKE_BCAST;
1372         if (options & MWF)
1373                 wolopts |= WAKE_MCAST;
1374
1375         return wolopts;
1376 }
1377
1378 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1379 {
1380         struct rtl8169_private *tp = netdev_priv(dev);
1381
1382         rtl_lock_work(tp);
1383
1384         wol->supported = WAKE_ANY;
1385         wol->wolopts = __rtl8169_get_wol(tp);
1386
1387         rtl_unlock_work(tp);
1388 }
1389
1390 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1391 {
1392         void __iomem *ioaddr = tp->mmio_addr;
1393         unsigned int i;
1394         static const struct {
1395                 u32 opt;
1396                 u16 reg;
1397                 u8  mask;
1398         } cfg[] = {
1399                 { WAKE_PHY,   Config3, LinkUp },
1400                 { WAKE_MAGIC, Config3, MagicPacket },
1401                 { WAKE_UCAST, Config5, UWF },
1402                 { WAKE_BCAST, Config5, BWF },
1403                 { WAKE_MCAST, Config5, MWF },
1404                 { WAKE_ANY,   Config5, LanWake }
1405         };
1406         u8 options;
1407
1408         RTL_W8(Cfg9346, Cfg9346_Unlock);
1409
1410         for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1411                 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
1412                 if (wolopts & cfg[i].opt)
1413                         options |= cfg[i].mask;
1414                 RTL_W8(cfg[i].reg, options);
1415         }
1416
1417         switch (tp->mac_version) {
1418         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1419                 options = RTL_R8(Config1) & ~PMEnable;
1420                 if (wolopts)
1421                         options |= PMEnable;
1422                 RTL_W8(Config1, options);
1423                 break;
1424         default:
1425                 break;
1426         }
1427
1428         RTL_W8(Cfg9346, Cfg9346_Lock);
1429 }
1430
1431 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1432 {
1433         struct rtl8169_private *tp = netdev_priv(dev);
1434
1435         rtl_lock_work(tp);
1436
1437         if (wol->wolopts)
1438                 tp->features |= RTL_FEATURE_WOL;
1439         else
1440                 tp->features &= ~RTL_FEATURE_WOL;
1441         __rtl8169_set_wol(tp, wol->wolopts);
1442
1443         rtl_unlock_work(tp);
1444
1445         device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1446
1447         return 0;
1448 }
1449
1450 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1451 {
1452         return rtl_chip_infos[tp->mac_version].fw_name;
1453 }
1454
1455 static void rtl8169_get_drvinfo(struct net_device *dev,
1456                                 struct ethtool_drvinfo *info)
1457 {
1458         struct rtl8169_private *tp = netdev_priv(dev);
1459         struct rtl_fw *rtl_fw = tp->rtl_fw;
1460
1461         strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1462         strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
1463         strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1464         BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1465         if (!IS_ERR_OR_NULL(rtl_fw))
1466                 strlcpy(info->fw_version, rtl_fw->version,
1467                         sizeof(info->fw_version));
1468 }
1469
1470 static int rtl8169_get_regs_len(struct net_device *dev)
1471 {
1472         return R8169_REGS_SIZE;
1473 }
1474
1475 static int rtl8169_set_speed_tbi(struct net_device *dev,
1476                                  u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1477 {
1478         struct rtl8169_private *tp = netdev_priv(dev);
1479         void __iomem *ioaddr = tp->mmio_addr;
1480         int ret = 0;
1481         u32 reg;
1482
1483         reg = RTL_R32(TBICSR);
1484         if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1485             (duplex == DUPLEX_FULL)) {
1486                 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1487         } else if (autoneg == AUTONEG_ENABLE)
1488                 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1489         else {
1490                 netif_warn(tp, link, dev,
1491                            "incorrect speed setting refused in TBI mode\n");
1492                 ret = -EOPNOTSUPP;
1493         }
1494
1495         return ret;
1496 }
1497
1498 static int rtl8169_set_speed_xmii(struct net_device *dev,
1499                                   u8 autoneg, u16 speed, u8 duplex, u32 adv)
1500 {
1501         struct rtl8169_private *tp = netdev_priv(dev);
1502         int giga_ctrl, bmcr;
1503         int rc = -EINVAL;
1504
1505         rtl_writephy(tp, 0x1f, 0x0000);
1506
1507         if (autoneg == AUTONEG_ENABLE) {
1508                 int auto_nego;
1509
1510                 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1511                 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1512                                 ADVERTISE_100HALF | ADVERTISE_100FULL);
1513
1514                 if (adv & ADVERTISED_10baseT_Half)
1515                         auto_nego |= ADVERTISE_10HALF;
1516                 if (adv & ADVERTISED_10baseT_Full)
1517                         auto_nego |= ADVERTISE_10FULL;
1518                 if (adv & ADVERTISED_100baseT_Half)
1519                         auto_nego |= ADVERTISE_100HALF;
1520                 if (adv & ADVERTISED_100baseT_Full)
1521                         auto_nego |= ADVERTISE_100FULL;
1522
1523                 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1524
1525                 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1526                 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1527
1528                 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1529                 if (tp->mii.supports_gmii) {
1530                         if (adv & ADVERTISED_1000baseT_Half)
1531                                 giga_ctrl |= ADVERTISE_1000HALF;
1532                         if (adv & ADVERTISED_1000baseT_Full)
1533                                 giga_ctrl |= ADVERTISE_1000FULL;
1534                 } else if (adv & (ADVERTISED_1000baseT_Half |
1535                                   ADVERTISED_1000baseT_Full)) {
1536                         netif_info(tp, link, dev,
1537                                    "PHY does not support 1000Mbps\n");
1538                         goto out;
1539                 }
1540
1541                 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1542
1543                 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1544                 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1545         } else {
1546                 giga_ctrl = 0;
1547
1548                 if (speed == SPEED_10)
1549                         bmcr = 0;
1550                 else if (speed == SPEED_100)
1551                         bmcr = BMCR_SPEED100;
1552                 else
1553                         goto out;
1554
1555                 if (duplex == DUPLEX_FULL)
1556                         bmcr |= BMCR_FULLDPLX;
1557         }
1558
1559         rtl_writephy(tp, MII_BMCR, bmcr);
1560
1561         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1562             tp->mac_version == RTL_GIGA_MAC_VER_03) {
1563                 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1564                         rtl_writephy(tp, 0x17, 0x2138);
1565                         rtl_writephy(tp, 0x0e, 0x0260);
1566                 } else {
1567                         rtl_writephy(tp, 0x17, 0x2108);
1568                         rtl_writephy(tp, 0x0e, 0x0000);
1569                 }
1570         }
1571
1572         rc = 0;
1573 out:
1574         return rc;
1575 }
1576
1577 static int rtl8169_set_speed(struct net_device *dev,
1578                              u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1579 {
1580         struct rtl8169_private *tp = netdev_priv(dev);
1581         int ret;
1582
1583         ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
1584         if (ret < 0)
1585                 goto out;
1586
1587         if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1588             (advertising & ADVERTISED_1000baseT_Full)) {
1589                 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1590         }
1591 out:
1592         return ret;
1593 }
1594
1595 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1596 {
1597         struct rtl8169_private *tp = netdev_priv(dev);
1598         int ret;
1599
1600         del_timer_sync(&tp->timer);
1601
1602         rtl_lock_work(tp);
1603         ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
1604                                 cmd->duplex, cmd->advertising);
1605         rtl_unlock_work(tp);
1606
1607         return ret;
1608 }
1609
1610 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1611         netdev_features_t features)
1612 {
1613         struct rtl8169_private *tp = netdev_priv(dev);
1614
1615         if (dev->mtu > TD_MSS_MAX)
1616                 features &= ~NETIF_F_ALL_TSO;
1617
1618         if (dev->mtu > JUMBO_1K &&
1619             !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
1620                 features &= ~NETIF_F_IP_CSUM;
1621
1622         return features;
1623 }
1624
1625 static void __rtl8169_set_features(struct net_device *dev,
1626                                    netdev_features_t features)
1627 {
1628         struct rtl8169_private *tp = netdev_priv(dev);
1629         netdev_features_t changed = features ^ dev->features;
1630         void __iomem *ioaddr = tp->mmio_addr;
1631
1632         if (!(changed & (NETIF_F_RXALL | NETIF_F_RXCSUM | NETIF_F_HW_VLAN_RX)))
1633                 return;
1634
1635         if (changed & (NETIF_F_RXCSUM | NETIF_F_HW_VLAN_RX)) {
1636                 if (features & NETIF_F_RXCSUM)
1637                         tp->cp_cmd |= RxChkSum;
1638                 else
1639                         tp->cp_cmd &= ~RxChkSum;
1640
1641                 if (dev->features & NETIF_F_HW_VLAN_RX)
1642                         tp->cp_cmd |= RxVlan;
1643                 else
1644                         tp->cp_cmd &= ~RxVlan;
1645
1646                 RTL_W16(CPlusCmd, tp->cp_cmd);
1647                 RTL_R16(CPlusCmd);
1648         }
1649         if (changed & NETIF_F_RXALL) {
1650                 int tmp = (RTL_R32(RxConfig) & ~(AcceptErr | AcceptRunt));
1651                 if (features & NETIF_F_RXALL)
1652                         tmp |= (AcceptErr | AcceptRunt);
1653                 RTL_W32(RxConfig, tmp);
1654         }
1655 }
1656
1657 static int rtl8169_set_features(struct net_device *dev,
1658                                 netdev_features_t features)
1659 {
1660         struct rtl8169_private *tp = netdev_priv(dev);
1661
1662         rtl_lock_work(tp);
1663         __rtl8169_set_features(dev, features);
1664         rtl_unlock_work(tp);
1665
1666         return 0;
1667 }
1668
1669
1670 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1671                                       struct sk_buff *skb)
1672 {
1673         return (vlan_tx_tag_present(skb)) ?
1674                 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1675 }
1676
1677 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1678 {
1679         u32 opts2 = le32_to_cpu(desc->opts2);
1680
1681         if (opts2 & RxVlanTag)
1682                 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
1683
1684         desc->opts2 = 0;
1685 }
1686
1687 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1688 {
1689         struct rtl8169_private *tp = netdev_priv(dev);
1690         void __iomem *ioaddr = tp->mmio_addr;
1691         u32 status;
1692
1693         cmd->supported =
1694                 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1695         cmd->port = PORT_FIBRE;
1696         cmd->transceiver = XCVR_INTERNAL;
1697
1698         status = RTL_R32(TBICSR);
1699         cmd->advertising = (status & TBINwEnable) ?  ADVERTISED_Autoneg : 0;
1700         cmd->autoneg = !!(status & TBINwEnable);
1701
1702         ethtool_cmd_speed_set(cmd, SPEED_1000);
1703         cmd->duplex = DUPLEX_FULL; /* Always set */
1704
1705         return 0;
1706 }
1707
1708 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1709 {
1710         struct rtl8169_private *tp = netdev_priv(dev);
1711
1712         return mii_ethtool_gset(&tp->mii, cmd);
1713 }
1714
1715 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1716 {
1717         struct rtl8169_private *tp = netdev_priv(dev);
1718         int rc;
1719
1720         rtl_lock_work(tp);
1721         rc = tp->get_settings(dev, cmd);
1722         rtl_unlock_work(tp);
1723
1724         return rc;
1725 }
1726
1727 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1728                              void *p)
1729 {
1730         struct rtl8169_private *tp = netdev_priv(dev);
1731
1732         if (regs->len > R8169_REGS_SIZE)
1733                 regs->len = R8169_REGS_SIZE;
1734
1735         rtl_lock_work(tp);
1736         memcpy_fromio(p, tp->mmio_addr, regs->len);
1737         rtl_unlock_work(tp);
1738 }
1739
1740 static u32 rtl8169_get_msglevel(struct net_device *dev)
1741 {
1742         struct rtl8169_private *tp = netdev_priv(dev);
1743
1744         return tp->msg_enable;
1745 }
1746
1747 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1748 {
1749         struct rtl8169_private *tp = netdev_priv(dev);
1750
1751         tp->msg_enable = value;
1752 }
1753
1754 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1755         "tx_packets",
1756         "rx_packets",
1757         "tx_errors",
1758         "rx_errors",
1759         "rx_missed",
1760         "align_errors",
1761         "tx_single_collisions",
1762         "tx_multi_collisions",
1763         "unicast",
1764         "broadcast",
1765         "multicast",
1766         "tx_aborted",
1767         "tx_underrun",
1768 };
1769
1770 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1771 {
1772         switch (sset) {
1773         case ETH_SS_STATS:
1774                 return ARRAY_SIZE(rtl8169_gstrings);
1775         default:
1776                 return -EOPNOTSUPP;
1777         }
1778 }
1779
1780 static void rtl8169_update_counters(struct net_device *dev)
1781 {
1782         struct rtl8169_private *tp = netdev_priv(dev);
1783         void __iomem *ioaddr = tp->mmio_addr;
1784         struct device *d = &tp->pci_dev->dev;
1785         struct rtl8169_counters *counters;
1786         dma_addr_t paddr;
1787         u32 cmd;
1788         int wait = 1000;
1789
1790         /*
1791          * Some chips are unable to dump tally counters when the receiver
1792          * is disabled.
1793          */
1794         if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1795                 return;
1796
1797         counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
1798         if (!counters)
1799                 return;
1800
1801         RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1802         cmd = (u64)paddr & DMA_BIT_MASK(32);
1803         RTL_W32(CounterAddrLow, cmd);
1804         RTL_W32(CounterAddrLow, cmd | CounterDump);
1805
1806         while (wait--) {
1807                 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1808                         memcpy(&tp->counters, counters, sizeof(*counters));
1809                         break;
1810                 }
1811                 udelay(10);
1812         }
1813
1814         RTL_W32(CounterAddrLow, 0);
1815         RTL_W32(CounterAddrHigh, 0);
1816
1817         dma_free_coherent(d, sizeof(*counters), counters, paddr);
1818 }
1819
1820 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1821                                       struct ethtool_stats *stats, u64 *data)
1822 {
1823         struct rtl8169_private *tp = netdev_priv(dev);
1824
1825         ASSERT_RTNL();
1826
1827         rtl8169_update_counters(dev);
1828
1829         data[0] = le64_to_cpu(tp->counters.tx_packets);
1830         data[1] = le64_to_cpu(tp->counters.rx_packets);
1831         data[2] = le64_to_cpu(tp->counters.tx_errors);
1832         data[3] = le32_to_cpu(tp->counters.rx_errors);
1833         data[4] = le16_to_cpu(tp->counters.rx_missed);
1834         data[5] = le16_to_cpu(tp->counters.align_errors);
1835         data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1836         data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1837         data[8] = le64_to_cpu(tp->counters.rx_unicast);
1838         data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1839         data[10] = le32_to_cpu(tp->counters.rx_multicast);
1840         data[11] = le16_to_cpu(tp->counters.tx_aborted);
1841         data[12] = le16_to_cpu(tp->counters.tx_underun);
1842 }
1843
1844 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1845 {
1846         switch(stringset) {
1847         case ETH_SS_STATS:
1848                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1849                 break;
1850         }
1851 }
1852
1853 static const struct ethtool_ops rtl8169_ethtool_ops = {
1854         .get_drvinfo            = rtl8169_get_drvinfo,
1855         .get_regs_len           = rtl8169_get_regs_len,
1856         .get_link               = ethtool_op_get_link,
1857         .get_settings           = rtl8169_get_settings,
1858         .set_settings           = rtl8169_set_settings,
1859         .get_msglevel           = rtl8169_get_msglevel,
1860         .set_msglevel           = rtl8169_set_msglevel,
1861         .get_regs               = rtl8169_get_regs,
1862         .get_wol                = rtl8169_get_wol,
1863         .set_wol                = rtl8169_set_wol,
1864         .get_strings            = rtl8169_get_strings,
1865         .get_sset_count         = rtl8169_get_sset_count,
1866         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
1867         .get_ts_info            = ethtool_op_get_ts_info,
1868 };
1869
1870 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1871                                     struct net_device *dev, u8 default_version)
1872 {
1873         void __iomem *ioaddr = tp->mmio_addr;
1874         /*
1875          * The driver currently handles the 8168Bf and the 8168Be identically
1876          * but they can be identified more specifically through the test below
1877          * if needed:
1878          *
1879          * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1880          *
1881          * Same thing for the 8101Eb and the 8101Ec:
1882          *
1883          * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1884          */
1885         static const struct rtl_mac_info {
1886                 u32 mask;
1887                 u32 val;
1888                 int mac_version;
1889         } mac_info[] = {
1890                 /* 8168F family. */
1891                 { 0x7cf00000, 0x48100000,       RTL_GIGA_MAC_VER_36 },
1892                 { 0x7cf00000, 0x48000000,       RTL_GIGA_MAC_VER_35 },
1893
1894                 /* 8168E family. */
1895                 { 0x7c800000, 0x2c800000,       RTL_GIGA_MAC_VER_34 },
1896                 { 0x7cf00000, 0x2c200000,       RTL_GIGA_MAC_VER_33 },
1897                 { 0x7cf00000, 0x2c100000,       RTL_GIGA_MAC_VER_32 },
1898                 { 0x7c800000, 0x2c000000,       RTL_GIGA_MAC_VER_33 },
1899
1900                 /* 8168D family. */
1901                 { 0x7cf00000, 0x28300000,       RTL_GIGA_MAC_VER_26 },
1902                 { 0x7cf00000, 0x28100000,       RTL_GIGA_MAC_VER_25 },
1903                 { 0x7c800000, 0x28000000,       RTL_GIGA_MAC_VER_26 },
1904
1905                 /* 8168DP family. */
1906                 { 0x7cf00000, 0x28800000,       RTL_GIGA_MAC_VER_27 },
1907                 { 0x7cf00000, 0x28a00000,       RTL_GIGA_MAC_VER_28 },
1908                 { 0x7cf00000, 0x28b00000,       RTL_GIGA_MAC_VER_31 },
1909
1910                 /* 8168C family. */
1911                 { 0x7cf00000, 0x3cb00000,       RTL_GIGA_MAC_VER_24 },
1912                 { 0x7cf00000, 0x3c900000,       RTL_GIGA_MAC_VER_23 },
1913                 { 0x7cf00000, 0x3c800000,       RTL_GIGA_MAC_VER_18 },
1914                 { 0x7c800000, 0x3c800000,       RTL_GIGA_MAC_VER_24 },
1915                 { 0x7cf00000, 0x3c000000,       RTL_GIGA_MAC_VER_19 },
1916                 { 0x7cf00000, 0x3c200000,       RTL_GIGA_MAC_VER_20 },
1917                 { 0x7cf00000, 0x3c300000,       RTL_GIGA_MAC_VER_21 },
1918                 { 0x7cf00000, 0x3c400000,       RTL_GIGA_MAC_VER_22 },
1919                 { 0x7c800000, 0x3c000000,       RTL_GIGA_MAC_VER_22 },
1920
1921                 /* 8168B family. */
1922                 { 0x7cf00000, 0x38000000,       RTL_GIGA_MAC_VER_12 },
1923                 { 0x7cf00000, 0x38500000,       RTL_GIGA_MAC_VER_17 },
1924                 { 0x7c800000, 0x38000000,       RTL_GIGA_MAC_VER_17 },
1925                 { 0x7c800000, 0x30000000,       RTL_GIGA_MAC_VER_11 },
1926
1927                 /* 8101 family. */
1928                 { 0x7cf00000, 0x40b00000,       RTL_GIGA_MAC_VER_30 },
1929                 { 0x7cf00000, 0x40a00000,       RTL_GIGA_MAC_VER_30 },
1930                 { 0x7cf00000, 0x40900000,       RTL_GIGA_MAC_VER_29 },
1931                 { 0x7c800000, 0x40800000,       RTL_GIGA_MAC_VER_30 },
1932                 { 0x7cf00000, 0x34a00000,       RTL_GIGA_MAC_VER_09 },
1933                 { 0x7cf00000, 0x24a00000,       RTL_GIGA_MAC_VER_09 },
1934                 { 0x7cf00000, 0x34900000,       RTL_GIGA_MAC_VER_08 },
1935                 { 0x7cf00000, 0x24900000,       RTL_GIGA_MAC_VER_08 },
1936                 { 0x7cf00000, 0x34800000,       RTL_GIGA_MAC_VER_07 },
1937                 { 0x7cf00000, 0x24800000,       RTL_GIGA_MAC_VER_07 },
1938                 { 0x7cf00000, 0x34000000,       RTL_GIGA_MAC_VER_13 },
1939                 { 0x7cf00000, 0x34300000,       RTL_GIGA_MAC_VER_10 },
1940                 { 0x7cf00000, 0x34200000,       RTL_GIGA_MAC_VER_16 },
1941                 { 0x7c800000, 0x34800000,       RTL_GIGA_MAC_VER_09 },
1942                 { 0x7c800000, 0x24800000,       RTL_GIGA_MAC_VER_09 },
1943                 { 0x7c800000, 0x34000000,       RTL_GIGA_MAC_VER_16 },
1944                 /* FIXME: where did these entries come from ? -- FR */
1945                 { 0xfc800000, 0x38800000,       RTL_GIGA_MAC_VER_15 },
1946                 { 0xfc800000, 0x30800000,       RTL_GIGA_MAC_VER_14 },
1947
1948                 /* 8110 family. */
1949                 { 0xfc800000, 0x98000000,       RTL_GIGA_MAC_VER_06 },
1950                 { 0xfc800000, 0x18000000,       RTL_GIGA_MAC_VER_05 },
1951                 { 0xfc800000, 0x10000000,       RTL_GIGA_MAC_VER_04 },
1952                 { 0xfc800000, 0x04000000,       RTL_GIGA_MAC_VER_03 },
1953                 { 0xfc800000, 0x00800000,       RTL_GIGA_MAC_VER_02 },
1954                 { 0xfc800000, 0x00000000,       RTL_GIGA_MAC_VER_01 },
1955
1956                 /* Catch-all */
1957                 { 0x00000000, 0x00000000,       RTL_GIGA_MAC_NONE   }
1958         };
1959         const struct rtl_mac_info *p = mac_info;
1960         u32 reg;
1961
1962         reg = RTL_R32(TxConfig);
1963         while ((reg & p->mask) != p->val)
1964                 p++;
1965         tp->mac_version = p->mac_version;
1966
1967         if (tp->mac_version == RTL_GIGA_MAC_NONE) {
1968                 netif_notice(tp, probe, dev,
1969                              "unknown MAC, using family default\n");
1970                 tp->mac_version = default_version;
1971         }
1972 }
1973
1974 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1975 {
1976         dprintk("mac_version = 0x%02x\n", tp->mac_version);
1977 }
1978
1979 struct phy_reg {
1980         u16 reg;
1981         u16 val;
1982 };
1983
1984 static void rtl_writephy_batch(struct rtl8169_private *tp,
1985                                const struct phy_reg *regs, int len)
1986 {
1987         while (len-- > 0) {
1988                 rtl_writephy(tp, regs->reg, regs->val);
1989                 regs++;
1990         }
1991 }
1992
1993 #define PHY_READ                0x00000000
1994 #define PHY_DATA_OR             0x10000000
1995 #define PHY_DATA_AND            0x20000000
1996 #define PHY_BJMPN               0x30000000
1997 #define PHY_READ_EFUSE          0x40000000
1998 #define PHY_READ_MAC_BYTE       0x50000000
1999 #define PHY_WRITE_MAC_BYTE      0x60000000
2000 #define PHY_CLEAR_READCOUNT     0x70000000
2001 #define PHY_WRITE               0x80000000
2002 #define PHY_READCOUNT_EQ_SKIP   0x90000000
2003 #define PHY_COMP_EQ_SKIPN       0xa0000000
2004 #define PHY_COMP_NEQ_SKIPN      0xb0000000
2005 #define PHY_WRITE_PREVIOUS      0xc0000000
2006 #define PHY_SKIPN               0xd0000000
2007 #define PHY_DELAY_MS            0xe0000000
2008 #define PHY_WRITE_ERI_WORD      0xf0000000
2009
2010 struct fw_info {
2011         u32     magic;
2012         char    version[RTL_VER_SIZE];
2013         __le32  fw_start;
2014         __le32  fw_len;
2015         u8      chksum;
2016 } __packed;
2017
2018 #define FW_OPCODE_SIZE  sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2019
2020 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2021 {
2022         const struct firmware *fw = rtl_fw->fw;
2023         struct fw_info *fw_info = (struct fw_info *)fw->data;
2024         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2025         char *version = rtl_fw->version;
2026         bool rc = false;
2027
2028         if (fw->size < FW_OPCODE_SIZE)
2029                 goto out;
2030
2031         if (!fw_info->magic) {
2032                 size_t i, size, start;
2033                 u8 checksum = 0;
2034
2035                 if (fw->size < sizeof(*fw_info))
2036                         goto out;
2037
2038                 for (i = 0; i < fw->size; i++)
2039                         checksum += fw->data[i];
2040                 if (checksum != 0)
2041                         goto out;
2042
2043                 start = le32_to_cpu(fw_info->fw_start);
2044                 if (start > fw->size)
2045                         goto out;
2046
2047                 size = le32_to_cpu(fw_info->fw_len);
2048                 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2049                         goto out;
2050
2051                 memcpy(version, fw_info->version, RTL_VER_SIZE);
2052
2053                 pa->code = (__le32 *)(fw->data + start);
2054                 pa->size = size;
2055         } else {
2056                 if (fw->size % FW_OPCODE_SIZE)
2057                         goto out;
2058
2059                 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2060
2061                 pa->code = (__le32 *)fw->data;
2062                 pa->size = fw->size / FW_OPCODE_SIZE;
2063         }
2064         version[RTL_VER_SIZE - 1] = 0;
2065
2066         rc = true;
2067 out:
2068         return rc;
2069 }
2070
2071 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2072                            struct rtl_fw_phy_action *pa)
2073 {
2074         bool rc = false;
2075         size_t index;
2076
2077         for (index = 0; index < pa->size; index++) {
2078                 u32 action = le32_to_cpu(pa->code[index]);
2079                 u32 regno = (action & 0x0fff0000) >> 16;
2080
2081                 switch(action & 0xf0000000) {
2082                 case PHY_READ:
2083                 case PHY_DATA_OR:
2084                 case PHY_DATA_AND:
2085                 case PHY_READ_EFUSE:
2086                 case PHY_CLEAR_READCOUNT:
2087                 case PHY_WRITE:
2088                 case PHY_WRITE_PREVIOUS:
2089                 case PHY_DELAY_MS:
2090                         break;
2091
2092                 case PHY_BJMPN:
2093                         if (regno > index) {
2094                                 netif_err(tp, ifup, tp->dev,
2095                                           "Out of range of firmware\n");
2096                                 goto out;
2097                         }
2098                         break;
2099                 case PHY_READCOUNT_EQ_SKIP:
2100                         if (index + 2 >= pa->size) {
2101                                 netif_err(tp, ifup, tp->dev,
2102                                           "Out of range of firmware\n");
2103                                 goto out;
2104                         }
2105                         break;
2106                 case PHY_COMP_EQ_SKIPN:
2107                 case PHY_COMP_NEQ_SKIPN:
2108                 case PHY_SKIPN:
2109                         if (index + 1 + regno >= pa->size) {
2110                                 netif_err(tp, ifup, tp->dev,
2111                                           "Out of range of firmware\n");
2112                                 goto out;
2113                         }
2114                         break;
2115
2116                 case PHY_READ_MAC_BYTE:
2117                 case PHY_WRITE_MAC_BYTE:
2118                 case PHY_WRITE_ERI_WORD:
2119                 default:
2120                         netif_err(tp, ifup, tp->dev,
2121                                   "Invalid action 0x%08x\n", action);
2122                         goto out;
2123                 }
2124         }
2125         rc = true;
2126 out:
2127         return rc;
2128 }
2129
2130 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2131 {
2132         struct net_device *dev = tp->dev;
2133         int rc = -EINVAL;
2134
2135         if (!rtl_fw_format_ok(tp, rtl_fw)) {
2136                 netif_err(tp, ifup, dev, "invalid firwmare\n");
2137                 goto out;
2138         }
2139
2140         if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2141                 rc = 0;
2142 out:
2143         return rc;
2144 }
2145
2146 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2147 {
2148         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2149         u32 predata, count;
2150         size_t index;
2151
2152         predata = count = 0;
2153
2154         for (index = 0; index < pa->size; ) {
2155                 u32 action = le32_to_cpu(pa->code[index]);
2156                 u32 data = action & 0x0000ffff;
2157                 u32 regno = (action & 0x0fff0000) >> 16;
2158
2159                 if (!action)
2160                         break;
2161
2162                 switch(action & 0xf0000000) {
2163                 case PHY_READ:
2164                         predata = rtl_readphy(tp, regno);
2165                         count++;
2166                         index++;
2167                         break;
2168                 case PHY_DATA_OR:
2169                         predata |= data;
2170                         index++;
2171                         break;
2172                 case PHY_DATA_AND:
2173                         predata &= data;
2174                         index++;
2175                         break;
2176                 case PHY_BJMPN:
2177                         index -= regno;
2178                         break;
2179                 case PHY_READ_EFUSE:
2180                         predata = rtl8168d_efuse_read(tp->mmio_addr, regno);
2181                         index++;
2182                         break;
2183                 case PHY_CLEAR_READCOUNT:
2184                         count = 0;
2185                         index++;
2186                         break;
2187                 case PHY_WRITE:
2188                         rtl_writephy(tp, regno, data);
2189                         index++;
2190                         break;
2191                 case PHY_READCOUNT_EQ_SKIP:
2192                         index += (count == data) ? 2 : 1;
2193                         break;
2194                 case PHY_COMP_EQ_SKIPN:
2195                         if (predata == data)
2196                                 index += regno;
2197                         index++;
2198                         break;
2199                 case PHY_COMP_NEQ_SKIPN:
2200                         if (predata != data)
2201                                 index += regno;
2202                         index++;
2203                         break;
2204                 case PHY_WRITE_PREVIOUS:
2205                         rtl_writephy(tp, regno, predata);
2206                         index++;
2207                         break;
2208                 case PHY_SKIPN:
2209                         index += regno + 1;
2210                         break;
2211                 case PHY_DELAY_MS:
2212                         mdelay(data);
2213                         index++;
2214                         break;
2215
2216                 case PHY_READ_MAC_BYTE:
2217                 case PHY_WRITE_MAC_BYTE:
2218                 case PHY_WRITE_ERI_WORD:
2219                 default:
2220                         BUG();
2221                 }
2222         }
2223 }
2224
2225 static void rtl_release_firmware(struct rtl8169_private *tp)
2226 {
2227         if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2228                 release_firmware(tp->rtl_fw->fw);
2229                 kfree(tp->rtl_fw);
2230         }
2231         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
2232 }
2233
2234 static void rtl_apply_firmware(struct rtl8169_private *tp)
2235 {
2236         struct rtl_fw *rtl_fw = tp->rtl_fw;
2237
2238         /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2239         if (!IS_ERR_OR_NULL(rtl_fw))
2240                 rtl_phy_write_fw(tp, rtl_fw);
2241 }
2242
2243 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2244 {
2245         if (rtl_readphy(tp, reg) != val)
2246                 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2247         else
2248                 rtl_apply_firmware(tp);
2249 }
2250
2251 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2252 {
2253         static const struct phy_reg phy_reg_init[] = {
2254                 { 0x1f, 0x0001 },
2255                 { 0x06, 0x006e },
2256                 { 0x08, 0x0708 },
2257                 { 0x15, 0x4000 },
2258                 { 0x18, 0x65c7 },
2259
2260                 { 0x1f, 0x0001 },
2261                 { 0x03, 0x00a1 },
2262                 { 0x02, 0x0008 },
2263                 { 0x01, 0x0120 },
2264                 { 0x00, 0x1000 },
2265                 { 0x04, 0x0800 },
2266                 { 0x04, 0x0000 },
2267
2268                 { 0x03, 0xff41 },
2269                 { 0x02, 0xdf60 },
2270                 { 0x01, 0x0140 },
2271                 { 0x00, 0x0077 },
2272                 { 0x04, 0x7800 },
2273                 { 0x04, 0x7000 },
2274
2275                 { 0x03, 0x802f },
2276                 { 0x02, 0x4f02 },
2277                 { 0x01, 0x0409 },
2278                 { 0x00, 0xf0f9 },
2279                 { 0x04, 0x9800 },
2280                 { 0x04, 0x9000 },
2281
2282                 { 0x03, 0xdf01 },
2283                 { 0x02, 0xdf20 },
2284                 { 0x01, 0xff95 },
2285                 { 0x00, 0xba00 },
2286                 { 0x04, 0xa800 },
2287                 { 0x04, 0xa000 },
2288
2289                 { 0x03, 0xff41 },
2290                 { 0x02, 0xdf20 },
2291                 { 0x01, 0x0140 },
2292                 { 0x00, 0x00bb },
2293                 { 0x04, 0xb800 },
2294                 { 0x04, 0xb000 },
2295
2296                 { 0x03, 0xdf41 },
2297                 { 0x02, 0xdc60 },
2298                 { 0x01, 0x6340 },
2299                 { 0x00, 0x007d },
2300                 { 0x04, 0xd800 },
2301                 { 0x04, 0xd000 },
2302
2303                 { 0x03, 0xdf01 },
2304                 { 0x02, 0xdf20 },
2305                 { 0x01, 0x100a },
2306                 { 0x00, 0xa0ff },
2307                 { 0x04, 0xf800 },
2308                 { 0x04, 0xf000 },
2309
2310                 { 0x1f, 0x0000 },
2311                 { 0x0b, 0x0000 },
2312                 { 0x00, 0x9200 }
2313         };
2314
2315         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2316 }
2317
2318 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2319 {
2320         static const struct phy_reg phy_reg_init[] = {
2321                 { 0x1f, 0x0002 },
2322                 { 0x01, 0x90d0 },
2323                 { 0x1f, 0x0000 }
2324         };
2325
2326         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2327 }
2328
2329 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2330 {
2331         struct pci_dev *pdev = tp->pci_dev;
2332
2333         if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2334             (pdev->subsystem_device != 0xe000))
2335                 return;
2336
2337         rtl_writephy(tp, 0x1f, 0x0001);
2338         rtl_writephy(tp, 0x10, 0xf01b);
2339         rtl_writephy(tp, 0x1f, 0x0000);
2340 }
2341
2342 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2343 {
2344         static const struct phy_reg phy_reg_init[] = {
2345                 { 0x1f, 0x0001 },
2346                 { 0x04, 0x0000 },
2347                 { 0x03, 0x00a1 },
2348                 { 0x02, 0x0008 },
2349                 { 0x01, 0x0120 },
2350                 { 0x00, 0x1000 },
2351                 { 0x04, 0x0800 },
2352                 { 0x04, 0x9000 },
2353                 { 0x03, 0x802f },
2354                 { 0x02, 0x4f02 },
2355                 { 0x01, 0x0409 },
2356                 { 0x00, 0xf099 },
2357                 { 0x04, 0x9800 },
2358                 { 0x04, 0xa000 },
2359                 { 0x03, 0xdf01 },
2360                 { 0x02, 0xdf20 },
2361                 { 0x01, 0xff95 },
2362                 { 0x00, 0xba00 },
2363                 { 0x04, 0xa800 },
2364                 { 0x04, 0xf000 },
2365                 { 0x03, 0xdf01 },
2366                 { 0x02, 0xdf20 },
2367                 { 0x01, 0x101a },
2368                 { 0x00, 0xa0ff },
2369                 { 0x04, 0xf800 },
2370                 { 0x04, 0x0000 },
2371                 { 0x1f, 0x0000 },
2372
2373                 { 0x1f, 0x0001 },
2374                 { 0x10, 0xf41b },
2375                 { 0x14, 0xfb54 },
2376                 { 0x18, 0xf5c7 },
2377                 { 0x1f, 0x0000 },
2378
2379                 { 0x1f, 0x0001 },
2380                 { 0x17, 0x0cc0 },
2381                 { 0x1f, 0x0000 }
2382         };
2383
2384         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2385
2386         rtl8169scd_hw_phy_config_quirk(tp);
2387 }
2388
2389 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2390 {
2391         static const struct phy_reg phy_reg_init[] = {
2392                 { 0x1f, 0x0001 },
2393                 { 0x04, 0x0000 },
2394                 { 0x03, 0x00a1 },
2395                 { 0x02, 0x0008 },
2396                 { 0x01, 0x0120 },
2397                 { 0x00, 0x1000 },
2398                 { 0x04, 0x0800 },
2399                 { 0x04, 0x9000 },
2400                 { 0x03, 0x802f },
2401                 { 0x02, 0x4f02 },
2402                 { 0x01, 0x0409 },
2403                 { 0x00, 0xf099 },
2404                 { 0x04, 0x9800 },
2405                 { 0x04, 0xa000 },
2406                 { 0x03, 0xdf01 },
2407                 { 0x02, 0xdf20 },
2408                 { 0x01, 0xff95 },
2409                 { 0x00, 0xba00 },
2410                 { 0x04, 0xa800 },
2411                 { 0x04, 0xf000 },
2412                 { 0x03, 0xdf01 },
2413                 { 0x02, 0xdf20 },
2414                 { 0x01, 0x101a },
2415                 { 0x00, 0xa0ff },
2416                 { 0x04, 0xf800 },
2417                 { 0x04, 0x0000 },
2418                 { 0x1f, 0x0000 },
2419
2420                 { 0x1f, 0x0001 },
2421                 { 0x0b, 0x8480 },
2422                 { 0x1f, 0x0000 },
2423
2424                 { 0x1f, 0x0001 },
2425                 { 0x18, 0x67c7 },
2426                 { 0x04, 0x2000 },
2427                 { 0x03, 0x002f },
2428                 { 0x02, 0x4360 },
2429                 { 0x01, 0x0109 },
2430                 { 0x00, 0x3022 },
2431                 { 0x04, 0x2800 },
2432                 { 0x1f, 0x0000 },
2433
2434                 { 0x1f, 0x0001 },
2435                 { 0x17, 0x0cc0 },
2436                 { 0x1f, 0x0000 }
2437         };
2438
2439         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2440 }
2441
2442 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2443 {
2444         static const struct phy_reg phy_reg_init[] = {
2445                 { 0x10, 0xf41b },
2446                 { 0x1f, 0x0000 }
2447         };
2448
2449         rtl_writephy(tp, 0x1f, 0x0001);
2450         rtl_patchphy(tp, 0x16, 1 << 0);
2451
2452         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2453 }
2454
2455 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2456 {
2457         static const struct phy_reg phy_reg_init[] = {
2458                 { 0x1f, 0x0001 },
2459                 { 0x10, 0xf41b },
2460                 { 0x1f, 0x0000 }
2461         };
2462
2463         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2464 }
2465
2466 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2467 {
2468         static const struct phy_reg phy_reg_init[] = {
2469                 { 0x1f, 0x0000 },
2470                 { 0x1d, 0x0f00 },
2471                 { 0x1f, 0x0002 },
2472                 { 0x0c, 0x1ec8 },
2473                 { 0x1f, 0x0000 }
2474         };
2475
2476         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2477 }
2478
2479 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2480 {
2481         static const struct phy_reg phy_reg_init[] = {
2482                 { 0x1f, 0x0001 },
2483                 { 0x1d, 0x3d98 },
2484                 { 0x1f, 0x0000 }
2485         };
2486
2487         rtl_writephy(tp, 0x1f, 0x0000);
2488         rtl_patchphy(tp, 0x14, 1 << 5);
2489         rtl_patchphy(tp, 0x0d, 1 << 5);
2490
2491         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2492 }
2493
2494 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2495 {
2496         static const struct phy_reg phy_reg_init[] = {
2497                 { 0x1f, 0x0001 },
2498                 { 0x12, 0x2300 },
2499                 { 0x1f, 0x0002 },
2500                 { 0x00, 0x88d4 },
2501                 { 0x01, 0x82b1 },
2502                 { 0x03, 0x7002 },
2503                 { 0x08, 0x9e30 },
2504                 { 0x09, 0x01f0 },
2505                 { 0x0a, 0x5500 },
2506                 { 0x0c, 0x00c8 },
2507                 { 0x1f, 0x0003 },
2508                 { 0x12, 0xc096 },
2509                 { 0x16, 0x000a },
2510                 { 0x1f, 0x0000 },
2511                 { 0x1f, 0x0000 },
2512                 { 0x09, 0x2000 },
2513                 { 0x09, 0x0000 }
2514         };
2515
2516         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2517
2518         rtl_patchphy(tp, 0x14, 1 << 5);
2519         rtl_patchphy(tp, 0x0d, 1 << 5);
2520         rtl_writephy(tp, 0x1f, 0x0000);
2521 }
2522
2523 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2524 {
2525         static const struct phy_reg phy_reg_init[] = {
2526                 { 0x1f, 0x0001 },
2527                 { 0x12, 0x2300 },
2528                 { 0x03, 0x802f },
2529                 { 0x02, 0x4f02 },
2530                 { 0x01, 0x0409 },
2531                 { 0x00, 0xf099 },
2532                 { 0x04, 0x9800 },
2533                 { 0x04, 0x9000 },
2534                 { 0x1d, 0x3d98 },
2535                 { 0x1f, 0x0002 },
2536                 { 0x0c, 0x7eb8 },
2537                 { 0x06, 0x0761 },
2538                 { 0x1f, 0x0003 },
2539                 { 0x16, 0x0f0a },
2540                 { 0x1f, 0x0000 }
2541         };
2542
2543         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2544
2545         rtl_patchphy(tp, 0x16, 1 << 0);
2546         rtl_patchphy(tp, 0x14, 1 << 5);
2547         rtl_patchphy(tp, 0x0d, 1 << 5);
2548         rtl_writephy(tp, 0x1f, 0x0000);
2549 }
2550
2551 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2552 {
2553         static const struct phy_reg phy_reg_init[] = {
2554                 { 0x1f, 0x0001 },
2555                 { 0x12, 0x2300 },
2556                 { 0x1d, 0x3d98 },
2557                 { 0x1f, 0x0002 },
2558                 { 0x0c, 0x7eb8 },
2559                 { 0x06, 0x5461 },
2560                 { 0x1f, 0x0003 },
2561                 { 0x16, 0x0f0a },
2562                 { 0x1f, 0x0000 }
2563         };
2564
2565         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2566
2567         rtl_patchphy(tp, 0x16, 1 << 0);
2568         rtl_patchphy(tp, 0x14, 1 << 5);
2569         rtl_patchphy(tp, 0x0d, 1 << 5);
2570         rtl_writephy(tp, 0x1f, 0x0000);
2571 }
2572
2573 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2574 {
2575         rtl8168c_3_hw_phy_config(tp);
2576 }
2577
2578 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2579 {
2580         static const struct phy_reg phy_reg_init_0[] = {
2581                 /* Channel Estimation */
2582                 { 0x1f, 0x0001 },
2583                 { 0x06, 0x4064 },
2584                 { 0x07, 0x2863 },
2585                 { 0x08, 0x059c },
2586                 { 0x09, 0x26b4 },
2587                 { 0x0a, 0x6a19 },
2588                 { 0x0b, 0xdcc8 },
2589                 { 0x10, 0xf06d },
2590                 { 0x14, 0x7f68 },
2591                 { 0x18, 0x7fd9 },
2592                 { 0x1c, 0xf0ff },
2593                 { 0x1d, 0x3d9c },
2594                 { 0x1f, 0x0003 },
2595                 { 0x12, 0xf49f },
2596                 { 0x13, 0x070b },
2597                 { 0x1a, 0x05ad },
2598                 { 0x14, 0x94c0 },
2599
2600                 /*
2601                  * Tx Error Issue
2602                  * Enhance line driver power
2603                  */
2604                 { 0x1f, 0x0002 },
2605                 { 0x06, 0x5561 },
2606                 { 0x1f, 0x0005 },
2607                 { 0x05, 0x8332 },
2608                 { 0x06, 0x5561 },
2609
2610                 /*
2611                  * Can not link to 1Gbps with bad cable
2612                  * Decrease SNR threshold form 21.07dB to 19.04dB
2613                  */
2614                 { 0x1f, 0x0001 },
2615                 { 0x17, 0x0cc0 },
2616
2617                 { 0x1f, 0x0000 },
2618                 { 0x0d, 0xf880 }
2619         };
2620         void __iomem *ioaddr = tp->mmio_addr;
2621
2622         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2623
2624         /*
2625          * Rx Error Issue
2626          * Fine Tune Switching regulator parameter
2627          */
2628         rtl_writephy(tp, 0x1f, 0x0002);
2629         rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2630         rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
2631
2632         if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2633                 static const struct phy_reg phy_reg_init[] = {
2634                         { 0x1f, 0x0002 },
2635                         { 0x05, 0x669a },
2636                         { 0x1f, 0x0005 },
2637                         { 0x05, 0x8330 },
2638                         { 0x06, 0x669a },
2639                         { 0x1f, 0x0002 }
2640                 };
2641                 int val;
2642
2643                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2644
2645                 val = rtl_readphy(tp, 0x0d);
2646
2647                 if ((val & 0x00ff) != 0x006c) {
2648                         static const u32 set[] = {
2649                                 0x0065, 0x0066, 0x0067, 0x0068,
2650                                 0x0069, 0x006a, 0x006b, 0x006c
2651                         };
2652                         int i;
2653
2654                         rtl_writephy(tp, 0x1f, 0x0002);
2655
2656                         val &= 0xff00;
2657                         for (i = 0; i < ARRAY_SIZE(set); i++)
2658                                 rtl_writephy(tp, 0x0d, val | set[i]);
2659                 }
2660         } else {
2661                 static const struct phy_reg phy_reg_init[] = {
2662                         { 0x1f, 0x0002 },
2663                         { 0x05, 0x6662 },
2664                         { 0x1f, 0x0005 },
2665                         { 0x05, 0x8330 },
2666                         { 0x06, 0x6662 }
2667                 };
2668
2669                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2670         }
2671
2672         /* RSET couple improve */
2673         rtl_writephy(tp, 0x1f, 0x0002);
2674         rtl_patchphy(tp, 0x0d, 0x0300);
2675         rtl_patchphy(tp, 0x0f, 0x0010);
2676
2677         /* Fine tune PLL performance */
2678         rtl_writephy(tp, 0x1f, 0x0002);
2679         rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2680         rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2681
2682         rtl_writephy(tp, 0x1f, 0x0005);
2683         rtl_writephy(tp, 0x05, 0x001b);
2684
2685         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2686
2687         rtl_writephy(tp, 0x1f, 0x0000);
2688 }
2689
2690 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2691 {
2692         static const struct phy_reg phy_reg_init_0[] = {
2693                 /* Channel Estimation */
2694                 { 0x1f, 0x0001 },
2695                 { 0x06, 0x4064 },
2696                 { 0x07, 0x2863 },
2697                 { 0x08, 0x059c },
2698                 { 0x09, 0x26b4 },
2699                 { 0x0a, 0x6a19 },
2700                 { 0x0b, 0xdcc8 },
2701                 { 0x10, 0xf06d },
2702                 { 0x14, 0x7f68 },
2703                 { 0x18, 0x7fd9 },
2704                 { 0x1c, 0xf0ff },
2705                 { 0x1d, 0x3d9c },
2706                 { 0x1f, 0x0003 },
2707                 { 0x12, 0xf49f },
2708                 { 0x13, 0x070b },
2709                 { 0x1a, 0x05ad },
2710                 { 0x14, 0x94c0 },
2711
2712                 /*
2713                  * Tx Error Issue
2714                  * Enhance line driver power
2715                  */
2716                 { 0x1f, 0x0002 },
2717                 { 0x06, 0x5561 },
2718                 { 0x1f, 0x0005 },
2719                 { 0x05, 0x8332 },
2720                 { 0x06, 0x5561 },
2721
2722                 /*
2723                  * Can not link to 1Gbps with bad cable
2724                  * Decrease SNR threshold form 21.07dB to 19.04dB
2725                  */
2726                 { 0x1f, 0x0001 },
2727                 { 0x17, 0x0cc0 },
2728
2729                 { 0x1f, 0x0000 },
2730                 { 0x0d, 0xf880 }
2731         };
2732         void __iomem *ioaddr = tp->mmio_addr;
2733
2734         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2735
2736         if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2737                 static const struct phy_reg phy_reg_init[] = {
2738                         { 0x1f, 0x0002 },
2739                         { 0x05, 0x669a },
2740                         { 0x1f, 0x0005 },
2741                         { 0x05, 0x8330 },
2742                         { 0x06, 0x669a },
2743
2744                         { 0x1f, 0x0002 }
2745                 };
2746                 int val;
2747
2748                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2749
2750                 val = rtl_readphy(tp, 0x0d);
2751                 if ((val & 0x00ff) != 0x006c) {
2752                         static const u32 set[] = {
2753                                 0x0065, 0x0066, 0x0067, 0x0068,
2754                                 0x0069, 0x006a, 0x006b, 0x006c
2755                         };
2756                         int i;
2757
2758                         rtl_writephy(tp, 0x1f, 0x0002);
2759
2760                         val &= 0xff00;
2761                         for (i = 0; i < ARRAY_SIZE(set); i++)
2762                                 rtl_writephy(tp, 0x0d, val | set[i]);
2763                 }
2764         } else {
2765                 static const struct phy_reg phy_reg_init[] = {
2766                         { 0x1f, 0x0002 },
2767                         { 0x05, 0x2642 },
2768                         { 0x1f, 0x0005 },
2769                         { 0x05, 0x8330 },
2770                         { 0x06, 0x2642 }
2771                 };
2772
2773                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2774         }
2775
2776         /* Fine tune PLL performance */
2777         rtl_writephy(tp, 0x1f, 0x0002);
2778         rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2779         rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2780
2781         /* Switching regulator Slew rate */
2782         rtl_writephy(tp, 0x1f, 0x0002);
2783         rtl_patchphy(tp, 0x0f, 0x0017);
2784
2785         rtl_writephy(tp, 0x1f, 0x0005);
2786         rtl_writephy(tp, 0x05, 0x001b);
2787
2788         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
2789
2790         rtl_writephy(tp, 0x1f, 0x0000);
2791 }
2792
2793 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
2794 {
2795         static const struct phy_reg phy_reg_init[] = {
2796                 { 0x1f, 0x0002 },
2797                 { 0x10, 0x0008 },
2798                 { 0x0d, 0x006c },
2799
2800                 { 0x1f, 0x0000 },
2801                 { 0x0d, 0xf880 },
2802
2803                 { 0x1f, 0x0001 },
2804                 { 0x17, 0x0cc0 },
2805
2806                 { 0x1f, 0x0001 },
2807                 { 0x0b, 0xa4d8 },
2808                 { 0x09, 0x281c },
2809                 { 0x07, 0x2883 },
2810                 { 0x0a, 0x6b35 },
2811                 { 0x1d, 0x3da4 },
2812                 { 0x1c, 0xeffd },
2813                 { 0x14, 0x7f52 },
2814                 { 0x18, 0x7fc6 },
2815                 { 0x08, 0x0601 },
2816                 { 0x06, 0x4063 },
2817                 { 0x10, 0xf074 },
2818                 { 0x1f, 0x0003 },
2819                 { 0x13, 0x0789 },
2820                 { 0x12, 0xf4bd },
2821                 { 0x1a, 0x04fd },
2822                 { 0x14, 0x84b0 },
2823                 { 0x1f, 0x0000 },
2824                 { 0x00, 0x9200 },
2825
2826                 { 0x1f, 0x0005 },
2827                 { 0x01, 0x0340 },
2828                 { 0x1f, 0x0001 },
2829                 { 0x04, 0x4000 },
2830                 { 0x03, 0x1d21 },
2831                 { 0x02, 0x0c32 },
2832                 { 0x01, 0x0200 },
2833                 { 0x00, 0x5554 },
2834                 { 0x04, 0x4800 },
2835                 { 0x04, 0x4000 },
2836                 { 0x04, 0xf000 },
2837                 { 0x03, 0xdf01 },
2838                 { 0x02, 0xdf20 },
2839                 { 0x01, 0x101a },
2840                 { 0x00, 0xa0ff },
2841                 { 0x04, 0xf800 },
2842                 { 0x04, 0xf000 },
2843                 { 0x1f, 0x0000 },
2844
2845                 { 0x1f, 0x0007 },
2846                 { 0x1e, 0x0023 },
2847                 { 0x16, 0x0000 },
2848                 { 0x1f, 0x0000 }
2849         };
2850
2851         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2852 }
2853
2854 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2855 {
2856         static const struct phy_reg phy_reg_init[] = {
2857                 { 0x1f, 0x0001 },
2858                 { 0x17, 0x0cc0 },
2859
2860                 { 0x1f, 0x0007 },
2861                 { 0x1e, 0x002d },
2862                 { 0x18, 0x0040 },
2863                 { 0x1f, 0x0000 }
2864         };
2865
2866         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2867         rtl_patchphy(tp, 0x0d, 1 << 5);
2868 }
2869
2870 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
2871 {
2872         static const struct phy_reg phy_reg_init[] = {
2873                 /* Enable Delay cap */
2874                 { 0x1f, 0x0005 },
2875                 { 0x05, 0x8b80 },
2876                 { 0x06, 0xc896 },
2877                 { 0x1f, 0x0000 },
2878
2879                 /* Channel estimation fine tune */
2880                 { 0x1f, 0x0001 },
2881                 { 0x0b, 0x6c20 },
2882                 { 0x07, 0x2872 },
2883                 { 0x1c, 0xefff },
2884                 { 0x1f, 0x0003 },
2885                 { 0x14, 0x6420 },
2886                 { 0x1f, 0x0000 },
2887
2888                 /* Update PFM & 10M TX idle timer */
2889                 { 0x1f, 0x0007 },
2890                 { 0x1e, 0x002f },
2891                 { 0x15, 0x1919 },
2892                 { 0x1f, 0x0000 },
2893
2894                 { 0x1f, 0x0007 },
2895                 { 0x1e, 0x00ac },
2896                 { 0x18, 0x0006 },
2897                 { 0x1f, 0x0000 }
2898         };
2899
2900         rtl_apply_firmware(tp);
2901
2902         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2903
2904         /* DCO enable for 10M IDLE Power */
2905         rtl_writephy(tp, 0x1f, 0x0007);
2906         rtl_writephy(tp, 0x1e, 0x0023);
2907         rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2908         rtl_writephy(tp, 0x1f, 0x0000);
2909
2910         /* For impedance matching */
2911         rtl_writephy(tp, 0x1f, 0x0002);
2912         rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
2913         rtl_writephy(tp, 0x1f, 0x0000);
2914
2915         /* PHY auto speed down */
2916         rtl_writephy(tp, 0x1f, 0x0007);
2917         rtl_writephy(tp, 0x1e, 0x002d);
2918         rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
2919         rtl_writephy(tp, 0x1f, 0x0000);
2920         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2921
2922         rtl_writephy(tp, 0x1f, 0x0005);
2923         rtl_writephy(tp, 0x05, 0x8b86);
2924         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2925         rtl_writephy(tp, 0x1f, 0x0000);
2926
2927         rtl_writephy(tp, 0x1f, 0x0005);
2928         rtl_writephy(tp, 0x05, 0x8b85);
2929         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
2930         rtl_writephy(tp, 0x1f, 0x0007);
2931         rtl_writephy(tp, 0x1e, 0x0020);
2932         rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
2933         rtl_writephy(tp, 0x1f, 0x0006);
2934         rtl_writephy(tp, 0x00, 0x5a00);
2935         rtl_writephy(tp, 0x1f, 0x0000);
2936         rtl_writephy(tp, 0x0d, 0x0007);
2937         rtl_writephy(tp, 0x0e, 0x003c);
2938         rtl_writephy(tp, 0x0d, 0x4007);
2939         rtl_writephy(tp, 0x0e, 0x0000);
2940         rtl_writephy(tp, 0x0d, 0x0000);
2941 }
2942
2943 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
2944 {
2945         static const struct phy_reg phy_reg_init[] = {
2946                 /* Enable Delay cap */
2947                 { 0x1f, 0x0004 },
2948                 { 0x1f, 0x0007 },
2949                 { 0x1e, 0x00ac },
2950                 { 0x18, 0x0006 },
2951                 { 0x1f, 0x0002 },
2952                 { 0x1f, 0x0000 },
2953                 { 0x1f, 0x0000 },
2954
2955                 /* Channel estimation fine tune */
2956                 { 0x1f, 0x0003 },
2957                 { 0x09, 0xa20f },
2958                 { 0x1f, 0x0000 },
2959                 { 0x1f, 0x0000 },
2960
2961                 /* Green Setting */
2962                 { 0x1f, 0x0005 },
2963                 { 0x05, 0x8b5b },
2964                 { 0x06, 0x9222 },
2965                 { 0x05, 0x8b6d },
2966                 { 0x06, 0x8000 },
2967                 { 0x05, 0x8b76 },
2968                 { 0x06, 0x8000 },
2969                 { 0x1f, 0x0000 }
2970         };
2971
2972         rtl_apply_firmware(tp);
2973
2974         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2975
2976         /* For 4-corner performance improve */
2977         rtl_writephy(tp, 0x1f, 0x0005);
2978         rtl_writephy(tp, 0x05, 0x8b80);
2979         rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2980         rtl_writephy(tp, 0x1f, 0x0000);
2981
2982         /* PHY auto speed down */
2983         rtl_writephy(tp, 0x1f, 0x0004);
2984         rtl_writephy(tp, 0x1f, 0x0007);
2985         rtl_writephy(tp, 0x1e, 0x002d);
2986         rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
2987         rtl_writephy(tp, 0x1f, 0x0002);
2988         rtl_writephy(tp, 0x1f, 0x0000);
2989         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2990
2991         /* improve 10M EEE waveform */
2992         rtl_writephy(tp, 0x1f, 0x0005);
2993         rtl_writephy(tp, 0x05, 0x8b86);
2994         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2995         rtl_writephy(tp, 0x1f, 0x0000);
2996
2997         /* Improve 2-pair detection performance */
2998         rtl_writephy(tp, 0x1f, 0x0005);
2999         rtl_writephy(tp, 0x05, 0x8b85);
3000         rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3001         rtl_writephy(tp, 0x1f, 0x0000);
3002
3003         /* EEE setting */
3004         rtl_w1w0_eri(tp->mmio_addr, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003,
3005                      ERIAR_EXGMAC);
3006         rtl_writephy(tp, 0x1f, 0x0005);
3007         rtl_writephy(tp, 0x05, 0x8b85);
3008         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3009         rtl_writephy(tp, 0x1f, 0x0004);
3010         rtl_writephy(tp, 0x1f, 0x0007);
3011         rtl_writephy(tp, 0x1e, 0x0020);
3012         rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
3013         rtl_writephy(tp, 0x1f, 0x0002);
3014         rtl_writephy(tp, 0x1f, 0x0000);
3015         rtl_writephy(tp, 0x0d, 0x0007);
3016         rtl_writephy(tp, 0x0e, 0x003c);
3017         rtl_writephy(tp, 0x0d, 0x4007);
3018         rtl_writephy(tp, 0x0e, 0x0000);
3019         rtl_writephy(tp, 0x0d, 0x0000);
3020
3021         /* Green feature */
3022         rtl_writephy(tp, 0x1f, 0x0003);
3023         rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
3024         rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
3025         rtl_writephy(tp, 0x1f, 0x0000);
3026 }
3027
3028 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3029 {
3030         static const struct phy_reg phy_reg_init[] = {
3031                 /* Channel estimation fine tune */
3032                 { 0x1f, 0x0003 },
3033                 { 0x09, 0xa20f },
3034                 { 0x1f, 0x0000 },
3035
3036                 /* Modify green table for giga & fnet */
3037                 { 0x1f, 0x0005 },
3038                 { 0x05, 0x8b55 },
3039                 { 0x06, 0x0000 },
3040                 { 0x05, 0x8b5e },
3041                 { 0x06, 0x0000 },
3042                 { 0x05, 0x8b67 },
3043                 { 0x06, 0x0000 },
3044                 { 0x05, 0x8b70 },
3045                 { 0x06, 0x0000 },
3046                 { 0x1f, 0x0000 },
3047                 { 0x1f, 0x0007 },
3048                 { 0x1e, 0x0078 },
3049                 { 0x17, 0x0000 },
3050                 { 0x19, 0x00fb },
3051                 { 0x1f, 0x0000 },
3052
3053                 /* Modify green table for 10M */
3054                 { 0x1f, 0x0005 },
3055                 { 0x05, 0x8b79 },
3056                 { 0x06, 0xaa00 },
3057                 { 0x1f, 0x0000 },
3058
3059                 /* Disable hiimpedance detection (RTCT) */
3060                 { 0x1f, 0x0003 },
3061                 { 0x01, 0x328a },
3062                 { 0x1f, 0x0000 }
3063         };
3064
3065         rtl_apply_firmware(tp);
3066
3067         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3068
3069         /* For 4-corner performance improve */
3070         rtl_writephy(tp, 0x1f, 0x0005);
3071         rtl_writephy(tp, 0x05, 0x8b80);
3072         rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000);
3073         rtl_writephy(tp, 0x1f, 0x0000);
3074
3075         /* PHY auto speed down */
3076         rtl_writephy(tp, 0x1f, 0x0007);
3077         rtl_writephy(tp, 0x1e, 0x002d);
3078         rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3079         rtl_writephy(tp, 0x1f, 0x0000);
3080         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3081
3082         /* Improve 10M EEE waveform */
3083         rtl_writephy(tp, 0x1f, 0x0005);
3084         rtl_writephy(tp, 0x05, 0x8b86);
3085         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3086         rtl_writephy(tp, 0x1f, 0x0000);
3087
3088         /* Improve 2-pair detection performance */
3089         rtl_writephy(tp, 0x1f, 0x0005);
3090         rtl_writephy(tp, 0x05, 0x8b85);
3091         rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3092         rtl_writephy(tp, 0x1f, 0x0000);
3093 }
3094
3095 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3096 {
3097         rtl_apply_firmware(tp);
3098
3099         /* For 4-corner performance improve */
3100         rtl_writephy(tp, 0x1f, 0x0005);
3101         rtl_writephy(tp, 0x05, 0x8b80);
3102         rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000);
3103         rtl_writephy(tp, 0x1f, 0x0000);
3104
3105         /* PHY auto speed down */
3106         rtl_writephy(tp, 0x1f, 0x0007);
3107         rtl_writephy(tp, 0x1e, 0x002d);
3108         rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3109         rtl_writephy(tp, 0x1f, 0x0000);
3110         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3111
3112         /* Improve 10M EEE waveform */
3113         rtl_writephy(tp, 0x1f, 0x0005);
3114         rtl_writephy(tp, 0x05, 0x8b86);
3115         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3116         rtl_writephy(tp, 0x1f, 0x0000);
3117 }
3118
3119 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
3120 {
3121         static const struct phy_reg phy_reg_init[] = {
3122                 { 0x1f, 0x0003 },
3123                 { 0x08, 0x441d },
3124                 { 0x01, 0x9100 },
3125                 { 0x1f, 0x0000 }
3126         };
3127
3128         rtl_writephy(tp, 0x1f, 0x0000);
3129         rtl_patchphy(tp, 0x11, 1 << 12);
3130         rtl_patchphy(tp, 0x19, 1 << 13);
3131         rtl_patchphy(tp, 0x10, 1 << 15);
3132
3133         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3134 }
3135
3136 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3137 {
3138         static const struct phy_reg phy_reg_init[] = {
3139                 { 0x1f, 0x0005 },
3140                 { 0x1a, 0x0000 },
3141                 { 0x1f, 0x0000 },
3142
3143                 { 0x1f, 0x0004 },
3144                 { 0x1c, 0x0000 },
3145                 { 0x1f, 0x0000 },
3146
3147                 { 0x1f, 0x0001 },
3148                 { 0x15, 0x7701 },
3149                 { 0x1f, 0x0000 }
3150         };
3151
3152         /* Disable ALDPS before ram code */
3153         rtl_writephy(tp, 0x1f, 0x0000);
3154         rtl_writephy(tp, 0x18, 0x0310);
3155         msleep(100);
3156
3157         rtl_apply_firmware(tp);
3158
3159         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3160 }
3161
3162 static void rtl_hw_phy_config(struct net_device *dev)
3163 {
3164         struct rtl8169_private *tp = netdev_priv(dev);
3165
3166         rtl8169_print_mac_version(tp);
3167
3168         switch (tp->mac_version) {
3169         case RTL_GIGA_MAC_VER_01:
3170                 break;
3171         case RTL_GIGA_MAC_VER_02:
3172         case RTL_GIGA_MAC_VER_03:
3173                 rtl8169s_hw_phy_config(tp);
3174                 break;
3175         case RTL_GIGA_MAC_VER_04:
3176                 rtl8169sb_hw_phy_config(tp);
3177                 break;
3178         case RTL_GIGA_MAC_VER_05:
3179                 rtl8169scd_hw_phy_config(tp);
3180                 break;
3181         case RTL_GIGA_MAC_VER_06:
3182                 rtl8169sce_hw_phy_config(tp);
3183                 break;
3184         case RTL_GIGA_MAC_VER_07:
3185         case RTL_GIGA_MAC_VER_08:
3186         case RTL_GIGA_MAC_VER_09:
3187                 rtl8102e_hw_phy_config(tp);
3188                 break;
3189         case RTL_GIGA_MAC_VER_11:
3190                 rtl8168bb_hw_phy_config(tp);
3191                 break;
3192         case RTL_GIGA_MAC_VER_12:
3193                 rtl8168bef_hw_phy_config(tp);
3194                 break;
3195         case RTL_GIGA_MAC_VER_17:
3196                 rtl8168bef_hw_phy_config(tp);
3197                 break;
3198         case RTL_GIGA_MAC_VER_18:
3199                 rtl8168cp_1_hw_phy_config(tp);
3200                 break;
3201         case RTL_GIGA_MAC_VER_19:
3202                 rtl8168c_1_hw_phy_config(tp);
3203                 break;
3204         case RTL_GIGA_MAC_VER_20:
3205                 rtl8168c_2_hw_phy_config(tp);
3206                 break;
3207         case RTL_GIGA_MAC_VER_21:
3208                 rtl8168c_3_hw_phy_config(tp);
3209                 break;
3210         case RTL_GIGA_MAC_VER_22:
3211                 rtl8168c_4_hw_phy_config(tp);
3212                 break;
3213         case RTL_GIGA_MAC_VER_23:
3214         case RTL_GIGA_MAC_VER_24:
3215                 rtl8168cp_2_hw_phy_config(tp);
3216                 break;
3217         case RTL_GIGA_MAC_VER_25:
3218                 rtl8168d_1_hw_phy_config(tp);
3219                 break;
3220         case RTL_GIGA_MAC_VER_26:
3221                 rtl8168d_2_hw_phy_config(tp);
3222                 break;
3223         case RTL_GIGA_MAC_VER_27:
3224                 rtl8168d_3_hw_phy_config(tp);
3225                 break;
3226         case RTL_GIGA_MAC_VER_28:
3227                 rtl8168d_4_hw_phy_config(tp);
3228                 break;
3229         case RTL_GIGA_MAC_VER_29:
3230         case RTL_GIGA_MAC_VER_30:
3231                 rtl8105e_hw_phy_config(tp);
3232                 break;
3233         case RTL_GIGA_MAC_VER_31:
3234                 /* None. */
3235                 break;
3236         case RTL_GIGA_MAC_VER_32:
3237         case RTL_GIGA_MAC_VER_33:
3238                 rtl8168e_1_hw_phy_config(tp);
3239                 break;
3240         case RTL_GIGA_MAC_VER_34:
3241                 rtl8168e_2_hw_phy_config(tp);
3242                 break;
3243         case RTL_GIGA_MAC_VER_35:
3244                 rtl8168f_1_hw_phy_config(tp);
3245                 break;
3246         case RTL_GIGA_MAC_VER_36:
3247                 rtl8168f_2_hw_phy_config(tp);
3248                 break;
3249
3250         default:
3251                 break;
3252         }
3253 }
3254
3255 static void rtl_phy_work(struct rtl8169_private *tp)
3256 {
3257         struct timer_list *timer = &tp->timer;
3258         void __iomem *ioaddr = tp->mmio_addr;
3259         unsigned long timeout = RTL8169_PHY_TIMEOUT;
3260
3261         assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
3262
3263         if (tp->phy_reset_pending(tp)) {
3264                 /*
3265                  * A busy loop could burn quite a few cycles on nowadays CPU.
3266                  * Let's delay the execution of the timer for a few ticks.
3267                  */
3268                 timeout = HZ/10;
3269                 goto out_mod_timer;
3270         }
3271
3272         if (tp->link_ok(ioaddr))
3273                 return;
3274
3275         netif_warn(tp, link, tp->dev, "PHY reset until link up\n");
3276
3277         tp->phy_reset_enable(tp);
3278
3279 out_mod_timer:
3280         mod_timer(timer, jiffies + timeout);
3281 }
3282
3283 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
3284 {
3285         if (!test_and_set_bit(flag, tp->wk.flags))
3286                 schedule_work(&tp->wk.work);
3287 }
3288
3289 static void rtl8169_phy_timer(unsigned long __opaque)
3290 {
3291         struct net_device *dev = (struct net_device *)__opaque;
3292         struct rtl8169_private *tp = netdev_priv(dev);
3293
3294         rtl_schedule_task(tp, RTL_FLAG_TASK_PHY_PENDING);
3295 }
3296
3297 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
3298                                   void __iomem *ioaddr)
3299 {
3300         iounmap(ioaddr);
3301         pci_release_regions(pdev);
3302         pci_clear_mwi(pdev);
3303         pci_disable_device(pdev);
3304         free_netdev(dev);
3305 }
3306
3307 static void rtl8169_phy_reset(struct net_device *dev,
3308                               struct rtl8169_private *tp)
3309 {
3310         unsigned int i;
3311
3312         tp->phy_reset_enable(tp);
3313         for (i = 0; i < 100; i++) {
3314                 if (!tp->phy_reset_pending(tp))
3315                         return;
3316                 msleep(1);
3317         }
3318         netif_err(tp, link, dev, "PHY reset failed\n");
3319 }
3320
3321 static bool rtl_tbi_enabled(struct rtl8169_private *tp)
3322 {
3323         void __iomem *ioaddr = tp->mmio_addr;
3324
3325         return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
3326             (RTL_R8(PHYstatus) & TBI_Enable);
3327 }
3328
3329 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
3330 {
3331         void __iomem *ioaddr = tp->mmio_addr;
3332
3333         rtl_hw_phy_config(dev);
3334
3335         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
3336                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3337                 RTL_W8(0x82, 0x01);
3338         }
3339
3340         pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
3341
3342         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3343                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
3344
3345         if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
3346                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3347                 RTL_W8(0x82, 0x01);
3348                 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
3349                 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
3350         }
3351
3352         rtl8169_phy_reset(dev, tp);
3353
3354         rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
3355                           ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3356                           ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
3357                           (tp->mii.supports_gmii ?
3358                            ADVERTISED_1000baseT_Half |
3359                            ADVERTISED_1000baseT_Full : 0));
3360
3361         if (rtl_tbi_enabled(tp))
3362                 netif_info(tp, link, dev, "TBI auto-negotiating\n");
3363 }
3364
3365 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
3366 {
3367         void __iomem *ioaddr = tp->mmio_addr;
3368         u32 high;
3369         u32 low;
3370
3371         low  = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
3372         high = addr[4] | (addr[5] << 8);
3373
3374         rtl_lock_work(tp);
3375
3376         RTL_W8(Cfg9346, Cfg9346_Unlock);
3377
3378         RTL_W32(MAC4, high);
3379         RTL_R32(MAC4);
3380
3381         RTL_W32(MAC0, low);
3382         RTL_R32(MAC0);
3383
3384         if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
3385                 const struct exgmac_reg e[] = {
3386                         { .addr = 0xe0, ERIAR_MASK_1111, .val = low },
3387                         { .addr = 0xe4, ERIAR_MASK_1111, .val = high },
3388                         { .addr = 0xf0, ERIAR_MASK_1111, .val = low << 16 },
3389                         { .addr = 0xf4, ERIAR_MASK_1111, .val = high << 16 |
3390                                                                 low  >> 16 },
3391                 };
3392
3393                 rtl_write_exgmac_batch(ioaddr, e, ARRAY_SIZE(e));
3394         }
3395
3396         RTL_W8(Cfg9346, Cfg9346_Lock);
3397
3398         rtl_unlock_work(tp);
3399 }
3400
3401 static int rtl_set_mac_address(struct net_device *dev, void *p)
3402 {
3403         struct rtl8169_private *tp = netdev_priv(dev);
3404         struct sockaddr *addr = p;
3405
3406         if (!is_valid_ether_addr(addr->sa_data))
3407                 return -EADDRNOTAVAIL;
3408
3409         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3410
3411         rtl_rar_set(tp, dev->dev_addr);
3412
3413         return 0;
3414 }
3415
3416 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3417 {
3418         struct rtl8169_private *tp = netdev_priv(dev);
3419         struct mii_ioctl_data *data = if_mii(ifr);
3420
3421         return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
3422 }
3423
3424 static int rtl_xmii_ioctl(struct rtl8169_private *tp,
3425                           struct mii_ioctl_data *data, int cmd)
3426 {
3427         switch (cmd) {
3428         case SIOCGMIIPHY:
3429                 data->phy_id = 32; /* Internal PHY */
3430                 return 0;
3431
3432         case SIOCGMIIREG:
3433                 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
3434                 return 0;
3435
3436         case SIOCSMIIREG:
3437                 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
3438                 return 0;
3439         }
3440         return -EOPNOTSUPP;
3441 }
3442
3443 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
3444 {
3445         return -EOPNOTSUPP;
3446 }
3447
3448 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
3449 {
3450         if (tp->features & RTL_FEATURE_MSI) {
3451                 pci_disable_msi(pdev);
3452                 tp->features &= ~RTL_FEATURE_MSI;
3453         }
3454 }
3455
3456 static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp)
3457 {
3458         struct mdio_ops *ops = &tp->mdio_ops;
3459
3460         switch (tp->mac_version) {
3461         case RTL_GIGA_MAC_VER_27:
3462                 ops->write      = r8168dp_1_mdio_write;
3463                 ops->read       = r8168dp_1_mdio_read;
3464                 break;
3465         case RTL_GIGA_MAC_VER_28:
3466         case RTL_GIGA_MAC_VER_31:
3467                 ops->write      = r8168dp_2_mdio_write;
3468                 ops->read       = r8168dp_2_mdio_read;
3469                 break;
3470         default:
3471                 ops->write      = r8169_mdio_write;
3472                 ops->read       = r8169_mdio_read;
3473                 break;
3474         }
3475 }
3476
3477 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
3478 {
3479         void __iomem *ioaddr = tp->mmio_addr;
3480
3481         switch (tp->mac_version) {
3482         case RTL_GIGA_MAC_VER_29:
3483         case RTL_GIGA_MAC_VER_30:
3484         case RTL_GIGA_MAC_VER_32:
3485         case RTL_GIGA_MAC_VER_33:
3486         case RTL_GIGA_MAC_VER_34:
3487                 RTL_W32(RxConfig, RTL_R32(RxConfig) |
3488                         AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
3489                 break;
3490         default:
3491                 break;
3492         }
3493 }
3494
3495 static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
3496 {
3497         if (!(__rtl8169_get_wol(tp) & WAKE_ANY))
3498                 return false;
3499
3500         rtl_writephy(tp, 0x1f, 0x0000);
3501         rtl_writephy(tp, MII_BMCR, 0x0000);
3502
3503         rtl_wol_suspend_quirk(tp);
3504
3505         return true;
3506 }
3507
3508 static void r810x_phy_power_down(struct rtl8169_private *tp)
3509 {
3510         rtl_writephy(tp, 0x1f, 0x0000);
3511         rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3512 }
3513
3514 static void r810x_phy_power_up(struct rtl8169_private *tp)
3515 {
3516         rtl_writephy(tp, 0x1f, 0x0000);
3517         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3518 }
3519
3520 static void r810x_pll_power_down(struct rtl8169_private *tp)
3521 {
3522         if (rtl_wol_pll_power_down(tp))
3523                 return;
3524
3525         r810x_phy_power_down(tp);
3526 }
3527
3528 static void r810x_pll_power_up(struct rtl8169_private *tp)
3529 {
3530         r810x_phy_power_up(tp);
3531 }
3532
3533 static void r8168_phy_power_up(struct rtl8169_private *tp)
3534 {
3535         rtl_writephy(tp, 0x1f, 0x0000);
3536         switch (tp->mac_version) {
3537         case RTL_GIGA_MAC_VER_11:
3538         case RTL_GIGA_MAC_VER_12:
3539         case RTL_GIGA_MAC_VER_17:
3540         case RTL_GIGA_MAC_VER_18:
3541         case RTL_GIGA_MAC_VER_19:
3542         case RTL_GIGA_MAC_VER_20:
3543         case RTL_GIGA_MAC_VER_21:
3544         case RTL_GIGA_MAC_VER_22:
3545         case RTL_GIGA_MAC_VER_23:
3546         case RTL_GIGA_MAC_VER_24:
3547         case RTL_GIGA_MAC_VER_25:
3548         case RTL_GIGA_MAC_VER_26:
3549         case RTL_GIGA_MAC_VER_27:
3550         case RTL_GIGA_MAC_VER_28:
3551         case RTL_GIGA_MAC_VER_31:
3552                 rtl_writephy(tp, 0x0e, 0x0000);
3553                 break;
3554         default:
3555                 break;
3556         }
3557         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3558 }
3559
3560 static void r8168_phy_power_down(struct rtl8169_private *tp)
3561 {
3562         rtl_writephy(tp, 0x1f, 0x0000);
3563         switch (tp->mac_version) {
3564         case RTL_GIGA_MAC_VER_32:
3565         case RTL_GIGA_MAC_VER_33:
3566                 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
3567                 break;
3568
3569         case RTL_GIGA_MAC_VER_11:
3570         case RTL_GIGA_MAC_VER_12:
3571         case RTL_GIGA_MAC_VER_17:
3572         case RTL_GIGA_MAC_VER_18:
3573         case RTL_GIGA_MAC_VER_19:
3574         case RTL_GIGA_MAC_VER_20:
3575         case RTL_GIGA_MAC_VER_21:
3576         case RTL_GIGA_MAC_VER_22:
3577         case RTL_GIGA_MAC_VER_23:
3578         case RTL_GIGA_MAC_VER_24:
3579         case RTL_GIGA_MAC_VER_25:
3580         case RTL_GIGA_MAC_VER_26:
3581         case RTL_GIGA_MAC_VER_27:
3582         case RTL_GIGA_MAC_VER_28:
3583         case RTL_GIGA_MAC_VER_31:
3584                 rtl_writephy(tp, 0x0e, 0x0200);
3585         default:
3586                 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3587                 break;
3588         }
3589 }
3590
3591 static void r8168_pll_power_down(struct rtl8169_private *tp)
3592 {
3593         void __iomem *ioaddr = tp->mmio_addr;
3594
3595         if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3596              tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3597              tp->mac_version == RTL_GIGA_MAC_VER_31) &&
3598             r8168dp_check_dash(tp)) {
3599                 return;
3600         }
3601
3602         if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
3603              tp->mac_version == RTL_GIGA_MAC_VER_24) &&
3604             (RTL_R16(CPlusCmd) & ASF)) {
3605                 return;
3606         }
3607
3608         if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3609             tp->mac_version == RTL_GIGA_MAC_VER_33)
3610                 rtl_ephy_write(ioaddr, 0x19, 0xff64);
3611
3612         if (rtl_wol_pll_power_down(tp))
3613                 return;
3614
3615         r8168_phy_power_down(tp);
3616
3617         switch (tp->mac_version) {
3618         case RTL_GIGA_MAC_VER_25:
3619         case RTL_GIGA_MAC_VER_26:
3620         case RTL_GIGA_MAC_VER_27:
3621         case RTL_GIGA_MAC_VER_28:
3622         case RTL_GIGA_MAC_VER_31:
3623         case RTL_GIGA_MAC_VER_32:
3624         case RTL_GIGA_MAC_VER_33:
3625                 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
3626                 break;
3627         }
3628 }
3629
3630 static void r8168_pll_power_up(struct rtl8169_private *tp)
3631 {
3632         void __iomem *ioaddr = tp->mmio_addr;
3633
3634         if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3635              tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3636              tp->mac_version == RTL_GIGA_MAC_VER_31) &&
3637             r8168dp_check_dash(tp)) {
3638                 return;
3639         }
3640
3641         switch (tp->mac_version) {
3642         case RTL_GIGA_MAC_VER_25:
3643         case RTL_GIGA_MAC_VER_26:
3644         case RTL_GIGA_MAC_VER_27:
3645         case RTL_GIGA_MAC_VER_28:
3646         case RTL_GIGA_MAC_VER_31:
3647         case RTL_GIGA_MAC_VER_32:
3648         case RTL_GIGA_MAC_VER_33:
3649                 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
3650                 break;
3651         }
3652
3653         r8168_phy_power_up(tp);
3654 }
3655
3656 static void rtl_generic_op(struct rtl8169_private *tp,
3657                            void (*op)(struct rtl8169_private *))
3658 {
3659         if (op)
3660                 op(tp);
3661 }
3662
3663 static void rtl_pll_power_down(struct rtl8169_private *tp)
3664 {
3665         rtl_generic_op(tp, tp->pll_power_ops.down);
3666 }
3667
3668 static void rtl_pll_power_up(struct rtl8169_private *tp)
3669 {
3670         rtl_generic_op(tp, tp->pll_power_ops.up);
3671 }
3672
3673 static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
3674 {
3675         struct pll_power_ops *ops = &tp->pll_power_ops;
3676
3677         switch (tp->mac_version) {
3678         case RTL_GIGA_MAC_VER_07:
3679         case RTL_GIGA_MAC_VER_08:
3680         case RTL_GIGA_MAC_VER_09:
3681         case RTL_GIGA_MAC_VER_10:
3682         case RTL_GIGA_MAC_VER_16:
3683         case RTL_GIGA_MAC_VER_29:
3684         case RTL_GIGA_MAC_VER_30:
3685                 ops->down       = r810x_pll_power_down;
3686                 ops->up         = r810x_pll_power_up;
3687                 break;
3688
3689         case RTL_GIGA_MAC_VER_11:
3690         case RTL_GIGA_MAC_VER_12:
3691         case RTL_GIGA_MAC_VER_17:
3692         case RTL_GIGA_MAC_VER_18:
3693         case RTL_GIGA_MAC_VER_19:
3694         case RTL_GIGA_MAC_VER_20:
3695         case RTL_GIGA_MAC_VER_21:
3696         case RTL_GIGA_MAC_VER_22:
3697         case RTL_GIGA_MAC_VER_23:
3698         case RTL_GIGA_MAC_VER_24:
3699         case RTL_GIGA_MAC_VER_25:
3700         case RTL_GIGA_MAC_VER_26:
3701         case RTL_GIGA_MAC_VER_27:
3702         case RTL_GIGA_MAC_VER_28:
3703         case RTL_GIGA_MAC_VER_31:
3704         case RTL_GIGA_MAC_VER_32:
3705         case RTL_GIGA_MAC_VER_33:
3706         case RTL_GIGA_MAC_VER_34:
3707         case RTL_GIGA_MAC_VER_35:
3708         case RTL_GIGA_MAC_VER_36:
3709                 ops->down       = r8168_pll_power_down;
3710                 ops->up         = r8168_pll_power_up;
3711                 break;
3712
3713         default:
3714                 ops->down       = NULL;
3715                 ops->up         = NULL;
3716                 break;
3717         }
3718 }
3719
3720 static void rtl_init_rxcfg(struct rtl8169_private *tp)
3721 {
3722         void __iomem *ioaddr = tp->mmio_addr;
3723
3724         switch (tp->mac_version) {
3725         case RTL_GIGA_MAC_VER_01:
3726         case RTL_GIGA_MAC_VER_02:
3727         case RTL_GIGA_MAC_VER_03:
3728         case RTL_GIGA_MAC_VER_04:
3729         case RTL_GIGA_MAC_VER_05:
3730         case RTL_GIGA_MAC_VER_06:
3731         case RTL_GIGA_MAC_VER_10:
3732         case RTL_GIGA_MAC_VER_11:
3733         case RTL_GIGA_MAC_VER_12:
3734         case RTL_GIGA_MAC_VER_13:
3735         case RTL_GIGA_MAC_VER_14:
3736         case RTL_GIGA_MAC_VER_15:
3737         case RTL_GIGA_MAC_VER_16:
3738         case RTL_GIGA_MAC_VER_17:
3739                 RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
3740                 break;
3741         case RTL_GIGA_MAC_VER_18:
3742         case RTL_GIGA_MAC_VER_19:
3743         case RTL_GIGA_MAC_VER_20:
3744         case RTL_GIGA_MAC_VER_21:
3745         case RTL_GIGA_MAC_VER_22:
3746         case RTL_GIGA_MAC_VER_23:
3747         case RTL_GIGA_MAC_VER_24:
3748                 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
3749                 break;
3750         default:
3751                 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
3752                 break;
3753         }
3754 }
3755
3756 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
3757 {
3758         tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
3759 }
3760
3761 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
3762 {
3763         void __iomem *ioaddr = tp->mmio_addr;
3764
3765         RTL_W8(Cfg9346, Cfg9346_Unlock);
3766         rtl_generic_op(tp, tp->jumbo_ops.enable);
3767         RTL_W8(Cfg9346, Cfg9346_Lock);
3768 }
3769
3770 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
3771 {
3772         void __iomem *ioaddr = tp->mmio_addr;
3773
3774         RTL_W8(Cfg9346, Cfg9346_Unlock);
3775         rtl_generic_op(tp, tp->jumbo_ops.disable);
3776         RTL_W8(Cfg9346, Cfg9346_Lock);
3777 }
3778
3779 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
3780 {
3781         void __iomem *ioaddr = tp->mmio_addr;
3782
3783         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3784         RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
3785         rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
3786 }
3787
3788 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
3789 {
3790         void __iomem *ioaddr = tp->mmio_addr;
3791
3792         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3793         RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
3794         rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
3795 }
3796
3797 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
3798 {
3799         void __iomem *ioaddr = tp->mmio_addr;
3800
3801         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3802 }
3803
3804 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
3805 {
3806         void __iomem *ioaddr = tp->mmio_addr;
3807
3808         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3809 }
3810
3811 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
3812 {
3813         void __iomem *ioaddr = tp->mmio_addr;
3814
3815         RTL_W8(MaxTxPacketSize, 0x3f);
3816         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3817         RTL_W8(Config4, RTL_R8(Config4) | 0x01);
3818         rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
3819 }
3820
3821 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
3822 {
3823         void __iomem *ioaddr = tp->mmio_addr;
3824
3825         RTL_W8(MaxTxPacketSize, 0x0c);
3826         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3827         RTL_W8(Config4, RTL_R8(Config4) & ~0x01);
3828         rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
3829 }
3830
3831 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
3832 {
3833         rtl_tx_performance_tweak(tp->pci_dev,
3834                 (0x2 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3835 }
3836
3837 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
3838 {
3839         rtl_tx_performance_tweak(tp->pci_dev,
3840                 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3841 }
3842
3843 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
3844 {
3845         void __iomem *ioaddr = tp->mmio_addr;
3846
3847         r8168b_0_hw_jumbo_enable(tp);
3848
3849         RTL_W8(Config4, RTL_R8(Config4) | (1 << 0));
3850 }
3851
3852 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
3853 {
3854         void __iomem *ioaddr = tp->mmio_addr;
3855
3856         r8168b_0_hw_jumbo_disable(tp);
3857
3858         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
3859 }
3860
3861 static void __devinit rtl_init_jumbo_ops(struct rtl8169_private *tp)
3862 {
3863         struct jumbo_ops *ops = &tp->jumbo_ops;
3864
3865         switch (tp->mac_version) {
3866         case RTL_GIGA_MAC_VER_11:
3867                 ops->disable    = r8168b_0_hw_jumbo_disable;
3868                 ops->enable     = r8168b_0_hw_jumbo_enable;
3869                 break;
3870         case RTL_GIGA_MAC_VER_12:
3871         case RTL_GIGA_MAC_VER_17:
3872                 ops->disable    = r8168b_1_hw_jumbo_disable;
3873                 ops->enable     = r8168b_1_hw_jumbo_enable;
3874                 break;
3875         case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
3876         case RTL_GIGA_MAC_VER_19:
3877         case RTL_GIGA_MAC_VER_20:
3878         case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
3879         case RTL_GIGA_MAC_VER_22:
3880         case RTL_GIGA_MAC_VER_23:
3881         case RTL_GIGA_MAC_VER_24:
3882         case RTL_GIGA_MAC_VER_25:
3883         case RTL_GIGA_MAC_VER_26:
3884                 ops->disable    = r8168c_hw_jumbo_disable;
3885                 ops->enable     = r8168c_hw_jumbo_enable;
3886                 break;
3887         case RTL_GIGA_MAC_VER_27:
3888         case RTL_GIGA_MAC_VER_28:
3889                 ops->disable    = r8168dp_hw_jumbo_disable;
3890                 ops->enable     = r8168dp_hw_jumbo_enable;
3891                 break;
3892         case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
3893         case RTL_GIGA_MAC_VER_32:
3894         case RTL_GIGA_MAC_VER_33:
3895         case RTL_GIGA_MAC_VER_34:
3896                 ops->disable    = r8168e_hw_jumbo_disable;
3897                 ops->enable     = r8168e_hw_jumbo_enable;
3898                 break;
3899
3900         /*
3901          * No action needed for jumbo frames with 8169.
3902          * No jumbo for 810x at all.
3903          */
3904         default:
3905                 ops->disable    = NULL;
3906                 ops->enable     = NULL;
3907                 break;
3908         }
3909 }
3910
3911 static void rtl_hw_reset(struct rtl8169_private *tp)
3912 {
3913         void __iomem *ioaddr = tp->mmio_addr;
3914         int i;
3915
3916         /* Soft reset the chip. */
3917         RTL_W8(ChipCmd, CmdReset);
3918
3919         /* Check that the chip has finished the reset. */
3920         for (i = 0; i < 100; i++) {
3921                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3922                         break;
3923                 udelay(100);
3924         }
3925 }
3926
3927 static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
3928 {
3929         struct rtl_fw *rtl_fw;
3930         const char *name;
3931         int rc = -ENOMEM;
3932
3933         name = rtl_lookup_firmware_name(tp);
3934         if (!name)
3935                 goto out_no_firmware;
3936
3937         rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
3938         if (!rtl_fw)
3939                 goto err_warn;
3940
3941         rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
3942         if (rc < 0)
3943                 goto err_free;
3944
3945         rc = rtl_check_firmware(tp, rtl_fw);
3946         if (rc < 0)
3947                 goto err_release_firmware;
3948
3949         tp->rtl_fw = rtl_fw;
3950 out:
3951         return;
3952
3953 err_release_firmware:
3954         release_firmware(rtl_fw->fw);
3955 err_free:
3956         kfree(rtl_fw);
3957 err_warn:
3958         netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
3959                    name, rc);
3960 out_no_firmware:
3961         tp->rtl_fw = NULL;
3962         goto out;
3963 }
3964
3965 static void rtl_request_firmware(struct rtl8169_private *tp)
3966 {
3967         if (IS_ERR(tp->rtl_fw))
3968                 rtl_request_uncached_firmware(tp);
3969 }
3970
3971 static void rtl_rx_close(struct rtl8169_private *tp)
3972 {
3973         void __iomem *ioaddr = tp->mmio_addr;
3974
3975         RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
3976 }
3977
3978 static void rtl8169_hw_reset(struct rtl8169_private *tp)
3979 {
3980         void __iomem *ioaddr = tp->mmio_addr;
3981
3982         /* Disable interrupts */
3983         rtl8169_irq_mask_and_ack(tp);
3984
3985         rtl_rx_close(tp);
3986
3987         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3988             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3989             tp->mac_version == RTL_GIGA_MAC_VER_31) {
3990                 while (RTL_R8(TxPoll) & NPQ)
3991                         udelay(20);
3992         } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
3993                    tp->mac_version == RTL_GIGA_MAC_VER_35 ||
3994                    tp->mac_version == RTL_GIGA_MAC_VER_36) {
3995                 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
3996                 while (!(RTL_R32(TxConfig) & TXCFG_EMPTY))
3997                         udelay(100);
3998         } else {
3999                 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
4000                 udelay(100);
4001         }
4002
4003         rtl_hw_reset(tp);
4004 }
4005
4006 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
4007 {
4008         void __iomem *ioaddr = tp->mmio_addr;
4009
4010         /* Set DMA burst size and Interframe Gap Time */
4011         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4012                 (InterFrameGap << TxInterFrameGapShift));
4013 }
4014
4015 static void rtl_hw_start(struct net_device *dev)
4016 {
4017         struct rtl8169_private *tp = netdev_priv(dev);
4018
4019         tp->hw_start(dev);
4020
4021         rtl_irq_enable_all(tp);
4022 }
4023
4024 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
4025                                          void __iomem *ioaddr)
4026 {
4027         /*
4028          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4029          * register to be written before TxDescAddrLow to work.
4030          * Switching from MMIO to I/O access fixes the issue as well.
4031          */
4032         RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4033         RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4034         RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4035         RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
4036 }
4037
4038 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
4039 {
4040         u16 cmd;
4041
4042         cmd = RTL_R16(CPlusCmd);
4043         RTL_W16(CPlusCmd, cmd);
4044         return cmd;
4045 }
4046
4047 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
4048 {
4049         /* Low hurts. Let's disable the filtering. */
4050         RTL_W16(RxMaxSize, rx_buf_sz + 1);
4051 }
4052
4053 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
4054 {
4055         static const struct rtl_cfg2_info {
4056                 u32 mac_version;
4057                 u32 clk;
4058                 u32 val;
4059         } cfg2_info [] = {
4060                 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
4061                 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
4062                 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
4063                 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
4064         };
4065         const struct rtl_cfg2_info *p = cfg2_info;
4066         unsigned int i;
4067         u32 clk;
4068
4069         clk = RTL_R8(Config2) & PCI_Clock_66MHz;
4070         for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
4071                 if ((p->mac_version == mac_version) && (p->clk == clk)) {
4072                         RTL_W32(0x7c, p->val);
4073                         break;
4074                 }
4075         }
4076 }
4077
4078 static void rtl_set_rx_mode(struct net_device *dev)
4079 {
4080         struct rtl8169_private *tp = netdev_priv(dev);
4081         void __iomem *ioaddr = tp->mmio_addr;
4082         u32 mc_filter[2];       /* Multicast hash filter */
4083         int rx_mode;
4084         u32 tmp = 0;
4085
4086         if (dev->flags & IFF_PROMISC) {
4087                 /* Unconditionally log net taps. */
4088                 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4089                 rx_mode =
4090                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4091                     AcceptAllPhys;
4092                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4093         } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4094                    (dev->flags & IFF_ALLMULTI)) {
4095                 /* Too many to filter perfectly -- accept all multicasts. */
4096                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4097                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4098         } else {
4099                 struct netdev_hw_addr *ha;
4100
4101                 rx_mode = AcceptBroadcast | AcceptMyPhys;
4102                 mc_filter[1] = mc_filter[0] = 0;
4103                 netdev_for_each_mc_addr(ha, dev) {
4104                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4105                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4106                         rx_mode |= AcceptMulticast;
4107                 }
4108         }
4109
4110         if (dev->features & NETIF_F_RXALL)
4111                 rx_mode |= (AcceptErr | AcceptRunt);
4112
4113         tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
4114
4115         if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4116                 u32 data = mc_filter[0];
4117
4118                 mc_filter[0] = swab32(mc_filter[1]);
4119                 mc_filter[1] = swab32(data);
4120         }
4121
4122         RTL_W32(MAR0 + 4, mc_filter[1]);
4123         RTL_W32(MAR0 + 0, mc_filter[0]);
4124
4125         RTL_W32(RxConfig, tmp);
4126 }
4127
4128 static void rtl_hw_start_8169(struct net_device *dev)
4129 {
4130         struct rtl8169_private *tp = netdev_priv(dev);
4131         void __iomem *ioaddr = tp->mmio_addr;
4132         struct pci_dev *pdev = tp->pci_dev;
4133
4134         if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
4135                 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
4136                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
4137         }
4138
4139         RTL_W8(Cfg9346, Cfg9346_Unlock);
4140         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4141             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4142             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4143             tp->mac_version == RTL_GIGA_MAC_VER_04)
4144                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4145
4146         rtl_init_rxcfg(tp);
4147
4148         RTL_W8(EarlyTxThres, NoEarlyTx);
4149
4150         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4151
4152         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4153             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4154             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4155             tp->mac_version == RTL_GIGA_MAC_VER_04)
4156                 rtl_set_rx_tx_config_registers(tp);
4157
4158         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
4159
4160         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4161             tp->mac_version == RTL_GIGA_MAC_VER_03) {
4162                 dprintk("Set MAC Reg C+CR Offset 0xE0. "
4163                         "Bit-3 and bit-14 MUST be 1\n");
4164                 tp->cp_cmd |= (1 << 14);
4165         }
4166
4167         RTL_W16(CPlusCmd, tp->cp_cmd);
4168
4169         rtl8169_set_magic_reg(ioaddr, tp->mac_version);
4170
4171         /*
4172          * Undocumented corner. Supposedly:
4173          * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4174          */
4175         RTL_W16(IntrMitigate, 0x0000);
4176
4177         rtl_set_rx_tx_desc_registers(tp, ioaddr);
4178
4179         if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
4180             tp->mac_version != RTL_GIGA_MAC_VER_02 &&
4181             tp->mac_version != RTL_GIGA_MAC_VER_03 &&
4182             tp->mac_version != RTL_GIGA_MAC_VER_04) {
4183                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4184                 rtl_set_rx_tx_config_registers(tp);
4185         }
4186
4187         RTL_W8(Cfg9346, Cfg9346_Lock);
4188
4189         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4190         RTL_R8(IntrMask);
4191
4192         RTL_W32(RxMissed, 0);
4193
4194         rtl_set_rx_mode(dev);
4195
4196         /* no early-rx interrupts */
4197         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
4198 }
4199
4200 static void rtl_csi_access_enable(void __iomem *ioaddr, u32 bits)
4201 {
4202         u32 csi;
4203
4204         csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
4205         rtl_csi_write(ioaddr, 0x070c, csi | bits);
4206 }
4207
4208 static void rtl_csi_access_enable_1(void __iomem *ioaddr)
4209 {
4210         rtl_csi_access_enable(ioaddr, 0x17000000);
4211 }
4212
4213 static void rtl_csi_access_enable_2(void __iomem *ioaddr)
4214 {
4215         rtl_csi_access_enable(ioaddr, 0x27000000);
4216 }
4217
4218 struct ephy_info {
4219         unsigned int offset;
4220         u16 mask;
4221         u16 bits;
4222 };
4223
4224 static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
4225 {
4226         u16 w;
4227
4228         while (len-- > 0) {
4229                 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
4230                 rtl_ephy_write(ioaddr, e->offset, w);
4231                 e++;
4232         }
4233 }
4234
4235 static void rtl_disable_clock_request(struct pci_dev *pdev)
4236 {
4237         int cap = pci_pcie_cap(pdev);
4238
4239         if (cap) {
4240                 u16 ctl;
4241
4242                 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
4243                 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
4244                 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
4245         }
4246 }
4247
4248 static void rtl_enable_clock_request(struct pci_dev *pdev)
4249 {
4250         int cap = pci_pcie_cap(pdev);
4251
4252         if (cap) {
4253                 u16 ctl;
4254
4255                 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
4256                 ctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
4257                 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
4258         }
4259 }
4260
4261 #define R8168_CPCMD_QUIRK_MASK (\
4262         EnableBist | \
4263         Mac_dbgo_oe | \
4264         Force_half_dup | \
4265         Force_rxflow_en | \
4266         Force_txflow_en | \
4267         Cxpl_dbg_sel | \
4268         ASF | \
4269         PktCntrDisable | \
4270         Mac_dbgo_sel)
4271
4272 static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
4273 {
4274         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4275
4276         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4277
4278         rtl_tx_performance_tweak(pdev,
4279                 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4280 }
4281
4282 static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
4283 {
4284         rtl_hw_start_8168bb(ioaddr, pdev);
4285
4286         RTL_W8(MaxTxPacketSize, TxPacketMax);
4287
4288         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
4289 }
4290
4291 static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
4292 {
4293         RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
4294
4295         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4296
4297         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4298
4299         rtl_disable_clock_request(pdev);
4300
4301         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4302 }
4303
4304 static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
4305 {
4306         static const struct ephy_info e_info_8168cp[] = {
4307                 { 0x01, 0,      0x0001 },
4308                 { 0x02, 0x0800, 0x1000 },
4309                 { 0x03, 0,      0x0042 },
4310                 { 0x06, 0x0080, 0x0000 },
4311                 { 0x07, 0,      0x2000 }
4312         };
4313
4314         rtl_csi_access_enable_2(ioaddr);
4315
4316         rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
4317
4318         __rtl_hw_start_8168cp(ioaddr, pdev);
4319 }
4320
4321 static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
4322 {
4323         rtl_csi_access_enable_2(ioaddr);
4324
4325         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4326
4327         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4328
4329         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4330 }
4331
4332 static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
4333 {
4334         rtl_csi_access_enable_2(ioaddr);
4335
4336         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4337
4338         /* Magic. */
4339         RTL_W8(DBG_REG, 0x20);
4340
4341         RTL_W8(MaxTxPacketSize, TxPacketMax);
4342
4343         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4344
4345         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4346 }
4347
4348 static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
4349 {
4350         static const struct ephy_info e_info_8168c_1[] = {
4351                 { 0x02, 0x0800, 0x1000 },
4352                 { 0x03, 0,      0x0002 },
4353                 { 0x06, 0x0080, 0x0000 }
4354         };
4355
4356         rtl_csi_access_enable_2(ioaddr);
4357
4358         RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4359
4360         rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
4361
4362         __rtl_hw_start_8168cp(ioaddr, pdev);
4363 }
4364
4365 static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
4366 {
4367         static const struct ephy_info e_info_8168c_2[] = {
4368                 { 0x01, 0,      0x0001 },
4369                 { 0x03, 0x0400, 0x0220 }
4370         };
4371
4372         rtl_csi_access_enable_2(ioaddr);
4373
4374         rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
4375
4376         __rtl_hw_start_8168cp(ioaddr, pdev);
4377 }
4378
4379 static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
4380 {
4381         rtl_hw_start_8168c_2(ioaddr, pdev);
4382 }
4383
4384 static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
4385 {
4386         rtl_csi_access_enable_2(ioaddr);
4387
4388         __rtl_hw_start_8168cp(ioaddr, pdev);
4389 }
4390
4391 static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
4392 {
4393         rtl_csi_access_enable_2(ioaddr);
4394
4395         rtl_disable_clock_request(pdev);
4396
4397         RTL_W8(MaxTxPacketSize, TxPacketMax);
4398
4399         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4400
4401         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4402 }
4403
4404 static void rtl_hw_start_8168dp(void __iomem *ioaddr, struct pci_dev *pdev)
4405 {
4406         rtl_csi_access_enable_1(ioaddr);
4407
4408         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4409
4410         RTL_W8(MaxTxPacketSize, TxPacketMax);
4411
4412         rtl_disable_clock_request(pdev);
4413 }
4414
4415 static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev)
4416 {
4417         static const struct ephy_info e_info_8168d_4[] = {
4418                 { 0x0b, ~0,     0x48 },
4419                 { 0x19, 0x20,   0x50 },
4420                 { 0x0c, ~0,     0x20 }
4421         };
4422         int i;
4423
4424         rtl_csi_access_enable_1(ioaddr);
4425
4426         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4427
4428         RTL_W8(MaxTxPacketSize, TxPacketMax);
4429
4430         for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
4431                 const struct ephy_info *e = e_info_8168d_4 + i;
4432                 u16 w;
4433
4434                 w = rtl_ephy_read(ioaddr, e->offset);
4435                 rtl_ephy_write(ioaddr, 0x03, (w & e->mask) | e->bits);
4436         }
4437
4438         rtl_enable_clock_request(pdev);
4439 }
4440
4441 static void rtl_hw_start_8168e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4442 {
4443         static const struct ephy_info e_info_8168e_1[] = {
4444                 { 0x00, 0x0200, 0x0100 },
4445                 { 0x00, 0x0000, 0x0004 },
4446                 { 0x06, 0x0002, 0x0001 },
4447                 { 0x06, 0x0000, 0x0030 },
4448                 { 0x07, 0x0000, 0x2000 },
4449                 { 0x00, 0x0000, 0x0020 },
4450                 { 0x03, 0x5800, 0x2000 },
4451                 { 0x03, 0x0000, 0x0001 },
4452                 { 0x01, 0x0800, 0x1000 },
4453                 { 0x07, 0x0000, 0x4000 },
4454                 { 0x1e, 0x0000, 0x2000 },
4455                 { 0x19, 0xffff, 0xfe6c },
4456                 { 0x0a, 0x0000, 0x0040 }
4457         };
4458
4459         rtl_csi_access_enable_2(ioaddr);
4460
4461         rtl_ephy_init(ioaddr, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
4462
4463         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4464
4465         RTL_W8(MaxTxPacketSize, TxPacketMax);
4466
4467         rtl_disable_clock_request(pdev);
4468
4469         /* Reset tx FIFO pointer */
4470         RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
4471         RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
4472
4473         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4474 }
4475
4476 static void rtl_hw_start_8168e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4477 {
4478         static const struct ephy_info e_info_8168e_2[] = {
4479                 { 0x09, 0x0000, 0x0080 },
4480                 { 0x19, 0x0000, 0x0224 }
4481         };
4482
4483         rtl_csi_access_enable_1(ioaddr);
4484
4485         rtl_ephy_init(ioaddr, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
4486
4487         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4488
4489         rtl_eri_write(ioaddr, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4490         rtl_eri_write(ioaddr, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4491         rtl_eri_write(ioaddr, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
4492         rtl_eri_write(ioaddr, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
4493         rtl_eri_write(ioaddr, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
4494         rtl_eri_write(ioaddr, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
4495         rtl_w1w0_eri(ioaddr, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4496         rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00,
4497                      ERIAR_EXGMAC);
4498
4499         RTL_W8(MaxTxPacketSize, EarlySize);
4500
4501         rtl_disable_clock_request(pdev);
4502
4503         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
4504         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
4505
4506         /* Adjust EEE LED frequency */
4507         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
4508
4509         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4510         RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
4511         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4512 }
4513
4514 static void rtl_hw_start_8168f_1(void __iomem *ioaddr, struct pci_dev *pdev)
4515 {
4516         static const struct ephy_info e_info_8168f_1[] = {
4517                 { 0x06, 0x00c0, 0x0020 },
4518                 { 0x08, 0x0001, 0x0002 },
4519                 { 0x09, 0x0000, 0x0080 },
4520                 { 0x19, 0x0000, 0x0224 }
4521         };
4522
4523         rtl_csi_access_enable_1(ioaddr);
4524
4525         rtl_ephy_init(ioaddr, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
4526
4527         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4528
4529         rtl_eri_write(ioaddr, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4530         rtl_eri_write(ioaddr, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4531         rtl_eri_write(ioaddr, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
4532         rtl_eri_write(ioaddr, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
4533         rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
4534         rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
4535         rtl_w1w0_eri(ioaddr, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4536         rtl_w1w0_eri(ioaddr, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4537         rtl_eri_write(ioaddr, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
4538         rtl_eri_write(ioaddr, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
4539         rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00,
4540                      ERIAR_EXGMAC);
4541
4542         RTL_W8(MaxTxPacketSize, EarlySize);
4543
4544         rtl_disable_clock_request(pdev);
4545
4546         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
4547         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
4548
4549         /* Adjust EEE LED frequency */
4550         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
4551
4552         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4553         RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
4554         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4555 }
4556
4557 static void rtl_hw_start_8168(struct net_device *dev)
4558 {
4559         struct rtl8169_private *tp = netdev_priv(dev);
4560         void __iomem *ioaddr = tp->mmio_addr;
4561         struct pci_dev *pdev = tp->pci_dev;
4562
4563         RTL_W8(Cfg9346, Cfg9346_Unlock);
4564
4565         RTL_W8(MaxTxPacketSize, TxPacketMax);
4566
4567         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4568
4569         tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
4570
4571         RTL_W16(CPlusCmd, tp->cp_cmd);
4572
4573         RTL_W16(IntrMitigate, 0x5151);
4574
4575         /* Work around for RxFIFO overflow. */
4576         if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
4577                 tp->event_slow |= RxFIFOOver | PCSTimeout;
4578                 tp->event_slow &= ~RxOverflow;
4579         }
4580
4581         rtl_set_rx_tx_desc_registers(tp, ioaddr);
4582
4583         rtl_set_rx_mode(dev);
4584
4585         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4586                 (InterFrameGap << TxInterFrameGapShift));
4587
4588         RTL_R8(IntrMask);
4589
4590         switch (tp->mac_version) {
4591         case RTL_GIGA_MAC_VER_11:
4592                 rtl_hw_start_8168bb(ioaddr, pdev);
4593                 break;
4594
4595         case RTL_GIGA_MAC_VER_12:
4596         case RTL_GIGA_MAC_VER_17:
4597                 rtl_hw_start_8168bef(ioaddr, pdev);
4598                 break;
4599
4600         case RTL_GIGA_MAC_VER_18:
4601                 rtl_hw_start_8168cp_1(ioaddr, pdev);
4602                 break;
4603
4604         case RTL_GIGA_MAC_VER_19:
4605                 rtl_hw_start_8168c_1(ioaddr, pdev);
4606                 break;
4607
4608         case RTL_GIGA_MAC_VER_20:
4609                 rtl_hw_start_8168c_2(ioaddr, pdev);
4610                 break;
4611
4612         case RTL_GIGA_MAC_VER_21:
4613                 rtl_hw_start_8168c_3(ioaddr, pdev);
4614                 break;
4615
4616         case RTL_GIGA_MAC_VER_22:
4617                 rtl_hw_start_8168c_4(ioaddr, pdev);
4618                 break;
4619
4620         case RTL_GIGA_MAC_VER_23:
4621                 rtl_hw_start_8168cp_2(ioaddr, pdev);
4622                 break;
4623
4624         case RTL_GIGA_MAC_VER_24:
4625                 rtl_hw_start_8168cp_3(ioaddr, pdev);
4626                 break;
4627
4628         case RTL_GIGA_MAC_VER_25:
4629         case RTL_GIGA_MAC_VER_26:
4630         case RTL_GIGA_MAC_VER_27:
4631                 rtl_hw_start_8168d(ioaddr, pdev);
4632                 break;
4633
4634         case RTL_GIGA_MAC_VER_28:
4635                 rtl_hw_start_8168d_4(ioaddr, pdev);
4636                 break;
4637
4638         case RTL_GIGA_MAC_VER_31:
4639                 rtl_hw_start_8168dp(ioaddr, pdev);
4640                 break;
4641
4642         case RTL_GIGA_MAC_VER_32:
4643         case RTL_GIGA_MAC_VER_33:
4644                 rtl_hw_start_8168e_1(ioaddr, pdev);
4645                 break;
4646         case RTL_GIGA_MAC_VER_34:
4647                 rtl_hw_start_8168e_2(ioaddr, pdev);
4648                 break;
4649
4650         case RTL_GIGA_MAC_VER_35:
4651         case RTL_GIGA_MAC_VER_36:
4652                 rtl_hw_start_8168f_1(ioaddr, pdev);
4653                 break;
4654
4655         default:
4656                 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
4657                         dev->name, tp->mac_version);
4658                 break;
4659         }
4660
4661         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4662
4663         RTL_W8(Cfg9346, Cfg9346_Lock);
4664
4665         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
4666 }
4667
4668 #define R810X_CPCMD_QUIRK_MASK (\
4669         EnableBist | \
4670         Mac_dbgo_oe | \
4671         Force_half_dup | \
4672         Force_rxflow_en | \
4673         Force_txflow_en | \
4674         Cxpl_dbg_sel | \
4675         ASF | \
4676         PktCntrDisable | \
4677         Mac_dbgo_sel)
4678
4679 static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4680 {
4681         static const struct ephy_info e_info_8102e_1[] = {
4682                 { 0x01, 0, 0x6e65 },
4683                 { 0x02, 0, 0x091f },
4684                 { 0x03, 0, 0xc2f9 },
4685                 { 0x06, 0, 0xafb5 },
4686                 { 0x07, 0, 0x0e00 },
4687                 { 0x19, 0, 0xec80 },
4688                 { 0x01, 0, 0x2e65 },
4689                 { 0x01, 0, 0x6e65 }
4690         };
4691         u8 cfg1;
4692
4693         rtl_csi_access_enable_2(ioaddr);
4694
4695         RTL_W8(DBG_REG, FIX_NAK_1);
4696
4697         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4698
4699         RTL_W8(Config1,
4700                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
4701         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4702
4703         cfg1 = RTL_R8(Config1);
4704         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
4705                 RTL_W8(Config1, cfg1 & ~LEDS0);
4706
4707         rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
4708 }
4709
4710 static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4711 {
4712         rtl_csi_access_enable_2(ioaddr);
4713
4714         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4715
4716         RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
4717         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4718 }
4719
4720 static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
4721 {
4722         rtl_hw_start_8102e_2(ioaddr, pdev);
4723
4724         rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
4725 }
4726
4727 static void rtl_hw_start_8105e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4728 {
4729         static const struct ephy_info e_info_8105e_1[] = {
4730                 { 0x07, 0, 0x4000 },
4731                 { 0x19, 0, 0x0200 },
4732                 { 0x19, 0, 0x0020 },
4733                 { 0x1e, 0, 0x2000 },
4734                 { 0x03, 0, 0x0001 },
4735                 { 0x19, 0, 0x0100 },
4736                 { 0x19, 0, 0x0004 },
4737                 { 0x0a, 0, 0x0020 }
4738         };
4739
4740         /* Force LAN exit from ASPM if Rx/Tx are not idle */
4741         RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
4742
4743         /* Disable Early Tally Counter */
4744         RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
4745
4746         RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
4747         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4748
4749         rtl_ephy_init(ioaddr, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
4750 }
4751
4752 static void rtl_hw_start_8105e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4753 {
4754         rtl_hw_start_8105e_1(ioaddr, pdev);
4755         rtl_ephy_write(ioaddr, 0x1e, rtl_ephy_read(ioaddr, 0x1e) | 0x8000);
4756 }
4757
4758 static void rtl_hw_start_8101(struct net_device *dev)
4759 {
4760         struct rtl8169_private *tp = netdev_priv(dev);
4761         void __iomem *ioaddr = tp->mmio_addr;
4762         struct pci_dev *pdev = tp->pci_dev;
4763
4764         if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
4765                 tp->event_slow &= ~RxFIFOOver;
4766
4767         if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
4768             tp->mac_version == RTL_GIGA_MAC_VER_16) {
4769                 int cap = pci_pcie_cap(pdev);
4770
4771                 if (cap) {
4772                         pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
4773                                               PCI_EXP_DEVCTL_NOSNOOP_EN);
4774                 }
4775         }
4776
4777         RTL_W8(Cfg9346, Cfg9346_Unlock);
4778
4779         switch (tp->mac_version) {
4780         case RTL_GIGA_MAC_VER_07:
4781                 rtl_hw_start_8102e_1(ioaddr, pdev);
4782                 break;
4783
4784         case RTL_GIGA_MAC_VER_08:
4785                 rtl_hw_start_8102e_3(ioaddr, pdev);
4786                 break;
4787
4788         case RTL_GIGA_MAC_VER_09:
4789                 rtl_hw_start_8102e_2(ioaddr, pdev);
4790                 break;
4791
4792         case RTL_GIGA_MAC_VER_29:
4793                 rtl_hw_start_8105e_1(ioaddr, pdev);
4794                 break;
4795         case RTL_GIGA_MAC_VER_30:
4796                 rtl_hw_start_8105e_2(ioaddr, pdev);
4797                 break;
4798         }
4799
4800         RTL_W8(Cfg9346, Cfg9346_Lock);
4801
4802         RTL_W8(MaxTxPacketSize, TxPacketMax);
4803
4804         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4805
4806         tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
4807         RTL_W16(CPlusCmd, tp->cp_cmd);
4808
4809         RTL_W16(IntrMitigate, 0x0000);
4810
4811         rtl_set_rx_tx_desc_registers(tp, ioaddr);
4812
4813         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4814         rtl_set_rx_tx_config_registers(tp);
4815
4816         RTL_R8(IntrMask);
4817
4818         rtl_set_rx_mode(dev);
4819
4820         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
4821 }
4822
4823 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
4824 {
4825         struct rtl8169_private *tp = netdev_priv(dev);
4826
4827         if (new_mtu < ETH_ZLEN ||
4828             new_mtu > rtl_chip_infos[tp->mac_version].jumbo_max)
4829                 return -EINVAL;
4830
4831         if (new_mtu > ETH_DATA_LEN)
4832                 rtl_hw_jumbo_enable(tp);
4833         else
4834                 rtl_hw_jumbo_disable(tp);
4835
4836         dev->mtu = new_mtu;
4837         netdev_update_features(dev);
4838
4839         return 0;
4840 }
4841
4842 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
4843 {
4844         desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
4845         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
4846 }
4847
4848 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
4849                                      void **data_buff, struct RxDesc *desc)
4850 {
4851         dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
4852                          DMA_FROM_DEVICE);
4853
4854         kfree(*data_buff);
4855         *data_buff = NULL;
4856         rtl8169_make_unusable_by_asic(desc);
4857 }
4858
4859 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
4860 {
4861         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
4862
4863         desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
4864 }
4865
4866 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
4867                                        u32 rx_buf_sz)
4868 {
4869         desc->addr = cpu_to_le64(mapping);
4870         wmb();
4871         rtl8169_mark_to_asic(desc, rx_buf_sz);
4872 }
4873
4874 static inline void *rtl8169_align(void *data)
4875 {
4876         return (void *)ALIGN((long)data, 16);
4877 }
4878
4879 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
4880                                              struct RxDesc *desc)
4881 {
4882         void *data;
4883         dma_addr_t mapping;
4884         struct device *d = &tp->pci_dev->dev;
4885         struct net_device *dev = tp->dev;
4886         int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
4887
4888         data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
4889         if (!data)
4890                 return NULL;
4891
4892         if (rtl8169_align(data) != data) {
4893                 kfree(data);
4894                 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
4895                 if (!data)
4896                         return NULL;
4897         }
4898
4899         mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
4900                                  DMA_FROM_DEVICE);
4901         if (unlikely(dma_mapping_error(d, mapping))) {
4902                 if (net_ratelimit())
4903                         netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
4904                 goto err_out;
4905         }
4906
4907         rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
4908         return data;
4909
4910 err_out:
4911         kfree(data);
4912         return NULL;
4913 }
4914
4915 static void rtl8169_rx_clear(struct rtl8169_private *tp)
4916 {
4917         unsigned int i;
4918
4919         for (i = 0; i < NUM_RX_DESC; i++) {
4920                 if (tp->Rx_databuff[i]) {
4921                         rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
4922                                             tp->RxDescArray + i);
4923                 }
4924         }
4925 }
4926
4927 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
4928 {
4929         desc->opts1 |= cpu_to_le32(RingEnd);
4930 }
4931
4932 static int rtl8169_rx_fill(struct rtl8169_private *tp)
4933 {
4934         unsigned int i;
4935
4936         for (i = 0; i < NUM_RX_DESC; i++) {
4937                 void *data;
4938
4939                 if (tp->Rx_databuff[i])
4940                         continue;
4941
4942                 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
4943                 if (!data) {
4944                         rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
4945                         goto err_out;
4946                 }
4947                 tp->Rx_databuff[i] = data;
4948         }
4949
4950         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
4951         return 0;
4952
4953 err_out:
4954         rtl8169_rx_clear(tp);
4955         return -ENOMEM;
4956 }
4957
4958 static int rtl8169_init_ring(struct net_device *dev)
4959 {
4960         struct rtl8169_private *tp = netdev_priv(dev);
4961
4962         rtl8169_init_ring_indexes(tp);
4963
4964         memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
4965         memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
4966
4967         return rtl8169_rx_fill(tp);
4968 }
4969
4970 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
4971                                  struct TxDesc *desc)
4972 {
4973         unsigned int len = tx_skb->len;
4974
4975         dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
4976
4977         desc->opts1 = 0x00;
4978         desc->opts2 = 0x00;
4979         desc->addr = 0x00;
4980         tx_skb->len = 0;
4981 }
4982
4983 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
4984                                    unsigned int n)
4985 {
4986         unsigned int i;
4987
4988         for (i = 0; i < n; i++) {
4989                 unsigned int entry = (start + i) % NUM_TX_DESC;
4990                 struct ring_info *tx_skb = tp->tx_skb + entry;
4991                 unsigned int len = tx_skb->len;
4992
4993                 if (len) {
4994                         struct sk_buff *skb = tx_skb->skb;
4995
4996                         rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
4997                                              tp->TxDescArray + entry);
4998                         if (skb) {
4999                                 tp->dev->stats.tx_dropped++;
5000                                 dev_kfree_skb(skb);
5001                                 tx_skb->skb = NULL;
5002                         }
5003                 }
5004         }
5005 }
5006
5007 static void rtl8169_tx_clear(struct rtl8169_private *tp)
5008 {
5009         rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
5010         tp->cur_tx = tp->dirty_tx = 0;
5011         netdev_reset_queue(tp->dev);
5012 }
5013
5014 static void rtl_reset_work(struct rtl8169_private *tp)
5015 {
5016         struct net_device *dev = tp->dev;
5017         int i;
5018
5019         napi_disable(&tp->napi);
5020         netif_stop_queue(dev);
5021         synchronize_sched();
5022
5023         rtl8169_hw_reset(tp);
5024
5025         for (i = 0; i < NUM_RX_DESC; i++)
5026                 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
5027
5028         rtl8169_tx_clear(tp);
5029         rtl8169_init_ring_indexes(tp);
5030
5031         napi_enable(&tp->napi);
5032         rtl_hw_start(dev);
5033         netif_wake_queue(dev);
5034         rtl8169_check_link_status(dev, tp, tp->mmio_addr);
5035 }
5036
5037 static void rtl8169_tx_timeout(struct net_device *dev)
5038 {
5039         struct rtl8169_private *tp = netdev_priv(dev);
5040
5041         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5042 }
5043
5044 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
5045                               u32 *opts)
5046 {
5047         struct skb_shared_info *info = skb_shinfo(skb);
5048         unsigned int cur_frag, entry;
5049         struct TxDesc * uninitialized_var(txd);
5050         struct device *d = &tp->pci_dev->dev;
5051
5052         entry = tp->cur_tx;
5053         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
5054                 const skb_frag_t *frag = info->frags + cur_frag;
5055                 dma_addr_t mapping;
5056                 u32 status, len;
5057                 void *addr;
5058
5059                 entry = (entry + 1) % NUM_TX_DESC;
5060
5061                 txd = tp->TxDescArray + entry;
5062                 len = skb_frag_size(frag);
5063                 addr = skb_frag_address(frag);
5064                 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
5065                 if (unlikely(dma_mapping_error(d, mapping))) {
5066                         if (net_ratelimit())
5067                                 netif_err(tp, drv, tp->dev,
5068                                           "Failed to map TX fragments DMA!\n");
5069                         goto err_out;
5070                 }
5071
5072                 /* Anti gcc 2.95.3 bugware (sic) */
5073                 status = opts[0] | len |
5074                         (RingEnd * !((entry + 1) % NUM_TX_DESC));
5075
5076                 txd->opts1 = cpu_to_le32(status);
5077                 txd->opts2 = cpu_to_le32(opts[1]);
5078                 txd->addr = cpu_to_le64(mapping);
5079
5080                 tp->tx_skb[entry].len = len;
5081         }
5082
5083         if (cur_frag) {
5084                 tp->tx_skb[entry].skb = skb;
5085                 txd->opts1 |= cpu_to_le32(LastFrag);
5086         }
5087
5088         return cur_frag;
5089
5090 err_out:
5091         rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5092         return -EIO;
5093 }
5094
5095 static inline void rtl8169_tso_csum(struct rtl8169_private *tp,
5096                                     struct sk_buff *skb, u32 *opts)
5097 {
5098         const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version;
5099         u32 mss = skb_shinfo(skb)->gso_size;
5100         int offset = info->opts_offset;
5101
5102         if (mss) {
5103                 opts[0] |= TD_LSO;
5104                 opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift;
5105         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5106                 const struct iphdr *ip = ip_hdr(skb);
5107
5108                 if (ip->protocol == IPPROTO_TCP)
5109                         opts[offset] |= info->checksum.tcp;
5110                 else if (ip->protocol == IPPROTO_UDP)
5111                         opts[offset] |= info->checksum.udp;
5112                 else
5113                         WARN_ON_ONCE(1);
5114         }
5115 }
5116
5117 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5118                                       struct net_device *dev)
5119 {
5120         struct rtl8169_private *tp = netdev_priv(dev);
5121         unsigned int entry = tp->cur_tx % NUM_TX_DESC;
5122         struct TxDesc *txd = tp->TxDescArray + entry;
5123         void __iomem *ioaddr = tp->mmio_addr;
5124         struct device *d = &tp->pci_dev->dev;
5125         dma_addr_t mapping;
5126         u32 status, len;
5127         u32 opts[2];
5128         int frags;
5129
5130         if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
5131                 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
5132                 goto err_stop_0;
5133         }
5134
5135         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
5136                 goto err_stop_0;
5137
5138         len = skb_headlen(skb);
5139         mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
5140         if (unlikely(dma_mapping_error(d, mapping))) {
5141                 if (net_ratelimit())
5142                         netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
5143                 goto err_dma_0;
5144         }
5145
5146         tp->tx_skb[entry].len = len;
5147         txd->addr = cpu_to_le64(mapping);
5148
5149         opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
5150         opts[0] = DescOwn;
5151
5152         rtl8169_tso_csum(tp, skb, opts);
5153
5154         frags = rtl8169_xmit_frags(tp, skb, opts);
5155         if (frags < 0)
5156                 goto err_dma_1;
5157         else if (frags)
5158                 opts[0] |= FirstFrag;
5159         else {
5160                 opts[0] |= FirstFrag | LastFrag;
5161                 tp->tx_skb[entry].skb = skb;
5162         }
5163
5164         txd->opts2 = cpu_to_le32(opts[1]);
5165
5166         netdev_sent_queue(dev, skb->len);
5167
5168         skb_tx_timestamp(skb);
5169
5170         wmb();
5171
5172         /* Anti gcc 2.95.3 bugware (sic) */
5173         status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
5174         txd->opts1 = cpu_to_le32(status);
5175
5176         tp->cur_tx += frags + 1;
5177
5178         wmb();
5179
5180         RTL_W8(TxPoll, NPQ);
5181
5182         mmiowb();
5183
5184         if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
5185                 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
5186                  * not miss a ring update when it notices a stopped queue.
5187                  */
5188                 smp_wmb();
5189                 netif_stop_queue(dev);
5190                 /* Sync with rtl_tx:
5191                  * - publish queue status and cur_tx ring index (write barrier)
5192                  * - refresh dirty_tx ring index (read barrier).
5193                  * May the current thread have a pessimistic view of the ring
5194                  * status and forget to wake up queue, a racing rtl_tx thread
5195                  * can't.
5196                  */
5197                 smp_mb();
5198                 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
5199                         netif_wake_queue(dev);
5200         }
5201
5202         return NETDEV_TX_OK;
5203
5204 err_dma_1:
5205         rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
5206 err_dma_0:
5207         dev_kfree_skb(skb);
5208         dev->stats.tx_dropped++;
5209         return NETDEV_TX_OK;
5210
5211 err_stop_0:
5212         netif_stop_queue(dev);
5213         dev->stats.tx_dropped++;
5214         return NETDEV_TX_BUSY;
5215 }
5216
5217 static void rtl8169_pcierr_interrupt(struct net_device *dev)
5218 {
5219         struct rtl8169_private *tp = netdev_priv(dev);
5220         struct pci_dev *pdev = tp->pci_dev;
5221         u16 pci_status, pci_cmd;
5222
5223         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
5224         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
5225
5226         netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
5227                   pci_cmd, pci_status);
5228
5229         /*
5230          * The recovery sequence below admits a very elaborated explanation:
5231          * - it seems to work;
5232          * - I did not see what else could be done;
5233          * - it makes iop3xx happy.
5234          *
5235          * Feel free to adjust to your needs.
5236          */
5237         if (pdev->broken_parity_status)
5238                 pci_cmd &= ~PCI_COMMAND_PARITY;
5239         else
5240                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
5241
5242         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
5243
5244         pci_write_config_word(pdev, PCI_STATUS,
5245                 pci_status & (PCI_STATUS_DETECTED_PARITY |
5246                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
5247                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
5248
5249         /* The infamous DAC f*ckup only happens at boot time */
5250         if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
5251                 void __iomem *ioaddr = tp->mmio_addr;
5252
5253                 netif_info(tp, intr, dev, "disabling PCI DAC\n");
5254                 tp->cp_cmd &= ~PCIDAC;
5255                 RTL_W16(CPlusCmd, tp->cp_cmd);
5256                 dev->features &= ~NETIF_F_HIGHDMA;
5257         }
5258
5259         rtl8169_hw_reset(tp);
5260
5261         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5262 }
5263
5264 struct rtl_txc {
5265         int packets;
5266         int bytes;
5267 };
5268
5269 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
5270 {
5271         struct rtl8169_stats *tx_stats = &tp->tx_stats;
5272         unsigned int dirty_tx, tx_left;
5273         struct rtl_txc txc = { 0, 0 };
5274
5275         dirty_tx = tp->dirty_tx;
5276         smp_rmb();
5277         tx_left = tp->cur_tx - dirty_tx;
5278
5279         while (tx_left > 0) {
5280                 unsigned int entry = dirty_tx % NUM_TX_DESC;
5281                 struct ring_info *tx_skb = tp->tx_skb + entry;
5282                 u32 status;
5283
5284                 rmb();
5285                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
5286                 if (status & DescOwn)
5287                         break;
5288
5289                 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
5290                                      tp->TxDescArray + entry);
5291                 if (status & LastFrag) {
5292                         struct sk_buff *skb = tx_skb->skb;
5293
5294                         txc.packets++;
5295                         txc.bytes += skb->len;
5296                         dev_kfree_skb(skb);
5297                         tx_skb->skb = NULL;
5298                 }
5299                 dirty_tx++;
5300                 tx_left--;
5301         }
5302
5303         u64_stats_update_begin(&tx_stats->syncp);
5304         tx_stats->packets += txc.packets;
5305         tx_stats->bytes += txc.bytes;
5306         u64_stats_update_end(&tx_stats->syncp);
5307
5308         netdev_completed_queue(dev, txc.packets, txc.bytes);
5309
5310         if (tp->dirty_tx != dirty_tx) {
5311                 tp->dirty_tx = dirty_tx;
5312                 /* Sync with rtl8169_start_xmit:
5313                  * - publish dirty_tx ring index (write barrier)
5314                  * - refresh cur_tx ring index and queue status (read barrier)
5315                  * May the current thread miss the stopped queue condition,
5316                  * a racing xmit thread can only have a right view of the
5317                  * ring status.
5318                  */
5319                 smp_mb();
5320                 if (netif_queue_stopped(dev) &&
5321                     (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
5322                         netif_wake_queue(dev);
5323                 }
5324                 /*
5325                  * 8168 hack: TxPoll requests are lost when the Tx packets are
5326                  * too close. Let's kick an extra TxPoll request when a burst
5327                  * of start_xmit activity is detected (if it is not detected,
5328                  * it is slow enough). -- FR
5329                  */
5330                 if (tp->cur_tx != dirty_tx) {
5331                         void __iomem *ioaddr = tp->mmio_addr;
5332
5333                         RTL_W8(TxPoll, NPQ);
5334                 }
5335         }
5336 }
5337
5338 static inline int rtl8169_fragmented_frame(u32 status)
5339 {
5340         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
5341 }
5342
5343 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
5344 {
5345         u32 status = opts1 & RxProtoMask;
5346
5347         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
5348             ((status == RxProtoUDP) && !(opts1 & UDPFail)))
5349                 skb->ip_summed = CHECKSUM_UNNECESSARY;
5350         else
5351                 skb_checksum_none_assert(skb);
5352 }
5353
5354 static struct sk_buff *rtl8169_try_rx_copy(void *data,
5355                                            struct rtl8169_private *tp,
5356                                            int pkt_size,
5357                                            dma_addr_t addr)
5358 {
5359         struct sk_buff *skb;
5360         struct device *d = &tp->pci_dev->dev;
5361
5362         data = rtl8169_align(data);
5363         dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
5364         prefetch(data);
5365         skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
5366         if (skb)
5367                 memcpy(skb->data, data, pkt_size);
5368         dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
5369
5370         return skb;
5371 }
5372
5373 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
5374 {
5375         unsigned int cur_rx, rx_left;
5376         unsigned int count;
5377
5378         cur_rx = tp->cur_rx;
5379         rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
5380         rx_left = min(rx_left, budget);
5381
5382         for (; rx_left > 0; rx_left--, cur_rx++) {
5383                 unsigned int entry = cur_rx % NUM_RX_DESC;
5384                 struct RxDesc *desc = tp->RxDescArray + entry;
5385                 u32 status;
5386
5387                 rmb();
5388                 status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
5389
5390                 if (status & DescOwn)
5391                         break;
5392                 if (unlikely(status & RxRES)) {
5393                         netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
5394                                    status);
5395                         dev->stats.rx_errors++;
5396                         if (status & (RxRWT | RxRUNT))
5397                                 dev->stats.rx_length_errors++;
5398                         if (status & RxCRC)
5399                                 dev->stats.rx_crc_errors++;
5400                         if (status & RxFOVF) {
5401                                 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5402                                 dev->stats.rx_fifo_errors++;
5403                         }
5404                         if ((status & (RxRUNT | RxCRC)) &&
5405                             !(status & (RxRWT | RxFOVF)) &&
5406                             (dev->features & NETIF_F_RXALL))
5407                                 goto process_pkt;
5408
5409                         rtl8169_mark_to_asic(desc, rx_buf_sz);
5410                 } else {
5411                         struct sk_buff *skb;
5412                         dma_addr_t addr;
5413                         int pkt_size;
5414
5415 process_pkt:
5416                         addr = le64_to_cpu(desc->addr);
5417                         if (likely(!(dev->features & NETIF_F_RXFCS)))
5418                                 pkt_size = (status & 0x00003fff) - 4;
5419                         else
5420                                 pkt_size = status & 0x00003fff;
5421
5422                         /*
5423                          * The driver does not support incoming fragmented
5424                          * frames. They are seen as a symptom of over-mtu
5425                          * sized frames.
5426                          */
5427                         if (unlikely(rtl8169_fragmented_frame(status))) {
5428                                 dev->stats.rx_dropped++;
5429                                 dev->stats.rx_length_errors++;
5430                                 rtl8169_mark_to_asic(desc, rx_buf_sz);
5431                                 continue;
5432                         }
5433
5434                         skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
5435                                                   tp, pkt_size, addr);
5436                         rtl8169_mark_to_asic(desc, rx_buf_sz);
5437                         if (!skb) {
5438                                 dev->stats.rx_dropped++;
5439                                 continue;
5440                         }
5441
5442                         rtl8169_rx_csum(skb, status);
5443                         skb_put(skb, pkt_size);
5444                         skb->protocol = eth_type_trans(skb, dev);
5445
5446                         rtl8169_rx_vlan_tag(desc, skb);
5447
5448                         napi_gro_receive(&tp->napi, skb);
5449
5450                         u64_stats_update_begin(&tp->rx_stats.syncp);
5451                         tp->rx_stats.packets++;
5452                         tp->rx_stats.bytes += pkt_size;
5453                         u64_stats_update_end(&tp->rx_stats.syncp);
5454                 }
5455
5456                 /* Work around for AMD plateform. */
5457                 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
5458                     (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
5459                         desc->opts2 = 0;
5460                         cur_rx++;
5461                 }
5462         }
5463
5464         count = cur_rx - tp->cur_rx;
5465         tp->cur_rx = cur_rx;
5466
5467         tp->dirty_rx += count;
5468
5469         return count;
5470 }
5471
5472 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
5473 {
5474         struct net_device *dev = dev_instance;
5475         struct rtl8169_private *tp = netdev_priv(dev);
5476         int handled = 0;
5477         u16 status;
5478
5479         status = rtl_get_events(tp);
5480         if (status && status != 0xffff) {
5481                 status &= RTL_EVENT_NAPI | tp->event_slow;
5482                 if (status) {
5483                         handled = 1;
5484
5485                         rtl_irq_disable(tp);
5486                         napi_schedule(&tp->napi);
5487                 }
5488         }
5489         return IRQ_RETVAL(handled);
5490 }
5491
5492 /*
5493  * Workqueue context.
5494  */
5495 static void rtl_slow_event_work(struct rtl8169_private *tp)
5496 {
5497         struct net_device *dev = tp->dev;
5498         u16 status;
5499
5500         status = rtl_get_events(tp) & tp->event_slow;
5501         rtl_ack_events(tp, status);
5502
5503         if (unlikely(status & RxFIFOOver)) {
5504                 switch (tp->mac_version) {
5505                 /* Work around for rx fifo overflow */
5506                 case RTL_GIGA_MAC_VER_11:
5507                         netif_stop_queue(dev);
5508                         /* XXX - Hack alert. See rtl_task(). */
5509                         set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
5510                 default:
5511                         break;
5512                 }
5513         }
5514
5515         if (unlikely(status & SYSErr))
5516                 rtl8169_pcierr_interrupt(dev);
5517
5518         if (status & LinkChg)
5519                 __rtl8169_check_link_status(dev, tp, tp->mmio_addr, true);
5520
5521         napi_disable(&tp->napi);
5522         rtl_irq_disable(tp);
5523
5524         napi_enable(&tp->napi);
5525         napi_schedule(&tp->napi);
5526 }
5527
5528 static void rtl_task(struct work_struct *work)
5529 {
5530         static const struct {
5531                 int bitnr;
5532                 void (*action)(struct rtl8169_private *);
5533         } rtl_work[] = {
5534                 /* XXX - keep rtl_slow_event_work() as first element. */
5535                 { RTL_FLAG_TASK_SLOW_PENDING,   rtl_slow_event_work },
5536                 { RTL_FLAG_TASK_RESET_PENDING,  rtl_reset_work },
5537                 { RTL_FLAG_TASK_PHY_PENDING,    rtl_phy_work }
5538         };
5539         struct rtl8169_private *tp =
5540                 container_of(work, struct rtl8169_private, wk.work);
5541         struct net_device *dev = tp->dev;
5542         int i;
5543
5544         rtl_lock_work(tp);
5545
5546         if (!netif_running(dev) ||
5547             !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
5548                 goto out_unlock;
5549
5550         for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
5551                 bool pending;
5552
5553                 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
5554                 if (pending)
5555                         rtl_work[i].action(tp);
5556         }
5557
5558 out_unlock:
5559         rtl_unlock_work(tp);
5560 }
5561
5562 static int rtl8169_poll(struct napi_struct *napi, int budget)
5563 {
5564         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
5565         struct net_device *dev = tp->dev;
5566         u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
5567         int work_done= 0;
5568         u16 status;
5569
5570         status = rtl_get_events(tp);
5571         rtl_ack_events(tp, status & ~tp->event_slow);
5572
5573         if (status & RTL_EVENT_NAPI_RX)
5574                 work_done = rtl_rx(dev, tp, (u32) budget);
5575
5576         if (status & RTL_EVENT_NAPI_TX)
5577                 rtl_tx(dev, tp);
5578
5579         if (status & tp->event_slow) {
5580                 enable_mask &= ~tp->event_slow;
5581
5582                 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
5583         }
5584
5585         if (work_done < budget) {
5586                 napi_complete(napi);
5587
5588                 rtl_irq_enable(tp, enable_mask);
5589                 mmiowb();
5590         }
5591
5592         return work_done;
5593 }
5594
5595 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
5596 {
5597         struct rtl8169_private *tp = netdev_priv(dev);
5598
5599         if (tp->mac_version > RTL_GIGA_MAC_VER_06)
5600                 return;
5601
5602         dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
5603         RTL_W32(RxMissed, 0);
5604 }
5605
5606 static void rtl8169_down(struct net_device *dev)
5607 {
5608         struct rtl8169_private *tp = netdev_priv(dev);
5609         void __iomem *ioaddr = tp->mmio_addr;
5610
5611         del_timer_sync(&tp->timer);
5612
5613         napi_disable(&tp->napi);
5614         netif_stop_queue(dev);
5615
5616         rtl8169_hw_reset(tp);
5617         /*
5618          * At this point device interrupts can not be enabled in any function,
5619          * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
5620          * and napi is disabled (rtl8169_poll).
5621          */
5622         rtl8169_rx_missed(dev, ioaddr);
5623
5624         /* Give a racing hard_start_xmit a few cycles to complete. */
5625         synchronize_sched();
5626
5627         rtl8169_tx_clear(tp);
5628
5629         rtl8169_rx_clear(tp);
5630
5631         rtl_pll_power_down(tp);
5632 }
5633
5634 static int rtl8169_close(struct net_device *dev)
5635 {
5636         struct rtl8169_private *tp = netdev_priv(dev);
5637         struct pci_dev *pdev = tp->pci_dev;
5638
5639         pm_runtime_get_sync(&pdev->dev);
5640
5641         /* Update counters before going down */
5642         rtl8169_update_counters(dev);
5643
5644         rtl_lock_work(tp);
5645         clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
5646
5647         rtl8169_down(dev);
5648         rtl_unlock_work(tp);
5649
5650         free_irq(pdev->irq, dev);
5651
5652         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
5653                           tp->RxPhyAddr);
5654         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
5655                           tp->TxPhyAddr);
5656         tp->TxDescArray = NULL;
5657         tp->RxDescArray = NULL;
5658
5659         pm_runtime_put_sync(&pdev->dev);
5660
5661         return 0;
5662 }
5663
5664 #ifdef CONFIG_NET_POLL_CONTROLLER
5665 static void rtl8169_netpoll(struct net_device *dev)
5666 {
5667         struct rtl8169_private *tp = netdev_priv(dev);
5668
5669         rtl8169_interrupt(tp->pci_dev->irq, dev);
5670 }
5671 #endif
5672
5673 static int rtl_open(struct net_device *dev)
5674 {
5675         struct rtl8169_private *tp = netdev_priv(dev);
5676         void __iomem *ioaddr = tp->mmio_addr;
5677         struct pci_dev *pdev = tp->pci_dev;
5678         int retval = -ENOMEM;
5679
5680         pm_runtime_get_sync(&pdev->dev);
5681
5682         /*
5683          * Rx and Tx desscriptors needs 256 bytes alignment.
5684          * dma_alloc_coherent provides more.
5685          */
5686         tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
5687                                              &tp->TxPhyAddr, GFP_KERNEL);
5688         if (!tp->TxDescArray)
5689                 goto err_pm_runtime_put;
5690
5691         tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
5692                                              &tp->RxPhyAddr, GFP_KERNEL);
5693         if (!tp->RxDescArray)
5694                 goto err_free_tx_0;
5695
5696         retval = rtl8169_init_ring(dev);
5697         if (retval < 0)
5698                 goto err_free_rx_1;
5699
5700         INIT_WORK(&tp->wk.work, rtl_task);
5701
5702         smp_mb();
5703
5704         rtl_request_firmware(tp);
5705
5706         retval = request_irq(pdev->irq, rtl8169_interrupt,
5707                              (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
5708                              dev->name, dev);
5709         if (retval < 0)
5710                 goto err_release_fw_2;
5711
5712         rtl_lock_work(tp);
5713
5714         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
5715
5716         napi_enable(&tp->napi);
5717
5718         rtl8169_init_phy(dev, tp);
5719
5720         __rtl8169_set_features(dev, dev->features);
5721
5722         rtl_pll_power_up(tp);
5723
5724         rtl_hw_start(dev);
5725
5726         netif_start_queue(dev);
5727
5728         rtl_unlock_work(tp);
5729
5730         tp->saved_wolopts = 0;
5731         pm_runtime_put_noidle(&pdev->dev);
5732
5733         rtl8169_check_link_status(dev, tp, ioaddr);
5734 out:
5735         return retval;
5736
5737 err_release_fw_2:
5738         rtl_release_firmware(tp);
5739         rtl8169_rx_clear(tp);
5740 err_free_rx_1:
5741         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
5742                           tp->RxPhyAddr);
5743         tp->RxDescArray = NULL;
5744 err_free_tx_0:
5745         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
5746                           tp->TxPhyAddr);
5747         tp->TxDescArray = NULL;
5748 err_pm_runtime_put:
5749         pm_runtime_put_noidle(&pdev->dev);
5750         goto out;
5751 }
5752
5753 static struct rtnl_link_stats64 *
5754 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
5755 {
5756         struct rtl8169_private *tp = netdev_priv(dev);
5757         void __iomem *ioaddr = tp->mmio_addr;
5758         unsigned int start;
5759
5760         if (netif_running(dev))
5761                 rtl8169_rx_missed(dev, ioaddr);
5762
5763         do {
5764                 start = u64_stats_fetch_begin_bh(&tp->rx_stats.syncp);
5765                 stats->rx_packets = tp->rx_stats.packets;
5766                 stats->rx_bytes = tp->rx_stats.bytes;
5767         } while (u64_stats_fetch_retry_bh(&tp->rx_stats.syncp, start));
5768
5769
5770         do {
5771                 start = u64_stats_fetch_begin_bh(&tp->tx_stats.syncp);
5772                 stats->tx_packets = tp->tx_stats.packets;
5773                 stats->tx_bytes = tp->tx_stats.bytes;
5774         } while (u64_stats_fetch_retry_bh(&tp->tx_stats.syncp, start));
5775
5776         stats->rx_dropped       = dev->stats.rx_dropped;
5777         stats->tx_dropped       = dev->stats.tx_dropped;
5778         stats->rx_length_errors = dev->stats.rx_length_errors;
5779         stats->rx_errors        = dev->stats.rx_errors;
5780         stats->rx_crc_errors    = dev->stats.rx_crc_errors;
5781         stats->rx_fifo_errors   = dev->stats.rx_fifo_errors;
5782         stats->rx_missed_errors = dev->stats.rx_missed_errors;
5783
5784         return stats;
5785 }
5786
5787 static void rtl8169_net_suspend(struct net_device *dev)
5788 {
5789         struct rtl8169_private *tp = netdev_priv(dev);
5790
5791         if (!netif_running(dev))
5792                 return;
5793
5794         netif_device_detach(dev);
5795         netif_stop_queue(dev);
5796
5797         rtl_lock_work(tp);
5798         napi_disable(&tp->napi);
5799         clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
5800         rtl_unlock_work(tp);
5801
5802         rtl_pll_power_down(tp);
5803 }
5804
5805 #ifdef CONFIG_PM
5806
5807 static int rtl8169_suspend(struct device *device)
5808 {
5809         struct pci_dev *pdev = to_pci_dev(device);
5810         struct net_device *dev = pci_get_drvdata(pdev);
5811
5812         rtl8169_net_suspend(dev);
5813
5814         return 0;
5815 }
5816
5817 static void __rtl8169_resume(struct net_device *dev)
5818 {
5819         struct rtl8169_private *tp = netdev_priv(dev);
5820
5821         netif_device_attach(dev);
5822
5823         rtl_pll_power_up(tp);
5824
5825         rtl_lock_work(tp);
5826         napi_enable(&tp->napi);
5827         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
5828         rtl_unlock_work(tp);
5829
5830         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5831 }
5832
5833 static int rtl8169_resume(struct device *device)
5834 {
5835         struct pci_dev *pdev = to_pci_dev(device);
5836         struct net_device *dev = pci_get_drvdata(pdev);
5837         struct rtl8169_private *tp = netdev_priv(dev);
5838
5839         rtl8169_init_phy(dev, tp);
5840
5841         if (netif_running(dev))
5842                 __rtl8169_resume(dev);
5843
5844         return 0;
5845 }
5846
5847 static int rtl8169_runtime_suspend(struct device *device)
5848 {
5849         struct pci_dev *pdev = to_pci_dev(device);
5850         struct net_device *dev = pci_get_drvdata(pdev);
5851         struct rtl8169_private *tp = netdev_priv(dev);
5852
5853         if (!tp->TxDescArray)
5854                 return 0;
5855
5856         rtl_lock_work(tp);
5857         tp->saved_wolopts = __rtl8169_get_wol(tp);
5858         __rtl8169_set_wol(tp, WAKE_ANY);
5859         rtl_unlock_work(tp);
5860
5861         rtl8169_net_suspend(dev);
5862
5863         return 0;
5864 }
5865
5866 static int rtl8169_runtime_resume(struct device *device)
5867 {
5868         struct pci_dev *pdev = to_pci_dev(device);
5869         struct net_device *dev = pci_get_drvdata(pdev);
5870         struct rtl8169_private *tp = netdev_priv(dev);
5871
5872         if (!tp->TxDescArray)
5873                 return 0;
5874
5875         rtl_lock_work(tp);
5876         __rtl8169_set_wol(tp, tp->saved_wolopts);
5877         tp->saved_wolopts = 0;
5878         rtl_unlock_work(tp);
5879
5880         rtl8169_init_phy(dev, tp);
5881
5882         __rtl8169_resume(dev);
5883
5884         return 0;
5885 }
5886
5887 static int rtl8169_runtime_idle(struct device *device)
5888 {
5889         struct pci_dev *pdev = to_pci_dev(device);
5890         struct net_device *dev = pci_get_drvdata(pdev);
5891         struct rtl8169_private *tp = netdev_priv(dev);
5892
5893         return tp->TxDescArray ? -EBUSY : 0;
5894 }
5895
5896 static const struct dev_pm_ops rtl8169_pm_ops = {
5897         .suspend                = rtl8169_suspend,
5898         .resume                 = rtl8169_resume,
5899         .freeze                 = rtl8169_suspend,
5900         .thaw                   = rtl8169_resume,
5901         .poweroff               = rtl8169_suspend,
5902         .restore                = rtl8169_resume,
5903         .runtime_suspend        = rtl8169_runtime_suspend,
5904         .runtime_resume         = rtl8169_runtime_resume,
5905         .runtime_idle           = rtl8169_runtime_idle,
5906 };
5907
5908 #define RTL8169_PM_OPS  (&rtl8169_pm_ops)
5909
5910 #else /* !CONFIG_PM */
5911
5912 #define RTL8169_PM_OPS  NULL
5913
5914 #endif /* !CONFIG_PM */
5915
5916 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
5917 {
5918         void __iomem *ioaddr = tp->mmio_addr;
5919
5920         /* WoL fails with 8168b when the receiver is disabled. */
5921         switch (tp->mac_version) {
5922         case RTL_GIGA_MAC_VER_11:
5923         case RTL_GIGA_MAC_VER_12:
5924         case RTL_GIGA_MAC_VER_17:
5925                 pci_clear_master(tp->pci_dev);
5926
5927                 RTL_W8(ChipCmd, CmdRxEnb);
5928                 /* PCI commit */
5929                 RTL_R8(ChipCmd);
5930                 break;
5931         default:
5932                 break;
5933         }
5934 }
5935
5936 static void rtl_shutdown(struct pci_dev *pdev)
5937 {
5938         struct net_device *dev = pci_get_drvdata(pdev);
5939         struct rtl8169_private *tp = netdev_priv(dev);
5940         struct device *d = &pdev->dev;
5941
5942         pm_runtime_get_sync(d);
5943
5944         rtl8169_net_suspend(dev);
5945
5946         /* Restore original MAC address */
5947         rtl_rar_set(tp, dev->perm_addr);
5948
5949         rtl8169_hw_reset(tp);
5950
5951         if (system_state == SYSTEM_POWER_OFF) {
5952                 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
5953                         rtl_wol_suspend_quirk(tp);
5954                         rtl_wol_shutdown_quirk(tp);
5955                 }
5956
5957                 pci_wake_from_d3(pdev, true);
5958                 pci_set_power_state(pdev, PCI_D3hot);
5959         }
5960
5961         pm_runtime_put_noidle(d);
5962 }
5963
5964 static void __devexit rtl_remove_one(struct pci_dev *pdev)
5965 {
5966         struct net_device *dev = pci_get_drvdata(pdev);
5967         struct rtl8169_private *tp = netdev_priv(dev);
5968
5969         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
5970             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
5971             tp->mac_version == RTL_GIGA_MAC_VER_31) {
5972                 rtl8168_driver_stop(tp);
5973         }
5974
5975         cancel_work_sync(&tp->wk.work);
5976
5977         unregister_netdev(dev);
5978
5979         rtl_release_firmware(tp);
5980
5981         if (pci_dev_run_wake(pdev))
5982                 pm_runtime_get_noresume(&pdev->dev);
5983
5984         /* restore original MAC address */
5985         rtl_rar_set(tp, dev->perm_addr);
5986
5987         rtl_disable_msi(pdev, tp);
5988         rtl8169_release_board(pdev, dev, tp->mmio_addr);
5989         pci_set_drvdata(pdev, NULL);
5990 }
5991
5992 static const struct net_device_ops rtl_netdev_ops = {
5993         .ndo_open               = rtl_open,
5994         .ndo_stop               = rtl8169_close,
5995         .ndo_get_stats64        = rtl8169_get_stats64,
5996         .ndo_start_xmit         = rtl8169_start_xmit,
5997         .ndo_tx_timeout         = rtl8169_tx_timeout,
5998         .ndo_validate_addr      = eth_validate_addr,
5999         .ndo_change_mtu         = rtl8169_change_mtu,
6000         .ndo_fix_features       = rtl8169_fix_features,
6001         .ndo_set_features       = rtl8169_set_features,
6002         .ndo_set_mac_address    = rtl_set_mac_address,
6003         .ndo_do_ioctl           = rtl8169_ioctl,
6004         .ndo_set_rx_mode        = rtl_set_rx_mode,
6005 #ifdef CONFIG_NET_POLL_CONTROLLER
6006         .ndo_poll_controller    = rtl8169_netpoll,
6007 #endif
6008
6009 };
6010
6011 static const struct rtl_cfg_info {
6012         void (*hw_start)(struct net_device *);
6013         unsigned int region;
6014         unsigned int align;
6015         u16 event_slow;
6016         unsigned features;
6017         u8 default_ver;
6018 } rtl_cfg_infos [] = {
6019         [RTL_CFG_0] = {
6020                 .hw_start       = rtl_hw_start_8169,
6021                 .region         = 1,
6022                 .align          = 0,
6023                 .event_slow     = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
6024                 .features       = RTL_FEATURE_GMII,
6025                 .default_ver    = RTL_GIGA_MAC_VER_01,
6026         },
6027         [RTL_CFG_1] = {
6028                 .hw_start       = rtl_hw_start_8168,
6029                 .region         = 2,
6030                 .align          = 8,
6031                 .event_slow     = SYSErr | LinkChg | RxOverflow,
6032                 .features       = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
6033                 .default_ver    = RTL_GIGA_MAC_VER_11,
6034         },
6035         [RTL_CFG_2] = {
6036                 .hw_start       = rtl_hw_start_8101,
6037                 .region         = 2,
6038                 .align          = 8,
6039                 .event_slow     = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
6040                                   PCSTimeout,
6041                 .features       = RTL_FEATURE_MSI,
6042                 .default_ver    = RTL_GIGA_MAC_VER_13,
6043         }
6044 };
6045
6046 /* Cfg9346_Unlock assumed. */
6047 static unsigned rtl_try_msi(struct rtl8169_private *tp,
6048                             const struct rtl_cfg_info *cfg)
6049 {
6050         void __iomem *ioaddr = tp->mmio_addr;
6051         unsigned msi = 0;
6052         u8 cfg2;
6053
6054         cfg2 = RTL_R8(Config2) & ~MSIEnable;
6055         if (cfg->features & RTL_FEATURE_MSI) {
6056                 if (pci_enable_msi(tp->pci_dev)) {
6057                         netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n");
6058                 } else {
6059                         cfg2 |= MSIEnable;
6060                         msi = RTL_FEATURE_MSI;
6061                 }
6062         }
6063         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
6064                 RTL_W8(Config2, cfg2);
6065         return msi;
6066 }
6067
6068 static int __devinit
6069 rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
6070 {
6071         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
6072         const unsigned int region = cfg->region;
6073         struct rtl8169_private *tp;
6074         struct mii_if_info *mii;
6075         struct net_device *dev;
6076         void __iomem *ioaddr;
6077         int chipset, i;
6078         int rc;
6079
6080         if (netif_msg_drv(&debug)) {
6081                 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
6082                        MODULENAME, RTL8169_VERSION);
6083         }
6084
6085         dev = alloc_etherdev(sizeof (*tp));
6086         if (!dev) {
6087                 rc = -ENOMEM;
6088                 goto out;
6089         }
6090
6091         SET_NETDEV_DEV(dev, &pdev->dev);
6092         dev->netdev_ops = &rtl_netdev_ops;
6093         tp = netdev_priv(dev);
6094         tp->dev = dev;
6095         tp->pci_dev = pdev;
6096         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
6097
6098         mii = &tp->mii;
6099         mii->dev = dev;
6100         mii->mdio_read = rtl_mdio_read;
6101         mii->mdio_write = rtl_mdio_write;
6102         mii->phy_id_mask = 0x1f;
6103         mii->reg_num_mask = 0x1f;
6104         mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
6105
6106         /* disable ASPM completely as that cause random device stop working
6107          * problems as well as full system hangs for some PCIe devices users */
6108         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
6109                                      PCIE_LINK_STATE_CLKPM);
6110
6111         /* enable device (incl. PCI PM wakeup and hotplug setup) */
6112         rc = pci_enable_device(pdev);
6113         if (rc < 0) {
6114                 netif_err(tp, probe, dev, "enable failure\n");
6115                 goto err_out_free_dev_1;
6116         }
6117
6118         if (pci_set_mwi(pdev) < 0)
6119                 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
6120
6121         /* make sure PCI base addr 1 is MMIO */
6122         if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
6123                 netif_err(tp, probe, dev,
6124                           "region #%d not an MMIO resource, aborting\n",
6125                           region);
6126                 rc = -ENODEV;
6127                 goto err_out_mwi_2;
6128         }
6129
6130         /* check for weird/broken PCI region reporting */
6131         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
6132                 netif_err(tp, probe, dev,
6133                           "Invalid PCI region size(s), aborting\n");
6134                 rc = -ENODEV;
6135                 goto err_out_mwi_2;
6136         }
6137
6138         rc = pci_request_regions(pdev, MODULENAME);
6139         if (rc < 0) {
6140                 netif_err(tp, probe, dev, "could not request regions\n");
6141                 goto err_out_mwi_2;
6142         }
6143
6144         tp->cp_cmd = RxChkSum;
6145
6146         if ((sizeof(dma_addr_t) > 4) &&
6147             !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
6148                 tp->cp_cmd |= PCIDAC;
6149                 dev->features |= NETIF_F_HIGHDMA;
6150         } else {
6151                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
6152                 if (rc < 0) {
6153                         netif_err(tp, probe, dev, "DMA configuration failed\n");
6154                         goto err_out_free_res_3;
6155                 }
6156         }
6157
6158         /* ioremap MMIO region */
6159         ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
6160         if (!ioaddr) {
6161                 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
6162                 rc = -EIO;
6163                 goto err_out_free_res_3;
6164         }
6165         tp->mmio_addr = ioaddr;
6166
6167         if (!pci_is_pcie(pdev))
6168                 netif_info(tp, probe, dev, "not PCI Express\n");
6169
6170         /* Identify chip attached to board */
6171         rtl8169_get_mac_version(tp, dev, cfg->default_ver);
6172
6173         rtl_init_rxcfg(tp);
6174
6175         rtl_irq_disable(tp);
6176
6177         rtl_hw_reset(tp);
6178
6179         rtl_ack_events(tp, 0xffff);
6180
6181         pci_set_master(pdev);
6182
6183         /*
6184          * Pretend we are using VLANs; This bypasses a nasty bug where
6185          * Interrupts stop flowing on high load on 8110SCd controllers.
6186          */
6187         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
6188                 tp->cp_cmd |= RxVlan;
6189
6190         rtl_init_mdio_ops(tp);
6191         rtl_init_pll_power_ops(tp);
6192         rtl_init_jumbo_ops(tp);
6193
6194         rtl8169_print_mac_version(tp);
6195
6196         chipset = tp->mac_version;
6197         tp->txd_version = rtl_chip_infos[chipset].txd_version;
6198
6199         RTL_W8(Cfg9346, Cfg9346_Unlock);
6200         RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
6201         RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
6202         if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
6203                 tp->features |= RTL_FEATURE_WOL;
6204         if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
6205                 tp->features |= RTL_FEATURE_WOL;
6206         tp->features |= rtl_try_msi(tp, cfg);
6207         RTL_W8(Cfg9346, Cfg9346_Lock);
6208
6209         if (rtl_tbi_enabled(tp)) {
6210                 tp->set_speed = rtl8169_set_speed_tbi;
6211                 tp->get_settings = rtl8169_gset_tbi;
6212                 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
6213                 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
6214                 tp->link_ok = rtl8169_tbi_link_ok;
6215                 tp->do_ioctl = rtl_tbi_ioctl;
6216         } else {
6217                 tp->set_speed = rtl8169_set_speed_xmii;
6218                 tp->get_settings = rtl8169_gset_xmii;
6219                 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
6220                 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
6221                 tp->link_ok = rtl8169_xmii_link_ok;
6222                 tp->do_ioctl = rtl_xmii_ioctl;
6223         }
6224
6225         mutex_init(&tp->wk.mutex);
6226
6227         /* Get MAC address */
6228         for (i = 0; i < ETH_ALEN; i++)
6229                 dev->dev_addr[i] = RTL_R8(MAC0 + i);
6230         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
6231
6232         SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
6233         dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
6234
6235         netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
6236
6237         /* don't enable SG, IP_CSUM and TSO by default - it might not work
6238          * properly for all devices */
6239         dev->features |= NETIF_F_RXCSUM |
6240                 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
6241
6242         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
6243                 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
6244         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
6245                 NETIF_F_HIGHDMA;
6246
6247         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
6248                 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
6249                 dev->hw_features &= ~NETIF_F_HW_VLAN_RX;
6250
6251         dev->hw_features |= NETIF_F_RXALL;
6252         dev->hw_features |= NETIF_F_RXFCS;
6253
6254         tp->hw_start = cfg->hw_start;
6255         tp->event_slow = cfg->event_slow;
6256
6257         tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
6258                 ~(RxBOVF | RxFOVF) : ~0;
6259
6260         init_timer(&tp->timer);
6261         tp->timer.data = (unsigned long) dev;
6262         tp->timer.function = rtl8169_phy_timer;
6263
6264         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
6265
6266         rc = register_netdev(dev);
6267         if (rc < 0)
6268                 goto err_out_msi_4;
6269
6270         pci_set_drvdata(pdev, dev);
6271
6272         netif_info(tp, probe, dev, "%s at 0x%p, %pM, XID %08x IRQ %d\n",
6273                    rtl_chip_infos[chipset].name, ioaddr, dev->dev_addr,
6274                    (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), pdev->irq);
6275         if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
6276                 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
6277                            "tx checksumming: %s]\n",
6278                            rtl_chip_infos[chipset].jumbo_max,
6279                            rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko");
6280         }
6281
6282         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
6283             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
6284             tp->mac_version == RTL_GIGA_MAC_VER_31) {
6285                 rtl8168_driver_start(tp);
6286         }
6287
6288         device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
6289
6290         if (pci_dev_run_wake(pdev))
6291                 pm_runtime_put_noidle(&pdev->dev);
6292
6293         netif_carrier_off(dev);
6294
6295 out:
6296         return rc;
6297
6298 err_out_msi_4:
6299         rtl_disable_msi(pdev, tp);
6300         iounmap(ioaddr);
6301 err_out_free_res_3:
6302         pci_release_regions(pdev);
6303 err_out_mwi_2:
6304         pci_clear_mwi(pdev);
6305         pci_disable_device(pdev);
6306 err_out_free_dev_1:
6307         free_netdev(dev);
6308         goto out;
6309 }
6310
6311 static struct pci_driver rtl8169_pci_driver = {
6312         .name           = MODULENAME,
6313         .id_table       = rtl8169_pci_tbl,
6314         .probe          = rtl_init_one,
6315         .remove         = __devexit_p(rtl_remove_one),
6316         .shutdown       = rtl_shutdown,
6317         .driver.pm      = RTL8169_PM_OPS,
6318 };
6319
6320 static int __init rtl8169_init_module(void)
6321 {
6322         return pci_register_driver(&rtl8169_pci_driver);
6323 }
6324
6325 static void __exit rtl8169_cleanup_module(void)
6326 {
6327         pci_unregister_driver(&rtl8169_pci_driver);
6328 }
6329
6330 module_init(rtl8169_init_module);
6331 module_exit(rtl8169_cleanup_module);