drivers/net/ethernet/realtek/r8169.c

   1 /*
   2  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   3  *
   4  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   5  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   6  * Copyright (c) a lot of people too. Please respect their work.
   7  *
   8  * See MAINTAINERS file for support contact information.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/moduleparam.h>
  13 #include <linux/pci.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/delay.h>
  17 #include <linux/ethtool.h>
  18 #include <linux/mii.h>
  19 #include <linux/if_vlan.h>
  20 #include <linux/crc32.h>
  21 #include <linux/in.h>
  22 #include <linux/ip.h>
  23 #include <linux/tcp.h>
  24 #include <linux/init.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/pm_runtime.h>
  28 #include <linux/firmware.h>
  29 #include <linux/pci-aspm.h>
  30 #include <linux/prefetch.h>
  31
  32 #include <asm/io.h>
  33 #include <asm/irq.h>
  34
  35 #define RTL8169_VERSION "2.3LK-NAPI"
  36 #define MODULENAME "r8169"
  37 #define PFX MODULENAME ": "
  38
  39 #define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
  40 #define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
  41 #define FIRMWARE_8168E_1        "rtl_nic/rtl8168e-1.fw"
  42 #define FIRMWARE_8168E_2        "rtl_nic/rtl8168e-2.fw"
  43 #define FIRMWARE_8168E_3        "rtl_nic/rtl8168e-3.fw"
  44 #define FIRMWARE_8168F_1        "rtl_nic/rtl8168f-1.fw"
  45 #define FIRMWARE_8168F_2        "rtl_nic/rtl8168f-2.fw"
  46 #define FIRMWARE_8105E_1        "rtl_nic/rtl8105e-1.fw"
  47 #define FIRMWARE_8402_1         "rtl_nic/rtl8402-1.fw"
  48 #define FIRMWARE_8411_1         "rtl_nic/rtl8411-1.fw"
  49 #define FIRMWARE_8106E_1        "rtl_nic/rtl8106e-1.fw"
  50 #define FIRMWARE_8168G_1        "rtl_nic/rtl8168g-1.fw"
  51
  52 #ifdef RTL8169_DEBUG
  53 #define assert(expr) \
  54         if (!(expr)) {                                  \
  55                 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
  56                 #expr,__FILE__,__func__,__LINE__);              \
  57         }
  58 #define dprintk(fmt, args...) \
  59         do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
  60 #else
  61 #define assert(expr) do {} while (0)
  62 #define dprintk(fmt, args...)   do {} while (0)
  63 #endif /* RTL8169_DEBUG */
  64
  65 #define R8169_MSG_DEFAULT \
  66         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  67
  68 #define TX_SLOTS_AVAIL(tp) \
  69         (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
  70
  71 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
  72 #define TX_FRAGS_READY_FOR(tp,nr_frags) \
  73         (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
  74
  75 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  76    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  77 static const int multicast_filter_limit = 32;
  78
  79 #define MAX_READ_REQUEST_SHIFT  12
  80 #define TX_DMA_BURST    7       /* Maximum PCI burst, '7' is unlimited */
  81 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  82
  83 #define R8169_REGS_SIZE         256
  84 #define R8169_NAPI_WEIGHT       64
  85 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
  86 #define NUM_RX_DESC     256U    /* Number of Rx descriptor registers */
  87 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  88 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  89
  90 #define RTL8169_TX_TIMEOUT      (6*HZ)
  91 #define RTL8169_PHY_TIMEOUT     (10*HZ)
  92
  93 /* write/read MMIO register */
  94 #define RTL_W8(reg, val8)       writeb ((val8), ioaddr + (reg))
  95 #define RTL_W16(reg, val16)     writew ((val16), ioaddr + (reg))
  96 #define RTL_W32(reg, val32)     writel ((val32), ioaddr + (reg))
  97 #define RTL_R8(reg)             readb (ioaddr + (reg))
  98 #define RTL_R16(reg)            readw (ioaddr + (reg))
  99 #define RTL_R32(reg)            readl (ioaddr + (reg))
 100
 101 enum mac_version {
 102         RTL_GIGA_MAC_VER_01 = 0,
 103         RTL_GIGA_MAC_VER_02,
 104         RTL_GIGA_MAC_VER_03,
 105         RTL_GIGA_MAC_VER_04,
 106         RTL_GIGA_MAC_VER_05,
 107         RTL_GIGA_MAC_VER_06,
 108         RTL_GIGA_MAC_VER_07,
 109         RTL_GIGA_MAC_VER_08,
 110         RTL_GIGA_MAC_VER_09,
 111         RTL_GIGA_MAC_VER_10,
 112         RTL_GIGA_MAC_VER_11,
 113         RTL_GIGA_MAC_VER_12,
 114         RTL_GIGA_MAC_VER_13,
 115         RTL_GIGA_MAC_VER_14,
 116         RTL_GIGA_MAC_VER_15,
 117         RTL_GIGA_MAC_VER_16,
 118         RTL_GIGA_MAC_VER_17,
 119         RTL_GIGA_MAC_VER_18,
 120         RTL_GIGA_MAC_VER_19,
 121         RTL_GIGA_MAC_VER_20,
 122         RTL_GIGA_MAC_VER_21,
 123         RTL_GIGA_MAC_VER_22,
 124         RTL_GIGA_MAC_VER_23,
 125         RTL_GIGA_MAC_VER_24,
 126         RTL_GIGA_MAC_VER_25,
 127         RTL_GIGA_MAC_VER_26,
 128         RTL_GIGA_MAC_VER_27,
 129         RTL_GIGA_MAC_VER_28,
 130         RTL_GIGA_MAC_VER_29,
 131         RTL_GIGA_MAC_VER_30,
 132         RTL_GIGA_MAC_VER_31,
 133         RTL_GIGA_MAC_VER_32,
 134         RTL_GIGA_MAC_VER_33,
 135         RTL_GIGA_MAC_VER_34,
 136         RTL_GIGA_MAC_VER_35,
 137         RTL_GIGA_MAC_VER_36,
 138         RTL_GIGA_MAC_VER_37,
 139         RTL_GIGA_MAC_VER_38,
 140         RTL_GIGA_MAC_VER_39,
 141         RTL_GIGA_MAC_VER_40,
 142         RTL_GIGA_MAC_VER_41,
 143         RTL_GIGA_MAC_NONE   = 0xff,
 144 };
 145
 146 enum rtl_tx_desc_version {
 147         RTL_TD_0        = 0,
 148         RTL_TD_1        = 1,
 149 };
 150
 151 #define JUMBO_1K        ETH_DATA_LEN
 152 #define JUMBO_4K        (4*1024 - ETH_HLEN - 2)
 153 #define JUMBO_6K        (6*1024 - ETH_HLEN - 2)
 154 #define JUMBO_7K        (7*1024 - ETH_HLEN - 2)
 155 #define JUMBO_9K        (9*1024 - ETH_HLEN - 2)
 156
 157 #define _R(NAME,TD,FW,SZ,B) {   \
 158         .name = NAME,           \
 159         .txd_version = TD,      \
 160         .fw_name = FW,          \
 161         .jumbo_max = SZ,        \
 162         .jumbo_tx_csum = B      \
 163 }
 164
 165 static const struct {
 166         const char *name;
 167         enum rtl_tx_desc_version txd_version;
 168         const char *fw_name;
 169         u16 jumbo_max;
 170         bool jumbo_tx_csum;
 171 } rtl_chip_infos[] = {
 172         /* PCI devices. */
 173         [RTL_GIGA_MAC_VER_01] =
 174                 _R("RTL8169",           RTL_TD_0, NULL, JUMBO_7K, true),
 175         [RTL_GIGA_MAC_VER_02] =
 176                 _R("RTL8169s",          RTL_TD_0, NULL, JUMBO_7K, true),
 177         [RTL_GIGA_MAC_VER_03] =
 178                 _R("RTL8110s",          RTL_TD_0, NULL, JUMBO_7K, true),
 179         [RTL_GIGA_MAC_VER_04] =
 180                 _R("RTL8169sb/8110sb",  RTL_TD_0, NULL, JUMBO_7K, true),
 181         [RTL_GIGA_MAC_VER_05] =
 182                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL, JUMBO_7K, true),
 183         [RTL_GIGA_MAC_VER_06] =
 184                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL, JUMBO_7K, true),
 185         /* PCI-E devices. */
 186         [RTL_GIGA_MAC_VER_07] =
 187                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 188         [RTL_GIGA_MAC_VER_08] =
 189                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 190         [RTL_GIGA_MAC_VER_09] =
 191                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 192         [RTL_GIGA_MAC_VER_10] =
 193                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 194         [RTL_GIGA_MAC_VER_11] =
 195                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K, false),
 196         [RTL_GIGA_MAC_VER_12] =
 197                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K, false),
 198         [RTL_GIGA_MAC_VER_13] =
 199                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 200         [RTL_GIGA_MAC_VER_14] =
 201                 _R("RTL8100e",          RTL_TD_0, NULL, JUMBO_1K, true),
 202         [RTL_GIGA_MAC_VER_15] =
 203                 _R("RTL8100e",          RTL_TD_0, NULL, JUMBO_1K, true),
 204         [RTL_GIGA_MAC_VER_16] =
 205                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 206         [RTL_GIGA_MAC_VER_17] =
 207                 _R("RTL8168b/8111b",    RTL_TD_1, NULL, JUMBO_4K, false),
 208         [RTL_GIGA_MAC_VER_18] =
 209                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 210         [RTL_GIGA_MAC_VER_19] =
 211                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 212         [RTL_GIGA_MAC_VER_20] =
 213                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 214         [RTL_GIGA_MAC_VER_21] =
 215                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 216         [RTL_GIGA_MAC_VER_22] =
 217                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 218         [RTL_GIGA_MAC_VER_23] =
 219                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 220         [RTL_GIGA_MAC_VER_24] =
 221                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 222         [RTL_GIGA_MAC_VER_25] =
 223                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_1,
 224                                                         JUMBO_9K, false),
 225         [RTL_GIGA_MAC_VER_26] =
 226                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_2,
 227                                                         JUMBO_9K, false),
 228         [RTL_GIGA_MAC_VER_27] =
 229                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 230         [RTL_GIGA_MAC_VER_28] =
 231                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 232         [RTL_GIGA_MAC_VER_29] =
 233                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1,
 234                                                         JUMBO_1K, true),
 235         [RTL_GIGA_MAC_VER_30] =
 236                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1,
 237                                                         JUMBO_1K, true),
 238         [RTL_GIGA_MAC_VER_31] =
 239                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 240         [RTL_GIGA_MAC_VER_32] =
 241                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_1,
 242                                                         JUMBO_9K, false),
 243         [RTL_GIGA_MAC_VER_33] =
 244                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_2,
 245                                                         JUMBO_9K, false),
 246         [RTL_GIGA_MAC_VER_34] =
 247                 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3,
 248                                                         JUMBO_9K, false),
 249         [RTL_GIGA_MAC_VER_35] =
 250                 _R("RTL8168f/8111f",    RTL_TD_1, FIRMWARE_8168F_1,
 251                                                         JUMBO_9K, false),
 252         [RTL_GIGA_MAC_VER_36] =
 253                 _R("RTL8168f/8111f",    RTL_TD_1, FIRMWARE_8168F_2,
 254                                                         JUMBO_9K, false),
 255         [RTL_GIGA_MAC_VER_37] =
 256                 _R("RTL8402",           RTL_TD_1, FIRMWARE_8402_1,
 257                                                         JUMBO_1K, true),
 258         [RTL_GIGA_MAC_VER_38] =
 259                 _R("RTL8411",           RTL_TD_1, FIRMWARE_8411_1,
 260                                                         JUMBO_9K, false),
 261         [RTL_GIGA_MAC_VER_39] =
 262                 _R("RTL8106e",          RTL_TD_1, FIRMWARE_8106E_1,
 263                                                         JUMBO_1K, true),
 264         [RTL_GIGA_MAC_VER_40] =
 265                 _R("RTL8168g/8111g",    RTL_TD_1, FIRMWARE_8168G_1,
 266                                                         JUMBO_9K, false),
 267         [RTL_GIGA_MAC_VER_41] =
 268                 _R("RTL8168g/8111g",    RTL_TD_1, NULL, JUMBO_9K, false),
 269 };
 270 #undef _R
 271
 272 enum cfg_version {
 273         RTL_CFG_0 = 0x00,
 274         RTL_CFG_1,
 275         RTL_CFG_2
 276 };
 277
 278 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
 279         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8129), 0, 0, RTL_CFG_0 },
 280         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8136), 0, 0, RTL_CFG_2 },
 281         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8167), 0, 0, RTL_CFG_0 },
 282         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8168), 0, 0, RTL_CFG_1 },
 283         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8169), 0, 0, RTL_CFG_0 },
 284         { PCI_VENDOR_ID_DLINK,                  0x4300,
 285                 PCI_VENDOR_ID_DLINK, 0x4b10,             0, 0, RTL_CFG_1 },
 286         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4300), 0, 0, RTL_CFG_0 },
 287         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4302), 0, 0, RTL_CFG_0 },
 288         { PCI_DEVICE(PCI_VENDOR_ID_AT,          0xc107), 0, 0, RTL_CFG_0 },
 289         { PCI_DEVICE(0x16ec,                    0x0116), 0, 0, RTL_CFG_0 },
 290         { PCI_VENDOR_ID_LINKSYS,                0x1032,
 291                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
 292         { 0x0001,                               0x8168,
 293                 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
 294         {0,},
 295 };
 296
 297 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 298
 299 static int rx_buf_sz = 16383;
 300 static int use_dac;
 301 static struct {
 302         u32 msg_enable;
 303 } debug = { -1 };
 304
 305 enum rtl_registers {
 306         MAC0            = 0,    /* Ethernet hardware address. */
 307         MAC4            = 4,
 308         MAR0            = 8,    /* Multicast filter. */
 309         CounterAddrLow          = 0x10,
 310         CounterAddrHigh         = 0x14,
 311         TxDescStartAddrLow      = 0x20,
 312         TxDescStartAddrHigh     = 0x24,
 313         TxHDescStartAddrLow     = 0x28,
 314         TxHDescStartAddrHigh    = 0x2c,
 315         FLASH           = 0x30,
 316         ERSR            = 0x36,
 317         ChipCmd         = 0x37,
 318         TxPoll          = 0x38,
 319         IntrMask        = 0x3c,
 320         IntrStatus      = 0x3e,
 321
 322         TxConfig        = 0x40,
 323 #define TXCFG_AUTO_FIFO                 (1 << 7)        /* 8111e-vl */
 324 #define TXCFG_EMPTY                     (1 << 11)       /* 8111e-vl */
 325
 326         RxConfig        = 0x44,
 327 #define RX128_INT_EN                    (1 << 15)       /* 8111c and later */
 328 #define RX_MULTI_EN                     (1 << 14)       /* 8111c only */
 329 #define RXCFG_FIFO_SHIFT                13
 330                                         /* No threshold before first PCI xfer */
 331 #define RX_FIFO_THRESH                  (7 << RXCFG_FIFO_SHIFT)
 332 #define RXCFG_DMA_SHIFT                 8
 333                                         /* Unlimited maximum PCI burst. */
 334 #define RX_DMA_BURST                    (7 << RXCFG_DMA_SHIFT)
 335
 336         RxMissed        = 0x4c,
 337         Cfg9346         = 0x50,
 338         Config0         = 0x51,
 339         Config1         = 0x52,
 340         Config2         = 0x53,
 341 #define PME_SIGNAL                      (1 << 5)        /* 8168c and later */
 342
 343         Config3         = 0x54,
 344         Config4         = 0x55,
 345         Config5         = 0x56,
 346         MultiIntr       = 0x5c,
 347         PHYAR           = 0x60,
 348         PHYstatus       = 0x6c,
 349         RxMaxSize       = 0xda,
 350         CPlusCmd        = 0xe0,
 351         IntrMitigate    = 0xe2,
 352         RxDescAddrLow   = 0xe4,
 353         RxDescAddrHigh  = 0xe8,
 354         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
 355
 356 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
 357
 358         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
 359
 360 #define TxPacketMax     (8064 >> 7)
 361 #define EarlySize       0x27
 362
 363         FuncEvent       = 0xf0,
 364         FuncEventMask   = 0xf4,
 365         FuncPresetState = 0xf8,
 366         FuncForceEvent  = 0xfc,
 367 };
 368
 369 enum rtl8110_registers {
 370         TBICSR                  = 0x64,
 371         TBI_ANAR                = 0x68,
 372         TBI_LPAR                = 0x6a,
 373 };
 374
 375 enum rtl8168_8101_registers {
 376         CSIDR                   = 0x64,
 377         CSIAR                   = 0x68,
 378 #define CSIAR_FLAG                      0x80000000
 379 #define CSIAR_WRITE_CMD                 0x80000000
 380 #define CSIAR_BYTE_ENABLE               0x0f
 381 #define CSIAR_BYTE_ENABLE_SHIFT         12
 382 #define CSIAR_ADDR_MASK                 0x0fff
 383 #define CSIAR_FUNC_CARD                 0x00000000
 384 #define CSIAR_FUNC_SDIO                 0x00010000
 385 #define CSIAR_FUNC_NIC                  0x00020000
 386         PMCH                    = 0x6f,
 387         EPHYAR                  = 0x80,
 388 #define EPHYAR_FLAG                     0x80000000
 389 #define EPHYAR_WRITE_CMD                0x80000000
 390 #define EPHYAR_REG_MASK                 0x1f
 391 #define EPHYAR_REG_SHIFT                16
 392 #define EPHYAR_DATA_MASK                0xffff
 393         DLLPR                   = 0xd0,
 394 #define PFM_EN                          (1 << 6)
 395         DBG_REG                 = 0xd1,
 396 #define FIX_NAK_1                       (1 << 4)
 397 #define FIX_NAK_2                       (1 << 3)
 398         TWSI                    = 0xd2,
 399         MCU                     = 0xd3,
 400 #define NOW_IS_OOB                      (1 << 7)
 401 #define TX_EMPTY                        (1 << 5)
 402 #define RX_EMPTY                        (1 << 4)
 403 #define RXTX_EMPTY                      (TX_EMPTY | RX_EMPTY)
 404 #define EN_NDP                          (1 << 3)
 405 #define EN_OOB_RESET                    (1 << 2)
 406 #define LINK_LIST_RDY                   (1 << 1)
 407         EFUSEAR                 = 0xdc,
 408 #define EFUSEAR_FLAG                    0x80000000
 409 #define EFUSEAR_WRITE_CMD               0x80000000
 410 #define EFUSEAR_READ_CMD                0x00000000
 411 #define EFUSEAR_REG_MASK                0x03ff
 412 #define EFUSEAR_REG_SHIFT               8
 413 #define EFUSEAR_DATA_MASK               0xff
 414 };
 415
 416 enum rtl8168_registers {
 417         LED_FREQ                = 0x1a,
 418         EEE_LED                 = 0x1b,
 419         ERIDR                   = 0x70,
 420         ERIAR                   = 0x74,
 421 #define ERIAR_FLAG                      0x80000000
 422 #define ERIAR_WRITE_CMD                 0x80000000
 423 #define ERIAR_READ_CMD                  0x00000000
 424 #define ERIAR_ADDR_BYTE_ALIGN           4
 425 #define ERIAR_TYPE_SHIFT                16
 426 #define ERIAR_EXGMAC                    (0x00 << ERIAR_TYPE_SHIFT)
 427 #define ERIAR_MSIX                      (0x01 << ERIAR_TYPE_SHIFT)
 428 #define ERIAR_ASF                       (0x02 << ERIAR_TYPE_SHIFT)
 429 #define ERIAR_MASK_SHIFT                12
 430 #define ERIAR_MASK_0001                 (0x1 << ERIAR_MASK_SHIFT)
 431 #define ERIAR_MASK_0011                 (0x3 << ERIAR_MASK_SHIFT)
 432 #define ERIAR_MASK_0101                 (0x5 << ERIAR_MASK_SHIFT)
 433 #define ERIAR_MASK_1111                 (0xf << ERIAR_MASK_SHIFT)
 434         EPHY_RXER_NUM           = 0x7c,
 435         OCPDR                   = 0xb0, /* OCP GPHY access */
 436 #define OCPDR_WRITE_CMD                 0x80000000
 437 #define OCPDR_READ_CMD                  0x00000000
 438 #define OCPDR_REG_MASK                  0x7f
 439 #define OCPDR_GPHY_REG_SHIFT            16
 440 #define OCPDR_DATA_MASK                 0xffff
 441         OCPAR                   = 0xb4,
 442 #define OCPAR_FLAG                      0x80000000
 443 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
 444 #define OCPAR_GPHY_READ_CMD             0x0000f060
 445         GPHY_OCP                = 0xb8,
 446         RDSAR1                  = 0xd0, /* 8168c only. Undocumented on 8168dp */
 447         MISC                    = 0xf0, /* 8168e only. */
 448 #define TXPLA_RST                       (1 << 29)
 449 #define DISABLE_LAN_EN                  (1 << 23) /* Enable GPIO pin */
 450 #define PWM_EN                          (1 << 22)
 451 #define RXDV_GATED_EN                   (1 << 19)
 452 #define EARLY_TALLY_EN                  (1 << 16)
 453 };
 454
 455 enum rtl_register_content {
 456         /* InterruptStatusBits */
 457         SYSErr          = 0x8000,
 458         PCSTimeout      = 0x4000,
 459         SWInt           = 0x0100,
 460         TxDescUnavail   = 0x0080,
 461         RxFIFOOver      = 0x0040,
 462         LinkChg         = 0x0020,
 463         RxOverflow      = 0x0010,
 464         TxErr           = 0x0008,
 465         TxOK            = 0x0004,
 466         RxErr           = 0x0002,
 467         RxOK            = 0x0001,
 468
 469         /* RxStatusDesc */
 470         RxBOVF  = (1 << 24),
 471         RxFOVF  = (1 << 23),
 472         RxRWT   = (1 << 22),
 473         RxRES   = (1 << 21),
 474         RxRUNT  = (1 << 20),
 475         RxCRC   = (1 << 19),
 476
 477         /* ChipCmdBits */
 478         StopReq         = 0x80,
 479         CmdReset        = 0x10,
 480         CmdRxEnb        = 0x08,
 481         CmdTxEnb        = 0x04,
 482         RxBufEmpty      = 0x01,
 483
 484         /* TXPoll register p.5 */
 485         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 486         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 487         FSWInt          = 0x01,         /* Forced software interrupt */
 488
 489         /* Cfg9346Bits */
 490         Cfg9346_Lock    = 0x00,
 491         Cfg9346_Unlock  = 0xc0,
 492
 493         /* rx_mode_bits */
 494         AcceptErr       = 0x20,
 495         AcceptRunt      = 0x10,
 496         AcceptBroadcast = 0x08,
 497         AcceptMulticast = 0x04,
 498         AcceptMyPhys    = 0x02,
 499         AcceptAllPhys   = 0x01,
 500 #define RX_CONFIG_ACCEPT_MASK           0x3f
 501
 502         /* TxConfigBits */
 503         TxInterFrameGapShift = 24,
 504         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 505
 506         /* Config1 register p.24 */
 507         LEDS1           = (1 << 7),
 508         LEDS0           = (1 << 6),
 509         Speed_down      = (1 << 4),
 510         MEMMAP          = (1 << 3),
 511         IOMAP           = (1 << 2),
 512         VPD             = (1 << 1),
 513         PMEnable        = (1 << 0),     /* Power Management Enable */
 514
 515         /* Config2 register p. 25 */
 516         MSIEnable       = (1 << 5),     /* 8169 only. Reserved in the 8168. */
 517         PCI_Clock_66MHz = 0x01,
 518         PCI_Clock_33MHz = 0x00,
 519
 520         /* Config3 register p.25 */
 521         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 522         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 523         Jumbo_En0       = (1 << 2),     /* 8168 only. Reserved in the 8168b */
 524         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
 525
 526         /* Config4 register */
 527         Jumbo_En1       = (1 << 1),     /* 8168 only. Reserved in the 8168b */
 528
 529         /* Config5 register p.27 */
 530         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 531         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 532         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 533         Spi_en          = (1 << 3),
 534         LanWake         = (1 << 1),     /* LanWake enable/disable */
 535         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 536
 537         /* TBICSR p.28 */
 538         TBIReset        = 0x80000000,
 539         TBILoopback     = 0x40000000,
 540         TBINwEnable     = 0x20000000,
 541         TBINwRestart    = 0x10000000,
 542         TBILinkOk       = 0x02000000,
 543         TBINwComplete   = 0x01000000,
 544
 545         /* CPlusCmd p.31 */
 546         EnableBist      = (1 << 15),    // 8168 8101
 547         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
 548         Normal_mode     = (1 << 13),    // unused
 549         Force_half_dup  = (1 << 12),    // 8168 8101
 550         Force_rxflow_en = (1 << 11),    // 8168 8101
 551         Force_txflow_en = (1 << 10),    // 8168 8101
 552         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
 553         ASF             = (1 << 8),     // 8168 8101
 554         PktCntrDisable  = (1 << 7),     // 8168 8101
 555         Mac_dbgo_sel    = 0x001c,       // 8168
 556         RxVlan          = (1 << 6),
 557         RxChkSum        = (1 << 5),
 558         PCIDAC          = (1 << 4),
 559         PCIMulRW        = (1 << 3),
 560         INTT_0          = 0x0000,       // 8168
 561         INTT_1          = 0x0001,       // 8168
 562         INTT_2          = 0x0002,       // 8168
 563         INTT_3          = 0x0003,       // 8168
 564
 565         /* rtl8169_PHYstatus */
 566         TBI_Enable      = 0x80,
 567         TxFlowCtrl      = 0x40,
 568         RxFlowCtrl      = 0x20,
 569         _1000bpsF       = 0x10,
 570         _100bps         = 0x08,
 571         _10bps          = 0x04,
 572         LinkStatus      = 0x02,
 573         FullDup         = 0x01,
 574
 575         /* _TBICSRBit */
 576         TBILinkOK       = 0x02000000,
 577
 578         /* DumpCounterCommand */
 579         CounterDump     = 0x8,
 580 };
 581
 582 enum rtl_desc_bit {
 583         /* First doubleword. */
 584         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 585         RingEnd         = (1 << 30), /* End of descriptor ring */
 586         FirstFrag       = (1 << 29), /* First segment of a packet */
 587         LastFrag        = (1 << 28), /* Final segment of a packet */
 588 };
 589
 590 /* Generic case. */
 591 enum rtl_tx_desc_bit {
 592         /* First doubleword. */
 593         TD_LSO          = (1 << 27),            /* Large Send Offload */
 594 #define TD_MSS_MAX                      0x07ffu /* MSS value */
 595
 596         /* Second doubleword. */
 597         TxVlanTag       = (1 << 17),            /* Add VLAN tag */
 598 };
 599
 600 /* 8169, 8168b and 810x except 8102e. */
 601 enum rtl_tx_desc_bit_0 {
 602         /* First doubleword. */
 603 #define TD0_MSS_SHIFT                   16      /* MSS position (11 bits) */
 604         TD0_TCP_CS      = (1 << 16),            /* Calculate TCP/IP checksum */
 605         TD0_UDP_CS      = (1 << 17),            /* Calculate UDP/IP checksum */
 606         TD0_IP_CS       = (1 << 18),            /* Calculate IP checksum */
 607 };
 608
 609 /* 8102e, 8168c and beyond. */
 610 enum rtl_tx_desc_bit_1 {
 611         /* Second doubleword. */
 612 #define TD1_MSS_SHIFT                   18      /* MSS position (11 bits) */
 613         TD1_IP_CS       = (1 << 29),            /* Calculate IP checksum */
 614         TD1_TCP_CS      = (1 << 30),            /* Calculate TCP/IP checksum */
 615         TD1_UDP_CS      = (1 << 31),            /* Calculate UDP/IP checksum */
 616 };
 617
 618 static const struct rtl_tx_desc_info {
 619         struct {
 620                 u32 udp;
 621                 u32 tcp;
 622         } checksum;
 623         u16 mss_shift;
 624         u16 opts_offset;
 625 } tx_desc_info [] = {
 626         [RTL_TD_0] = {
 627                 .checksum = {
 628                         .udp    = TD0_IP_CS | TD0_UDP_CS,
 629                         .tcp    = TD0_IP_CS | TD0_TCP_CS
 630                 },
 631                 .mss_shift      = TD0_MSS_SHIFT,
 632                 .opts_offset    = 0
 633         },
 634         [RTL_TD_1] = {
 635                 .checksum = {
 636                         .udp    = TD1_IP_CS | TD1_UDP_CS,
 637                         .tcp    = TD1_IP_CS | TD1_TCP_CS
 638                 },
 639                 .mss_shift      = TD1_MSS_SHIFT,
 640                 .opts_offset    = 1
 641         }
 642 };
 643
 644 enum rtl_rx_desc_bit {
 645         /* Rx private */
 646         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 647         PID0            = (1 << 17), /* Protocol ID bit 2/2 */
 648
 649 #define RxProtoUDP      (PID1)
 650 #define RxProtoTCP      (PID0)
 651 #define RxProtoIP       (PID1 | PID0)
 652 #define RxProtoMask     RxProtoIP
 653
 654         IPFail          = (1 << 16), /* IP checksum failed */
 655         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 656         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 657         RxVlanTag       = (1 << 16), /* VLAN tag available */
 658 };
 659
 660 #define RsvdMask        0x3fffc000
 661
 662 struct TxDesc {
 663         __le32 opts1;
 664         __le32 opts2;
 665         __le64 addr;
 666 };
 667
 668 struct RxDesc {
 669         __le32 opts1;
 670         __le32 opts2;
 671         __le64 addr;
 672 };
 673
 674 struct ring_info {
 675         struct sk_buff  *skb;
 676         u32             len;
 677         u8              __pad[sizeof(void *) - sizeof(u32)];
 678 };
 679
 680 enum features {
 681         RTL_FEATURE_WOL         = (1 << 0),
 682         RTL_FEATURE_MSI         = (1 << 1),
 683         RTL_FEATURE_GMII        = (1 << 2),
 684 };
 685
 686 struct rtl8169_counters {
 687         __le64  tx_packets;
 688         __le64  rx_packets;
 689         __le64  tx_errors;
 690         __le32  rx_errors;
 691         __le16  rx_missed;
 692         __le16  align_errors;
 693         __le32  tx_one_collision;
 694         __le32  tx_multi_collision;
 695         __le64  rx_unicast;
 696         __le64  rx_broadcast;
 697         __le32  rx_multicast;
 698         __le16  tx_aborted;
 699         __le16  tx_underun;
 700 };
 701
 702 enum rtl_flag {
 703         RTL_FLAG_TASK_ENABLED,
 704         RTL_FLAG_TASK_SLOW_PENDING,
 705         RTL_FLAG_TASK_RESET_PENDING,
 706         RTL_FLAG_TASK_PHY_PENDING,
 707         RTL_FLAG_MAX
 708 };
 709
 710 struct rtl8169_stats {
 711         u64                     packets;
 712         u64                     bytes;
 713         struct u64_stats_sync   syncp;
 714 };
 715
 716 struct rtl8169_private {
 717         void __iomem *mmio_addr;        /* memory map physical address */
 718         struct pci_dev *pci_dev;
 719         struct net_device *dev;
 720         struct napi_struct napi;
 721         u32 msg_enable;
 722         u16 txd_version;
 723         u16 mac_version;
 724         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 725         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 726         u32 dirty_tx;
 727         struct rtl8169_stats rx_stats;
 728         struct rtl8169_stats tx_stats;
 729         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 730         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 731         dma_addr_t TxPhyAddr;
 732         dma_addr_t RxPhyAddr;
 733         void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
 734         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 735         struct timer_list timer;
 736         u16 cp_cmd;
 737
 738         u16 event_slow;
 739
 740         struct mdio_ops {
 741                 void (*write)(struct rtl8169_private *, int, int);
 742                 int (*read)(struct rtl8169_private *, int);
 743         } mdio_ops;
 744
 745         struct pll_power_ops {
 746                 void (*down)(struct rtl8169_private *);
 747                 void (*up)(struct rtl8169_private *);
 748         } pll_power_ops;
 749
 750         struct jumbo_ops {
 751                 void (*enable)(struct rtl8169_private *);
 752                 void (*disable)(struct rtl8169_private *);
 753         } jumbo_ops;
 754
 755         struct csi_ops {
 756                 void (*write)(struct rtl8169_private *, int, int);
 757                 u32 (*read)(struct rtl8169_private *, int);
 758         } csi_ops;
 759
 760         int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
 761         int (*get_settings)(struct net_device *, struct ethtool_cmd *);
 762         void (*phy_reset_enable)(struct rtl8169_private *tp);
 763         void (*hw_start)(struct net_device *);
 764         unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
 765         unsigned int (*link_ok)(void __iomem *);
 766         int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
 767
 768         struct {
 769                 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
 770                 struct mutex mutex;
 771                 struct work_struct work;
 772         } wk;
 773
 774         unsigned features;
 775
 776         struct mii_if_info mii;
 777         struct rtl8169_counters counters;
 778         u32 saved_wolopts;
 779         u32 opts1_mask;
 780
 781         struct rtl_fw {
 782                 const struct firmware *fw;
 783
 784 #define RTL_VER_SIZE            32
 785
 786                 char version[RTL_VER_SIZE];
 787
 788                 struct rtl_fw_phy_action {
 789                         __le32 *code;
 790                         size_t size;
 791                 } phy_action;
 792         } *rtl_fw;
 793 #define RTL_FIRMWARE_UNKNOWN    ERR_PTR(-EAGAIN)
 794
 795         u32 ocp_base;
 796 };
 797
 798 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 799 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 800 module_param(use_dac, int, 0);
 801 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
 802 module_param_named(debug, debug.msg_enable, int, 0);
 803 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
 804 MODULE_LICENSE("GPL");
 805 MODULE_VERSION(RTL8169_VERSION);
 806 MODULE_FIRMWARE(FIRMWARE_8168D_1);
 807 MODULE_FIRMWARE(FIRMWARE_8168D_2);
 808 MODULE_FIRMWARE(FIRMWARE_8168E_1);
 809 MODULE_FIRMWARE(FIRMWARE_8168E_2);
 810 MODULE_FIRMWARE(FIRMWARE_8168E_3);
 811 MODULE_FIRMWARE(FIRMWARE_8105E_1);
 812 MODULE_FIRMWARE(FIRMWARE_8168F_1);
 813 MODULE_FIRMWARE(FIRMWARE_8168F_2);
 814 MODULE_FIRMWARE(FIRMWARE_8402_1);
 815 MODULE_FIRMWARE(FIRMWARE_8411_1);
 816 MODULE_FIRMWARE(FIRMWARE_8106E_1);
 817 MODULE_FIRMWARE(FIRMWARE_8168G_1);
 818
 819 static void rtl_lock_work(struct rtl8169_private *tp)
 820 {
 821         mutex_lock(&tp->wk.mutex);
 822 }
 823
 824 static void rtl_unlock_work(struct rtl8169_private *tp)
 825 {
 826         mutex_unlock(&tp->wk.mutex);
 827 }
 828
 829 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
 830 {
 831         pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL,
 832                                            PCI_EXP_DEVCTL_READRQ, force);
 833 }
 834
 835 struct rtl_cond {
 836         bool (*check)(struct rtl8169_private *);
 837         const char *msg;
 838 };
 839
 840 static void rtl_udelay(unsigned int d)
 841 {
 842         udelay(d);
 843 }
 844
 845 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
 846                           void (*delay)(unsigned int), unsigned int d, int n,
 847                           bool high)
 848 {
 849         int i;
 850
 851         for (i = 0; i < n; i++) {
 852                 delay(d);
 853                 if (c->check(tp) == high)
 854                         return true;
 855         }
 856         netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
 857                   c->msg, !high, n, d);
 858         return false;
 859 }
 860
 861 static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
 862                                       const struct rtl_cond *c,
 863                                       unsigned int d, int n)
 864 {
 865         return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
 866 }
 867
 868 static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
 869                                      const struct rtl_cond *c,
 870                                      unsigned int d, int n)
 871 {
 872         return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
 873 }
 874
 875 static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
 876                                       const struct rtl_cond *c,
 877                                       unsigned int d, int n)
 878 {
 879         return rtl_loop_wait(tp, c, msleep, d, n, true);
 880 }
 881
 882 static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
 883                                      const struct rtl_cond *c,
 884                                      unsigned int d, int n)
 885 {
 886         return rtl_loop_wait(tp, c, msleep, d, n, false);
 887 }
 888
 889 #define DECLARE_RTL_COND(name)                          \
 890 static bool name ## _check(struct rtl8169_private *);   \
 891                                                         \
 892 static const struct rtl_cond name = {                   \
 893         .check  = name ## _check,                       \
 894         .msg    = #name                                 \
 895 };                                                      \
 896                                                         \
 897 static bool name ## _check(struct rtl8169_private *tp)
 898
 899 DECLARE_RTL_COND(rtl_ocpar_cond)
 900 {
 901         void __iomem *ioaddr = tp->mmio_addr;
 902
 903         return RTL_R32(OCPAR) & OCPAR_FLAG;
 904 }
 905
 906 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
 907 {
 908         void __iomem *ioaddr = tp->mmio_addr;
 909
 910         RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
 911
 912         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
 913                 RTL_R32(OCPDR) : ~0;
 914 }
 915
 916 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
 917 {
 918         void __iomem *ioaddr = tp->mmio_addr;
 919
 920         RTL_W32(OCPDR, data);
 921         RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
 922
 923         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
 924 }
 925
 926 DECLARE_RTL_COND(rtl_eriar_cond)
 927 {
 928         void __iomem *ioaddr = tp->mmio_addr;
 929
 930         return RTL_R32(ERIAR) & ERIAR_FLAG;
 931 }
 932
 933 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
 934 {
 935         void __iomem *ioaddr = tp->mmio_addr;
 936
 937         RTL_W8(ERIDR, cmd);
 938         RTL_W32(ERIAR, 0x800010e8);
 939         msleep(2);
 940
 941         if (!rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 5))
 942                 return;
 943
 944         ocp_write(tp, 0x1, 0x30, 0x00000001);
 945 }
 946
 947 #define OOB_CMD_RESET           0x00
 948 #define OOB_CMD_DRIVER_START    0x05
 949 #define OOB_CMD_DRIVER_STOP     0x06
 950
 951 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
 952 {
 953         return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
 954 }
 955
 956 DECLARE_RTL_COND(rtl_ocp_read_cond)
 957 {
 958         u16 reg;
 959
 960         reg = rtl8168_get_ocp_reg(tp);
 961
 962         return ocp_read(tp, 0x0f, reg) & 0x00000800;
 963 }
 964
 965 static void rtl8168_driver_start(struct rtl8169_private *tp)
 966 {
 967         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
 968
 969         rtl_msleep_loop_wait_high(tp, &rtl_ocp_read_cond, 10, 10);
 970 }
 971
 972 static void rtl8168_driver_stop(struct rtl8169_private *tp)
 973 {
 974         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
 975
 976         rtl_msleep_loop_wait_low(tp, &rtl_ocp_read_cond, 10, 10);
 977 }
 978
 979 static int r8168dp_check_dash(struct rtl8169_private *tp)
 980 {
 981         u16 reg = rtl8168_get_ocp_reg(tp);
 982
 983         return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
 984 }
 985
 986 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
 987 {
 988         if (reg & 0xffff0001) {
 989                 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
 990                 return true;
 991         }
 992         return false;
 993 }
 994
 995 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
 996 {
 997         void __iomem *ioaddr = tp->mmio_addr;
 998
 999         return RTL_R32(GPHY_OCP) & OCPAR_FLAG;
1000 }
1001
1002 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
1003 {
1004         void __iomem *ioaddr = tp->mmio_addr;
1005
1006         if (rtl_ocp_reg_failure(tp, reg))
1007                 return;
1008
1009         RTL_W32(GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
1010
1011         rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
1012 }
1013
1014 static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
1015 {
1016         void __iomem *ioaddr = tp->mmio_addr;
1017
1018         if (rtl_ocp_reg_failure(tp, reg))
1019                 return 0;
1020
1021         RTL_W32(GPHY_OCP, reg << 15);
1022
1023         return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
1024                 (RTL_R32(GPHY_OCP) & 0xffff) : ~0;
1025 }
1026
1027 static void rtl_w1w0_phy_ocp(struct rtl8169_private *tp, int reg, int p, int m)
1028 {
1029         int val;
1030
1031         val = r8168_phy_ocp_read(tp, reg);
1032         r8168_phy_ocp_write(tp, reg, (val | p) & ~m);
1033 }
1034
1035 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
1036 {
1037         void __iomem *ioaddr = tp->mmio_addr;
1038
1039         if (rtl_ocp_reg_failure(tp, reg))
1040                 return;
1041
1042         RTL_W32(OCPDR, OCPAR_FLAG | (reg << 15) | data);
1043 }
1044
1045 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
1046 {
1047         void __iomem *ioaddr = tp->mmio_addr;
1048
1049         if (rtl_ocp_reg_failure(tp, reg))
1050                 return 0;
1051
1052         RTL_W32(OCPDR, reg << 15);
1053
1054         return RTL_R32(OCPDR);
1055 }
1056
1057 #define OCP_STD_PHY_BASE        0xa400
1058
1059 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
1060 {
1061         if (reg == 0x1f) {
1062                 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
1063                 return;
1064         }
1065
1066         if (tp->ocp_base != OCP_STD_PHY_BASE)
1067                 reg -= 0x10;
1068
1069         r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
1070 }
1071
1072 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
1073 {
1074         if (tp->ocp_base != OCP_STD_PHY_BASE)
1075                 reg -= 0x10;
1076
1077         return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
1078 }
1079
1080 DECLARE_RTL_COND(rtl_phyar_cond)
1081 {
1082         void __iomem *ioaddr = tp->mmio_addr;
1083
1084         return RTL_R32(PHYAR) & 0x80000000;
1085 }
1086
1087 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
1088 {
1089         void __iomem *ioaddr = tp->mmio_addr;
1090
1091         RTL_W32(PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
1092
1093         rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
1094         /*
1095          * According to hardware specs a 20us delay is required after write
1096          * complete indication, but before sending next command.
1097          */
1098         udelay(20);
1099 }
1100
1101 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
1102 {
1103         void __iomem *ioaddr = tp->mmio_addr;
1104         int value;
1105
1106         RTL_W32(PHYAR, 0x0 | (reg & 0x1f) << 16);
1107
1108         value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
1109                 RTL_R32(PHYAR) & 0xffff : ~0;
1110
1111         /*
1112          * According to hardware specs a 20us delay is required after read
1113          * complete indication, but before sending next command.
1114          */
1115         udelay(20);
1116
1117         return value;
1118 }
1119
1120 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
1121 {
1122         void __iomem *ioaddr = tp->mmio_addr;
1123
1124         RTL_W32(OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
1125         RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
1126         RTL_W32(EPHY_RXER_NUM, 0);
1127
1128         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
1129 }
1130
1131 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
1132 {
1133         r8168dp_1_mdio_access(tp, reg,
1134                               OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
1135 }
1136
1137 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
1138 {
1139         void __iomem *ioaddr = tp->mmio_addr;
1140
1141         r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
1142
1143         mdelay(1);
1144         RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
1145         RTL_W32(EPHY_RXER_NUM, 0);
1146
1147         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
1148                 RTL_R32(OCPDR) & OCPDR_DATA_MASK : ~0;
1149 }
1150
1151 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
1152
1153 static void r8168dp_2_mdio_start(void __iomem *ioaddr)
1154 {
1155         RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
1156 }
1157
1158 static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
1159 {
1160         RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
1161 }
1162
1163 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
1164 {
1165         void __iomem *ioaddr = tp->mmio_addr;
1166
1167         r8168dp_2_mdio_start(ioaddr);
1168
1169         r8169_mdio_write(tp, reg, value);
1170
1171         r8168dp_2_mdio_stop(ioaddr);
1172 }
1173
1174 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
1175 {
1176         void __iomem *ioaddr = tp->mmio_addr;
1177         int value;
1178
1179         r8168dp_2_mdio_start(ioaddr);
1180
1181         value = r8169_mdio_read(tp, reg);
1182
1183         r8168dp_2_mdio_stop(ioaddr);
1184
1185         return value;
1186 }
1187
1188 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
1189 {
1190         tp->mdio_ops.write(tp, location, val);
1191 }
1192
1193 static int rtl_readphy(struct rtl8169_private *tp, int location)
1194 {
1195         return tp->mdio_ops.read(tp, location);
1196 }
1197
1198 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1199 {
1200         rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1201 }
1202
1203 static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1204 {
1205         int val;
1206
1207         val = rtl_readphy(tp, reg_addr);
1208         rtl_writephy(tp, reg_addr, (val | p) & ~m);
1209 }
1210
1211 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
1212                            int val)
1213 {
1214         struct rtl8169_private *tp = netdev_priv(dev);
1215
1216         rtl_writephy(tp, location, val);
1217 }
1218
1219 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1220 {
1221         struct rtl8169_private *tp = netdev_priv(dev);
1222
1223         return rtl_readphy(tp, location);
1224 }
1225
1226 DECLARE_RTL_COND(rtl_ephyar_cond)
1227 {
1228         void __iomem *ioaddr = tp->mmio_addr;
1229
1230         return RTL_R32(EPHYAR) & EPHYAR_FLAG;
1231 }
1232
1233 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1234 {
1235         void __iomem *ioaddr = tp->mmio_addr;
1236
1237         RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1238                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1239
1240         rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1241
1242         udelay(10);
1243 }
1244
1245 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1246 {
1247         void __iomem *ioaddr = tp->mmio_addr;
1248
1249         RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1250
1251         return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1252                 RTL_R32(EPHYAR) & EPHYAR_DATA_MASK : ~0;
1253 }
1254
1255 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1256                           u32 val, int type)
1257 {
1258         void __iomem *ioaddr = tp->mmio_addr;
1259
1260         BUG_ON((addr & 3) || (mask == 0));
1261         RTL_W32(ERIDR, val);
1262         RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1263
1264         rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
1265 }
1266
1267 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
1268 {
1269         void __iomem *ioaddr = tp->mmio_addr;
1270
1271         RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1272
1273         return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1274                 RTL_R32(ERIDR) : ~0;
1275 }
1276
1277 static void rtl_w1w0_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1278                          u32 m, int type)
1279 {
1280         u32 val;
1281
1282         val = rtl_eri_read(tp, addr, type);
1283         rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
1284 }
1285
1286 struct exgmac_reg {
1287         u16 addr;
1288         u16 mask;
1289         u32 val;
1290 };
1291
1292 static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
1293                                    const struct exgmac_reg *r, int len)
1294 {
1295         while (len-- > 0) {
1296                 rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1297                 r++;
1298         }
1299 }
1300
1301 DECLARE_RTL_COND(rtl_efusear_cond)
1302 {
1303         void __iomem *ioaddr = tp->mmio_addr;
1304
1305         return RTL_R32(EFUSEAR) & EFUSEAR_FLAG;
1306 }
1307
1308 static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1309 {
1310         void __iomem *ioaddr = tp->mmio_addr;
1311
1312         RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1313
1314         return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1315                 RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1316 }
1317
1318 static u16 rtl_get_events(struct rtl8169_private *tp)
1319 {
1320         void __iomem *ioaddr = tp->mmio_addr;
1321
1322         return RTL_R16(IntrStatus);
1323 }
1324
1325 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1326 {
1327         void __iomem *ioaddr = tp->mmio_addr;
1328
1329         RTL_W16(IntrStatus, bits);
1330         mmiowb();
1331 }
1332
1333 static void rtl_irq_disable(struct rtl8169_private *tp)
1334 {
1335         void __iomem *ioaddr = tp->mmio_addr;
1336
1337         RTL_W16(IntrMask, 0);
1338         mmiowb();
1339 }
1340
1341 static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1342 {
1343         void __iomem *ioaddr = tp->mmio_addr;
1344
1345         RTL_W16(IntrMask, bits);
1346 }
1347
1348 #define RTL_EVENT_NAPI_RX       (RxOK | RxErr)
1349 #define RTL_EVENT_NAPI_TX       (TxOK | TxErr)
1350 #define RTL_EVENT_NAPI          (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1351
1352 static void rtl_irq_enable_all(struct rtl8169_private *tp)
1353 {
1354         rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1355 }
1356
1357 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1358 {
1359         void __iomem *ioaddr = tp->mmio_addr;
1360
1361         rtl_irq_disable(tp);
1362         rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
1363         RTL_R8(ChipCmd);
1364 }
1365
1366 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1367 {
1368         void __iomem *ioaddr = tp->mmio_addr;
1369
1370         return RTL_R32(TBICSR) & TBIReset;
1371 }
1372
1373 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1374 {
1375         return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1376 }
1377
1378 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1379 {
1380         return RTL_R32(TBICSR) & TBILinkOk;
1381 }
1382
1383 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1384 {
1385         return RTL_R8(PHYstatus) & LinkStatus;
1386 }
1387
1388 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1389 {
1390         void __iomem *ioaddr = tp->mmio_addr;
1391
1392         RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1393 }
1394
1395 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1396 {
1397         unsigned int val;
1398
1399         val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1400         rtl_writephy(tp, MII_BMCR, val & 0xffff);
1401 }
1402
1403 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1404 {
1405         void __iomem *ioaddr = tp->mmio_addr;
1406         struct net_device *dev = tp->dev;
1407
1408         if (!netif_running(dev))
1409                 return;
1410
1411         if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1412             tp->mac_version == RTL_GIGA_MAC_VER_38) {
1413                 if (RTL_R8(PHYstatus) & _1000bpsF) {
1414                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1415                                       ERIAR_EXGMAC);
1416                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1417                                       ERIAR_EXGMAC);
1418                 } else if (RTL_R8(PHYstatus) & _100bps) {
1419                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1420                                       ERIAR_EXGMAC);
1421                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1422                                       ERIAR_EXGMAC);
1423                 } else {
1424                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1425                                       ERIAR_EXGMAC);
1426                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1427                                       ERIAR_EXGMAC);
1428                 }
1429                 /* Reset packet filter */
1430                 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1431                              ERIAR_EXGMAC);
1432                 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1433                              ERIAR_EXGMAC);
1434         } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1435                    tp->mac_version == RTL_GIGA_MAC_VER_36) {
1436                 if (RTL_R8(PHYstatus) & _1000bpsF) {
1437                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1438                                       ERIAR_EXGMAC);
1439                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1440                                       ERIAR_EXGMAC);
1441                 } else {
1442                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1443                                       ERIAR_EXGMAC);
1444                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1445                                       ERIAR_EXGMAC);
1446                 }
1447         } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1448                 if (RTL_R8(PHYstatus) & _10bps) {
1449                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,
1450                                       ERIAR_EXGMAC);
1451                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,
1452                                       ERIAR_EXGMAC);
1453                 } else {
1454                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,
1455                                       ERIAR_EXGMAC);
1456                 }
1457         }
1458 }
1459
1460 static void __rtl8169_check_link_status(struct net_device *dev,
1461                                         struct rtl8169_private *tp,
1462                                         void __iomem *ioaddr, bool pm)
1463 {
1464         if (tp->link_ok(ioaddr)) {
1465                 rtl_link_chg_patch(tp);
1466                 /* This is to cancel a scheduled suspend if there's one. */
1467                 if (pm)
1468                         pm_request_resume(&tp->pci_dev->dev);
1469                 netif_carrier_on(dev);
1470                 if (net_ratelimit())
1471                         netif_info(tp, ifup, dev, "link up\n");
1472         } else {
1473                 netif_carrier_off(dev);
1474                 netif_info(tp, ifdown, dev, "link down\n");
1475                 if (pm)
1476                         pm_schedule_suspend(&tp->pci_dev->dev, 5000);
1477         }
1478 }
1479
1480 static void rtl8169_check_link_status(struct net_device *dev,
1481                                       struct rtl8169_private *tp,
1482                                       void __iomem *ioaddr)
1483 {
1484         __rtl8169_check_link_status(dev, tp, ioaddr, false);
1485 }
1486
1487 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1488
1489 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1490 {
1491         void __iomem *ioaddr = tp->mmio_addr;
1492         u8 options;
1493         u32 wolopts = 0;
1494
1495         options = RTL_R8(Config1);
1496         if (!(options & PMEnable))
1497                 return 0;
1498
1499         options = RTL_R8(Config3);
1500         if (options & LinkUp)
1501                 wolopts |= WAKE_PHY;
1502         if (options & MagicPacket)
1503                 wolopts |= WAKE_MAGIC;
1504
1505         options = RTL_R8(Config5);
1506         if (options & UWF)
1507                 wolopts |= WAKE_UCAST;
1508         if (options & BWF)
1509                 wolopts |= WAKE_BCAST;
1510         if (options & MWF)
1511                 wolopts |= WAKE_MCAST;
1512
1513         return wolopts;
1514 }
1515
1516 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1517 {
1518         struct rtl8169_private *tp = netdev_priv(dev);
1519
1520         rtl_lock_work(tp);
1521
1522         wol->supported = WAKE_ANY;
1523         wol->wolopts = __rtl8169_get_wol(tp);
1524
1525         rtl_unlock_work(tp);
1526 }
1527
1528 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1529 {
1530         void __iomem *ioaddr = tp->mmio_addr;
1531         unsigned int i;
1532         static const struct {
1533                 u32 opt;
1534                 u16 reg;
1535                 u8  mask;
1536         } cfg[] = {
1537                 { WAKE_PHY,   Config3, LinkUp },
1538                 { WAKE_MAGIC, Config3, MagicPacket },
1539                 { WAKE_UCAST, Config5, UWF },
1540                 { WAKE_BCAST, Config5, BWF },
1541                 { WAKE_MCAST, Config5, MWF },
1542                 { WAKE_ANY,   Config5, LanWake }
1543         };
1544         u8 options;
1545
1546         RTL_W8(Cfg9346, Cfg9346_Unlock);
1547
1548         for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1549                 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
1550                 if (wolopts & cfg[i].opt)
1551                         options |= cfg[i].mask;
1552                 RTL_W8(cfg[i].reg, options);
1553         }
1554
1555         switch (tp->mac_version) {
1556         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1557                 options = RTL_R8(Config1) & ~PMEnable;
1558                 if (wolopts)
1559                         options |= PMEnable;
1560                 RTL_W8(Config1, options);
1561                 break;
1562         default:
1563                 options = RTL_R8(Config2) & ~PME_SIGNAL;
1564                 if (wolopts)
1565                         options |= PME_SIGNAL;
1566                 RTL_W8(Config2, options);
1567                 break;
1568         }
1569
1570         RTL_W8(Cfg9346, Cfg9346_Lock);
1571 }
1572
1573 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1574 {
1575         struct rtl8169_private *tp = netdev_priv(dev);
1576
1577         rtl_lock_work(tp);
1578
1579         if (wol->wolopts)
1580                 tp->features |= RTL_FEATURE_WOL;
1581         else
1582                 tp->features &= ~RTL_FEATURE_WOL;
1583         __rtl8169_set_wol(tp, wol->wolopts);
1584
1585         rtl_unlock_work(tp);
1586
1587         device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1588
1589         return 0;
1590 }
1591
1592 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1593 {
1594         return rtl_chip_infos[tp->mac_version].fw_name;
1595 }
1596
1597 static void rtl8169_get_drvinfo(struct net_device *dev,
1598                                 struct ethtool_drvinfo *info)
1599 {
1600         struct rtl8169_private *tp = netdev_priv(dev);
1601         struct rtl_fw *rtl_fw = tp->rtl_fw;
1602
1603         strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1604         strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
1605         strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1606         BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1607         if (!IS_ERR_OR_NULL(rtl_fw))
1608                 strlcpy(info->fw_version, rtl_fw->version,
1609                         sizeof(info->fw_version));
1610 }
1611
1612 static int rtl8169_get_regs_len(struct net_device *dev)
1613 {
1614         return R8169_REGS_SIZE;
1615 }
1616
1617 static int rtl8169_set_speed_tbi(struct net_device *dev,
1618                                  u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1619 {
1620         struct rtl8169_private *tp = netdev_priv(dev);
1621         void __iomem *ioaddr = tp->mmio_addr;
1622         int ret = 0;
1623         u32 reg;
1624
1625         reg = RTL_R32(TBICSR);
1626         if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1627             (duplex == DUPLEX_FULL)) {
1628                 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1629         } else if (autoneg == AUTONEG_ENABLE)
1630                 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1631         else {
1632                 netif_warn(tp, link, dev,
1633                            "incorrect speed setting refused in TBI mode\n");
1634                 ret = -EOPNOTSUPP;
1635         }
1636
1637         return ret;
1638 }
1639
1640 static int rtl8169_set_speed_xmii(struct net_device *dev,
1641                                   u8 autoneg, u16 speed, u8 duplex, u32 adv)
1642 {
1643         struct rtl8169_private *tp = netdev_priv(dev);
1644         int giga_ctrl, bmcr;
1645         int rc = -EINVAL;
1646
1647         rtl_writephy(tp, 0x1f, 0x0000);
1648
1649         if (autoneg == AUTONEG_ENABLE) {
1650                 int auto_nego;
1651
1652                 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1653                 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1654                                 ADVERTISE_100HALF | ADVERTISE_100FULL);
1655
1656                 if (adv & ADVERTISED_10baseT_Half)
1657                         auto_nego |= ADVERTISE_10HALF;
1658                 if (adv & ADVERTISED_10baseT_Full)
1659                         auto_nego |= ADVERTISE_10FULL;
1660                 if (adv & ADVERTISED_100baseT_Half)
1661                         auto_nego |= ADVERTISE_100HALF;
1662                 if (adv & ADVERTISED_100baseT_Full)
1663                         auto_nego |= ADVERTISE_100FULL;
1664
1665                 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1666
1667                 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1668                 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1669
1670                 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1671                 if (tp->mii.supports_gmii) {
1672                         if (adv & ADVERTISED_1000baseT_Half)
1673                                 giga_ctrl |= ADVERTISE_1000HALF;
1674                         if (adv & ADVERTISED_1000baseT_Full)
1675                                 giga_ctrl |= ADVERTISE_1000FULL;
1676                 } else if (adv & (ADVERTISED_1000baseT_Half |
1677                                   ADVERTISED_1000baseT_Full)) {
1678                         netif_info(tp, link, dev,
1679                                    "PHY does not support 1000Mbps\n");
1680                         goto out;
1681                 }
1682
1683                 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1684
1685                 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1686                 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1687         } else {
1688                 giga_ctrl = 0;
1689
1690                 if (speed == SPEED_10)
1691                         bmcr = 0;
1692                 else if (speed == SPEED_100)
1693                         bmcr = BMCR_SPEED100;
1694                 else
1695                         goto out;
1696
1697                 if (duplex == DUPLEX_FULL)
1698                         bmcr |= BMCR_FULLDPLX;
1699         }
1700
1701         rtl_writephy(tp, MII_BMCR, bmcr);
1702
1703         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1704             tp->mac_version == RTL_GIGA_MAC_VER_03) {
1705                 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1706                         rtl_writephy(tp, 0x17, 0x2138);
1707                         rtl_writephy(tp, 0x0e, 0x0260);
1708                 } else {
1709                         rtl_writephy(tp, 0x17, 0x2108);
1710                         rtl_writephy(tp, 0x0e, 0x0000);
1711                 }
1712         }
1713
1714         rc = 0;
1715 out:
1716         return rc;
1717 }
1718
1719 static int rtl8169_set_speed(struct net_device *dev,
1720                              u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1721 {
1722         struct rtl8169_private *tp = netdev_priv(dev);
1723         int ret;
1724
1725         ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
1726         if (ret < 0)
1727                 goto out;
1728
1729         if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1730             (advertising & ADVERTISED_1000baseT_Full)) {
1731                 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1732         }
1733 out:
1734         return ret;
1735 }
1736
1737 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1738 {
1739         struct rtl8169_private *tp = netdev_priv(dev);
1740         int ret;
1741
1742         del_timer_sync(&tp->timer);
1743
1744         rtl_lock_work(tp);
1745         ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
1746                                 cmd->duplex, cmd->advertising);
1747         rtl_unlock_work(tp);
1748
1749         return ret;
1750 }
1751
1752 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1753         netdev_features_t features)
1754 {
1755         struct rtl8169_private *tp = netdev_priv(dev);
1756
1757         if (dev->mtu > TD_MSS_MAX)
1758                 features &= ~NETIF_F_ALL_TSO;
1759
1760         if (dev->mtu > JUMBO_1K &&
1761             !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
1762                 features &= ~NETIF_F_IP_CSUM;
1763
1764         return features;
1765 }
1766
1767 static void __rtl8169_set_features(struct net_device *dev,
1768                                    netdev_features_t features)
1769 {
1770         struct rtl8169_private *tp = netdev_priv(dev);
1771         netdev_features_t changed = features ^ dev->features;
1772         void __iomem *ioaddr = tp->mmio_addr;
1773
1774         if (!(changed & (NETIF_F_RXALL | NETIF_F_RXCSUM | NETIF_F_HW_VLAN_RX)))
1775                 return;
1776
1777         if (changed & (NETIF_F_RXCSUM | NETIF_F_HW_VLAN_RX)) {
1778                 if (features & NETIF_F_RXCSUM)
1779                         tp->cp_cmd |= RxChkSum;
1780                 else
1781                         tp->cp_cmd &= ~RxChkSum;
1782
1783                 if (dev->features & NETIF_F_HW_VLAN_RX)
1784                         tp->cp_cmd |= RxVlan;
1785                 else
1786                         tp->cp_cmd &= ~RxVlan;
1787
1788                 RTL_W16(CPlusCmd, tp->cp_cmd);
1789                 RTL_R16(CPlusCmd);
1790         }
1791         if (changed & NETIF_F_RXALL) {
1792                 int tmp = (RTL_R32(RxConfig) & ~(AcceptErr | AcceptRunt));
1793                 if (features & NETIF_F_RXALL)
1794                         tmp |= (AcceptErr | AcceptRunt);
1795                 RTL_W32(RxConfig, tmp);
1796         }
1797 }
1798
1799 static int rtl8169_set_features(struct net_device *dev,
1800                                 netdev_features_t features)
1801 {
1802         struct rtl8169_private *tp = netdev_priv(dev);
1803
1804         rtl_lock_work(tp);
1805         __rtl8169_set_features(dev, features);
1806         rtl_unlock_work(tp);
1807
1808         return 0;
1809 }
1810
1811
1812 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1813 {
1814         return (vlan_tx_tag_present(skb)) ?
1815                 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1816 }
1817
1818 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1819 {
1820         u32 opts2 = le32_to_cpu(desc->opts2);
1821
1822         if (opts2 & RxVlanTag)
1823                 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
1824 }
1825
1826 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1827 {
1828         struct rtl8169_private *tp = netdev_priv(dev);
1829         void __iomem *ioaddr = tp->mmio_addr;
1830         u32 status;
1831
1832         cmd->supported =
1833                 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1834         cmd->port = PORT_FIBRE;
1835         cmd->transceiver = XCVR_INTERNAL;
1836
1837         status = RTL_R32(TBICSR);
1838         cmd->advertising = (status & TBINwEnable) ?  ADVERTISED_Autoneg : 0;
1839         cmd->autoneg = !!(status & TBINwEnable);
1840
1841         ethtool_cmd_speed_set(cmd, SPEED_1000);
1842         cmd->duplex = DUPLEX_FULL; /* Always set */
1843
1844         return 0;
1845 }
1846
1847 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1848 {
1849         struct rtl8169_private *tp = netdev_priv(dev);
1850
1851         return mii_ethtool_gset(&tp->mii, cmd);
1852 }
1853
1854 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1855 {
1856         struct rtl8169_private *tp = netdev_priv(dev);
1857         int rc;
1858
1859         rtl_lock_work(tp);
1860         rc = tp->get_settings(dev, cmd);
1861         rtl_unlock_work(tp);
1862
1863         return rc;
1864 }
1865
1866 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1867                              void *p)
1868 {
1869         struct rtl8169_private *tp = netdev_priv(dev);
1870
1871         if (regs->len > R8169_REGS_SIZE)
1872                 regs->len = R8169_REGS_SIZE;
1873
1874         rtl_lock_work(tp);
1875         memcpy_fromio(p, tp->mmio_addr, regs->len);
1876         rtl_unlock_work(tp);
1877 }
1878
1879 static u32 rtl8169_get_msglevel(struct net_device *dev)
1880 {
1881         struct rtl8169_private *tp = netdev_priv(dev);
1882
1883         return tp->msg_enable;
1884 }
1885
1886 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1887 {
1888         struct rtl8169_private *tp = netdev_priv(dev);
1889
1890         tp->msg_enable = value;
1891 }
1892
1893 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1894         "tx_packets",
1895         "rx_packets",
1896         "tx_errors",
1897         "rx_errors",
1898         "rx_missed",
1899         "align_errors",
1900         "tx_single_collisions",
1901         "tx_multi_collisions",
1902         "unicast",
1903         "broadcast",
1904         "multicast",
1905         "tx_aborted",
1906         "tx_underrun",
1907 };
1908
1909 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1910 {
1911         switch (sset) {
1912         case ETH_SS_STATS:
1913                 return ARRAY_SIZE(rtl8169_gstrings);
1914         default:
1915                 return -EOPNOTSUPP;
1916         }
1917 }
1918
1919 DECLARE_RTL_COND(rtl_counters_cond)
1920 {
1921         void __iomem *ioaddr = tp->mmio_addr;
1922
1923         return RTL_R32(CounterAddrLow) & CounterDump;
1924 }
1925
1926 static void rtl8169_update_counters(struct net_device *dev)
1927 {
1928         struct rtl8169_private *tp = netdev_priv(dev);
1929         void __iomem *ioaddr = tp->mmio_addr;
1930         struct device *d = &tp->pci_dev->dev;
1931         struct rtl8169_counters *counters;
1932         dma_addr_t paddr;
1933         u32 cmd;
1934
1935         /*
1936          * Some chips are unable to dump tally counters when the receiver
1937          * is disabled.
1938          */
1939         if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1940                 return;
1941
1942         counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
1943         if (!counters)
1944                 return;
1945
1946         RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1947         cmd = (u64)paddr & DMA_BIT_MASK(32);
1948         RTL_W32(CounterAddrLow, cmd);
1949         RTL_W32(CounterAddrLow, cmd | CounterDump);
1950
1951         if (rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000))
1952                 memcpy(&tp->counters, counters, sizeof(*counters));
1953
1954         RTL_W32(CounterAddrLow, 0);
1955         RTL_W32(CounterAddrHigh, 0);
1956
1957         dma_free_coherent(d, sizeof(*counters), counters, paddr);
1958 }
1959
1960 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1961                                       struct ethtool_stats *stats, u64 *data)
1962 {
1963         struct rtl8169_private *tp = netdev_priv(dev);
1964
1965         ASSERT_RTNL();
1966
1967         rtl8169_update_counters(dev);
1968
1969         data[0] = le64_to_cpu(tp->counters.tx_packets);
1970         data[1] = le64_to_cpu(tp->counters.rx_packets);
1971         data[2] = le64_to_cpu(tp->counters.tx_errors);
1972         data[3] = le32_to_cpu(tp->counters.rx_errors);
1973         data[4] = le16_to_cpu(tp->counters.rx_missed);
1974         data[5] = le16_to_cpu(tp->counters.align_errors);
1975         data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1976         data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1977         data[8] = le64_to_cpu(tp->counters.rx_unicast);
1978         data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1979         data[10] = le32_to_cpu(tp->counters.rx_multicast);
1980         data[11] = le16_to_cpu(tp->counters.tx_aborted);
1981         data[12] = le16_to_cpu(tp->counters.tx_underun);
1982 }
1983
1984 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1985 {
1986         switch(stringset) {
1987         case ETH_SS_STATS:
1988                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1989                 break;
1990         }
1991 }
1992
1993 static const struct ethtool_ops rtl8169_ethtool_ops = {
1994         .get_drvinfo            = rtl8169_get_drvinfo,
1995         .get_regs_len           = rtl8169_get_regs_len,
1996         .get_link               = ethtool_op_get_link,
1997         .get_settings           = rtl8169_get_settings,
1998         .set_settings           = rtl8169_set_settings,
1999         .get_msglevel           = rtl8169_get_msglevel,
2000         .set_msglevel           = rtl8169_set_msglevel,
2001         .get_regs               = rtl8169_get_regs,
2002         .get_wol                = rtl8169_get_wol,
2003         .set_wol                = rtl8169_set_wol,
2004         .get_strings            = rtl8169_get_strings,
2005         .get_sset_count         = rtl8169_get_sset_count,
2006         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
2007         .get_ts_info            = ethtool_op_get_ts_info,
2008 };
2009
2010 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
2011                                     struct net_device *dev, u8 default_version)
2012 {
2013         void __iomem *ioaddr = tp->mmio_addr;
2014         /*
2015          * The driver currently handles the 8168Bf and the 8168Be identically
2016          * but they can be identified more specifically through the test below
2017          * if needed:
2018          *
2019          * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2020          *
2021          * Same thing for the 8101Eb and the 8101Ec:
2022          *
2023          * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2024          */
2025         static const struct rtl_mac_info {
2026                 u32 mask;
2027                 u32 val;
2028                 int mac_version;
2029         } mac_info[] = {
2030                 /* 8168G family. */
2031                 { 0x7cf00000, 0x4c100000,       RTL_GIGA_MAC_VER_41 },
2032                 { 0x7cf00000, 0x4c000000,       RTL_GIGA_MAC_VER_40 },
2033
2034                 /* 8168F family. */
2035                 { 0x7c800000, 0x48800000,       RTL_GIGA_MAC_VER_38 },
2036                 { 0x7cf00000, 0x48100000,       RTL_GIGA_MAC_VER_36 },
2037                 { 0x7cf00000, 0x48000000,       RTL_GIGA_MAC_VER_35 },
2038
2039                 /* 8168E family. */
2040                 { 0x7c800000, 0x2c800000,       RTL_GIGA_MAC_VER_34 },
2041                 { 0x7cf00000, 0x2c200000,       RTL_GIGA_MAC_VER_33 },
2042                 { 0x7cf00000, 0x2c100000,       RTL_GIGA_MAC_VER_32 },
2043                 { 0x7c800000, 0x2c000000,       RTL_GIGA_MAC_VER_33 },
2044
2045                 /* 8168D family. */
2046                 { 0x7cf00000, 0x28300000,       RTL_GIGA_MAC_VER_26 },
2047                 { 0x7cf00000, 0x28100000,       RTL_GIGA_MAC_VER_25 },
2048                 { 0x7c800000, 0x28000000,       RTL_GIGA_MAC_VER_26 },
2049
2050                 /* 8168DP family. */
2051                 { 0x7cf00000, 0x28800000,       RTL_GIGA_MAC_VER_27 },
2052                 { 0x7cf00000, 0x28a00000,       RTL_GIGA_MAC_VER_28 },
2053                 { 0x7cf00000, 0x28b00000,       RTL_GIGA_MAC_VER_31 },
2054
2055                 /* 8168C family. */
2056                 { 0x7cf00000, 0x3cb00000,       RTL_GIGA_MAC_VER_24 },
2057                 { 0x7cf00000, 0x3c900000,       RTL_GIGA_MAC_VER_23 },
2058                 { 0x7cf00000, 0x3c800000,       RTL_GIGA_MAC_VER_18 },
2059                 { 0x7c800000, 0x3c800000,       RTL_GIGA_MAC_VER_24 },
2060                 { 0x7cf00000, 0x3c000000,       RTL_GIGA_MAC_VER_19 },
2061                 { 0x7cf00000, 0x3c200000,       RTL_GIGA_MAC_VER_20 },
2062                 { 0x7cf00000, 0x3c300000,       RTL_GIGA_MAC_VER_21 },
2063                 { 0x7cf00000, 0x3c400000,       RTL_GIGA_MAC_VER_22 },
2064                 { 0x7c800000, 0x3c000000,       RTL_GIGA_MAC_VER_22 },
2065
2066                 /* 8168B family. */
2067                 { 0x7cf00000, 0x38000000,       RTL_GIGA_MAC_VER_12 },
2068                 { 0x7cf00000, 0x38500000,       RTL_GIGA_MAC_VER_17 },
2069                 { 0x7c800000, 0x38000000,       RTL_GIGA_MAC_VER_17 },
2070                 { 0x7c800000, 0x30000000,       RTL_GIGA_MAC_VER_11 },
2071
2072                 /* 8101 family. */
2073                 { 0x7cf00000, 0x44900000,       RTL_GIGA_MAC_VER_39 },
2074                 { 0x7c800000, 0x44800000,       RTL_GIGA_MAC_VER_39 },
2075                 { 0x7c800000, 0x44000000,       RTL_GIGA_MAC_VER_37 },
2076                 { 0x7cf00000, 0x40b00000,       RTL_GIGA_MAC_VER_30 },
2077                 { 0x7cf00000, 0x40a00000,       RTL_GIGA_MAC_VER_30 },
2078                 { 0x7cf00000, 0x40900000,       RTL_GIGA_MAC_VER_29 },
2079                 { 0x7c800000, 0x40800000,       RTL_GIGA_MAC_VER_30 },
2080                 { 0x7cf00000, 0x34a00000,       RTL_GIGA_MAC_VER_09 },
2081                 { 0x7cf00000, 0x24a00000,       RTL_GIGA_MAC_VER_09 },
2082                 { 0x7cf00000, 0x34900000,       RTL_GIGA_MAC_VER_08 },
2083                 { 0x7cf00000, 0x24900000,       RTL_GIGA_MAC_VER_08 },
2084                 { 0x7cf00000, 0x34800000,       RTL_GIGA_MAC_VER_07 },
2085                 { 0x7cf00000, 0x24800000,       RTL_GIGA_MAC_VER_07 },
2086                 { 0x7cf00000, 0x34000000,       RTL_GIGA_MAC_VER_13 },
2087                 { 0x7cf00000, 0x34300000,       RTL_GIGA_MAC_VER_10 },
2088                 { 0x7cf00000, 0x34200000,       RTL_GIGA_MAC_VER_16 },
2089                 { 0x7c800000, 0x34800000,       RTL_GIGA_MAC_VER_09 },
2090                 { 0x7c800000, 0x24800000,       RTL_GIGA_MAC_VER_09 },
2091                 { 0x7c800000, 0x34000000,       RTL_GIGA_MAC_VER_16 },
2092                 /* FIXME: where did these entries come from ? -- FR */
2093                 { 0xfc800000, 0x38800000,       RTL_GIGA_MAC_VER_15 },
2094                 { 0xfc800000, 0x30800000,       RTL_GIGA_MAC_VER_14 },
2095
2096                 /* 8110 family. */
2097                 { 0xfc800000, 0x98000000,       RTL_GIGA_MAC_VER_06 },
2098                 { 0xfc800000, 0x18000000,       RTL_GIGA_MAC_VER_05 },
2099                 { 0xfc800000, 0x10000000,       RTL_GIGA_MAC_VER_04 },
2100                 { 0xfc800000, 0x04000000,       RTL_GIGA_MAC_VER_03 },
2101                 { 0xfc800000, 0x00800000,       RTL_GIGA_MAC_VER_02 },
2102                 { 0xfc800000, 0x00000000,       RTL_GIGA_MAC_VER_01 },
2103
2104                 /* Catch-all */
2105                 { 0x00000000, 0x00000000,       RTL_GIGA_MAC_NONE   }
2106         };
2107         const struct rtl_mac_info *p = mac_info;
2108         u32 reg;
2109
2110         reg = RTL_R32(TxConfig);
2111         while ((reg & p->mask) != p->val)
2112                 p++;
2113         tp->mac_version = p->mac_version;
2114
2115         if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2116                 netif_notice(tp, probe, dev,
2117                              "unknown MAC, using family default\n");
2118                 tp->mac_version = default_version;
2119         }
2120 }
2121
2122 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
2123 {
2124         dprintk("mac_version = 0x%02x\n", tp->mac_version);
2125 }
2126
2127 struct phy_reg {
2128         u16 reg;
2129         u16 val;
2130 };
2131
2132 static void rtl_writephy_batch(struct rtl8169_private *tp,
2133                                const struct phy_reg *regs, int len)
2134 {
2135         while (len-- > 0) {
2136                 rtl_writephy(tp, regs->reg, regs->val);
2137                 regs++;
2138         }
2139 }
2140
2141 #define PHY_READ                0x00000000
2142 #define PHY_DATA_OR             0x10000000
2143 #define PHY_DATA_AND            0x20000000
2144 #define PHY_BJMPN               0x30000000
2145 #define PHY_READ_EFUSE          0x40000000
2146 #define PHY_READ_MAC_BYTE       0x50000000
2147 #define PHY_WRITE_MAC_BYTE      0x60000000
2148 #define PHY_CLEAR_READCOUNT     0x70000000
2149 #define PHY_WRITE               0x80000000
2150 #define PHY_READCOUNT_EQ_SKIP   0x90000000
2151 #define PHY_COMP_EQ_SKIPN       0xa0000000
2152 #define PHY_COMP_NEQ_SKIPN      0xb0000000
2153 #define PHY_WRITE_PREVIOUS      0xc0000000
2154 #define PHY_SKIPN               0xd0000000
2155 #define PHY_DELAY_MS            0xe0000000
2156 #define PHY_WRITE_ERI_WORD      0xf0000000
2157
2158 struct fw_info {
2159         u32     magic;
2160         char    version[RTL_VER_SIZE];
2161         __le32  fw_start;
2162         __le32  fw_len;
2163         u8      chksum;
2164 } __packed;
2165
2166 #define FW_OPCODE_SIZE  sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2167
2168 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2169 {
2170         const struct firmware *fw = rtl_fw->fw;
2171         struct fw_info *fw_info = (struct fw_info *)fw->data;
2172         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2173         char *version = rtl_fw->version;
2174         bool rc = false;
2175
2176         if (fw->size < FW_OPCODE_SIZE)
2177                 goto out;
2178
2179         if (!fw_info->magic) {
2180                 size_t i, size, start;
2181                 u8 checksum = 0;
2182
2183                 if (fw->size < sizeof(*fw_info))
2184                         goto out;
2185
2186                 for (i = 0; i < fw->size; i++)
2187                         checksum += fw->data[i];
2188                 if (checksum != 0)
2189                         goto out;
2190
2191                 start = le32_to_cpu(fw_info->fw_start);
2192                 if (start > fw->size)
2193                         goto out;
2194
2195                 size = le32_to_cpu(fw_info->fw_len);
2196                 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2197                         goto out;
2198
2199                 memcpy(version, fw_info->version, RTL_VER_SIZE);
2200
2201                 pa->code = (__le32 *)(fw->data + start);
2202                 pa->size = size;
2203         } else {
2204                 if (fw->size % FW_OPCODE_SIZE)
2205                         goto out;
2206
2207                 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2208
2209                 pa->code = (__le32 *)fw->data;
2210                 pa->size = fw->size / FW_OPCODE_SIZE;
2211         }
2212         version[RTL_VER_SIZE - 1] = 0;
2213
2214         rc = true;
2215 out:
2216         return rc;
2217 }
2218
2219 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2220                            struct rtl_fw_phy_action *pa)
2221 {
2222         bool rc = false;
2223         size_t index;
2224
2225         for (index = 0; index < pa->size; index++) {
2226                 u32 action = le32_to_cpu(pa->code[index]);
2227                 u32 regno = (action & 0x0fff0000) >> 16;
2228
2229                 switch(action & 0xf0000000) {
2230                 case PHY_READ:
2231                 case PHY_DATA_OR:
2232                 case PHY_DATA_AND:
2233                 case PHY_READ_EFUSE:
2234                 case PHY_CLEAR_READCOUNT:
2235                 case PHY_WRITE:
2236                 case PHY_WRITE_PREVIOUS:
2237                 case PHY_DELAY_MS:
2238                         break;
2239
2240                 case PHY_BJMPN:
2241                         if (regno > index) {
2242                                 netif_err(tp, ifup, tp->dev,
2243                                           "Out of range of firmware\n");
2244                                 goto out;
2245                         }
2246                         break;
2247                 case PHY_READCOUNT_EQ_SKIP:
2248                         if (index + 2 >= pa->size) {
2249                                 netif_err(tp, ifup, tp->dev,
2250                                           "Out of range of firmware\n");
2251                                 goto out;
2252                         }
2253                         break;
2254                 case PHY_COMP_EQ_SKIPN:
2255                 case PHY_COMP_NEQ_SKIPN:
2256                 case PHY_SKIPN:
2257                         if (index + 1 + regno >= pa->size) {
2258                                 netif_err(tp, ifup, tp->dev,
2259                                           "Out of range of firmware\n");
2260                                 goto out;
2261                         }
2262                         break;
2263
2264                 case PHY_READ_MAC_BYTE:
2265                 case PHY_WRITE_MAC_BYTE:
2266                 case PHY_WRITE_ERI_WORD:
2267                 default:
2268                         netif_err(tp, ifup, tp->dev,
2269                                   "Invalid action 0x%08x\n", action);
2270                         goto out;
2271                 }
2272         }
2273         rc = true;
2274 out:
2275         return rc;
2276 }
2277
2278 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2279 {
2280         struct net_device *dev = tp->dev;
2281         int rc = -EINVAL;
2282
2283         if (!rtl_fw_format_ok(tp, rtl_fw)) {
2284                 netif_err(tp, ifup, dev, "invalid firwmare\n");
2285                 goto out;
2286         }
2287
2288         if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2289                 rc = 0;
2290 out:
2291         return rc;
2292 }
2293
2294 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2295 {
2296         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2297         u32 predata, count;
2298         size_t index;
2299
2300         predata = count = 0;
2301
2302         for (index = 0; index < pa->size; ) {
2303                 u32 action = le32_to_cpu(pa->code[index]);
2304                 u32 data = action & 0x0000ffff;
2305                 u32 regno = (action & 0x0fff0000) >> 16;
2306
2307                 if (!action)
2308                         break;
2309
2310                 switch(action & 0xf0000000) {
2311                 case PHY_READ:
2312                         predata = rtl_readphy(tp, regno);
2313                         count++;
2314                         index++;
2315                         break;
2316                 case PHY_DATA_OR:
2317                         predata |= data;
2318                         index++;
2319                         break;
2320                 case PHY_DATA_AND:
2321                         predata &= data;
2322                         index++;
2323                         break;
2324                 case PHY_BJMPN:
2325                         index -= regno;
2326                         break;
2327                 case PHY_READ_EFUSE:
2328                         predata = rtl8168d_efuse_read(tp, regno);
2329                         index++;
2330                         break;
2331                 case PHY_CLEAR_READCOUNT:
2332                         count = 0;
2333                         index++;
2334                         break;
2335                 case PHY_WRITE:
2336                         rtl_writephy(tp, regno, data);
2337                         index++;
2338                         break;
2339                 case PHY_READCOUNT_EQ_SKIP:
2340                         index += (count == data) ? 2 : 1;
2341                         break;
2342                 case PHY_COMP_EQ_SKIPN:
2343                         if (predata == data)
2344                                 index += regno;
2345                         index++;
2346                         break;
2347                 case PHY_COMP_NEQ_SKIPN:
2348                         if (predata != data)
2349                                 index += regno;
2350                         index++;
2351                         break;
2352                 case PHY_WRITE_PREVIOUS:
2353                         rtl_writephy(tp, regno, predata);
2354                         index++;
2355                         break;
2356                 case PHY_SKIPN:
2357                         index += regno + 1;
2358                         break;
2359                 case PHY_DELAY_MS:
2360                         mdelay(data);
2361                         index++;
2362                         break;
2363
2364                 case PHY_READ_MAC_BYTE:
2365                 case PHY_WRITE_MAC_BYTE:
2366                 case PHY_WRITE_ERI_WORD:
2367                 default:
2368                         BUG();
2369                 }
2370         }
2371 }
2372
2373 static void rtl_release_firmware(struct rtl8169_private *tp)
2374 {
2375         if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2376                 release_firmware(tp->rtl_fw->fw);
2377                 kfree(tp->rtl_fw);
2378         }
2379         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
2380 }
2381
2382 static void rtl_apply_firmware(struct rtl8169_private *tp)
2383 {
2384         struct rtl_fw *rtl_fw = tp->rtl_fw;
2385
2386         /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2387         if (!IS_ERR_OR_NULL(rtl_fw))
2388                 rtl_phy_write_fw(tp, rtl_fw);
2389 }
2390
2391 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2392 {
2393         if (rtl_readphy(tp, reg) != val)
2394                 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2395         else
2396                 rtl_apply_firmware(tp);
2397 }
2398
2399 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2400 {
2401         static const struct phy_reg phy_reg_init[] = {
2402                 { 0x1f, 0x0001 },
2403                 { 0x06, 0x006e },
2404                 { 0x08, 0x0708 },
2405                 { 0x15, 0x4000 },
2406                 { 0x18, 0x65c7 },
2407
2408                 { 0x1f, 0x0001 },
2409                 { 0x03, 0x00a1 },
2410                 { 0x02, 0x0008 },
2411                 { 0x01, 0x0120 },
2412                 { 0x00, 0x1000 },
2413                 { 0x04, 0x0800 },
2414                 { 0x04, 0x0000 },
2415
2416                 { 0x03, 0xff41 },
2417                 { 0x02, 0xdf60 },
2418                 { 0x01, 0x0140 },
2419                 { 0x00, 0x0077 },
2420                 { 0x04, 0x7800 },
2421                 { 0x04, 0x7000 },
2422
2423                 { 0x03, 0x802f },
2424                 { 0x02, 0x4f02 },
2425                 { 0x01, 0x0409 },
2426                 { 0x00, 0xf0f9 },
2427                 { 0x04, 0x9800 },
2428                 { 0x04, 0x9000 },
2429
2430                 { 0x03, 0xdf01 },
2431                 { 0x02, 0xdf20 },
2432                 { 0x01, 0xff95 },
2433                 { 0x00, 0xba00 },
2434                 { 0x04, 0xa800 },
2435                 { 0x04, 0xa000 },
2436
2437                 { 0x03, 0xff41 },
2438                 { 0x02, 0xdf20 },
2439                 { 0x01, 0x0140 },
2440                 { 0x00, 0x00bb },
2441                 { 0x04, 0xb800 },
2442                 { 0x04, 0xb000 },
2443
2444                 { 0x03, 0xdf41 },
2445                 { 0x02, 0xdc60 },
2446                 { 0x01, 0x6340 },
2447                 { 0x00, 0x007d },
2448                 { 0x04, 0xd800 },
2449                 { 0x04, 0xd000 },
2450
2451                 { 0x03, 0xdf01 },
2452                 { 0x02, 0xdf20 },
2453                 { 0x01, 0x100a },
2454                 { 0x00, 0xa0ff },
2455                 { 0x04, 0xf800 },
2456                 { 0x04, 0xf000 },
2457
2458                 { 0x1f, 0x0000 },
2459                 { 0x0b, 0x0000 },
2460                 { 0x00, 0x9200 }
2461         };
2462
2463         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2464 }
2465
2466 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2467 {
2468         static const struct phy_reg phy_reg_init[] = {
2469                 { 0x1f, 0x0002 },
2470                 { 0x01, 0x90d0 },
2471                 { 0x1f, 0x0000 }
2472         };
2473
2474         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2475 }
2476
2477 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2478 {
2479         struct pci_dev *pdev = tp->pci_dev;
2480
2481         if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2482             (pdev->subsystem_device != 0xe000))
2483                 return;
2484
2485         rtl_writephy(tp, 0x1f, 0x0001);
2486         rtl_writephy(tp, 0x10, 0xf01b);
2487         rtl_writephy(tp, 0x1f, 0x0000);
2488 }
2489
2490 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2491 {
2492         static const struct phy_reg phy_reg_init[] = {
2493                 { 0x1f, 0x0001 },
2494                 { 0x04, 0x0000 },
2495                 { 0x03, 0x00a1 },
2496                 { 0x02, 0x0008 },
2497                 { 0x01, 0x0120 },
2498                 { 0x00, 0x1000 },
2499                 { 0x04, 0x0800 },
2500                 { 0x04, 0x9000 },
2501                 { 0x03, 0x802f },
2502                 { 0x02, 0x4f02 },
2503                 { 0x01, 0x0409 },
2504                 { 0x00, 0xf099 },
2505                 { 0x04, 0x9800 },
2506                 { 0x04, 0xa000 },
2507                 { 0x03, 0xdf01 },
2508                 { 0x02, 0xdf20 },
2509                 { 0x01, 0xff95 },
2510                 { 0x00, 0xba00 },
2511                 { 0x04, 0xa800 },
2512                 { 0x04, 0xf000 },
2513                 { 0x03, 0xdf01 },
2514                 { 0x02, 0xdf20 },
2515                 { 0x01, 0x101a },
2516                 { 0x00, 0xa0ff },
2517                 { 0x04, 0xf800 },
2518                 { 0x04, 0x0000 },
2519                 { 0x1f, 0x0000 },
2520
2521                 { 0x1f, 0x0001 },
2522                 { 0x10, 0xf41b },
2523                 { 0x14, 0xfb54 },
2524                 { 0x18, 0xf5c7 },
2525                 { 0x1f, 0x0000 },
2526
2527                 { 0x1f, 0x0001 },
2528                 { 0x17, 0x0cc0 },
2529                 { 0x1f, 0x0000 }
2530         };
2531
2532         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2533
2534         rtl8169scd_hw_phy_config_quirk(tp);
2535 }
2536
2537 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2538 {
2539         static const struct phy_reg phy_reg_init[] = {
2540                 { 0x1f, 0x0001 },
2541                 { 0x04, 0x0000 },
2542                 { 0x03, 0x00a1 },
2543                 { 0x02, 0x0008 },
2544                 { 0x01, 0x0120 },
2545                 { 0x00, 0x1000 },
2546                 { 0x04, 0x0800 },
2547                 { 0x04, 0x9000 },
2548                 { 0x03, 0x802f },
2549                 { 0x02, 0x4f02 },
2550                 { 0x01, 0x0409 },
2551                 { 0x00, 0xf099 },
2552                 { 0x04, 0x9800 },
2553                 { 0x04, 0xa000 },
2554                 { 0x03, 0xdf01 },
2555                 { 0x02, 0xdf20 },
2556                 { 0x01, 0xff95 },
2557                 { 0x00, 0xba00 },
2558                 { 0x04, 0xa800 },
2559                 { 0x04, 0xf000 },
2560                 { 0x03, 0xdf01 },
2561                 { 0x02, 0xdf20 },
2562                 { 0x01, 0x101a },
2563                 { 0x00, 0xa0ff },
2564                 { 0x04, 0xf800 },
2565                 { 0x04, 0x0000 },
2566                 { 0x1f, 0x0000 },
2567
2568                 { 0x1f, 0x0001 },
2569                 { 0x0b, 0x8480 },
2570                 { 0x1f, 0x0000 },
2571
2572                 { 0x1f, 0x0001 },
2573                 { 0x18, 0x67c7 },
2574                 { 0x04, 0x2000 },
2575                 { 0x03, 0x002f },
2576                 { 0x02, 0x4360 },
2577                 { 0x01, 0x0109 },
2578                 { 0x00, 0x3022 },
2579                 { 0x04, 0x2800 },
2580                 { 0x1f, 0x0000 },
2581
2582                 { 0x1f, 0x0001 },
2583                 { 0x17, 0x0cc0 },
2584                 { 0x1f, 0x0000 }
2585         };
2586
2587         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2588 }
2589
2590 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2591 {
2592         static const struct phy_reg phy_reg_init[] = {
2593                 { 0x10, 0xf41b },
2594                 { 0x1f, 0x0000 }
2595         };
2596
2597         rtl_writephy(tp, 0x1f, 0x0001);
2598         rtl_patchphy(tp, 0x16, 1 << 0);
2599
2600         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2601 }
2602
2603 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2604 {
2605         static const struct phy_reg phy_reg_init[] = {
2606                 { 0x1f, 0x0001 },
2607                 { 0x10, 0xf41b },
2608                 { 0x1f, 0x0000 }
2609         };
2610
2611         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2612 }
2613
2614 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2615 {
2616         static const struct phy_reg phy_reg_init[] = {
2617                 { 0x1f, 0x0000 },
2618                 { 0x1d, 0x0f00 },
2619                 { 0x1f, 0x0002 },
2620                 { 0x0c, 0x1ec8 },
2621                 { 0x1f, 0x0000 }
2622         };
2623
2624         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2625 }
2626
2627 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2628 {
2629         static const struct phy_reg phy_reg_init[] = {
2630                 { 0x1f, 0x0001 },
2631                 { 0x1d, 0x3d98 },
2632                 { 0x1f, 0x0000 }
2633         };
2634
2635         rtl_writephy(tp, 0x1f, 0x0000);
2636         rtl_patchphy(tp, 0x14, 1 << 5);
2637         rtl_patchphy(tp, 0x0d, 1 << 5);
2638
2639         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2640 }
2641
2642 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2643 {
2644         static const struct phy_reg phy_reg_init[] = {
2645                 { 0x1f, 0x0001 },
2646                 { 0x12, 0x2300 },
2647                 { 0x1f, 0x0002 },
2648                 { 0x00, 0x88d4 },
2649                 { 0x01, 0x82b1 },
2650                 { 0x03, 0x7002 },
2651                 { 0x08, 0x9e30 },
2652                 { 0x09, 0x01f0 },
2653                 { 0x0a, 0x5500 },
2654                 { 0x0c, 0x00c8 },
2655                 { 0x1f, 0x0003 },
2656                 { 0x12, 0xc096 },
2657                 { 0x16, 0x000a },
2658                 { 0x1f, 0x0000 },
2659                 { 0x1f, 0x0000 },
2660                 { 0x09, 0x2000 },
2661                 { 0x09, 0x0000 }
2662         };
2663
2664         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2665
2666         rtl_patchphy(tp, 0x14, 1 << 5);
2667         rtl_patchphy(tp, 0x0d, 1 << 5);
2668         rtl_writephy(tp, 0x1f, 0x0000);
2669 }
2670
2671 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2672 {
2673         static const struct phy_reg phy_reg_init[] = {
2674                 { 0x1f, 0x0001 },
2675                 { 0x12, 0x2300 },
2676                 { 0x03, 0x802f },
2677                 { 0x02, 0x4f02 },
2678                 { 0x01, 0x0409 },
2679                 { 0x00, 0xf099 },
2680                 { 0x04, 0x9800 },
2681                 { 0x04, 0x9000 },
2682                 { 0x1d, 0x3d98 },
2683                 { 0x1f, 0x0002 },
2684                 { 0x0c, 0x7eb8 },
2685                 { 0x06, 0x0761 },
2686                 { 0x1f, 0x0003 },
2687                 { 0x16, 0x0f0a },
2688                 { 0x1f, 0x0000 }
2689         };
2690
2691         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2692
2693         rtl_patchphy(tp, 0x16, 1 << 0);
2694         rtl_patchphy(tp, 0x14, 1 << 5);
2695         rtl_patchphy(tp, 0x0d, 1 << 5);
2696         rtl_writephy(tp, 0x1f, 0x0000);
2697 }
2698
2699 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2700 {
2701         static const struct phy_reg phy_reg_init[] = {
2702                 { 0x1f, 0x0001 },
2703                 { 0x12, 0x2300 },
2704                 { 0x1d, 0x3d98 },
2705                 { 0x1f, 0x0002 },
2706                 { 0x0c, 0x7eb8 },
2707                 { 0x06, 0x5461 },
2708                 { 0x1f, 0x0003 },
2709                 { 0x16, 0x0f0a },
2710                 { 0x1f, 0x0000 }
2711         };
2712
2713         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2714
2715         rtl_patchphy(tp, 0x16, 1 << 0);
2716         rtl_patchphy(tp, 0x14, 1 << 5);
2717         rtl_patchphy(tp, 0x0d, 1 << 5);
2718         rtl_writephy(tp, 0x1f, 0x0000);
2719 }
2720
2721 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2722 {
2723         rtl8168c_3_hw_phy_config(tp);
2724 }
2725
2726 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2727 {
2728         static const struct phy_reg phy_reg_init_0[] = {
2729                 /* Channel Estimation */
2730                 { 0x1f, 0x0001 },
2731                 { 0x06, 0x4064 },
2732                 { 0x07, 0x2863 },
2733                 { 0x08, 0x059c },
2734                 { 0x09, 0x26b4 },
2735                 { 0x0a, 0x6a19 },
2736                 { 0x0b, 0xdcc8 },
2737                 { 0x10, 0xf06d },
2738                 { 0x14, 0x7f68 },
2739                 { 0x18, 0x7fd9 },
2740                 { 0x1c, 0xf0ff },
2741                 { 0x1d, 0x3d9c },
2742                 { 0x1f, 0x0003 },
2743                 { 0x12, 0xf49f },
2744                 { 0x13, 0x070b },
2745                 { 0x1a, 0x05ad },
2746                 { 0x14, 0x94c0 },
2747
2748                 /*
2749                  * Tx Error Issue
2750                  * Enhance line driver power
2751                  */
2752                 { 0x1f, 0x0002 },
2753                 { 0x06, 0x5561 },
2754                 { 0x1f, 0x0005 },
2755                 { 0x05, 0x8332 },
2756                 { 0x06, 0x5561 },
2757
2758                 /*
2759                  * Can not link to 1Gbps with bad cable
2760                  * Decrease SNR threshold form 21.07dB to 19.04dB
2761                  */
2762                 { 0x1f, 0x0001 },
2763                 { 0x17, 0x0cc0 },
2764
2765                 { 0x1f, 0x0000 },
2766                 { 0x0d, 0xf880 }
2767         };
2768
2769         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2770
2771         /*
2772          * Rx Error Issue
2773          * Fine Tune Switching regulator parameter
2774          */
2775         rtl_writephy(tp, 0x1f, 0x0002);
2776         rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2777         rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
2778
2779         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2780                 static const struct phy_reg phy_reg_init[] = {
2781                         { 0x1f, 0x0002 },
2782                         { 0x05, 0x669a },
2783                         { 0x1f, 0x0005 },
2784                         { 0x05, 0x8330 },
2785                         { 0x06, 0x669a },
2786                         { 0x1f, 0x0002 }
2787                 };
2788                 int val;
2789
2790                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2791
2792                 val = rtl_readphy(tp, 0x0d);
2793
2794                 if ((val & 0x00ff) != 0x006c) {
2795                         static const u32 set[] = {
2796                                 0x0065, 0x0066, 0x0067, 0x0068,
2797                                 0x0069, 0x006a, 0x006b, 0x006c
2798                         };
2799                         int i;
2800
2801                         rtl_writephy(tp, 0x1f, 0x0002);
2802
2803                         val &= 0xff00;
2804                         for (i = 0; i < ARRAY_SIZE(set); i++)
2805                                 rtl_writephy(tp, 0x0d, val | set[i]);
2806                 }
2807         } else {
2808                 static const struct phy_reg phy_reg_init[] = {
2809                         { 0x1f, 0x0002 },
2810                         { 0x05, 0x6662 },
2811                         { 0x1f, 0x0005 },
2812                         { 0x05, 0x8330 },
2813                         { 0x06, 0x6662 }
2814                 };
2815
2816                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2817         }
2818
2819         /* RSET couple improve */
2820         rtl_writephy(tp, 0x1f, 0x0002);
2821         rtl_patchphy(tp, 0x0d, 0x0300);
2822         rtl_patchphy(tp, 0x0f, 0x0010);
2823
2824         /* Fine tune PLL performance */
2825         rtl_writephy(tp, 0x1f, 0x0002);
2826         rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2827         rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2828
2829         rtl_writephy(tp, 0x1f, 0x0005);
2830         rtl_writephy(tp, 0x05, 0x001b);
2831
2832         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2833
2834         rtl_writephy(tp, 0x1f, 0x0000);
2835 }
2836
2837 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2838 {
2839         static const struct phy_reg phy_reg_init_0[] = {
2840                 /* Channel Estimation */
2841                 { 0x1f, 0x0001 },
2842                 { 0x06, 0x4064 },
2843                 { 0x07, 0x2863 },
2844                 { 0x08, 0x059c },
2845                 { 0x09, 0x26b4 },
2846                 { 0x0a, 0x6a19 },
2847                 { 0x0b, 0xdcc8 },
2848                 { 0x10, 0xf06d },
2849                 { 0x14, 0x7f68 },
2850                 { 0x18, 0x7fd9 },
2851                 { 0x1c, 0xf0ff },
2852                 { 0x1d, 0x3d9c },
2853                 { 0x1f, 0x0003 },
2854                 { 0x12, 0xf49f },
2855                 { 0x13, 0x070b },
2856                 { 0x1a, 0x05ad },
2857                 { 0x14, 0x94c0 },
2858
2859                 /*
2860                  * Tx Error Issue
2861                  * Enhance line driver power
2862                  */
2863                 { 0x1f, 0x0002 },
2864                 { 0x06, 0x5561 },
2865                 { 0x1f, 0x0005 },
2866                 { 0x05, 0x8332 },
2867                 { 0x06, 0x5561 },
2868
2869                 /*
2870                  * Can not link to 1Gbps with bad cable
2871                  * Decrease SNR threshold form 21.07dB to 19.04dB
2872                  */
2873                 { 0x1f, 0x0001 },
2874                 { 0x17, 0x0cc0 },
2875
2876                 { 0x1f, 0x0000 },
2877                 { 0x0d, 0xf880 }
2878         };
2879
2880         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2881
2882         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2883                 static const struct phy_reg phy_reg_init[] = {
2884                         { 0x1f, 0x0002 },
2885                         { 0x05, 0x669a },
2886                         { 0x1f, 0x0005 },
2887                         { 0x05, 0x8330 },
2888                         { 0x06, 0x669a },
2889
2890                         { 0x1f, 0x0002 }
2891                 };
2892                 int val;
2893
2894                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2895
2896                 val = rtl_readphy(tp, 0x0d);
2897                 if ((val & 0x00ff) != 0x006c) {
2898                         static const u32 set[] = {
2899                                 0x0065, 0x0066, 0x0067, 0x0068,
2900                                 0x0069, 0x006a, 0x006b, 0x006c
2901                         };
2902                         int i;
2903
2904                         rtl_writephy(tp, 0x1f, 0x0002);
2905
2906                         val &= 0xff00;
2907                         for (i = 0; i < ARRAY_SIZE(set); i++)
2908                                 rtl_writephy(tp, 0x0d, val | set[i]);
2909                 }
2910         } else {
2911                 static const struct phy_reg phy_reg_init[] = {
2912                         { 0x1f, 0x0002 },
2913                         { 0x05, 0x2642 },
2914                         { 0x1f, 0x0005 },
2915                         { 0x05, 0x8330 },
2916                         { 0x06, 0x2642 }
2917                 };
2918
2919                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2920         }
2921
2922         /* Fine tune PLL performance */
2923         rtl_writephy(tp, 0x1f, 0x0002);
2924         rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2925         rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2926
2927         /* Switching regulator Slew rate */
2928         rtl_writephy(tp, 0x1f, 0x0002);
2929         rtl_patchphy(tp, 0x0f, 0x0017);
2930
2931         rtl_writephy(tp, 0x1f, 0x0005);
2932         rtl_writephy(tp, 0x05, 0x001b);
2933
2934         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
2935
2936         rtl_writephy(tp, 0x1f, 0x0000);
2937 }
2938
2939 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
2940 {
2941         static const struct phy_reg phy_reg_init[] = {
2942                 { 0x1f, 0x0002 },
2943                 { 0x10, 0x0008 },
2944                 { 0x0d, 0x006c },
2945
2946                 { 0x1f, 0x0000 },
2947                 { 0x0d, 0xf880 },
2948
2949                 { 0x1f, 0x0001 },
2950                 { 0x17, 0x0cc0 },
2951
2952                 { 0x1f, 0x0001 },
2953                 { 0x0b, 0xa4d8 },
2954                 { 0x09, 0x281c },
2955                 { 0x07, 0x2883 },
2956                 { 0x0a, 0x6b35 },
2957                 { 0x1d, 0x3da4 },
2958                 { 0x1c, 0xeffd },
2959                 { 0x14, 0x7f52 },
2960                 { 0x18, 0x7fc6 },
2961                 { 0x08, 0x0601 },
2962                 { 0x06, 0x4063 },
2963                 { 0x10, 0xf074 },
2964                 { 0x1f, 0x0003 },
2965                 { 0x13, 0x0789 },
2966                 { 0x12, 0xf4bd },
2967                 { 0x1a, 0x04fd },
2968                 { 0x14, 0x84b0 },
2969                 { 0x1f, 0x0000 },
2970                 { 0x00, 0x9200 },
2971
2972                 { 0x1f, 0x0005 },
2973                 { 0x01, 0x0340 },
2974                 { 0x1f, 0x0001 },
2975                 { 0x04, 0x4000 },
2976                 { 0x03, 0x1d21 },
2977                 { 0x02, 0x0c32 },
2978                 { 0x01, 0x0200 },
2979                 { 0x00, 0x5554 },
2980                 { 0x04, 0x4800 },
2981                 { 0x04, 0x4000 },
2982                 { 0x04, 0xf000 },
2983                 { 0x03, 0xdf01 },
2984                 { 0x02, 0xdf20 },
2985                 { 0x01, 0x101a },
2986                 { 0x00, 0xa0ff },
2987                 { 0x04, 0xf800 },
2988                 { 0x04, 0xf000 },
2989                 { 0x1f, 0x0000 },
2990
2991                 { 0x1f, 0x0007 },
2992                 { 0x1e, 0x0023 },
2993                 { 0x16, 0x0000 },
2994                 { 0x1f, 0x0000 }
2995         };
2996
2997         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2998 }
2999
3000 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
3001 {
3002         static const struct phy_reg phy_reg_init[] = {
3003                 { 0x1f, 0x0001 },
3004                 { 0x17, 0x0cc0 },
3005
3006                 { 0x1f, 0x0007 },
3007                 { 0x1e, 0x002d },
3008                 { 0x18, 0x0040 },
3009                 { 0x1f, 0x0000 }
3010         };
3011
3012         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3013         rtl_patchphy(tp, 0x0d, 1 << 5);
3014 }
3015
3016 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
3017 {
3018         static const struct phy_reg phy_reg_init[] = {
3019                 /* Enable Delay cap */
3020                 { 0x1f, 0x0005 },
3021                 { 0x05, 0x8b80 },
3022                 { 0x06, 0xc896 },
3023                 { 0x1f, 0x0000 },
3024
3025                 /* Channel estimation fine tune */
3026                 { 0x1f, 0x0001 },
3027                 { 0x0b, 0x6c20 },
3028                 { 0x07, 0x2872 },
3029                 { 0x1c, 0xefff },
3030                 { 0x1f, 0x0003 },
3031                 { 0x14, 0x6420 },
3032                 { 0x1f, 0x0000 },
3033
3034                 /* Update PFM & 10M TX idle timer */
3035                 { 0x1f, 0x0007 },
3036                 { 0x1e, 0x002f },
3037                 { 0x15, 0x1919 },
3038                 { 0x1f, 0x0000 },
3039
3040                 { 0x1f, 0x0007 },
3041                 { 0x1e, 0x00ac },
3042                 { 0x18, 0x0006 },
3043                 { 0x1f, 0x0000 }
3044         };
3045
3046         rtl_apply_firmware(tp);
3047
3048         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3049
3050         /* DCO enable for 10M IDLE Power */
3051         rtl_writephy(tp, 0x1f, 0x0007);
3052         rtl_writephy(tp, 0x1e, 0x0023);
3053         rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
3054         rtl_writephy(tp, 0x1f, 0x0000);
3055
3056         /* For impedance matching */
3057         rtl_writephy(tp, 0x1f, 0x0002);
3058         rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
3059         rtl_writephy(tp, 0x1f, 0x0000);
3060
3061         /* PHY auto speed down */
3062         rtl_writephy(tp, 0x1f, 0x0007);
3063         rtl_writephy(tp, 0x1e, 0x002d);
3064         rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
3065         rtl_writephy(tp, 0x1f, 0x0000);
3066         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3067
3068         rtl_writephy(tp, 0x1f, 0x0005);
3069         rtl_writephy(tp, 0x05, 0x8b86);
3070         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3071         rtl_writephy(tp, 0x1f, 0x0000);
3072
3073         rtl_writephy(tp, 0x1f, 0x0005);
3074         rtl_writephy(tp, 0x05, 0x8b85);
3075         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3076         rtl_writephy(tp, 0x1f, 0x0007);
3077         rtl_writephy(tp, 0x1e, 0x0020);
3078         rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
3079         rtl_writephy(tp, 0x1f, 0x0006);
3080         rtl_writephy(tp, 0x00, 0x5a00);
3081         rtl_writephy(tp, 0x1f, 0x0000);
3082         rtl_writephy(tp, 0x0d, 0x0007);
3083         rtl_writephy(tp, 0x0e, 0x003c);
3084         rtl_writephy(tp, 0x0d, 0x4007);
3085         rtl_writephy(tp, 0x0e, 0x0000);
3086         rtl_writephy(tp, 0x0d, 0x0000);
3087 }
3088
3089 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3090 {
3091         const u16 w[] = {
3092                 addr[0] | (addr[1] << 8),
3093                 addr[2] | (addr[3] << 8),
3094                 addr[4] | (addr[5] << 8)
3095         };
3096         const struct exgmac_reg e[] = {
3097                 { .addr = 0xe0, ERIAR_MASK_1111, .val = w[0] | (w[1] << 16) },
3098                 { .addr = 0xe4, ERIAR_MASK_1111, .val = w[2] },
3099                 { .addr = 0xf0, ERIAR_MASK_1111, .val = w[0] << 16 },
3100                 { .addr = 0xf4, ERIAR_MASK_1111, .val = w[1] | (w[2] << 16) }
3101         };
3102
3103         rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e));
3104 }
3105
3106 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3107 {
3108         static const struct phy_reg phy_reg_init[] = {
3109                 /* Enable Delay cap */
3110                 { 0x1f, 0x0004 },
3111                 { 0x1f, 0x0007 },
3112                 { 0x1e, 0x00ac },
3113                 { 0x18, 0x0006 },
3114                 { 0x1f, 0x0002 },
3115                 { 0x1f, 0x0000 },
3116                 { 0x1f, 0x0000 },
3117
3118                 /* Channel estimation fine tune */
3119                 { 0x1f, 0x0003 },
3120                 { 0x09, 0xa20f },
3121                 { 0x1f, 0x0000 },
3122                 { 0x1f, 0x0000 },
3123
3124                 /* Green Setting */
3125                 { 0x1f, 0x0005 },
3126                 { 0x05, 0x8b5b },
3127                 { 0x06, 0x9222 },
3128                 { 0x05, 0x8b6d },
3129                 { 0x06, 0x8000 },
3130                 { 0x05, 0x8b76 },
3131                 { 0x06, 0x8000 },
3132                 { 0x1f, 0x0000 }
3133         };
3134
3135         rtl_apply_firmware(tp);
3136
3137         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3138
3139         /* For 4-corner performance improve */
3140         rtl_writephy(tp, 0x1f, 0x0005);
3141         rtl_writephy(tp, 0x05, 0x8b80);
3142         rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
3143         rtl_writephy(tp, 0x1f, 0x0000);
3144
3145         /* PHY auto speed down */
3146         rtl_writephy(tp, 0x1f, 0x0004);
3147         rtl_writephy(tp, 0x1f, 0x0007);
3148         rtl_writephy(tp, 0x1e, 0x002d);
3149         rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3150         rtl_writephy(tp, 0x1f, 0x0002);
3151         rtl_writephy(tp, 0x1f, 0x0000);
3152         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3153
3154         /* improve 10M EEE waveform */
3155         rtl_writephy(tp, 0x1f, 0x0005);
3156         rtl_writephy(tp, 0x05, 0x8b86);
3157         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3158         rtl_writephy(tp, 0x1f, 0x0000);
3159
3160         /* Improve 2-pair detection performance */
3161         rtl_writephy(tp, 0x1f, 0x0005);
3162         rtl_writephy(tp, 0x05, 0x8b85);
3163         rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3164         rtl_writephy(tp, 0x1f, 0x0000);
3165
3166         /* EEE setting */
3167         rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003, ERIAR_EXGMAC);
3168         rtl_writephy(tp, 0x1f, 0x0005);
3169         rtl_writephy(tp, 0x05, 0x8b85);
3170         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3171         rtl_writephy(tp, 0x1f, 0x0004);
3172         rtl_writephy(tp, 0x1f, 0x0007);
3173         rtl_writephy(tp, 0x1e, 0x0020);
3174         rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
3175         rtl_writephy(tp, 0x1f, 0x0002);
3176         rtl_writephy(tp, 0x1f, 0x0000);
3177         rtl_writephy(tp, 0x0d, 0x0007);
3178         rtl_writephy(tp, 0x0e, 0x003c);
3179         rtl_writephy(tp, 0x0d, 0x4007);
3180         rtl_writephy(tp, 0x0e, 0x0000);
3181         rtl_writephy(tp, 0x0d, 0x0000);
3182
3183         /* Green feature */
3184         rtl_writephy(tp, 0x1f, 0x0003);
3185         rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
3186         rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
3187         rtl_writephy(tp, 0x1f, 0x0000);
3188
3189         /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3190         rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
3191 }
3192
3193 static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3194 {
3195         /* For 4-corner performance improve */
3196         rtl_writephy(tp, 0x1f, 0x0005);
3197         rtl_writephy(tp, 0x05, 0x8b80);
3198         rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000);
3199         rtl_writephy(tp, 0x1f, 0x0000);
3200
3201         /* PHY auto speed down */
3202         rtl_writephy(tp, 0x1f, 0x0007);
3203         rtl_writephy(tp, 0x1e, 0x002d);
3204         rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3205         rtl_writephy(tp, 0x1f, 0x0000);
3206         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3207
3208         /* Improve 10M EEE waveform */
3209         rtl_writephy(tp, 0x1f, 0x0005);
3210         rtl_writephy(tp, 0x05, 0x8b86);
3211         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3212         rtl_writephy(tp, 0x1f, 0x0000);
3213 }
3214
3215 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3216 {
3217         static const struct phy_reg phy_reg_init[] = {
3218                 /* Channel estimation fine tune */
3219                 { 0x1f, 0x0003 },
3220                 { 0x09, 0xa20f },
3221                 { 0x1f, 0x0000 },
3222
3223                 /* Modify green table for giga & fnet */
3224                 { 0x1f, 0x0005 },
3225                 { 0x05, 0x8b55 },
3226                 { 0x06, 0x0000 },
3227                 { 0x05, 0x8b5e },
3228                 { 0x06, 0x0000 },
3229                 { 0x05, 0x8b67 },
3230                 { 0x06, 0x0000 },
3231                 { 0x05, 0x8b70 },
3232                 { 0x06, 0x0000 },
3233                 { 0x1f, 0x0000 },
3234                 { 0x1f, 0x0007 },
3235                 { 0x1e, 0x0078 },
3236                 { 0x17, 0x0000 },
3237                 { 0x19, 0x00fb },
3238                 { 0x1f, 0x0000 },
3239
3240                 /* Modify green table for 10M */
3241                 { 0x1f, 0x0005 },
3242                 { 0x05, 0x8b79 },
3243                 { 0x06, 0xaa00 },
3244                 { 0x1f, 0x0000 },
3245
3246                 /* Disable hiimpedance detection (RTCT) */
3247                 { 0x1f, 0x0003 },
3248                 { 0x01, 0x328a },
3249                 { 0x1f, 0x0000 }
3250         };
3251
3252         rtl_apply_firmware(tp);
3253
3254         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3255
3256         rtl8168f_hw_phy_config(tp);
3257
3258         /* Improve 2-pair detection performance */
3259         rtl_writephy(tp, 0x1f, 0x0005);
3260         rtl_writephy(tp, 0x05, 0x8b85);
3261         rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3262         rtl_writephy(tp, 0x1f, 0x0000);
3263 }
3264
3265 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3266 {
3267         rtl_apply_firmware(tp);
3268
3269         rtl8168f_hw_phy_config(tp);
3270 }
3271
3272 static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3273 {
3274         static const struct phy_reg phy_reg_init[] = {
3275                 /* Channel estimation fine tune */
3276                 { 0x1f, 0x0003 },
3277                 { 0x09, 0xa20f },
3278                 { 0x1f, 0x0000 },
3279
3280                 /* Modify green table for giga & fnet */
3281                 { 0x1f, 0x0005 },
3282                 { 0x05, 0x8b55 },
3283                 { 0x06, 0x0000 },
3284                 { 0x05, 0x8b5e },
3285                 { 0x06, 0x0000 },
3286                 { 0x05, 0x8b67 },
3287                 { 0x06, 0x0000 },
3288                 { 0x05, 0x8b70 },
3289                 { 0x06, 0x0000 },
3290                 { 0x1f, 0x0000 },
3291                 { 0x1f, 0x0007 },
3292                 { 0x1e, 0x0078 },
3293                 { 0x17, 0x0000 },
3294                 { 0x19, 0x00aa },
3295                 { 0x1f, 0x0000 },
3296
3297                 /* Modify green table for 10M */
3298                 { 0x1f, 0x0005 },
3299                 { 0x05, 0x8b79 },
3300                 { 0x06, 0xaa00 },
3301                 { 0x1f, 0x0000 },
3302
3303                 /* Disable hiimpedance detection (RTCT) */
3304                 { 0x1f, 0x0003 },
3305                 { 0x01, 0x328a },
3306                 { 0x1f, 0x0000 }
3307         };
3308
3309
3310         rtl_apply_firmware(tp);
3311
3312         rtl8168f_hw_phy_config(tp);
3313
3314         /* Improve 2-pair detection performance */
3315         rtl_writephy(tp, 0x1f, 0x0005);
3316         rtl_writephy(tp, 0x05, 0x8b85);
3317         rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3318         rtl_writephy(tp, 0x1f, 0x0000);
3319
3320         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3321
3322         /* Modify green table for giga */
3323         rtl_writephy(tp, 0x1f, 0x0005);
3324         rtl_writephy(tp, 0x05, 0x8b54);
3325         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0800);
3326         rtl_writephy(tp, 0x05, 0x8b5d);
3327         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0800);
3328         rtl_writephy(tp, 0x05, 0x8a7c);
3329         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3330         rtl_writephy(tp, 0x05, 0x8a7f);
3331         rtl_w1w0_phy(tp, 0x06, 0x0100, 0x0000);
3332         rtl_writephy(tp, 0x05, 0x8a82);
3333         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3334         rtl_writephy(tp, 0x05, 0x8a85);
3335         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3336         rtl_writephy(tp, 0x05, 0x8a88);
3337         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3338         rtl_writephy(tp, 0x1f, 0x0000);
3339
3340         /* uc same-seed solution */
3341         rtl_writephy(tp, 0x1f, 0x0005);
3342         rtl_writephy(tp, 0x05, 0x8b85);
3343         rtl_w1w0_phy(tp, 0x06, 0x8000, 0x0000);
3344         rtl_writephy(tp, 0x1f, 0x0000);
3345
3346         /* eee setting */
3347         rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC);
3348         rtl_writephy(tp, 0x1f, 0x0005);
3349         rtl_writephy(tp, 0x05, 0x8b85);
3350         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3351         rtl_writephy(tp, 0x1f, 0x0004);
3352         rtl_writephy(tp, 0x1f, 0x0007);
3353         rtl_writephy(tp, 0x1e, 0x0020);
3354         rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
3355         rtl_writephy(tp, 0x1f, 0x0000);
3356         rtl_writephy(tp, 0x0d, 0x0007);
3357         rtl_writephy(tp, 0x0e, 0x003c);
3358         rtl_writephy(tp, 0x0d, 0x4007);
3359         rtl_writephy(tp, 0x0e, 0x0000);
3360         rtl_writephy(tp, 0x0d, 0x0000);
3361
3362         /* Green feature */
3363         rtl_writephy(tp, 0x1f, 0x0003);
3364         rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
3365         rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
3366         rtl_writephy(tp, 0x1f, 0x0000);
3367 }
3368
3369 static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3370 {
3371         rtl_apply_firmware(tp);
3372
3373         if (r8168_phy_ocp_read(tp, 0xa460) & 0x0100)
3374                 rtl_w1w0_phy_ocp(tp, 0xbcc4, 0x0000, 0x8000);
3375         else
3376                 rtl_w1w0_phy_ocp(tp, 0xbcc4, 0x8000, 0x0000);
3377
3378         if (r8168_phy_ocp_read(tp, 0xa466) & 0x0100)
3379                 rtl_w1w0_phy_ocp(tp, 0xc41a, 0x0002, 0x0000);
3380         else
3381                 rtl_w1w0_phy_ocp(tp, 0xbcc4, 0x0000, 0x0002);
3382
3383         rtl_w1w0_phy_ocp(tp, 0xa442, 0x000c, 0x0000);
3384         rtl_w1w0_phy_ocp(tp, 0xa4b2, 0x0004, 0x0000);
3385
3386         r8168_phy_ocp_write(tp, 0xa436, 0x8012);
3387         rtl_w1w0_phy_ocp(tp, 0xa438, 0x8000, 0x0000);
3388
3389         rtl_w1w0_phy_ocp(tp, 0xc422, 0x4000, 0x2000);
3390 }
3391
3392 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
3393 {
3394         static const struct phy_reg phy_reg_init[] = {
3395                 { 0x1f, 0x0003 },
3396                 { 0x08, 0x441d },
3397                 { 0x01, 0x9100 },
3398                 { 0x1f, 0x0000 }
3399         };
3400
3401         rtl_writephy(tp, 0x1f, 0x0000);
3402         rtl_patchphy(tp, 0x11, 1 << 12);
3403         rtl_patchphy(tp, 0x19, 1 << 13);
3404         rtl_patchphy(tp, 0x10, 1 << 15);
3405
3406         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3407 }
3408
3409 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3410 {
3411         static const struct phy_reg phy_reg_init[] = {
3412                 { 0x1f, 0x0005 },
3413                 { 0x1a, 0x0000 },
3414                 { 0x1f, 0x0000 },
3415
3416                 { 0x1f, 0x0004 },
3417                 { 0x1c, 0x0000 },
3418                 { 0x1f, 0x0000 },
3419
3420                 { 0x1f, 0x0001 },
3421                 { 0x15, 0x7701 },
3422                 { 0x1f, 0x0000 }
3423         };
3424
3425         /* Disable ALDPS before ram code */
3426         rtl_writephy(tp, 0x1f, 0x0000);
3427         rtl_writephy(tp, 0x18, 0x0310);
3428         msleep(100);
3429
3430         rtl_apply_firmware(tp);
3431
3432         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3433 }
3434
3435 static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
3436 {
3437         /* Disable ALDPS before setting firmware */
3438         rtl_writephy(tp, 0x1f, 0x0000);
3439         rtl_writephy(tp, 0x18, 0x0310);
3440         msleep(20);
3441
3442         rtl_apply_firmware(tp);
3443
3444         /* EEE setting */
3445         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3446         rtl_writephy(tp, 0x1f, 0x0004);
3447         rtl_writephy(tp, 0x10, 0x401f);
3448         rtl_writephy(tp, 0x19, 0x7030);
3449         rtl_writephy(tp, 0x1f, 0x0000);
3450 }
3451
3452 static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
3453 {
3454         static const struct phy_reg phy_reg_init[] = {
3455                 { 0x1f, 0x0004 },
3456                 { 0x10, 0xc07f },
3457                 { 0x19, 0x7030 },
3458                 { 0x1f, 0x0000 }
3459         };
3460
3461         /* Disable ALDPS before ram code */
3462         rtl_writephy(tp, 0x1f, 0x0000);
3463         rtl_writephy(tp, 0x18, 0x0310);
3464         msleep(100);
3465
3466         rtl_apply_firmware(tp);
3467
3468         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3469         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3470
3471         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3472 }
3473
3474 static void rtl_hw_phy_config(struct net_device *dev)
3475 {
3476         struct rtl8169_private *tp = netdev_priv(dev);
3477
3478         rtl8169_print_mac_version(tp);
3479
3480         switch (tp->mac_version) {
3481         case RTL_GIGA_MAC_VER_01:
3482                 break;
3483         case RTL_GIGA_MAC_VER_02:
3484         case RTL_GIGA_MAC_VER_03:
3485                 rtl8169s_hw_phy_config(tp);
3486                 break;
3487         case RTL_GIGA_MAC_VER_04:
3488                 rtl8169sb_hw_phy_config(tp);
3489                 break;
3490         case RTL_GIGA_MAC_VER_05:
3491                 rtl8169scd_hw_phy_config(tp);
3492                 break;
3493         case RTL_GIGA_MAC_VER_06:
3494                 rtl8169sce_hw_phy_config(tp);
3495                 break;
3496         case RTL_GIGA_MAC_VER_07:
3497         case RTL_GIGA_MAC_VER_08:
3498         case RTL_GIGA_MAC_VER_09:
3499                 rtl8102e_hw_phy_config(tp);
3500                 break;
3501         case RTL_GIGA_MAC_VER_11:
3502                 rtl8168bb_hw_phy_config(tp);
3503                 break;
3504         case RTL_GIGA_MAC_VER_12:
3505                 rtl8168bef_hw_phy_config(tp);
3506                 break;
3507         case RTL_GIGA_MAC_VER_17:
3508                 rtl8168bef_hw_phy_config(tp);
3509                 break;
3510         case RTL_GIGA_MAC_VER_18:
3511                 rtl8168cp_1_hw_phy_config(tp);
3512                 break;
3513         case RTL_GIGA_MAC_VER_19:
3514                 rtl8168c_1_hw_phy_config(tp);
3515                 break;
3516         case RTL_GIGA_MAC_VER_20:
3517                 rtl8168c_2_hw_phy_config(tp);
3518                 break;
3519         case RTL_GIGA_MAC_VER_21:
3520                 rtl8168c_3_hw_phy_config(tp);
3521                 break;
3522         case RTL_GIGA_MAC_VER_22:
3523                 rtl8168c_4_hw_phy_config(tp);
3524                 break;
3525         case RTL_GIGA_MAC_VER_23:
3526         case RTL_GIGA_MAC_VER_24:
3527                 rtl8168cp_2_hw_phy_config(tp);
3528                 break;
3529         case RTL_GIGA_MAC_VER_25:
3530                 rtl8168d_1_hw_phy_config(tp);
3531                 break;
3532         case RTL_GIGA_MAC_VER_26:
3533                 rtl8168d_2_hw_phy_config(tp);
3534                 break;
3535         case RTL_GIGA_MAC_VER_27:
3536                 rtl8168d_3_hw_phy_config(tp);
3537                 break;
3538         case RTL_GIGA_MAC_VER_28:
3539                 rtl8168d_4_hw_phy_config(tp);
3540                 break;
3541         case RTL_GIGA_MAC_VER_29:
3542         case RTL_GIGA_MAC_VER_30:
3543                 rtl8105e_hw_phy_config(tp);
3544                 break;
3545         case RTL_GIGA_MAC_VER_31:
3546                 /* None. */
3547                 break;
3548         case RTL_GIGA_MAC_VER_32:
3549         case RTL_GIGA_MAC_VER_33:
3550                 rtl8168e_1_hw_phy_config(tp);
3551                 break;
3552         case RTL_GIGA_MAC_VER_34:
3553                 rtl8168e_2_hw_phy_config(tp);
3554                 break;
3555         case RTL_GIGA_MAC_VER_35:
3556                 rtl8168f_1_hw_phy_config(tp);
3557                 break;
3558         case RTL_GIGA_MAC_VER_36:
3559                 rtl8168f_2_hw_phy_config(tp);
3560                 break;
3561
3562         case RTL_GIGA_MAC_VER_37:
3563                 rtl8402_hw_phy_config(tp);
3564                 break;
3565
3566         case RTL_GIGA_MAC_VER_38:
3567                 rtl8411_hw_phy_config(tp);
3568                 break;
3569
3570         case RTL_GIGA_MAC_VER_39:
3571                 rtl8106e_hw_phy_config(tp);
3572                 break;
3573
3574         case RTL_GIGA_MAC_VER_40:
3575                 rtl8168g_1_hw_phy_config(tp);
3576                 break;
3577
3578         case RTL_GIGA_MAC_VER_41:
3579         default:
3580                 break;
3581         }
3582 }
3583
3584 static void rtl_phy_work(struct rtl8169_private *tp)
3585 {
3586         struct timer_list *timer = &tp->timer;
3587         void __iomem *ioaddr = tp->mmio_addr;
3588         unsigned long timeout = RTL8169_PHY_TIMEOUT;
3589
3590         assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
3591
3592         if (tp->phy_reset_pending(tp)) {
3593                 /*
3594                  * A busy loop could burn quite a few cycles on nowadays CPU.
3595                  * Let's delay the execution of the timer for a few ticks.
3596                  */
3597                 timeout = HZ/10;
3598                 goto out_mod_timer;
3599         }
3600
3601         if (tp->link_ok(ioaddr))
3602                 return;
3603
3604         netif_warn(tp, link, tp->dev, "PHY reset until link up\n");
3605
3606         tp->phy_reset_enable(tp);
3607
3608 out_mod_timer:
3609         mod_timer(timer, jiffies + timeout);
3610 }
3611
3612 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
3613 {
3614         if (!test_and_set_bit(flag, tp->wk.flags))
3615                 schedule_work(&tp->wk.work);
3616 }
3617
3618 static void rtl8169_phy_timer(unsigned long __opaque)
3619 {
3620         struct net_device *dev = (struct net_device *)__opaque;
3621         struct rtl8169_private *tp = netdev_priv(dev);
3622
3623         rtl_schedule_task(tp, RTL_FLAG_TASK_PHY_PENDING);
3624 }
3625
3626 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
3627                                   void __iomem *ioaddr)
3628 {
3629         iounmap(ioaddr);
3630         pci_release_regions(pdev);
3631         pci_clear_mwi(pdev);
3632         pci_disable_device(pdev);
3633         free_netdev(dev);
3634 }
3635
3636 DECLARE_RTL_COND(rtl_phy_reset_cond)
3637 {
3638         return tp->phy_reset_pending(tp);
3639 }
3640
3641 static void rtl8169_phy_reset(struct net_device *dev,
3642                               struct rtl8169_private *tp)
3643 {
3644         tp->phy_reset_enable(tp);
3645         rtl_msleep_loop_wait_low(tp, &rtl_phy_reset_cond, 1, 100);
3646 }
3647
3648 static bool rtl_tbi_enabled(struct rtl8169_private *tp)
3649 {
3650         void __iomem *ioaddr = tp->mmio_addr;
3651
3652         return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
3653             (RTL_R8(PHYstatus) & TBI_Enable);
3654 }
3655
3656 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
3657 {
3658         void __iomem *ioaddr = tp->mmio_addr;
3659
3660         rtl_hw_phy_config(dev);
3661
3662         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
3663                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3664                 RTL_W8(0x82, 0x01);
3665         }
3666
3667         pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
3668
3669         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3670                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
3671
3672         if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
3673                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3674                 RTL_W8(0x82, 0x01);
3675                 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
3676                 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
3677         }
3678
3679         rtl8169_phy_reset(dev, tp);
3680
3681         rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
3682                           ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3683                           ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
3684                           (tp->mii.supports_gmii ?
3685                            ADVERTISED_1000baseT_Half |
3686                            ADVERTISED_1000baseT_Full : 0));
3687
3688         if (rtl_tbi_enabled(tp))
3689                 netif_info(tp, link, dev, "TBI auto-negotiating\n");
3690 }
3691
3692 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
3693 {
3694         void __iomem *ioaddr = tp->mmio_addr;
3695
3696         rtl_lock_work(tp);
3697
3698         RTL_W8(Cfg9346, Cfg9346_Unlock);
3699
3700         RTL_W32(MAC4, addr[4] | addr[5] << 8);
3701         RTL_R32(MAC4);
3702
3703         RTL_W32(MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
3704         RTL_R32(MAC0);
3705
3706         if (tp->mac_version == RTL_GIGA_MAC_VER_34)
3707                 rtl_rar_exgmac_set(tp, addr);
3708
3709         RTL_W8(Cfg9346, Cfg9346_Lock);
3710
3711         rtl_unlock_work(tp);
3712 }
3713
3714 static int rtl_set_mac_address(struct net_device *dev, void *p)
3715 {
3716         struct rtl8169_private *tp = netdev_priv(dev);
3717         struct sockaddr *addr = p;
3718
3719         if (!is_valid_ether_addr(addr->sa_data))
3720                 return -EADDRNOTAVAIL;
3721
3722         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3723
3724         rtl_rar_set(tp, dev->dev_addr);
3725
3726         return 0;
3727 }
3728
3729 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3730 {
3731         struct rtl8169_private *tp = netdev_priv(dev);
3732         struct mii_ioctl_data *data = if_mii(ifr);
3733
3734         return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
3735 }
3736
3737 static int rtl_xmii_ioctl(struct rtl8169_private *tp,
3738                           struct mii_ioctl_data *data, int cmd)
3739 {
3740         switch (cmd) {
3741         case SIOCGMIIPHY:
3742                 data->phy_id = 32; /* Internal PHY */
3743                 return 0;
3744
3745         case SIOCGMIIREG:
3746                 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
3747                 return 0;
3748
3749         case SIOCSMIIREG:
3750                 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
3751                 return 0;
3752         }
3753         return -EOPNOTSUPP;
3754 }
3755
3756 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
3757 {
3758         return -EOPNOTSUPP;
3759 }
3760
3761 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
3762 {
3763         if (tp->features & RTL_FEATURE_MSI) {
3764                 pci_disable_msi(pdev);
3765                 tp->features &= ~RTL_FEATURE_MSI;
3766         }
3767 }
3768
3769 static void rtl_init_mdio_ops(struct rtl8169_private *tp)
3770 {
3771         struct mdio_ops *ops = &tp->mdio_ops;
3772
3773         switch (tp->mac_version) {
3774         case RTL_GIGA_MAC_VER_27:
3775                 ops->write      = r8168dp_1_mdio_write;
3776                 ops->read       = r8168dp_1_mdio_read;
3777                 break;
3778         case RTL_GIGA_MAC_VER_28:
3779         case RTL_GIGA_MAC_VER_31:
3780                 ops->write      = r8168dp_2_mdio_write;
3781                 ops->read       = r8168dp_2_mdio_read;
3782                 break;
3783         case RTL_GIGA_MAC_VER_40:
3784         case RTL_GIGA_MAC_VER_41:
3785                 ops->write      = r8168g_mdio_write;
3786                 ops->read       = r8168g_mdio_read;
3787                 break;
3788         default:
3789                 ops->write      = r8169_mdio_write;
3790                 ops->read       = r8169_mdio_read;
3791                 break;
3792         }
3793 }
3794
3795 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
3796 {
3797         void __iomem *ioaddr = tp->mmio_addr;
3798
3799         switch (tp->mac_version) {
3800         case RTL_GIGA_MAC_VER_25:
3801         case RTL_GIGA_MAC_VER_26:
3802         case RTL_GIGA_MAC_VER_29:
3803         case RTL_GIGA_MAC_VER_30:
3804         case RTL_GIGA_MAC_VER_32:
3805         case RTL_GIGA_MAC_VER_33:
3806         case RTL_GIGA_MAC_VER_34:
3807         case RTL_GIGA_MAC_VER_37:
3808         case RTL_GIGA_MAC_VER_38:
3809         case RTL_GIGA_MAC_VER_39:
3810         case RTL_GIGA_MAC_VER_40:
3811         case RTL_GIGA_MAC_VER_41:
3812                 RTL_W32(RxConfig, RTL_R32(RxConfig) |
3813                         AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
3814                 break;
3815         default:
3816                 break;
3817         }
3818 }
3819
3820 static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
3821 {
3822         if (!(__rtl8169_get_wol(tp) & WAKE_ANY))
3823                 return false;
3824
3825         rtl_writephy(tp, 0x1f, 0x0000);
3826         rtl_writephy(tp, MII_BMCR, 0x0000);
3827
3828         rtl_wol_suspend_quirk(tp);
3829
3830         return true;
3831 }
3832
3833 static void r810x_phy_power_down(struct rtl8169_private *tp)
3834 {
3835         rtl_writephy(tp, 0x1f, 0x0000);
3836         rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3837 }
3838
3839 static void r810x_phy_power_up(struct rtl8169_private *tp)
3840 {
3841         rtl_writephy(tp, 0x1f, 0x0000);
3842         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3843 }
3844
3845 static void r810x_pll_power_down(struct rtl8169_private *tp)
3846 {
3847         void __iomem *ioaddr = tp->mmio_addr;
3848
3849         if (rtl_wol_pll_power_down(tp))
3850                 return;
3851
3852         r810x_phy_power_down(tp);
3853
3854         switch (tp->mac_version) {
3855         case RTL_GIGA_MAC_VER_07:
3856         case RTL_GIGA_MAC_VER_08:
3857         case RTL_GIGA_MAC_VER_09:
3858         case RTL_GIGA_MAC_VER_10:
3859         case RTL_GIGA_MAC_VER_13:
3860         case RTL_GIGA_MAC_VER_16:
3861                 break;
3862         default:
3863                 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
3864                 break;
3865         }
3866 }
3867
3868 static void r810x_pll_power_up(struct rtl8169_private *tp)
3869 {
3870         void __iomem *ioaddr = tp->mmio_addr;
3871
3872         r810x_phy_power_up(tp);
3873
3874         switch (tp->mac_version) {
3875         case RTL_GIGA_MAC_VER_07:
3876         case RTL_GIGA_MAC_VER_08:
3877         case RTL_GIGA_MAC_VER_09:
3878         case RTL_GIGA_MAC_VER_10:
3879         case RTL_GIGA_MAC_VER_13:
3880         case RTL_GIGA_MAC_VER_16:
3881                 break;
3882         default:
3883                 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
3884                 break;
3885         }
3886 }
3887
3888 static void r8168_phy_power_up(struct rtl8169_private *tp)
3889 {
3890         rtl_writephy(tp, 0x1f, 0x0000);
3891         switch (tp->mac_version) {
3892         case RTL_GIGA_MAC_VER_11:
3893         case RTL_GIGA_MAC_VER_12:
3894         case RTL_GIGA_MAC_VER_17:
3895         case RTL_GIGA_MAC_VER_18:
3896         case RTL_GIGA_MAC_VER_19:
3897         case RTL_GIGA_MAC_VER_20:
3898         case RTL_GIGA_MAC_VER_21:
3899         case RTL_GIGA_MAC_VER_22:
3900         case RTL_GIGA_MAC_VER_23:
3901         case RTL_GIGA_MAC_VER_24:
3902         case RTL_GIGA_MAC_VER_25:
3903         case RTL_GIGA_MAC_VER_26:
3904         case RTL_GIGA_MAC_VER_27:
3905         case RTL_GIGA_MAC_VER_28:
3906         case RTL_GIGA_MAC_VER_31:
3907                 rtl_writephy(tp, 0x0e, 0x0000);
3908                 break;
3909         default:
3910                 break;
3911         }
3912         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3913 }
3914
3915 static void r8168_phy_power_down(struct rtl8169_private *tp)
3916 {
3917         rtl_writephy(tp, 0x1f, 0x0000);
3918         switch (tp->mac_version) {
3919         case RTL_GIGA_MAC_VER_32:
3920         case RTL_GIGA_MAC_VER_33:
3921                 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
3922                 break;
3923
3924         case RTL_GIGA_MAC_VER_11:
3925         case RTL_GIGA_MAC_VER_12:
3926         case RTL_GIGA_MAC_VER_17:
3927         case RTL_GIGA_MAC_VER_18:
3928         case RTL_GIGA_MAC_VER_19:
3929         case RTL_GIGA_MAC_VER_20:
3930         case RTL_GIGA_MAC_VER_21:
3931         case RTL_GIGA_MAC_VER_22:
3932         case RTL_GIGA_MAC_VER_23:
3933         case RTL_GIGA_MAC_VER_24:
3934         case RTL_GIGA_MAC_VER_25:
3935         case RTL_GIGA_MAC_VER_26:
3936         case RTL_GIGA_MAC_VER_27:
3937         case RTL_GIGA_MAC_VER_28:
3938         case RTL_GIGA_MAC_VER_31:
3939                 rtl_writephy(tp, 0x0e, 0x0200);
3940         default:
3941                 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3942                 break;
3943         }
3944 }
3945
3946 static void r8168_pll_power_down(struct rtl8169_private *tp)
3947 {
3948         void __iomem *ioaddr = tp->mmio_addr;
3949
3950         if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3951              tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3952              tp->mac_version == RTL_GIGA_MAC_VER_31) &&
3953             r8168dp_check_dash(tp)) {
3954                 return;
3955         }
3956
3957         if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
3958              tp->mac_version == RTL_GIGA_MAC_VER_24) &&
3959             (RTL_R16(CPlusCmd) & ASF)) {
3960                 return;
3961         }
3962
3963         if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3964             tp->mac_version == RTL_GIGA_MAC_VER_33)
3965                 rtl_ephy_write(tp, 0x19, 0xff64);
3966
3967         if (rtl_wol_pll_power_down(tp))
3968                 return;
3969
3970         r8168_phy_power_down(tp);
3971
3972         switch (tp->mac_version) {
3973         case RTL_GIGA_MAC_VER_25:
3974         case RTL_GIGA_MAC_VER_26:
3975         case RTL_GIGA_MAC_VER_27:
3976         case RTL_GIGA_MAC_VER_28:
3977         case RTL_GIGA_MAC_VER_31:
3978         case RTL_GIGA_MAC_VER_32:
3979         case RTL_GIGA_MAC_VER_33:
3980                 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
3981                 break;
3982         }
3983 }
3984
3985 static void r8168_pll_power_up(struct rtl8169_private *tp)
3986 {
3987         void __iomem *ioaddr = tp->mmio_addr;
3988
3989         switch (tp->mac_version) {
3990         case RTL_GIGA_MAC_VER_25:
3991         case RTL_GIGA_MAC_VER_26:
3992         case RTL_GIGA_MAC_VER_27:
3993         case RTL_GIGA_MAC_VER_28:
3994         case RTL_GIGA_MAC_VER_31:
3995         case RTL_GIGA_MAC_VER_32:
3996         case RTL_GIGA_MAC_VER_33:
3997                 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
3998                 break;
3999         }
4000
4001         r8168_phy_power_up(tp);
4002 }
4003
4004 static void rtl_generic_op(struct rtl8169_private *tp,
4005                            void (*op)(struct rtl8169_private *))
4006 {
4007         if (op)
4008                 op(tp);
4009 }
4010
4011 static void rtl_pll_power_down(struct rtl8169_private *tp)
4012 {
4013         rtl_generic_op(tp, tp->pll_power_ops.down);
4014 }
4015
4016 static void rtl_pll_power_up(struct rtl8169_private *tp)
4017 {
4018         rtl_generic_op(tp, tp->pll_power_ops.up);
4019 }
4020
4021 static void rtl_init_pll_power_ops(struct rtl8169_private *tp)
4022 {
4023         struct pll_power_ops *ops = &tp->pll_power_ops;
4024
4025         switch (tp->mac_version) {
4026         case RTL_GIGA_MAC_VER_07:
4027         case RTL_GIGA_MAC_VER_08:
4028         case RTL_GIGA_MAC_VER_09:
4029         case RTL_GIGA_MAC_VER_10:
4030         case RTL_GIGA_MAC_VER_16:
4031         case RTL_GIGA_MAC_VER_29:
4032         case RTL_GIGA_MAC_VER_30:
4033         case RTL_GIGA_MAC_VER_37:
4034         case RTL_GIGA_MAC_VER_39:
4035                 ops->down       = r810x_pll_power_down;
4036                 ops->up         = r810x_pll_power_up;
4037                 break;
4038
4039         case RTL_GIGA_MAC_VER_11:
4040         case RTL_GIGA_MAC_VER_12:
4041         case RTL_GIGA_MAC_VER_17:
4042         case RTL_GIGA_MAC_VER_18:
4043         case RTL_GIGA_MAC_VER_19:
4044         case RTL_GIGA_MAC_VER_20:
4045         case RTL_GIGA_MAC_VER_21:
4046         case RTL_GIGA_MAC_VER_22:
4047         case RTL_GIGA_MAC_VER_23:
4048         case RTL_GIGA_MAC_VER_24:
4049         case RTL_GIGA_MAC_VER_25:
4050         case RTL_GIGA_MAC_VER_26:
4051         case RTL_GIGA_MAC_VER_27:
4052         case RTL_GIGA_MAC_VER_28:
4053         case RTL_GIGA_MAC_VER_31:
4054         case RTL_GIGA_MAC_VER_32:
4055         case RTL_GIGA_MAC_VER_33:
4056         case RTL_GIGA_MAC_VER_34:
4057         case RTL_GIGA_MAC_VER_35:
4058         case RTL_GIGA_MAC_VER_36:
4059         case RTL_GIGA_MAC_VER_38:
4060         case RTL_GIGA_MAC_VER_40:
4061         case RTL_GIGA_MAC_VER_41:
4062                 ops->down       = r8168_pll_power_down;
4063                 ops->up         = r8168_pll_power_up;
4064                 break;
4065
4066         default:
4067                 ops->down       = NULL;
4068                 ops->up         = NULL;
4069                 break;
4070         }
4071 }
4072
4073 static void rtl_init_rxcfg(struct rtl8169_private *tp)
4074 {
4075         void __iomem *ioaddr = tp->mmio_addr;
4076
4077         switch (tp->mac_version) {
4078         case RTL_GIGA_MAC_VER_01:
4079         case RTL_GIGA_MAC_VER_02:
4080         case RTL_GIGA_MAC_VER_03:
4081         case RTL_GIGA_MAC_VER_04:
4082         case RTL_GIGA_MAC_VER_05:
4083         case RTL_GIGA_MAC_VER_06:
4084         case RTL_GIGA_MAC_VER_10:
4085         case RTL_GIGA_MAC_VER_11:
4086         case RTL_GIGA_MAC_VER_12:
4087         case RTL_GIGA_MAC_VER_13:
4088         case RTL_GIGA_MAC_VER_14:
4089         case RTL_GIGA_MAC_VER_15:
4090         case RTL_GIGA_MAC_VER_16:
4091         case RTL_GIGA_MAC_VER_17:
4092                 RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
4093                 break;
4094         case RTL_GIGA_MAC_VER_18:
4095         case RTL_GIGA_MAC_VER_19:
4096         case RTL_GIGA_MAC_VER_20:
4097         case RTL_GIGA_MAC_VER_21:
4098         case RTL_GIGA_MAC_VER_22:
4099         case RTL_GIGA_MAC_VER_23:
4100         case RTL_GIGA_MAC_VER_24:
4101         case RTL_GIGA_MAC_VER_34:
4102                 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
4103                 break;
4104         default:
4105                 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
4106                 break;
4107         }
4108 }
4109
4110 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4111 {
4112         tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
4113 }
4114
4115 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
4116 {
4117         void __iomem *ioaddr = tp->mmio_addr;
4118
4119         RTL_W8(Cfg9346, Cfg9346_Unlock);
4120         rtl_generic_op(tp, tp->jumbo_ops.enable);
4121         RTL_W8(Cfg9346, Cfg9346_Lock);
4122 }
4123
4124 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
4125 {
4126         void __iomem *ioaddr = tp->mmio_addr;
4127
4128         RTL_W8(Cfg9346, Cfg9346_Unlock);
4129         rtl_generic_op(tp, tp->jumbo_ops.disable);
4130         RTL_W8(Cfg9346, Cfg9346_Lock);
4131 }
4132
4133 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
4134 {
4135         void __iomem *ioaddr = tp->mmio_addr;
4136
4137         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4138         RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
4139         rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
4140 }
4141
4142 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
4143 {
4144         void __iomem *ioaddr = tp->mmio_addr;
4145
4146         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4147         RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
4148         rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
4149 }
4150
4151 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
4152 {
4153         void __iomem *ioaddr = tp->mmio_addr;
4154
4155         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4156 }
4157
4158 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
4159 {
4160         void __iomem *ioaddr = tp->mmio_addr;
4161
4162         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4163 }
4164
4165 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
4166 {
4167         void __iomem *ioaddr = tp->mmio_addr;
4168
4169         RTL_W8(MaxTxPacketSize, 0x3f);
4170         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4171         RTL_W8(Config4, RTL_R8(Config4) | 0x01);
4172         rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
4173 }
4174
4175 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
4176 {
4177         void __iomem *ioaddr = tp->mmio_addr;
4178
4179         RTL_W8(MaxTxPacketSize, 0x0c);
4180         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4181         RTL_W8(Config4, RTL_R8(Config4) & ~0x01);
4182         rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
4183 }
4184
4185 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
4186 {
4187         rtl_tx_performance_tweak(tp->pci_dev,
4188                 (0x2 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4189 }
4190
4191 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
4192 {
4193         rtl_tx_performance_tweak(tp->pci_dev,
4194                 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4195 }
4196
4197 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
4198 {
4199         void __iomem *ioaddr = tp->mmio_addr;
4200
4201         r8168b_0_hw_jumbo_enable(tp);
4202
4203         RTL_W8(Config4, RTL_R8(Config4) | (1 << 0));
4204 }
4205
4206 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
4207 {
4208         void __iomem *ioaddr = tp->mmio_addr;
4209
4210         r8168b_0_hw_jumbo_disable(tp);
4211
4212         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
4213 }
4214
4215 static void rtl_init_jumbo_ops(struct rtl8169_private *tp)
4216 {
4217         struct jumbo_ops *ops = &tp->jumbo_ops;
4218
4219         switch (tp->mac_version) {
4220         case RTL_GIGA_MAC_VER_11:
4221                 ops->disable    = r8168b_0_hw_jumbo_disable;
4222                 ops->enable     = r8168b_0_hw_jumbo_enable;
4223                 break;
4224         case RTL_GIGA_MAC_VER_12:
4225         case RTL_GIGA_MAC_VER_17:
4226                 ops->disable    = r8168b_1_hw_jumbo_disable;
4227                 ops->enable     = r8168b_1_hw_jumbo_enable;
4228                 break;
4229         case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
4230         case RTL_GIGA_MAC_VER_19:
4231         case RTL_GIGA_MAC_VER_20:
4232         case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
4233         case RTL_GIGA_MAC_VER_22:
4234         case RTL_GIGA_MAC_VER_23:
4235         case RTL_GIGA_MAC_VER_24:
4236         case RTL_GIGA_MAC_VER_25:
4237         case RTL_GIGA_MAC_VER_26:
4238                 ops->disable    = r8168c_hw_jumbo_disable;
4239                 ops->enable     = r8168c_hw_jumbo_enable;
4240                 break;
4241         case RTL_GIGA_MAC_VER_27:
4242         case RTL_GIGA_MAC_VER_28:
4243                 ops->disable    = r8168dp_hw_jumbo_disable;
4244                 ops->enable     = r8168dp_hw_jumbo_enable;
4245                 break;
4246         case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
4247         case RTL_GIGA_MAC_VER_32:
4248         case RTL_GIGA_MAC_VER_33:
4249         case RTL_GIGA_MAC_VER_34:
4250                 ops->disable    = r8168e_hw_jumbo_disable;
4251                 ops->enable     = r8168e_hw_jumbo_enable;
4252                 break;
4253
4254         /*
4255          * No action needed for jumbo frames with 8169.
4256          * No jumbo for 810x at all.
4257          */
4258         case RTL_GIGA_MAC_VER_40:
4259         case RTL_GIGA_MAC_VER_41:
4260         default:
4261                 ops->disable    = NULL;
4262                 ops->enable     = NULL;
4263                 break;
4264         }
4265 }
4266
4267 DECLARE_RTL_COND(rtl_chipcmd_cond)
4268 {
4269         void __iomem *ioaddr = tp->mmio_addr;
4270
4271         return RTL_R8(ChipCmd) & CmdReset;
4272 }
4273
4274 static void rtl_hw_reset(struct rtl8169_private *tp)
4275 {
4276         void __iomem *ioaddr = tp->mmio_addr;
4277
4278         RTL_W8(ChipCmd, CmdReset);
4279
4280         rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
4281 }
4282
4283 static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
4284 {
4285         struct rtl_fw *rtl_fw;
4286         const char *name;
4287         int rc = -ENOMEM;
4288
4289         name = rtl_lookup_firmware_name(tp);
4290         if (!name)
4291                 goto out_no_firmware;
4292
4293         rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
4294         if (!rtl_fw)
4295                 goto err_warn;
4296
4297         rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
4298         if (rc < 0)
4299                 goto err_free;
4300
4301         rc = rtl_check_firmware(tp, rtl_fw);
4302         if (rc < 0)
4303                 goto err_release_firmware;
4304
4305         tp->rtl_fw = rtl_fw;
4306 out:
4307         return;
4308
4309 err_release_firmware:
4310         release_firmware(rtl_fw->fw);
4311 err_free:
4312         kfree(rtl_fw);
4313 err_warn:
4314         netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
4315                    name, rc);
4316 out_no_firmware:
4317         tp->rtl_fw = NULL;
4318         goto out;
4319 }
4320
4321 static void rtl_request_firmware(struct rtl8169_private *tp)
4322 {
4323         if (IS_ERR(tp->rtl_fw))
4324                 rtl_request_uncached_firmware(tp);
4325 }
4326
4327 static void rtl_rx_close(struct rtl8169_private *tp)
4328 {
4329         void __iomem *ioaddr = tp->mmio_addr;
4330
4331         RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
4332 }
4333
4334 DECLARE_RTL_COND(rtl_npq_cond)
4335 {
4336         void __iomem *ioaddr = tp->mmio_addr;
4337
4338         return RTL_R8(TxPoll) & NPQ;
4339 }
4340
4341 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
4342 {
4343         void __iomem *ioaddr = tp->mmio_addr;
4344
4345         return RTL_R32(TxConfig) & TXCFG_EMPTY;
4346 }
4347
4348 static void rtl8169_hw_reset(struct rtl8169_private *tp)
4349 {
4350         void __iomem *ioaddr = tp->mmio_addr;
4351
4352         /* Disable interrupts */
4353         rtl8169_irq_mask_and_ack(tp);
4354
4355         rtl_rx_close(tp);
4356
4357         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4358             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4359             tp->mac_version == RTL_GIGA_MAC_VER_31) {
4360                 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
4361         } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
4362                    tp->mac_version == RTL_GIGA_MAC_VER_35 ||
4363                    tp->mac_version == RTL_GIGA_MAC_VER_36 ||
4364                    tp->mac_version == RTL_GIGA_MAC_VER_37 ||
4365                    tp->mac_version == RTL_GIGA_MAC_VER_40 ||
4366                    tp->mac_version == RTL_GIGA_MAC_VER_41 ||
4367                    tp->mac_version == RTL_GIGA_MAC_VER_38) {
4368                 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
4369                 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
4370         } else {
4371                 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
4372                 udelay(100);
4373         }
4374
4375         rtl_hw_reset(tp);
4376 }
4377
4378 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
4379 {
4380         void __iomem *ioaddr = tp->mmio_addr;
4381
4382         /* Set DMA burst size and Interframe Gap Time */
4383         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4384                 (InterFrameGap << TxInterFrameGapShift));
4385 }
4386
4387 static void rtl_hw_start(struct net_device *dev)
4388 {
4389         struct rtl8169_private *tp = netdev_priv(dev);
4390
4391         tp->hw_start(dev);
4392
4393         rtl_irq_enable_all(tp);
4394 }
4395
4396 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
4397                                          void __iomem *ioaddr)
4398 {
4399         /*
4400          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4401          * register to be written before TxDescAddrLow to work.
4402          * Switching from MMIO to I/O access fixes the issue as well.
4403          */
4404         RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4405         RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4406         RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4407         RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
4408 }
4409
4410 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
4411 {
4412         u16 cmd;
4413
4414         cmd = RTL_R16(CPlusCmd);
4415         RTL_W16(CPlusCmd, cmd);
4416         return cmd;
4417 }
4418
4419 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
4420 {
4421         /* Low hurts. Let's disable the filtering. */
4422         RTL_W16(RxMaxSize, rx_buf_sz + 1);
4423 }
4424
4425 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
4426 {
4427         static const struct rtl_cfg2_info {
4428                 u32 mac_version;
4429                 u32 clk;
4430                 u32 val;
4431         } cfg2_info [] = {
4432                 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
4433                 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
4434                 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
4435                 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
4436         };
4437         const struct rtl_cfg2_info *p = cfg2_info;
4438         unsigned int i;
4439         u32 clk;
4440
4441         clk = RTL_R8(Config2) & PCI_Clock_66MHz;
4442         for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
4443                 if ((p->mac_version == mac_version) && (p->clk == clk)) {
4444                         RTL_W32(0x7c, p->val);
4445                         break;
4446                 }
4447         }
4448 }
4449
4450 static void rtl_set_rx_mode(struct net_device *dev)
4451 {
4452         struct rtl8169_private *tp = netdev_priv(dev);
4453         void __iomem *ioaddr = tp->mmio_addr;
4454         u32 mc_filter[2];       /* Multicast hash filter */
4455         int rx_mode;
4456         u32 tmp = 0;
4457
4458         if (dev->flags & IFF_PROMISC) {
4459                 /* Unconditionally log net taps. */
4460                 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4461                 rx_mode =
4462                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4463                     AcceptAllPhys;
4464                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4465         } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4466                    (dev->flags & IFF_ALLMULTI)) {
4467                 /* Too many to filter perfectly -- accept all multicasts. */
4468                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4469                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4470         } else {
4471                 struct netdev_hw_addr *ha;
4472
4473                 rx_mode = AcceptBroadcast | AcceptMyPhys;
4474                 mc_filter[1] = mc_filter[0] = 0;
4475                 netdev_for_each_mc_addr(ha, dev) {
4476                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4477                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4478                         rx_mode |= AcceptMulticast;
4479                 }
4480         }
4481
4482         if (dev->features & NETIF_F_RXALL)
4483                 rx_mode |= (AcceptErr | AcceptRunt);
4484
4485         tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
4486
4487         if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4488                 u32 data = mc_filter[0];
4489
4490                 mc_filter[0] = swab32(mc_filter[1]);
4491                 mc_filter[1] = swab32(data);
4492         }
4493
4494         if (tp->mac_version == RTL_GIGA_MAC_VER_35)
4495                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4496
4497         RTL_W32(MAR0 + 4, mc_filter[1]);
4498         RTL_W32(MAR0 + 0, mc_filter[0]);
4499
4500         RTL_W32(RxConfig, tmp);
4501 }
4502
4503 static void rtl_hw_start_8169(struct net_device *dev)
4504 {
4505         struct rtl8169_private *tp = netdev_priv(dev);
4506         void __iomem *ioaddr = tp->mmio_addr;
4507         struct pci_dev *pdev = tp->pci_dev;
4508
4509         if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
4510                 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
4511                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
4512         }
4513
4514         RTL_W8(Cfg9346, Cfg9346_Unlock);
4515         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4516             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4517             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4518             tp->mac_version == RTL_GIGA_MAC_VER_04)
4519                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4520
4521         rtl_init_rxcfg(tp);
4522
4523         RTL_W8(EarlyTxThres, NoEarlyTx);
4524
4525         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4526
4527         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4528             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4529             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4530             tp->mac_version == RTL_GIGA_MAC_VER_04)
4531                 rtl_set_rx_tx_config_registers(tp);
4532
4533         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
4534
4535         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4536             tp->mac_version == RTL_GIGA_MAC_VER_03) {
4537                 dprintk("Set MAC Reg C+CR Offset 0xE0. "
4538                         "Bit-3 and bit-14 MUST be 1\n");
4539                 tp->cp_cmd |= (1 << 14);
4540         }
4541
4542         RTL_W16(CPlusCmd, tp->cp_cmd);
4543
4544         rtl8169_set_magic_reg(ioaddr, tp->mac_version);
4545
4546         /*
4547          * Undocumented corner. Supposedly:
4548          * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4549          */
4550         RTL_W16(IntrMitigate, 0x0000);
4551
4552         rtl_set_rx_tx_desc_registers(tp, ioaddr);
4553
4554         if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
4555             tp->mac_version != RTL_GIGA_MAC_VER_02 &&
4556             tp->mac_version != RTL_GIGA_MAC_VER_03 &&
4557             tp->mac_version != RTL_GIGA_MAC_VER_04) {
4558                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4559                 rtl_set_rx_tx_config_registers(tp);
4560         }
4561
4562         RTL_W8(Cfg9346, Cfg9346_Lock);
4563
4564         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4565         RTL_R8(IntrMask);
4566
4567         RTL_W32(RxMissed, 0);
4568
4569         rtl_set_rx_mode(dev);
4570
4571         /* no early-rx interrupts */
4572         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
4573 }
4574
4575 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
4576 {
4577         if (tp->csi_ops.write)
4578                 tp->csi_ops.write(tp, addr, value);
4579 }
4580
4581 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
4582 {
4583         return tp->csi_ops.read ? tp->csi_ops.read(tp, addr) : ~0;
4584 }
4585
4586 static void rtl_csi_access_enable(struct rtl8169_private *tp, u32 bits)
4587 {
4588         u32 csi;
4589
4590         csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
4591         rtl_csi_write(tp, 0x070c, csi | bits);
4592 }
4593
4594 static void rtl_csi_access_enable_1(struct rtl8169_private *tp)
4595 {
4596         rtl_csi_access_enable(tp, 0x17000000);
4597 }
4598
4599 static void rtl_csi_access_enable_2(struct rtl8169_private *tp)
4600 {
4601         rtl_csi_access_enable(tp, 0x27000000);
4602 }
4603
4604 DECLARE_RTL_COND(rtl_csiar_cond)
4605 {
4606         void __iomem *ioaddr = tp->mmio_addr;
4607
4608         return RTL_R32(CSIAR) & CSIAR_FLAG;
4609 }
4610
4611 static void r8169_csi_write(struct rtl8169_private *tp, int addr, int value)
4612 {
4613         void __iomem *ioaddr = tp->mmio_addr;
4614
4615         RTL_W32(CSIDR, value);
4616         RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4617                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
4618
4619         rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
4620 }
4621
4622 static u32 r8169_csi_read(struct rtl8169_private *tp, int addr)
4623 {
4624         void __iomem *ioaddr = tp->mmio_addr;
4625
4626         RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
4627                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
4628
4629         return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4630                 RTL_R32(CSIDR) : ~0;
4631 }
4632
4633 static void r8402_csi_write(struct rtl8169_private *tp, int addr, int value)
4634 {
4635         void __iomem *ioaddr = tp->mmio_addr;
4636
4637         RTL_W32(CSIDR, value);
4638         RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4639                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
4640                 CSIAR_FUNC_NIC);
4641
4642         rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
4643 }
4644
4645 static u32 r8402_csi_read(struct rtl8169_private *tp, int addr)
4646 {
4647         void __iomem *ioaddr = tp->mmio_addr;
4648
4649         RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC |
4650                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
4651
4652         return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4653                 RTL_R32(CSIDR) : ~0;
4654 }
4655
4656 static void rtl_init_csi_ops(struct rtl8169_private *tp)
4657 {
4658         struct csi_ops *ops = &tp->csi_ops;
4659
4660         switch (tp->mac_version) {
4661         case RTL_GIGA_MAC_VER_01:
4662         case RTL_GIGA_MAC_VER_02:
4663         case RTL_GIGA_MAC_VER_03:
4664         case RTL_GIGA_MAC_VER_04:
4665         case RTL_GIGA_MAC_VER_05:
4666         case RTL_GIGA_MAC_VER_06:
4667         case RTL_GIGA_MAC_VER_10:
4668         case RTL_GIGA_MAC_VER_11:
4669         case RTL_GIGA_MAC_VER_12:
4670         case RTL_GIGA_MAC_VER_13:
4671         case RTL_GIGA_MAC_VER_14:
4672         case RTL_GIGA_MAC_VER_15:
4673         case RTL_GIGA_MAC_VER_16:
4674         case RTL_GIGA_MAC_VER_17:
4675                 ops->write      = NULL;
4676                 ops->read       = NULL;
4677                 break;
4678
4679         case RTL_GIGA_MAC_VER_37:
4680         case RTL_GIGA_MAC_VER_38:
4681                 ops->write      = r8402_csi_write;
4682                 ops->read       = r8402_csi_read;
4683                 break;
4684
4685         default:
4686                 ops->write      = r8169_csi_write;
4687                 ops->read       = r8169_csi_read;
4688                 break;
4689         }
4690 }
4691
4692 struct ephy_info {
4693         unsigned int offset;
4694         u16 mask;
4695         u16 bits;
4696 };
4697
4698 static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e,
4699                           int len)
4700 {
4701         u16 w;
4702
4703         while (len-- > 0) {
4704                 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
4705                 rtl_ephy_write(tp, e->offset, w);
4706                 e++;
4707         }
4708 }
4709
4710 static void rtl_disable_clock_request(struct pci_dev *pdev)
4711 {
4712         pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL,
4713                                    PCI_EXP_LNKCTL_CLKREQ_EN);
4714 }
4715
4716 static void rtl_enable_clock_request(struct pci_dev *pdev)
4717 {
4718         pcie_capability_set_word(pdev, PCI_EXP_LNKCTL,
4719                                  PCI_EXP_LNKCTL_CLKREQ_EN);
4720 }
4721
4722 #define R8168_CPCMD_QUIRK_MASK (\
4723         EnableBist | \
4724         Mac_dbgo_oe | \
4725         Force_half_dup | \
4726         Force_rxflow_en | \
4727         Force_txflow_en | \
4728         Cxpl_dbg_sel | \
4729         ASF | \
4730         PktCntrDisable | \
4731         Mac_dbgo_sel)
4732
4733 static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
4734 {
4735         void __iomem *ioaddr = tp->mmio_addr;
4736         struct pci_dev *pdev = tp->pci_dev;
4737
4738         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4739
4740         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4741
4742         if (tp->dev->mtu <= ETH_DATA_LEN) {
4743                 rtl_tx_performance_tweak(pdev, (0x5 << MAX_READ_REQUEST_SHIFT) |
4744                                          PCI_EXP_DEVCTL_NOSNOOP_EN);
4745         }
4746 }
4747
4748 static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
4749 {
4750         void __iomem *ioaddr = tp->mmio_addr;
4751
4752         rtl_hw_start_8168bb(tp);
4753
4754         RTL_W8(MaxTxPacketSize, TxPacketMax);
4755
4756         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
4757 }
4758
4759 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
4760 {
4761         void __iomem *ioaddr = tp->mmio_addr;
4762         struct pci_dev *pdev = tp->pci_dev;
4763
4764         RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
4765
4766         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4767
4768         if (tp->dev->mtu <= ETH_DATA_LEN)
4769                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4770
4771         rtl_disable_clock_request(pdev);
4772
4773         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4774 }
4775
4776 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
4777 {
4778         static const struct ephy_info e_info_8168cp[] = {
4779                 { 0x01, 0,      0x0001 },
4780                 { 0x02, 0x0800, 0x1000 },
4781                 { 0x03, 0,      0x0042 },
4782                 { 0x06, 0x0080, 0x0000 },
4783                 { 0x07, 0,      0x2000 }
4784         };
4785
4786         rtl_csi_access_enable_2(tp);
4787
4788         rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
4789
4790         __rtl_hw_start_8168cp(tp);
4791 }
4792
4793 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
4794 {
4795         void __iomem *ioaddr = tp->mmio_addr;
4796         struct pci_dev *pdev = tp->pci_dev;
4797
4798         rtl_csi_access_enable_2(tp);
4799
4800         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4801
4802         if (tp->dev->mtu <= ETH_DATA_LEN)
4803                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4804
4805         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4806 }
4807
4808 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
4809 {
4810         void __iomem *ioaddr = tp->mmio_addr;
4811         struct pci_dev *pdev = tp->pci_dev;
4812
4813         rtl_csi_access_enable_2(tp);
4814
4815         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4816
4817         /* Magic. */
4818         RTL_W8(DBG_REG, 0x20);
4819
4820         RTL_W8(MaxTxPacketSize, TxPacketMax);
4821
4822         if (tp->dev->mtu <= ETH_DATA_LEN)
4823                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4824
4825         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4826 }
4827
4828 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
4829 {
4830         void __iomem *ioaddr = tp->mmio_addr;
4831         static const struct ephy_info e_info_8168c_1[] = {
4832                 { 0x02, 0x0800, 0x1000 },
4833                 { 0x03, 0,      0x0002 },
4834                 { 0x06, 0x0080, 0x0000 }
4835         };
4836
4837         rtl_csi_access_enable_2(tp);
4838
4839         RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4840
4841         rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
4842
4843         __rtl_hw_start_8168cp(tp);
4844 }
4845
4846 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
4847 {
4848         static const struct ephy_info e_info_8168c_2[] = {
4849                 { 0x01, 0,      0x0001 },
4850                 { 0x03, 0x0400, 0x0220 }
4851         };
4852
4853         rtl_csi_access_enable_2(tp);
4854
4855         rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
4856
4857         __rtl_hw_start_8168cp(tp);
4858 }
4859
4860 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
4861 {
4862         rtl_hw_start_8168c_2(tp);
4863 }
4864
4865 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
4866 {
4867         rtl_csi_access_enable_2(tp);
4868
4869         __rtl_hw_start_8168cp(tp);
4870 }
4871
4872 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
4873 {
4874         void __iomem *ioaddr = tp->mmio_addr;
4875         struct pci_dev *pdev = tp->pci_dev;
4876
4877         rtl_csi_access_enable_2(tp);
4878
4879         rtl_disable_clock_request(pdev);
4880
4881         RTL_W8(MaxTxPacketSize, TxPacketMax);
4882
4883         if (tp->dev->mtu <= ETH_DATA_LEN)
4884                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4885
4886         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4887 }
4888
4889 static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
4890 {
4891         void __iomem *ioaddr = tp->mmio_addr;
4892         struct pci_dev *pdev = tp->pci_dev;
4893
4894         rtl_csi_access_enable_1(tp);
4895
4896         if (tp->dev->mtu <= ETH_DATA_LEN)
4897                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4898
4899         RTL_W8(MaxTxPacketSize, TxPacketMax);
4900
4901         rtl_disable_clock_request(pdev);
4902 }
4903
4904 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
4905 {
4906         void __iomem *ioaddr = tp->mmio_addr;
4907         struct pci_dev *pdev = tp->pci_dev;
4908         static const struct ephy_info e_info_8168d_4[] = {
4909                 { 0x0b, ~0,     0x48 },
4910                 { 0x19, 0x20,   0x50 },
4911                 { 0x0c, ~0,     0x20 }
4912         };
4913         int i;
4914
4915         rtl_csi_access_enable_1(tp);
4916
4917         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4918
4919         RTL_W8(MaxTxPacketSize, TxPacketMax);
4920
4921         for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
4922                 const struct ephy_info *e = e_info_8168d_4 + i;
4923                 u16 w;
4924
4925                 w = rtl_ephy_read(tp, e->offset);
4926                 rtl_ephy_write(tp, 0x03, (w & e->mask) | e->bits);
4927         }
4928
4929         rtl_enable_clock_request(pdev);
4930 }
4931
4932 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
4933 {
4934         void __iomem *ioaddr = tp->mmio_addr;
4935         struct pci_dev *pdev = tp->pci_dev;
4936         static const struct ephy_info e_info_8168e_1[] = {
4937                 { 0x00, 0x0200, 0x0100 },
4938                 { 0x00, 0x0000, 0x0004 },
4939                 { 0x06, 0x0002, 0x0001 },
4940                 { 0x06, 0x0000, 0x0030 },
4941                 { 0x07, 0x0000, 0x2000 },
4942                 { 0x00, 0x0000, 0x0020 },
4943                 { 0x03, 0x5800, 0x2000 },
4944                 { 0x03, 0x0000, 0x0001 },
4945                 { 0x01, 0x0800, 0x1000 },
4946                 { 0x07, 0x0000, 0x4000 },
4947                 { 0x1e, 0x0000, 0x2000 },
4948                 { 0x19, 0xffff, 0xfe6c },
4949                 { 0x0a, 0x0000, 0x0040 }
4950         };
4951
4952         rtl_csi_access_enable_2(tp);
4953
4954         rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
4955
4956         if (tp->dev->mtu <= ETH_DATA_LEN)
4957                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4958
4959         RTL_W8(MaxTxPacketSize, TxPacketMax);
4960
4961         rtl_disable_clock_request(pdev);
4962
4963         /* Reset tx FIFO pointer */
4964         RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
4965         RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
4966
4967         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4968 }
4969
4970 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
4971 {
4972         void __iomem *ioaddr = tp->mmio_addr;
4973         struct pci_dev *pdev = tp->pci_dev;
4974         static const struct ephy_info e_info_8168e_2[] = {
4975                 { 0x09, 0x0000, 0x0080 },
4976                 { 0x19, 0x0000, 0x0224 }
4977         };
4978
4979         rtl_csi_access_enable_1(tp);
4980
4981         rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
4982
4983         if (tp->dev->mtu <= ETH_DATA_LEN)
4984                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4985
4986         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4987         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4988         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
4989         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
4990         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
4991         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
4992         rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4993         rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
4994
4995         RTL_W8(MaxTxPacketSize, EarlySize);
4996
4997         rtl_disable_clock_request(pdev);
4998
4999         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5000         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5001
5002         /* Adjust EEE LED frequency */
5003         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5004
5005         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5006         RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
5007         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
5008 }
5009
5010 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
5011 {
5012         void __iomem *ioaddr = tp->mmio_addr;
5013         struct pci_dev *pdev = tp->pci_dev;
5014
5015         rtl_csi_access_enable_2(tp);
5016
5017         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5018
5019         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5020         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5021         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5022         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5023         rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5024         rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5025         rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5026         rtl_w1w0_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5027         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5028         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
5029
5030         RTL_W8(MaxTxPacketSize, EarlySize);
5031
5032         rtl_disable_clock_request(pdev);
5033
5034         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5035         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5036         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5037         RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
5038         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
5039 }
5040
5041 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
5042 {
5043         void __iomem *ioaddr = tp->mmio_addr;
5044         static const struct ephy_info e_info_8168f_1[] = {
5045                 { 0x06, 0x00c0, 0x0020 },
5046                 { 0x08, 0x0001, 0x0002 },
5047                 { 0x09, 0x0000, 0x0080 },
5048                 { 0x19, 0x0000, 0x0224 }
5049         };
5050
5051         rtl_hw_start_8168f(tp);
5052
5053         rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5054
5055         rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5056
5057         /* Adjust EEE LED frequency */
5058         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5059 }
5060
5061 static void rtl_hw_start_8411(struct rtl8169_private *tp)
5062 {
5063         static const struct ephy_info e_info_8168f_1[] = {
5064                 { 0x06, 0x00c0, 0x0020 },
5065                 { 0x0f, 0xffff, 0x5200 },
5066                 { 0x1e, 0x0000, 0x4000 },
5067                 { 0x19, 0x0000, 0x0224 }
5068         };
5069
5070         rtl_hw_start_8168f(tp);
5071
5072         rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5073
5074         rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC);
5075 }
5076
5077 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
5078 {
5079         void __iomem *ioaddr = tp->mmio_addr;
5080         struct pci_dev *pdev = tp->pci_dev;
5081
5082         rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC);
5083         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5084         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5085         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5086
5087         rtl_csi_access_enable_1(tp);
5088
5089         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5090
5091         rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5092         rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5093
5094         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5095         RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
5096         RTL_W8(MaxTxPacketSize, EarlySize);
5097
5098         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5099         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5100
5101         /* Adjust EEE LED frequency */
5102         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5103
5104         rtl_w1w0_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x02, ERIAR_EXGMAC);
5105 }
5106
5107 static void rtl_hw_start_8168(struct net_device *dev)
5108 {
5109         struct rtl8169_private *tp = netdev_priv(dev);
5110         void __iomem *ioaddr = tp->mmio_addr;
5111
5112         RTL_W8(Cfg9346, Cfg9346_Unlock);
5113
5114         RTL_W8(MaxTxPacketSize, TxPacketMax);
5115
5116         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
5117
5118         tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
5119
5120         RTL_W16(CPlusCmd, tp->cp_cmd);
5121
5122         RTL_W16(IntrMitigate, 0x5151);
5123
5124         /* Work around for RxFIFO overflow. */
5125         if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
5126                 tp->event_slow |= RxFIFOOver | PCSTimeout;
5127                 tp->event_slow &= ~RxOverflow;
5128         }
5129
5130         rtl_set_rx_tx_desc_registers(tp, ioaddr);
5131
5132         rtl_set_rx_mode(dev);
5133
5134         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
5135                 (InterFrameGap << TxInterFrameGapShift));
5136
5137         RTL_R8(IntrMask);
5138
5139         switch (tp->mac_version) {
5140         case RTL_GIGA_MAC_VER_11:
5141                 rtl_hw_start_8168bb(tp);
5142                 break;
5143
5144         case RTL_GIGA_MAC_VER_12:
5145         case RTL_GIGA_MAC_VER_17:
5146                 rtl_hw_start_8168bef(tp);
5147                 break;
5148
5149         case RTL_GIGA_MAC_VER_18:
5150                 rtl_hw_start_8168cp_1(tp);
5151                 break;
5152
5153         case RTL_GIGA_MAC_VER_19:
5154                 rtl_hw_start_8168c_1(tp);
5155                 break;
5156
5157         case RTL_GIGA_MAC_VER_20:
5158                 rtl_hw_start_8168c_2(tp);
5159                 break;
5160
5161         case RTL_GIGA_MAC_VER_21:
5162                 rtl_hw_start_8168c_3(tp);
5163                 break;
5164
5165         case RTL_GIGA_MAC_VER_22:
5166                 rtl_hw_start_8168c_4(tp);
5167                 break;
5168
5169         case RTL_GIGA_MAC_VER_23:
5170                 rtl_hw_start_8168cp_2(tp);
5171                 break;
5172
5173         case RTL_GIGA_MAC_VER_24:
5174                 rtl_hw_start_8168cp_3(tp);
5175                 break;
5176
5177         case RTL_GIGA_MAC_VER_25:
5178         case RTL_GIGA_MAC_VER_26:
5179         case RTL_GIGA_MAC_VER_27:
5180                 rtl_hw_start_8168d(tp);
5181                 break;
5182
5183         case RTL_GIGA_MAC_VER_28:
5184                 rtl_hw_start_8168d_4(tp);
5185                 break;
5186
5187         case RTL_GIGA_MAC_VER_31:
5188                 rtl_hw_start_8168dp(tp);
5189                 break;
5190
5191         case RTL_GIGA_MAC_VER_32:
5192         case RTL_GIGA_MAC_VER_33:
5193                 rtl_hw_start_8168e_1(tp);
5194                 break;
5195         case RTL_GIGA_MAC_VER_34:
5196                 rtl_hw_start_8168e_2(tp);
5197                 break;
5198
5199         case RTL_GIGA_MAC_VER_35:
5200         case RTL_GIGA_MAC_VER_36:
5201                 rtl_hw_start_8168f_1(tp);
5202                 break;
5203
5204         case RTL_GIGA_MAC_VER_38:
5205                 rtl_hw_start_8411(tp);
5206                 break;
5207
5208         case RTL_GIGA_MAC_VER_40:
5209         case RTL_GIGA_MAC_VER_41:
5210                 rtl_hw_start_8168g_1(tp);
5211                 break;
5212
5213         default:
5214                 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
5215                         dev->name, tp->mac_version);
5216                 break;
5217         }
5218
5219         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5220
5221         RTL_W8(Cfg9346, Cfg9346_Lock);
5222
5223         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
5224 }
5225
5226 #define R810X_CPCMD_QUIRK_MASK (\
5227         EnableBist | \
5228         Mac_dbgo_oe | \
5229         Force_half_dup | \
5230         Force_rxflow_en | \
5231         Force_txflow_en | \
5232         Cxpl_dbg_sel | \
5233         ASF | \
5234         PktCntrDisable | \
5235         Mac_dbgo_sel)
5236
5237 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
5238 {
5239         void __iomem *ioaddr = tp->mmio_addr;
5240         struct pci_dev *pdev = tp->pci_dev;
5241         static const struct ephy_info e_info_8102e_1[] = {
5242                 { 0x01, 0, 0x6e65 },
5243                 { 0x02, 0, 0x091f },
5244                 { 0x03, 0, 0xc2f9 },
5245                 { 0x06, 0, 0xafb5 },
5246                 { 0x07, 0, 0x0e00 },
5247                 { 0x19, 0, 0xec80 },
5248                 { 0x01, 0, 0x2e65 },
5249                 { 0x01, 0, 0x6e65 }
5250         };
5251         u8 cfg1;
5252
5253         rtl_csi_access_enable_2(tp);
5254
5255         RTL_W8(DBG_REG, FIX_NAK_1);
5256
5257         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5258
5259         RTL_W8(Config1,
5260                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
5261         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5262
5263         cfg1 = RTL_R8(Config1);
5264         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
5265                 RTL_W8(Config1, cfg1 & ~LEDS0);
5266
5267         rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
5268 }
5269
5270 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
5271 {
5272         void __iomem *ioaddr = tp->mmio_addr;
5273         struct pci_dev *pdev = tp->pci_dev;
5274
5275         rtl_csi_access_enable_2(tp);
5276
5277         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5278
5279         RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
5280         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5281 }
5282
5283 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
5284 {
5285         rtl_hw_start_8102e_2(tp);
5286
5287         rtl_ephy_write(tp, 0x03, 0xc2f9);
5288 }
5289
5290 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
5291 {
5292         void __iomem *ioaddr = tp->mmio_addr;
5293         static const struct ephy_info e_info_8105e_1[] = {
5294                 { 0x07, 0, 0x4000 },
5295                 { 0x19, 0, 0x0200 },
5296                 { 0x19, 0, 0x0020 },
5297                 { 0x1e, 0, 0x2000 },
5298                 { 0x03, 0, 0x0001 },
5299                 { 0x19, 0, 0x0100 },
5300                 { 0x19, 0, 0x0004 },
5301                 { 0x0a, 0, 0x0020 }
5302         };
5303
5304         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5305         RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5306
5307         /* Disable Early Tally Counter */
5308         RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
5309
5310         RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
5311         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5312
5313         rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
5314 }
5315
5316 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
5317 {
5318         rtl_hw_start_8105e_1(tp);
5319         rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
5320 }
5321
5322 static void rtl_hw_start_8402(struct rtl8169_private *tp)
5323 {
5324         void __iomem *ioaddr = tp->mmio_addr;
5325         static const struct ephy_info e_info_8402[] = {
5326                 { 0x19, 0xffff, 0xff64 },
5327                 { 0x1e, 0, 0x4000 }
5328         };
5329
5330         rtl_csi_access_enable_2(tp);
5331
5332         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5333         RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5334
5335         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5336         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5337
5338         rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402));
5339
5340         rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
5341
5342         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
5343         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
5344         rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5345         rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5346         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5347         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5348         rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC);
5349 }
5350
5351 static void rtl_hw_start_8106(struct rtl8169_private *tp)
5352 {
5353         void __iomem *ioaddr = tp->mmio_addr;
5354
5355         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5356         RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5357
5358         RTL_W32(MISC, (RTL_R32(MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
5359         RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
5360         RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
5361 }
5362
5363 static void rtl_hw_start_8101(struct net_device *dev)
5364 {
5365         struct rtl8169_private *tp = netdev_priv(dev);
5366         void __iomem *ioaddr = tp->mmio_addr;
5367         struct pci_dev *pdev = tp->pci_dev;
5368
5369         if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
5370                 tp->event_slow &= ~RxFIFOOver;
5371
5372         if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
5373             tp->mac_version == RTL_GIGA_MAC_VER_16)
5374                 pcie_capability_set_word(pdev, PCI_EXP_DEVCTL,
5375                                          PCI_EXP_DEVCTL_NOSNOOP_EN);
5376
5377         RTL_W8(Cfg9346, Cfg9346_Unlock);
5378
5379         switch (tp->mac_version) {
5380         case RTL_GIGA_MAC_VER_07:
5381                 rtl_hw_start_8102e_1(tp);
5382                 break;
5383
5384         case RTL_GIGA_MAC_VER_08:
5385                 rtl_hw_start_8102e_3(tp);
5386                 break;
5387
5388         case RTL_GIGA_MAC_VER_09:
5389                 rtl_hw_start_8102e_2(tp);
5390                 break;
5391
5392         case RTL_GIGA_MAC_VER_29:
5393                 rtl_hw_start_8105e_1(tp);
5394                 break;
5395         case RTL_GIGA_MAC_VER_30:
5396                 rtl_hw_start_8105e_2(tp);
5397                 break;
5398
5399         case RTL_GIGA_MAC_VER_37:
5400                 rtl_hw_start_8402(tp);
5401                 break;
5402
5403         case RTL_GIGA_MAC_VER_39:
5404                 rtl_hw_start_8106(tp);
5405                 break;
5406         }
5407
5408         RTL_W8(Cfg9346, Cfg9346_Lock);
5409
5410         RTL_W8(MaxTxPacketSize, TxPacketMax);
5411
5412         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
5413
5414         tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
5415         RTL_W16(CPlusCmd, tp->cp_cmd);
5416
5417         RTL_W16(IntrMitigate, 0x0000);
5418
5419         rtl_set_rx_tx_desc_registers(tp, ioaddr);
5420
5421         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5422         rtl_set_rx_tx_config_registers(tp);
5423
5424         RTL_R8(IntrMask);
5425
5426         rtl_set_rx_mode(dev);
5427
5428         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
5429 }
5430
5431 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
5432 {
5433         struct rtl8169_private *tp = netdev_priv(dev);
5434
5435         if (new_mtu < ETH_ZLEN ||
5436             new_mtu > rtl_chip_infos[tp->mac_version].jumbo_max)
5437                 return -EINVAL;
5438
5439         if (new_mtu > ETH_DATA_LEN)
5440                 rtl_hw_jumbo_enable(tp);
5441         else
5442                 rtl_hw_jumbo_disable(tp);
5443
5444         dev->mtu = new_mtu;
5445         netdev_update_features(dev);
5446
5447         return 0;
5448 }
5449
5450 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
5451 {
5452         desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
5453         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
5454 }
5455
5456 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
5457                                      void **data_buff, struct RxDesc *desc)
5458 {
5459         dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
5460                          DMA_FROM_DEVICE);
5461
5462         kfree(*data_buff);
5463         *data_buff = NULL;
5464         rtl8169_make_unusable_by_asic(desc);
5465 }
5466
5467 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
5468 {
5469         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
5470
5471         desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
5472 }
5473
5474 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
5475                                        u32 rx_buf_sz)
5476 {
5477         desc->addr = cpu_to_le64(mapping);
5478         wmb();
5479         rtl8169_mark_to_asic(desc, rx_buf_sz);
5480 }
5481
5482 static inline void *rtl8169_align(void *data)
5483 {
5484         return (void *)ALIGN((long)data, 16);
5485 }
5486
5487 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
5488                                              struct RxDesc *desc)
5489 {
5490         void *data;
5491         dma_addr_t mapping;
5492         struct device *d = &tp->pci_dev->dev;
5493         struct net_device *dev = tp->dev;
5494         int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
5495
5496         data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
5497         if (!data)
5498                 return NULL;
5499
5500         if (rtl8169_align(data) != data) {
5501                 kfree(data);
5502                 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
5503                 if (!data)
5504                         return NULL;
5505         }
5506
5507         mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
5508                                  DMA_FROM_DEVICE);
5509         if (unlikely(dma_mapping_error(d, mapping))) {
5510                 if (net_ratelimit())
5511                         netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
5512                 goto err_out;
5513         }
5514
5515         rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
5516         return data;
5517
5518 err_out:
5519         kfree(data);
5520         return NULL;
5521 }
5522
5523 static void rtl8169_rx_clear(struct rtl8169_private *tp)
5524 {
5525         unsigned int i;
5526
5527         for (i = 0; i < NUM_RX_DESC; i++) {
5528                 if (tp->Rx_databuff[i]) {
5529                         rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
5530                                             tp->RxDescArray + i);
5531                 }
5532         }
5533 }
5534
5535 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
5536 {
5537         desc->opts1 |= cpu_to_le32(RingEnd);
5538 }
5539
5540 static int rtl8169_rx_fill(struct rtl8169_private *tp)
5541 {
5542         unsigned int i;
5543
5544         for (i = 0; i < NUM_RX_DESC; i++) {
5545                 void *data;
5546
5547                 if (tp->Rx_databuff[i])
5548                         continue;
5549
5550                 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
5551                 if (!data) {
5552                         rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
5553                         goto err_out;
5554                 }
5555                 tp->Rx_databuff[i] = data;
5556         }
5557
5558         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
5559         return 0;
5560
5561 err_out:
5562         rtl8169_rx_clear(tp);
5563         return -ENOMEM;
5564 }
5565
5566 static int rtl8169_init_ring(struct net_device *dev)
5567 {
5568         struct rtl8169_private *tp = netdev_priv(dev);
5569
5570         rtl8169_init_ring_indexes(tp);
5571
5572         memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
5573         memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
5574
5575         return rtl8169_rx_fill(tp);
5576 }
5577
5578 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
5579                                  struct TxDesc *desc)
5580 {
5581         unsigned int len = tx_skb->len;
5582
5583         dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
5584
5585         desc->opts1 = 0x00;
5586         desc->opts2 = 0x00;
5587         desc->addr = 0x00;
5588         tx_skb->len = 0;
5589 }
5590
5591 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
5592                                    unsigned int n)
5593 {
5594         unsigned int i;
5595
5596         for (i = 0; i < n; i++) {
5597                 unsigned int entry = (start + i) % NUM_TX_DESC;
5598                 struct ring_info *tx_skb = tp->tx_skb + entry;
5599                 unsigned int len = tx_skb->len;
5600
5601                 if (len) {
5602                         struct sk_buff *skb = tx_skb->skb;
5603
5604                         rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
5605                                              tp->TxDescArray + entry);
5606                         if (skb) {
5607                                 tp->dev->stats.tx_dropped++;
5608                                 dev_kfree_skb(skb);
5609                                 tx_skb->skb = NULL;
5610                         }
5611                 }
5612         }
5613 }
5614
5615 static void rtl8169_tx_clear(struct rtl8169_private *tp)
5616 {
5617         rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
5618         tp->cur_tx = tp->dirty_tx = 0;
5619 }
5620
5621 static void rtl_reset_work(struct rtl8169_private *tp)
5622 {
5623         struct net_device *dev = tp->dev;
5624         int i;
5625
5626         napi_disable(&tp->napi);
5627         netif_stop_queue(dev);
5628         synchronize_sched();
5629
5630         rtl8169_hw_reset(tp);
5631
5632         for (i = 0; i < NUM_RX_DESC; i++)
5633                 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
5634
5635         rtl8169_tx_clear(tp);
5636         rtl8169_init_ring_indexes(tp);
5637
5638         napi_enable(&tp->napi);
5639         rtl_hw_start(dev);
5640         netif_wake_queue(dev);
5641         rtl8169_check_link_status(dev, tp, tp->mmio_addr);
5642 }
5643
5644 static void rtl8169_tx_timeout(struct net_device *dev)
5645 {
5646         struct rtl8169_private *tp = netdev_priv(dev);
5647
5648         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5649 }
5650
5651 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
5652                               u32 *opts)
5653 {
5654         struct skb_shared_info *info = skb_shinfo(skb);
5655         unsigned int cur_frag, entry;
5656         struct TxDesc * uninitialized_var(txd);
5657         struct device *d = &tp->pci_dev->dev;
5658
5659         entry = tp->cur_tx;
5660         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
5661                 const skb_frag_t *frag = info->frags + cur_frag;
5662                 dma_addr_t mapping;
5663                 u32 status, len;
5664                 void *addr;
5665
5666                 entry = (entry + 1) % NUM_TX_DESC;
5667
5668                 txd = tp->TxDescArray + entry;
5669                 len = skb_frag_size(frag);
5670                 addr = skb_frag_address(frag);
5671                 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
5672                 if (unlikely(dma_mapping_error(d, mapping))) {
5673                         if (net_ratelimit())
5674                                 netif_err(tp, drv, tp->dev,
5675                                           "Failed to map TX fragments DMA!\n");
5676                         goto err_out;
5677                 }
5678
5679                 /* Anti gcc 2.95.3 bugware (sic) */
5680                 status = opts[0] | len |
5681                         (RingEnd * !((entry + 1) % NUM_TX_DESC));
5682
5683                 txd->opts1 = cpu_to_le32(status);
5684                 txd->opts2 = cpu_to_le32(opts[1]);
5685                 txd->addr = cpu_to_le64(mapping);
5686
5687                 tp->tx_skb[entry].len = len;
5688         }
5689
5690         if (cur_frag) {
5691                 tp->tx_skb[entry].skb = skb;
5692                 txd->opts1 |= cpu_to_le32(LastFrag);
5693         }
5694
5695         return cur_frag;
5696
5697 err_out:
5698         rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5699         return -EIO;
5700 }
5701
5702 static inline void rtl8169_tso_csum(struct rtl8169_private *tp,
5703                                     struct sk_buff *skb, u32 *opts)
5704 {
5705         const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version;
5706         u32 mss = skb_shinfo(skb)->gso_size;
5707         int offset = info->opts_offset;
5708
5709         if (mss) {
5710                 opts[0] |= TD_LSO;
5711                 opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift;
5712         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5713                 const struct iphdr *ip = ip_hdr(skb);
5714
5715                 if (ip->protocol == IPPROTO_TCP)
5716                         opts[offset] |= info->checksum.tcp;
5717                 else if (ip->protocol == IPPROTO_UDP)
5718                         opts[offset] |= info->checksum.udp;
5719                 else
5720                         WARN_ON_ONCE(1);
5721         }
5722 }
5723
5724 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5725                                       struct net_device *dev)
5726 {
5727         struct rtl8169_private *tp = netdev_priv(dev);
5728         unsigned int entry = tp->cur_tx % NUM_TX_DESC;
5729         struct TxDesc *txd = tp->TxDescArray + entry;
5730         void __iomem *ioaddr = tp->mmio_addr;
5731         struct device *d = &tp->pci_dev->dev;
5732         dma_addr_t mapping;
5733         u32 status, len;
5734         u32 opts[2];
5735         int frags;
5736
5737         if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
5738                 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
5739                 goto err_stop_0;
5740         }
5741
5742         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
5743                 goto err_stop_0;
5744
5745         len = skb_headlen(skb);
5746         mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
5747         if (unlikely(dma_mapping_error(d, mapping))) {
5748                 if (net_ratelimit())
5749                         netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
5750                 goto err_dma_0;
5751         }
5752
5753         tp->tx_skb[entry].len = len;
5754         txd->addr = cpu_to_le64(mapping);
5755
5756         opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb));
5757         opts[0] = DescOwn;
5758
5759         rtl8169_tso_csum(tp, skb, opts);
5760
5761         frags = rtl8169_xmit_frags(tp, skb, opts);
5762         if (frags < 0)
5763                 goto err_dma_1;
5764         else if (frags)
5765                 opts[0] |= FirstFrag;
5766         else {
5767                 opts[0] |= FirstFrag | LastFrag;
5768                 tp->tx_skb[entry].skb = skb;
5769         }
5770
5771         txd->opts2 = cpu_to_le32(opts[1]);
5772
5773         skb_tx_timestamp(skb);
5774
5775         wmb();
5776
5777         /* Anti gcc 2.95.3 bugware (sic) */
5778         status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
5779         txd->opts1 = cpu_to_le32(status);
5780
5781         tp->cur_tx += frags + 1;
5782
5783         wmb();
5784
5785         RTL_W8(TxPoll, NPQ);
5786
5787         mmiowb();
5788
5789         if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
5790                 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
5791                  * not miss a ring update when it notices a stopped queue.
5792                  */
5793                 smp_wmb();
5794                 netif_stop_queue(dev);
5795                 /* Sync with rtl_tx:
5796                  * - publish queue status and cur_tx ring index (write barrier)
5797                  * - refresh dirty_tx ring index (read barrier).
5798                  * May the current thread have a pessimistic view of the ring
5799                  * status and forget to wake up queue, a racing rtl_tx thread
5800                  * can't.
5801                  */
5802                 smp_mb();
5803                 if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
5804                         netif_wake_queue(dev);
5805         }
5806
5807         return NETDEV_TX_OK;
5808
5809 err_dma_1:
5810         rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
5811 err_dma_0:
5812         dev_kfree_skb(skb);
5813         dev->stats.tx_dropped++;
5814         return NETDEV_TX_OK;
5815
5816 err_stop_0:
5817         netif_stop_queue(dev);
5818         dev->stats.tx_dropped++;
5819         return NETDEV_TX_BUSY;
5820 }
5821
5822 static void rtl8169_pcierr_interrupt(struct net_device *dev)
5823 {
5824         struct rtl8169_private *tp = netdev_priv(dev);
5825         struct pci_dev *pdev = tp->pci_dev;
5826         u16 pci_status, pci_cmd;
5827
5828         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
5829         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
5830
5831         netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
5832                   pci_cmd, pci_status);
5833
5834         /*
5835          * The recovery sequence below admits a very elaborated explanation:
5836          * - it seems to work;
5837          * - I did not see what else could be done;
5838          * - it makes iop3xx happy.
5839          *
5840          * Feel free to adjust to your needs.
5841          */
5842         if (pdev->broken_parity_status)
5843                 pci_cmd &= ~PCI_COMMAND_PARITY;
5844         else
5845                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
5846
5847         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
5848
5849         pci_write_config_word(pdev, PCI_STATUS,
5850                 pci_status & (PCI_STATUS_DETECTED_PARITY |
5851                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
5852                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
5853
5854         /* The infamous DAC f*ckup only happens at boot time */
5855         if ((tp->cp_cmd & PCIDAC) && !tp->cur_rx) {
5856                 void __iomem *ioaddr = tp->mmio_addr;
5857
5858                 netif_info(tp, intr, dev, "disabling PCI DAC\n");
5859                 tp->cp_cmd &= ~PCIDAC;
5860                 RTL_W16(CPlusCmd, tp->cp_cmd);
5861                 dev->features &= ~NETIF_F_HIGHDMA;
5862         }
5863
5864         rtl8169_hw_reset(tp);
5865
5866         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5867 }
5868
5869 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
5870 {
5871         unsigned int dirty_tx, tx_left;
5872
5873         dirty_tx = tp->dirty_tx;
5874         smp_rmb();
5875         tx_left = tp->cur_tx - dirty_tx;
5876
5877         while (tx_left > 0) {
5878                 unsigned int entry = dirty_tx % NUM_TX_DESC;
5879                 struct ring_info *tx_skb = tp->tx_skb + entry;
5880                 u32 status;
5881
5882                 rmb();
5883                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
5884                 if (status & DescOwn)
5885                         break;
5886
5887                 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
5888                                      tp->TxDescArray + entry);
5889                 if (status & LastFrag) {
5890                         u64_stats_update_begin(&tp->tx_stats.syncp);
5891                         tp->tx_stats.packets++;
5892                         tp->tx_stats.bytes += tx_skb->skb->len;
5893                         u64_stats_update_end(&tp->tx_stats.syncp);
5894                         dev_kfree_skb(tx_skb->skb);
5895                         tx_skb->skb = NULL;
5896                 }
5897                 dirty_tx++;
5898                 tx_left--;
5899         }
5900
5901         if (tp->dirty_tx != dirty_tx) {
5902                 tp->dirty_tx = dirty_tx;
5903                 /* Sync with rtl8169_start_xmit:
5904                  * - publish dirty_tx ring index (write barrier)
5905                  * - refresh cur_tx ring index and queue status (read barrier)
5906                  * May the current thread miss the stopped queue condition,
5907                  * a racing xmit thread can only have a right view of the
5908                  * ring status.
5909                  */
5910                 smp_mb();
5911                 if (netif_queue_stopped(dev) &&
5912                     TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
5913                         netif_wake_queue(dev);
5914                 }
5915                 /*
5916                  * 8168 hack: TxPoll requests are lost when the Tx packets are
5917                  * too close. Let's kick an extra TxPoll request when a burst
5918                  * of start_xmit activity is detected (if it is not detected,
5919                  * it is slow enough). -- FR
5920                  */
5921                 if (tp->cur_tx != dirty_tx) {
5922                         void __iomem *ioaddr = tp->mmio_addr;
5923
5924                         RTL_W8(TxPoll, NPQ);
5925                 }
5926         }
5927 }
5928
5929 static inline int rtl8169_fragmented_frame(u32 status)
5930 {
5931         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
5932 }
5933
5934 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
5935 {
5936         u32 status = opts1 & RxProtoMask;
5937
5938         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
5939             ((status == RxProtoUDP) && !(opts1 & UDPFail)))
5940                 skb->ip_summed = CHECKSUM_UNNECESSARY;
5941         else
5942                 skb_checksum_none_assert(skb);
5943 }
5944
5945 static struct sk_buff *rtl8169_try_rx_copy(void *data,
5946                                            struct rtl8169_private *tp,
5947                                            int pkt_size,
5948                                            dma_addr_t addr)
5949 {
5950         struct sk_buff *skb;
5951         struct device *d = &tp->pci_dev->dev;
5952
5953         data = rtl8169_align(data);
5954         dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
5955         prefetch(data);
5956         skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
5957         if (skb)
5958                 memcpy(skb->data, data, pkt_size);
5959         dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
5960
5961         return skb;
5962 }
5963
5964 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
5965 {
5966         unsigned int cur_rx, rx_left;
5967         unsigned int count;
5968
5969         cur_rx = tp->cur_rx;
5970
5971         for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
5972                 unsigned int entry = cur_rx % NUM_RX_DESC;
5973                 struct RxDesc *desc = tp->RxDescArray + entry;
5974                 u32 status;
5975
5976                 rmb();
5977                 status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
5978
5979                 if (status & DescOwn)
5980                         break;
5981                 if (unlikely(status & RxRES)) {
5982                         netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
5983                                    status);
5984                         dev->stats.rx_errors++;
5985                         if (status & (RxRWT | RxRUNT))
5986                                 dev->stats.rx_length_errors++;
5987                         if (status & RxCRC)
5988                                 dev->stats.rx_crc_errors++;
5989                         if (status & RxFOVF) {
5990                                 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5991                                 dev->stats.rx_fifo_errors++;
5992                         }
5993                         if ((status & (RxRUNT | RxCRC)) &&
5994                             !(status & (RxRWT | RxFOVF)) &&
5995                             (dev->features & NETIF_F_RXALL))
5996                                 goto process_pkt;
5997                 } else {
5998                         struct sk_buff *skb;
5999                         dma_addr_t addr;
6000                         int pkt_size;
6001
6002 process_pkt:
6003                         addr = le64_to_cpu(desc->addr);
6004                         if (likely(!(dev->features & NETIF_F_RXFCS)))
6005                                 pkt_size = (status & 0x00003fff) - 4;
6006                         else
6007                                 pkt_size = status & 0x00003fff;
6008
6009                         /*
6010                          * The driver does not support incoming fragmented
6011                          * frames. They are seen as a symptom of over-mtu
6012                          * sized frames.
6013                          */
6014                         if (unlikely(rtl8169_fragmented_frame(status))) {
6015                                 dev->stats.rx_dropped++;
6016                                 dev->stats.rx_length_errors++;
6017                                 goto release_descriptor;
6018                         }
6019
6020                         skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
6021                                                   tp, pkt_size, addr);
6022                         if (!skb) {
6023                                 dev->stats.rx_dropped++;
6024                                 goto release_descriptor;
6025                         }
6026
6027                         rtl8169_rx_csum(skb, status);
6028                         skb_put(skb, pkt_size);
6029                         skb->protocol = eth_type_trans(skb, dev);
6030
6031                         rtl8169_rx_vlan_tag(desc, skb);
6032
6033                         napi_gro_receive(&tp->napi, skb);
6034
6035                         u64_stats_update_begin(&tp->rx_stats.syncp);
6036                         tp->rx_stats.packets++;
6037                         tp->rx_stats.bytes += pkt_size;
6038                         u64_stats_update_end(&tp->rx_stats.syncp);
6039                 }
6040 release_descriptor:
6041                 desc->opts2 = 0;
6042                 wmb();
6043                 rtl8169_mark_to_asic(desc, rx_buf_sz);
6044         }
6045
6046         count = cur_rx - tp->cur_rx;
6047         tp->cur_rx = cur_rx;
6048
6049         return count;
6050 }
6051
6052 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
6053 {
6054         struct net_device *dev = dev_instance;
6055         struct rtl8169_private *tp = netdev_priv(dev);
6056         int handled = 0;
6057         u16 status;
6058
6059         status = rtl_get_events(tp);
6060         if (status && status != 0xffff) {
6061                 status &= RTL_EVENT_NAPI | tp->event_slow;
6062                 if (status) {
6063                         handled = 1;
6064
6065                         rtl_irq_disable(tp);
6066                         napi_schedule(&tp->napi);
6067                 }
6068         }
6069         return IRQ_RETVAL(handled);
6070 }
6071
6072 /*
6073  * Workqueue context.
6074  */
6075 static void rtl_slow_event_work(struct rtl8169_private *tp)
6076 {
6077         struct net_device *dev = tp->dev;
6078         u16 status;
6079
6080         status = rtl_get_events(tp) & tp->event_slow;
6081         rtl_ack_events(tp, status);
6082
6083         if (unlikely(status & RxFIFOOver)) {
6084                 switch (tp->mac_version) {
6085                 /* Work around for rx fifo overflow */
6086                 case RTL_GIGA_MAC_VER_11:
6087                         netif_stop_queue(dev);
6088                         /* XXX - Hack alert. See rtl_task(). */
6089                         set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
6090                 default:
6091                         break;
6092                 }
6093         }
6094
6095         if (unlikely(status & SYSErr))
6096                 rtl8169_pcierr_interrupt(dev);
6097
6098         if (status & LinkChg)
6099                 __rtl8169_check_link_status(dev, tp, tp->mmio_addr, true);
6100
6101         rtl_irq_enable_all(tp);
6102 }
6103
6104 static void rtl_task(struct work_struct *work)
6105 {
6106         static const struct {
6107                 int bitnr;
6108                 void (*action)(struct rtl8169_private *);
6109         } rtl_work[] = {
6110                 /* XXX - keep rtl_slow_event_work() as first element. */
6111                 { RTL_FLAG_TASK_SLOW_PENDING,   rtl_slow_event_work },
6112                 { RTL_FLAG_TASK_RESET_PENDING,  rtl_reset_work },
6113                 { RTL_FLAG_TASK_PHY_PENDING,    rtl_phy_work }
6114         };
6115         struct rtl8169_private *tp =
6116                 container_of(work, struct rtl8169_private, wk.work);
6117         struct net_device *dev = tp->dev;
6118         int i;
6119
6120         rtl_lock_work(tp);
6121
6122         if (!netif_running(dev) ||
6123             !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
6124                 goto out_unlock;
6125
6126         for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
6127                 bool pending;
6128
6129                 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
6130                 if (pending)
6131                         rtl_work[i].action(tp);
6132         }
6133
6134 out_unlock:
6135         rtl_unlock_work(tp);
6136 }
6137
6138 static int rtl8169_poll(struct napi_struct *napi, int budget)
6139 {
6140         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
6141         struct net_device *dev = tp->dev;
6142         u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
6143         int work_done= 0;
6144         u16 status;
6145
6146         status = rtl_get_events(tp);
6147         rtl_ack_events(tp, status & ~tp->event_slow);
6148
6149         if (status & RTL_EVENT_NAPI_RX)
6150                 work_done = rtl_rx(dev, tp, (u32) budget);
6151
6152         if (status & RTL_EVENT_NAPI_TX)
6153                 rtl_tx(dev, tp);
6154
6155         if (status & tp->event_slow) {
6156                 enable_mask &= ~tp->event_slow;
6157
6158                 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
6159         }
6160
6161         if (work_done < budget) {
6162                 napi_complete(napi);
6163
6164                 rtl_irq_enable(tp, enable_mask);
6165                 mmiowb();
6166         }
6167
6168         return work_done;
6169 }
6170
6171 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
6172 {
6173         struct rtl8169_private *tp = netdev_priv(dev);
6174
6175         if (tp->mac_version > RTL_GIGA_MAC_VER_06)
6176                 return;
6177
6178         dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
6179         RTL_W32(RxMissed, 0);
6180 }
6181
6182 static void rtl8169_down(struct net_device *dev)
6183 {
6184         struct rtl8169_private *tp = netdev_priv(dev);
6185         void __iomem *ioaddr = tp->mmio_addr;
6186
6187         del_timer_sync(&tp->timer);
6188
6189         napi_disable(&tp->napi);
6190         netif_stop_queue(dev);
6191
6192         rtl8169_hw_reset(tp);
6193         /*
6194          * At this point device interrupts can not be enabled in any function,
6195          * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
6196          * and napi is disabled (rtl8169_poll).
6197          */
6198         rtl8169_rx_missed(dev, ioaddr);
6199
6200         /* Give a racing hard_start_xmit a few cycles to complete. */
6201         synchronize_sched();
6202
6203         rtl8169_tx_clear(tp);
6204
6205         rtl8169_rx_clear(tp);
6206
6207         rtl_pll_power_down(tp);
6208 }
6209
6210 static int rtl8169_close(struct net_device *dev)
6211 {
6212         struct rtl8169_private *tp = netdev_priv(dev);
6213         struct pci_dev *pdev = tp->pci_dev;
6214
6215         pm_runtime_get_sync(&pdev->dev);
6216
6217         /* Update counters before going down */
6218         rtl8169_update_counters(dev);
6219
6220         rtl_lock_work(tp);
6221         clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6222
6223         rtl8169_down(dev);
6224         rtl_unlock_work(tp);
6225
6226         free_irq(pdev->irq, dev);
6227
6228         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6229                           tp->RxPhyAddr);
6230         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6231                           tp->TxPhyAddr);
6232         tp->TxDescArray = NULL;
6233         tp->RxDescArray = NULL;
6234
6235         pm_runtime_put_sync(&pdev->dev);
6236
6237         return 0;
6238 }
6239
6240 #ifdef CONFIG_NET_POLL_CONTROLLER
6241 static void rtl8169_netpoll(struct net_device *dev)
6242 {
6243         struct rtl8169_private *tp = netdev_priv(dev);
6244
6245         rtl8169_interrupt(tp->pci_dev->irq, dev);
6246 }
6247 #endif
6248
6249 static int rtl_open(struct net_device *dev)
6250 {
6251         struct rtl8169_private *tp = netdev_priv(dev);
6252         void __iomem *ioaddr = tp->mmio_addr;
6253         struct pci_dev *pdev = tp->pci_dev;
6254         int retval = -ENOMEM;
6255
6256         pm_runtime_get_sync(&pdev->dev);
6257
6258         /*
6259          * Rx and Tx descriptors needs 256 bytes alignment.
6260          * dma_alloc_coherent provides more.
6261          */
6262         tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
6263                                              &tp->TxPhyAddr, GFP_KERNEL);
6264         if (!tp->TxDescArray)
6265                 goto err_pm_runtime_put;
6266
6267         tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
6268                                              &tp->RxPhyAddr, GFP_KERNEL);
6269         if (!tp->RxDescArray)
6270                 goto err_free_tx_0;
6271
6272         retval = rtl8169_init_ring(dev);
6273         if (retval < 0)
6274                 goto err_free_rx_1;
6275
6276         INIT_WORK(&tp->wk.work, rtl_task);
6277
6278         smp_mb();
6279
6280         rtl_request_firmware(tp);
6281
6282         retval = request_irq(pdev->irq, rtl8169_interrupt,
6283                              (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
6284                              dev->name, dev);
6285         if (retval < 0)
6286                 goto err_release_fw_2;
6287
6288         rtl_lock_work(tp);
6289
6290         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6291
6292         napi_enable(&tp->napi);
6293
6294         rtl8169_init_phy(dev, tp);
6295
6296         __rtl8169_set_features(dev, dev->features);
6297
6298         rtl_pll_power_up(tp);
6299
6300         rtl_hw_start(dev);
6301
6302         netif_start_queue(dev);
6303
6304         rtl_unlock_work(tp);
6305
6306         tp->saved_wolopts = 0;
6307         pm_runtime_put_noidle(&pdev->dev);
6308
6309         rtl8169_check_link_status(dev, tp, ioaddr);
6310 out:
6311         return retval;
6312
6313 err_release_fw_2:
6314         rtl_release_firmware(tp);
6315         rtl8169_rx_clear(tp);
6316 err_free_rx_1:
6317         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6318                           tp->RxPhyAddr);
6319         tp->RxDescArray = NULL;
6320 err_free_tx_0:
6321         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6322                           tp->TxPhyAddr);
6323         tp->TxDescArray = NULL;
6324 err_pm_runtime_put:
6325         pm_runtime_put_noidle(&pdev->dev);
6326         goto out;
6327 }
6328
6329 static struct rtnl_link_stats64 *
6330 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
6331 {
6332         struct rtl8169_private *tp = netdev_priv(dev);
6333         void __iomem *ioaddr = tp->mmio_addr;
6334         unsigned int start;
6335
6336         if (netif_running(dev))
6337                 rtl8169_rx_missed(dev, ioaddr);
6338
6339         do {
6340                 start = u64_stats_fetch_begin_bh(&tp->rx_stats.syncp);
6341                 stats->rx_packets = tp->rx_stats.packets;
6342                 stats->rx_bytes = tp->rx_stats.bytes;
6343         } while (u64_stats_fetch_retry_bh(&tp->rx_stats.syncp, start));
6344
6345
6346         do {
6347                 start = u64_stats_fetch_begin_bh(&tp->tx_stats.syncp);
6348                 stats->tx_packets = tp->tx_stats.packets;
6349                 stats->tx_bytes = tp->tx_stats.bytes;
6350         } while (u64_stats_fetch_retry_bh(&tp->tx_stats.syncp, start));
6351
6352         stats->rx_dropped       = dev->stats.rx_dropped;
6353         stats->tx_dropped       = dev->stats.tx_dropped;
6354         stats->rx_length_errors = dev->stats.rx_length_errors;
6355         stats->rx_errors        = dev->stats.rx_errors;
6356         stats->rx_crc_errors    = dev->stats.rx_crc_errors;
6357         stats->rx_fifo_errors   = dev->stats.rx_fifo_errors;
6358         stats->rx_missed_errors = dev->stats.rx_missed_errors;
6359
6360         return stats;
6361 }
6362
6363 static void rtl8169_net_suspend(struct net_device *dev)
6364 {
6365         struct rtl8169_private *tp = netdev_priv(dev);
6366
6367         if (!netif_running(dev))
6368                 return;
6369
6370         netif_device_detach(dev);
6371         netif_stop_queue(dev);
6372
6373         rtl_lock_work(tp);
6374         napi_disable(&tp->napi);
6375         clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6376         rtl_unlock_work(tp);
6377
6378         rtl_pll_power_down(tp);
6379 }
6380
6381 #ifdef CONFIG_PM
6382
6383 static int rtl8169_suspend(struct device *device)
6384 {
6385         struct pci_dev *pdev = to_pci_dev(device);
6386         struct net_device *dev = pci_get_drvdata(pdev);
6387
6388         rtl8169_net_suspend(dev);
6389
6390         return 0;
6391 }
6392
6393 static void __rtl8169_resume(struct net_device *dev)
6394 {
6395         struct rtl8169_private *tp = netdev_priv(dev);
6396
6397         netif_device_attach(dev);
6398
6399         rtl_pll_power_up(tp);
6400
6401         rtl_lock_work(tp);
6402         napi_enable(&tp->napi);
6403         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6404         rtl_unlock_work(tp);
6405
6406         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6407 }
6408
6409 static int rtl8169_resume(struct device *device)
6410 {
6411         struct pci_dev *pdev = to_pci_dev(device);
6412         struct net_device *dev = pci_get_drvdata(pdev);
6413         struct rtl8169_private *tp = netdev_priv(dev);
6414
6415         rtl8169_init_phy(dev, tp);
6416
6417         if (netif_running(dev))
6418                 __rtl8169_resume(dev);
6419
6420         return 0;
6421 }
6422
6423 static int rtl8169_runtime_suspend(struct device *device)
6424 {
6425         struct pci_dev *pdev = to_pci_dev(device);
6426         struct net_device *dev = pci_get_drvdata(pdev);
6427         struct rtl8169_private *tp = netdev_priv(dev);
6428
6429         if (!tp->TxDescArray)
6430                 return 0;
6431
6432         rtl_lock_work(tp);
6433         tp->saved_wolopts = __rtl8169_get_wol(tp);
6434         __rtl8169_set_wol(tp, WAKE_ANY);
6435         rtl_unlock_work(tp);
6436
6437         rtl8169_net_suspend(dev);
6438
6439         return 0;
6440 }
6441
6442 static int rtl8169_runtime_resume(struct device *device)
6443 {
6444         struct pci_dev *pdev = to_pci_dev(device);
6445         struct net_device *dev = pci_get_drvdata(pdev);
6446         struct rtl8169_private *tp = netdev_priv(dev);
6447
6448         if (!tp->TxDescArray)
6449                 return 0;
6450
6451         rtl_lock_work(tp);
6452         __rtl8169_set_wol(tp, tp->saved_wolopts);
6453         tp->saved_wolopts = 0;
6454         rtl_unlock_work(tp);
6455
6456         rtl8169_init_phy(dev, tp);
6457
6458         __rtl8169_resume(dev);
6459
6460         return 0;
6461 }
6462
6463 static int rtl8169_runtime_idle(struct device *device)
6464 {
6465         struct pci_dev *pdev = to_pci_dev(device);
6466         struct net_device *dev = pci_get_drvdata(pdev);
6467         struct rtl8169_private *tp = netdev_priv(dev);
6468
6469         return tp->TxDescArray ? -EBUSY : 0;
6470 }
6471
6472 static const struct dev_pm_ops rtl8169_pm_ops = {
6473         .suspend                = rtl8169_suspend,
6474         .resume                 = rtl8169_resume,
6475         .freeze                 = rtl8169_suspend,
6476         .thaw                   = rtl8169_resume,
6477         .poweroff               = rtl8169_suspend,
6478         .restore                = rtl8169_resume,
6479         .runtime_suspend        = rtl8169_runtime_suspend,
6480         .runtime_resume         = rtl8169_runtime_resume,
6481         .runtime_idle           = rtl8169_runtime_idle,
6482 };
6483
6484 #define RTL8169_PM_OPS  (&rtl8169_pm_ops)
6485
6486 #else /* !CONFIG_PM */
6487
6488 #define RTL8169_PM_OPS  NULL
6489
6490 #endif /* !CONFIG_PM */
6491
6492 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
6493 {
6494         void __iomem *ioaddr = tp->mmio_addr;
6495
6496         /* WoL fails with 8168b when the receiver is disabled. */
6497         switch (tp->mac_version) {
6498         case RTL_GIGA_MAC_VER_11:
6499         case RTL_GIGA_MAC_VER_12:
6500         case RTL_GIGA_MAC_VER_17:
6501                 pci_clear_master(tp->pci_dev);
6502
6503                 RTL_W8(ChipCmd, CmdRxEnb);
6504                 /* PCI commit */
6505                 RTL_R8(ChipCmd);
6506                 break;
6507         default:
6508                 break;
6509         }
6510 }
6511
6512 static void rtl_shutdown(struct pci_dev *pdev)
6513 {
6514         struct net_device *dev = pci_get_drvdata(pdev);
6515         struct rtl8169_private *tp = netdev_priv(dev);
6516         struct device *d = &pdev->dev;
6517
6518         pm_runtime_get_sync(d);
6519
6520         rtl8169_net_suspend(dev);
6521
6522         /* Restore original MAC address */
6523         rtl_rar_set(tp, dev->perm_addr);
6524
6525         rtl8169_hw_reset(tp);
6526
6527         if (system_state == SYSTEM_POWER_OFF) {
6528                 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
6529                         rtl_wol_suspend_quirk(tp);
6530                         rtl_wol_shutdown_quirk(tp);
6531                 }
6532
6533                 pci_wake_from_d3(pdev, true);
6534                 pci_set_power_state(pdev, PCI_D3hot);
6535         }
6536
6537         pm_runtime_put_noidle(d);
6538 }
6539
6540 static void rtl_remove_one(struct pci_dev *pdev)
6541 {
6542         struct net_device *dev = pci_get_drvdata(pdev);
6543         struct rtl8169_private *tp = netdev_priv(dev);
6544
6545         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
6546             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
6547             tp->mac_version == RTL_GIGA_MAC_VER_31) {
6548                 rtl8168_driver_stop(tp);
6549         }
6550
6551         cancel_work_sync(&tp->wk.work);
6552
6553         netif_napi_del(&tp->napi);
6554
6555         unregister_netdev(dev);
6556
6557         rtl_release_firmware(tp);
6558
6559         if (pci_dev_run_wake(pdev))
6560                 pm_runtime_get_noresume(&pdev->dev);
6561
6562         /* restore original MAC address */
6563         rtl_rar_set(tp, dev->perm_addr);
6564
6565         rtl_disable_msi(pdev, tp);
6566         rtl8169_release_board(pdev, dev, tp->mmio_addr);
6567         pci_set_drvdata(pdev, NULL);
6568 }
6569
6570 static const struct net_device_ops rtl_netdev_ops = {
6571         .ndo_open               = rtl_open,
6572         .ndo_stop               = rtl8169_close,
6573         .ndo_get_stats64        = rtl8169_get_stats64,
6574         .ndo_start_xmit         = rtl8169_start_xmit,
6575         .ndo_tx_timeout         = rtl8169_tx_timeout,
6576         .ndo_validate_addr      = eth_validate_addr,
6577         .ndo_change_mtu         = rtl8169_change_mtu,
6578         .ndo_fix_features       = rtl8169_fix_features,
6579         .ndo_set_features       = rtl8169_set_features,
6580         .ndo_set_mac_address    = rtl_set_mac_address,
6581         .ndo_do_ioctl           = rtl8169_ioctl,
6582         .ndo_set_rx_mode        = rtl_set_rx_mode,
6583 #ifdef CONFIG_NET_POLL_CONTROLLER
6584         .ndo_poll_controller    = rtl8169_netpoll,
6585 #endif
6586
6587 };
6588
6589 static const struct rtl_cfg_info {
6590         void (*hw_start)(struct net_device *);
6591         unsigned int region;
6592         unsigned int align;
6593         u16 event_slow;
6594         unsigned features;
6595         u8 default_ver;
6596 } rtl_cfg_infos [] = {
6597         [RTL_CFG_0] = {
6598                 .hw_start       = rtl_hw_start_8169,
6599                 .region         = 1,
6600                 .align          = 0,
6601                 .event_slow     = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
6602                 .features       = RTL_FEATURE_GMII,
6603                 .default_ver    = RTL_GIGA_MAC_VER_01,
6604         },
6605         [RTL_CFG_1] = {
6606                 .hw_start       = rtl_hw_start_8168,
6607                 .region         = 2,
6608                 .align          = 8,
6609                 .event_slow     = SYSErr | LinkChg | RxOverflow,
6610                 .features       = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
6611                 .default_ver    = RTL_GIGA_MAC_VER_11,
6612         },
6613         [RTL_CFG_2] = {
6614                 .hw_start       = rtl_hw_start_8101,
6615                 .region         = 2,
6616                 .align          = 8,
6617                 .event_slow     = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
6618                                   PCSTimeout,
6619                 .features       = RTL_FEATURE_MSI,
6620                 .default_ver    = RTL_GIGA_MAC_VER_13,
6621         }
6622 };
6623
6624 /* Cfg9346_Unlock assumed. */
6625 static unsigned rtl_try_msi(struct rtl8169_private *tp,
6626                             const struct rtl_cfg_info *cfg)
6627 {
6628         void __iomem *ioaddr = tp->mmio_addr;
6629         unsigned msi = 0;
6630         u8 cfg2;
6631
6632         cfg2 = RTL_R8(Config2) & ~MSIEnable;
6633         if (cfg->features & RTL_FEATURE_MSI) {
6634                 if (pci_enable_msi(tp->pci_dev)) {
6635                         netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n");
6636                 } else {
6637                         cfg2 |= MSIEnable;
6638                         msi = RTL_FEATURE_MSI;
6639                 }
6640         }
6641         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
6642                 RTL_W8(Config2, cfg2);
6643         return msi;
6644 }
6645
6646 DECLARE_RTL_COND(rtl_link_list_ready_cond)
6647 {
6648         void __iomem *ioaddr = tp->mmio_addr;
6649
6650         return RTL_R8(MCU) & LINK_LIST_RDY;
6651 }
6652
6653 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
6654 {
6655         void __iomem *ioaddr = tp->mmio_addr;
6656
6657         return (RTL_R8(MCU) & RXTX_EMPTY) == RXTX_EMPTY;
6658 }
6659
6660 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
6661 {
6662         void __iomem *ioaddr = tp->mmio_addr;
6663         u32 data;
6664
6665         tp->ocp_base = OCP_STD_PHY_BASE;
6666
6667         RTL_W32(MISC, RTL_R32(MISC) | RXDV_GATED_EN);
6668
6669         if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
6670                 return;
6671
6672         if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
6673                 return;
6674
6675         RTL_W8(ChipCmd, RTL_R8(ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
6676         msleep(1);
6677         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
6678
6679         data = r8168_mac_ocp_read(tp, 0xe8de);
6680         data &= ~(1 << 14);
6681         r8168_mac_ocp_write(tp, 0xe8de, data);
6682
6683         if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
6684                 return;
6685
6686         data = r8168_mac_ocp_read(tp, 0xe8de);
6687         data |= (1 << 15);
6688         r8168_mac_ocp_write(tp, 0xe8de, data);
6689
6690         if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
6691                 return;
6692 }
6693
6694 static void rtl_hw_initialize(struct rtl8169_private *tp)
6695 {
6696         switch (tp->mac_version) {
6697         case RTL_GIGA_MAC_VER_40:
6698         case RTL_GIGA_MAC_VER_41:
6699                 rtl_hw_init_8168g(tp);
6700                 break;
6701
6702         default:
6703                 break;
6704         }
6705 }
6706
6707 static int
6708 rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
6709 {
6710         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
6711         const unsigned int region = cfg->region;
6712         struct rtl8169_private *tp;
6713         struct mii_if_info *mii;
6714         struct net_device *dev;
6715         void __iomem *ioaddr;
6716         int chipset, i;
6717         int rc;
6718
6719         if (netif_msg_drv(&debug)) {
6720                 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
6721                        MODULENAME, RTL8169_VERSION);
6722         }
6723
6724         dev = alloc_etherdev(sizeof (*tp));
6725         if (!dev) {
6726                 rc = -ENOMEM;
6727                 goto out;
6728         }
6729
6730         SET_NETDEV_DEV(dev, &pdev->dev);
6731         dev->netdev_ops = &rtl_netdev_ops;
6732         tp = netdev_priv(dev);
6733         tp->dev = dev;
6734         tp->pci_dev = pdev;
6735         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
6736
6737         mii = &tp->mii;
6738         mii->dev = dev;
6739         mii->mdio_read = rtl_mdio_read;
6740         mii->mdio_write = rtl_mdio_write;
6741         mii->phy_id_mask = 0x1f;
6742         mii->reg_num_mask = 0x1f;
6743         mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
6744
6745         /* disable ASPM completely as that cause random device stop working
6746          * problems as well as full system hangs for some PCIe devices users */
6747         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
6748                                      PCIE_LINK_STATE_CLKPM);
6749
6750         /* enable device (incl. PCI PM wakeup and hotplug setup) */
6751         rc = pci_enable_device(pdev);
6752         if (rc < 0) {
6753                 netif_err(tp, probe, dev, "enable failure\n");
6754                 goto err_out_free_dev_1;
6755         }
6756
6757         if (pci_set_mwi(pdev) < 0)
6758                 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
6759
6760         /* make sure PCI base addr 1 is MMIO */
6761         if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
6762                 netif_err(tp, probe, dev,
6763                           "region #%d not an MMIO resource, aborting\n",
6764                           region);
6765                 rc = -ENODEV;
6766                 goto err_out_mwi_2;
6767         }
6768
6769         /* check for weird/broken PCI region reporting */
6770         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
6771                 netif_err(tp, probe, dev,
6772                           "Invalid PCI region size(s), aborting\n");
6773                 rc = -ENODEV;
6774                 goto err_out_mwi_2;
6775         }
6776
6777         rc = pci_request_regions(pdev, MODULENAME);
6778         if (rc < 0) {
6779                 netif_err(tp, probe, dev, "could not request regions\n");
6780                 goto err_out_mwi_2;
6781         }
6782
6783         tp->cp_cmd = RxChkSum;
6784
6785         if ((sizeof(dma_addr_t) > 4) &&
6786             !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
6787                 tp->cp_cmd |= PCIDAC;
6788                 dev->features |= NETIF_F_HIGHDMA;
6789         } else {
6790                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
6791                 if (rc < 0) {
6792                         netif_err(tp, probe, dev, "DMA configuration failed\n");
6793                         goto err_out_free_res_3;
6794                 }
6795         }
6796
6797         /* ioremap MMIO region */
6798         ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
6799         if (!ioaddr) {
6800                 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
6801                 rc = -EIO;
6802                 goto err_out_free_res_3;
6803         }
6804         tp->mmio_addr = ioaddr;
6805
6806         if (!pci_is_pcie(pdev))
6807                 netif_info(tp, probe, dev, "not PCI Express\n");
6808
6809         /* Identify chip attached to board */
6810         rtl8169_get_mac_version(tp, dev, cfg->default_ver);
6811
6812         rtl_init_rxcfg(tp);
6813
6814         rtl_irq_disable(tp);
6815
6816         rtl_hw_initialize(tp);
6817
6818         rtl_hw_reset(tp);
6819
6820         rtl_ack_events(tp, 0xffff);
6821
6822         pci_set_master(pdev);
6823
6824         /*
6825          * Pretend we are using VLANs; This bypasses a nasty bug where
6826          * Interrupts stop flowing on high load on 8110SCd controllers.
6827          */
6828         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
6829                 tp->cp_cmd |= RxVlan;
6830
6831         rtl_init_mdio_ops(tp);
6832         rtl_init_pll_power_ops(tp);
6833         rtl_init_jumbo_ops(tp);
6834         rtl_init_csi_ops(tp);
6835
6836         rtl8169_print_mac_version(tp);
6837
6838         chipset = tp->mac_version;
6839         tp->txd_version = rtl_chip_infos[chipset].txd_version;
6840
6841         RTL_W8(Cfg9346, Cfg9346_Unlock);
6842         RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
6843         RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
6844         if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
6845                 tp->features |= RTL_FEATURE_WOL;
6846         if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
6847                 tp->features |= RTL_FEATURE_WOL;
6848         tp->features |= rtl_try_msi(tp, cfg);
6849         RTL_W8(Cfg9346, Cfg9346_Lock);
6850
6851         if (rtl_tbi_enabled(tp)) {
6852                 tp->set_speed = rtl8169_set_speed_tbi;
6853                 tp->get_settings = rtl8169_gset_tbi;
6854                 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
6855                 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
6856                 tp->link_ok = rtl8169_tbi_link_ok;
6857                 tp->do_ioctl = rtl_tbi_ioctl;
6858         } else {
6859                 tp->set_speed = rtl8169_set_speed_xmii;
6860                 tp->get_settings = rtl8169_gset_xmii;
6861                 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
6862                 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
6863                 tp->link_ok = rtl8169_xmii_link_ok;
6864                 tp->do_ioctl = rtl_xmii_ioctl;
6865         }
6866
6867         mutex_init(&tp->wk.mutex);
6868
6869         /* Get MAC address */
6870         for (i = 0; i < ETH_ALEN; i++)
6871                 dev->dev_addr[i] = RTL_R8(MAC0 + i);
6872
6873         SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
6874         dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
6875
6876         netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
6877
6878         /* don't enable SG, IP_CSUM and TSO by default - it might not work
6879          * properly for all devices */
6880         dev->features |= NETIF_F_RXCSUM |
6881                 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
6882
6883         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
6884                 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
6885         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
6886                 NETIF_F_HIGHDMA;
6887
6888         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
6889                 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
6890                 dev->hw_features &= ~NETIF_F_HW_VLAN_RX;
6891
6892         dev->hw_features |= NETIF_F_RXALL;
6893         dev->hw_features |= NETIF_F_RXFCS;
6894
6895         tp->hw_start = cfg->hw_start;
6896         tp->event_slow = cfg->event_slow;
6897
6898         tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
6899                 ~(RxBOVF | RxFOVF) : ~0;
6900
6901         init_timer(&tp->timer);
6902         tp->timer.data = (unsigned long) dev;
6903         tp->timer.function = rtl8169_phy_timer;
6904
6905         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
6906
6907         rc = register_netdev(dev);
6908         if (rc < 0)
6909                 goto err_out_msi_4;
6910
6911         pci_set_drvdata(pdev, dev);
6912
6913         netif_info(tp, probe, dev, "%s at 0x%p, %pM, XID %08x IRQ %d\n",
6914                    rtl_chip_infos[chipset].name, ioaddr, dev->dev_addr,
6915                    (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), pdev->irq);
6916         if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
6917                 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
6918                            "tx checksumming: %s]\n",
6919                            rtl_chip_infos[chipset].jumbo_max,
6920                            rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko");
6921         }
6922
6923         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
6924             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
6925             tp->mac_version == RTL_GIGA_MAC_VER_31) {
6926                 rtl8168_driver_start(tp);
6927         }
6928
6929         device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
6930
6931         if (pci_dev_run_wake(pdev))
6932                 pm_runtime_put_noidle(&pdev->dev);
6933
6934         netif_carrier_off(dev);
6935
6936 out:
6937         return rc;
6938
6939 err_out_msi_4:
6940         netif_napi_del(&tp->napi);
6941         rtl_disable_msi(pdev, tp);
6942         iounmap(ioaddr);
6943 err_out_free_res_3:
6944         pci_release_regions(pdev);
6945 err_out_mwi_2:
6946         pci_clear_mwi(pdev);
6947         pci_disable_device(pdev);
6948 err_out_free_dev_1:
6949         free_netdev(dev);
6950         goto out;
6951 }
6952
6953 static struct pci_driver rtl8169_pci_driver = {
6954         .name           = MODULENAME,
6955         .id_table       = rtl8169_pci_tbl,
6956         .probe          = rtl_init_one,
6957         .remove         = rtl_remove_one,
6958         .shutdown       = rtl_shutdown,
6959         .driver.pm      = RTL8169_PM_OPS,
6960 };
6961
6962 module_pci_driver(rtl8169_pci_driver);