2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
8 * See MAINTAINERS file for support contact information.
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
23 #include <linux/tcp.h>
24 #include <linux/init.h>
25 #include <linux/interrupt.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/firmware.h>
29 #include <linux/pci-aspm.h>
30 #include <linux/prefetch.h>
35 #define RTL8169_VERSION "2.3LK-NAPI"
36 #define MODULENAME "r8169"
37 #define PFX MODULENAME ": "
39 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
40 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
41 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
42 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
43 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
44 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
45 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
46 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
47 #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw"
48 #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw"
49 #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw"
50 #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw"
51 #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw"
52 #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw"
55 #define assert(expr) \
57 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
58 #expr,__FILE__,__func__,__LINE__); \
60 #define dprintk(fmt, args...) \
61 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
63 #define assert(expr) do {} while (0)
64 #define dprintk(fmt, args...) do {} while (0)
65 #endif /* RTL8169_DEBUG */
67 #define R8169_MSG_DEFAULT \
68 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
70 #define TX_SLOTS_AVAIL(tp) \
71 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
73 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
74 #define TX_FRAGS_READY_FOR(tp,nr_frags) \
75 (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
77 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
78 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
79 static const int multicast_filter_limit = 32;
81 #define MAX_READ_REQUEST_SHIFT 12
82 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */
83 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
85 #define R8169_REGS_SIZE 256
86 #define R8169_NAPI_WEIGHT 64
87 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
88 #define NUM_RX_DESC 256U /* Number of Rx descriptor registers */
89 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
90 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
92 #define RTL8169_TX_TIMEOUT (6*HZ)
93 #define RTL8169_PHY_TIMEOUT (10*HZ)
95 /* write/read MMIO register */
96 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
97 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
98 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
99 #define RTL_R8(reg) readb (ioaddr + (reg))
100 #define RTL_R16(reg) readw (ioaddr + (reg))
101 #define RTL_R32(reg) readl (ioaddr + (reg))
104 RTL_GIGA_MAC_VER_01 = 0,
147 RTL_GIGA_MAC_NONE = 0xff,
150 enum rtl_tx_desc_version {
155 #define JUMBO_1K ETH_DATA_LEN
156 #define JUMBO_4K (4*1024 - ETH_HLEN - 2)
157 #define JUMBO_6K (6*1024 - ETH_HLEN - 2)
158 #define JUMBO_7K (7*1024 - ETH_HLEN - 2)
159 #define JUMBO_9K (9*1024 - ETH_HLEN - 2)
161 #define _R(NAME,TD,FW,SZ,B) { \
169 static const struct {
171 enum rtl_tx_desc_version txd_version;
175 } rtl_chip_infos[] = {
177 [RTL_GIGA_MAC_VER_01] =
178 _R("RTL8169", RTL_TD_0, NULL, JUMBO_7K, true),
179 [RTL_GIGA_MAC_VER_02] =
180 _R("RTL8169s", RTL_TD_0, NULL, JUMBO_7K, true),
181 [RTL_GIGA_MAC_VER_03] =
182 _R("RTL8110s", RTL_TD_0, NULL, JUMBO_7K, true),
183 [RTL_GIGA_MAC_VER_04] =
184 _R("RTL8169sb/8110sb", RTL_TD_0, NULL, JUMBO_7K, true),
185 [RTL_GIGA_MAC_VER_05] =
186 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
187 [RTL_GIGA_MAC_VER_06] =
188 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
190 [RTL_GIGA_MAC_VER_07] =
191 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
192 [RTL_GIGA_MAC_VER_08] =
193 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
194 [RTL_GIGA_MAC_VER_09] =
195 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
196 [RTL_GIGA_MAC_VER_10] =
197 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
198 [RTL_GIGA_MAC_VER_11] =
199 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
200 [RTL_GIGA_MAC_VER_12] =
201 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
202 [RTL_GIGA_MAC_VER_13] =
203 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
204 [RTL_GIGA_MAC_VER_14] =
205 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
206 [RTL_GIGA_MAC_VER_15] =
207 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
208 [RTL_GIGA_MAC_VER_16] =
209 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
210 [RTL_GIGA_MAC_VER_17] =
211 _R("RTL8168b/8111b", RTL_TD_1, NULL, JUMBO_4K, false),
212 [RTL_GIGA_MAC_VER_18] =
213 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
214 [RTL_GIGA_MAC_VER_19] =
215 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
216 [RTL_GIGA_MAC_VER_20] =
217 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
218 [RTL_GIGA_MAC_VER_21] =
219 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
220 [RTL_GIGA_MAC_VER_22] =
221 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
222 [RTL_GIGA_MAC_VER_23] =
223 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
224 [RTL_GIGA_MAC_VER_24] =
225 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
226 [RTL_GIGA_MAC_VER_25] =
227 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_1,
229 [RTL_GIGA_MAC_VER_26] =
230 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_2,
232 [RTL_GIGA_MAC_VER_27] =
233 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
234 [RTL_GIGA_MAC_VER_28] =
235 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
236 [RTL_GIGA_MAC_VER_29] =
237 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
239 [RTL_GIGA_MAC_VER_30] =
240 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
242 [RTL_GIGA_MAC_VER_31] =
243 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
244 [RTL_GIGA_MAC_VER_32] =
245 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_1,
247 [RTL_GIGA_MAC_VER_33] =
248 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2,
250 [RTL_GIGA_MAC_VER_34] =
251 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3,
253 [RTL_GIGA_MAC_VER_35] =
254 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_1,
256 [RTL_GIGA_MAC_VER_36] =
257 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_2,
259 [RTL_GIGA_MAC_VER_37] =
260 _R("RTL8402", RTL_TD_1, FIRMWARE_8402_1,
262 [RTL_GIGA_MAC_VER_38] =
263 _R("RTL8411", RTL_TD_1, FIRMWARE_8411_1,
265 [RTL_GIGA_MAC_VER_39] =
266 _R("RTL8106e", RTL_TD_1, FIRMWARE_8106E_1,
268 [RTL_GIGA_MAC_VER_40] =
269 _R("RTL8168g/8111g", RTL_TD_1, FIRMWARE_8168G_2,
271 [RTL_GIGA_MAC_VER_41] =
272 _R("RTL8168g/8111g", RTL_TD_1, NULL, JUMBO_9K, false),
273 [RTL_GIGA_MAC_VER_42] =
274 _R("RTL8168g/8111g", RTL_TD_1, FIRMWARE_8168G_3,
276 [RTL_GIGA_MAC_VER_43] =
277 _R("RTL8106e", RTL_TD_1, FIRMWARE_8106E_2,
288 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
289 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
290 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
291 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
292 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
293 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
294 { PCI_VENDOR_ID_DLINK, 0x4300,
295 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0, RTL_CFG_1 },
296 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
297 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302), 0, 0, RTL_CFG_0 },
298 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
299 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
300 { PCI_VENDOR_ID_LINKSYS, 0x1032,
301 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
303 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
307 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
309 static int rx_buf_sz = 16383;
316 MAC0 = 0, /* Ethernet hardware address. */
318 MAR0 = 8, /* Multicast filter. */
319 CounterAddrLow = 0x10,
320 CounterAddrHigh = 0x14,
321 TxDescStartAddrLow = 0x20,
322 TxDescStartAddrHigh = 0x24,
323 TxHDescStartAddrLow = 0x28,
324 TxHDescStartAddrHigh = 0x2c,
333 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
334 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
337 #define RX128_INT_EN (1 << 15) /* 8111c and later */
338 #define RX_MULTI_EN (1 << 14) /* 8111c only */
339 #define RXCFG_FIFO_SHIFT 13
340 /* No threshold before first PCI xfer */
341 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
342 #define RX_EARLY_OFF (1 << 11)
343 #define RXCFG_DMA_SHIFT 8
344 /* Unlimited maximum PCI burst. */
345 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
352 #define PME_SIGNAL (1 << 5) /* 8168c and later */
363 RxDescAddrLow = 0xe4,
364 RxDescAddrHigh = 0xe8,
365 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
367 #define NoEarlyTx 0x3f /* Max value : no early transmit. */
369 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
371 #define TxPacketMax (8064 >> 7)
372 #define EarlySize 0x27
375 FuncEventMask = 0xf4,
376 FuncPresetState = 0xf8,
377 FuncForceEvent = 0xfc,
380 enum rtl8110_registers {
386 enum rtl8168_8101_registers {
389 #define CSIAR_FLAG 0x80000000
390 #define CSIAR_WRITE_CMD 0x80000000
391 #define CSIAR_BYTE_ENABLE 0x0f
392 #define CSIAR_BYTE_ENABLE_SHIFT 12
393 #define CSIAR_ADDR_MASK 0x0fff
394 #define CSIAR_FUNC_CARD 0x00000000
395 #define CSIAR_FUNC_SDIO 0x00010000
396 #define CSIAR_FUNC_NIC 0x00020000
399 #define EPHYAR_FLAG 0x80000000
400 #define EPHYAR_WRITE_CMD 0x80000000
401 #define EPHYAR_REG_MASK 0x1f
402 #define EPHYAR_REG_SHIFT 16
403 #define EPHYAR_DATA_MASK 0xffff
405 #define PFM_EN (1 << 6)
407 #define FIX_NAK_1 (1 << 4)
408 #define FIX_NAK_2 (1 << 3)
411 #define NOW_IS_OOB (1 << 7)
412 #define TX_EMPTY (1 << 5)
413 #define RX_EMPTY (1 << 4)
414 #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY)
415 #define EN_NDP (1 << 3)
416 #define EN_OOB_RESET (1 << 2)
417 #define LINK_LIST_RDY (1 << 1)
419 #define EFUSEAR_FLAG 0x80000000
420 #define EFUSEAR_WRITE_CMD 0x80000000
421 #define EFUSEAR_READ_CMD 0x00000000
422 #define EFUSEAR_REG_MASK 0x03ff
423 #define EFUSEAR_REG_SHIFT 8
424 #define EFUSEAR_DATA_MASK 0xff
427 enum rtl8168_registers {
432 #define ERIAR_FLAG 0x80000000
433 #define ERIAR_WRITE_CMD 0x80000000
434 #define ERIAR_READ_CMD 0x00000000
435 #define ERIAR_ADDR_BYTE_ALIGN 4
436 #define ERIAR_TYPE_SHIFT 16
437 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
438 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
439 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
440 #define ERIAR_MASK_SHIFT 12
441 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
442 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
443 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT)
444 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
445 EPHY_RXER_NUM = 0x7c,
446 OCPDR = 0xb0, /* OCP GPHY access */
447 #define OCPDR_WRITE_CMD 0x80000000
448 #define OCPDR_READ_CMD 0x00000000
449 #define OCPDR_REG_MASK 0x7f
450 #define OCPDR_GPHY_REG_SHIFT 16
451 #define OCPDR_DATA_MASK 0xffff
453 #define OCPAR_FLAG 0x80000000
454 #define OCPAR_GPHY_WRITE_CMD 0x8000f060
455 #define OCPAR_GPHY_READ_CMD 0x0000f060
457 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
458 MISC = 0xf0, /* 8168e only. */
459 #define TXPLA_RST (1 << 29)
460 #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */
461 #define PWM_EN (1 << 22)
462 #define RXDV_GATED_EN (1 << 19)
463 #define EARLY_TALLY_EN (1 << 16)
466 enum rtl_register_content {
467 /* InterruptStatusBits */
471 TxDescUnavail = 0x0080,
495 /* TXPoll register p.5 */
496 HPQ = 0x80, /* Poll cmd on the high prio queue */
497 NPQ = 0x40, /* Poll cmd on the low prio queue */
498 FSWInt = 0x01, /* Forced software interrupt */
502 Cfg9346_Unlock = 0xc0,
507 AcceptBroadcast = 0x08,
508 AcceptMulticast = 0x04,
510 AcceptAllPhys = 0x01,
511 #define RX_CONFIG_ACCEPT_MASK 0x3f
514 TxInterFrameGapShift = 24,
515 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
517 /* Config1 register p.24 */
520 Speed_down = (1 << 4),
524 PMEnable = (1 << 0), /* Power Management Enable */
526 /* Config2 register p. 25 */
527 ClkReqEn = (1 << 7), /* Clock Request Enable */
528 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
529 PCI_Clock_66MHz = 0x01,
530 PCI_Clock_33MHz = 0x00,
532 /* Config3 register p.25 */
533 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
534 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
535 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
536 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
538 /* Config4 register */
539 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
541 /* Config5 register p.27 */
542 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
543 MWF = (1 << 5), /* Accept Multicast wakeup frame */
544 UWF = (1 << 4), /* Accept Unicast wakeup frame */
546 LanWake = (1 << 1), /* LanWake enable/disable */
547 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
548 ASPM_en = (1 << 0), /* ASPM enable */
551 TBIReset = 0x80000000,
552 TBILoopback = 0x40000000,
553 TBINwEnable = 0x20000000,
554 TBINwRestart = 0x10000000,
555 TBILinkOk = 0x02000000,
556 TBINwComplete = 0x01000000,
559 EnableBist = (1 << 15), // 8168 8101
560 Mac_dbgo_oe = (1 << 14), // 8168 8101
561 Normal_mode = (1 << 13), // unused
562 Force_half_dup = (1 << 12), // 8168 8101
563 Force_rxflow_en = (1 << 11), // 8168 8101
564 Force_txflow_en = (1 << 10), // 8168 8101
565 Cxpl_dbg_sel = (1 << 9), // 8168 8101
566 ASF = (1 << 8), // 8168 8101
567 PktCntrDisable = (1 << 7), // 8168 8101
568 Mac_dbgo_sel = 0x001c, // 8168
573 INTT_0 = 0x0000, // 8168
574 INTT_1 = 0x0001, // 8168
575 INTT_2 = 0x0002, // 8168
576 INTT_3 = 0x0003, // 8168
578 /* rtl8169_PHYstatus */
589 TBILinkOK = 0x02000000,
591 /* DumpCounterCommand */
596 /* First doubleword. */
597 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
598 RingEnd = (1 << 30), /* End of descriptor ring */
599 FirstFrag = (1 << 29), /* First segment of a packet */
600 LastFrag = (1 << 28), /* Final segment of a packet */
604 enum rtl_tx_desc_bit {
605 /* First doubleword. */
606 TD_LSO = (1 << 27), /* Large Send Offload */
607 #define TD_MSS_MAX 0x07ffu /* MSS value */
609 /* Second doubleword. */
610 TxVlanTag = (1 << 17), /* Add VLAN tag */
613 /* 8169, 8168b and 810x except 8102e. */
614 enum rtl_tx_desc_bit_0 {
615 /* First doubleword. */
616 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
617 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
618 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
619 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
622 /* 8102e, 8168c and beyond. */
623 enum rtl_tx_desc_bit_1 {
624 /* Second doubleword. */
625 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
626 TD1_IP_CS = (1 << 29), /* Calculate IP checksum */
627 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
628 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
631 static const struct rtl_tx_desc_info {
638 } tx_desc_info [] = {
641 .udp = TD0_IP_CS | TD0_UDP_CS,
642 .tcp = TD0_IP_CS | TD0_TCP_CS
644 .mss_shift = TD0_MSS_SHIFT,
649 .udp = TD1_IP_CS | TD1_UDP_CS,
650 .tcp = TD1_IP_CS | TD1_TCP_CS
652 .mss_shift = TD1_MSS_SHIFT,
657 enum rtl_rx_desc_bit {
659 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
660 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
662 #define RxProtoUDP (PID1)
663 #define RxProtoTCP (PID0)
664 #define RxProtoIP (PID1 | PID0)
665 #define RxProtoMask RxProtoIP
667 IPFail = (1 << 16), /* IP checksum failed */
668 UDPFail = (1 << 15), /* UDP/IP checksum failed */
669 TCPFail = (1 << 14), /* TCP/IP checksum failed */
670 RxVlanTag = (1 << 16), /* VLAN tag available */
673 #define RsvdMask 0x3fffc000
690 u8 __pad[sizeof(void *) - sizeof(u32)];
694 RTL_FEATURE_WOL = (1 << 0),
695 RTL_FEATURE_MSI = (1 << 1),
696 RTL_FEATURE_GMII = (1 << 2),
699 struct rtl8169_counters {
706 __le32 tx_one_collision;
707 __le32 tx_multi_collision;
716 RTL_FLAG_TASK_ENABLED,
717 RTL_FLAG_TASK_SLOW_PENDING,
718 RTL_FLAG_TASK_RESET_PENDING,
719 RTL_FLAG_TASK_PHY_PENDING,
723 struct rtl8169_stats {
726 struct u64_stats_sync syncp;
729 struct rtl8169_private {
730 void __iomem *mmio_addr; /* memory map physical address */
731 struct pci_dev *pci_dev;
732 struct net_device *dev;
733 struct napi_struct napi;
737 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
738 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
740 struct rtl8169_stats rx_stats;
741 struct rtl8169_stats tx_stats;
742 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
743 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
744 dma_addr_t TxPhyAddr;
745 dma_addr_t RxPhyAddr;
746 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
747 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
748 struct timer_list timer;
754 void (*write)(struct rtl8169_private *, int, int);
755 int (*read)(struct rtl8169_private *, int);
758 struct pll_power_ops {
759 void (*down)(struct rtl8169_private *);
760 void (*up)(struct rtl8169_private *);
764 void (*enable)(struct rtl8169_private *);
765 void (*disable)(struct rtl8169_private *);
769 void (*write)(struct rtl8169_private *, int, int);
770 u32 (*read)(struct rtl8169_private *, int);
773 int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
774 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
775 void (*phy_reset_enable)(struct rtl8169_private *tp);
776 void (*hw_start)(struct net_device *);
777 unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
778 unsigned int (*link_ok)(void __iomem *);
779 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
782 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
784 struct work_struct work;
789 struct mii_if_info mii;
790 struct rtl8169_counters counters;
795 const struct firmware *fw;
797 #define RTL_VER_SIZE 32
799 char version[RTL_VER_SIZE];
801 struct rtl_fw_phy_action {
806 #define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN)
811 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
812 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
813 module_param(use_dac, int, 0);
814 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
815 module_param_named(debug, debug.msg_enable, int, 0);
816 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
817 MODULE_LICENSE("GPL");
818 MODULE_VERSION(RTL8169_VERSION);
819 MODULE_FIRMWARE(FIRMWARE_8168D_1);
820 MODULE_FIRMWARE(FIRMWARE_8168D_2);
821 MODULE_FIRMWARE(FIRMWARE_8168E_1);
822 MODULE_FIRMWARE(FIRMWARE_8168E_2);
823 MODULE_FIRMWARE(FIRMWARE_8168E_3);
824 MODULE_FIRMWARE(FIRMWARE_8105E_1);
825 MODULE_FIRMWARE(FIRMWARE_8168F_1);
826 MODULE_FIRMWARE(FIRMWARE_8168F_2);
827 MODULE_FIRMWARE(FIRMWARE_8402_1);
828 MODULE_FIRMWARE(FIRMWARE_8411_1);
829 MODULE_FIRMWARE(FIRMWARE_8106E_1);
830 MODULE_FIRMWARE(FIRMWARE_8106E_2);
831 MODULE_FIRMWARE(FIRMWARE_8168G_2);
832 MODULE_FIRMWARE(FIRMWARE_8168G_3);
834 static void rtl_lock_work(struct rtl8169_private *tp)
836 mutex_lock(&tp->wk.mutex);
839 static void rtl_unlock_work(struct rtl8169_private *tp)
841 mutex_unlock(&tp->wk.mutex);
844 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
846 pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL,
847 PCI_EXP_DEVCTL_READRQ, force);
851 bool (*check)(struct rtl8169_private *);
855 static void rtl_udelay(unsigned int d)
860 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
861 void (*delay)(unsigned int), unsigned int d, int n,
866 for (i = 0; i < n; i++) {
868 if (c->check(tp) == high)
871 netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
872 c->msg, !high, n, d);
876 static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
877 const struct rtl_cond *c,
878 unsigned int d, int n)
880 return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
883 static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
884 const struct rtl_cond *c,
885 unsigned int d, int n)
887 return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
890 static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
891 const struct rtl_cond *c,
892 unsigned int d, int n)
894 return rtl_loop_wait(tp, c, msleep, d, n, true);
897 static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
898 const struct rtl_cond *c,
899 unsigned int d, int n)
901 return rtl_loop_wait(tp, c, msleep, d, n, false);
904 #define DECLARE_RTL_COND(name) \
905 static bool name ## _check(struct rtl8169_private *); \
907 static const struct rtl_cond name = { \
908 .check = name ## _check, \
912 static bool name ## _check(struct rtl8169_private *tp)
914 DECLARE_RTL_COND(rtl_ocpar_cond)
916 void __iomem *ioaddr = tp->mmio_addr;
918 return RTL_R32(OCPAR) & OCPAR_FLAG;
921 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
923 void __iomem *ioaddr = tp->mmio_addr;
925 RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
927 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
931 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
933 void __iomem *ioaddr = tp->mmio_addr;
935 RTL_W32(OCPDR, data);
936 RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
938 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
941 DECLARE_RTL_COND(rtl_eriar_cond)
943 void __iomem *ioaddr = tp->mmio_addr;
945 return RTL_R32(ERIAR) & ERIAR_FLAG;
948 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
950 void __iomem *ioaddr = tp->mmio_addr;
953 RTL_W32(ERIAR, 0x800010e8);
956 if (!rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 5))
959 ocp_write(tp, 0x1, 0x30, 0x00000001);
962 #define OOB_CMD_RESET 0x00
963 #define OOB_CMD_DRIVER_START 0x05
964 #define OOB_CMD_DRIVER_STOP 0x06
966 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
968 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
971 DECLARE_RTL_COND(rtl_ocp_read_cond)
975 reg = rtl8168_get_ocp_reg(tp);
977 return ocp_read(tp, 0x0f, reg) & 0x00000800;
980 static void rtl8168_driver_start(struct rtl8169_private *tp)
982 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
984 rtl_msleep_loop_wait_high(tp, &rtl_ocp_read_cond, 10, 10);
987 static void rtl8168_driver_stop(struct rtl8169_private *tp)
989 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
991 rtl_msleep_loop_wait_low(tp, &rtl_ocp_read_cond, 10, 10);
994 static int r8168dp_check_dash(struct rtl8169_private *tp)
996 u16 reg = rtl8168_get_ocp_reg(tp);
998 return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
1001 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
1003 if (reg & 0xffff0001) {
1004 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
1010 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
1012 void __iomem *ioaddr = tp->mmio_addr;
1014 return RTL_R32(GPHY_OCP) & OCPAR_FLAG;
1017 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
1019 void __iomem *ioaddr = tp->mmio_addr;
1021 if (rtl_ocp_reg_failure(tp, reg))
1024 RTL_W32(GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
1026 rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
1029 static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
1031 void __iomem *ioaddr = tp->mmio_addr;
1033 if (rtl_ocp_reg_failure(tp, reg))
1036 RTL_W32(GPHY_OCP, reg << 15);
1038 return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
1039 (RTL_R32(GPHY_OCP) & 0xffff) : ~0;
1042 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
1044 void __iomem *ioaddr = tp->mmio_addr;
1046 if (rtl_ocp_reg_failure(tp, reg))
1049 RTL_W32(OCPDR, OCPAR_FLAG | (reg << 15) | data);
1052 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
1054 void __iomem *ioaddr = tp->mmio_addr;
1056 if (rtl_ocp_reg_failure(tp, reg))
1059 RTL_W32(OCPDR, reg << 15);
1061 return RTL_R32(OCPDR);
1064 #define OCP_STD_PHY_BASE 0xa400
1066 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
1069 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
1073 if (tp->ocp_base != OCP_STD_PHY_BASE)
1076 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
1079 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
1081 if (tp->ocp_base != OCP_STD_PHY_BASE)
1084 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
1087 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
1090 tp->ocp_base = value << 4;
1094 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
1097 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
1099 return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
1102 DECLARE_RTL_COND(rtl_phyar_cond)
1104 void __iomem *ioaddr = tp->mmio_addr;
1106 return RTL_R32(PHYAR) & 0x80000000;
1109 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
1111 void __iomem *ioaddr = tp->mmio_addr;
1113 RTL_W32(PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
1115 rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
1117 * According to hardware specs a 20us delay is required after write
1118 * complete indication, but before sending next command.
1123 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
1125 void __iomem *ioaddr = tp->mmio_addr;
1128 RTL_W32(PHYAR, 0x0 | (reg & 0x1f) << 16);
1130 value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
1131 RTL_R32(PHYAR) & 0xffff : ~0;
1134 * According to hardware specs a 20us delay is required after read
1135 * complete indication, but before sending next command.
1142 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
1144 void __iomem *ioaddr = tp->mmio_addr;
1146 RTL_W32(OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
1147 RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
1148 RTL_W32(EPHY_RXER_NUM, 0);
1150 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
1153 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
1155 r8168dp_1_mdio_access(tp, reg,
1156 OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
1159 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
1161 void __iomem *ioaddr = tp->mmio_addr;
1163 r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
1166 RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
1167 RTL_W32(EPHY_RXER_NUM, 0);
1169 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
1170 RTL_R32(OCPDR) & OCPDR_DATA_MASK : ~0;
1173 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
1175 static void r8168dp_2_mdio_start(void __iomem *ioaddr)
1177 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
1180 static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
1182 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
1185 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
1187 void __iomem *ioaddr = tp->mmio_addr;
1189 r8168dp_2_mdio_start(ioaddr);
1191 r8169_mdio_write(tp, reg, value);
1193 r8168dp_2_mdio_stop(ioaddr);
1196 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
1198 void __iomem *ioaddr = tp->mmio_addr;
1201 r8168dp_2_mdio_start(ioaddr);
1203 value = r8169_mdio_read(tp, reg);
1205 r8168dp_2_mdio_stop(ioaddr);
1210 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
1212 tp->mdio_ops.write(tp, location, val);
1215 static int rtl_readphy(struct rtl8169_private *tp, int location)
1217 return tp->mdio_ops.read(tp, location);
1220 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1222 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1225 static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1229 val = rtl_readphy(tp, reg_addr);
1230 rtl_writephy(tp, reg_addr, (val | p) & ~m);
1233 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
1236 struct rtl8169_private *tp = netdev_priv(dev);
1238 rtl_writephy(tp, location, val);
1241 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1243 struct rtl8169_private *tp = netdev_priv(dev);
1245 return rtl_readphy(tp, location);
1248 DECLARE_RTL_COND(rtl_ephyar_cond)
1250 void __iomem *ioaddr = tp->mmio_addr;
1252 return RTL_R32(EPHYAR) & EPHYAR_FLAG;
1255 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1257 void __iomem *ioaddr = tp->mmio_addr;
1259 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1260 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1262 rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1267 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1269 void __iomem *ioaddr = tp->mmio_addr;
1271 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1273 return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1274 RTL_R32(EPHYAR) & EPHYAR_DATA_MASK : ~0;
1277 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1280 void __iomem *ioaddr = tp->mmio_addr;
1282 BUG_ON((addr & 3) || (mask == 0));
1283 RTL_W32(ERIDR, val);
1284 RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1286 rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
1289 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
1291 void __iomem *ioaddr = tp->mmio_addr;
1293 RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1295 return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1296 RTL_R32(ERIDR) : ~0;
1299 static void rtl_w1w0_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1304 val = rtl_eri_read(tp, addr, type);
1305 rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
1314 static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
1315 const struct exgmac_reg *r, int len)
1318 rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1323 DECLARE_RTL_COND(rtl_efusear_cond)
1325 void __iomem *ioaddr = tp->mmio_addr;
1327 return RTL_R32(EFUSEAR) & EFUSEAR_FLAG;
1330 static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1332 void __iomem *ioaddr = tp->mmio_addr;
1334 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1336 return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1337 RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1340 static u16 rtl_get_events(struct rtl8169_private *tp)
1342 void __iomem *ioaddr = tp->mmio_addr;
1344 return RTL_R16(IntrStatus);
1347 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1349 void __iomem *ioaddr = tp->mmio_addr;
1351 RTL_W16(IntrStatus, bits);
1355 static void rtl_irq_disable(struct rtl8169_private *tp)
1357 void __iomem *ioaddr = tp->mmio_addr;
1359 RTL_W16(IntrMask, 0);
1363 static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1365 void __iomem *ioaddr = tp->mmio_addr;
1367 RTL_W16(IntrMask, bits);
1370 #define RTL_EVENT_NAPI_RX (RxOK | RxErr)
1371 #define RTL_EVENT_NAPI_TX (TxOK | TxErr)
1372 #define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1374 static void rtl_irq_enable_all(struct rtl8169_private *tp)
1376 rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1379 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1381 void __iomem *ioaddr = tp->mmio_addr;
1383 rtl_irq_disable(tp);
1384 rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
1388 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1390 void __iomem *ioaddr = tp->mmio_addr;
1392 return RTL_R32(TBICSR) & TBIReset;
1395 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1397 return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1400 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1402 return RTL_R32(TBICSR) & TBILinkOk;
1405 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1407 return RTL_R8(PHYstatus) & LinkStatus;
1410 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1412 void __iomem *ioaddr = tp->mmio_addr;
1414 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1417 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1421 val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1422 rtl_writephy(tp, MII_BMCR, val & 0xffff);
1425 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1427 void __iomem *ioaddr = tp->mmio_addr;
1428 struct net_device *dev = tp->dev;
1430 if (!netif_running(dev))
1433 if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1434 tp->mac_version == RTL_GIGA_MAC_VER_38) {
1435 if (RTL_R8(PHYstatus) & _1000bpsF) {
1436 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1438 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1440 } else if (RTL_R8(PHYstatus) & _100bps) {
1441 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1443 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1446 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1448 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1451 /* Reset packet filter */
1452 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1454 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1456 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1457 tp->mac_version == RTL_GIGA_MAC_VER_36) {
1458 if (RTL_R8(PHYstatus) & _1000bpsF) {
1459 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1461 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1464 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1466 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1469 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1470 if (RTL_R8(PHYstatus) & _10bps) {
1471 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,
1473 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,
1476 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,
1482 static void __rtl8169_check_link_status(struct net_device *dev,
1483 struct rtl8169_private *tp,
1484 void __iomem *ioaddr, bool pm)
1486 if (tp->link_ok(ioaddr)) {
1487 rtl_link_chg_patch(tp);
1488 /* This is to cancel a scheduled suspend if there's one. */
1490 pm_request_resume(&tp->pci_dev->dev);
1491 netif_carrier_on(dev);
1492 if (net_ratelimit())
1493 netif_info(tp, ifup, dev, "link up\n");
1495 netif_carrier_off(dev);
1496 netif_info(tp, ifdown, dev, "link down\n");
1498 pm_schedule_suspend(&tp->pci_dev->dev, 5000);
1502 static void rtl8169_check_link_status(struct net_device *dev,
1503 struct rtl8169_private *tp,
1504 void __iomem *ioaddr)
1506 __rtl8169_check_link_status(dev, tp, ioaddr, false);
1509 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1511 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1513 void __iomem *ioaddr = tp->mmio_addr;
1517 options = RTL_R8(Config1);
1518 if (!(options & PMEnable))
1521 options = RTL_R8(Config3);
1522 if (options & LinkUp)
1523 wolopts |= WAKE_PHY;
1524 if (options & MagicPacket)
1525 wolopts |= WAKE_MAGIC;
1527 options = RTL_R8(Config5);
1529 wolopts |= WAKE_UCAST;
1531 wolopts |= WAKE_BCAST;
1533 wolopts |= WAKE_MCAST;
1538 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1540 struct rtl8169_private *tp = netdev_priv(dev);
1544 wol->supported = WAKE_ANY;
1545 wol->wolopts = __rtl8169_get_wol(tp);
1547 rtl_unlock_work(tp);
1550 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1552 void __iomem *ioaddr = tp->mmio_addr;
1554 static const struct {
1559 { WAKE_PHY, Config3, LinkUp },
1560 { WAKE_MAGIC, Config3, MagicPacket },
1561 { WAKE_UCAST, Config5, UWF },
1562 { WAKE_BCAST, Config5, BWF },
1563 { WAKE_MCAST, Config5, MWF },
1564 { WAKE_ANY, Config5, LanWake }
1568 RTL_W8(Cfg9346, Cfg9346_Unlock);
1570 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1571 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
1572 if (wolopts & cfg[i].opt)
1573 options |= cfg[i].mask;
1574 RTL_W8(cfg[i].reg, options);
1577 switch (tp->mac_version) {
1578 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1579 options = RTL_R8(Config1) & ~PMEnable;
1581 options |= PMEnable;
1582 RTL_W8(Config1, options);
1585 options = RTL_R8(Config2) & ~PME_SIGNAL;
1587 options |= PME_SIGNAL;
1588 RTL_W8(Config2, options);
1592 RTL_W8(Cfg9346, Cfg9346_Lock);
1595 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1597 struct rtl8169_private *tp = netdev_priv(dev);
1602 tp->features |= RTL_FEATURE_WOL;
1604 tp->features &= ~RTL_FEATURE_WOL;
1605 __rtl8169_set_wol(tp, wol->wolopts);
1607 rtl_unlock_work(tp);
1609 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1614 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1616 return rtl_chip_infos[tp->mac_version].fw_name;
1619 static void rtl8169_get_drvinfo(struct net_device *dev,
1620 struct ethtool_drvinfo *info)
1622 struct rtl8169_private *tp = netdev_priv(dev);
1623 struct rtl_fw *rtl_fw = tp->rtl_fw;
1625 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1626 strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
1627 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1628 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1629 if (!IS_ERR_OR_NULL(rtl_fw))
1630 strlcpy(info->fw_version, rtl_fw->version,
1631 sizeof(info->fw_version));
1634 static int rtl8169_get_regs_len(struct net_device *dev)
1636 return R8169_REGS_SIZE;
1639 static int rtl8169_set_speed_tbi(struct net_device *dev,
1640 u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1642 struct rtl8169_private *tp = netdev_priv(dev);
1643 void __iomem *ioaddr = tp->mmio_addr;
1647 reg = RTL_R32(TBICSR);
1648 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1649 (duplex == DUPLEX_FULL)) {
1650 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1651 } else if (autoneg == AUTONEG_ENABLE)
1652 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1654 netif_warn(tp, link, dev,
1655 "incorrect speed setting refused in TBI mode\n");
1662 static int rtl8169_set_speed_xmii(struct net_device *dev,
1663 u8 autoneg, u16 speed, u8 duplex, u32 adv)
1665 struct rtl8169_private *tp = netdev_priv(dev);
1666 int giga_ctrl, bmcr;
1669 rtl_writephy(tp, 0x1f, 0x0000);
1671 if (autoneg == AUTONEG_ENABLE) {
1674 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1675 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1676 ADVERTISE_100HALF | ADVERTISE_100FULL);
1678 if (adv & ADVERTISED_10baseT_Half)
1679 auto_nego |= ADVERTISE_10HALF;
1680 if (adv & ADVERTISED_10baseT_Full)
1681 auto_nego |= ADVERTISE_10FULL;
1682 if (adv & ADVERTISED_100baseT_Half)
1683 auto_nego |= ADVERTISE_100HALF;
1684 if (adv & ADVERTISED_100baseT_Full)
1685 auto_nego |= ADVERTISE_100FULL;
1687 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1689 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1690 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1692 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1693 if (tp->mii.supports_gmii) {
1694 if (adv & ADVERTISED_1000baseT_Half)
1695 giga_ctrl |= ADVERTISE_1000HALF;
1696 if (adv & ADVERTISED_1000baseT_Full)
1697 giga_ctrl |= ADVERTISE_1000FULL;
1698 } else if (adv & (ADVERTISED_1000baseT_Half |
1699 ADVERTISED_1000baseT_Full)) {
1700 netif_info(tp, link, dev,
1701 "PHY does not support 1000Mbps\n");
1705 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1707 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1708 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1712 if (speed == SPEED_10)
1714 else if (speed == SPEED_100)
1715 bmcr = BMCR_SPEED100;
1719 if (duplex == DUPLEX_FULL)
1720 bmcr |= BMCR_FULLDPLX;
1723 rtl_writephy(tp, MII_BMCR, bmcr);
1725 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1726 tp->mac_version == RTL_GIGA_MAC_VER_03) {
1727 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1728 rtl_writephy(tp, 0x17, 0x2138);
1729 rtl_writephy(tp, 0x0e, 0x0260);
1731 rtl_writephy(tp, 0x17, 0x2108);
1732 rtl_writephy(tp, 0x0e, 0x0000);
1741 static int rtl8169_set_speed(struct net_device *dev,
1742 u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1744 struct rtl8169_private *tp = netdev_priv(dev);
1747 ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
1751 if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1752 (advertising & ADVERTISED_1000baseT_Full)) {
1753 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1759 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1761 struct rtl8169_private *tp = netdev_priv(dev);
1764 del_timer_sync(&tp->timer);
1767 ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
1768 cmd->duplex, cmd->advertising);
1769 rtl_unlock_work(tp);
1774 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1775 netdev_features_t features)
1777 struct rtl8169_private *tp = netdev_priv(dev);
1779 if (dev->mtu > TD_MSS_MAX)
1780 features &= ~NETIF_F_ALL_TSO;
1782 if (dev->mtu > JUMBO_1K &&
1783 !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
1784 features &= ~NETIF_F_IP_CSUM;
1789 static void __rtl8169_set_features(struct net_device *dev,
1790 netdev_features_t features)
1792 struct rtl8169_private *tp = netdev_priv(dev);
1793 netdev_features_t changed = features ^ dev->features;
1794 void __iomem *ioaddr = tp->mmio_addr;
1796 if (!(changed & (NETIF_F_RXALL | NETIF_F_RXCSUM | NETIF_F_HW_VLAN_RX)))
1799 if (changed & (NETIF_F_RXCSUM | NETIF_F_HW_VLAN_RX)) {
1800 if (features & NETIF_F_RXCSUM)
1801 tp->cp_cmd |= RxChkSum;
1803 tp->cp_cmd &= ~RxChkSum;
1805 if (dev->features & NETIF_F_HW_VLAN_RX)
1806 tp->cp_cmd |= RxVlan;
1808 tp->cp_cmd &= ~RxVlan;
1810 RTL_W16(CPlusCmd, tp->cp_cmd);
1813 if (changed & NETIF_F_RXALL) {
1814 int tmp = (RTL_R32(RxConfig) & ~(AcceptErr | AcceptRunt));
1815 if (features & NETIF_F_RXALL)
1816 tmp |= (AcceptErr | AcceptRunt);
1817 RTL_W32(RxConfig, tmp);
1821 static int rtl8169_set_features(struct net_device *dev,
1822 netdev_features_t features)
1824 struct rtl8169_private *tp = netdev_priv(dev);
1827 __rtl8169_set_features(dev, features);
1828 rtl_unlock_work(tp);
1834 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1836 return (vlan_tx_tag_present(skb)) ?
1837 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1840 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1842 u32 opts2 = le32_to_cpu(desc->opts2);
1844 if (opts2 & RxVlanTag)
1845 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
1848 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1850 struct rtl8169_private *tp = netdev_priv(dev);
1851 void __iomem *ioaddr = tp->mmio_addr;
1855 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1856 cmd->port = PORT_FIBRE;
1857 cmd->transceiver = XCVR_INTERNAL;
1859 status = RTL_R32(TBICSR);
1860 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1861 cmd->autoneg = !!(status & TBINwEnable);
1863 ethtool_cmd_speed_set(cmd, SPEED_1000);
1864 cmd->duplex = DUPLEX_FULL; /* Always set */
1869 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1871 struct rtl8169_private *tp = netdev_priv(dev);
1873 return mii_ethtool_gset(&tp->mii, cmd);
1876 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1878 struct rtl8169_private *tp = netdev_priv(dev);
1882 rc = tp->get_settings(dev, cmd);
1883 rtl_unlock_work(tp);
1888 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1891 struct rtl8169_private *tp = netdev_priv(dev);
1893 if (regs->len > R8169_REGS_SIZE)
1894 regs->len = R8169_REGS_SIZE;
1897 memcpy_fromio(p, tp->mmio_addr, regs->len);
1898 rtl_unlock_work(tp);
1901 static u32 rtl8169_get_msglevel(struct net_device *dev)
1903 struct rtl8169_private *tp = netdev_priv(dev);
1905 return tp->msg_enable;
1908 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1910 struct rtl8169_private *tp = netdev_priv(dev);
1912 tp->msg_enable = value;
1915 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1922 "tx_single_collisions",
1923 "tx_multi_collisions",
1931 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1935 return ARRAY_SIZE(rtl8169_gstrings);
1941 DECLARE_RTL_COND(rtl_counters_cond)
1943 void __iomem *ioaddr = tp->mmio_addr;
1945 return RTL_R32(CounterAddrLow) & CounterDump;
1948 static void rtl8169_update_counters(struct net_device *dev)
1950 struct rtl8169_private *tp = netdev_priv(dev);
1951 void __iomem *ioaddr = tp->mmio_addr;
1952 struct device *d = &tp->pci_dev->dev;
1953 struct rtl8169_counters *counters;
1958 * Some chips are unable to dump tally counters when the receiver
1961 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1964 counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
1968 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1969 cmd = (u64)paddr & DMA_BIT_MASK(32);
1970 RTL_W32(CounterAddrLow, cmd);
1971 RTL_W32(CounterAddrLow, cmd | CounterDump);
1973 if (rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000))
1974 memcpy(&tp->counters, counters, sizeof(*counters));
1976 RTL_W32(CounterAddrLow, 0);
1977 RTL_W32(CounterAddrHigh, 0);
1979 dma_free_coherent(d, sizeof(*counters), counters, paddr);
1982 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1983 struct ethtool_stats *stats, u64 *data)
1985 struct rtl8169_private *tp = netdev_priv(dev);
1989 rtl8169_update_counters(dev);
1991 data[0] = le64_to_cpu(tp->counters.tx_packets);
1992 data[1] = le64_to_cpu(tp->counters.rx_packets);
1993 data[2] = le64_to_cpu(tp->counters.tx_errors);
1994 data[3] = le32_to_cpu(tp->counters.rx_errors);
1995 data[4] = le16_to_cpu(tp->counters.rx_missed);
1996 data[5] = le16_to_cpu(tp->counters.align_errors);
1997 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1998 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1999 data[8] = le64_to_cpu(tp->counters.rx_unicast);
2000 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
2001 data[10] = le32_to_cpu(tp->counters.rx_multicast);
2002 data[11] = le16_to_cpu(tp->counters.tx_aborted);
2003 data[12] = le16_to_cpu(tp->counters.tx_underun);
2006 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2010 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
2015 static const struct ethtool_ops rtl8169_ethtool_ops = {
2016 .get_drvinfo = rtl8169_get_drvinfo,
2017 .get_regs_len = rtl8169_get_regs_len,
2018 .get_link = ethtool_op_get_link,
2019 .get_settings = rtl8169_get_settings,
2020 .set_settings = rtl8169_set_settings,
2021 .get_msglevel = rtl8169_get_msglevel,
2022 .set_msglevel = rtl8169_set_msglevel,
2023 .get_regs = rtl8169_get_regs,
2024 .get_wol = rtl8169_get_wol,
2025 .set_wol = rtl8169_set_wol,
2026 .get_strings = rtl8169_get_strings,
2027 .get_sset_count = rtl8169_get_sset_count,
2028 .get_ethtool_stats = rtl8169_get_ethtool_stats,
2029 .get_ts_info = ethtool_op_get_ts_info,
2032 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
2033 struct net_device *dev, u8 default_version)
2035 void __iomem *ioaddr = tp->mmio_addr;
2037 * The driver currently handles the 8168Bf and the 8168Be identically
2038 * but they can be identified more specifically through the test below
2041 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2043 * Same thing for the 8101Eb and the 8101Ec:
2045 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2047 static const struct rtl_mac_info {
2053 { 0x7cf00000, 0x50900000, RTL_GIGA_MAC_VER_42 },
2054 { 0x7cf00000, 0x4c100000, RTL_GIGA_MAC_VER_41 },
2055 { 0x7cf00000, 0x4c000000, RTL_GIGA_MAC_VER_40 },
2058 { 0x7c800000, 0x48800000, RTL_GIGA_MAC_VER_38 },
2059 { 0x7cf00000, 0x48100000, RTL_GIGA_MAC_VER_36 },
2060 { 0x7cf00000, 0x48000000, RTL_GIGA_MAC_VER_35 },
2063 { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34 },
2064 { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33 },
2065 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 },
2066 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 },
2069 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
2070 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
2071 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
2073 /* 8168DP family. */
2074 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
2075 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
2076 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 },
2079 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 },
2080 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
2081 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
2082 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
2083 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
2084 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
2085 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
2086 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
2087 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
2090 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
2091 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
2092 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
2093 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
2096 { 0x7cf00000, 0x44900000, RTL_GIGA_MAC_VER_39 },
2097 { 0x7c800000, 0x44800000, RTL_GIGA_MAC_VER_39 },
2098 { 0x7c800000, 0x44000000, RTL_GIGA_MAC_VER_37 },
2099 { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30 },
2100 { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30 },
2101 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 },
2102 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 },
2103 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
2104 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
2105 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
2106 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
2107 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
2108 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
2109 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
2110 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
2111 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
2112 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
2113 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
2114 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
2115 /* FIXME: where did these entries come from ? -- FR */
2116 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
2117 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
2120 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
2121 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
2122 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
2123 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
2124 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
2125 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
2128 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
2130 const struct rtl_mac_info *p = mac_info;
2133 reg = RTL_R32(TxConfig);
2134 while ((reg & p->mask) != p->val)
2136 tp->mac_version = p->mac_version;
2138 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2139 netif_notice(tp, probe, dev,
2140 "unknown MAC, using family default\n");
2141 tp->mac_version = default_version;
2142 } else if (tp->mac_version == RTL_GIGA_MAC_VER_42) {
2143 tp->mac_version = tp->mii.supports_gmii ?
2144 RTL_GIGA_MAC_VER_42 :
2145 RTL_GIGA_MAC_VER_43;
2149 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
2151 dprintk("mac_version = 0x%02x\n", tp->mac_version);
2159 static void rtl_writephy_batch(struct rtl8169_private *tp,
2160 const struct phy_reg *regs, int len)
2163 rtl_writephy(tp, regs->reg, regs->val);
2168 #define PHY_READ 0x00000000
2169 #define PHY_DATA_OR 0x10000000
2170 #define PHY_DATA_AND 0x20000000
2171 #define PHY_BJMPN 0x30000000
2172 #define PHY_MDIO_CHG 0x40000000
2173 #define PHY_CLEAR_READCOUNT 0x70000000
2174 #define PHY_WRITE 0x80000000
2175 #define PHY_READCOUNT_EQ_SKIP 0x90000000
2176 #define PHY_COMP_EQ_SKIPN 0xa0000000
2177 #define PHY_COMP_NEQ_SKIPN 0xb0000000
2178 #define PHY_WRITE_PREVIOUS 0xc0000000
2179 #define PHY_SKIPN 0xd0000000
2180 #define PHY_DELAY_MS 0xe0000000
2184 char version[RTL_VER_SIZE];
2190 #define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2192 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2194 const struct firmware *fw = rtl_fw->fw;
2195 struct fw_info *fw_info = (struct fw_info *)fw->data;
2196 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2197 char *version = rtl_fw->version;
2200 if (fw->size < FW_OPCODE_SIZE)
2203 if (!fw_info->magic) {
2204 size_t i, size, start;
2207 if (fw->size < sizeof(*fw_info))
2210 for (i = 0; i < fw->size; i++)
2211 checksum += fw->data[i];
2215 start = le32_to_cpu(fw_info->fw_start);
2216 if (start > fw->size)
2219 size = le32_to_cpu(fw_info->fw_len);
2220 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2223 memcpy(version, fw_info->version, RTL_VER_SIZE);
2225 pa->code = (__le32 *)(fw->data + start);
2228 if (fw->size % FW_OPCODE_SIZE)
2231 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2233 pa->code = (__le32 *)fw->data;
2234 pa->size = fw->size / FW_OPCODE_SIZE;
2236 version[RTL_VER_SIZE - 1] = 0;
2243 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2244 struct rtl_fw_phy_action *pa)
2249 for (index = 0; index < pa->size; index++) {
2250 u32 action = le32_to_cpu(pa->code[index]);
2251 u32 regno = (action & 0x0fff0000) >> 16;
2253 switch(action & 0xf0000000) {
2258 case PHY_CLEAR_READCOUNT:
2260 case PHY_WRITE_PREVIOUS:
2265 if (regno > index) {
2266 netif_err(tp, ifup, tp->dev,
2267 "Out of range of firmware\n");
2271 case PHY_READCOUNT_EQ_SKIP:
2272 if (index + 2 >= pa->size) {
2273 netif_err(tp, ifup, tp->dev,
2274 "Out of range of firmware\n");
2278 case PHY_COMP_EQ_SKIPN:
2279 case PHY_COMP_NEQ_SKIPN:
2281 if (index + 1 + regno >= pa->size) {
2282 netif_err(tp, ifup, tp->dev,
2283 "Out of range of firmware\n");
2289 netif_err(tp, ifup, tp->dev,
2290 "Invalid action 0x%08x\n", action);
2299 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2301 struct net_device *dev = tp->dev;
2304 if (!rtl_fw_format_ok(tp, rtl_fw)) {
2305 netif_err(tp, ifup, dev, "invalid firwmare\n");
2309 if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2315 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2317 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2318 struct mdio_ops org, *ops = &tp->mdio_ops;
2322 predata = count = 0;
2323 org.write = ops->write;
2324 org.read = ops->read;
2326 for (index = 0; index < pa->size; ) {
2327 u32 action = le32_to_cpu(pa->code[index]);
2328 u32 data = action & 0x0000ffff;
2329 u32 regno = (action & 0x0fff0000) >> 16;
2334 switch(action & 0xf0000000) {
2336 predata = rtl_readphy(tp, regno);
2353 ops->write = org.write;
2354 ops->read = org.read;
2355 } else if (data == 1) {
2356 ops->write = mac_mcu_write;
2357 ops->read = mac_mcu_read;
2362 case PHY_CLEAR_READCOUNT:
2367 rtl_writephy(tp, regno, data);
2370 case PHY_READCOUNT_EQ_SKIP:
2371 index += (count == data) ? 2 : 1;
2373 case PHY_COMP_EQ_SKIPN:
2374 if (predata == data)
2378 case PHY_COMP_NEQ_SKIPN:
2379 if (predata != data)
2383 case PHY_WRITE_PREVIOUS:
2384 rtl_writephy(tp, regno, predata);
2400 ops->write = org.write;
2401 ops->read = org.read;
2404 static void rtl_release_firmware(struct rtl8169_private *tp)
2406 if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2407 release_firmware(tp->rtl_fw->fw);
2410 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
2413 static void rtl_apply_firmware(struct rtl8169_private *tp)
2415 struct rtl_fw *rtl_fw = tp->rtl_fw;
2417 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2418 if (!IS_ERR_OR_NULL(rtl_fw))
2419 rtl_phy_write_fw(tp, rtl_fw);
2422 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2424 if (rtl_readphy(tp, reg) != val)
2425 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2427 rtl_apply_firmware(tp);
2430 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2432 static const struct phy_reg phy_reg_init[] = {
2494 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2497 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2499 static const struct phy_reg phy_reg_init[] = {
2505 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2508 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2510 struct pci_dev *pdev = tp->pci_dev;
2512 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2513 (pdev->subsystem_device != 0xe000))
2516 rtl_writephy(tp, 0x1f, 0x0001);
2517 rtl_writephy(tp, 0x10, 0xf01b);
2518 rtl_writephy(tp, 0x1f, 0x0000);
2521 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2523 static const struct phy_reg phy_reg_init[] = {
2563 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2565 rtl8169scd_hw_phy_config_quirk(tp);
2568 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2570 static const struct phy_reg phy_reg_init[] = {
2618 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2621 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2623 static const struct phy_reg phy_reg_init[] = {
2628 rtl_writephy(tp, 0x1f, 0x0001);
2629 rtl_patchphy(tp, 0x16, 1 << 0);
2631 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2634 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2636 static const struct phy_reg phy_reg_init[] = {
2642 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2645 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2647 static const struct phy_reg phy_reg_init[] = {
2655 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2658 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2660 static const struct phy_reg phy_reg_init[] = {
2666 rtl_writephy(tp, 0x1f, 0x0000);
2667 rtl_patchphy(tp, 0x14, 1 << 5);
2668 rtl_patchphy(tp, 0x0d, 1 << 5);
2670 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2673 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2675 static const struct phy_reg phy_reg_init[] = {
2695 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2697 rtl_patchphy(tp, 0x14, 1 << 5);
2698 rtl_patchphy(tp, 0x0d, 1 << 5);
2699 rtl_writephy(tp, 0x1f, 0x0000);
2702 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2704 static const struct phy_reg phy_reg_init[] = {
2722 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2724 rtl_patchphy(tp, 0x16, 1 << 0);
2725 rtl_patchphy(tp, 0x14, 1 << 5);
2726 rtl_patchphy(tp, 0x0d, 1 << 5);
2727 rtl_writephy(tp, 0x1f, 0x0000);
2730 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2732 static const struct phy_reg phy_reg_init[] = {
2744 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2746 rtl_patchphy(tp, 0x16, 1 << 0);
2747 rtl_patchphy(tp, 0x14, 1 << 5);
2748 rtl_patchphy(tp, 0x0d, 1 << 5);
2749 rtl_writephy(tp, 0x1f, 0x0000);
2752 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2754 rtl8168c_3_hw_phy_config(tp);
2757 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2759 static const struct phy_reg phy_reg_init_0[] = {
2760 /* Channel Estimation */
2781 * Enhance line driver power
2790 * Can not link to 1Gbps with bad cable
2791 * Decrease SNR threshold form 21.07dB to 19.04dB
2800 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2804 * Fine Tune Switching regulator parameter
2806 rtl_writephy(tp, 0x1f, 0x0002);
2807 rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2808 rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
2810 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2811 static const struct phy_reg phy_reg_init[] = {
2821 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2823 val = rtl_readphy(tp, 0x0d);
2825 if ((val & 0x00ff) != 0x006c) {
2826 static const u32 set[] = {
2827 0x0065, 0x0066, 0x0067, 0x0068,
2828 0x0069, 0x006a, 0x006b, 0x006c
2832 rtl_writephy(tp, 0x1f, 0x0002);
2835 for (i = 0; i < ARRAY_SIZE(set); i++)
2836 rtl_writephy(tp, 0x0d, val | set[i]);
2839 static const struct phy_reg phy_reg_init[] = {
2847 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2850 /* RSET couple improve */
2851 rtl_writephy(tp, 0x1f, 0x0002);
2852 rtl_patchphy(tp, 0x0d, 0x0300);
2853 rtl_patchphy(tp, 0x0f, 0x0010);
2855 /* Fine tune PLL performance */
2856 rtl_writephy(tp, 0x1f, 0x0002);
2857 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2858 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2860 rtl_writephy(tp, 0x1f, 0x0005);
2861 rtl_writephy(tp, 0x05, 0x001b);
2863 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2865 rtl_writephy(tp, 0x1f, 0x0000);
2868 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2870 static const struct phy_reg phy_reg_init_0[] = {
2871 /* Channel Estimation */
2892 * Enhance line driver power
2901 * Can not link to 1Gbps with bad cable
2902 * Decrease SNR threshold form 21.07dB to 19.04dB
2911 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2913 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2914 static const struct phy_reg phy_reg_init[] = {
2925 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2927 val = rtl_readphy(tp, 0x0d);
2928 if ((val & 0x00ff) != 0x006c) {
2929 static const u32 set[] = {
2930 0x0065, 0x0066, 0x0067, 0x0068,
2931 0x0069, 0x006a, 0x006b, 0x006c
2935 rtl_writephy(tp, 0x1f, 0x0002);
2938 for (i = 0; i < ARRAY_SIZE(set); i++)
2939 rtl_writephy(tp, 0x0d, val | set[i]);
2942 static const struct phy_reg phy_reg_init[] = {
2950 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2953 /* Fine tune PLL performance */
2954 rtl_writephy(tp, 0x1f, 0x0002);
2955 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2956 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2958 /* Switching regulator Slew rate */
2959 rtl_writephy(tp, 0x1f, 0x0002);
2960 rtl_patchphy(tp, 0x0f, 0x0017);
2962 rtl_writephy(tp, 0x1f, 0x0005);
2963 rtl_writephy(tp, 0x05, 0x001b);
2965 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
2967 rtl_writephy(tp, 0x1f, 0x0000);
2970 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
2972 static const struct phy_reg phy_reg_init[] = {
3028 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3031 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
3033 static const struct phy_reg phy_reg_init[] = {
3043 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3044 rtl_patchphy(tp, 0x0d, 1 << 5);
3047 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
3049 static const struct phy_reg phy_reg_init[] = {
3050 /* Enable Delay cap */
3056 /* Channel estimation fine tune */
3065 /* Update PFM & 10M TX idle timer */
3077 rtl_apply_firmware(tp);
3079 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3081 /* DCO enable for 10M IDLE Power */
3082 rtl_writephy(tp, 0x1f, 0x0007);
3083 rtl_writephy(tp, 0x1e, 0x0023);
3084 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
3085 rtl_writephy(tp, 0x1f, 0x0000);
3087 /* For impedance matching */
3088 rtl_writephy(tp, 0x1f, 0x0002);
3089 rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
3090 rtl_writephy(tp, 0x1f, 0x0000);
3092 /* PHY auto speed down */
3093 rtl_writephy(tp, 0x1f, 0x0007);
3094 rtl_writephy(tp, 0x1e, 0x002d);
3095 rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
3096 rtl_writephy(tp, 0x1f, 0x0000);
3097 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3099 rtl_writephy(tp, 0x1f, 0x0005);
3100 rtl_writephy(tp, 0x05, 0x8b86);
3101 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3102 rtl_writephy(tp, 0x1f, 0x0000);
3104 rtl_writephy(tp, 0x1f, 0x0005);
3105 rtl_writephy(tp, 0x05, 0x8b85);
3106 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3107 rtl_writephy(tp, 0x1f, 0x0007);
3108 rtl_writephy(tp, 0x1e, 0x0020);
3109 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
3110 rtl_writephy(tp, 0x1f, 0x0006);
3111 rtl_writephy(tp, 0x00, 0x5a00);
3112 rtl_writephy(tp, 0x1f, 0x0000);
3113 rtl_writephy(tp, 0x0d, 0x0007);
3114 rtl_writephy(tp, 0x0e, 0x003c);
3115 rtl_writephy(tp, 0x0d, 0x4007);
3116 rtl_writephy(tp, 0x0e, 0x0000);
3117 rtl_writephy(tp, 0x0d, 0x0000);
3120 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3123 addr[0] | (addr[1] << 8),
3124 addr[2] | (addr[3] << 8),
3125 addr[4] | (addr[5] << 8)
3127 const struct exgmac_reg e[] = {
3128 { .addr = 0xe0, ERIAR_MASK_1111, .val = w[0] | (w[1] << 16) },
3129 { .addr = 0xe4, ERIAR_MASK_1111, .val = w[2] },
3130 { .addr = 0xf0, ERIAR_MASK_1111, .val = w[0] << 16 },
3131 { .addr = 0xf4, ERIAR_MASK_1111, .val = w[1] | (w[2] << 16) }
3134 rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e));
3137 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3139 static const struct phy_reg phy_reg_init[] = {
3140 /* Enable Delay cap */
3149 /* Channel estimation fine tune */
3166 rtl_apply_firmware(tp);
3168 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3170 /* For 4-corner performance improve */
3171 rtl_writephy(tp, 0x1f, 0x0005);
3172 rtl_writephy(tp, 0x05, 0x8b80);
3173 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
3174 rtl_writephy(tp, 0x1f, 0x0000);
3176 /* PHY auto speed down */
3177 rtl_writephy(tp, 0x1f, 0x0004);
3178 rtl_writephy(tp, 0x1f, 0x0007);
3179 rtl_writephy(tp, 0x1e, 0x002d);
3180 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3181 rtl_writephy(tp, 0x1f, 0x0002);
3182 rtl_writephy(tp, 0x1f, 0x0000);
3183 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3185 /* improve 10M EEE waveform */
3186 rtl_writephy(tp, 0x1f, 0x0005);
3187 rtl_writephy(tp, 0x05, 0x8b86);
3188 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3189 rtl_writephy(tp, 0x1f, 0x0000);
3191 /* Improve 2-pair detection performance */
3192 rtl_writephy(tp, 0x1f, 0x0005);
3193 rtl_writephy(tp, 0x05, 0x8b85);
3194 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3195 rtl_writephy(tp, 0x1f, 0x0000);
3198 rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003, ERIAR_EXGMAC);
3199 rtl_writephy(tp, 0x1f, 0x0005);
3200 rtl_writephy(tp, 0x05, 0x8b85);
3201 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3202 rtl_writephy(tp, 0x1f, 0x0004);
3203 rtl_writephy(tp, 0x1f, 0x0007);
3204 rtl_writephy(tp, 0x1e, 0x0020);
3205 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
3206 rtl_writephy(tp, 0x1f, 0x0002);
3207 rtl_writephy(tp, 0x1f, 0x0000);
3208 rtl_writephy(tp, 0x0d, 0x0007);
3209 rtl_writephy(tp, 0x0e, 0x003c);
3210 rtl_writephy(tp, 0x0d, 0x4007);
3211 rtl_writephy(tp, 0x0e, 0x0000);
3212 rtl_writephy(tp, 0x0d, 0x0000);
3215 rtl_writephy(tp, 0x1f, 0x0003);
3216 rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
3217 rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
3218 rtl_writephy(tp, 0x1f, 0x0000);
3220 /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3221 rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
3224 static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3226 /* For 4-corner performance improve */
3227 rtl_writephy(tp, 0x1f, 0x0005);
3228 rtl_writephy(tp, 0x05, 0x8b80);
3229 rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000);
3230 rtl_writephy(tp, 0x1f, 0x0000);
3232 /* PHY auto speed down */
3233 rtl_writephy(tp, 0x1f, 0x0007);
3234 rtl_writephy(tp, 0x1e, 0x002d);
3235 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3236 rtl_writephy(tp, 0x1f, 0x0000);
3237 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3239 /* Improve 10M EEE waveform */
3240 rtl_writephy(tp, 0x1f, 0x0005);
3241 rtl_writephy(tp, 0x05, 0x8b86);
3242 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3243 rtl_writephy(tp, 0x1f, 0x0000);
3246 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3248 static const struct phy_reg phy_reg_init[] = {
3249 /* Channel estimation fine tune */
3254 /* Modify green table for giga & fnet */
3271 /* Modify green table for 10M */
3277 /* Disable hiimpedance detection (RTCT) */
3283 rtl_apply_firmware(tp);
3285 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3287 rtl8168f_hw_phy_config(tp);
3289 /* Improve 2-pair detection performance */
3290 rtl_writephy(tp, 0x1f, 0x0005);
3291 rtl_writephy(tp, 0x05, 0x8b85);
3292 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3293 rtl_writephy(tp, 0x1f, 0x0000);
3296 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3298 rtl_apply_firmware(tp);
3300 rtl8168f_hw_phy_config(tp);
3303 static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3305 static const struct phy_reg phy_reg_init[] = {
3306 /* Channel estimation fine tune */
3311 /* Modify green table for giga & fnet */
3328 /* Modify green table for 10M */
3334 /* Disable hiimpedance detection (RTCT) */
3341 rtl_apply_firmware(tp);
3343 rtl8168f_hw_phy_config(tp);
3345 /* Improve 2-pair detection performance */
3346 rtl_writephy(tp, 0x1f, 0x0005);
3347 rtl_writephy(tp, 0x05, 0x8b85);
3348 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3349 rtl_writephy(tp, 0x1f, 0x0000);
3351 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3353 /* Modify green table for giga */
3354 rtl_writephy(tp, 0x1f, 0x0005);
3355 rtl_writephy(tp, 0x05, 0x8b54);
3356 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0800);
3357 rtl_writephy(tp, 0x05, 0x8b5d);
3358 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0800);
3359 rtl_writephy(tp, 0x05, 0x8a7c);
3360 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3361 rtl_writephy(tp, 0x05, 0x8a7f);
3362 rtl_w1w0_phy(tp, 0x06, 0x0100, 0x0000);
3363 rtl_writephy(tp, 0x05, 0x8a82);
3364 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3365 rtl_writephy(tp, 0x05, 0x8a85);
3366 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3367 rtl_writephy(tp, 0x05, 0x8a88);
3368 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3369 rtl_writephy(tp, 0x1f, 0x0000);
3371 /* uc same-seed solution */
3372 rtl_writephy(tp, 0x1f, 0x0005);
3373 rtl_writephy(tp, 0x05, 0x8b85);
3374 rtl_w1w0_phy(tp, 0x06, 0x8000, 0x0000);
3375 rtl_writephy(tp, 0x1f, 0x0000);
3378 rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC);
3379 rtl_writephy(tp, 0x1f, 0x0005);
3380 rtl_writephy(tp, 0x05, 0x8b85);
3381 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3382 rtl_writephy(tp, 0x1f, 0x0004);
3383 rtl_writephy(tp, 0x1f, 0x0007);
3384 rtl_writephy(tp, 0x1e, 0x0020);
3385 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
3386 rtl_writephy(tp, 0x1f, 0x0000);
3387 rtl_writephy(tp, 0x0d, 0x0007);
3388 rtl_writephy(tp, 0x0e, 0x003c);
3389 rtl_writephy(tp, 0x0d, 0x4007);
3390 rtl_writephy(tp, 0x0e, 0x0000);
3391 rtl_writephy(tp, 0x0d, 0x0000);
3394 rtl_writephy(tp, 0x1f, 0x0003);
3395 rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
3396 rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
3397 rtl_writephy(tp, 0x1f, 0x0000);
3400 static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3402 rtl_apply_firmware(tp);
3404 rtl_writephy(tp, 0x1f, 0x0a46);
3405 if (rtl_readphy(tp, 0x10) & 0x0100) {
3406 rtl_writephy(tp, 0x1f, 0x0bcc);
3407 rtl_w1w0_phy(tp, 0x12, 0x0000, 0x8000);
3409 rtl_writephy(tp, 0x1f, 0x0bcc);
3410 rtl_w1w0_phy(tp, 0x12, 0x8000, 0x0000);
3413 rtl_writephy(tp, 0x1f, 0x0a46);
3414 if (rtl_readphy(tp, 0x13) & 0x0100) {
3415 rtl_writephy(tp, 0x1f, 0x0c41);
3416 rtl_w1w0_phy(tp, 0x15, 0x0002, 0x0000);
3418 rtl_writephy(tp, 0x1f, 0x0c41);
3419 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0002);
3422 /* Enable PHY auto speed down */
3423 rtl_writephy(tp, 0x1f, 0x0a44);
3424 rtl_w1w0_phy(tp, 0x11, 0x000c, 0x0000);
3426 rtl_writephy(tp, 0x1f, 0x0bcc);
3427 rtl_w1w0_phy(tp, 0x14, 0x0100, 0x0000);
3428 rtl_writephy(tp, 0x1f, 0x0a44);
3429 rtl_w1w0_phy(tp, 0x11, 0x00c0, 0x0000);
3430 rtl_writephy(tp, 0x1f, 0x0a43);
3431 rtl_writephy(tp, 0x13, 0x8084);
3432 rtl_w1w0_phy(tp, 0x14, 0x0000, 0x6000);
3433 rtl_w1w0_phy(tp, 0x10, 0x1003, 0x0000);
3435 /* EEE auto-fallback function */
3436 rtl_writephy(tp, 0x1f, 0x0a4b);
3437 rtl_w1w0_phy(tp, 0x11, 0x0004, 0x0000);
3439 /* Enable UC LPF tune function */
3440 rtl_writephy(tp, 0x1f, 0x0a43);
3441 rtl_writephy(tp, 0x13, 0x8012);
3442 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3444 rtl_writephy(tp, 0x1f, 0x0c42);
3445 rtl_w1w0_phy(tp, 0x11, 0x4000, 0x2000);
3447 /* Improve SWR Efficiency */
3448 rtl_writephy(tp, 0x1f, 0x0bcd);
3449 rtl_writephy(tp, 0x14, 0x5065);
3450 rtl_writephy(tp, 0x14, 0xd065);
3451 rtl_writephy(tp, 0x1f, 0x0bc8);
3452 rtl_writephy(tp, 0x11, 0x5655);
3453 rtl_writephy(tp, 0x1f, 0x0bcd);
3454 rtl_writephy(tp, 0x14, 0x1065);
3455 rtl_writephy(tp, 0x14, 0x9065);
3456 rtl_writephy(tp, 0x14, 0x1065);
3458 rtl_writephy(tp, 0x1f, 0x0000);
3461 static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
3463 rtl_apply_firmware(tp);
3466 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
3468 static const struct phy_reg phy_reg_init[] = {
3475 rtl_writephy(tp, 0x1f, 0x0000);
3476 rtl_patchphy(tp, 0x11, 1 << 12);
3477 rtl_patchphy(tp, 0x19, 1 << 13);
3478 rtl_patchphy(tp, 0x10, 1 << 15);
3480 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3483 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3485 static const struct phy_reg phy_reg_init[] = {
3499 /* Disable ALDPS before ram code */
3500 rtl_writephy(tp, 0x1f, 0x0000);
3501 rtl_writephy(tp, 0x18, 0x0310);
3504 rtl_apply_firmware(tp);
3506 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3509 static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
3511 /* Disable ALDPS before setting firmware */
3512 rtl_writephy(tp, 0x1f, 0x0000);
3513 rtl_writephy(tp, 0x18, 0x0310);
3516 rtl_apply_firmware(tp);
3519 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3520 rtl_writephy(tp, 0x1f, 0x0004);
3521 rtl_writephy(tp, 0x10, 0x401f);
3522 rtl_writephy(tp, 0x19, 0x7030);
3523 rtl_writephy(tp, 0x1f, 0x0000);
3526 static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
3528 static const struct phy_reg phy_reg_init[] = {
3535 /* Disable ALDPS before ram code */
3536 rtl_writephy(tp, 0x1f, 0x0000);
3537 rtl_writephy(tp, 0x18, 0x0310);
3540 rtl_apply_firmware(tp);
3542 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3543 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3545 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3548 static void rtl_hw_phy_config(struct net_device *dev)
3550 struct rtl8169_private *tp = netdev_priv(dev);
3552 rtl8169_print_mac_version(tp);
3554 switch (tp->mac_version) {
3555 case RTL_GIGA_MAC_VER_01:
3557 case RTL_GIGA_MAC_VER_02:
3558 case RTL_GIGA_MAC_VER_03:
3559 rtl8169s_hw_phy_config(tp);
3561 case RTL_GIGA_MAC_VER_04:
3562 rtl8169sb_hw_phy_config(tp);
3564 case RTL_GIGA_MAC_VER_05:
3565 rtl8169scd_hw_phy_config(tp);
3567 case RTL_GIGA_MAC_VER_06:
3568 rtl8169sce_hw_phy_config(tp);
3570 case RTL_GIGA_MAC_VER_07:
3571 case RTL_GIGA_MAC_VER_08:
3572 case RTL_GIGA_MAC_VER_09:
3573 rtl8102e_hw_phy_config(tp);
3575 case RTL_GIGA_MAC_VER_11:
3576 rtl8168bb_hw_phy_config(tp);
3578 case RTL_GIGA_MAC_VER_12:
3579 rtl8168bef_hw_phy_config(tp);
3581 case RTL_GIGA_MAC_VER_17:
3582 rtl8168bef_hw_phy_config(tp);
3584 case RTL_GIGA_MAC_VER_18:
3585 rtl8168cp_1_hw_phy_config(tp);
3587 case RTL_GIGA_MAC_VER_19:
3588 rtl8168c_1_hw_phy_config(tp);
3590 case RTL_GIGA_MAC_VER_20:
3591 rtl8168c_2_hw_phy_config(tp);
3593 case RTL_GIGA_MAC_VER_21:
3594 rtl8168c_3_hw_phy_config(tp);
3596 case RTL_GIGA_MAC_VER_22:
3597 rtl8168c_4_hw_phy_config(tp);
3599 case RTL_GIGA_MAC_VER_23:
3600 case RTL_GIGA_MAC_VER_24:
3601 rtl8168cp_2_hw_phy_config(tp);
3603 case RTL_GIGA_MAC_VER_25:
3604 rtl8168d_1_hw_phy_config(tp);
3606 case RTL_GIGA_MAC_VER_26:
3607 rtl8168d_2_hw_phy_config(tp);
3609 case RTL_GIGA_MAC_VER_27:
3610 rtl8168d_3_hw_phy_config(tp);
3612 case RTL_GIGA_MAC_VER_28:
3613 rtl8168d_4_hw_phy_config(tp);
3615 case RTL_GIGA_MAC_VER_29:
3616 case RTL_GIGA_MAC_VER_30:
3617 rtl8105e_hw_phy_config(tp);
3619 case RTL_GIGA_MAC_VER_31:
3622 case RTL_GIGA_MAC_VER_32:
3623 case RTL_GIGA_MAC_VER_33:
3624 rtl8168e_1_hw_phy_config(tp);
3626 case RTL_GIGA_MAC_VER_34:
3627 rtl8168e_2_hw_phy_config(tp);
3629 case RTL_GIGA_MAC_VER_35:
3630 rtl8168f_1_hw_phy_config(tp);
3632 case RTL_GIGA_MAC_VER_36:
3633 rtl8168f_2_hw_phy_config(tp);
3636 case RTL_GIGA_MAC_VER_37:
3637 rtl8402_hw_phy_config(tp);
3640 case RTL_GIGA_MAC_VER_38:
3641 rtl8411_hw_phy_config(tp);
3644 case RTL_GIGA_MAC_VER_39:
3645 rtl8106e_hw_phy_config(tp);
3648 case RTL_GIGA_MAC_VER_40:
3649 rtl8168g_1_hw_phy_config(tp);
3651 case RTL_GIGA_MAC_VER_42:
3652 case RTL_GIGA_MAC_VER_43:
3653 rtl8168g_2_hw_phy_config(tp);
3656 case RTL_GIGA_MAC_VER_41:
3662 static void rtl_phy_work(struct rtl8169_private *tp)
3664 struct timer_list *timer = &tp->timer;
3665 void __iomem *ioaddr = tp->mmio_addr;
3666 unsigned long timeout = RTL8169_PHY_TIMEOUT;
3668 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
3670 if (tp->phy_reset_pending(tp)) {
3672 * A busy loop could burn quite a few cycles on nowadays CPU.
3673 * Let's delay the execution of the timer for a few ticks.
3679 if (tp->link_ok(ioaddr))
3682 netif_warn(tp, link, tp->dev, "PHY reset until link up\n");
3684 tp->phy_reset_enable(tp);
3687 mod_timer(timer, jiffies + timeout);
3690 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
3692 if (!test_and_set_bit(flag, tp->wk.flags))
3693 schedule_work(&tp->wk.work);
3696 static void rtl8169_phy_timer(unsigned long __opaque)
3698 struct net_device *dev = (struct net_device *)__opaque;
3699 struct rtl8169_private *tp = netdev_priv(dev);
3701 rtl_schedule_task(tp, RTL_FLAG_TASK_PHY_PENDING);
3704 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
3705 void __iomem *ioaddr)
3708 pci_release_regions(pdev);
3709 pci_clear_mwi(pdev);
3710 pci_disable_device(pdev);
3714 DECLARE_RTL_COND(rtl_phy_reset_cond)
3716 return tp->phy_reset_pending(tp);
3719 static void rtl8169_phy_reset(struct net_device *dev,
3720 struct rtl8169_private *tp)
3722 tp->phy_reset_enable(tp);
3723 rtl_msleep_loop_wait_low(tp, &rtl_phy_reset_cond, 1, 100);
3726 static bool rtl_tbi_enabled(struct rtl8169_private *tp)
3728 void __iomem *ioaddr = tp->mmio_addr;
3730 return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
3731 (RTL_R8(PHYstatus) & TBI_Enable);
3734 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
3736 void __iomem *ioaddr = tp->mmio_addr;
3738 rtl_hw_phy_config(dev);
3740 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
3741 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3745 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
3747 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3748 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
3750 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
3751 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3753 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
3754 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
3757 rtl8169_phy_reset(dev, tp);
3759 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
3760 ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3761 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
3762 (tp->mii.supports_gmii ?
3763 ADVERTISED_1000baseT_Half |
3764 ADVERTISED_1000baseT_Full : 0));
3766 if (rtl_tbi_enabled(tp))
3767 netif_info(tp, link, dev, "TBI auto-negotiating\n");
3770 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
3772 void __iomem *ioaddr = tp->mmio_addr;
3776 RTL_W8(Cfg9346, Cfg9346_Unlock);
3778 RTL_W32(MAC4, addr[4] | addr[5] << 8);
3781 RTL_W32(MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
3784 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
3785 rtl_rar_exgmac_set(tp, addr);
3787 RTL_W8(Cfg9346, Cfg9346_Lock);
3789 rtl_unlock_work(tp);
3792 static int rtl_set_mac_address(struct net_device *dev, void *p)
3794 struct rtl8169_private *tp = netdev_priv(dev);
3795 struct sockaddr *addr = p;
3797 if (!is_valid_ether_addr(addr->sa_data))
3798 return -EADDRNOTAVAIL;
3800 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3802 rtl_rar_set(tp, dev->dev_addr);
3807 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3809 struct rtl8169_private *tp = netdev_priv(dev);
3810 struct mii_ioctl_data *data = if_mii(ifr);
3812 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
3815 static int rtl_xmii_ioctl(struct rtl8169_private *tp,
3816 struct mii_ioctl_data *data, int cmd)
3820 data->phy_id = 32; /* Internal PHY */
3824 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
3828 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
3834 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
3839 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
3841 if (tp->features & RTL_FEATURE_MSI) {
3842 pci_disable_msi(pdev);
3843 tp->features &= ~RTL_FEATURE_MSI;
3847 static void rtl_init_mdio_ops(struct rtl8169_private *tp)
3849 struct mdio_ops *ops = &tp->mdio_ops;
3851 switch (tp->mac_version) {
3852 case RTL_GIGA_MAC_VER_27:
3853 ops->write = r8168dp_1_mdio_write;
3854 ops->read = r8168dp_1_mdio_read;
3856 case RTL_GIGA_MAC_VER_28:
3857 case RTL_GIGA_MAC_VER_31:
3858 ops->write = r8168dp_2_mdio_write;
3859 ops->read = r8168dp_2_mdio_read;
3861 case RTL_GIGA_MAC_VER_40:
3862 case RTL_GIGA_MAC_VER_41:
3863 case RTL_GIGA_MAC_VER_42:
3864 case RTL_GIGA_MAC_VER_43:
3865 ops->write = r8168g_mdio_write;
3866 ops->read = r8168g_mdio_read;
3869 ops->write = r8169_mdio_write;
3870 ops->read = r8169_mdio_read;
3875 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
3877 void __iomem *ioaddr = tp->mmio_addr;
3879 switch (tp->mac_version) {
3880 case RTL_GIGA_MAC_VER_25:
3881 case RTL_GIGA_MAC_VER_26:
3882 case RTL_GIGA_MAC_VER_29:
3883 case RTL_GIGA_MAC_VER_30:
3884 case RTL_GIGA_MAC_VER_32:
3885 case RTL_GIGA_MAC_VER_33:
3886 case RTL_GIGA_MAC_VER_34:
3887 case RTL_GIGA_MAC_VER_37:
3888 case RTL_GIGA_MAC_VER_38:
3889 case RTL_GIGA_MAC_VER_39:
3890 case RTL_GIGA_MAC_VER_40:
3891 case RTL_GIGA_MAC_VER_41:
3892 case RTL_GIGA_MAC_VER_42:
3893 case RTL_GIGA_MAC_VER_43:
3894 RTL_W32(RxConfig, RTL_R32(RxConfig) |
3895 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
3902 static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
3904 if (!(__rtl8169_get_wol(tp) & WAKE_ANY))
3907 rtl_writephy(tp, 0x1f, 0x0000);
3908 rtl_writephy(tp, MII_BMCR, 0x0000);
3910 rtl_wol_suspend_quirk(tp);
3915 static void r810x_phy_power_down(struct rtl8169_private *tp)
3917 rtl_writephy(tp, 0x1f, 0x0000);
3918 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3921 static void r810x_phy_power_up(struct rtl8169_private *tp)
3923 rtl_writephy(tp, 0x1f, 0x0000);
3924 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3927 static void r810x_pll_power_down(struct rtl8169_private *tp)
3929 void __iomem *ioaddr = tp->mmio_addr;
3931 if (rtl_wol_pll_power_down(tp))
3934 r810x_phy_power_down(tp);
3936 switch (tp->mac_version) {
3937 case RTL_GIGA_MAC_VER_07:
3938 case RTL_GIGA_MAC_VER_08:
3939 case RTL_GIGA_MAC_VER_09:
3940 case RTL_GIGA_MAC_VER_10:
3941 case RTL_GIGA_MAC_VER_13:
3942 case RTL_GIGA_MAC_VER_16:
3945 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
3950 static void r810x_pll_power_up(struct rtl8169_private *tp)
3952 void __iomem *ioaddr = tp->mmio_addr;
3954 r810x_phy_power_up(tp);
3956 switch (tp->mac_version) {
3957 case RTL_GIGA_MAC_VER_07:
3958 case RTL_GIGA_MAC_VER_08:
3959 case RTL_GIGA_MAC_VER_09:
3960 case RTL_GIGA_MAC_VER_10:
3961 case RTL_GIGA_MAC_VER_13:
3962 case RTL_GIGA_MAC_VER_16:
3965 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
3970 static void r8168_phy_power_up(struct rtl8169_private *tp)
3972 rtl_writephy(tp, 0x1f, 0x0000);
3973 switch (tp->mac_version) {
3974 case RTL_GIGA_MAC_VER_11:
3975 case RTL_GIGA_MAC_VER_12:
3976 case RTL_GIGA_MAC_VER_17:
3977 case RTL_GIGA_MAC_VER_18:
3978 case RTL_GIGA_MAC_VER_19:
3979 case RTL_GIGA_MAC_VER_20:
3980 case RTL_GIGA_MAC_VER_21:
3981 case RTL_GIGA_MAC_VER_22:
3982 case RTL_GIGA_MAC_VER_23:
3983 case RTL_GIGA_MAC_VER_24:
3984 case RTL_GIGA_MAC_VER_25:
3985 case RTL_GIGA_MAC_VER_26:
3986 case RTL_GIGA_MAC_VER_27:
3987 case RTL_GIGA_MAC_VER_28:
3988 case RTL_GIGA_MAC_VER_31:
3989 rtl_writephy(tp, 0x0e, 0x0000);
3994 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3997 static void r8168_phy_power_down(struct rtl8169_private *tp)
3999 rtl_writephy(tp, 0x1f, 0x0000);
4000 switch (tp->mac_version) {
4001 case RTL_GIGA_MAC_VER_32:
4002 case RTL_GIGA_MAC_VER_33:
4003 case RTL_GIGA_MAC_VER_40:
4004 case RTL_GIGA_MAC_VER_41:
4005 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
4008 case RTL_GIGA_MAC_VER_11:
4009 case RTL_GIGA_MAC_VER_12:
4010 case RTL_GIGA_MAC_VER_17:
4011 case RTL_GIGA_MAC_VER_18:
4012 case RTL_GIGA_MAC_VER_19:
4013 case RTL_GIGA_MAC_VER_20:
4014 case RTL_GIGA_MAC_VER_21:
4015 case RTL_GIGA_MAC_VER_22:
4016 case RTL_GIGA_MAC_VER_23:
4017 case RTL_GIGA_MAC_VER_24:
4018 case RTL_GIGA_MAC_VER_25:
4019 case RTL_GIGA_MAC_VER_26:
4020 case RTL_GIGA_MAC_VER_27:
4021 case RTL_GIGA_MAC_VER_28:
4022 case RTL_GIGA_MAC_VER_31:
4023 rtl_writephy(tp, 0x0e, 0x0200);
4025 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
4030 static void r8168_pll_power_down(struct rtl8169_private *tp)
4032 void __iomem *ioaddr = tp->mmio_addr;
4034 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4035 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4036 tp->mac_version == RTL_GIGA_MAC_VER_31) &&
4037 r8168dp_check_dash(tp)) {
4041 if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
4042 tp->mac_version == RTL_GIGA_MAC_VER_24) &&
4043 (RTL_R16(CPlusCmd) & ASF)) {
4047 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
4048 tp->mac_version == RTL_GIGA_MAC_VER_33)
4049 rtl_ephy_write(tp, 0x19, 0xff64);
4051 if (rtl_wol_pll_power_down(tp))
4054 r8168_phy_power_down(tp);
4056 switch (tp->mac_version) {
4057 case RTL_GIGA_MAC_VER_25:
4058 case RTL_GIGA_MAC_VER_26:
4059 case RTL_GIGA_MAC_VER_27:
4060 case RTL_GIGA_MAC_VER_28:
4061 case RTL_GIGA_MAC_VER_31:
4062 case RTL_GIGA_MAC_VER_32:
4063 case RTL_GIGA_MAC_VER_33:
4064 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
4066 case RTL_GIGA_MAC_VER_40:
4067 case RTL_GIGA_MAC_VER_41:
4068 rtl_w1w0_eri(tp, 0x1a8, ERIAR_MASK_1111, 0x00000000,
4069 0xfc000000, ERIAR_EXGMAC);
4074 static void r8168_pll_power_up(struct rtl8169_private *tp)
4076 void __iomem *ioaddr = tp->mmio_addr;
4078 switch (tp->mac_version) {
4079 case RTL_GIGA_MAC_VER_25:
4080 case RTL_GIGA_MAC_VER_26:
4081 case RTL_GIGA_MAC_VER_27:
4082 case RTL_GIGA_MAC_VER_28:
4083 case RTL_GIGA_MAC_VER_31:
4084 case RTL_GIGA_MAC_VER_32:
4085 case RTL_GIGA_MAC_VER_33:
4086 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
4088 case RTL_GIGA_MAC_VER_40:
4089 case RTL_GIGA_MAC_VER_41:
4090 rtl_w1w0_eri(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000,
4091 0x00000000, ERIAR_EXGMAC);
4095 r8168_phy_power_up(tp);
4098 static void rtl_generic_op(struct rtl8169_private *tp,
4099 void (*op)(struct rtl8169_private *))
4105 static void rtl_pll_power_down(struct rtl8169_private *tp)
4107 rtl_generic_op(tp, tp->pll_power_ops.down);
4110 static void rtl_pll_power_up(struct rtl8169_private *tp)
4112 rtl_generic_op(tp, tp->pll_power_ops.up);
4115 static void rtl_init_pll_power_ops(struct rtl8169_private *tp)
4117 struct pll_power_ops *ops = &tp->pll_power_ops;
4119 switch (tp->mac_version) {
4120 case RTL_GIGA_MAC_VER_07:
4121 case RTL_GIGA_MAC_VER_08:
4122 case RTL_GIGA_MAC_VER_09:
4123 case RTL_GIGA_MAC_VER_10:
4124 case RTL_GIGA_MAC_VER_16:
4125 case RTL_GIGA_MAC_VER_29:
4126 case RTL_GIGA_MAC_VER_30:
4127 case RTL_GIGA_MAC_VER_37:
4128 case RTL_GIGA_MAC_VER_39:
4129 case RTL_GIGA_MAC_VER_43:
4130 ops->down = r810x_pll_power_down;
4131 ops->up = r810x_pll_power_up;
4134 case RTL_GIGA_MAC_VER_11:
4135 case RTL_GIGA_MAC_VER_12:
4136 case RTL_GIGA_MAC_VER_17:
4137 case RTL_GIGA_MAC_VER_18:
4138 case RTL_GIGA_MAC_VER_19:
4139 case RTL_GIGA_MAC_VER_20:
4140 case RTL_GIGA_MAC_VER_21:
4141 case RTL_GIGA_MAC_VER_22:
4142 case RTL_GIGA_MAC_VER_23:
4143 case RTL_GIGA_MAC_VER_24:
4144 case RTL_GIGA_MAC_VER_25:
4145 case RTL_GIGA_MAC_VER_26:
4146 case RTL_GIGA_MAC_VER_27:
4147 case RTL_GIGA_MAC_VER_28:
4148 case RTL_GIGA_MAC_VER_31:
4149 case RTL_GIGA_MAC_VER_32:
4150 case RTL_GIGA_MAC_VER_33:
4151 case RTL_GIGA_MAC_VER_34:
4152 case RTL_GIGA_MAC_VER_35:
4153 case RTL_GIGA_MAC_VER_36:
4154 case RTL_GIGA_MAC_VER_38:
4155 case RTL_GIGA_MAC_VER_40:
4156 case RTL_GIGA_MAC_VER_41:
4157 case RTL_GIGA_MAC_VER_42:
4158 ops->down = r8168_pll_power_down;
4159 ops->up = r8168_pll_power_up;
4169 static void rtl_init_rxcfg(struct rtl8169_private *tp)
4171 void __iomem *ioaddr = tp->mmio_addr;
4173 switch (tp->mac_version) {
4174 case RTL_GIGA_MAC_VER_01:
4175 case RTL_GIGA_MAC_VER_02:
4176 case RTL_GIGA_MAC_VER_03:
4177 case RTL_GIGA_MAC_VER_04:
4178 case RTL_GIGA_MAC_VER_05:
4179 case RTL_GIGA_MAC_VER_06:
4180 case RTL_GIGA_MAC_VER_10:
4181 case RTL_GIGA_MAC_VER_11:
4182 case RTL_GIGA_MAC_VER_12:
4183 case RTL_GIGA_MAC_VER_13:
4184 case RTL_GIGA_MAC_VER_14:
4185 case RTL_GIGA_MAC_VER_15:
4186 case RTL_GIGA_MAC_VER_16:
4187 case RTL_GIGA_MAC_VER_17:
4188 RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
4190 case RTL_GIGA_MAC_VER_18:
4191 case RTL_GIGA_MAC_VER_19:
4192 case RTL_GIGA_MAC_VER_20:
4193 case RTL_GIGA_MAC_VER_21:
4194 case RTL_GIGA_MAC_VER_22:
4195 case RTL_GIGA_MAC_VER_23:
4196 case RTL_GIGA_MAC_VER_24:
4197 case RTL_GIGA_MAC_VER_34:
4198 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
4200 case RTL_GIGA_MAC_VER_40:
4201 case RTL_GIGA_MAC_VER_41:
4202 case RTL_GIGA_MAC_VER_42:
4203 case RTL_GIGA_MAC_VER_43:
4204 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST | RX_EARLY_OFF);
4207 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
4212 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4214 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
4217 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
4219 void __iomem *ioaddr = tp->mmio_addr;
4221 RTL_W8(Cfg9346, Cfg9346_Unlock);
4222 rtl_generic_op(tp, tp->jumbo_ops.enable);
4223 RTL_W8(Cfg9346, Cfg9346_Lock);
4226 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
4228 void __iomem *ioaddr = tp->mmio_addr;
4230 RTL_W8(Cfg9346, Cfg9346_Unlock);
4231 rtl_generic_op(tp, tp->jumbo_ops.disable);
4232 RTL_W8(Cfg9346, Cfg9346_Lock);
4235 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
4237 void __iomem *ioaddr = tp->mmio_addr;
4239 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4240 RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
4241 rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
4244 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
4246 void __iomem *ioaddr = tp->mmio_addr;
4248 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4249 RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
4250 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
4253 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
4255 void __iomem *ioaddr = tp->mmio_addr;
4257 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4260 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
4262 void __iomem *ioaddr = tp->mmio_addr;
4264 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4267 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
4269 void __iomem *ioaddr = tp->mmio_addr;
4271 RTL_W8(MaxTxPacketSize, 0x3f);
4272 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4273 RTL_W8(Config4, RTL_R8(Config4) | 0x01);
4274 rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
4277 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
4279 void __iomem *ioaddr = tp->mmio_addr;
4281 RTL_W8(MaxTxPacketSize, 0x0c);
4282 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4283 RTL_W8(Config4, RTL_R8(Config4) & ~0x01);
4284 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
4287 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
4289 rtl_tx_performance_tweak(tp->pci_dev,
4290 (0x2 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4293 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
4295 rtl_tx_performance_tweak(tp->pci_dev,
4296 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4299 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
4301 void __iomem *ioaddr = tp->mmio_addr;
4303 r8168b_0_hw_jumbo_enable(tp);
4305 RTL_W8(Config4, RTL_R8(Config4) | (1 << 0));
4308 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
4310 void __iomem *ioaddr = tp->mmio_addr;
4312 r8168b_0_hw_jumbo_disable(tp);
4314 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
4317 static void rtl_init_jumbo_ops(struct rtl8169_private *tp)
4319 struct jumbo_ops *ops = &tp->jumbo_ops;
4321 switch (tp->mac_version) {
4322 case RTL_GIGA_MAC_VER_11:
4323 ops->disable = r8168b_0_hw_jumbo_disable;
4324 ops->enable = r8168b_0_hw_jumbo_enable;
4326 case RTL_GIGA_MAC_VER_12:
4327 case RTL_GIGA_MAC_VER_17:
4328 ops->disable = r8168b_1_hw_jumbo_disable;
4329 ops->enable = r8168b_1_hw_jumbo_enable;
4331 case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
4332 case RTL_GIGA_MAC_VER_19:
4333 case RTL_GIGA_MAC_VER_20:
4334 case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
4335 case RTL_GIGA_MAC_VER_22:
4336 case RTL_GIGA_MAC_VER_23:
4337 case RTL_GIGA_MAC_VER_24:
4338 case RTL_GIGA_MAC_VER_25:
4339 case RTL_GIGA_MAC_VER_26:
4340 ops->disable = r8168c_hw_jumbo_disable;
4341 ops->enable = r8168c_hw_jumbo_enable;
4343 case RTL_GIGA_MAC_VER_27:
4344 case RTL_GIGA_MAC_VER_28:
4345 ops->disable = r8168dp_hw_jumbo_disable;
4346 ops->enable = r8168dp_hw_jumbo_enable;
4348 case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
4349 case RTL_GIGA_MAC_VER_32:
4350 case RTL_GIGA_MAC_VER_33:
4351 case RTL_GIGA_MAC_VER_34:
4352 ops->disable = r8168e_hw_jumbo_disable;
4353 ops->enable = r8168e_hw_jumbo_enable;
4357 * No action needed for jumbo frames with 8169.
4358 * No jumbo for 810x at all.
4360 case RTL_GIGA_MAC_VER_40:
4361 case RTL_GIGA_MAC_VER_41:
4362 case RTL_GIGA_MAC_VER_42:
4363 case RTL_GIGA_MAC_VER_43:
4365 ops->disable = NULL;
4371 DECLARE_RTL_COND(rtl_chipcmd_cond)
4373 void __iomem *ioaddr = tp->mmio_addr;
4375 return RTL_R8(ChipCmd) & CmdReset;
4378 static void rtl_hw_reset(struct rtl8169_private *tp)
4380 void __iomem *ioaddr = tp->mmio_addr;
4382 RTL_W8(ChipCmd, CmdReset);
4384 rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
4387 static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
4389 struct rtl_fw *rtl_fw;
4393 name = rtl_lookup_firmware_name(tp);
4395 goto out_no_firmware;
4397 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
4401 rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
4405 rc = rtl_check_firmware(tp, rtl_fw);
4407 goto err_release_firmware;
4409 tp->rtl_fw = rtl_fw;
4413 err_release_firmware:
4414 release_firmware(rtl_fw->fw);
4418 netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
4425 static void rtl_request_firmware(struct rtl8169_private *tp)
4427 if (IS_ERR(tp->rtl_fw))
4428 rtl_request_uncached_firmware(tp);
4431 static void rtl_rx_close(struct rtl8169_private *tp)
4433 void __iomem *ioaddr = tp->mmio_addr;
4435 RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
4438 DECLARE_RTL_COND(rtl_npq_cond)
4440 void __iomem *ioaddr = tp->mmio_addr;
4442 return RTL_R8(TxPoll) & NPQ;
4445 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
4447 void __iomem *ioaddr = tp->mmio_addr;
4449 return RTL_R32(TxConfig) & TXCFG_EMPTY;
4452 static void rtl8169_hw_reset(struct rtl8169_private *tp)
4454 void __iomem *ioaddr = tp->mmio_addr;
4456 /* Disable interrupts */
4457 rtl8169_irq_mask_and_ack(tp);
4461 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4462 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4463 tp->mac_version == RTL_GIGA_MAC_VER_31) {
4464 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
4465 } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
4466 tp->mac_version == RTL_GIGA_MAC_VER_35 ||
4467 tp->mac_version == RTL_GIGA_MAC_VER_36 ||
4468 tp->mac_version == RTL_GIGA_MAC_VER_37 ||
4469 tp->mac_version == RTL_GIGA_MAC_VER_40 ||
4470 tp->mac_version == RTL_GIGA_MAC_VER_41 ||
4471 tp->mac_version == RTL_GIGA_MAC_VER_42 ||
4472 tp->mac_version == RTL_GIGA_MAC_VER_43 ||
4473 tp->mac_version == RTL_GIGA_MAC_VER_38) {
4474 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
4475 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
4477 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
4484 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
4486 void __iomem *ioaddr = tp->mmio_addr;
4488 /* Set DMA burst size and Interframe Gap Time */
4489 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4490 (InterFrameGap << TxInterFrameGapShift));
4493 static void rtl_hw_start(struct net_device *dev)
4495 struct rtl8169_private *tp = netdev_priv(dev);
4499 rtl_irq_enable_all(tp);
4502 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
4503 void __iomem *ioaddr)
4506 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4507 * register to be written before TxDescAddrLow to work.
4508 * Switching from MMIO to I/O access fixes the issue as well.
4510 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4511 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4512 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4513 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
4516 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
4520 cmd = RTL_R16(CPlusCmd);
4521 RTL_W16(CPlusCmd, cmd);
4525 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
4527 /* Low hurts. Let's disable the filtering. */
4528 RTL_W16(RxMaxSize, rx_buf_sz + 1);
4531 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
4533 static const struct rtl_cfg2_info {
4538 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
4539 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
4540 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
4541 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
4543 const struct rtl_cfg2_info *p = cfg2_info;
4547 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
4548 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
4549 if ((p->mac_version == mac_version) && (p->clk == clk)) {
4550 RTL_W32(0x7c, p->val);
4556 static void rtl_set_rx_mode(struct net_device *dev)
4558 struct rtl8169_private *tp = netdev_priv(dev);
4559 void __iomem *ioaddr = tp->mmio_addr;
4560 u32 mc_filter[2]; /* Multicast hash filter */
4564 if (dev->flags & IFF_PROMISC) {
4565 /* Unconditionally log net taps. */
4566 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4568 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4570 mc_filter[1] = mc_filter[0] = 0xffffffff;
4571 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4572 (dev->flags & IFF_ALLMULTI)) {
4573 /* Too many to filter perfectly -- accept all multicasts. */
4574 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4575 mc_filter[1] = mc_filter[0] = 0xffffffff;
4577 struct netdev_hw_addr *ha;
4579 rx_mode = AcceptBroadcast | AcceptMyPhys;
4580 mc_filter[1] = mc_filter[0] = 0;
4581 netdev_for_each_mc_addr(ha, dev) {
4582 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4583 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4584 rx_mode |= AcceptMulticast;
4588 if (dev->features & NETIF_F_RXALL)
4589 rx_mode |= (AcceptErr | AcceptRunt);
4591 tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
4593 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4594 u32 data = mc_filter[0];
4596 mc_filter[0] = swab32(mc_filter[1]);
4597 mc_filter[1] = swab32(data);
4600 if (tp->mac_version == RTL_GIGA_MAC_VER_35)
4601 mc_filter[1] = mc_filter[0] = 0xffffffff;
4603 RTL_W32(MAR0 + 4, mc_filter[1]);
4604 RTL_W32(MAR0 + 0, mc_filter[0]);
4606 RTL_W32(RxConfig, tmp);
4609 static void rtl_hw_start_8169(struct net_device *dev)
4611 struct rtl8169_private *tp = netdev_priv(dev);
4612 void __iomem *ioaddr = tp->mmio_addr;
4613 struct pci_dev *pdev = tp->pci_dev;
4615 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
4616 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
4617 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
4620 RTL_W8(Cfg9346, Cfg9346_Unlock);
4621 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4622 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4623 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4624 tp->mac_version == RTL_GIGA_MAC_VER_04)
4625 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4629 RTL_W8(EarlyTxThres, NoEarlyTx);
4631 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4633 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4634 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4635 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4636 tp->mac_version == RTL_GIGA_MAC_VER_04)
4637 rtl_set_rx_tx_config_registers(tp);
4639 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
4641 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4642 tp->mac_version == RTL_GIGA_MAC_VER_03) {
4643 dprintk("Set MAC Reg C+CR Offset 0xE0. "
4644 "Bit-3 and bit-14 MUST be 1\n");
4645 tp->cp_cmd |= (1 << 14);
4648 RTL_W16(CPlusCmd, tp->cp_cmd);
4650 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
4653 * Undocumented corner. Supposedly:
4654 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4656 RTL_W16(IntrMitigate, 0x0000);
4658 rtl_set_rx_tx_desc_registers(tp, ioaddr);
4660 if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
4661 tp->mac_version != RTL_GIGA_MAC_VER_02 &&
4662 tp->mac_version != RTL_GIGA_MAC_VER_03 &&
4663 tp->mac_version != RTL_GIGA_MAC_VER_04) {
4664 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4665 rtl_set_rx_tx_config_registers(tp);
4668 RTL_W8(Cfg9346, Cfg9346_Lock);
4670 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4673 RTL_W32(RxMissed, 0);
4675 rtl_set_rx_mode(dev);
4677 /* no early-rx interrupts */
4678 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
4681 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
4683 if (tp->csi_ops.write)
4684 tp->csi_ops.write(tp, addr, value);
4687 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
4689 return tp->csi_ops.read ? tp->csi_ops.read(tp, addr) : ~0;
4692 static void rtl_csi_access_enable(struct rtl8169_private *tp, u32 bits)
4696 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
4697 rtl_csi_write(tp, 0x070c, csi | bits);
4700 static void rtl_csi_access_enable_1(struct rtl8169_private *tp)
4702 rtl_csi_access_enable(tp, 0x17000000);
4705 static void rtl_csi_access_enable_2(struct rtl8169_private *tp)
4707 rtl_csi_access_enable(tp, 0x27000000);
4710 DECLARE_RTL_COND(rtl_csiar_cond)
4712 void __iomem *ioaddr = tp->mmio_addr;
4714 return RTL_R32(CSIAR) & CSIAR_FLAG;
4717 static void r8169_csi_write(struct rtl8169_private *tp, int addr, int value)
4719 void __iomem *ioaddr = tp->mmio_addr;
4721 RTL_W32(CSIDR, value);
4722 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4723 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
4725 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
4728 static u32 r8169_csi_read(struct rtl8169_private *tp, int addr)
4730 void __iomem *ioaddr = tp->mmio_addr;
4732 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
4733 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
4735 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4736 RTL_R32(CSIDR) : ~0;
4739 static void r8402_csi_write(struct rtl8169_private *tp, int addr, int value)
4741 void __iomem *ioaddr = tp->mmio_addr;
4743 RTL_W32(CSIDR, value);
4744 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4745 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
4748 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
4751 static u32 r8402_csi_read(struct rtl8169_private *tp, int addr)
4753 void __iomem *ioaddr = tp->mmio_addr;
4755 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC |
4756 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
4758 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4759 RTL_R32(CSIDR) : ~0;
4762 static void rtl_init_csi_ops(struct rtl8169_private *tp)
4764 struct csi_ops *ops = &tp->csi_ops;
4766 switch (tp->mac_version) {
4767 case RTL_GIGA_MAC_VER_01:
4768 case RTL_GIGA_MAC_VER_02:
4769 case RTL_GIGA_MAC_VER_03:
4770 case RTL_GIGA_MAC_VER_04:
4771 case RTL_GIGA_MAC_VER_05:
4772 case RTL_GIGA_MAC_VER_06:
4773 case RTL_GIGA_MAC_VER_10:
4774 case RTL_GIGA_MAC_VER_11:
4775 case RTL_GIGA_MAC_VER_12:
4776 case RTL_GIGA_MAC_VER_13:
4777 case RTL_GIGA_MAC_VER_14:
4778 case RTL_GIGA_MAC_VER_15:
4779 case RTL_GIGA_MAC_VER_16:
4780 case RTL_GIGA_MAC_VER_17:
4785 case RTL_GIGA_MAC_VER_37:
4786 case RTL_GIGA_MAC_VER_38:
4787 ops->write = r8402_csi_write;
4788 ops->read = r8402_csi_read;
4792 ops->write = r8169_csi_write;
4793 ops->read = r8169_csi_read;
4799 unsigned int offset;
4804 static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e,
4810 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
4811 rtl_ephy_write(tp, e->offset, w);
4816 static void rtl_disable_clock_request(struct pci_dev *pdev)
4818 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL,
4819 PCI_EXP_LNKCTL_CLKREQ_EN);
4822 static void rtl_enable_clock_request(struct pci_dev *pdev)
4824 pcie_capability_set_word(pdev, PCI_EXP_LNKCTL,
4825 PCI_EXP_LNKCTL_CLKREQ_EN);
4828 #define R8168_CPCMD_QUIRK_MASK (\
4839 static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
4841 void __iomem *ioaddr = tp->mmio_addr;
4842 struct pci_dev *pdev = tp->pci_dev;
4844 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4846 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4848 if (tp->dev->mtu <= ETH_DATA_LEN) {
4849 rtl_tx_performance_tweak(pdev, (0x5 << MAX_READ_REQUEST_SHIFT) |
4850 PCI_EXP_DEVCTL_NOSNOOP_EN);
4854 static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
4856 void __iomem *ioaddr = tp->mmio_addr;
4858 rtl_hw_start_8168bb(tp);
4860 RTL_W8(MaxTxPacketSize, TxPacketMax);
4862 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
4865 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
4867 void __iomem *ioaddr = tp->mmio_addr;
4868 struct pci_dev *pdev = tp->pci_dev;
4870 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
4872 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4874 if (tp->dev->mtu <= ETH_DATA_LEN)
4875 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4877 rtl_disable_clock_request(pdev);
4879 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4882 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
4884 static const struct ephy_info e_info_8168cp[] = {
4885 { 0x01, 0, 0x0001 },
4886 { 0x02, 0x0800, 0x1000 },
4887 { 0x03, 0, 0x0042 },
4888 { 0x06, 0x0080, 0x0000 },
4892 rtl_csi_access_enable_2(tp);
4894 rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
4896 __rtl_hw_start_8168cp(tp);
4899 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
4901 void __iomem *ioaddr = tp->mmio_addr;
4902 struct pci_dev *pdev = tp->pci_dev;
4904 rtl_csi_access_enable_2(tp);
4906 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4908 if (tp->dev->mtu <= ETH_DATA_LEN)
4909 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4911 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4914 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
4916 void __iomem *ioaddr = tp->mmio_addr;
4917 struct pci_dev *pdev = tp->pci_dev;
4919 rtl_csi_access_enable_2(tp);
4921 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4924 RTL_W8(DBG_REG, 0x20);
4926 RTL_W8(MaxTxPacketSize, TxPacketMax);
4928 if (tp->dev->mtu <= ETH_DATA_LEN)
4929 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4931 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4934 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
4936 void __iomem *ioaddr = tp->mmio_addr;
4937 static const struct ephy_info e_info_8168c_1[] = {
4938 { 0x02, 0x0800, 0x1000 },
4939 { 0x03, 0, 0x0002 },
4940 { 0x06, 0x0080, 0x0000 }
4943 rtl_csi_access_enable_2(tp);
4945 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4947 rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
4949 __rtl_hw_start_8168cp(tp);
4952 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
4954 static const struct ephy_info e_info_8168c_2[] = {
4955 { 0x01, 0, 0x0001 },
4956 { 0x03, 0x0400, 0x0220 }
4959 rtl_csi_access_enable_2(tp);
4961 rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
4963 __rtl_hw_start_8168cp(tp);
4966 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
4968 rtl_hw_start_8168c_2(tp);
4971 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
4973 rtl_csi_access_enable_2(tp);
4975 __rtl_hw_start_8168cp(tp);
4978 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
4980 void __iomem *ioaddr = tp->mmio_addr;
4981 struct pci_dev *pdev = tp->pci_dev;
4983 rtl_csi_access_enable_2(tp);
4985 rtl_disable_clock_request(pdev);
4987 RTL_W8(MaxTxPacketSize, TxPacketMax);
4989 if (tp->dev->mtu <= ETH_DATA_LEN)
4990 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4992 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4995 static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
4997 void __iomem *ioaddr = tp->mmio_addr;
4998 struct pci_dev *pdev = tp->pci_dev;
5000 rtl_csi_access_enable_1(tp);
5002 if (tp->dev->mtu <= ETH_DATA_LEN)
5003 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5005 RTL_W8(MaxTxPacketSize, TxPacketMax);
5007 rtl_disable_clock_request(pdev);
5010 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
5012 void __iomem *ioaddr = tp->mmio_addr;
5013 struct pci_dev *pdev = tp->pci_dev;
5014 static const struct ephy_info e_info_8168d_4[] = {
5016 { 0x19, 0x20, 0x50 },
5021 rtl_csi_access_enable_1(tp);
5023 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5025 RTL_W8(MaxTxPacketSize, TxPacketMax);
5027 for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
5028 const struct ephy_info *e = e_info_8168d_4 + i;
5031 w = rtl_ephy_read(tp, e->offset);
5032 rtl_ephy_write(tp, 0x03, (w & e->mask) | e->bits);
5035 rtl_enable_clock_request(pdev);
5038 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
5040 void __iomem *ioaddr = tp->mmio_addr;
5041 struct pci_dev *pdev = tp->pci_dev;
5042 static const struct ephy_info e_info_8168e_1[] = {
5043 { 0x00, 0x0200, 0x0100 },
5044 { 0x00, 0x0000, 0x0004 },
5045 { 0x06, 0x0002, 0x0001 },
5046 { 0x06, 0x0000, 0x0030 },
5047 { 0x07, 0x0000, 0x2000 },
5048 { 0x00, 0x0000, 0x0020 },
5049 { 0x03, 0x5800, 0x2000 },
5050 { 0x03, 0x0000, 0x0001 },
5051 { 0x01, 0x0800, 0x1000 },
5052 { 0x07, 0x0000, 0x4000 },
5053 { 0x1e, 0x0000, 0x2000 },
5054 { 0x19, 0xffff, 0xfe6c },
5055 { 0x0a, 0x0000, 0x0040 }
5058 rtl_csi_access_enable_2(tp);
5060 rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
5062 if (tp->dev->mtu <= ETH_DATA_LEN)
5063 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5065 RTL_W8(MaxTxPacketSize, TxPacketMax);
5067 rtl_disable_clock_request(pdev);
5069 /* Reset tx FIFO pointer */
5070 RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
5071 RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
5073 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
5076 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
5078 void __iomem *ioaddr = tp->mmio_addr;
5079 struct pci_dev *pdev = tp->pci_dev;
5080 static const struct ephy_info e_info_8168e_2[] = {
5081 { 0x09, 0x0000, 0x0080 },
5082 { 0x19, 0x0000, 0x0224 }
5085 rtl_csi_access_enable_1(tp);
5087 rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
5089 if (tp->dev->mtu <= ETH_DATA_LEN)
5090 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5092 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5093 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5094 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5095 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5096 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5097 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
5098 rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5099 rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5101 RTL_W8(MaxTxPacketSize, EarlySize);
5103 rtl_disable_clock_request(pdev);
5105 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5106 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5108 /* Adjust EEE LED frequency */
5109 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5111 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5112 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
5113 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
5116 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
5118 void __iomem *ioaddr = tp->mmio_addr;
5119 struct pci_dev *pdev = tp->pci_dev;
5121 rtl_csi_access_enable_2(tp);
5123 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5125 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5126 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5127 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5128 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5129 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5130 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5131 rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5132 rtl_w1w0_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5133 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5134 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
5136 RTL_W8(MaxTxPacketSize, EarlySize);
5138 rtl_disable_clock_request(pdev);
5140 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5141 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5142 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5143 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
5144 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
5147 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
5149 void __iomem *ioaddr = tp->mmio_addr;
5150 static const struct ephy_info e_info_8168f_1[] = {
5151 { 0x06, 0x00c0, 0x0020 },
5152 { 0x08, 0x0001, 0x0002 },
5153 { 0x09, 0x0000, 0x0080 },
5154 { 0x19, 0x0000, 0x0224 }
5157 rtl_hw_start_8168f(tp);
5159 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5161 rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5163 /* Adjust EEE LED frequency */
5164 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5167 static void rtl_hw_start_8411(struct rtl8169_private *tp)
5169 static const struct ephy_info e_info_8168f_1[] = {
5170 { 0x06, 0x00c0, 0x0020 },
5171 { 0x0f, 0xffff, 0x5200 },
5172 { 0x1e, 0x0000, 0x4000 },
5173 { 0x19, 0x0000, 0x0224 }
5176 rtl_hw_start_8168f(tp);
5178 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5180 rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC);
5183 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
5185 void __iomem *ioaddr = tp->mmio_addr;
5186 struct pci_dev *pdev = tp->pci_dev;
5188 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5190 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC);
5191 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5192 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5193 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5195 rtl_csi_access_enable_1(tp);
5197 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5199 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5200 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5201 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f, ERIAR_EXGMAC);
5203 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5204 RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
5205 RTL_W8(MaxTxPacketSize, EarlySize);
5207 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5208 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5210 /* Adjust EEE LED frequency */
5211 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5213 rtl_w1w0_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
5214 rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
5217 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
5219 void __iomem *ioaddr = tp->mmio_addr;
5220 static const struct ephy_info e_info_8168g_2[] = {
5221 { 0x00, 0x0000, 0x0008 },
5222 { 0x0c, 0x3df0, 0x0200 },
5223 { 0x19, 0xffff, 0xfc00 },
5224 { 0x1e, 0xffff, 0x20eb }
5227 rtl_hw_start_8168g_1(tp);
5229 /* disable aspm and clock request before access ephy */
5230 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
5231 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
5232 rtl_ephy_init(tp, e_info_8168g_2, ARRAY_SIZE(e_info_8168g_2));
5235 static void rtl_hw_start_8168(struct net_device *dev)
5237 struct rtl8169_private *tp = netdev_priv(dev);
5238 void __iomem *ioaddr = tp->mmio_addr;
5240 RTL_W8(Cfg9346, Cfg9346_Unlock);
5242 RTL_W8(MaxTxPacketSize, TxPacketMax);
5244 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
5246 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
5248 RTL_W16(CPlusCmd, tp->cp_cmd);
5250 RTL_W16(IntrMitigate, 0x5151);
5252 /* Work around for RxFIFO overflow. */
5253 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
5254 tp->event_slow |= RxFIFOOver | PCSTimeout;
5255 tp->event_slow &= ~RxOverflow;
5258 rtl_set_rx_tx_desc_registers(tp, ioaddr);
5260 rtl_set_rx_tx_config_registers(tp);
5264 switch (tp->mac_version) {
5265 case RTL_GIGA_MAC_VER_11:
5266 rtl_hw_start_8168bb(tp);
5269 case RTL_GIGA_MAC_VER_12:
5270 case RTL_GIGA_MAC_VER_17:
5271 rtl_hw_start_8168bef(tp);
5274 case RTL_GIGA_MAC_VER_18:
5275 rtl_hw_start_8168cp_1(tp);
5278 case RTL_GIGA_MAC_VER_19:
5279 rtl_hw_start_8168c_1(tp);
5282 case RTL_GIGA_MAC_VER_20:
5283 rtl_hw_start_8168c_2(tp);
5286 case RTL_GIGA_MAC_VER_21:
5287 rtl_hw_start_8168c_3(tp);
5290 case RTL_GIGA_MAC_VER_22:
5291 rtl_hw_start_8168c_4(tp);
5294 case RTL_GIGA_MAC_VER_23:
5295 rtl_hw_start_8168cp_2(tp);
5298 case RTL_GIGA_MAC_VER_24:
5299 rtl_hw_start_8168cp_3(tp);
5302 case RTL_GIGA_MAC_VER_25:
5303 case RTL_GIGA_MAC_VER_26:
5304 case RTL_GIGA_MAC_VER_27:
5305 rtl_hw_start_8168d(tp);
5308 case RTL_GIGA_MAC_VER_28:
5309 rtl_hw_start_8168d_4(tp);
5312 case RTL_GIGA_MAC_VER_31:
5313 rtl_hw_start_8168dp(tp);
5316 case RTL_GIGA_MAC_VER_32:
5317 case RTL_GIGA_MAC_VER_33:
5318 rtl_hw_start_8168e_1(tp);
5320 case RTL_GIGA_MAC_VER_34:
5321 rtl_hw_start_8168e_2(tp);
5324 case RTL_GIGA_MAC_VER_35:
5325 case RTL_GIGA_MAC_VER_36:
5326 rtl_hw_start_8168f_1(tp);
5329 case RTL_GIGA_MAC_VER_38:
5330 rtl_hw_start_8411(tp);
5333 case RTL_GIGA_MAC_VER_40:
5334 case RTL_GIGA_MAC_VER_41:
5335 rtl_hw_start_8168g_1(tp);
5337 case RTL_GIGA_MAC_VER_42:
5338 rtl_hw_start_8168g_2(tp);
5342 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
5343 dev->name, tp->mac_version);
5347 RTL_W8(Cfg9346, Cfg9346_Lock);
5349 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5351 rtl_set_rx_mode(dev);
5353 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
5356 #define R810X_CPCMD_QUIRK_MASK (\
5367 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
5369 void __iomem *ioaddr = tp->mmio_addr;
5370 struct pci_dev *pdev = tp->pci_dev;
5371 static const struct ephy_info e_info_8102e_1[] = {
5372 { 0x01, 0, 0x6e65 },
5373 { 0x02, 0, 0x091f },
5374 { 0x03, 0, 0xc2f9 },
5375 { 0x06, 0, 0xafb5 },
5376 { 0x07, 0, 0x0e00 },
5377 { 0x19, 0, 0xec80 },
5378 { 0x01, 0, 0x2e65 },
5383 rtl_csi_access_enable_2(tp);
5385 RTL_W8(DBG_REG, FIX_NAK_1);
5387 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5390 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
5391 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5393 cfg1 = RTL_R8(Config1);
5394 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
5395 RTL_W8(Config1, cfg1 & ~LEDS0);
5397 rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
5400 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
5402 void __iomem *ioaddr = tp->mmio_addr;
5403 struct pci_dev *pdev = tp->pci_dev;
5405 rtl_csi_access_enable_2(tp);
5407 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5409 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
5410 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5413 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
5415 rtl_hw_start_8102e_2(tp);
5417 rtl_ephy_write(tp, 0x03, 0xc2f9);
5420 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
5422 void __iomem *ioaddr = tp->mmio_addr;
5423 static const struct ephy_info e_info_8105e_1[] = {
5424 { 0x07, 0, 0x4000 },
5425 { 0x19, 0, 0x0200 },
5426 { 0x19, 0, 0x0020 },
5427 { 0x1e, 0, 0x2000 },
5428 { 0x03, 0, 0x0001 },
5429 { 0x19, 0, 0x0100 },
5430 { 0x19, 0, 0x0004 },
5434 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5435 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5437 /* Disable Early Tally Counter */
5438 RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
5440 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
5441 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5443 rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
5446 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
5448 rtl_hw_start_8105e_1(tp);
5449 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
5452 static void rtl_hw_start_8402(struct rtl8169_private *tp)
5454 void __iomem *ioaddr = tp->mmio_addr;
5455 static const struct ephy_info e_info_8402[] = {
5456 { 0x19, 0xffff, 0xff64 },
5460 rtl_csi_access_enable_2(tp);
5462 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5463 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5465 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5466 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5468 rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402));
5470 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
5472 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
5473 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
5474 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5475 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5476 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5477 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5478 rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC);
5481 static void rtl_hw_start_8106(struct rtl8169_private *tp)
5483 void __iomem *ioaddr = tp->mmio_addr;
5485 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5486 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5488 RTL_W32(MISC, (RTL_R32(MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
5489 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
5490 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
5493 static void rtl_hw_start_8101(struct net_device *dev)
5495 struct rtl8169_private *tp = netdev_priv(dev);
5496 void __iomem *ioaddr = tp->mmio_addr;
5497 struct pci_dev *pdev = tp->pci_dev;
5499 if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
5500 tp->event_slow &= ~RxFIFOOver;
5502 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
5503 tp->mac_version == RTL_GIGA_MAC_VER_16)
5504 pcie_capability_set_word(pdev, PCI_EXP_DEVCTL,
5505 PCI_EXP_DEVCTL_NOSNOOP_EN);
5507 RTL_W8(Cfg9346, Cfg9346_Unlock);
5509 RTL_W8(MaxTxPacketSize, TxPacketMax);
5511 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
5513 tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
5514 RTL_W16(CPlusCmd, tp->cp_cmd);
5516 rtl_set_rx_tx_desc_registers(tp, ioaddr);
5518 rtl_set_rx_tx_config_registers(tp);
5520 switch (tp->mac_version) {
5521 case RTL_GIGA_MAC_VER_07:
5522 rtl_hw_start_8102e_1(tp);
5525 case RTL_GIGA_MAC_VER_08:
5526 rtl_hw_start_8102e_3(tp);
5529 case RTL_GIGA_MAC_VER_09:
5530 rtl_hw_start_8102e_2(tp);
5533 case RTL_GIGA_MAC_VER_29:
5534 rtl_hw_start_8105e_1(tp);
5536 case RTL_GIGA_MAC_VER_30:
5537 rtl_hw_start_8105e_2(tp);
5540 case RTL_GIGA_MAC_VER_37:
5541 rtl_hw_start_8402(tp);
5544 case RTL_GIGA_MAC_VER_39:
5545 rtl_hw_start_8106(tp);
5547 case RTL_GIGA_MAC_VER_43:
5548 rtl_hw_start_8168g_2(tp);
5552 RTL_W8(Cfg9346, Cfg9346_Lock);
5554 RTL_W16(IntrMitigate, 0x0000);
5556 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5558 rtl_set_rx_mode(dev);
5562 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
5565 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
5567 struct rtl8169_private *tp = netdev_priv(dev);
5569 if (new_mtu < ETH_ZLEN ||
5570 new_mtu > rtl_chip_infos[tp->mac_version].jumbo_max)
5573 if (new_mtu > ETH_DATA_LEN)
5574 rtl_hw_jumbo_enable(tp);
5576 rtl_hw_jumbo_disable(tp);
5579 netdev_update_features(dev);
5584 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
5586 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
5587 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
5590 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
5591 void **data_buff, struct RxDesc *desc)
5593 dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
5598 rtl8169_make_unusable_by_asic(desc);
5601 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
5603 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
5605 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
5608 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
5611 desc->addr = cpu_to_le64(mapping);
5613 rtl8169_mark_to_asic(desc, rx_buf_sz);
5616 static inline void *rtl8169_align(void *data)
5618 return (void *)ALIGN((long)data, 16);
5621 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
5622 struct RxDesc *desc)
5626 struct device *d = &tp->pci_dev->dev;
5627 struct net_device *dev = tp->dev;
5628 int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
5630 data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
5634 if (rtl8169_align(data) != data) {
5636 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
5641 mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
5643 if (unlikely(dma_mapping_error(d, mapping))) {
5644 if (net_ratelimit())
5645 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
5649 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
5657 static void rtl8169_rx_clear(struct rtl8169_private *tp)
5661 for (i = 0; i < NUM_RX_DESC; i++) {
5662 if (tp->Rx_databuff[i]) {
5663 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
5664 tp->RxDescArray + i);
5669 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
5671 desc->opts1 |= cpu_to_le32(RingEnd);
5674 static int rtl8169_rx_fill(struct rtl8169_private *tp)
5678 for (i = 0; i < NUM_RX_DESC; i++) {
5681 if (tp->Rx_databuff[i])
5684 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
5686 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
5689 tp->Rx_databuff[i] = data;
5692 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
5696 rtl8169_rx_clear(tp);
5700 static int rtl8169_init_ring(struct net_device *dev)
5702 struct rtl8169_private *tp = netdev_priv(dev);
5704 rtl8169_init_ring_indexes(tp);
5706 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
5707 memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
5709 return rtl8169_rx_fill(tp);
5712 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
5713 struct TxDesc *desc)
5715 unsigned int len = tx_skb->len;
5717 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
5725 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
5730 for (i = 0; i < n; i++) {
5731 unsigned int entry = (start + i) % NUM_TX_DESC;
5732 struct ring_info *tx_skb = tp->tx_skb + entry;
5733 unsigned int len = tx_skb->len;
5736 struct sk_buff *skb = tx_skb->skb;
5738 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
5739 tp->TxDescArray + entry);
5741 tp->dev->stats.tx_dropped++;
5749 static void rtl8169_tx_clear(struct rtl8169_private *tp)
5751 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
5752 tp->cur_tx = tp->dirty_tx = 0;
5755 static void rtl_reset_work(struct rtl8169_private *tp)
5757 struct net_device *dev = tp->dev;
5760 napi_disable(&tp->napi);
5761 netif_stop_queue(dev);
5762 synchronize_sched();
5764 rtl8169_hw_reset(tp);
5766 for (i = 0; i < NUM_RX_DESC; i++)
5767 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
5769 rtl8169_tx_clear(tp);
5770 rtl8169_init_ring_indexes(tp);
5772 napi_enable(&tp->napi);
5774 netif_wake_queue(dev);
5775 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
5778 static void rtl8169_tx_timeout(struct net_device *dev)
5780 struct rtl8169_private *tp = netdev_priv(dev);
5782 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5785 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
5788 struct skb_shared_info *info = skb_shinfo(skb);
5789 unsigned int cur_frag, entry;
5790 struct TxDesc * uninitialized_var(txd);
5791 struct device *d = &tp->pci_dev->dev;
5794 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
5795 const skb_frag_t *frag = info->frags + cur_frag;
5800 entry = (entry + 1) % NUM_TX_DESC;
5802 txd = tp->TxDescArray + entry;
5803 len = skb_frag_size(frag);
5804 addr = skb_frag_address(frag);
5805 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
5806 if (unlikely(dma_mapping_error(d, mapping))) {
5807 if (net_ratelimit())
5808 netif_err(tp, drv, tp->dev,
5809 "Failed to map TX fragments DMA!\n");
5813 /* Anti gcc 2.95.3 bugware (sic) */
5814 status = opts[0] | len |
5815 (RingEnd * !((entry + 1) % NUM_TX_DESC));
5817 txd->opts1 = cpu_to_le32(status);
5818 txd->opts2 = cpu_to_le32(opts[1]);
5819 txd->addr = cpu_to_le64(mapping);
5821 tp->tx_skb[entry].len = len;
5825 tp->tx_skb[entry].skb = skb;
5826 txd->opts1 |= cpu_to_le32(LastFrag);
5832 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5836 static inline void rtl8169_tso_csum(struct rtl8169_private *tp,
5837 struct sk_buff *skb, u32 *opts)
5839 const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version;
5840 u32 mss = skb_shinfo(skb)->gso_size;
5841 int offset = info->opts_offset;
5845 opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift;
5846 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5847 const struct iphdr *ip = ip_hdr(skb);
5849 if (ip->protocol == IPPROTO_TCP)
5850 opts[offset] |= info->checksum.tcp;
5851 else if (ip->protocol == IPPROTO_UDP)
5852 opts[offset] |= info->checksum.udp;
5858 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5859 struct net_device *dev)
5861 struct rtl8169_private *tp = netdev_priv(dev);
5862 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
5863 struct TxDesc *txd = tp->TxDescArray + entry;
5864 void __iomem *ioaddr = tp->mmio_addr;
5865 struct device *d = &tp->pci_dev->dev;
5871 if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
5872 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
5876 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
5879 len = skb_headlen(skb);
5880 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
5881 if (unlikely(dma_mapping_error(d, mapping))) {
5882 if (net_ratelimit())
5883 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
5887 tp->tx_skb[entry].len = len;
5888 txd->addr = cpu_to_le64(mapping);
5890 opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb));
5893 rtl8169_tso_csum(tp, skb, opts);
5895 frags = rtl8169_xmit_frags(tp, skb, opts);
5899 opts[0] |= FirstFrag;
5901 opts[0] |= FirstFrag | LastFrag;
5902 tp->tx_skb[entry].skb = skb;
5905 txd->opts2 = cpu_to_le32(opts[1]);
5907 skb_tx_timestamp(skb);
5911 /* Anti gcc 2.95.3 bugware (sic) */
5912 status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
5913 txd->opts1 = cpu_to_le32(status);
5915 tp->cur_tx += frags + 1;
5919 RTL_W8(TxPoll, NPQ);
5923 if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
5924 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
5925 * not miss a ring update when it notices a stopped queue.
5928 netif_stop_queue(dev);
5929 /* Sync with rtl_tx:
5930 * - publish queue status and cur_tx ring index (write barrier)
5931 * - refresh dirty_tx ring index (read barrier).
5932 * May the current thread have a pessimistic view of the ring
5933 * status and forget to wake up queue, a racing rtl_tx thread
5937 if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
5938 netif_wake_queue(dev);
5941 return NETDEV_TX_OK;
5944 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
5947 dev->stats.tx_dropped++;
5948 return NETDEV_TX_OK;
5951 netif_stop_queue(dev);
5952 dev->stats.tx_dropped++;
5953 return NETDEV_TX_BUSY;
5956 static void rtl8169_pcierr_interrupt(struct net_device *dev)
5958 struct rtl8169_private *tp = netdev_priv(dev);
5959 struct pci_dev *pdev = tp->pci_dev;
5960 u16 pci_status, pci_cmd;
5962 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
5963 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
5965 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
5966 pci_cmd, pci_status);
5969 * The recovery sequence below admits a very elaborated explanation:
5970 * - it seems to work;
5971 * - I did not see what else could be done;
5972 * - it makes iop3xx happy.
5974 * Feel free to adjust to your needs.
5976 if (pdev->broken_parity_status)
5977 pci_cmd &= ~PCI_COMMAND_PARITY;
5979 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
5981 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
5983 pci_write_config_word(pdev, PCI_STATUS,
5984 pci_status & (PCI_STATUS_DETECTED_PARITY |
5985 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
5986 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
5988 /* The infamous DAC f*ckup only happens at boot time */
5989 if ((tp->cp_cmd & PCIDAC) && !tp->cur_rx) {
5990 void __iomem *ioaddr = tp->mmio_addr;
5992 netif_info(tp, intr, dev, "disabling PCI DAC\n");
5993 tp->cp_cmd &= ~PCIDAC;
5994 RTL_W16(CPlusCmd, tp->cp_cmd);
5995 dev->features &= ~NETIF_F_HIGHDMA;
5998 rtl8169_hw_reset(tp);
6000 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6003 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
6005 unsigned int dirty_tx, tx_left;
6007 dirty_tx = tp->dirty_tx;
6009 tx_left = tp->cur_tx - dirty_tx;
6011 while (tx_left > 0) {
6012 unsigned int entry = dirty_tx % NUM_TX_DESC;
6013 struct ring_info *tx_skb = tp->tx_skb + entry;
6017 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
6018 if (status & DescOwn)
6021 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
6022 tp->TxDescArray + entry);
6023 if (status & LastFrag) {
6024 u64_stats_update_begin(&tp->tx_stats.syncp);
6025 tp->tx_stats.packets++;
6026 tp->tx_stats.bytes += tx_skb->skb->len;
6027 u64_stats_update_end(&tp->tx_stats.syncp);
6028 dev_kfree_skb(tx_skb->skb);
6035 if (tp->dirty_tx != dirty_tx) {
6036 tp->dirty_tx = dirty_tx;
6037 /* Sync with rtl8169_start_xmit:
6038 * - publish dirty_tx ring index (write barrier)
6039 * - refresh cur_tx ring index and queue status (read barrier)
6040 * May the current thread miss the stopped queue condition,
6041 * a racing xmit thread can only have a right view of the
6045 if (netif_queue_stopped(dev) &&
6046 TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
6047 netif_wake_queue(dev);
6050 * 8168 hack: TxPoll requests are lost when the Tx packets are
6051 * too close. Let's kick an extra TxPoll request when a burst
6052 * of start_xmit activity is detected (if it is not detected,
6053 * it is slow enough). -- FR
6055 if (tp->cur_tx != dirty_tx) {
6056 void __iomem *ioaddr = tp->mmio_addr;
6058 RTL_W8(TxPoll, NPQ);
6063 static inline int rtl8169_fragmented_frame(u32 status)
6065 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
6068 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
6070 u32 status = opts1 & RxProtoMask;
6072 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
6073 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
6074 skb->ip_summed = CHECKSUM_UNNECESSARY;
6076 skb_checksum_none_assert(skb);
6079 static struct sk_buff *rtl8169_try_rx_copy(void *data,
6080 struct rtl8169_private *tp,
6084 struct sk_buff *skb;
6085 struct device *d = &tp->pci_dev->dev;
6087 data = rtl8169_align(data);
6088 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6090 skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
6092 memcpy(skb->data, data, pkt_size);
6093 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
6098 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
6100 unsigned int cur_rx, rx_left;
6103 cur_rx = tp->cur_rx;
6105 for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
6106 unsigned int entry = cur_rx % NUM_RX_DESC;
6107 struct RxDesc *desc = tp->RxDescArray + entry;
6111 status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
6113 if (status & DescOwn)
6115 if (unlikely(status & RxRES)) {
6116 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
6118 dev->stats.rx_errors++;
6119 if (status & (RxRWT | RxRUNT))
6120 dev->stats.rx_length_errors++;
6122 dev->stats.rx_crc_errors++;
6123 if (status & RxFOVF) {
6124 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6125 dev->stats.rx_fifo_errors++;
6127 if ((status & (RxRUNT | RxCRC)) &&
6128 !(status & (RxRWT | RxFOVF)) &&
6129 (dev->features & NETIF_F_RXALL))
6132 struct sk_buff *skb;
6137 addr = le64_to_cpu(desc->addr);
6138 if (likely(!(dev->features & NETIF_F_RXFCS)))
6139 pkt_size = (status & 0x00003fff) - 4;
6141 pkt_size = status & 0x00003fff;
6144 * The driver does not support incoming fragmented
6145 * frames. They are seen as a symptom of over-mtu
6148 if (unlikely(rtl8169_fragmented_frame(status))) {
6149 dev->stats.rx_dropped++;
6150 dev->stats.rx_length_errors++;
6151 goto release_descriptor;
6154 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
6155 tp, pkt_size, addr);
6157 dev->stats.rx_dropped++;
6158 goto release_descriptor;
6161 rtl8169_rx_csum(skb, status);
6162 skb_put(skb, pkt_size);
6163 skb->protocol = eth_type_trans(skb, dev);
6165 rtl8169_rx_vlan_tag(desc, skb);
6167 napi_gro_receive(&tp->napi, skb);
6169 u64_stats_update_begin(&tp->rx_stats.syncp);
6170 tp->rx_stats.packets++;
6171 tp->rx_stats.bytes += pkt_size;
6172 u64_stats_update_end(&tp->rx_stats.syncp);
6177 rtl8169_mark_to_asic(desc, rx_buf_sz);
6180 count = cur_rx - tp->cur_rx;
6181 tp->cur_rx = cur_rx;
6186 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
6188 struct net_device *dev = dev_instance;
6189 struct rtl8169_private *tp = netdev_priv(dev);
6193 status = rtl_get_events(tp);
6194 if (status && status != 0xffff) {
6195 status &= RTL_EVENT_NAPI | tp->event_slow;
6199 rtl_irq_disable(tp);
6200 napi_schedule(&tp->napi);
6203 return IRQ_RETVAL(handled);
6207 * Workqueue context.
6209 static void rtl_slow_event_work(struct rtl8169_private *tp)
6211 struct net_device *dev = tp->dev;
6214 status = rtl_get_events(tp) & tp->event_slow;
6215 rtl_ack_events(tp, status);
6217 if (unlikely(status & RxFIFOOver)) {
6218 switch (tp->mac_version) {
6219 /* Work around for rx fifo overflow */
6220 case RTL_GIGA_MAC_VER_11:
6221 netif_stop_queue(dev);
6222 /* XXX - Hack alert. See rtl_task(). */
6223 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
6229 if (unlikely(status & SYSErr))
6230 rtl8169_pcierr_interrupt(dev);
6232 if (status & LinkChg)
6233 __rtl8169_check_link_status(dev, tp, tp->mmio_addr, true);
6235 rtl_irq_enable_all(tp);
6238 static void rtl_task(struct work_struct *work)
6240 static const struct {
6242 void (*action)(struct rtl8169_private *);
6244 /* XXX - keep rtl_slow_event_work() as first element. */
6245 { RTL_FLAG_TASK_SLOW_PENDING, rtl_slow_event_work },
6246 { RTL_FLAG_TASK_RESET_PENDING, rtl_reset_work },
6247 { RTL_FLAG_TASK_PHY_PENDING, rtl_phy_work }
6249 struct rtl8169_private *tp =
6250 container_of(work, struct rtl8169_private, wk.work);
6251 struct net_device *dev = tp->dev;
6256 if (!netif_running(dev) ||
6257 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
6260 for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
6263 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
6265 rtl_work[i].action(tp);
6269 rtl_unlock_work(tp);
6272 static int rtl8169_poll(struct napi_struct *napi, int budget)
6274 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
6275 struct net_device *dev = tp->dev;
6276 u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
6280 status = rtl_get_events(tp);
6281 rtl_ack_events(tp, status & ~tp->event_slow);
6283 if (status & RTL_EVENT_NAPI_RX)
6284 work_done = rtl_rx(dev, tp, (u32) budget);
6286 if (status & RTL_EVENT_NAPI_TX)
6289 if (status & tp->event_slow) {
6290 enable_mask &= ~tp->event_slow;
6292 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
6295 if (work_done < budget) {
6296 napi_complete(napi);
6298 rtl_irq_enable(tp, enable_mask);
6305 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
6307 struct rtl8169_private *tp = netdev_priv(dev);
6309 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
6312 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
6313 RTL_W32(RxMissed, 0);
6316 static void rtl8169_down(struct net_device *dev)
6318 struct rtl8169_private *tp = netdev_priv(dev);
6319 void __iomem *ioaddr = tp->mmio_addr;
6321 del_timer_sync(&tp->timer);
6323 napi_disable(&tp->napi);
6324 netif_stop_queue(dev);
6326 rtl8169_hw_reset(tp);
6328 * At this point device interrupts can not be enabled in any function,
6329 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
6330 * and napi is disabled (rtl8169_poll).
6332 rtl8169_rx_missed(dev, ioaddr);
6334 /* Give a racing hard_start_xmit a few cycles to complete. */
6335 synchronize_sched();
6337 rtl8169_tx_clear(tp);
6339 rtl8169_rx_clear(tp);
6341 rtl_pll_power_down(tp);
6344 static int rtl8169_close(struct net_device *dev)
6346 struct rtl8169_private *tp = netdev_priv(dev);
6347 struct pci_dev *pdev = tp->pci_dev;
6349 pm_runtime_get_sync(&pdev->dev);
6351 /* Update counters before going down */
6352 rtl8169_update_counters(dev);
6355 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6358 rtl_unlock_work(tp);
6360 free_irq(pdev->irq, dev);
6362 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6364 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6366 tp->TxDescArray = NULL;
6367 tp->RxDescArray = NULL;
6369 pm_runtime_put_sync(&pdev->dev);
6374 #ifdef CONFIG_NET_POLL_CONTROLLER
6375 static void rtl8169_netpoll(struct net_device *dev)
6377 struct rtl8169_private *tp = netdev_priv(dev);
6379 rtl8169_interrupt(tp->pci_dev->irq, dev);
6383 static int rtl_open(struct net_device *dev)
6385 struct rtl8169_private *tp = netdev_priv(dev);
6386 void __iomem *ioaddr = tp->mmio_addr;
6387 struct pci_dev *pdev = tp->pci_dev;
6388 int retval = -ENOMEM;
6390 pm_runtime_get_sync(&pdev->dev);
6393 * Rx and Tx descriptors needs 256 bytes alignment.
6394 * dma_alloc_coherent provides more.
6396 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
6397 &tp->TxPhyAddr, GFP_KERNEL);
6398 if (!tp->TxDescArray)
6399 goto err_pm_runtime_put;
6401 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
6402 &tp->RxPhyAddr, GFP_KERNEL);
6403 if (!tp->RxDescArray)
6406 retval = rtl8169_init_ring(dev);
6410 INIT_WORK(&tp->wk.work, rtl_task);
6414 rtl_request_firmware(tp);
6416 retval = request_irq(pdev->irq, rtl8169_interrupt,
6417 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
6420 goto err_release_fw_2;
6424 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6426 napi_enable(&tp->napi);
6428 rtl8169_init_phy(dev, tp);
6430 __rtl8169_set_features(dev, dev->features);
6432 rtl_pll_power_up(tp);
6436 netif_start_queue(dev);
6438 rtl_unlock_work(tp);
6440 tp->saved_wolopts = 0;
6441 pm_runtime_put_noidle(&pdev->dev);
6443 rtl8169_check_link_status(dev, tp, ioaddr);
6448 rtl_release_firmware(tp);
6449 rtl8169_rx_clear(tp);
6451 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6453 tp->RxDescArray = NULL;
6455 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6457 tp->TxDescArray = NULL;
6459 pm_runtime_put_noidle(&pdev->dev);
6463 static struct rtnl_link_stats64 *
6464 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
6466 struct rtl8169_private *tp = netdev_priv(dev);
6467 void __iomem *ioaddr = tp->mmio_addr;
6470 if (netif_running(dev))
6471 rtl8169_rx_missed(dev, ioaddr);
6474 start = u64_stats_fetch_begin_bh(&tp->rx_stats.syncp);
6475 stats->rx_packets = tp->rx_stats.packets;
6476 stats->rx_bytes = tp->rx_stats.bytes;
6477 } while (u64_stats_fetch_retry_bh(&tp->rx_stats.syncp, start));
6481 start = u64_stats_fetch_begin_bh(&tp->tx_stats.syncp);
6482 stats->tx_packets = tp->tx_stats.packets;
6483 stats->tx_bytes = tp->tx_stats.bytes;
6484 } while (u64_stats_fetch_retry_bh(&tp->tx_stats.syncp, start));
6486 stats->rx_dropped = dev->stats.rx_dropped;
6487 stats->tx_dropped = dev->stats.tx_dropped;
6488 stats->rx_length_errors = dev->stats.rx_length_errors;
6489 stats->rx_errors = dev->stats.rx_errors;
6490 stats->rx_crc_errors = dev->stats.rx_crc_errors;
6491 stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
6492 stats->rx_missed_errors = dev->stats.rx_missed_errors;
6497 static void rtl8169_net_suspend(struct net_device *dev)
6499 struct rtl8169_private *tp = netdev_priv(dev);
6501 if (!netif_running(dev))
6504 netif_device_detach(dev);
6505 netif_stop_queue(dev);
6508 napi_disable(&tp->napi);
6509 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6510 rtl_unlock_work(tp);
6512 rtl_pll_power_down(tp);
6517 static int rtl8169_suspend(struct device *device)
6519 struct pci_dev *pdev = to_pci_dev(device);
6520 struct net_device *dev = pci_get_drvdata(pdev);
6522 rtl8169_net_suspend(dev);
6527 static void __rtl8169_resume(struct net_device *dev)
6529 struct rtl8169_private *tp = netdev_priv(dev);
6531 netif_device_attach(dev);
6533 rtl_pll_power_up(tp);
6536 napi_enable(&tp->napi);
6537 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6538 rtl_unlock_work(tp);
6540 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6543 static int rtl8169_resume(struct device *device)
6545 struct pci_dev *pdev = to_pci_dev(device);
6546 struct net_device *dev = pci_get_drvdata(pdev);
6547 struct rtl8169_private *tp = netdev_priv(dev);
6549 rtl8169_init_phy(dev, tp);
6551 if (netif_running(dev))
6552 __rtl8169_resume(dev);
6557 static int rtl8169_runtime_suspend(struct device *device)
6559 struct pci_dev *pdev = to_pci_dev(device);
6560 struct net_device *dev = pci_get_drvdata(pdev);
6561 struct rtl8169_private *tp = netdev_priv(dev);
6563 if (!tp->TxDescArray)
6567 tp->saved_wolopts = __rtl8169_get_wol(tp);
6568 __rtl8169_set_wol(tp, WAKE_ANY);
6569 rtl_unlock_work(tp);
6571 rtl8169_net_suspend(dev);
6576 static int rtl8169_runtime_resume(struct device *device)
6578 struct pci_dev *pdev = to_pci_dev(device);
6579 struct net_device *dev = pci_get_drvdata(pdev);
6580 struct rtl8169_private *tp = netdev_priv(dev);
6582 if (!tp->TxDescArray)
6586 __rtl8169_set_wol(tp, tp->saved_wolopts);
6587 tp->saved_wolopts = 0;
6588 rtl_unlock_work(tp);
6590 rtl8169_init_phy(dev, tp);
6592 __rtl8169_resume(dev);
6597 static int rtl8169_runtime_idle(struct device *device)
6599 struct pci_dev *pdev = to_pci_dev(device);
6600 struct net_device *dev = pci_get_drvdata(pdev);
6601 struct rtl8169_private *tp = netdev_priv(dev);
6603 return tp->TxDescArray ? -EBUSY : 0;
6606 static const struct dev_pm_ops rtl8169_pm_ops = {
6607 .suspend = rtl8169_suspend,
6608 .resume = rtl8169_resume,
6609 .freeze = rtl8169_suspend,
6610 .thaw = rtl8169_resume,
6611 .poweroff = rtl8169_suspend,
6612 .restore = rtl8169_resume,
6613 .runtime_suspend = rtl8169_runtime_suspend,
6614 .runtime_resume = rtl8169_runtime_resume,
6615 .runtime_idle = rtl8169_runtime_idle,
6618 #define RTL8169_PM_OPS (&rtl8169_pm_ops)
6620 #else /* !CONFIG_PM */
6622 #define RTL8169_PM_OPS NULL
6624 #endif /* !CONFIG_PM */
6626 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
6628 void __iomem *ioaddr = tp->mmio_addr;
6630 /* WoL fails with 8168b when the receiver is disabled. */
6631 switch (tp->mac_version) {
6632 case RTL_GIGA_MAC_VER_11:
6633 case RTL_GIGA_MAC_VER_12:
6634 case RTL_GIGA_MAC_VER_17:
6635 pci_clear_master(tp->pci_dev);
6637 RTL_W8(ChipCmd, CmdRxEnb);
6646 static void rtl_shutdown(struct pci_dev *pdev)
6648 struct net_device *dev = pci_get_drvdata(pdev);
6649 struct rtl8169_private *tp = netdev_priv(dev);
6650 struct device *d = &pdev->dev;
6652 pm_runtime_get_sync(d);
6654 rtl8169_net_suspend(dev);
6656 /* Restore original MAC address */
6657 rtl_rar_set(tp, dev->perm_addr);
6659 rtl8169_hw_reset(tp);
6661 if (system_state == SYSTEM_POWER_OFF) {
6662 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
6663 rtl_wol_suspend_quirk(tp);
6664 rtl_wol_shutdown_quirk(tp);
6667 pci_wake_from_d3(pdev, true);
6668 pci_set_power_state(pdev, PCI_D3hot);
6671 pm_runtime_put_noidle(d);
6674 static void rtl_remove_one(struct pci_dev *pdev)
6676 struct net_device *dev = pci_get_drvdata(pdev);
6677 struct rtl8169_private *tp = netdev_priv(dev);
6679 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
6680 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
6681 tp->mac_version == RTL_GIGA_MAC_VER_31) {
6682 rtl8168_driver_stop(tp);
6685 cancel_work_sync(&tp->wk.work);
6687 netif_napi_del(&tp->napi);
6689 unregister_netdev(dev);
6691 rtl_release_firmware(tp);
6693 if (pci_dev_run_wake(pdev))
6694 pm_runtime_get_noresume(&pdev->dev);
6696 /* restore original MAC address */
6697 rtl_rar_set(tp, dev->perm_addr);
6699 rtl_disable_msi(pdev, tp);
6700 rtl8169_release_board(pdev, dev, tp->mmio_addr);
6701 pci_set_drvdata(pdev, NULL);
6704 static const struct net_device_ops rtl_netdev_ops = {
6705 .ndo_open = rtl_open,
6706 .ndo_stop = rtl8169_close,
6707 .ndo_get_stats64 = rtl8169_get_stats64,
6708 .ndo_start_xmit = rtl8169_start_xmit,
6709 .ndo_tx_timeout = rtl8169_tx_timeout,
6710 .ndo_validate_addr = eth_validate_addr,
6711 .ndo_change_mtu = rtl8169_change_mtu,
6712 .ndo_fix_features = rtl8169_fix_features,
6713 .ndo_set_features = rtl8169_set_features,
6714 .ndo_set_mac_address = rtl_set_mac_address,
6715 .ndo_do_ioctl = rtl8169_ioctl,
6716 .ndo_set_rx_mode = rtl_set_rx_mode,
6717 #ifdef CONFIG_NET_POLL_CONTROLLER
6718 .ndo_poll_controller = rtl8169_netpoll,
6723 static const struct rtl_cfg_info {
6724 void (*hw_start)(struct net_device *);
6725 unsigned int region;
6730 } rtl_cfg_infos [] = {
6732 .hw_start = rtl_hw_start_8169,
6735 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
6736 .features = RTL_FEATURE_GMII,
6737 .default_ver = RTL_GIGA_MAC_VER_01,
6740 .hw_start = rtl_hw_start_8168,
6743 .event_slow = SYSErr | LinkChg | RxOverflow,
6744 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
6745 .default_ver = RTL_GIGA_MAC_VER_11,
6748 .hw_start = rtl_hw_start_8101,
6751 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
6753 .features = RTL_FEATURE_MSI,
6754 .default_ver = RTL_GIGA_MAC_VER_13,
6758 /* Cfg9346_Unlock assumed. */
6759 static unsigned rtl_try_msi(struct rtl8169_private *tp,
6760 const struct rtl_cfg_info *cfg)
6762 void __iomem *ioaddr = tp->mmio_addr;
6766 cfg2 = RTL_R8(Config2) & ~MSIEnable;
6767 if (cfg->features & RTL_FEATURE_MSI) {
6768 if (pci_enable_msi(tp->pci_dev)) {
6769 netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n");
6772 msi = RTL_FEATURE_MSI;
6775 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
6776 RTL_W8(Config2, cfg2);
6780 DECLARE_RTL_COND(rtl_link_list_ready_cond)
6782 void __iomem *ioaddr = tp->mmio_addr;
6784 return RTL_R8(MCU) & LINK_LIST_RDY;
6787 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
6789 void __iomem *ioaddr = tp->mmio_addr;
6791 return (RTL_R8(MCU) & RXTX_EMPTY) == RXTX_EMPTY;
6794 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
6796 void __iomem *ioaddr = tp->mmio_addr;
6799 tp->ocp_base = OCP_STD_PHY_BASE;
6801 RTL_W32(MISC, RTL_R32(MISC) | RXDV_GATED_EN);
6803 if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
6806 if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
6809 RTL_W8(ChipCmd, RTL_R8(ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
6811 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
6813 data = r8168_mac_ocp_read(tp, 0xe8de);
6815 r8168_mac_ocp_write(tp, 0xe8de, data);
6817 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
6820 data = r8168_mac_ocp_read(tp, 0xe8de);
6822 r8168_mac_ocp_write(tp, 0xe8de, data);
6824 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
6828 static void rtl_hw_initialize(struct rtl8169_private *tp)
6830 switch (tp->mac_version) {
6831 case RTL_GIGA_MAC_VER_40:
6832 case RTL_GIGA_MAC_VER_41:
6833 case RTL_GIGA_MAC_VER_42:
6834 case RTL_GIGA_MAC_VER_43:
6835 rtl_hw_init_8168g(tp);
6844 rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
6846 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
6847 const unsigned int region = cfg->region;
6848 struct rtl8169_private *tp;
6849 struct mii_if_info *mii;
6850 struct net_device *dev;
6851 void __iomem *ioaddr;
6855 if (netif_msg_drv(&debug)) {
6856 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
6857 MODULENAME, RTL8169_VERSION);
6860 dev = alloc_etherdev(sizeof (*tp));
6866 SET_NETDEV_DEV(dev, &pdev->dev);
6867 dev->netdev_ops = &rtl_netdev_ops;
6868 tp = netdev_priv(dev);
6871 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
6875 mii->mdio_read = rtl_mdio_read;
6876 mii->mdio_write = rtl_mdio_write;
6877 mii->phy_id_mask = 0x1f;
6878 mii->reg_num_mask = 0x1f;
6879 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
6881 /* disable ASPM completely as that cause random device stop working
6882 * problems as well as full system hangs for some PCIe devices users */
6883 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
6884 PCIE_LINK_STATE_CLKPM);
6886 /* enable device (incl. PCI PM wakeup and hotplug setup) */
6887 rc = pci_enable_device(pdev);
6889 netif_err(tp, probe, dev, "enable failure\n");
6890 goto err_out_free_dev_1;
6893 if (pci_set_mwi(pdev) < 0)
6894 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
6896 /* make sure PCI base addr 1 is MMIO */
6897 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
6898 netif_err(tp, probe, dev,
6899 "region #%d not an MMIO resource, aborting\n",
6905 /* check for weird/broken PCI region reporting */
6906 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
6907 netif_err(tp, probe, dev,
6908 "Invalid PCI region size(s), aborting\n");
6913 rc = pci_request_regions(pdev, MODULENAME);
6915 netif_err(tp, probe, dev, "could not request regions\n");
6919 tp->cp_cmd = RxChkSum;
6921 if ((sizeof(dma_addr_t) > 4) &&
6922 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
6923 tp->cp_cmd |= PCIDAC;
6924 dev->features |= NETIF_F_HIGHDMA;
6926 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
6928 netif_err(tp, probe, dev, "DMA configuration failed\n");
6929 goto err_out_free_res_3;
6933 /* ioremap MMIO region */
6934 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
6936 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
6938 goto err_out_free_res_3;
6940 tp->mmio_addr = ioaddr;
6942 if (!pci_is_pcie(pdev))
6943 netif_info(tp, probe, dev, "not PCI Express\n");
6945 /* Identify chip attached to board */
6946 rtl8169_get_mac_version(tp, dev, cfg->default_ver);
6950 rtl_irq_disable(tp);
6952 rtl_hw_initialize(tp);
6956 rtl_ack_events(tp, 0xffff);
6958 pci_set_master(pdev);
6961 * Pretend we are using VLANs; This bypasses a nasty bug where
6962 * Interrupts stop flowing on high load on 8110SCd controllers.
6964 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
6965 tp->cp_cmd |= RxVlan;
6967 rtl_init_mdio_ops(tp);
6968 rtl_init_pll_power_ops(tp);
6969 rtl_init_jumbo_ops(tp);
6970 rtl_init_csi_ops(tp);
6972 rtl8169_print_mac_version(tp);
6974 chipset = tp->mac_version;
6975 tp->txd_version = rtl_chip_infos[chipset].txd_version;
6977 RTL_W8(Cfg9346, Cfg9346_Unlock);
6978 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
6979 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
6980 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
6981 tp->features |= RTL_FEATURE_WOL;
6982 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
6983 tp->features |= RTL_FEATURE_WOL;
6984 tp->features |= rtl_try_msi(tp, cfg);
6985 RTL_W8(Cfg9346, Cfg9346_Lock);
6987 if (rtl_tbi_enabled(tp)) {
6988 tp->set_speed = rtl8169_set_speed_tbi;
6989 tp->get_settings = rtl8169_gset_tbi;
6990 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
6991 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
6992 tp->link_ok = rtl8169_tbi_link_ok;
6993 tp->do_ioctl = rtl_tbi_ioctl;
6995 tp->set_speed = rtl8169_set_speed_xmii;
6996 tp->get_settings = rtl8169_gset_xmii;
6997 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
6998 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
6999 tp->link_ok = rtl8169_xmii_link_ok;
7000 tp->do_ioctl = rtl_xmii_ioctl;
7003 mutex_init(&tp->wk.mutex);
7005 /* Get MAC address */
7006 for (i = 0; i < ETH_ALEN; i++)
7007 dev->dev_addr[i] = RTL_R8(MAC0 + i);
7009 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
7010 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
7012 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
7014 /* don't enable SG, IP_CSUM and TSO by default - it might not work
7015 * properly for all devices */
7016 dev->features |= NETIF_F_RXCSUM |
7017 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
7019 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7020 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
7021 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7024 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
7025 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
7026 dev->hw_features &= ~NETIF_F_HW_VLAN_RX;
7028 dev->hw_features |= NETIF_F_RXALL;
7029 dev->hw_features |= NETIF_F_RXFCS;
7031 tp->hw_start = cfg->hw_start;
7032 tp->event_slow = cfg->event_slow;
7034 tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
7035 ~(RxBOVF | RxFOVF) : ~0;
7037 init_timer(&tp->timer);
7038 tp->timer.data = (unsigned long) dev;
7039 tp->timer.function = rtl8169_phy_timer;
7041 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
7043 rc = register_netdev(dev);
7047 pci_set_drvdata(pdev, dev);
7049 netif_info(tp, probe, dev, "%s at 0x%p, %pM, XID %08x IRQ %d\n",
7050 rtl_chip_infos[chipset].name, ioaddr, dev->dev_addr,
7051 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), pdev->irq);
7052 if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
7053 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
7054 "tx checksumming: %s]\n",
7055 rtl_chip_infos[chipset].jumbo_max,
7056 rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko");
7059 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
7060 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
7061 tp->mac_version == RTL_GIGA_MAC_VER_31) {
7062 rtl8168_driver_start(tp);
7065 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
7067 if (pci_dev_run_wake(pdev))
7068 pm_runtime_put_noidle(&pdev->dev);
7070 netif_carrier_off(dev);
7076 netif_napi_del(&tp->napi);
7077 rtl_disable_msi(pdev, tp);
7080 pci_release_regions(pdev);
7082 pci_clear_mwi(pdev);
7083 pci_disable_device(pdev);
7089 static struct pci_driver rtl8169_pci_driver = {
7091 .id_table = rtl8169_pci_tbl,
7092 .probe = rtl_init_one,
7093 .remove = rtl_remove_one,
7094 .shutdown = rtl_shutdown,
7095 .driver.pm = RTL8169_PM_OPS,
7098 module_pci_driver(rtl8169_pci_driver);