1 /* Renesas Ethernet AVB device driver
3 * Copyright (C) 2014-2015 Renesas Electronics Corporation
4 * Copyright (C) 2015 Renesas Solutions Corp.
5 * Copyright (C) 2015 Cogent Embedded, Inc. <source@cogentembedded.com>
7 * Based on the SuperH Ethernet driver
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms and conditions of the GNU General Public License version 2,
11 * as published by the Free Software Foundation.
17 #include <linux/interrupt.h>
19 #include <linux/kernel.h>
20 #include <linux/mdio-bitbang.h>
21 #include <linux/netdevice.h>
22 #include <linux/phy.h>
23 #include <linux/platform_device.h>
24 #include <linux/ptp_clock_kernel.h>
26 #define BE_TX_RING_SIZE 64 /* TX ring size for Best Effort */
27 #define BE_RX_RING_SIZE 1024 /* RX ring size for Best Effort */
28 #define NC_TX_RING_SIZE 64 /* TX ring size for Network Control */
29 #define NC_RX_RING_SIZE 64 /* RX ring size for Network Control */
30 #define BE_TX_RING_MIN 64
31 #define BE_RX_RING_MIN 64
32 #define BE_TX_RING_MAX 1024
33 #define BE_RX_RING_MAX 2048
35 #define PKT_BUF_SZ 1538
37 /* Driver's parameters */
38 #define RAVB_ALIGN 128
40 /* Hardware time stamp */
41 #define RAVB_TXTSTAMP_VALID 0x00000001 /* TX timestamp valid */
42 #define RAVB_TXTSTAMP_ENABLED 0x00000010 /* Enable TX timestamping */
44 #define RAVB_RXTSTAMP_VALID 0x00000001 /* RX timestamp valid */
45 #define RAVB_RXTSTAMP_TYPE 0x00000006 /* RX type mask */
46 #define RAVB_RXTSTAMP_TYPE_V2_L2_EVENT 0x00000002
47 #define RAVB_RXTSTAMP_TYPE_ALL 0x00000006
48 #define RAVB_RXTSTAMP_ENABLED 0x00000010 /* Enable RX timestamping */
51 /* AVB-DMAC registers */
169 GCPT = 0x03B4, /* Undocumented? */
174 /* E-MAC registers */
188 TROCR = 0x0700, /* Undocumented? */
189 CDCR = 0x0708, /* Undocumented? */
190 LCCR = 0x0710, /* Undocumented? */
196 CERCR = 0x0768, /* Undocumented? */
197 CEECR = 0x0770, /* Undocumented? */
202 /* Register bits of the Ethernet AVB */
205 CCC_OPC = 0x00000003,
206 CCC_OPC_RESET = 0x00000000,
207 CCC_OPC_CONFIG = 0x00000001,
208 CCC_OPC_OPERATION = 0x00000002,
209 CCC_DTSR = 0x00000100,
210 CCC_CSEL = 0x00030000,
211 CCC_CSEL_HPB = 0x00010000,
212 CCC_CSEL_ETH_TX = 0x00020000,
213 CCC_CSEL_GMII_REF = 0x00030000,
214 CCC_BOC = 0x00100000, /* Undocumented? */
215 CCC_LBME = 0x01000000,
220 CSR_OPS = 0x0000000F,
221 CSR_OPS_RESET = 0x00000001,
222 CSR_OPS_CONFIG = 0x00000002,
223 CSR_OPS_OPERATION = 0x00000004,
224 CSR_OPS_STANDBY = 0x00000008, /* Undocumented? */
225 CSR_DTS = 0x00000100,
226 CSR_TPO0 = 0x00010000,
227 CSR_TPO1 = 0x00020000,
228 CSR_TPO2 = 0x00040000,
229 CSR_TPO3 = 0x00080000,
230 CSR_RPO = 0x00100000,
235 ESR_EQN = 0x0000001F,
237 ESR_EIL = 0x00001000,
242 RCR_EFFS = 0x00000001,
243 RCR_ENCF = 0x00000002,
244 RCR_ESF = 0x0000000C,
245 RCR_ETS0 = 0x00000010,
246 RCR_ETS2 = 0x00000020,
247 RCR_RFCL = 0x1FFF0000,
252 RQC_RSM0 = 0x00000003,
253 RQC_UFCC0 = 0x00000030,
254 RQC_RSM1 = 0x00000300,
255 RQC_UFCC1 = 0x00003000,
256 RQC_RSM2 = 0x00030000,
257 RQC_UFCC2 = 0x00300000,
258 RQC_RSM3 = 0x03000000,
259 RQC_UFCC3 = 0x30000000,
264 RPC_PCNT = 0x00000700,
265 RPC_DCNT = 0x00FF0000,
270 UFCW_WL0 = 0x0000003F,
271 UFCW_WL1 = 0x00003F00,
272 UFCW_WL2 = 0x003F0000,
273 UFCW_WL3 = 0x3F000000,
278 UFCS_SL0 = 0x0000003F,
279 UFCS_SL1 = 0x00003F00,
280 UFCS_SL2 = 0x003F0000,
281 UFCS_SL3 = 0x3F000000,
286 UFCV_CV0 = 0x0000003F,
287 UFCV_CV1 = 0x00003F00,
288 UFCV_CV2 = 0x003F0000,
289 UFCV_CV3 = 0x3F000000,
294 UFCD_DV0 = 0x0000003F,
295 UFCD_DV1 = 0x00003F00,
296 UFCD_DV2 = 0x003F0000,
297 UFCD_DV3 = 0x3F000000,
302 SFO_FPB = 0x0000003F,
307 RTC_MFL0 = 0x00000FFF,
308 RTC_MFL1 = 0x0FFF0000,
313 TGC_TSM0 = 0x00000001,
314 TGC_TSM1 = 0x00000002,
315 TGC_TSM2 = 0x00000004,
316 TGC_TSM3 = 0x00000008,
317 TGC_TQP = 0x00000030,
318 TGC_TQP_NONAVB = 0x00000000,
319 TGC_TQP_AVBMODE1 = 0x00000010,
320 TGC_TQP_AVBMODE2 = 0x00000030,
321 TGC_TBD0 = 0x00000300,
322 TGC_TBD1 = 0x00003000,
323 TGC_TBD2 = 0x00030000,
324 TGC_TBD3 = 0x00300000,
329 TCCR_TSRQ0 = 0x00000001,
330 TCCR_TSRQ1 = 0x00000002,
331 TCCR_TSRQ2 = 0x00000004,
332 TCCR_TSRQ3 = 0x00000008,
333 TCCR_TFEN = 0x00000100,
334 TCCR_TFR = 0x00000200,
339 TSR_CCS0 = 0x00000003,
340 TSR_CCS1 = 0x0000000C,
341 TSR_TFFL = 0x00000700,
346 TFA2_TSV = 0x0000FFFF,
347 TFA2_TST = 0x03FF0000,
352 DIC_DPE1 = 0x00000002,
353 DIC_DPE2 = 0x00000004,
354 DIC_DPE3 = 0x00000008,
355 DIC_DPE4 = 0x00000010,
356 DIC_DPE5 = 0x00000020,
357 DIC_DPE6 = 0x00000040,
358 DIC_DPE7 = 0x00000080,
359 DIC_DPE8 = 0x00000100,
360 DIC_DPE9 = 0x00000200,
361 DIC_DPE10 = 0x00000400,
362 DIC_DPE11 = 0x00000800,
363 DIC_DPE12 = 0x00001000,
364 DIC_DPE13 = 0x00002000,
365 DIC_DPE14 = 0x00004000,
366 DIC_DPE15 = 0x00008000,
371 DIS_DPF1 = 0x00000002,
372 DIS_DPF2 = 0x00000004,
373 DIS_DPF3 = 0x00000008,
374 DIS_DPF4 = 0x00000010,
375 DIS_DPF5 = 0x00000020,
376 DIS_DPF6 = 0x00000040,
377 DIS_DPF7 = 0x00000080,
378 DIS_DPF8 = 0x00000100,
379 DIS_DPF9 = 0x00000200,
380 DIS_DPF10 = 0x00000400,
381 DIS_DPF11 = 0x00000800,
382 DIS_DPF12 = 0x00001000,
383 DIS_DPF13 = 0x00002000,
384 DIS_DPF14 = 0x00004000,
385 DIS_DPF15 = 0x00008000,
390 EIC_MREE = 0x00000001,
391 EIC_MTEE = 0x00000002,
392 EIC_QEE = 0x00000004,
393 EIC_SEE = 0x00000008,
394 EIC_CLLE0 = 0x00000010,
395 EIC_CLLE1 = 0x00000020,
396 EIC_CULE0 = 0x00000040,
397 EIC_CULE1 = 0x00000080,
398 EIC_TFFE = 0x00000100,
403 EIS_MREF = 0x00000001,
404 EIS_MTEF = 0x00000002,
405 EIS_QEF = 0x00000004,
406 EIS_SEF = 0x00000008,
407 EIS_CLLF0 = 0x00000010,
408 EIS_CLLF1 = 0x00000020,
409 EIS_CULF0 = 0x00000040,
410 EIS_CULF1 = 0x00000080,
411 EIS_TFFF = 0x00000100,
412 EIS_QFS = 0x00010000,
417 RIC0_FRE0 = 0x00000001,
418 RIC0_FRE1 = 0x00000002,
419 RIC0_FRE2 = 0x00000004,
420 RIC0_FRE3 = 0x00000008,
421 RIC0_FRE4 = 0x00000010,
422 RIC0_FRE5 = 0x00000020,
423 RIC0_FRE6 = 0x00000040,
424 RIC0_FRE7 = 0x00000080,
425 RIC0_FRE8 = 0x00000100,
426 RIC0_FRE9 = 0x00000200,
427 RIC0_FRE10 = 0x00000400,
428 RIC0_FRE11 = 0x00000800,
429 RIC0_FRE12 = 0x00001000,
430 RIC0_FRE13 = 0x00002000,
431 RIC0_FRE14 = 0x00004000,
432 RIC0_FRE15 = 0x00008000,
433 RIC0_FRE16 = 0x00010000,
434 RIC0_FRE17 = 0x00020000,
439 RIS0_FRF0 = 0x00000001,
440 RIS0_FRF1 = 0x00000002,
441 RIS0_FRF2 = 0x00000004,
442 RIS0_FRF3 = 0x00000008,
443 RIS0_FRF4 = 0x00000010,
444 RIS0_FRF5 = 0x00000020,
445 RIS0_FRF6 = 0x00000040,
446 RIS0_FRF7 = 0x00000080,
447 RIS0_FRF8 = 0x00000100,
448 RIS0_FRF9 = 0x00000200,
449 RIS0_FRF10 = 0x00000400,
450 RIS0_FRF11 = 0x00000800,
451 RIS0_FRF12 = 0x00001000,
452 RIS0_FRF13 = 0x00002000,
453 RIS0_FRF14 = 0x00004000,
454 RIS0_FRF15 = 0x00008000,
455 RIS0_FRF16 = 0x00010000,
456 RIS0_FRF17 = 0x00020000,
461 RIC1_RFWE = 0x80000000,
466 RIS1_RFWF = 0x80000000,
471 RIC2_QFE0 = 0x00000001,
472 RIC2_QFE1 = 0x00000002,
473 RIC2_QFE2 = 0x00000004,
474 RIC2_QFE3 = 0x00000008,
475 RIC2_QFE4 = 0x00000010,
476 RIC2_QFE5 = 0x00000020,
477 RIC2_QFE6 = 0x00000040,
478 RIC2_QFE7 = 0x00000080,
479 RIC2_QFE8 = 0x00000100,
480 RIC2_QFE9 = 0x00000200,
481 RIC2_QFE10 = 0x00000400,
482 RIC2_QFE11 = 0x00000800,
483 RIC2_QFE12 = 0x00001000,
484 RIC2_QFE13 = 0x00002000,
485 RIC2_QFE14 = 0x00004000,
486 RIC2_QFE15 = 0x00008000,
487 RIC2_QFE16 = 0x00010000,
488 RIC2_QFE17 = 0x00020000,
489 RIC2_RFFE = 0x80000000,
494 RIS2_QFF0 = 0x00000001,
495 RIS2_QFF1 = 0x00000002,
496 RIS2_QFF2 = 0x00000004,
497 RIS2_QFF3 = 0x00000008,
498 RIS2_QFF4 = 0x00000010,
499 RIS2_QFF5 = 0x00000020,
500 RIS2_QFF6 = 0x00000040,
501 RIS2_QFF7 = 0x00000080,
502 RIS2_QFF8 = 0x00000100,
503 RIS2_QFF9 = 0x00000200,
504 RIS2_QFF10 = 0x00000400,
505 RIS2_QFF11 = 0x00000800,
506 RIS2_QFF12 = 0x00001000,
507 RIS2_QFF13 = 0x00002000,
508 RIS2_QFF14 = 0x00004000,
509 RIS2_QFF15 = 0x00008000,
510 RIS2_QFF16 = 0x00010000,
511 RIS2_QFF17 = 0x00020000,
512 RIS2_RFFF = 0x80000000,
517 TIC_FTE0 = 0x00000001, /* Undocumented? */
518 TIC_FTE1 = 0x00000002, /* Undocumented? */
519 TIC_TFUE = 0x00000100,
520 TIC_TFWE = 0x00000200,
525 TIS_FTF0 = 0x00000001, /* Undocumented? */
526 TIS_FTF1 = 0x00000002, /* Undocumented? */
527 TIS_TFUF = 0x00000100,
528 TIS_TFWF = 0x00000200,
533 ISS_FRS = 0x00000001, /* Undocumented? */
534 ISS_FTS = 0x00000004, /* Undocumented? */
537 ISS_TFUS = 0x00000100,
538 ISS_TFWS = 0x00000200,
539 ISS_RFWS = 0x00001000,
540 ISS_CGIS = 0x00002000,
541 ISS_DPS1 = 0x00020000,
542 ISS_DPS2 = 0x00040000,
543 ISS_DPS3 = 0x00080000,
544 ISS_DPS4 = 0x00100000,
545 ISS_DPS5 = 0x00200000,
546 ISS_DPS6 = 0x00400000,
547 ISS_DPS7 = 0x00800000,
548 ISS_DPS8 = 0x01000000,
549 ISS_DPS9 = 0x02000000,
550 ISS_DPS10 = 0x04000000,
551 ISS_DPS11 = 0x08000000,
552 ISS_DPS12 = 0x10000000,
553 ISS_DPS13 = 0x20000000,
554 ISS_DPS14 = 0x40000000,
555 ISS_DPS15 = 0x80000000,
560 GCCR_TCR = 0x00000003,
561 GCCR_TCR_NOREQ = 0x00000000, /* No request */
562 GCCR_TCR_RESET = 0x00000001, /* gPTP/AVTP presentation timer reset */
563 GCCR_TCR_CAPTURE = 0x00000003, /* Capture value set in GCCR.TCSS */
564 GCCR_LTO = 0x00000004,
565 GCCR_LTI = 0x00000008,
566 GCCR_LPTC = 0x00000010,
567 GCCR_LMTT = 0x00000020,
568 GCCR_TCSS = 0x00000300,
569 GCCR_TCSS_GPTP = 0x00000000, /* gPTP timer value */
570 GCCR_TCSS_ADJGPTP = 0x00000100, /* Adjusted gPTP timer value */
571 GCCR_TCSS_AVTP = 0x00000200, /* AVTP presentation time value */
576 GTI_TIV = 0x0FFFFFFF,
581 GIC_PTCE = 0x00000001, /* Undocumented? */
582 GIC_PTME = 0x00000004,
587 GIS_PTCF = 0x00000001, /* Undocumented? */
588 GIS_PTMF = 0x00000004,
593 ECMR_PRM = 0x00000001,
594 ECMR_DM = 0x00000002,
595 ECMR_TE = 0x00000020,
596 ECMR_RE = 0x00000040,
597 ECMR_MPDE = 0x00000200,
598 ECMR_TXF = 0x00010000, /* Undocumented? */
599 ECMR_RXF = 0x00020000,
600 ECMR_PFR = 0x00040000,
601 ECMR_ZPF = 0x00080000, /* Undocumented? */
602 ECMR_RZPF = 0x00100000,
603 ECMR_DPAD = 0x00200000,
604 ECMR_RCSC = 0x00800000,
605 ECMR_TRCCM = 0x04000000,
610 ECSR_ICD = 0x00000001,
611 ECSR_MPD = 0x00000002,
612 ECSR_LCHNG = 0x00000004,
613 ECSR_PHYI = 0x00000008,
618 ECSIPR_ICDIP = 0x00000001,
619 ECSIPR_MPDIP = 0x00000002,
620 ECSIPR_LCHNGIP = 0x00000004, /* Undocumented? */
625 PIR_MDC = 0x00000001,
626 PIR_MMD = 0x00000002,
627 PIR_MDO = 0x00000004,
628 PIR_MDI = 0x00000008,
633 PSR_LMON = 0x00000001,
638 PIPR_PHYIP = 0x00000001,
648 GECMR_SPEED = 0x00000001,
649 GECMR_SPEED_100 = 0x00000000,
650 GECMR_SPEED_1000 = 0x00000001,
653 /* The Ethernet AVB descriptor definitions. */
655 __le16 ds; /* Descriptor size */
656 u8 cc; /* Content control MSBs (reserved) */
657 u8 die_dt; /* Descriptor interrupt enable and type */
658 __le32 dptr; /* Descriptor pointer */
661 #define DPTR_ALIGN 4 /* Required descriptor pointer alignment */
673 /* HW/SW arbitration */
682 struct ravb_rx_desc {
683 __le16 ds_cc; /* Descriptor size and content control LSBs */
684 u8 msc; /* MAC status code */
685 u8 die_dt; /* Descriptor interrupt enable and type */
686 __le32 dptr; /* Descpriptor pointer */
689 struct ravb_ex_rx_desc {
690 __le16 ds_cc; /* Descriptor size and content control lower bits */
691 u8 msc; /* MAC status code */
692 u8 die_dt; /* Descriptor interrupt enable and type */
693 __le32 dptr; /* Descpriptor pointer */
694 __le32 ts_n; /* Timestampe nsec */
695 __le32 ts_sl; /* Timestamp low */
696 __le16 ts_sh; /* Timestamp high */
697 __le16 res; /* Reserved bits */
701 RX_DS = 0x0fff, /* Data size */
702 RX_TR = 0x1000, /* Truncation indication */
703 RX_EI = 0x2000, /* Error indication */
704 RX_PS = 0xc000, /* Padding selection */
707 /* E-MAC status code */
709 MSC_CRC = 0x01, /* Frame CRC error */
710 MSC_RFE = 0x02, /* Frame reception error (flagged by PHY) */
711 MSC_RTSF = 0x04, /* Frame length error (frame too short) */
712 MSC_RTLF = 0x08, /* Frame length error (frame too long) */
713 MSC_FRE = 0x10, /* Fraction error (not a multiple of 8 bits) */
714 MSC_CRL = 0x20, /* Carrier lost */
715 MSC_CEEF = 0x40, /* Carrier extension error */
716 MSC_MC = 0x80, /* Multicast frame reception */
719 struct ravb_tx_desc {
720 __le16 ds_tagl; /* Descriptor size and frame tag LSBs */
721 u8 tagh_tsr; /* Frame tag MSBs and timestamp storage request bit */
722 u8 die_dt; /* Descriptor interrupt enable and type */
723 __le32 dptr; /* Descpriptor pointer */
726 enum TX_DS_TAGL_BIT {
727 TX_DS = 0x0fff, /* Data size */
728 TX_TAGL = 0xf000, /* Frame tag LSBs */
731 enum TX_TAGH_TSR_BIT {
732 TX_TAGH = 0x3f, /* Frame tag MSBs */
733 TX_TSR = 0x40, /* Timestamp storage request */
736 RAVB_BE = 0, /* Best Effort Queue */
737 RAVB_NC, /* Network Control Queue */
740 #define DBAT_ENTRY_NUM 22
741 #define RX_QUEUE_OFFSET 4
742 #define NUM_RX_QUEUE 2
743 #define NUM_TX_QUEUE 2
744 #define NUM_TX_DESC 2 /* TX descriptors per packet */
746 struct ravb_tstamp_skb {
747 struct list_head list;
752 struct ravb_ptp_perout {
761 struct ptp_clock *clock;
762 struct ptp_clock_info info;
766 struct ravb_ptp_perout perout[N_PER_OUT];
769 struct ravb_private {
770 struct net_device *ndev;
771 struct platform_device *pdev;
773 struct mdiobb_ctrl mdiobb;
774 u32 num_rx_ring[NUM_RX_QUEUE];
775 u32 num_tx_ring[NUM_TX_QUEUE];
777 dma_addr_t desc_bat_dma;
778 struct ravb_desc *desc_bat;
779 dma_addr_t rx_desc_dma[NUM_RX_QUEUE];
780 dma_addr_t tx_desc_dma[NUM_TX_QUEUE];
781 struct ravb_ex_rx_desc *rx_ring[NUM_RX_QUEUE];
782 struct ravb_tx_desc *tx_ring[NUM_TX_QUEUE];
783 void *tx_align[NUM_TX_QUEUE];
784 struct sk_buff **rx_skb[NUM_RX_QUEUE];
785 struct sk_buff **tx_skb[NUM_TX_QUEUE];
788 struct net_device_stats stats[NUM_RX_QUEUE];
791 struct list_head ts_skb_list;
794 spinlock_t lock; /* Register access lock */
795 u32 cur_rx[NUM_RX_QUEUE]; /* Consumer ring indices */
796 u32 dirty_rx[NUM_RX_QUEUE]; /* Producer ring indices */
797 u32 cur_tx[NUM_TX_QUEUE];
798 u32 dirty_tx[NUM_TX_QUEUE];
799 struct napi_struct napi[NUM_RX_QUEUE];
800 struct work_struct work;
801 /* MII transceiver section. */
802 struct mii_bus *mii_bus; /* MDIO bus control */
803 struct phy_device *phydev; /* PHY device control */
805 phy_interface_t phy_interface;
810 unsigned no_avb_link:1;
811 unsigned avb_link_active_low:1;
814 static inline u32 ravb_read(struct net_device *ndev, enum ravb_reg reg)
816 struct ravb_private *priv = netdev_priv(ndev);
818 return ioread32(priv->addr + reg);
821 static inline void ravb_write(struct net_device *ndev, u32 data,
824 struct ravb_private *priv = netdev_priv(ndev);
826 iowrite32(data, priv->addr + reg);
829 int ravb_wait(struct net_device *ndev, enum ravb_reg reg, u32 mask, u32 value);
831 irqreturn_t ravb_ptp_interrupt(struct net_device *ndev);
832 void ravb_ptp_init(struct net_device *ndev, struct platform_device *pdev);
833 void ravb_ptp_stop(struct net_device *ndev);
835 #endif /* #ifndef __RAVB_H__ */