drivers/net/ethernet/renesas/sh_eth.c

   1 /*
   2  *  SuperH Ethernet device driver
   3  *
   4  *  Copyright (C) 2006-2012 Nobuhiro Iwamatsu
   5  *  Copyright (C) 2008-2013 Renesas Solutions Corp.
   6  *  Copyright (C) 2013 Cogent Embedded, Inc.
   7  *
   8  *  This program is free software; you can redistribute it and/or modify it
   9  *  under the terms and conditions of the GNU General Public License,
  10  *  version 2, as published by the Free Software Foundation.
  11  *
  12  *  This program is distributed in the hope it will be useful, but WITHOUT
  13  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  *  more details.
  16  *  You should have received a copy of the GNU General Public License along with
  17  *  this program; if not, write to the Free Software Foundation, Inc.,
  18  *  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  19  *
  20  *  The full GNU General Public License is included in this distribution in
  21  *  the file called "COPYING".
  22  */
  23
  24 #include <linux/init.h>
  25 #include <linux/module.h>
  26 #include <linux/kernel.h>
  27 #include <linux/spinlock.h>
  28 #include <linux/interrupt.h>
  29 #include <linux/dma-mapping.h>
  30 #include <linux/etherdevice.h>
  31 #include <linux/delay.h>
  32 #include <linux/platform_device.h>
  33 #include <linux/mdio-bitbang.h>
  34 #include <linux/netdevice.h>
  35 #include <linux/phy.h>
  36 #include <linux/cache.h>
  37 #include <linux/io.h>
  38 #include <linux/pm_runtime.h>
  39 #include <linux/slab.h>
  40 #include <linux/ethtool.h>
  41 #include <linux/if_vlan.h>
  42 #include <linux/clk.h>
  43 #include <linux/sh_eth.h>
  44
  45 #include "sh_eth.h"
  46
  47 #define SH_ETH_DEF_MSG_ENABLE \
  48                 (NETIF_MSG_LINK | \
  49                 NETIF_MSG_TIMER | \
  50                 NETIF_MSG_RX_ERR| \
  51                 NETIF_MSG_TX_ERR)
  52
  53 static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
  54         [EDSR]          = 0x0000,
  55         [EDMR]          = 0x0400,
  56         [EDTRR]         = 0x0408,
  57         [EDRRR]         = 0x0410,
  58         [EESR]          = 0x0428,
  59         [EESIPR]        = 0x0430,
  60         [TDLAR]         = 0x0010,
  61         [TDFAR]         = 0x0014,
  62         [TDFXR]         = 0x0018,
  63         [TDFFR]         = 0x001c,
  64         [RDLAR]         = 0x0030,
  65         [RDFAR]         = 0x0034,
  66         [RDFXR]         = 0x0038,
  67         [RDFFR]         = 0x003c,
  68         [TRSCER]        = 0x0438,
  69         [RMFCR]         = 0x0440,
  70         [TFTR]          = 0x0448,
  71         [FDR]           = 0x0450,
  72         [RMCR]          = 0x0458,
  73         [RPADIR]        = 0x0460,
  74         [FCFTR]         = 0x0468,
  75         [CSMR]          = 0x04E4,
  76
  77         [ECMR]          = 0x0500,
  78         [ECSR]          = 0x0510,
  79         [ECSIPR]        = 0x0518,
  80         [PIR]           = 0x0520,
  81         [PSR]           = 0x0528,
  82         [PIPR]          = 0x052c,
  83         [RFLR]          = 0x0508,
  84         [APR]           = 0x0554,
  85         [MPR]           = 0x0558,
  86         [PFTCR]         = 0x055c,
  87         [PFRCR]         = 0x0560,
  88         [TPAUSER]       = 0x0564,
  89         [GECMR]         = 0x05b0,
  90         [BCULR]         = 0x05b4,
  91         [MAHR]          = 0x05c0,
  92         [MALR]          = 0x05c8,
  93         [TROCR]         = 0x0700,
  94         [CDCR]          = 0x0708,
  95         [LCCR]          = 0x0710,
  96         [CEFCR]         = 0x0740,
  97         [FRECR]         = 0x0748,
  98         [TSFRCR]        = 0x0750,
  99         [TLFRCR]        = 0x0758,
 100         [RFCR]          = 0x0760,
 101         [CERCR]         = 0x0768,
 102         [CEECR]         = 0x0770,
 103         [MAFCR]         = 0x0778,
 104         [RMII_MII]      = 0x0790,
 105
 106         [ARSTR]         = 0x0000,
 107         [TSU_CTRST]     = 0x0004,
 108         [TSU_FWEN0]     = 0x0010,
 109         [TSU_FWEN1]     = 0x0014,
 110         [TSU_FCM]       = 0x0018,
 111         [TSU_BSYSL0]    = 0x0020,
 112         [TSU_BSYSL1]    = 0x0024,
 113         [TSU_PRISL0]    = 0x0028,
 114         [TSU_PRISL1]    = 0x002c,
 115         [TSU_FWSL0]     = 0x0030,
 116         [TSU_FWSL1]     = 0x0034,
 117         [TSU_FWSLC]     = 0x0038,
 118         [TSU_QTAG0]     = 0x0040,
 119         [TSU_QTAG1]     = 0x0044,
 120         [TSU_FWSR]      = 0x0050,
 121         [TSU_FWINMK]    = 0x0054,
 122         [TSU_ADQT0]     = 0x0048,
 123         [TSU_ADQT1]     = 0x004c,
 124         [TSU_VTAG0]     = 0x0058,
 125         [TSU_VTAG1]     = 0x005c,
 126         [TSU_ADSBSY]    = 0x0060,
 127         [TSU_TEN]       = 0x0064,
 128         [TSU_POST1]     = 0x0070,
 129         [TSU_POST2]     = 0x0074,
 130         [TSU_POST3]     = 0x0078,
 131         [TSU_POST4]     = 0x007c,
 132         [TSU_ADRH0]     = 0x0100,
 133         [TSU_ADRL0]     = 0x0104,
 134         [TSU_ADRH31]    = 0x01f8,
 135         [TSU_ADRL31]    = 0x01fc,
 136
 137         [TXNLCR0]       = 0x0080,
 138         [TXALCR0]       = 0x0084,
 139         [RXNLCR0]       = 0x0088,
 140         [RXALCR0]       = 0x008c,
 141         [FWNLCR0]       = 0x0090,
 142         [FWALCR0]       = 0x0094,
 143         [TXNLCR1]       = 0x00a0,
 144         [TXALCR1]       = 0x00a0,
 145         [RXNLCR1]       = 0x00a8,
 146         [RXALCR1]       = 0x00ac,
 147         [FWNLCR1]       = 0x00b0,
 148         [FWALCR1]       = 0x00b4,
 149 };
 150
 151 static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = {
 152         [ECMR]          = 0x0300,
 153         [RFLR]          = 0x0308,
 154         [ECSR]          = 0x0310,
 155         [ECSIPR]        = 0x0318,
 156         [PIR]           = 0x0320,
 157         [PSR]           = 0x0328,
 158         [RDMLR]         = 0x0340,
 159         [IPGR]          = 0x0350,
 160         [APR]           = 0x0354,
 161         [MPR]           = 0x0358,
 162         [RFCF]          = 0x0360,
 163         [TPAUSER]       = 0x0364,
 164         [TPAUSECR]      = 0x0368,
 165         [MAHR]          = 0x03c0,
 166         [MALR]          = 0x03c8,
 167         [TROCR]         = 0x03d0,
 168         [CDCR]          = 0x03d4,
 169         [LCCR]          = 0x03d8,
 170         [CNDCR]         = 0x03dc,
 171         [CEFCR]         = 0x03e4,
 172         [FRECR]         = 0x03e8,
 173         [TSFRCR]        = 0x03ec,
 174         [TLFRCR]        = 0x03f0,
 175         [RFCR]          = 0x03f4,
 176         [MAFCR]         = 0x03f8,
 177
 178         [EDMR]          = 0x0200,
 179         [EDTRR]         = 0x0208,
 180         [EDRRR]         = 0x0210,
 181         [TDLAR]         = 0x0218,
 182         [RDLAR]         = 0x0220,
 183         [EESR]          = 0x0228,
 184         [EESIPR]        = 0x0230,
 185         [TRSCER]        = 0x0238,
 186         [RMFCR]         = 0x0240,
 187         [TFTR]          = 0x0248,
 188         [FDR]           = 0x0250,
 189         [RMCR]          = 0x0258,
 190         [TFUCR]         = 0x0264,
 191         [RFOCR]         = 0x0268,
 192         [FCFTR]         = 0x0270,
 193         [TRIMD]         = 0x027c,
 194 };
 195
 196 static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
 197         [ECMR]          = 0x0100,
 198         [RFLR]          = 0x0108,
 199         [ECSR]          = 0x0110,
 200         [ECSIPR]        = 0x0118,
 201         [PIR]           = 0x0120,
 202         [PSR]           = 0x0128,
 203         [RDMLR]         = 0x0140,
 204         [IPGR]          = 0x0150,
 205         [APR]           = 0x0154,
 206         [MPR]           = 0x0158,
 207         [TPAUSER]       = 0x0164,
 208         [RFCF]          = 0x0160,
 209         [TPAUSECR]      = 0x0168,
 210         [BCFRR]         = 0x016c,
 211         [MAHR]          = 0x01c0,
 212         [MALR]          = 0x01c8,
 213         [TROCR]         = 0x01d0,
 214         [CDCR]          = 0x01d4,
 215         [LCCR]          = 0x01d8,
 216         [CNDCR]         = 0x01dc,
 217         [CEFCR]         = 0x01e4,
 218         [FRECR]         = 0x01e8,
 219         [TSFRCR]        = 0x01ec,
 220         [TLFRCR]        = 0x01f0,
 221         [RFCR]          = 0x01f4,
 222         [MAFCR]         = 0x01f8,
 223         [RTRATE]        = 0x01fc,
 224
 225         [EDMR]          = 0x0000,
 226         [EDTRR]         = 0x0008,
 227         [EDRRR]         = 0x0010,
 228         [TDLAR]         = 0x0018,
 229         [RDLAR]         = 0x0020,
 230         [EESR]          = 0x0028,
 231         [EESIPR]        = 0x0030,
 232         [TRSCER]        = 0x0038,
 233         [RMFCR]         = 0x0040,
 234         [TFTR]          = 0x0048,
 235         [FDR]           = 0x0050,
 236         [RMCR]          = 0x0058,
 237         [TFUCR]         = 0x0064,
 238         [RFOCR]         = 0x0068,
 239         [FCFTR]         = 0x0070,
 240         [RPADIR]        = 0x0078,
 241         [TRIMD]         = 0x007c,
 242         [RBWAR]         = 0x00c8,
 243         [RDFAR]         = 0x00cc,
 244         [TBRAR]         = 0x00d4,
 245         [TDFAR]         = 0x00d8,
 246 };
 247
 248 static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
 249         [ECMR]          = 0x0160,
 250         [ECSR]          = 0x0164,
 251         [ECSIPR]        = 0x0168,
 252         [PIR]           = 0x016c,
 253         [MAHR]          = 0x0170,
 254         [MALR]          = 0x0174,
 255         [RFLR]          = 0x0178,
 256         [PSR]           = 0x017c,
 257         [TROCR]         = 0x0180,
 258         [CDCR]          = 0x0184,
 259         [LCCR]          = 0x0188,
 260         [CNDCR]         = 0x018c,
 261         [CEFCR]         = 0x0194,
 262         [FRECR]         = 0x0198,
 263         [TSFRCR]        = 0x019c,
 264         [TLFRCR]        = 0x01a0,
 265         [RFCR]          = 0x01a4,
 266         [MAFCR]         = 0x01a8,
 267         [IPGR]          = 0x01b4,
 268         [APR]           = 0x01b8,
 269         [MPR]           = 0x01bc,
 270         [TPAUSER]       = 0x01c4,
 271         [BCFR]          = 0x01cc,
 272
 273         [ARSTR]         = 0x0000,
 274         [TSU_CTRST]     = 0x0004,
 275         [TSU_FWEN0]     = 0x0010,
 276         [TSU_FWEN1]     = 0x0014,
 277         [TSU_FCM]       = 0x0018,
 278         [TSU_BSYSL0]    = 0x0020,
 279         [TSU_BSYSL1]    = 0x0024,
 280         [TSU_PRISL0]    = 0x0028,
 281         [TSU_PRISL1]    = 0x002c,
 282         [TSU_FWSL0]     = 0x0030,
 283         [TSU_FWSL1]     = 0x0034,
 284         [TSU_FWSLC]     = 0x0038,
 285         [TSU_QTAGM0]    = 0x0040,
 286         [TSU_QTAGM1]    = 0x0044,
 287         [TSU_ADQT0]     = 0x0048,
 288         [TSU_ADQT1]     = 0x004c,
 289         [TSU_FWSR]      = 0x0050,
 290         [TSU_FWINMK]    = 0x0054,
 291         [TSU_ADSBSY]    = 0x0060,
 292         [TSU_TEN]       = 0x0064,
 293         [TSU_POST1]     = 0x0070,
 294         [TSU_POST2]     = 0x0074,
 295         [TSU_POST3]     = 0x0078,
 296         [TSU_POST4]     = 0x007c,
 297
 298         [TXNLCR0]       = 0x0080,
 299         [TXALCR0]       = 0x0084,
 300         [RXNLCR0]       = 0x0088,
 301         [RXALCR0]       = 0x008c,
 302         [FWNLCR0]       = 0x0090,
 303         [FWALCR0]       = 0x0094,
 304         [TXNLCR1]       = 0x00a0,
 305         [TXALCR1]       = 0x00a0,
 306         [RXNLCR1]       = 0x00a8,
 307         [RXALCR1]       = 0x00ac,
 308         [FWNLCR1]       = 0x00b0,
 309         [FWALCR1]       = 0x00b4,
 310
 311         [TSU_ADRH0]     = 0x0100,
 312         [TSU_ADRL0]     = 0x0104,
 313         [TSU_ADRL31]    = 0x01fc,
 314 };
 315
 316 static int sh_eth_is_gether(struct sh_eth_private *mdp)
 317 {
 318         if (mdp->reg_offset == sh_eth_offset_gigabit)
 319                 return 1;
 320         else
 321                 return 0;
 322 }
 323
 324 static void sh_eth_select_mii(struct net_device *ndev)
 325 {
 326         u32 value = 0x0;
 327         struct sh_eth_private *mdp = netdev_priv(ndev);
 328
 329         switch (mdp->phy_interface) {
 330         case PHY_INTERFACE_MODE_GMII:
 331                 value = 0x2;
 332                 break;
 333         case PHY_INTERFACE_MODE_MII:
 334                 value = 0x1;
 335                 break;
 336         case PHY_INTERFACE_MODE_RMII:
 337                 value = 0x0;
 338                 break;
 339         default:
 340                 pr_warn("PHY interface mode was not setup. Set to MII.\n");
 341                 value = 0x1;
 342                 break;
 343         }
 344
 345         sh_eth_write(ndev, value, RMII_MII);
 346 }
 347
 348 static void sh_eth_set_duplex(struct net_device *ndev)
 349 {
 350         struct sh_eth_private *mdp = netdev_priv(ndev);
 351
 352         if (mdp->duplex) /* Full */
 353                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
 354         else            /* Half */
 355                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
 356 }
 357
 358 /* There is CPU dependent code */
 359 static void sh_eth_set_rate_r8a777x(struct net_device *ndev)
 360 {
 361         struct sh_eth_private *mdp = netdev_priv(ndev);
 362
 363         switch (mdp->speed) {
 364         case 10: /* 10BASE */
 365                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_ELB, ECMR);
 366                 break;
 367         case 100:/* 100BASE */
 368                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_ELB, ECMR);
 369                 break;
 370         default:
 371                 break;
 372         }
 373 }
 374
 375 /* R8A7778/9 */
 376 static struct sh_eth_cpu_data r8a777x_data = {
 377         .set_duplex     = sh_eth_set_duplex,
 378         .set_rate       = sh_eth_set_rate_r8a777x,
 379
 380         .ecsr_value     = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
 381         .ecsipr_value   = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
 382         .eesipr_value   = 0x01ff009f,
 383
 384         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
 385         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE |
 386                           EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI,
 387
 388         .apr            = 1,
 389         .mpr            = 1,
 390         .tpauser        = 1,
 391         .hw_swap        = 1,
 392 };
 393
 394 static void sh_eth_set_rate_sh7724(struct net_device *ndev)
 395 {
 396         struct sh_eth_private *mdp = netdev_priv(ndev);
 397
 398         switch (mdp->speed) {
 399         case 10: /* 10BASE */
 400                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_RTM, ECMR);
 401                 break;
 402         case 100:/* 100BASE */
 403                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_RTM, ECMR);
 404                 break;
 405         default:
 406                 break;
 407         }
 408 }
 409
 410 /* SH7724 */
 411 static struct sh_eth_cpu_data sh7724_data = {
 412         .set_duplex     = sh_eth_set_duplex,
 413         .set_rate       = sh_eth_set_rate_sh7724,
 414
 415         .ecsr_value     = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
 416         .ecsipr_value   = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
 417         .eesipr_value   = 0x01ff009f,
 418
 419         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
 420         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE |
 421                           EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI,
 422
 423         .apr            = 1,
 424         .mpr            = 1,
 425         .tpauser        = 1,
 426         .hw_swap        = 1,
 427         .rpadir         = 1,
 428         .rpadir_value   = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
 429 };
 430
 431 static void sh_eth_set_rate_sh7757(struct net_device *ndev)
 432 {
 433         struct sh_eth_private *mdp = netdev_priv(ndev);
 434
 435         switch (mdp->speed) {
 436         case 10: /* 10BASE */
 437                 sh_eth_write(ndev, 0, RTRATE);
 438                 break;
 439         case 100:/* 100BASE */
 440                 sh_eth_write(ndev, 1, RTRATE);
 441                 break;
 442         default:
 443                 break;
 444         }
 445 }
 446
 447 /* SH7757 */
 448 static struct sh_eth_cpu_data sh7757_data = {
 449         .set_duplex     = sh_eth_set_duplex,
 450         .set_rate       = sh_eth_set_rate_sh7757,
 451
 452         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 453         .rmcr_value     = 0x00000001,
 454
 455         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
 456         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE |
 457                           EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI,
 458
 459         .irq_flags      = IRQF_SHARED,
 460         .apr            = 1,
 461         .mpr            = 1,
 462         .tpauser        = 1,
 463         .hw_swap        = 1,
 464         .no_ade         = 1,
 465         .rpadir         = 1,
 466         .rpadir_value   = 2 << 16,
 467 };
 468
 469 #define SH_GIGA_ETH_BASE        0xfee00000UL
 470 #define GIGA_MALR(port)         (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
 471 #define GIGA_MAHR(port)         (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
 472 static void sh_eth_chip_reset_giga(struct net_device *ndev)
 473 {
 474         int i;
 475         unsigned long mahr[2], malr[2];
 476
 477         /* save MAHR and MALR */
 478         for (i = 0; i < 2; i++) {
 479                 malr[i] = ioread32((void *)GIGA_MALR(i));
 480                 mahr[i] = ioread32((void *)GIGA_MAHR(i));
 481         }
 482
 483         /* reset device */
 484         iowrite32(ARSTR_ARSTR, (void *)(SH_GIGA_ETH_BASE + 0x1800));
 485         mdelay(1);
 486
 487         /* restore MAHR and MALR */
 488         for (i = 0; i < 2; i++) {
 489                 iowrite32(malr[i], (void *)GIGA_MALR(i));
 490                 iowrite32(mahr[i], (void *)GIGA_MAHR(i));
 491         }
 492 }
 493
 494 static void sh_eth_set_rate_giga(struct net_device *ndev)
 495 {
 496         struct sh_eth_private *mdp = netdev_priv(ndev);
 497
 498         switch (mdp->speed) {
 499         case 10: /* 10BASE */
 500                 sh_eth_write(ndev, 0x00000000, GECMR);
 501                 break;
 502         case 100:/* 100BASE */
 503                 sh_eth_write(ndev, 0x00000010, GECMR);
 504                 break;
 505         case 1000: /* 1000BASE */
 506                 sh_eth_write(ndev, 0x00000020, GECMR);
 507                 break;
 508         default:
 509                 break;
 510         }
 511 }
 512
 513 /* SH7757(GETHERC) */
 514 static struct sh_eth_cpu_data sh7757_data_giga = {
 515         .chip_reset     = sh_eth_chip_reset_giga,
 516         .set_duplex     = sh_eth_set_duplex,
 517         .set_rate       = sh_eth_set_rate_giga,
 518
 519         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 520         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 521         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 522
 523         .tx_check       = EESR_TC1 | EESR_FTC,
 524         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \
 525                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \
 526                           EESR_ECI,
 527         .fdr_value      = 0x0000072f,
 528         .rmcr_value     = 0x00000001,
 529
 530         .irq_flags      = IRQF_SHARED,
 531         .apr            = 1,
 532         .mpr            = 1,
 533         .tpauser        = 1,
 534         .bculr          = 1,
 535         .hw_swap        = 1,
 536         .rpadir         = 1,
 537         .rpadir_value   = 2 << 16,
 538         .no_trimd       = 1,
 539         .no_ade         = 1,
 540         .tsu            = 1,
 541 };
 542
 543 static void sh_eth_chip_reset(struct net_device *ndev)
 544 {
 545         struct sh_eth_private *mdp = netdev_priv(ndev);
 546
 547         /* reset device */
 548         sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
 549         mdelay(1);
 550 }
 551
 552 static void sh_eth_set_rate_gether(struct net_device *ndev)
 553 {
 554         struct sh_eth_private *mdp = netdev_priv(ndev);
 555
 556         switch (mdp->speed) {
 557         case 10: /* 10BASE */
 558                 sh_eth_write(ndev, GECMR_10, GECMR);
 559                 break;
 560         case 100:/* 100BASE */
 561                 sh_eth_write(ndev, GECMR_100, GECMR);
 562                 break;
 563         case 1000: /* 1000BASE */
 564                 sh_eth_write(ndev, GECMR_1000, GECMR);
 565                 break;
 566         default:
 567                 break;
 568         }
 569 }
 570
 571 /* SH7734 */
 572 static struct sh_eth_cpu_data sh7734_data = {
 573         .chip_reset     = sh_eth_chip_reset,
 574         .set_duplex     = sh_eth_set_duplex,
 575         .set_rate       = sh_eth_set_rate_gether,
 576
 577         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 578         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 579         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 580
 581         .tx_check       = EESR_TC1 | EESR_FTC,
 582         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \
 583                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \
 584                           EESR_ECI,
 585
 586         .apr            = 1,
 587         .mpr            = 1,
 588         .tpauser        = 1,
 589         .bculr          = 1,
 590         .hw_swap        = 1,
 591         .no_trimd       = 1,
 592         .no_ade         = 1,
 593         .tsu            = 1,
 594         .hw_crc         = 1,
 595         .select_mii     = 1,
 596 };
 597
 598 /* SH7763 */
 599 static struct sh_eth_cpu_data sh7763_data = {
 600         .chip_reset     = sh_eth_chip_reset,
 601         .set_duplex     = sh_eth_set_duplex,
 602         .set_rate       = sh_eth_set_rate_gether,
 603
 604         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 605         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 606         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 607
 608         .tx_check       = EESR_TC1 | EESR_FTC,
 609         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \
 610                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \
 611                           EESR_ECI,
 612
 613         .apr            = 1,
 614         .mpr            = 1,
 615         .tpauser        = 1,
 616         .bculr          = 1,
 617         .hw_swap        = 1,
 618         .no_trimd       = 1,
 619         .no_ade         = 1,
 620         .tsu            = 1,
 621         .irq_flags      = IRQF_SHARED,
 622 };
 623
 624 static void sh_eth_chip_reset_r8a7740(struct net_device *ndev)
 625 {
 626         struct sh_eth_private *mdp = netdev_priv(ndev);
 627
 628         /* reset device */
 629         sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
 630         mdelay(1);
 631
 632         sh_eth_select_mii(ndev);
 633 }
 634
 635 /* R8A7740 */
 636 static struct sh_eth_cpu_data r8a7740_data = {
 637         .chip_reset     = sh_eth_chip_reset_r8a7740,
 638         .set_duplex     = sh_eth_set_duplex,
 639         .set_rate       = sh_eth_set_rate_gether,
 640
 641         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 642         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 643         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 644
 645         .tx_check       = EESR_TC1 | EESR_FTC,
 646         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \
 647                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \
 648                           EESR_ECI,
 649
 650         .apr            = 1,
 651         .mpr            = 1,
 652         .tpauser        = 1,
 653         .bculr          = 1,
 654         .hw_swap        = 1,
 655         .no_trimd       = 1,
 656         .no_ade         = 1,
 657         .tsu            = 1,
 658         .select_mii     = 1,
 659 };
 660
 661 static struct sh_eth_cpu_data sh7619_data = {
 662         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 663
 664         .apr            = 1,
 665         .mpr            = 1,
 666         .tpauser        = 1,
 667         .hw_swap        = 1,
 668 };
 669
 670 static struct sh_eth_cpu_data sh771x_data = {
 671         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 672         .tsu            = 1,
 673 };
 674
 675 static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
 676 {
 677         if (!cd->ecsr_value)
 678                 cd->ecsr_value = DEFAULT_ECSR_INIT;
 679
 680         if (!cd->ecsipr_value)
 681                 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
 682
 683         if (!cd->fcftr_value)
 684                 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF | \
 685                                   DEFAULT_FIFO_F_D_RFD;
 686
 687         if (!cd->fdr_value)
 688                 cd->fdr_value = DEFAULT_FDR_INIT;
 689
 690         if (!cd->rmcr_value)
 691                 cd->rmcr_value = DEFAULT_RMCR_VALUE;
 692
 693         if (!cd->tx_check)
 694                 cd->tx_check = DEFAULT_TX_CHECK;
 695
 696         if (!cd->eesr_err_check)
 697                 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
 698 }
 699
 700 static int sh_eth_check_reset(struct net_device *ndev)
 701 {
 702         int ret = 0;
 703         int cnt = 100;
 704
 705         while (cnt > 0) {
 706                 if (!(sh_eth_read(ndev, EDMR) & 0x3))
 707                         break;
 708                 mdelay(1);
 709                 cnt--;
 710         }
 711         if (cnt <= 0) {
 712                 pr_err("Device reset failed\n");
 713                 ret = -ETIMEDOUT;
 714         }
 715         return ret;
 716 }
 717
 718 static int sh_eth_reset(struct net_device *ndev)
 719 {
 720         struct sh_eth_private *mdp = netdev_priv(ndev);
 721         int ret = 0;
 722
 723         if (sh_eth_is_gether(mdp)) {
 724                 sh_eth_write(ndev, EDSR_ENALL, EDSR);
 725                 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER,
 726                              EDMR);
 727
 728                 ret = sh_eth_check_reset(ndev);
 729                 if (ret)
 730                         goto out;
 731
 732                 /* Table Init */
 733                 sh_eth_write(ndev, 0x0, TDLAR);
 734                 sh_eth_write(ndev, 0x0, TDFAR);
 735                 sh_eth_write(ndev, 0x0, TDFXR);
 736                 sh_eth_write(ndev, 0x0, TDFFR);
 737                 sh_eth_write(ndev, 0x0, RDLAR);
 738                 sh_eth_write(ndev, 0x0, RDFAR);
 739                 sh_eth_write(ndev, 0x0, RDFXR);
 740                 sh_eth_write(ndev, 0x0, RDFFR);
 741
 742                 /* Reset HW CRC register */
 743                 if (mdp->cd->hw_crc)
 744                         sh_eth_write(ndev, 0x0, CSMR);
 745
 746                 /* Select MII mode */
 747                 if (mdp->cd->select_mii)
 748                         sh_eth_select_mii(ndev);
 749         } else {
 750                 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER,
 751                              EDMR);
 752                 mdelay(3);
 753                 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER,
 754                              EDMR);
 755         }
 756
 757 out:
 758         return ret;
 759 }
 760
 761 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
 762 static void sh_eth_set_receive_align(struct sk_buff *skb)
 763 {
 764         int reserve;
 765
 766         reserve = SH4_SKB_RX_ALIGN - ((u32)skb->data & (SH4_SKB_RX_ALIGN - 1));
 767         if (reserve)
 768                 skb_reserve(skb, reserve);
 769 }
 770 #else
 771 static void sh_eth_set_receive_align(struct sk_buff *skb)
 772 {
 773         skb_reserve(skb, SH2_SH3_SKB_RX_ALIGN);
 774 }
 775 #endif
 776
 777
 778 /* CPU <-> EDMAC endian convert */
 779 static inline __u32 cpu_to_edmac(struct sh_eth_private *mdp, u32 x)
 780 {
 781         switch (mdp->edmac_endian) {
 782         case EDMAC_LITTLE_ENDIAN:
 783                 return cpu_to_le32(x);
 784         case EDMAC_BIG_ENDIAN:
 785                 return cpu_to_be32(x);
 786         }
 787         return x;
 788 }
 789
 790 static inline __u32 edmac_to_cpu(struct sh_eth_private *mdp, u32 x)
 791 {
 792         switch (mdp->edmac_endian) {
 793         case EDMAC_LITTLE_ENDIAN:
 794                 return le32_to_cpu(x);
 795         case EDMAC_BIG_ENDIAN:
 796                 return be32_to_cpu(x);
 797         }
 798         return x;
 799 }
 800
 801 /*
 802  * Program the hardware MAC address from dev->dev_addr.
 803  */
 804 static void update_mac_address(struct net_device *ndev)
 805 {
 806         sh_eth_write(ndev,
 807                 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
 808                 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
 809         sh_eth_write(ndev,
 810                 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
 811 }
 812
 813 /*
 814  * Get MAC address from SuperH MAC address register
 815  *
 816  * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
 817  * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
 818  * When you want use this device, you must set MAC address in bootloader.
 819  *
 820  */
 821 static void read_mac_address(struct net_device *ndev, unsigned char *mac)
 822 {
 823         if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
 824                 memcpy(ndev->dev_addr, mac, 6);
 825         } else {
 826                 ndev->dev_addr[0] = (sh_eth_read(ndev, MAHR) >> 24);
 827                 ndev->dev_addr[1] = (sh_eth_read(ndev, MAHR) >> 16) & 0xFF;
 828                 ndev->dev_addr[2] = (sh_eth_read(ndev, MAHR) >> 8) & 0xFF;
 829                 ndev->dev_addr[3] = (sh_eth_read(ndev, MAHR) & 0xFF);
 830                 ndev->dev_addr[4] = (sh_eth_read(ndev, MALR) >> 8) & 0xFF;
 831                 ndev->dev_addr[5] = (sh_eth_read(ndev, MALR) & 0xFF);
 832         }
 833 }
 834
 835 static unsigned long sh_eth_get_edtrr_trns(struct sh_eth_private *mdp)
 836 {
 837         if (sh_eth_is_gether(mdp))
 838                 return EDTRR_TRNS_GETHER;
 839         else
 840                 return EDTRR_TRNS_ETHER;
 841 }
 842
 843 struct bb_info {
 844         void (*set_gate)(void *addr);
 845         struct mdiobb_ctrl ctrl;
 846         void *addr;
 847         u32 mmd_msk;/* MMD */
 848         u32 mdo_msk;
 849         u32 mdi_msk;
 850         u32 mdc_msk;
 851 };
 852
 853 /* PHY bit set */
 854 static void bb_set(void *addr, u32 msk)
 855 {
 856         iowrite32(ioread32(addr) | msk, addr);
 857 }
 858
 859 /* PHY bit clear */
 860 static void bb_clr(void *addr, u32 msk)
 861 {
 862         iowrite32((ioread32(addr) & ~msk), addr);
 863 }
 864
 865 /* PHY bit read */
 866 static int bb_read(void *addr, u32 msk)
 867 {
 868         return (ioread32(addr) & msk) != 0;
 869 }
 870
 871 /* Data I/O pin control */
 872 static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
 873 {
 874         struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
 875
 876         if (bitbang->set_gate)
 877                 bitbang->set_gate(bitbang->addr);
 878
 879         if (bit)
 880                 bb_set(bitbang->addr, bitbang->mmd_msk);
 881         else
 882                 bb_clr(bitbang->addr, bitbang->mmd_msk);
 883 }
 884
 885 /* Set bit data*/
 886 static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
 887 {
 888         struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
 889
 890         if (bitbang->set_gate)
 891                 bitbang->set_gate(bitbang->addr);
 892
 893         if (bit)
 894                 bb_set(bitbang->addr, bitbang->mdo_msk);
 895         else
 896                 bb_clr(bitbang->addr, bitbang->mdo_msk);
 897 }
 898
 899 /* Get bit data*/
 900 static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
 901 {
 902         struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
 903
 904         if (bitbang->set_gate)
 905                 bitbang->set_gate(bitbang->addr);
 906
 907         return bb_read(bitbang->addr, bitbang->mdi_msk);
 908 }
 909
 910 /* MDC pin control */
 911 static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
 912 {
 913         struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
 914
 915         if (bitbang->set_gate)
 916                 bitbang->set_gate(bitbang->addr);
 917
 918         if (bit)
 919                 bb_set(bitbang->addr, bitbang->mdc_msk);
 920         else
 921                 bb_clr(bitbang->addr, bitbang->mdc_msk);
 922 }
 923
 924 /* mdio bus control struct */
 925 static struct mdiobb_ops bb_ops = {
 926         .owner = THIS_MODULE,
 927         .set_mdc = sh_mdc_ctrl,
 928         .set_mdio_dir = sh_mmd_ctrl,
 929         .set_mdio_data = sh_set_mdio,
 930         .get_mdio_data = sh_get_mdio,
 931 };
 932
 933 /* free skb and descriptor buffer */
 934 static void sh_eth_ring_free(struct net_device *ndev)
 935 {
 936         struct sh_eth_private *mdp = netdev_priv(ndev);
 937         int i;
 938
 939         /* Free Rx skb ringbuffer */
 940         if (mdp->rx_skbuff) {
 941                 for (i = 0; i < mdp->num_rx_ring; i++) {
 942                         if (mdp->rx_skbuff[i])
 943                                 dev_kfree_skb(mdp->rx_skbuff[i]);
 944                 }
 945         }
 946         kfree(mdp->rx_skbuff);
 947         mdp->rx_skbuff = NULL;
 948
 949         /* Free Tx skb ringbuffer */
 950         if (mdp->tx_skbuff) {
 951                 for (i = 0; i < mdp->num_tx_ring; i++) {
 952                         if (mdp->tx_skbuff[i])
 953                                 dev_kfree_skb(mdp->tx_skbuff[i]);
 954                 }
 955         }
 956         kfree(mdp->tx_skbuff);
 957         mdp->tx_skbuff = NULL;
 958 }
 959
 960 /* format skb and descriptor buffer */
 961 static void sh_eth_ring_format(struct net_device *ndev)
 962 {
 963         struct sh_eth_private *mdp = netdev_priv(ndev);
 964         int i;
 965         struct sk_buff *skb;
 966         struct sh_eth_rxdesc *rxdesc = NULL;
 967         struct sh_eth_txdesc *txdesc = NULL;
 968         int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring;
 969         int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring;
 970
 971         mdp->cur_rx = mdp->cur_tx = 0;
 972         mdp->dirty_rx = mdp->dirty_tx = 0;
 973
 974         memset(mdp->rx_ring, 0, rx_ringsize);
 975
 976         /* build Rx ring buffer */
 977         for (i = 0; i < mdp->num_rx_ring; i++) {
 978                 /* skb */
 979                 mdp->rx_skbuff[i] = NULL;
 980                 skb = netdev_alloc_skb(ndev, mdp->rx_buf_sz);
 981                 mdp->rx_skbuff[i] = skb;
 982                 if (skb == NULL)
 983                         break;
 984                 dma_map_single(&ndev->dev, skb->data, mdp->rx_buf_sz,
 985                                 DMA_FROM_DEVICE);
 986                 sh_eth_set_receive_align(skb);
 987
 988                 /* RX descriptor */
 989                 rxdesc = &mdp->rx_ring[i];
 990                 rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
 991                 rxdesc->status = cpu_to_edmac(mdp, RD_RACT | RD_RFP);
 992
 993                 /* The size of the buffer is 16 byte boundary. */
 994                 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
 995                 /* Rx descriptor address set */
 996                 if (i == 0) {
 997                         sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
 998                         if (sh_eth_is_gether(mdp))
 999                                 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
1000                 }
1001         }
1002
1003         mdp->dirty_rx = (u32) (i - mdp->num_rx_ring);
1004
1005         /* Mark the last entry as wrapping the ring. */
1006         rxdesc->status |= cpu_to_edmac(mdp, RD_RDEL);
1007
1008         memset(mdp->tx_ring, 0, tx_ringsize);
1009
1010         /* build Tx ring buffer */
1011         for (i = 0; i < mdp->num_tx_ring; i++) {
1012                 mdp->tx_skbuff[i] = NULL;
1013                 txdesc = &mdp->tx_ring[i];
1014                 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
1015                 txdesc->buffer_length = 0;
1016                 if (i == 0) {
1017                         /* Tx descriptor address set */
1018                         sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
1019                         if (sh_eth_is_gether(mdp))
1020                                 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
1021                 }
1022         }
1023
1024         txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
1025 }
1026
1027 /* Get skb and descriptor buffer */
1028 static int sh_eth_ring_init(struct net_device *ndev)
1029 {
1030         struct sh_eth_private *mdp = netdev_priv(ndev);
1031         int rx_ringsize, tx_ringsize, ret = 0;
1032
1033         /*
1034          * +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
1035          * card needs room to do 8 byte alignment, +2 so we can reserve
1036          * the first 2 bytes, and +16 gets room for the status word from the
1037          * card.
1038          */
1039         mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
1040                           (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
1041         if (mdp->cd->rpadir)
1042                 mdp->rx_buf_sz += NET_IP_ALIGN;
1043
1044         /* Allocate RX and TX skb rings */
1045         mdp->rx_skbuff = kmalloc_array(mdp->num_rx_ring,
1046                                        sizeof(*mdp->rx_skbuff), GFP_KERNEL);
1047         if (!mdp->rx_skbuff) {
1048                 ret = -ENOMEM;
1049                 return ret;
1050         }
1051
1052         mdp->tx_skbuff = kmalloc_array(mdp->num_tx_ring,
1053                                        sizeof(*mdp->tx_skbuff), GFP_KERNEL);
1054         if (!mdp->tx_skbuff) {
1055                 ret = -ENOMEM;
1056                 goto skb_ring_free;
1057         }
1058
1059         /* Allocate all Rx descriptors. */
1060         rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1061         mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma,
1062                                           GFP_KERNEL);
1063         if (!mdp->rx_ring) {
1064                 ret = -ENOMEM;
1065                 goto desc_ring_free;
1066         }
1067
1068         mdp->dirty_rx = 0;
1069
1070         /* Allocate all Tx descriptors. */
1071         tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1072         mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma,
1073                                           GFP_KERNEL);
1074         if (!mdp->tx_ring) {
1075                 ret = -ENOMEM;
1076                 goto desc_ring_free;
1077         }
1078         return ret;
1079
1080 desc_ring_free:
1081         /* free DMA buffer */
1082         dma_free_coherent(NULL, rx_ringsize, mdp->rx_ring, mdp->rx_desc_dma);
1083
1084 skb_ring_free:
1085         /* Free Rx and Tx skb ring buffer */
1086         sh_eth_ring_free(ndev);
1087         mdp->tx_ring = NULL;
1088         mdp->rx_ring = NULL;
1089
1090         return ret;
1091 }
1092
1093 static void sh_eth_free_dma_buffer(struct sh_eth_private *mdp)
1094 {
1095         int ringsize;
1096
1097         if (mdp->rx_ring) {
1098                 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1099                 dma_free_coherent(NULL, ringsize, mdp->rx_ring,
1100                                   mdp->rx_desc_dma);
1101                 mdp->rx_ring = NULL;
1102         }
1103
1104         if (mdp->tx_ring) {
1105                 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1106                 dma_free_coherent(NULL, ringsize, mdp->tx_ring,
1107                                   mdp->tx_desc_dma);
1108                 mdp->tx_ring = NULL;
1109         }
1110 }
1111
1112 static int sh_eth_dev_init(struct net_device *ndev, bool start)
1113 {
1114         int ret = 0;
1115         struct sh_eth_private *mdp = netdev_priv(ndev);
1116         u32 val;
1117
1118         /* Soft Reset */
1119         ret = sh_eth_reset(ndev);
1120         if (ret)
1121                 goto out;
1122
1123         /* Descriptor format */
1124         sh_eth_ring_format(ndev);
1125         if (mdp->cd->rpadir)
1126                 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR);
1127
1128         /* all sh_eth int mask */
1129         sh_eth_write(ndev, 0, EESIPR);
1130
1131 #if defined(__LITTLE_ENDIAN)
1132         if (mdp->cd->hw_swap)
1133                 sh_eth_write(ndev, EDMR_EL, EDMR);
1134         else
1135 #endif
1136                 sh_eth_write(ndev, 0, EDMR);
1137
1138         /* FIFO size set */
1139         sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
1140         sh_eth_write(ndev, 0, TFTR);
1141
1142         /* Frame recv control */
1143         sh_eth_write(ndev, mdp->cd->rmcr_value, RMCR);
1144
1145         sh_eth_write(ndev, DESC_I_RINT8 | DESC_I_RINT5 | DESC_I_TINT2, TRSCER);
1146
1147         if (mdp->cd->bculr)
1148                 sh_eth_write(ndev, 0x800, BCULR);       /* Burst sycle set */
1149
1150         sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
1151
1152         if (!mdp->cd->no_trimd)
1153                 sh_eth_write(ndev, 0, TRIMD);
1154
1155         /* Recv frame limit set register */
1156         sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN,
1157                      RFLR);
1158
1159         sh_eth_write(ndev, sh_eth_read(ndev, EESR), EESR);
1160         if (start)
1161                 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1162
1163         /* PAUSE Prohibition */
1164         val = (sh_eth_read(ndev, ECMR) & ECMR_DM) |
1165                 ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE;
1166
1167         sh_eth_write(ndev, val, ECMR);
1168
1169         if (mdp->cd->set_rate)
1170                 mdp->cd->set_rate(ndev);
1171
1172         /* E-MAC Status Register clear */
1173         sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
1174
1175         /* E-MAC Interrupt Enable register */
1176         if (start)
1177                 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
1178
1179         /* Set MAC address */
1180         update_mac_address(ndev);
1181
1182         /* mask reset */
1183         if (mdp->cd->apr)
1184                 sh_eth_write(ndev, APR_AP, APR);
1185         if (mdp->cd->mpr)
1186                 sh_eth_write(ndev, MPR_MP, MPR);
1187         if (mdp->cd->tpauser)
1188                 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
1189
1190         if (start) {
1191                 /* Setting the Rx mode will start the Rx process. */
1192                 sh_eth_write(ndev, EDRRR_R, EDRRR);
1193
1194                 netif_start_queue(ndev);
1195         }
1196
1197 out:
1198         return ret;
1199 }
1200
1201 /* free Tx skb function */
1202 static int sh_eth_txfree(struct net_device *ndev)
1203 {
1204         struct sh_eth_private *mdp = netdev_priv(ndev);
1205         struct sh_eth_txdesc *txdesc;
1206         int freeNum = 0;
1207         int entry = 0;
1208
1209         for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
1210                 entry = mdp->dirty_tx % mdp->num_tx_ring;
1211                 txdesc = &mdp->tx_ring[entry];
1212                 if (txdesc->status & cpu_to_edmac(mdp, TD_TACT))
1213                         break;
1214                 /* Free the original skb. */
1215                 if (mdp->tx_skbuff[entry]) {
1216                         dma_unmap_single(&ndev->dev, txdesc->addr,
1217                                          txdesc->buffer_length, DMA_TO_DEVICE);
1218                         dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
1219                         mdp->tx_skbuff[entry] = NULL;
1220                         freeNum++;
1221                 }
1222                 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
1223                 if (entry >= mdp->num_tx_ring - 1)
1224                         txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
1225
1226                 ndev->stats.tx_packets++;
1227                 ndev->stats.tx_bytes += txdesc->buffer_length;
1228         }
1229         return freeNum;
1230 }
1231
1232 /* Packet receive function */
1233 static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota)
1234 {
1235         struct sh_eth_private *mdp = netdev_priv(ndev);
1236         struct sh_eth_rxdesc *rxdesc;
1237
1238         int entry = mdp->cur_rx % mdp->num_rx_ring;
1239         int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx;
1240         struct sk_buff *skb;
1241         int exceeded = 0;
1242         u16 pkt_len = 0;
1243         u32 desc_status;
1244
1245         rxdesc = &mdp->rx_ring[entry];
1246         while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT))) {
1247                 desc_status = edmac_to_cpu(mdp, rxdesc->status);
1248                 pkt_len = rxdesc->frame_length;
1249
1250                 if (--boguscnt < 0)
1251                         break;
1252
1253                 if (*quota <= 0) {
1254                         exceeded = 1;
1255                         break;
1256                 }
1257                 (*quota)--;
1258
1259                 if (!(desc_status & RDFEND))
1260                         ndev->stats.rx_length_errors++;
1261
1262 #if defined(CONFIG_ARCH_R8A7740)
1263                 /*
1264                  * In case of almost all GETHER/ETHERs, the Receive Frame State
1265                  * (RFS) bits in the Receive Descriptor 0 are from bit 9 to
1266                  * bit 0. However, in case of the R8A7740's GETHER, the RFS
1267                  * bits are from bit 25 to bit 16. So, the driver needs right
1268                  * shifting by 16.
1269                  */
1270                 desc_status >>= 16;
1271 #endif
1272
1273                 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
1274                                    RD_RFS5 | RD_RFS6 | RD_RFS10)) {
1275                         ndev->stats.rx_errors++;
1276                         if (desc_status & RD_RFS1)
1277                                 ndev->stats.rx_crc_errors++;
1278                         if (desc_status & RD_RFS2)
1279                                 ndev->stats.rx_frame_errors++;
1280                         if (desc_status & RD_RFS3)
1281                                 ndev->stats.rx_length_errors++;
1282                         if (desc_status & RD_RFS4)
1283                                 ndev->stats.rx_length_errors++;
1284                         if (desc_status & RD_RFS6)
1285                                 ndev->stats.rx_missed_errors++;
1286                         if (desc_status & RD_RFS10)
1287                                 ndev->stats.rx_over_errors++;
1288                 } else {
1289                         if (!mdp->cd->hw_swap)
1290                                 sh_eth_soft_swap(
1291                                         phys_to_virt(ALIGN(rxdesc->addr, 4)),
1292                                         pkt_len + 2);
1293                         skb = mdp->rx_skbuff[entry];
1294                         mdp->rx_skbuff[entry] = NULL;
1295                         if (mdp->cd->rpadir)
1296                                 skb_reserve(skb, NET_IP_ALIGN);
1297                         skb_put(skb, pkt_len);
1298                         skb->protocol = eth_type_trans(skb, ndev);
1299                         netif_rx(skb);
1300                         ndev->stats.rx_packets++;
1301                         ndev->stats.rx_bytes += pkt_len;
1302                 }
1303                 rxdesc->status |= cpu_to_edmac(mdp, RD_RACT);
1304                 entry = (++mdp->cur_rx) % mdp->num_rx_ring;
1305                 rxdesc = &mdp->rx_ring[entry];
1306         }
1307
1308         /* Refill the Rx ring buffers. */
1309         for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
1310                 entry = mdp->dirty_rx % mdp->num_rx_ring;
1311                 rxdesc = &mdp->rx_ring[entry];
1312                 /* The size of the buffer is 16 byte boundary. */
1313                 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
1314
1315                 if (mdp->rx_skbuff[entry] == NULL) {
1316                         skb = netdev_alloc_skb(ndev, mdp->rx_buf_sz);
1317                         mdp->rx_skbuff[entry] = skb;
1318                         if (skb == NULL)
1319                                 break;  /* Better luck next round. */
1320                         dma_map_single(&ndev->dev, skb->data, mdp->rx_buf_sz,
1321                                         DMA_FROM_DEVICE);
1322                         sh_eth_set_receive_align(skb);
1323
1324                         skb_checksum_none_assert(skb);
1325                         rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
1326                 }
1327                 if (entry >= mdp->num_rx_ring - 1)
1328                         rxdesc->status |=
1329                                 cpu_to_edmac(mdp, RD_RACT | RD_RFP | RD_RDEL);
1330                 else
1331                         rxdesc->status |=
1332                                 cpu_to_edmac(mdp, RD_RACT | RD_RFP);
1333         }
1334
1335         /* Restart Rx engine if stopped. */
1336         /* If we don't need to check status, don't. -KDU */
1337         if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) {
1338                 /* fix the values for the next receiving if RDE is set */
1339                 if (intr_status & EESR_RDE)
1340                         mdp->cur_rx = mdp->dirty_rx =
1341                                 (sh_eth_read(ndev, RDFAR) -
1342                                  sh_eth_read(ndev, RDLAR)) >> 4;
1343                 sh_eth_write(ndev, EDRRR_R, EDRRR);
1344         }
1345
1346         return exceeded;
1347 }
1348
1349 static void sh_eth_rcv_snd_disable(struct net_device *ndev)
1350 {
1351         /* disable tx and rx */
1352         sh_eth_write(ndev, sh_eth_read(ndev, ECMR) &
1353                 ~(ECMR_RE | ECMR_TE), ECMR);
1354 }
1355
1356 static void sh_eth_rcv_snd_enable(struct net_device *ndev)
1357 {
1358         /* enable tx and rx */
1359         sh_eth_write(ndev, sh_eth_read(ndev, ECMR) |
1360                 (ECMR_RE | ECMR_TE), ECMR);
1361 }
1362
1363 /* error control function */
1364 static void sh_eth_error(struct net_device *ndev, int intr_status)
1365 {
1366         struct sh_eth_private *mdp = netdev_priv(ndev);
1367         u32 felic_stat;
1368         u32 link_stat;
1369         u32 mask;
1370
1371         if (intr_status & EESR_ECI) {
1372                 felic_stat = sh_eth_read(ndev, ECSR);
1373                 sh_eth_write(ndev, felic_stat, ECSR);   /* clear int */
1374                 if (felic_stat & ECSR_ICD)
1375                         ndev->stats.tx_carrier_errors++;
1376                 if (felic_stat & ECSR_LCHNG) {
1377                         /* Link Changed */
1378                         if (mdp->cd->no_psr || mdp->no_ether_link) {
1379                                 goto ignore_link;
1380                         } else {
1381                                 link_stat = (sh_eth_read(ndev, PSR));
1382                                 if (mdp->ether_link_active_low)
1383                                         link_stat = ~link_stat;
1384                         }
1385                         if (!(link_stat & PHY_ST_LINK))
1386                                 sh_eth_rcv_snd_disable(ndev);
1387                         else {
1388                                 /* Link Up */
1389                                 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) &
1390                                           ~DMAC_M_ECI, EESIPR);
1391                                 /*clear int */
1392                                 sh_eth_write(ndev, sh_eth_read(ndev, ECSR),
1393                                           ECSR);
1394                                 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) |
1395                                           DMAC_M_ECI, EESIPR);
1396                                 /* enable tx and rx */
1397                                 sh_eth_rcv_snd_enable(ndev);
1398                         }
1399                 }
1400         }
1401
1402 ignore_link:
1403         if (intr_status & EESR_TWB) {
1404                 /* Write buck end. unused write back interrupt */
1405                 if (intr_status & EESR_TABT)    /* Transmit Abort int */
1406                         ndev->stats.tx_aborted_errors++;
1407                         if (netif_msg_tx_err(mdp))
1408                                 dev_err(&ndev->dev, "Transmit Abort\n");
1409         }
1410
1411         if (intr_status & EESR_RABT) {
1412                 /* Receive Abort int */
1413                 if (intr_status & EESR_RFRMER) {
1414                         /* Receive Frame Overflow int */
1415                         ndev->stats.rx_frame_errors++;
1416                         if (netif_msg_rx_err(mdp))
1417                                 dev_err(&ndev->dev, "Receive Abort\n");
1418                 }
1419         }
1420
1421         if (intr_status & EESR_TDE) {
1422                 /* Transmit Descriptor Empty int */
1423                 ndev->stats.tx_fifo_errors++;
1424                 if (netif_msg_tx_err(mdp))
1425                         dev_err(&ndev->dev, "Transmit Descriptor Empty\n");
1426         }
1427
1428         if (intr_status & EESR_TFE) {
1429                 /* FIFO under flow */
1430                 ndev->stats.tx_fifo_errors++;
1431                 if (netif_msg_tx_err(mdp))
1432                         dev_err(&ndev->dev, "Transmit FIFO Under flow\n");
1433         }
1434
1435         if (intr_status & EESR_RDE) {
1436                 /* Receive Descriptor Empty int */
1437                 ndev->stats.rx_over_errors++;
1438
1439                 if (netif_msg_rx_err(mdp))
1440                         dev_err(&ndev->dev, "Receive Descriptor Empty\n");
1441         }
1442
1443         if (intr_status & EESR_RFE) {
1444                 /* Receive FIFO Overflow int */
1445                 ndev->stats.rx_fifo_errors++;
1446                 if (netif_msg_rx_err(mdp))
1447                         dev_err(&ndev->dev, "Receive FIFO Overflow\n");
1448         }
1449
1450         if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
1451                 /* Address Error */
1452                 ndev->stats.tx_fifo_errors++;
1453                 if (netif_msg_tx_err(mdp))
1454                         dev_err(&ndev->dev, "Address Error\n");
1455         }
1456
1457         mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
1458         if (mdp->cd->no_ade)
1459                 mask &= ~EESR_ADE;
1460         if (intr_status & mask) {
1461                 /* Tx error */
1462                 u32 edtrr = sh_eth_read(ndev, EDTRR);
1463                 /* dmesg */
1464                 dev_err(&ndev->dev, "TX error. status=%8.8x cur_tx=%8.8x ",
1465                                 intr_status, mdp->cur_tx);
1466                 dev_err(&ndev->dev, "dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
1467                                 mdp->dirty_tx, (u32) ndev->state, edtrr);
1468                 /* dirty buffer free */
1469                 sh_eth_txfree(ndev);
1470
1471                 /* SH7712 BUG */
1472                 if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) {
1473                         /* tx dma start */
1474                         sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
1475                 }
1476                 /* wakeup */
1477                 netif_wake_queue(ndev);
1478         }
1479 }
1480
1481 static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
1482 {
1483         struct net_device *ndev = netdev;
1484         struct sh_eth_private *mdp = netdev_priv(ndev);
1485         struct sh_eth_cpu_data *cd = mdp->cd;
1486         irqreturn_t ret = IRQ_NONE;
1487         unsigned long intr_status, intr_enable;
1488
1489         spin_lock(&mdp->lock);
1490
1491         /* Get interrupt status */
1492         intr_status = sh_eth_read(ndev, EESR);
1493         /* Mask it with the interrupt mask, forcing ECI interrupt to be always
1494          * enabled since it's the one that  comes thru regardless of the mask,
1495          * and we need to fully handle it in sh_eth_error() in order to quench
1496          * it as it doesn't get cleared by just writing 1 to the ECI bit...
1497          */
1498         intr_enable = sh_eth_read(ndev, EESIPR);
1499         intr_status &= intr_enable | DMAC_M_ECI;
1500         if (intr_status & (EESR_RX_CHECK | cd->tx_check | cd->eesr_err_check))
1501                 ret = IRQ_HANDLED;
1502         else
1503                 goto other_irq;
1504
1505         if (intr_status & EESR_RX_CHECK) {
1506                 if (napi_schedule_prep(&mdp->napi)) {
1507                         /* Mask Rx interrupts */
1508                         sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK,
1509                                      EESIPR);
1510                         __napi_schedule(&mdp->napi);
1511                 } else {
1512                         dev_warn(&ndev->dev,
1513                                  "ignoring interrupt, status 0x%08lx, mask 0x%08lx.\n",
1514                                  intr_status, intr_enable);
1515                 }
1516         }
1517
1518         /* Tx Check */
1519         if (intr_status & cd->tx_check) {
1520                 /* Clear Tx interrupts */
1521                 sh_eth_write(ndev, intr_status & cd->tx_check, EESR);
1522
1523                 sh_eth_txfree(ndev);
1524                 netif_wake_queue(ndev);
1525         }
1526
1527         if (intr_status & cd->eesr_err_check) {
1528                 /* Clear error interrupts */
1529                 sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR);
1530
1531                 sh_eth_error(ndev, intr_status);
1532         }
1533
1534 other_irq:
1535         spin_unlock(&mdp->lock);
1536
1537         return ret;
1538 }
1539
1540 static int sh_eth_poll(struct napi_struct *napi, int budget)
1541 {
1542         struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private,
1543                                                   napi);
1544         struct net_device *ndev = napi->dev;
1545         int quota = budget;
1546         unsigned long intr_status;
1547
1548         for (;;) {
1549                 intr_status = sh_eth_read(ndev, EESR);
1550                 if (!(intr_status & EESR_RX_CHECK))
1551                         break;
1552                 /* Clear Rx interrupts */
1553                 sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR);
1554
1555                 if (sh_eth_rx(ndev, intr_status, &quota))
1556                         goto out;
1557         }
1558
1559         napi_complete(napi);
1560
1561         /* Reenable Rx interrupts */
1562         sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1563 out:
1564         return budget - quota;
1565 }
1566
1567 /* PHY state control function */
1568 static void sh_eth_adjust_link(struct net_device *ndev)
1569 {
1570         struct sh_eth_private *mdp = netdev_priv(ndev);
1571         struct phy_device *phydev = mdp->phydev;
1572         int new_state = 0;
1573
1574         if (phydev->link) {
1575                 if (phydev->duplex != mdp->duplex) {
1576                         new_state = 1;
1577                         mdp->duplex = phydev->duplex;
1578                         if (mdp->cd->set_duplex)
1579                                 mdp->cd->set_duplex(ndev);
1580                 }
1581
1582                 if (phydev->speed != mdp->speed) {
1583                         new_state = 1;
1584                         mdp->speed = phydev->speed;
1585                         if (mdp->cd->set_rate)
1586                                 mdp->cd->set_rate(ndev);
1587                 }
1588                 if (!mdp->link) {
1589                         sh_eth_write(ndev,
1590                                 (sh_eth_read(ndev, ECMR) & ~ECMR_TXF), ECMR);
1591                         new_state = 1;
1592                         mdp->link = phydev->link;
1593                         if (mdp->cd->no_psr || mdp->no_ether_link)
1594                                 sh_eth_rcv_snd_enable(ndev);
1595                 }
1596         } else if (mdp->link) {
1597                 new_state = 1;
1598                 mdp->link = 0;
1599                 mdp->speed = 0;
1600                 mdp->duplex = -1;
1601                 if (mdp->cd->no_psr || mdp->no_ether_link)
1602                         sh_eth_rcv_snd_disable(ndev);
1603         }
1604
1605         if (new_state && netif_msg_link(mdp))
1606                 phy_print_status(phydev);
1607 }
1608
1609 /* PHY init function */
1610 static int sh_eth_phy_init(struct net_device *ndev)
1611 {
1612         struct sh_eth_private *mdp = netdev_priv(ndev);
1613         char phy_id[MII_BUS_ID_SIZE + 3];
1614         struct phy_device *phydev = NULL;
1615
1616         snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
1617                 mdp->mii_bus->id , mdp->phy_id);
1618
1619         mdp->link = 0;
1620         mdp->speed = 0;
1621         mdp->duplex = -1;
1622
1623         /* Try connect to PHY */
1624         phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
1625                              mdp->phy_interface);
1626         if (IS_ERR(phydev)) {
1627                 dev_err(&ndev->dev, "phy_connect failed\n");
1628                 return PTR_ERR(phydev);
1629         }
1630
1631         dev_info(&ndev->dev, "attached phy %i to driver %s\n",
1632                 phydev->addr, phydev->drv->name);
1633
1634         mdp->phydev = phydev;
1635
1636         return 0;
1637 }
1638
1639 /* PHY control start function */
1640 static int sh_eth_phy_start(struct net_device *ndev)
1641 {
1642         struct sh_eth_private *mdp = netdev_priv(ndev);
1643         int ret;
1644
1645         ret = sh_eth_phy_init(ndev);
1646         if (ret)
1647                 return ret;
1648
1649         /* reset phy - this also wakes it from PDOWN */
1650         phy_write(mdp->phydev, MII_BMCR, BMCR_RESET);
1651         phy_start(mdp->phydev);
1652
1653         return 0;
1654 }
1655
1656 static int sh_eth_get_settings(struct net_device *ndev,
1657                         struct ethtool_cmd *ecmd)
1658 {
1659         struct sh_eth_private *mdp = netdev_priv(ndev);
1660         unsigned long flags;
1661         int ret;
1662
1663         spin_lock_irqsave(&mdp->lock, flags);
1664         ret = phy_ethtool_gset(mdp->phydev, ecmd);
1665         spin_unlock_irqrestore(&mdp->lock, flags);
1666
1667         return ret;
1668 }
1669
1670 static int sh_eth_set_settings(struct net_device *ndev,
1671                 struct ethtool_cmd *ecmd)
1672 {
1673         struct sh_eth_private *mdp = netdev_priv(ndev);
1674         unsigned long flags;
1675         int ret;
1676
1677         spin_lock_irqsave(&mdp->lock, flags);
1678
1679         /* disable tx and rx */
1680         sh_eth_rcv_snd_disable(ndev);
1681
1682         ret = phy_ethtool_sset(mdp->phydev, ecmd);
1683         if (ret)
1684                 goto error_exit;
1685
1686         if (ecmd->duplex == DUPLEX_FULL)
1687                 mdp->duplex = 1;
1688         else
1689                 mdp->duplex = 0;
1690
1691         if (mdp->cd->set_duplex)
1692                 mdp->cd->set_duplex(ndev);
1693
1694 error_exit:
1695         mdelay(1);
1696
1697         /* enable tx and rx */
1698         sh_eth_rcv_snd_enable(ndev);
1699
1700         spin_unlock_irqrestore(&mdp->lock, flags);
1701
1702         return ret;
1703 }
1704
1705 static int sh_eth_nway_reset(struct net_device *ndev)
1706 {
1707         struct sh_eth_private *mdp = netdev_priv(ndev);
1708         unsigned long flags;
1709         int ret;
1710
1711         spin_lock_irqsave(&mdp->lock, flags);
1712         ret = phy_start_aneg(mdp->phydev);
1713         spin_unlock_irqrestore(&mdp->lock, flags);
1714
1715         return ret;
1716 }
1717
1718 static u32 sh_eth_get_msglevel(struct net_device *ndev)
1719 {
1720         struct sh_eth_private *mdp = netdev_priv(ndev);
1721         return mdp->msg_enable;
1722 }
1723
1724 static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
1725 {
1726         struct sh_eth_private *mdp = netdev_priv(ndev);
1727         mdp->msg_enable = value;
1728 }
1729
1730 static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
1731         "rx_current", "tx_current",
1732         "rx_dirty", "tx_dirty",
1733 };
1734 #define SH_ETH_STATS_LEN  ARRAY_SIZE(sh_eth_gstrings_stats)
1735
1736 static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
1737 {
1738         switch (sset) {
1739         case ETH_SS_STATS:
1740                 return SH_ETH_STATS_LEN;
1741         default:
1742                 return -EOPNOTSUPP;
1743         }
1744 }
1745
1746 static void sh_eth_get_ethtool_stats(struct net_device *ndev,
1747                         struct ethtool_stats *stats, u64 *data)
1748 {
1749         struct sh_eth_private *mdp = netdev_priv(ndev);
1750         int i = 0;
1751
1752         /* device-specific stats */
1753         data[i++] = mdp->cur_rx;
1754         data[i++] = mdp->cur_tx;
1755         data[i++] = mdp->dirty_rx;
1756         data[i++] = mdp->dirty_tx;
1757 }
1758
1759 static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1760 {
1761         switch (stringset) {
1762         case ETH_SS_STATS:
1763                 memcpy(data, *sh_eth_gstrings_stats,
1764                                         sizeof(sh_eth_gstrings_stats));
1765                 break;
1766         }
1767 }
1768
1769 static void sh_eth_get_ringparam(struct net_device *ndev,
1770                                  struct ethtool_ringparam *ring)
1771 {
1772         struct sh_eth_private *mdp = netdev_priv(ndev);
1773
1774         ring->rx_max_pending = RX_RING_MAX;
1775         ring->tx_max_pending = TX_RING_MAX;
1776         ring->rx_pending = mdp->num_rx_ring;
1777         ring->tx_pending = mdp->num_tx_ring;
1778 }
1779
1780 static int sh_eth_set_ringparam(struct net_device *ndev,
1781                                 struct ethtool_ringparam *ring)
1782 {
1783         struct sh_eth_private *mdp = netdev_priv(ndev);
1784         int ret;
1785
1786         if (ring->tx_pending > TX_RING_MAX ||
1787             ring->rx_pending > RX_RING_MAX ||
1788             ring->tx_pending < TX_RING_MIN ||
1789             ring->rx_pending < RX_RING_MIN)
1790                 return -EINVAL;
1791         if (ring->rx_mini_pending || ring->rx_jumbo_pending)
1792                 return -EINVAL;
1793
1794         if (netif_running(ndev)) {
1795                 netif_tx_disable(ndev);
1796                 /* Disable interrupts by clearing the interrupt mask. */
1797                 sh_eth_write(ndev, 0x0000, EESIPR);
1798                 /* Stop the chip's Tx and Rx processes. */
1799                 sh_eth_write(ndev, 0, EDTRR);
1800                 sh_eth_write(ndev, 0, EDRRR);
1801                 synchronize_irq(ndev->irq);
1802         }
1803
1804         /* Free all the skbuffs in the Rx queue. */
1805         sh_eth_ring_free(ndev);
1806         /* Free DMA buffer */
1807         sh_eth_free_dma_buffer(mdp);
1808
1809         /* Set new parameters */
1810         mdp->num_rx_ring = ring->rx_pending;
1811         mdp->num_tx_ring = ring->tx_pending;
1812
1813         ret = sh_eth_ring_init(ndev);
1814         if (ret < 0) {
1815                 dev_err(&ndev->dev, "%s: sh_eth_ring_init failed.\n", __func__);
1816                 return ret;
1817         }
1818         ret = sh_eth_dev_init(ndev, false);
1819         if (ret < 0) {
1820                 dev_err(&ndev->dev, "%s: sh_eth_dev_init failed.\n", __func__);
1821                 return ret;
1822         }
1823
1824         if (netif_running(ndev)) {
1825                 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1826                 /* Setting the Rx mode will start the Rx process. */
1827                 sh_eth_write(ndev, EDRRR_R, EDRRR);
1828                 netif_wake_queue(ndev);
1829         }
1830
1831         return 0;
1832 }
1833
1834 static const struct ethtool_ops sh_eth_ethtool_ops = {
1835         .get_settings   = sh_eth_get_settings,
1836         .set_settings   = sh_eth_set_settings,
1837         .nway_reset     = sh_eth_nway_reset,
1838         .get_msglevel   = sh_eth_get_msglevel,
1839         .set_msglevel   = sh_eth_set_msglevel,
1840         .get_link       = ethtool_op_get_link,
1841         .get_strings    = sh_eth_get_strings,
1842         .get_ethtool_stats  = sh_eth_get_ethtool_stats,
1843         .get_sset_count     = sh_eth_get_sset_count,
1844         .get_ringparam  = sh_eth_get_ringparam,
1845         .set_ringparam  = sh_eth_set_ringparam,
1846 };
1847
1848 /* network device open function */
1849 static int sh_eth_open(struct net_device *ndev)
1850 {
1851         int ret = 0;
1852         struct sh_eth_private *mdp = netdev_priv(ndev);
1853
1854         pm_runtime_get_sync(&mdp->pdev->dev);
1855
1856         ret = request_irq(ndev->irq, sh_eth_interrupt,
1857                           mdp->cd->irq_flags, ndev->name, ndev);
1858         if (ret) {
1859                 dev_err(&ndev->dev, "Can not assign IRQ number\n");
1860                 return ret;
1861         }
1862
1863         /* Descriptor set */
1864         ret = sh_eth_ring_init(ndev);
1865         if (ret)
1866                 goto out_free_irq;
1867
1868         /* device init */
1869         ret = sh_eth_dev_init(ndev, true);
1870         if (ret)
1871                 goto out_free_irq;
1872
1873         /* PHY control start*/
1874         ret = sh_eth_phy_start(ndev);
1875         if (ret)
1876                 goto out_free_irq;
1877
1878         napi_enable(&mdp->napi);
1879
1880         return ret;
1881
1882 out_free_irq:
1883         free_irq(ndev->irq, ndev);
1884         pm_runtime_put_sync(&mdp->pdev->dev);
1885         return ret;
1886 }
1887
1888 /* Timeout function */
1889 static void sh_eth_tx_timeout(struct net_device *ndev)
1890 {
1891         struct sh_eth_private *mdp = netdev_priv(ndev);
1892         struct sh_eth_rxdesc *rxdesc;
1893         int i;
1894
1895         netif_stop_queue(ndev);
1896
1897         if (netif_msg_timer(mdp))
1898                 dev_err(&ndev->dev, "%s: transmit timed out, status %8.8x,"
1899                " resetting...\n", ndev->name, (int)sh_eth_read(ndev, EESR));
1900
1901         /* tx_errors count up */
1902         ndev->stats.tx_errors++;
1903
1904         /* Free all the skbuffs in the Rx queue. */
1905         for (i = 0; i < mdp->num_rx_ring; i++) {
1906                 rxdesc = &mdp->rx_ring[i];
1907                 rxdesc->status = 0;
1908                 rxdesc->addr = 0xBADF00D0;
1909                 if (mdp->rx_skbuff[i])
1910                         dev_kfree_skb(mdp->rx_skbuff[i]);
1911                 mdp->rx_skbuff[i] = NULL;
1912         }
1913         for (i = 0; i < mdp->num_tx_ring; i++) {
1914                 if (mdp->tx_skbuff[i])
1915                         dev_kfree_skb(mdp->tx_skbuff[i]);
1916                 mdp->tx_skbuff[i] = NULL;
1917         }
1918
1919         /* device init */
1920         sh_eth_dev_init(ndev, true);
1921 }
1922
1923 /* Packet transmit function */
1924 static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1925 {
1926         struct sh_eth_private *mdp = netdev_priv(ndev);
1927         struct sh_eth_txdesc *txdesc;
1928         u32 entry;
1929         unsigned long flags;
1930
1931         spin_lock_irqsave(&mdp->lock, flags);
1932         if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) {
1933                 if (!sh_eth_txfree(ndev)) {
1934                         if (netif_msg_tx_queued(mdp))
1935                                 dev_warn(&ndev->dev, "TxFD exhausted.\n");
1936                         netif_stop_queue(ndev);
1937                         spin_unlock_irqrestore(&mdp->lock, flags);
1938                         return NETDEV_TX_BUSY;
1939                 }
1940         }
1941         spin_unlock_irqrestore(&mdp->lock, flags);
1942
1943         entry = mdp->cur_tx % mdp->num_tx_ring;
1944         mdp->tx_skbuff[entry] = skb;
1945         txdesc = &mdp->tx_ring[entry];
1946         /* soft swap. */
1947         if (!mdp->cd->hw_swap)
1948                 sh_eth_soft_swap(phys_to_virt(ALIGN(txdesc->addr, 4)),
1949                                  skb->len + 2);
1950         txdesc->addr = dma_map_single(&ndev->dev, skb->data, skb->len,
1951                                       DMA_TO_DEVICE);
1952         if (skb->len < ETHERSMALL)
1953                 txdesc->buffer_length = ETHERSMALL;
1954         else
1955                 txdesc->buffer_length = skb->len;
1956
1957         if (entry >= mdp->num_tx_ring - 1)
1958                 txdesc->status |= cpu_to_edmac(mdp, TD_TACT | TD_TDLE);
1959         else
1960                 txdesc->status |= cpu_to_edmac(mdp, TD_TACT);
1961
1962         mdp->cur_tx++;
1963
1964         if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp)))
1965                 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
1966
1967         return NETDEV_TX_OK;
1968 }
1969
1970 /* device close function */
1971 static int sh_eth_close(struct net_device *ndev)
1972 {
1973         struct sh_eth_private *mdp = netdev_priv(ndev);
1974
1975         napi_disable(&mdp->napi);
1976
1977         netif_stop_queue(ndev);
1978
1979         /* Disable interrupts by clearing the interrupt mask. */
1980         sh_eth_write(ndev, 0x0000, EESIPR);
1981
1982         /* Stop the chip's Tx and Rx processes. */
1983         sh_eth_write(ndev, 0, EDTRR);
1984         sh_eth_write(ndev, 0, EDRRR);
1985
1986         /* PHY Disconnect */
1987         if (mdp->phydev) {
1988                 phy_stop(mdp->phydev);
1989                 phy_disconnect(mdp->phydev);
1990         }
1991
1992         free_irq(ndev->irq, ndev);
1993
1994         /* Free all the skbuffs in the Rx queue. */
1995         sh_eth_ring_free(ndev);
1996
1997         /* free DMA buffer */
1998         sh_eth_free_dma_buffer(mdp);
1999
2000         pm_runtime_put_sync(&mdp->pdev->dev);
2001
2002         return 0;
2003 }
2004
2005 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
2006 {
2007         struct sh_eth_private *mdp = netdev_priv(ndev);
2008
2009         pm_runtime_get_sync(&mdp->pdev->dev);
2010
2011         ndev->stats.tx_dropped += sh_eth_read(ndev, TROCR);
2012         sh_eth_write(ndev, 0, TROCR);   /* (write clear) */
2013         ndev->stats.collisions += sh_eth_read(ndev, CDCR);
2014         sh_eth_write(ndev, 0, CDCR);    /* (write clear) */
2015         ndev->stats.tx_carrier_errors += sh_eth_read(ndev, LCCR);
2016         sh_eth_write(ndev, 0, LCCR);    /* (write clear) */
2017         if (sh_eth_is_gether(mdp)) {
2018                 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CERCR);
2019                 sh_eth_write(ndev, 0, CERCR);   /* (write clear) */
2020                 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CEECR);
2021                 sh_eth_write(ndev, 0, CEECR);   /* (write clear) */
2022         } else {
2023                 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CNDCR);
2024                 sh_eth_write(ndev, 0, CNDCR);   /* (write clear) */
2025         }
2026         pm_runtime_put_sync(&mdp->pdev->dev);
2027
2028         return &ndev->stats;
2029 }
2030
2031 /* ioctl to device function */
2032 static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq,
2033                                 int cmd)
2034 {
2035         struct sh_eth_private *mdp = netdev_priv(ndev);
2036         struct phy_device *phydev = mdp->phydev;
2037
2038         if (!netif_running(ndev))
2039                 return -EINVAL;
2040
2041         if (!phydev)
2042                 return -ENODEV;
2043
2044         return phy_mii_ioctl(phydev, rq, cmd);
2045 }
2046
2047 /* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
2048 static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private *mdp,
2049                                             int entry)
2050 {
2051         return sh_eth_tsu_get_offset(mdp, TSU_POST1) + (entry / 8 * 4);
2052 }
2053
2054 static u32 sh_eth_tsu_get_post_mask(int entry)
2055 {
2056         return 0x0f << (28 - ((entry % 8) * 4));
2057 }
2058
2059 static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry)
2060 {
2061         return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4));
2062 }
2063
2064 static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev,
2065                                              int entry)
2066 {
2067         struct sh_eth_private *mdp = netdev_priv(ndev);
2068         u32 tmp;
2069         void *reg_offset;
2070
2071         reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2072         tmp = ioread32(reg_offset);
2073         iowrite32(tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg_offset);
2074 }
2075
2076 static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev,
2077                                               int entry)
2078 {
2079         struct sh_eth_private *mdp = netdev_priv(ndev);
2080         u32 post_mask, ref_mask, tmp;
2081         void *reg_offset;
2082
2083         reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2084         post_mask = sh_eth_tsu_get_post_mask(entry);
2085         ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask;
2086
2087         tmp = ioread32(reg_offset);
2088         iowrite32(tmp & ~post_mask, reg_offset);
2089
2090         /* If other port enables, the function returns "true" */
2091         return tmp & ref_mask;
2092 }
2093
2094 static int sh_eth_tsu_busy(struct net_device *ndev)
2095 {
2096         int timeout = SH_ETH_TSU_TIMEOUT_MS * 100;
2097         struct sh_eth_private *mdp = netdev_priv(ndev);
2098
2099         while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) {
2100                 udelay(10);
2101                 timeout--;
2102                 if (timeout <= 0) {
2103                         dev_err(&ndev->dev, "%s: timeout\n", __func__);
2104                         return -ETIMEDOUT;
2105                 }
2106         }
2107
2108         return 0;
2109 }
2110
2111 static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg,
2112                                   const u8 *addr)
2113 {
2114         u32 val;
2115
2116         val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
2117         iowrite32(val, reg);
2118         if (sh_eth_tsu_busy(ndev) < 0)
2119                 return -EBUSY;
2120
2121         val = addr[4] << 8 | addr[5];
2122         iowrite32(val, reg + 4);
2123         if (sh_eth_tsu_busy(ndev) < 0)
2124                 return -EBUSY;
2125
2126         return 0;
2127 }
2128
2129 static void sh_eth_tsu_read_entry(void *reg, u8 *addr)
2130 {
2131         u32 val;
2132
2133         val = ioread32(reg);
2134         addr[0] = (val >> 24) & 0xff;
2135         addr[1] = (val >> 16) & 0xff;
2136         addr[2] = (val >> 8) & 0xff;
2137         addr[3] = val & 0xff;
2138         val = ioread32(reg + 4);
2139         addr[4] = (val >> 8) & 0xff;
2140         addr[5] = val & 0xff;
2141 }
2142
2143
2144 static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr)
2145 {
2146         struct sh_eth_private *mdp = netdev_priv(ndev);
2147         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2148         int i;
2149         u8 c_addr[ETH_ALEN];
2150
2151         for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2152                 sh_eth_tsu_read_entry(reg_offset, c_addr);
2153                 if (memcmp(addr, c_addr, ETH_ALEN) == 0)
2154                         return i;
2155         }
2156
2157         return -ENOENT;
2158 }
2159
2160 static int sh_eth_tsu_find_empty(struct net_device *ndev)
2161 {
2162         u8 blank[ETH_ALEN];
2163         int entry;
2164
2165         memset(blank, 0, sizeof(blank));
2166         entry = sh_eth_tsu_find_entry(ndev, blank);
2167         return (entry < 0) ? -ENOMEM : entry;
2168 }
2169
2170 static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev,
2171                                               int entry)
2172 {
2173         struct sh_eth_private *mdp = netdev_priv(ndev);
2174         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2175         int ret;
2176         u8 blank[ETH_ALEN];
2177
2178         sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) &
2179                          ~(1 << (31 - entry)), TSU_TEN);
2180
2181         memset(blank, 0, sizeof(blank));
2182         ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank);
2183         if (ret < 0)
2184                 return ret;
2185         return 0;
2186 }
2187
2188 static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr)
2189 {
2190         struct sh_eth_private *mdp = netdev_priv(ndev);
2191         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2192         int i, ret;
2193
2194         if (!mdp->cd->tsu)
2195                 return 0;
2196
2197         i = sh_eth_tsu_find_entry(ndev, addr);
2198         if (i < 0) {
2199                 /* No entry found, create one */
2200                 i = sh_eth_tsu_find_empty(ndev);
2201                 if (i < 0)
2202                         return -ENOMEM;
2203                 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr);
2204                 if (ret < 0)
2205                         return ret;
2206
2207                 /* Enable the entry */
2208                 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) |
2209                                  (1 << (31 - i)), TSU_TEN);
2210         }
2211
2212         /* Entry found or created, enable POST */
2213         sh_eth_tsu_enable_cam_entry_post(ndev, i);
2214
2215         return 0;
2216 }
2217
2218 static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr)
2219 {
2220         struct sh_eth_private *mdp = netdev_priv(ndev);
2221         int i, ret;
2222
2223         if (!mdp->cd->tsu)
2224                 return 0;
2225
2226         i = sh_eth_tsu_find_entry(ndev, addr);
2227         if (i) {
2228                 /* Entry found */
2229                 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2230                         goto done;
2231
2232                 /* Disable the entry if both ports was disabled */
2233                 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2234                 if (ret < 0)
2235                         return ret;
2236         }
2237 done:
2238         return 0;
2239 }
2240
2241 static int sh_eth_tsu_purge_all(struct net_device *ndev)
2242 {
2243         struct sh_eth_private *mdp = netdev_priv(ndev);
2244         int i, ret;
2245
2246         if (unlikely(!mdp->cd->tsu))
2247                 return 0;
2248
2249         for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) {
2250                 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2251                         continue;
2252
2253                 /* Disable the entry if both ports was disabled */
2254                 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2255                 if (ret < 0)
2256                         return ret;
2257         }
2258
2259         return 0;
2260 }
2261
2262 static void sh_eth_tsu_purge_mcast(struct net_device *ndev)
2263 {
2264         struct sh_eth_private *mdp = netdev_priv(ndev);
2265         u8 addr[ETH_ALEN];
2266         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2267         int i;
2268
2269         if (unlikely(!mdp->cd->tsu))
2270                 return;
2271
2272         for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2273                 sh_eth_tsu_read_entry(reg_offset, addr);
2274                 if (is_multicast_ether_addr(addr))
2275                         sh_eth_tsu_del_entry(ndev, addr);
2276         }
2277 }
2278
2279 /* Multicast reception directions set */
2280 static void sh_eth_set_multicast_list(struct net_device *ndev)
2281 {
2282         struct sh_eth_private *mdp = netdev_priv(ndev);
2283         u32 ecmr_bits;
2284         int mcast_all = 0;
2285         unsigned long flags;
2286
2287         spin_lock_irqsave(&mdp->lock, flags);
2288         /*
2289          * Initial condition is MCT = 1, PRM = 0.
2290          * Depending on ndev->flags, set PRM or clear MCT
2291          */
2292         ecmr_bits = (sh_eth_read(ndev, ECMR) & ~ECMR_PRM) | ECMR_MCT;
2293
2294         if (!(ndev->flags & IFF_MULTICAST)) {
2295                 sh_eth_tsu_purge_mcast(ndev);
2296                 mcast_all = 1;
2297         }
2298         if (ndev->flags & IFF_ALLMULTI) {
2299                 sh_eth_tsu_purge_mcast(ndev);
2300                 ecmr_bits &= ~ECMR_MCT;
2301                 mcast_all = 1;
2302         }
2303
2304         if (ndev->flags & IFF_PROMISC) {
2305                 sh_eth_tsu_purge_all(ndev);
2306                 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM;
2307         } else if (mdp->cd->tsu) {
2308                 struct netdev_hw_addr *ha;
2309                 netdev_for_each_mc_addr(ha, ndev) {
2310                         if (mcast_all && is_multicast_ether_addr(ha->addr))
2311                                 continue;
2312
2313                         if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) {
2314                                 if (!mcast_all) {
2315                                         sh_eth_tsu_purge_mcast(ndev);
2316                                         ecmr_bits &= ~ECMR_MCT;
2317                                         mcast_all = 1;
2318                                 }
2319                         }
2320                 }
2321         } else {
2322                 /* Normal, unicast/broadcast-only mode. */
2323                 ecmr_bits = (ecmr_bits & ~ECMR_PRM) | ECMR_MCT;
2324         }
2325
2326         /* update the ethernet mode */
2327         sh_eth_write(ndev, ecmr_bits, ECMR);
2328
2329         spin_unlock_irqrestore(&mdp->lock, flags);
2330 }
2331
2332 static int sh_eth_get_vtag_index(struct sh_eth_private *mdp)
2333 {
2334         if (!mdp->port)
2335                 return TSU_VTAG0;
2336         else
2337                 return TSU_VTAG1;
2338 }
2339
2340 static int sh_eth_vlan_rx_add_vid(struct net_device *ndev,
2341                                   __be16 proto, u16 vid)
2342 {
2343         struct sh_eth_private *mdp = netdev_priv(ndev);
2344         int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2345
2346         if (unlikely(!mdp->cd->tsu))
2347                 return -EPERM;
2348
2349         /* No filtering if vid = 0 */
2350         if (!vid)
2351                 return 0;
2352
2353         mdp->vlan_num_ids++;
2354
2355         /*
2356          * The controller has one VLAN tag HW filter. So, if the filter is
2357          * already enabled, the driver disables it and the filte
2358          */
2359         if (mdp->vlan_num_ids > 1) {
2360                 /* disable VLAN filter */
2361                 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2362                 return 0;
2363         }
2364
2365         sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK),
2366                          vtag_reg_index);
2367
2368         return 0;
2369 }
2370
2371 static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev,
2372                                    __be16 proto, u16 vid)
2373 {
2374         struct sh_eth_private *mdp = netdev_priv(ndev);
2375         int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2376
2377         if (unlikely(!mdp->cd->tsu))
2378                 return -EPERM;
2379
2380         /* No filtering if vid = 0 */
2381         if (!vid)
2382                 return 0;
2383
2384         mdp->vlan_num_ids--;
2385         sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2386
2387         return 0;
2388 }
2389
2390 /* SuperH's TSU register init function */
2391 static void sh_eth_tsu_init(struct sh_eth_private *mdp)
2392 {
2393         sh_eth_tsu_write(mdp, 0, TSU_FWEN0);    /* Disable forward(0->1) */
2394         sh_eth_tsu_write(mdp, 0, TSU_FWEN1);    /* Disable forward(1->0) */
2395         sh_eth_tsu_write(mdp, 0, TSU_FCM);      /* forward fifo 3k-3k */
2396         sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
2397         sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
2398         sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
2399         sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
2400         sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
2401         sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
2402         sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
2403         if (sh_eth_is_gether(mdp)) {
2404                 sh_eth_tsu_write(mdp, 0, TSU_QTAG0);    /* Disable QTAG(0->1) */
2405                 sh_eth_tsu_write(mdp, 0, TSU_QTAG1);    /* Disable QTAG(1->0) */
2406         } else {
2407                 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0);   /* Disable QTAG(0->1) */
2408                 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1);   /* Disable QTAG(1->0) */
2409         }
2410         sh_eth_tsu_write(mdp, 0, TSU_FWSR);     /* all interrupt status clear */
2411         sh_eth_tsu_write(mdp, 0, TSU_FWINMK);   /* Disable all interrupt */
2412         sh_eth_tsu_write(mdp, 0, TSU_TEN);      /* Disable all CAM entry */
2413         sh_eth_tsu_write(mdp, 0, TSU_POST1);    /* Disable CAM entry [ 0- 7] */
2414         sh_eth_tsu_write(mdp, 0, TSU_POST2);    /* Disable CAM entry [ 8-15] */
2415         sh_eth_tsu_write(mdp, 0, TSU_POST3);    /* Disable CAM entry [16-23] */
2416         sh_eth_tsu_write(mdp, 0, TSU_POST4);    /* Disable CAM entry [24-31] */
2417 }
2418
2419 /* MDIO bus release function */
2420 static int sh_mdio_release(struct net_device *ndev)
2421 {
2422         struct mii_bus *bus = dev_get_drvdata(&ndev->dev);
2423
2424         /* unregister mdio bus */
2425         mdiobus_unregister(bus);
2426
2427         /* remove mdio bus info from net_device */
2428         dev_set_drvdata(&ndev->dev, NULL);
2429
2430         /* free bitbang info */
2431         free_mdio_bitbang(bus);
2432
2433         return 0;
2434 }
2435
2436 /* MDIO bus init function */
2437 static int sh_mdio_init(struct net_device *ndev, int id,
2438                         struct sh_eth_plat_data *pd)
2439 {
2440         int ret, i;
2441         struct bb_info *bitbang;
2442         struct sh_eth_private *mdp = netdev_priv(ndev);
2443
2444         /* create bit control struct for PHY */
2445         bitbang = devm_kzalloc(&ndev->dev, sizeof(struct bb_info),
2446                                GFP_KERNEL);
2447         if (!bitbang) {
2448                 ret = -ENOMEM;
2449                 goto out;
2450         }
2451
2452         /* bitbang init */
2453         bitbang->addr = mdp->addr + mdp->reg_offset[PIR];
2454         bitbang->set_gate = pd->set_mdio_gate;
2455         bitbang->mdi_msk = PIR_MDI;
2456         bitbang->mdo_msk = PIR_MDO;
2457         bitbang->mmd_msk = PIR_MMD;
2458         bitbang->mdc_msk = PIR_MDC;
2459         bitbang->ctrl.ops = &bb_ops;
2460
2461         /* MII controller setting */
2462         mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
2463         if (!mdp->mii_bus) {
2464                 ret = -ENOMEM;
2465                 goto out;
2466         }
2467
2468         /* Hook up MII support for ethtool */
2469         mdp->mii_bus->name = "sh_mii";
2470         mdp->mii_bus->parent = &ndev->dev;
2471         snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
2472                 mdp->pdev->name, id);
2473
2474         /* PHY IRQ */
2475         mdp->mii_bus->irq = devm_kzalloc(&ndev->dev,
2476                                          sizeof(int) * PHY_MAX_ADDR,
2477                                          GFP_KERNEL);
2478         if (!mdp->mii_bus->irq) {
2479                 ret = -ENOMEM;
2480                 goto out_free_bus;
2481         }
2482
2483         for (i = 0; i < PHY_MAX_ADDR; i++)
2484                 mdp->mii_bus->irq[i] = PHY_POLL;
2485
2486         /* register mdio bus */
2487         ret = mdiobus_register(mdp->mii_bus);
2488         if (ret)
2489                 goto out_free_bus;
2490
2491         dev_set_drvdata(&ndev->dev, mdp->mii_bus);
2492
2493         return 0;
2494
2495 out_free_bus:
2496         free_mdio_bitbang(mdp->mii_bus);
2497
2498 out:
2499         return ret;
2500 }
2501
2502 static const u16 *sh_eth_get_register_offset(int register_type)
2503 {
2504         const u16 *reg_offset = NULL;
2505
2506         switch (register_type) {
2507         case SH_ETH_REG_GIGABIT:
2508                 reg_offset = sh_eth_offset_gigabit;
2509                 break;
2510         case SH_ETH_REG_FAST_RCAR:
2511                 reg_offset = sh_eth_offset_fast_rcar;
2512                 break;
2513         case SH_ETH_REG_FAST_SH4:
2514                 reg_offset = sh_eth_offset_fast_sh4;
2515                 break;
2516         case SH_ETH_REG_FAST_SH3_SH2:
2517                 reg_offset = sh_eth_offset_fast_sh3_sh2;
2518                 break;
2519         default:
2520                 pr_err("Unknown register type (%d)\n", register_type);
2521                 break;
2522         }
2523
2524         return reg_offset;
2525 }
2526
2527 static const struct net_device_ops sh_eth_netdev_ops = {
2528         .ndo_open               = sh_eth_open,
2529         .ndo_stop               = sh_eth_close,
2530         .ndo_start_xmit         = sh_eth_start_xmit,
2531         .ndo_get_stats          = sh_eth_get_stats,
2532         .ndo_tx_timeout         = sh_eth_tx_timeout,
2533         .ndo_do_ioctl           = sh_eth_do_ioctl,
2534         .ndo_validate_addr      = eth_validate_addr,
2535         .ndo_set_mac_address    = eth_mac_addr,
2536         .ndo_change_mtu         = eth_change_mtu,
2537 };
2538
2539 static const struct net_device_ops sh_eth_netdev_ops_tsu = {
2540         .ndo_open               = sh_eth_open,
2541         .ndo_stop               = sh_eth_close,
2542         .ndo_start_xmit         = sh_eth_start_xmit,
2543         .ndo_get_stats          = sh_eth_get_stats,
2544         .ndo_set_rx_mode        = sh_eth_set_multicast_list,
2545         .ndo_vlan_rx_add_vid    = sh_eth_vlan_rx_add_vid,
2546         .ndo_vlan_rx_kill_vid   = sh_eth_vlan_rx_kill_vid,
2547         .ndo_tx_timeout         = sh_eth_tx_timeout,
2548         .ndo_do_ioctl           = sh_eth_do_ioctl,
2549         .ndo_validate_addr      = eth_validate_addr,
2550         .ndo_set_mac_address    = eth_mac_addr,
2551         .ndo_change_mtu         = eth_change_mtu,
2552 };
2553
2554 static int sh_eth_drv_probe(struct platform_device *pdev)
2555 {
2556         int ret, devno = 0;
2557         struct resource *res;
2558         struct net_device *ndev = NULL;
2559         struct sh_eth_private *mdp = NULL;
2560         struct sh_eth_plat_data *pd = pdev->dev.platform_data;
2561         const struct platform_device_id *id = platform_get_device_id(pdev);
2562
2563         /* get base addr */
2564         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2565         if (unlikely(res == NULL)) {
2566                 dev_err(&pdev->dev, "invalid resource\n");
2567                 ret = -EINVAL;
2568                 goto out;
2569         }
2570
2571         ndev = alloc_etherdev(sizeof(struct sh_eth_private));
2572         if (!ndev) {
2573                 ret = -ENOMEM;
2574                 goto out;
2575         }
2576
2577         /* The sh Ether-specific entries in the device structure. */
2578         ndev->base_addr = res->start;
2579         devno = pdev->id;
2580         if (devno < 0)
2581                 devno = 0;
2582
2583         ndev->dma = -1;
2584         ret = platform_get_irq(pdev, 0);
2585         if (ret < 0) {
2586                 ret = -ENODEV;
2587                 goto out_release;
2588         }
2589         ndev->irq = ret;
2590
2591         SET_NETDEV_DEV(ndev, &pdev->dev);
2592
2593         /* Fill in the fields of the device structure with ethernet values. */
2594         ether_setup(ndev);
2595
2596         mdp = netdev_priv(ndev);
2597         mdp->num_tx_ring = TX_RING_SIZE;
2598         mdp->num_rx_ring = RX_RING_SIZE;
2599         mdp->addr = devm_ioremap_resource(&pdev->dev, res);
2600         if (IS_ERR(mdp->addr)) {
2601                 ret = PTR_ERR(mdp->addr);
2602                 goto out_release;
2603         }
2604
2605         spin_lock_init(&mdp->lock);
2606         mdp->pdev = pdev;
2607         pm_runtime_enable(&pdev->dev);
2608         pm_runtime_resume(&pdev->dev);
2609
2610         /* get PHY ID */
2611         mdp->phy_id = pd->phy;
2612         mdp->phy_interface = pd->phy_interface;
2613         /* EDMAC endian */
2614         mdp->edmac_endian = pd->edmac_endian;
2615         mdp->no_ether_link = pd->no_ether_link;
2616         mdp->ether_link_active_low = pd->ether_link_active_low;
2617         mdp->reg_offset = sh_eth_get_register_offset(pd->register_type);
2618
2619         /* set cpu data */
2620         mdp->cd = (struct sh_eth_cpu_data *)id->driver_data;
2621         sh_eth_set_default_cpu_data(mdp->cd);
2622
2623         /* set function */
2624         if (mdp->cd->tsu)
2625                 ndev->netdev_ops = &sh_eth_netdev_ops_tsu;
2626         else
2627                 ndev->netdev_ops = &sh_eth_netdev_ops;
2628         SET_ETHTOOL_OPS(ndev, &sh_eth_ethtool_ops);
2629         ndev->watchdog_timeo = TX_TIMEOUT;
2630
2631         /* debug message level */
2632         mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
2633
2634         /* read and set MAC address */
2635         read_mac_address(ndev, pd->mac_addr);
2636         if (!is_valid_ether_addr(ndev->dev_addr)) {
2637                 dev_warn(&pdev->dev,
2638                          "no valid MAC address supplied, using a random one.\n");
2639                 eth_hw_addr_random(ndev);
2640         }
2641
2642         /* ioremap the TSU registers */
2643         if (mdp->cd->tsu) {
2644                 struct resource *rtsu;
2645                 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2646                 mdp->tsu_addr = devm_ioremap_resource(&pdev->dev, rtsu);
2647                 if (IS_ERR(mdp->tsu_addr)) {
2648                         ret = PTR_ERR(mdp->tsu_addr);
2649                         goto out_release;
2650                 }
2651                 mdp->port = devno % 2;
2652                 ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER;
2653         }
2654
2655         /* initialize first or needed device */
2656         if (!devno || pd->needs_init) {
2657                 if (mdp->cd->chip_reset)
2658                         mdp->cd->chip_reset(ndev);
2659
2660                 if (mdp->cd->tsu) {
2661                         /* TSU init (Init only)*/
2662                         sh_eth_tsu_init(mdp);
2663                 }
2664         }
2665
2666         netif_napi_add(ndev, &mdp->napi, sh_eth_poll, 64);
2667
2668         /* network device register */
2669         ret = register_netdev(ndev);
2670         if (ret)
2671                 goto out_napi_del;
2672
2673         /* mdio bus init */
2674         ret = sh_mdio_init(ndev, pdev->id, pd);
2675         if (ret)
2676                 goto out_unregister;
2677
2678         /* print device information */
2679         pr_info("Base address at 0x%x, %pM, IRQ %d.\n",
2680                (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
2681
2682         platform_set_drvdata(pdev, ndev);
2683
2684         return ret;
2685
2686 out_unregister:
2687         unregister_netdev(ndev);
2688
2689 out_napi_del:
2690         netif_napi_del(&mdp->napi);
2691
2692 out_release:
2693         /* net_dev free */
2694         if (ndev)
2695                 free_netdev(ndev);
2696
2697 out:
2698         return ret;
2699 }
2700
2701 static int sh_eth_drv_remove(struct platform_device *pdev)
2702 {
2703         struct net_device *ndev = platform_get_drvdata(pdev);
2704         struct sh_eth_private *mdp = netdev_priv(ndev);
2705
2706         sh_mdio_release(ndev);
2707         unregister_netdev(ndev);
2708         netif_napi_del(&mdp->napi);
2709         pm_runtime_disable(&pdev->dev);
2710         free_netdev(ndev);
2711
2712         return 0;
2713 }
2714
2715 #ifdef CONFIG_PM
2716 static int sh_eth_runtime_nop(struct device *dev)
2717 {
2718         /*
2719          * Runtime PM callback shared between ->runtime_suspend()
2720          * and ->runtime_resume(). Simply returns success.
2721          *
2722          * This driver re-initializes all registers after
2723          * pm_runtime_get_sync() anyway so there is no need
2724          * to save and restore registers here.
2725          */
2726         return 0;
2727 }
2728
2729 static const struct dev_pm_ops sh_eth_dev_pm_ops = {
2730         .runtime_suspend = sh_eth_runtime_nop,
2731         .runtime_resume = sh_eth_runtime_nop,
2732 };
2733 #define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops)
2734 #else
2735 #define SH_ETH_PM_OPS NULL
2736 #endif
2737
2738 static struct platform_device_id sh_eth_id_table[] = {
2739         { "sh7619-ether", (kernel_ulong_t)&sh7619_data },
2740         { "sh771x-ether", (kernel_ulong_t)&sh771x_data },
2741         { "sh7724-ether", (kernel_ulong_t)&sh7724_data },
2742         { "sh7734-gether", (kernel_ulong_t)&sh7734_data },
2743         { "sh7757-ether", (kernel_ulong_t)&sh7757_data },
2744         { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga },
2745         { "sh7763-gether", (kernel_ulong_t)&sh7763_data },
2746         { "r8a7740-gether", (kernel_ulong_t)&r8a7740_data },
2747         { "r8a777x-ether", (kernel_ulong_t)&r8a777x_data },
2748         { }
2749 };
2750 MODULE_DEVICE_TABLE(platform, sh_eth_id_table);
2751
2752 static struct platform_driver sh_eth_driver = {
2753         .probe = sh_eth_drv_probe,
2754         .remove = sh_eth_drv_remove,
2755         .id_table = sh_eth_id_table,
2756         .driver = {
2757                    .name = CARDNAME,
2758                    .pm = SH_ETH_PM_OPS,
2759         },
2760 };
2761
2762 module_platform_driver(sh_eth_driver);
2763
2764 MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
2765 MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
2766 MODULE_LICENSE("GPL v2");