drivers/net/ethernet/sfc/ef10.c

   1 /****************************************************************************
   2  * Driver for Solarflare network controllers and boards
   3  * Copyright 2012-2013 Solarflare Communications Inc.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 as published
   7  * by the Free Software Foundation, incorporated herein by reference.
   8  */
   9
  10 #include "net_driver.h"
  11 #include "ef10_regs.h"
  12 #include "io.h"
  13 #include "mcdi.h"
  14 #include "mcdi_pcol.h"
  15 #include "nic.h"
  16 #include "workarounds.h"
  17 #include "selftest.h"
  18 #include <linux/in.h>
  19 #include <linux/jhash.h>
  20 #include <linux/wait.h>
  21 #include <linux/workqueue.h>
  22
  23 /* Hardware control for EF10 architecture including 'Huntington'. */
  24
  25 #define EFX_EF10_DRVGEN_EV              7
  26 enum {
  27         EFX_EF10_TEST = 1,
  28         EFX_EF10_REFILL,
  29 };
  30
  31 /* The reserved RSS context value */
  32 #define EFX_EF10_RSS_CONTEXT_INVALID    0xffffffff
  33
  34 /* The filter table(s) are managed by firmware and we have write-only
  35  * access.  When removing filters we must identify them to the
  36  * firmware by a 64-bit handle, but this is too wide for Linux kernel
  37  * interfaces (32-bit for RX NFC, 16-bit for RFS).  Also, we need to
  38  * be able to tell in advance whether a requested insertion will
  39  * replace an existing filter.  Therefore we maintain a software hash
  40  * table, which should be at least as large as the hardware hash
  41  * table.
  42  *
  43  * Huntington has a single 8K filter table shared between all filter
  44  * types and both ports.
  45  */
  46 #define HUNT_FILTER_TBL_ROWS 8192
  47
  48 struct efx_ef10_filter_table {
  49 /* The RX match field masks supported by this fw & hw, in order of priority */
  50         enum efx_filter_match_flags rx_match_flags[
  51                 MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MAXNUM];
  52         unsigned int rx_match_count;
  53
  54         struct {
  55                 unsigned long spec;     /* pointer to spec plus flag bits */
  56 /* BUSY flag indicates that an update is in progress.  AUTO_OLD is
  57  * used to mark and sweep MAC filters for the device address lists.
  58  */
  59 #define EFX_EF10_FILTER_FLAG_BUSY       1UL
  60 #define EFX_EF10_FILTER_FLAG_AUTO_OLD   2UL
  61 #define EFX_EF10_FILTER_FLAGS           3UL
  62                 u64 handle;             /* firmware handle */
  63         } *entry;
  64         wait_queue_head_t waitq;
  65 /* Shadow of net_device address lists, guarded by mac_lock */
  66 #define EFX_EF10_FILTER_DEV_UC_MAX      32
  67 #define EFX_EF10_FILTER_DEV_MC_MAX      256
  68         struct {
  69                 u8 addr[ETH_ALEN];
  70                 u16 id;
  71         } dev_uc_list[EFX_EF10_FILTER_DEV_UC_MAX],
  72           dev_mc_list[EFX_EF10_FILTER_DEV_MC_MAX];
  73         int dev_uc_count;               /* negative for PROMISC */
  74         int dev_mc_count;               /* negative for PROMISC/ALLMULTI */
  75 };
  76
  77 /* An arbitrary search limit for the software hash table */
  78 #define EFX_EF10_FILTER_SEARCH_LIMIT 200
  79
  80 static void efx_ef10_rx_push_rss_config(struct efx_nic *efx);
  81 static void efx_ef10_rx_free_indir_table(struct efx_nic *efx);
  82 static void efx_ef10_filter_table_remove(struct efx_nic *efx);
  83
  84 static int efx_ef10_get_warm_boot_count(struct efx_nic *efx)
  85 {
  86         efx_dword_t reg;
  87
  88         efx_readd(efx, &reg, ER_DZ_BIU_MC_SFT_STATUS);
  89         return EFX_DWORD_FIELD(reg, EFX_WORD_1) == 0xb007 ?
  90                 EFX_DWORD_FIELD(reg, EFX_WORD_0) : -EIO;
  91 }
  92
  93 static unsigned int efx_ef10_mem_map_size(struct efx_nic *efx)
  94 {
  95         return resource_size(&efx->pci_dev->resource[EFX_MEM_BAR]);
  96 }
  97
  98 static int efx_ef10_init_datapath_caps(struct efx_nic *efx)
  99 {
 100         MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CAPABILITIES_OUT_LEN);
 101         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 102         size_t outlen;
 103         int rc;
 104
 105         BUILD_BUG_ON(MC_CMD_GET_CAPABILITIES_IN_LEN != 0);
 106
 107         rc = efx_mcdi_rpc(efx, MC_CMD_GET_CAPABILITIES, NULL, 0,
 108                           outbuf, sizeof(outbuf), &outlen);
 109         if (rc)
 110                 return rc;
 111         if (outlen < sizeof(outbuf)) {
 112                 netif_err(efx, drv, efx->net_dev,
 113                           "unable to read datapath firmware capabilities\n");
 114                 return -EIO;
 115         }
 116
 117         nic_data->datapath_caps =
 118                 MCDI_DWORD(outbuf, GET_CAPABILITIES_OUT_FLAGS1);
 119
 120         if (!(nic_data->datapath_caps &
 121               (1 << MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN))) {
 122                 netif_err(efx, drv, efx->net_dev,
 123                           "current firmware does not support TSO\n");
 124                 return -ENODEV;
 125         }
 126
 127         if (!(nic_data->datapath_caps &
 128               (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN))) {
 129                 netif_err(efx, probe, efx->net_dev,
 130                           "current firmware does not support an RX prefix\n");
 131                 return -ENODEV;
 132         }
 133
 134         return 0;
 135 }
 136
 137 static int efx_ef10_get_sysclk_freq(struct efx_nic *efx)
 138 {
 139         MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CLOCK_OUT_LEN);
 140         int rc;
 141
 142         rc = efx_mcdi_rpc(efx, MC_CMD_GET_CLOCK, NULL, 0,
 143                           outbuf, sizeof(outbuf), NULL);
 144         if (rc)
 145                 return rc;
 146         rc = MCDI_DWORD(outbuf, GET_CLOCK_OUT_SYS_FREQ);
 147         return rc > 0 ? rc : -ERANGE;
 148 }
 149
 150 static int efx_ef10_get_mac_address(struct efx_nic *efx, u8 *mac_address)
 151 {
 152         MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_MAC_ADDRESSES_OUT_LEN);
 153         size_t outlen;
 154         int rc;
 155
 156         BUILD_BUG_ON(MC_CMD_GET_MAC_ADDRESSES_IN_LEN != 0);
 157
 158         rc = efx_mcdi_rpc(efx, MC_CMD_GET_MAC_ADDRESSES, NULL, 0,
 159                           outbuf, sizeof(outbuf), &outlen);
 160         if (rc)
 161                 return rc;
 162         if (outlen < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN)
 163                 return -EIO;
 164
 165         ether_addr_copy(mac_address,
 166                         MCDI_PTR(outbuf, GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE));
 167         return 0;
 168 }
 169
 170 static int efx_ef10_probe(struct efx_nic *efx)
 171 {
 172         struct efx_ef10_nic_data *nic_data;
 173         int i, rc;
 174
 175         /* We can have one VI for each 8K region.  However, until we
 176          * use TX option descriptors we need two TX queues per channel.
 177          */
 178         efx->max_channels =
 179                 min_t(unsigned int,
 180                       EFX_MAX_CHANNELS,
 181                       resource_size(&efx->pci_dev->resource[EFX_MEM_BAR]) /
 182                       (EFX_VI_PAGE_SIZE * EFX_TXQ_TYPES));
 183         BUG_ON(efx->max_channels == 0);
 184
 185         nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
 186         if (!nic_data)
 187                 return -ENOMEM;
 188         efx->nic_data = nic_data;
 189
 190         rc = efx_nic_alloc_buffer(efx, &nic_data->mcdi_buf,
 191                                   8 + MCDI_CTL_SDU_LEN_MAX_V2, GFP_KERNEL);
 192         if (rc)
 193                 goto fail1;
 194
 195         /* Get the MC's warm boot count.  In case it's rebooting right
 196          * now, be prepared to retry.
 197          */
 198         i = 0;
 199         for (;;) {
 200                 rc = efx_ef10_get_warm_boot_count(efx);
 201                 if (rc >= 0)
 202                         break;
 203                 if (++i == 5)
 204                         goto fail2;
 205                 ssleep(1);
 206         }
 207         nic_data->warm_boot_count = rc;
 208
 209         nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
 210
 211         /* In case we're recovering from a crash (kexec), we want to
 212          * cancel any outstanding request by the previous user of this
 213          * function.  We send a special message using the least
 214          * significant bits of the 'high' (doorbell) register.
 215          */
 216         _efx_writed(efx, cpu_to_le32(1), ER_DZ_MC_DB_HWRD);
 217
 218         rc = efx_mcdi_init(efx);
 219         if (rc)
 220                 goto fail2;
 221
 222         /* Reset (most) configuration for this function */
 223         rc = efx_mcdi_reset(efx, RESET_TYPE_ALL);
 224         if (rc)
 225                 goto fail3;
 226
 227         /* Enable event logging */
 228         rc = efx_mcdi_log_ctrl(efx, true, false, 0);
 229         if (rc)
 230                 goto fail3;
 231
 232         rc = efx_ef10_init_datapath_caps(efx);
 233         if (rc < 0)
 234                 goto fail3;
 235
 236         efx->rx_packet_len_offset =
 237                 ES_DZ_RX_PREFIX_PKTLEN_OFST - ES_DZ_RX_PREFIX_SIZE;
 238
 239         rc = efx_mcdi_port_get_number(efx);
 240         if (rc < 0)
 241                 goto fail3;
 242         efx->port_num = rc;
 243
 244         rc = efx_ef10_get_mac_address(efx, efx->net_dev->perm_addr);
 245         if (rc)
 246                 goto fail3;
 247
 248         rc = efx_ef10_get_sysclk_freq(efx);
 249         if (rc < 0)
 250                 goto fail3;
 251         efx->timer_quantum_ns = 1536000 / rc; /* 1536 cycles */
 252
 253         /* Check whether firmware supports bug 35388 workaround */
 254         rc = efx_mcdi_set_workaround(efx, MC_CMD_WORKAROUND_BUG35388, true);
 255         if (rc == 0)
 256                 nic_data->workaround_35388 = true;
 257         else if (rc != -ENOSYS && rc != -ENOENT)
 258                 goto fail3;
 259         netif_dbg(efx, probe, efx->net_dev,
 260                   "workaround for bug 35388 is %sabled\n",
 261                   nic_data->workaround_35388 ? "en" : "dis");
 262
 263         rc = efx_mcdi_mon_probe(efx);
 264         if (rc)
 265                 goto fail3;
 266
 267         efx_ptp_probe(efx, NULL);
 268
 269         return 0;
 270
 271 fail3:
 272         efx_mcdi_fini(efx);
 273 fail2:
 274         efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
 275 fail1:
 276         kfree(nic_data);
 277         efx->nic_data = NULL;
 278         return rc;
 279 }
 280
 281 static int efx_ef10_free_vis(struct efx_nic *efx)
 282 {
 283         MCDI_DECLARE_BUF_OUT_OR_ERR(outbuf, 0);
 284         size_t outlen;
 285         int rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FREE_VIS, NULL, 0,
 286                                     outbuf, sizeof(outbuf), &outlen);
 287
 288         /* -EALREADY means nothing to free, so ignore */
 289         if (rc == -EALREADY)
 290                 rc = 0;
 291         if (rc)
 292                 efx_mcdi_display_error(efx, MC_CMD_FREE_VIS, 0, outbuf, outlen,
 293                                        rc);
 294         return rc;
 295 }
 296
 297 #ifdef EFX_USE_PIO
 298
 299 static void efx_ef10_free_piobufs(struct efx_nic *efx)
 300 {
 301         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 302         MCDI_DECLARE_BUF(inbuf, MC_CMD_FREE_PIOBUF_IN_LEN);
 303         unsigned int i;
 304         int rc;
 305
 306         BUILD_BUG_ON(MC_CMD_FREE_PIOBUF_OUT_LEN != 0);
 307
 308         for (i = 0; i < nic_data->n_piobufs; i++) {
 309                 MCDI_SET_DWORD(inbuf, FREE_PIOBUF_IN_PIOBUF_HANDLE,
 310                                nic_data->piobuf_handle[i]);
 311                 rc = efx_mcdi_rpc(efx, MC_CMD_FREE_PIOBUF, inbuf, sizeof(inbuf),
 312                                   NULL, 0, NULL);
 313                 WARN_ON(rc);
 314         }
 315
 316         nic_data->n_piobufs = 0;
 317 }
 318
 319 static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n)
 320 {
 321         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 322         MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_PIOBUF_OUT_LEN);
 323         unsigned int i;
 324         size_t outlen;
 325         int rc = 0;
 326
 327         BUILD_BUG_ON(MC_CMD_ALLOC_PIOBUF_IN_LEN != 0);
 328
 329         for (i = 0; i < n; i++) {
 330                 rc = efx_mcdi_rpc(efx, MC_CMD_ALLOC_PIOBUF, NULL, 0,
 331                                   outbuf, sizeof(outbuf), &outlen);
 332                 if (rc)
 333                         break;
 334                 if (outlen < MC_CMD_ALLOC_PIOBUF_OUT_LEN) {
 335                         rc = -EIO;
 336                         break;
 337                 }
 338                 nic_data->piobuf_handle[i] =
 339                         MCDI_DWORD(outbuf, ALLOC_PIOBUF_OUT_PIOBUF_HANDLE);
 340                 netif_dbg(efx, probe, efx->net_dev,
 341                           "allocated PIO buffer %u handle %x\n", i,
 342                           nic_data->piobuf_handle[i]);
 343         }
 344
 345         nic_data->n_piobufs = i;
 346         if (rc)
 347                 efx_ef10_free_piobufs(efx);
 348         return rc;
 349 }
 350
 351 static int efx_ef10_link_piobufs(struct efx_nic *efx)
 352 {
 353         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 354         MCDI_DECLARE_BUF(inbuf,
 355                          max(MC_CMD_LINK_PIOBUF_IN_LEN,
 356                              MC_CMD_UNLINK_PIOBUF_IN_LEN));
 357         struct efx_channel *channel;
 358         struct efx_tx_queue *tx_queue;
 359         unsigned int offset, index;
 360         int rc;
 361
 362         BUILD_BUG_ON(MC_CMD_LINK_PIOBUF_OUT_LEN != 0);
 363         BUILD_BUG_ON(MC_CMD_UNLINK_PIOBUF_OUT_LEN != 0);
 364
 365         /* Link a buffer to each VI in the write-combining mapping */
 366         for (index = 0; index < nic_data->n_piobufs; ++index) {
 367                 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_PIOBUF_HANDLE,
 368                                nic_data->piobuf_handle[index]);
 369                 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_TXQ_INSTANCE,
 370                                nic_data->pio_write_vi_base + index);
 371                 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF,
 372                                   inbuf, MC_CMD_LINK_PIOBUF_IN_LEN,
 373                                   NULL, 0, NULL);
 374                 if (rc) {
 375                         netif_err(efx, drv, efx->net_dev,
 376                                   "failed to link VI %u to PIO buffer %u (%d)\n",
 377                                   nic_data->pio_write_vi_base + index, index,
 378                                   rc);
 379                         goto fail;
 380                 }
 381                 netif_dbg(efx, probe, efx->net_dev,
 382                           "linked VI %u to PIO buffer %u\n",
 383                           nic_data->pio_write_vi_base + index, index);
 384         }
 385
 386         /* Link a buffer to each TX queue */
 387         efx_for_each_channel(channel, efx) {
 388                 efx_for_each_channel_tx_queue(tx_queue, channel) {
 389                         /* We assign the PIO buffers to queues in
 390                          * reverse order to allow for the following
 391                          * special case.
 392                          */
 393                         offset = ((efx->tx_channel_offset + efx->n_tx_channels -
 394                                    tx_queue->channel->channel - 1) *
 395                                   efx_piobuf_size);
 396                         index = offset / ER_DZ_TX_PIOBUF_SIZE;
 397                         offset = offset % ER_DZ_TX_PIOBUF_SIZE;
 398
 399                         /* When the host page size is 4K, the first
 400                          * host page in the WC mapping may be within
 401                          * the same VI page as the last TX queue.  We
 402                          * can only link one buffer to each VI.
 403                          */
 404                         if (tx_queue->queue == nic_data->pio_write_vi_base) {
 405                                 BUG_ON(index != 0);
 406                                 rc = 0;
 407                         } else {
 408                                 MCDI_SET_DWORD(inbuf,
 409                                                LINK_PIOBUF_IN_PIOBUF_HANDLE,
 410                                                nic_data->piobuf_handle[index]);
 411                                 MCDI_SET_DWORD(inbuf,
 412                                                LINK_PIOBUF_IN_TXQ_INSTANCE,
 413                                                tx_queue->queue);
 414                                 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF,
 415                                                   inbuf, MC_CMD_LINK_PIOBUF_IN_LEN,
 416                                                   NULL, 0, NULL);
 417                         }
 418
 419                         if (rc) {
 420                                 /* This is non-fatal; the TX path just
 421                                  * won't use PIO for this queue
 422                                  */
 423                                 netif_err(efx, drv, efx->net_dev,
 424                                           "failed to link VI %u to PIO buffer %u (%d)\n",
 425                                           tx_queue->queue, index, rc);
 426                                 tx_queue->piobuf = NULL;
 427                         } else {
 428                                 tx_queue->piobuf =
 429                                         nic_data->pio_write_base +
 430                                         index * EFX_VI_PAGE_SIZE + offset;
 431                                 tx_queue->piobuf_offset = offset;
 432                                 netif_dbg(efx, probe, efx->net_dev,
 433                                           "linked VI %u to PIO buffer %u offset %x addr %p\n",
 434                                           tx_queue->queue, index,
 435                                           tx_queue->piobuf_offset,
 436                                           tx_queue->piobuf);
 437                         }
 438                 }
 439         }
 440
 441         return 0;
 442
 443 fail:
 444         while (index--) {
 445                 MCDI_SET_DWORD(inbuf, UNLINK_PIOBUF_IN_TXQ_INSTANCE,
 446                                nic_data->pio_write_vi_base + index);
 447                 efx_mcdi_rpc(efx, MC_CMD_UNLINK_PIOBUF,
 448                              inbuf, MC_CMD_UNLINK_PIOBUF_IN_LEN,
 449                              NULL, 0, NULL);
 450         }
 451         return rc;
 452 }
 453
 454 #else /* !EFX_USE_PIO */
 455
 456 static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n)
 457 {
 458         return n == 0 ? 0 : -ENOBUFS;
 459 }
 460
 461 static int efx_ef10_link_piobufs(struct efx_nic *efx)
 462 {
 463         return 0;
 464 }
 465
 466 static void efx_ef10_free_piobufs(struct efx_nic *efx)
 467 {
 468 }
 469
 470 #endif /* EFX_USE_PIO */
 471
 472 static void efx_ef10_remove(struct efx_nic *efx)
 473 {
 474         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 475         int rc;
 476
 477         efx_ptp_remove(efx);
 478
 479         efx_mcdi_mon_remove(efx);
 480
 481         efx_ef10_rx_free_indir_table(efx);
 482
 483         if (nic_data->wc_membase)
 484                 iounmap(nic_data->wc_membase);
 485
 486         rc = efx_ef10_free_vis(efx);
 487         WARN_ON(rc != 0);
 488
 489         if (!nic_data->must_restore_piobufs)
 490                 efx_ef10_free_piobufs(efx);
 491
 492         efx_mcdi_fini(efx);
 493         efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
 494         kfree(nic_data);
 495 }
 496
 497 static int efx_ef10_alloc_vis(struct efx_nic *efx,
 498                               unsigned int min_vis, unsigned int max_vis)
 499 {
 500         MCDI_DECLARE_BUF(inbuf, MC_CMD_ALLOC_VIS_IN_LEN);
 501         MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_VIS_OUT_LEN);
 502         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 503         size_t outlen;
 504         int rc;
 505
 506         MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MIN_VI_COUNT, min_vis);
 507         MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MAX_VI_COUNT, max_vis);
 508         rc = efx_mcdi_rpc(efx, MC_CMD_ALLOC_VIS, inbuf, sizeof(inbuf),
 509                           outbuf, sizeof(outbuf), &outlen);
 510         if (rc != 0)
 511                 return rc;
 512
 513         if (outlen < MC_CMD_ALLOC_VIS_OUT_LEN)
 514                 return -EIO;
 515
 516         netif_dbg(efx, drv, efx->net_dev, "base VI is A0x%03x\n",
 517                   MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE));
 518
 519         nic_data->vi_base = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE);
 520         nic_data->n_allocated_vis = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_COUNT);
 521         return 0;
 522 }
 523
 524 /* Note that the failure path of this function does not free
 525  * resources, as this will be done by efx_ef10_remove().
 526  */
 527 static int efx_ef10_dimension_resources(struct efx_nic *efx)
 528 {
 529         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 530         unsigned int uc_mem_map_size, wc_mem_map_size;
 531         unsigned int min_vis, pio_write_vi_base, max_vis;
 532         void __iomem *membase;
 533         int rc;
 534
 535         min_vis = max(efx->n_channels, efx->n_tx_channels * EFX_TXQ_TYPES);
 536
 537 #ifdef EFX_USE_PIO
 538         /* Try to allocate PIO buffers if wanted and if the full
 539          * number of PIO buffers would be sufficient to allocate one
 540          * copy-buffer per TX channel.  Failure is non-fatal, as there
 541          * are only a small number of PIO buffers shared between all
 542          * functions of the controller.
 543          */
 544         if (efx_piobuf_size != 0 &&
 545             ER_DZ_TX_PIOBUF_SIZE / efx_piobuf_size * EF10_TX_PIOBUF_COUNT >=
 546             efx->n_tx_channels) {
 547                 unsigned int n_piobufs =
 548                         DIV_ROUND_UP(efx->n_tx_channels,
 549                                      ER_DZ_TX_PIOBUF_SIZE / efx_piobuf_size);
 550
 551                 rc = efx_ef10_alloc_piobufs(efx, n_piobufs);
 552                 if (rc)
 553                         netif_err(efx, probe, efx->net_dev,
 554                                   "failed to allocate PIO buffers (%d)\n", rc);
 555                 else
 556                         netif_dbg(efx, probe, efx->net_dev,
 557                                   "allocated %u PIO buffers\n", n_piobufs);
 558         }
 559 #else
 560         nic_data->n_piobufs = 0;
 561 #endif
 562
 563         /* PIO buffers should be mapped with write-combining enabled,
 564          * and we want to make single UC and WC mappings rather than
 565          * several of each (in fact that's the only option if host
 566          * page size is >4K).  So we may allocate some extra VIs just
 567          * for writing PIO buffers through.
 568          *
 569          * The UC mapping contains (min_vis - 1) complete VIs and the
 570          * first half of the next VI.  Then the WC mapping begins with
 571          * the second half of this last VI.
 572          */
 573         uc_mem_map_size = PAGE_ALIGN((min_vis - 1) * EFX_VI_PAGE_SIZE +
 574                                      ER_DZ_TX_PIOBUF);
 575         if (nic_data->n_piobufs) {
 576                 /* pio_write_vi_base rounds down to give the number of complete
 577                  * VIs inside the UC mapping.
 578                  */
 579                 pio_write_vi_base = uc_mem_map_size / EFX_VI_PAGE_SIZE;
 580                 wc_mem_map_size = (PAGE_ALIGN((pio_write_vi_base +
 581                                                nic_data->n_piobufs) *
 582                                               EFX_VI_PAGE_SIZE) -
 583                                    uc_mem_map_size);
 584                 max_vis = pio_write_vi_base + nic_data->n_piobufs;
 585         } else {
 586                 pio_write_vi_base = 0;
 587                 wc_mem_map_size = 0;
 588                 max_vis = min_vis;
 589         }
 590
 591         /* In case the last attached driver failed to free VIs, do it now */
 592         rc = efx_ef10_free_vis(efx);
 593         if (rc != 0)
 594                 return rc;
 595
 596         rc = efx_ef10_alloc_vis(efx, min_vis, max_vis);
 597         if (rc != 0)
 598                 return rc;
 599
 600         /* If we didn't get enough VIs to map all the PIO buffers, free the
 601          * PIO buffers
 602          */
 603         if (nic_data->n_piobufs &&
 604             nic_data->n_allocated_vis <
 605             pio_write_vi_base + nic_data->n_piobufs) {
 606                 netif_dbg(efx, probe, efx->net_dev,
 607                           "%u VIs are not sufficient to map %u PIO buffers\n",
 608                           nic_data->n_allocated_vis, nic_data->n_piobufs);
 609                 efx_ef10_free_piobufs(efx);
 610         }
 611
 612         /* Shrink the original UC mapping of the memory BAR */
 613         membase = ioremap_nocache(efx->membase_phys, uc_mem_map_size);
 614         if (!membase) {
 615                 netif_err(efx, probe, efx->net_dev,
 616                           "could not shrink memory BAR to %x\n",
 617                           uc_mem_map_size);
 618                 return -ENOMEM;
 619         }
 620         iounmap(efx->membase);
 621         efx->membase = membase;
 622
 623         /* Set up the WC mapping if needed */
 624         if (wc_mem_map_size) {
 625                 nic_data->wc_membase = ioremap_wc(efx->membase_phys +
 626                                                   uc_mem_map_size,
 627                                                   wc_mem_map_size);
 628                 if (!nic_data->wc_membase) {
 629                         netif_err(efx, probe, efx->net_dev,
 630                                   "could not allocate WC mapping of size %x\n",
 631                                   wc_mem_map_size);
 632                         return -ENOMEM;
 633                 }
 634                 nic_data->pio_write_vi_base = pio_write_vi_base;
 635                 nic_data->pio_write_base =
 636                         nic_data->wc_membase +
 637                         (pio_write_vi_base * EFX_VI_PAGE_SIZE + ER_DZ_TX_PIOBUF -
 638                          uc_mem_map_size);
 639
 640                 rc = efx_ef10_link_piobufs(efx);
 641                 if (rc)
 642                         efx_ef10_free_piobufs(efx);
 643         }
 644
 645         netif_dbg(efx, probe, efx->net_dev,
 646                   "memory BAR at %pa (virtual %p+%x UC, %p+%x WC)\n",
 647                   &efx->membase_phys, efx->membase, uc_mem_map_size,
 648                   nic_data->wc_membase, wc_mem_map_size);
 649
 650         return 0;
 651 }
 652
 653 static int efx_ef10_init_nic(struct efx_nic *efx)
 654 {
 655         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 656         int rc;
 657
 658         if (nic_data->must_check_datapath_caps) {
 659                 rc = efx_ef10_init_datapath_caps(efx);
 660                 if (rc)
 661                         return rc;
 662                 nic_data->must_check_datapath_caps = false;
 663         }
 664
 665         if (nic_data->must_realloc_vis) {
 666                 /* We cannot let the number of VIs change now */
 667                 rc = efx_ef10_alloc_vis(efx, nic_data->n_allocated_vis,
 668                                         nic_data->n_allocated_vis);
 669                 if (rc)
 670                         return rc;
 671                 nic_data->must_realloc_vis = false;
 672         }
 673
 674         if (nic_data->must_restore_piobufs && nic_data->n_piobufs) {
 675                 rc = efx_ef10_alloc_piobufs(efx, nic_data->n_piobufs);
 676                 if (rc == 0) {
 677                         rc = efx_ef10_link_piobufs(efx);
 678                         if (rc)
 679                                 efx_ef10_free_piobufs(efx);
 680                 }
 681
 682                 /* Log an error on failure, but this is non-fatal */
 683                 if (rc)
 684                         netif_err(efx, drv, efx->net_dev,
 685                                   "failed to restore PIO buffers (%d)\n", rc);
 686                 nic_data->must_restore_piobufs = false;
 687         }
 688
 689         efx_ef10_rx_push_rss_config(efx);
 690         return 0;
 691 }
 692
 693 static void efx_ef10_reset_mc_allocations(struct efx_nic *efx)
 694 {
 695         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 696
 697         /* All our allocations have been reset */
 698         nic_data->must_realloc_vis = true;
 699         nic_data->must_restore_filters = true;
 700         nic_data->must_restore_piobufs = true;
 701         nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
 702 }
 703
 704 static int efx_ef10_map_reset_flags(u32 *flags)
 705 {
 706         enum {
 707                 EF10_RESET_PORT = ((ETH_RESET_MAC | ETH_RESET_PHY) <<
 708                                    ETH_RESET_SHARED_SHIFT),
 709                 EF10_RESET_MC = ((ETH_RESET_DMA | ETH_RESET_FILTER |
 710                                   ETH_RESET_OFFLOAD | ETH_RESET_MAC |
 711                                   ETH_RESET_PHY | ETH_RESET_MGMT) <<
 712                                  ETH_RESET_SHARED_SHIFT)
 713         };
 714
 715         /* We assume for now that our PCI function is permitted to
 716          * reset everything.
 717          */
 718
 719         if ((*flags & EF10_RESET_MC) == EF10_RESET_MC) {
 720                 *flags &= ~EF10_RESET_MC;
 721                 return RESET_TYPE_WORLD;
 722         }
 723
 724         if ((*flags & EF10_RESET_PORT) == EF10_RESET_PORT) {
 725                 *flags &= ~EF10_RESET_PORT;
 726                 return RESET_TYPE_ALL;
 727         }
 728
 729         /* no invisible reset implemented */
 730
 731         return -EINVAL;
 732 }
 733
 734 static int efx_ef10_reset(struct efx_nic *efx, enum reset_type reset_type)
 735 {
 736         int rc = efx_mcdi_reset(efx, reset_type);
 737
 738         /* If it was a port reset, trigger reallocation of MC resources.
 739          * Note that on an MC reset nothing needs to be done now because we'll
 740          * detect the MC reset later and handle it then.
 741          * For an FLR, we never get an MC reset event, but the MC has reset all
 742          * resources assigned to us, so we have to trigger reallocation now.
 743          */
 744         if ((reset_type == RESET_TYPE_ALL ||
 745              reset_type == RESET_TYPE_MCDI_TIMEOUT) && !rc)
 746                 efx_ef10_reset_mc_allocations(efx);
 747         return rc;
 748 }
 749
 750 #define EF10_DMA_STAT(ext_name, mcdi_name)                      \
 751         [EF10_STAT_ ## ext_name] =                              \
 752         { #ext_name, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
 753 #define EF10_DMA_INVIS_STAT(int_name, mcdi_name)                \
 754         [EF10_STAT_ ## int_name] =                              \
 755         { NULL, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
 756 #define EF10_OTHER_STAT(ext_name)                               \
 757         [EF10_STAT_ ## ext_name] = { #ext_name, 0, 0 }
 758 #define GENERIC_SW_STAT(ext_name)                               \
 759         [GENERIC_STAT_ ## ext_name] = { #ext_name, 0, 0 }
 760
 761 static const struct efx_hw_stat_desc efx_ef10_stat_desc[EF10_STAT_COUNT] = {
 762         EF10_DMA_STAT(tx_bytes, TX_BYTES),
 763         EF10_DMA_STAT(tx_packets, TX_PKTS),
 764         EF10_DMA_STAT(tx_pause, TX_PAUSE_PKTS),
 765         EF10_DMA_STAT(tx_control, TX_CONTROL_PKTS),
 766         EF10_DMA_STAT(tx_unicast, TX_UNICAST_PKTS),
 767         EF10_DMA_STAT(tx_multicast, TX_MULTICAST_PKTS),
 768         EF10_DMA_STAT(tx_broadcast, TX_BROADCAST_PKTS),
 769         EF10_DMA_STAT(tx_lt64, TX_LT64_PKTS),
 770         EF10_DMA_STAT(tx_64, TX_64_PKTS),
 771         EF10_DMA_STAT(tx_65_to_127, TX_65_TO_127_PKTS),
 772         EF10_DMA_STAT(tx_128_to_255, TX_128_TO_255_PKTS),
 773         EF10_DMA_STAT(tx_256_to_511, TX_256_TO_511_PKTS),
 774         EF10_DMA_STAT(tx_512_to_1023, TX_512_TO_1023_PKTS),
 775         EF10_DMA_STAT(tx_1024_to_15xx, TX_1024_TO_15XX_PKTS),
 776         EF10_DMA_STAT(tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS),
 777         EF10_DMA_STAT(rx_bytes, RX_BYTES),
 778         EF10_DMA_INVIS_STAT(rx_bytes_minus_good_bytes, RX_BAD_BYTES),
 779         EF10_OTHER_STAT(rx_good_bytes),
 780         EF10_OTHER_STAT(rx_bad_bytes),
 781         EF10_DMA_STAT(rx_packets, RX_PKTS),
 782         EF10_DMA_STAT(rx_good, RX_GOOD_PKTS),
 783         EF10_DMA_STAT(rx_bad, RX_BAD_FCS_PKTS),
 784         EF10_DMA_STAT(rx_pause, RX_PAUSE_PKTS),
 785         EF10_DMA_STAT(rx_control, RX_CONTROL_PKTS),
 786         EF10_DMA_STAT(rx_unicast, RX_UNICAST_PKTS),
 787         EF10_DMA_STAT(rx_multicast, RX_MULTICAST_PKTS),
 788         EF10_DMA_STAT(rx_broadcast, RX_BROADCAST_PKTS),
 789         EF10_DMA_STAT(rx_lt64, RX_UNDERSIZE_PKTS),
 790         EF10_DMA_STAT(rx_64, RX_64_PKTS),
 791         EF10_DMA_STAT(rx_65_to_127, RX_65_TO_127_PKTS),
 792         EF10_DMA_STAT(rx_128_to_255, RX_128_TO_255_PKTS),
 793         EF10_DMA_STAT(rx_256_to_511, RX_256_TO_511_PKTS),
 794         EF10_DMA_STAT(rx_512_to_1023, RX_512_TO_1023_PKTS),
 795         EF10_DMA_STAT(rx_1024_to_15xx, RX_1024_TO_15XX_PKTS),
 796         EF10_DMA_STAT(rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS),
 797         EF10_DMA_STAT(rx_gtjumbo, RX_GTJUMBO_PKTS),
 798         EF10_DMA_STAT(rx_bad_gtjumbo, RX_JABBER_PKTS),
 799         EF10_DMA_STAT(rx_overflow, RX_OVERFLOW_PKTS),
 800         EF10_DMA_STAT(rx_align_error, RX_ALIGN_ERROR_PKTS),
 801         EF10_DMA_STAT(rx_length_error, RX_LENGTH_ERROR_PKTS),
 802         EF10_DMA_STAT(rx_nodesc_drops, RX_NODESC_DROPS),
 803         GENERIC_SW_STAT(rx_nodesc_trunc),
 804         GENERIC_SW_STAT(rx_noskb_drops),
 805         EF10_DMA_STAT(rx_pm_trunc_bb_overflow, PM_TRUNC_BB_OVERFLOW),
 806         EF10_DMA_STAT(rx_pm_discard_bb_overflow, PM_DISCARD_BB_OVERFLOW),
 807         EF10_DMA_STAT(rx_pm_trunc_vfifo_full, PM_TRUNC_VFIFO_FULL),
 808         EF10_DMA_STAT(rx_pm_discard_vfifo_full, PM_DISCARD_VFIFO_FULL),
 809         EF10_DMA_STAT(rx_pm_trunc_qbb, PM_TRUNC_QBB),
 810         EF10_DMA_STAT(rx_pm_discard_qbb, PM_DISCARD_QBB),
 811         EF10_DMA_STAT(rx_pm_discard_mapping, PM_DISCARD_MAPPING),
 812         EF10_DMA_STAT(rx_dp_q_disabled_packets, RXDP_Q_DISABLED_PKTS),
 813         EF10_DMA_STAT(rx_dp_di_dropped_packets, RXDP_DI_DROPPED_PKTS),
 814         EF10_DMA_STAT(rx_dp_streaming_packets, RXDP_STREAMING_PKTS),
 815         EF10_DMA_STAT(rx_dp_hlb_fetch, RXDP_EMERGENCY_FETCH_CONDITIONS),
 816         EF10_DMA_STAT(rx_dp_hlb_wait, RXDP_EMERGENCY_WAIT_CONDITIONS),
 817 };
 818
 819 #define HUNT_COMMON_STAT_MASK ((1ULL << EF10_STAT_tx_bytes) |           \
 820                                (1ULL << EF10_STAT_tx_packets) |         \
 821                                (1ULL << EF10_STAT_tx_pause) |           \
 822                                (1ULL << EF10_STAT_tx_unicast) |         \
 823                                (1ULL << EF10_STAT_tx_multicast) |       \
 824                                (1ULL << EF10_STAT_tx_broadcast) |       \
 825                                (1ULL << EF10_STAT_rx_bytes) |           \
 826                                (1ULL << EF10_STAT_rx_bytes_minus_good_bytes) | \
 827                                (1ULL << EF10_STAT_rx_good_bytes) |      \
 828                                (1ULL << EF10_STAT_rx_bad_bytes) |       \
 829                                (1ULL << EF10_STAT_rx_packets) |         \
 830                                (1ULL << EF10_STAT_rx_good) |            \
 831                                (1ULL << EF10_STAT_rx_bad) |             \
 832                                (1ULL << EF10_STAT_rx_pause) |           \
 833                                (1ULL << EF10_STAT_rx_control) |         \
 834                                (1ULL << EF10_STAT_rx_unicast) |         \
 835                                (1ULL << EF10_STAT_rx_multicast) |       \
 836                                (1ULL << EF10_STAT_rx_broadcast) |       \
 837                                (1ULL << EF10_STAT_rx_lt64) |            \
 838                                (1ULL << EF10_STAT_rx_64) |              \
 839                                (1ULL << EF10_STAT_rx_65_to_127) |       \
 840                                (1ULL << EF10_STAT_rx_128_to_255) |      \
 841                                (1ULL << EF10_STAT_rx_256_to_511) |      \
 842                                (1ULL << EF10_STAT_rx_512_to_1023) |     \
 843                                (1ULL << EF10_STAT_rx_1024_to_15xx) |    \
 844                                (1ULL << EF10_STAT_rx_15xx_to_jumbo) |   \
 845                                (1ULL << EF10_STAT_rx_gtjumbo) |         \
 846                                (1ULL << EF10_STAT_rx_bad_gtjumbo) |     \
 847                                (1ULL << EF10_STAT_rx_overflow) |        \
 848                                (1ULL << EF10_STAT_rx_nodesc_drops) |    \
 849                                (1ULL << GENERIC_STAT_rx_nodesc_trunc) | \
 850                                (1ULL << GENERIC_STAT_rx_noskb_drops))
 851
 852 /* These statistics are only provided by the 10G MAC.  For a 10G/40G
 853  * switchable port we do not expose these because they might not
 854  * include all the packets they should.
 855  */
 856 #define HUNT_10G_ONLY_STAT_MASK ((1ULL << EF10_STAT_tx_control) |       \
 857                                  (1ULL << EF10_STAT_tx_lt64) |          \
 858                                  (1ULL << EF10_STAT_tx_64) |            \
 859                                  (1ULL << EF10_STAT_tx_65_to_127) |     \
 860                                  (1ULL << EF10_STAT_tx_128_to_255) |    \
 861                                  (1ULL << EF10_STAT_tx_256_to_511) |    \
 862                                  (1ULL << EF10_STAT_tx_512_to_1023) |   \
 863                                  (1ULL << EF10_STAT_tx_1024_to_15xx) |  \
 864                                  (1ULL << EF10_STAT_tx_15xx_to_jumbo))
 865
 866 /* These statistics are only provided by the 40G MAC.  For a 10G/40G
 867  * switchable port we do expose these because the errors will otherwise
 868  * be silent.
 869  */
 870 #define HUNT_40G_EXTRA_STAT_MASK ((1ULL << EF10_STAT_rx_align_error) |  \
 871                                   (1ULL << EF10_STAT_rx_length_error))
 872
 873 /* These statistics are only provided if the firmware supports the
 874  * capability PM_AND_RXDP_COUNTERS.
 875  */
 876 #define HUNT_PM_AND_RXDP_STAT_MASK (                                    \
 877         (1ULL << EF10_STAT_rx_pm_trunc_bb_overflow) |                   \
 878         (1ULL << EF10_STAT_rx_pm_discard_bb_overflow) |                 \
 879         (1ULL << EF10_STAT_rx_pm_trunc_vfifo_full) |                    \
 880         (1ULL << EF10_STAT_rx_pm_discard_vfifo_full) |                  \
 881         (1ULL << EF10_STAT_rx_pm_trunc_qbb) |                           \
 882         (1ULL << EF10_STAT_rx_pm_discard_qbb) |                         \
 883         (1ULL << EF10_STAT_rx_pm_discard_mapping) |                     \
 884         (1ULL << EF10_STAT_rx_dp_q_disabled_packets) |                  \
 885         (1ULL << EF10_STAT_rx_dp_di_dropped_packets) |                  \
 886         (1ULL << EF10_STAT_rx_dp_streaming_packets) |                   \
 887         (1ULL << EF10_STAT_rx_dp_hlb_fetch) |                           \
 888         (1ULL << EF10_STAT_rx_dp_hlb_wait))
 889
 890 static u64 efx_ef10_raw_stat_mask(struct efx_nic *efx)
 891 {
 892         u64 raw_mask = HUNT_COMMON_STAT_MASK;
 893         u32 port_caps = efx_mcdi_phy_get_caps(efx);
 894         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 895
 896         if (port_caps & (1 << MC_CMD_PHY_CAP_40000FDX_LBN))
 897                 raw_mask |= HUNT_40G_EXTRA_STAT_MASK;
 898         else
 899                 raw_mask |= HUNT_10G_ONLY_STAT_MASK;
 900
 901         if (nic_data->datapath_caps &
 902             (1 << MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_LBN))
 903                 raw_mask |= HUNT_PM_AND_RXDP_STAT_MASK;
 904
 905         return raw_mask;
 906 }
 907
 908 static void efx_ef10_get_stat_mask(struct efx_nic *efx, unsigned long *mask)
 909 {
 910         u64 raw_mask = efx_ef10_raw_stat_mask(efx);
 911
 912 #if BITS_PER_LONG == 64
 913         mask[0] = raw_mask;
 914 #else
 915         mask[0] = raw_mask & 0xffffffff;
 916         mask[1] = raw_mask >> 32;
 917 #endif
 918 }
 919
 920 static size_t efx_ef10_describe_stats(struct efx_nic *efx, u8 *names)
 921 {
 922         DECLARE_BITMAP(mask, EF10_STAT_COUNT);
 923
 924         efx_ef10_get_stat_mask(efx, mask);
 925         return efx_nic_describe_stats(efx_ef10_stat_desc, EF10_STAT_COUNT,
 926                                       mask, names);
 927 }
 928
 929 static int efx_ef10_try_update_nic_stats(struct efx_nic *efx)
 930 {
 931         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 932         DECLARE_BITMAP(mask, EF10_STAT_COUNT);
 933         __le64 generation_start, generation_end;
 934         u64 *stats = nic_data->stats;
 935         __le64 *dma_stats;
 936
 937         efx_ef10_get_stat_mask(efx, mask);
 938
 939         dma_stats = efx->stats_buffer.addr;
 940         nic_data = efx->nic_data;
 941
 942         generation_end = dma_stats[MC_CMD_MAC_GENERATION_END];
 943         if (generation_end == EFX_MC_STATS_GENERATION_INVALID)
 944                 return 0;
 945         rmb();
 946         efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask,
 947                              stats, efx->stats_buffer.addr, false);
 948         rmb();
 949         generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
 950         if (generation_end != generation_start)
 951                 return -EAGAIN;
 952
 953         /* Update derived statistics */
 954         efx_nic_fix_nodesc_drop_stat(efx, &stats[EF10_STAT_rx_nodesc_drops]);
 955         stats[EF10_STAT_rx_good_bytes] =
 956                 stats[EF10_STAT_rx_bytes] -
 957                 stats[EF10_STAT_rx_bytes_minus_good_bytes];
 958         efx_update_diff_stat(&stats[EF10_STAT_rx_bad_bytes],
 959                              stats[EF10_STAT_rx_bytes_minus_good_bytes]);
 960         efx_update_sw_stats(efx, stats);
 961         return 0;
 962 }
 963
 964
 965 static size_t efx_ef10_update_stats(struct efx_nic *efx, u64 *full_stats,
 966                                     struct rtnl_link_stats64 *core_stats)
 967 {
 968         DECLARE_BITMAP(mask, EF10_STAT_COUNT);
 969         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 970         u64 *stats = nic_data->stats;
 971         size_t stats_count = 0, index;
 972         int retry;
 973
 974         efx_ef10_get_stat_mask(efx, mask);
 975
 976         /* If we're unlucky enough to read statistics during the DMA, wait
 977          * up to 10ms for it to finish (typically takes <500us)
 978          */
 979         for (retry = 0; retry < 100; ++retry) {
 980                 if (efx_ef10_try_update_nic_stats(efx) == 0)
 981                         break;
 982                 udelay(100);
 983         }
 984
 985         if (full_stats) {
 986                 for_each_set_bit(index, mask, EF10_STAT_COUNT) {
 987                         if (efx_ef10_stat_desc[index].name) {
 988                                 *full_stats++ = stats[index];
 989                                 ++stats_count;
 990                         }
 991                 }
 992         }
 993
 994         if (core_stats) {
 995                 core_stats->rx_packets = stats[EF10_STAT_rx_packets];
 996                 core_stats->tx_packets = stats[EF10_STAT_tx_packets];
 997                 core_stats->rx_bytes = stats[EF10_STAT_rx_bytes];
 998                 core_stats->tx_bytes = stats[EF10_STAT_tx_bytes];
 999                 core_stats->rx_dropped = stats[EF10_STAT_rx_nodesc_drops] +
1000                                          stats[GENERIC_STAT_rx_nodesc_trunc] +
1001                                          stats[GENERIC_STAT_rx_noskb_drops];
1002                 core_stats->multicast = stats[EF10_STAT_rx_multicast];
1003                 core_stats->rx_length_errors =
1004                         stats[EF10_STAT_rx_gtjumbo] +
1005                         stats[EF10_STAT_rx_length_error];
1006                 core_stats->rx_crc_errors = stats[EF10_STAT_rx_bad];
1007                 core_stats->rx_frame_errors = stats[EF10_STAT_rx_align_error];
1008                 core_stats->rx_fifo_errors = stats[EF10_STAT_rx_overflow];
1009                 core_stats->rx_errors = (core_stats->rx_length_errors +
1010                                          core_stats->rx_crc_errors +
1011                                          core_stats->rx_frame_errors);
1012         }
1013
1014         return stats_count;
1015 }
1016
1017 static void efx_ef10_push_irq_moderation(struct efx_channel *channel)
1018 {
1019         struct efx_nic *efx = channel->efx;
1020         unsigned int mode, value;
1021         efx_dword_t timer_cmd;
1022
1023         if (channel->irq_moderation) {
1024                 mode = 3;
1025                 value = channel->irq_moderation - 1;
1026         } else {
1027                 mode = 0;
1028                 value = 0;
1029         }
1030
1031         if (EFX_EF10_WORKAROUND_35388(efx)) {
1032                 EFX_POPULATE_DWORD_3(timer_cmd, ERF_DD_EVQ_IND_TIMER_FLAGS,
1033                                      EFE_DD_EVQ_IND_TIMER_FLAGS,
1034                                      ERF_DD_EVQ_IND_TIMER_MODE, mode,
1035                                      ERF_DD_EVQ_IND_TIMER_VAL, value);
1036                 efx_writed_page(efx, &timer_cmd, ER_DD_EVQ_INDIRECT,
1037                                 channel->channel);
1038         } else {
1039                 EFX_POPULATE_DWORD_2(timer_cmd, ERF_DZ_TC_TIMER_MODE, mode,
1040                                      ERF_DZ_TC_TIMER_VAL, value);
1041                 efx_writed_page(efx, &timer_cmd, ER_DZ_EVQ_TMR,
1042                                 channel->channel);
1043         }
1044 }
1045
1046 static void efx_ef10_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol)
1047 {
1048         wol->supported = 0;
1049         wol->wolopts = 0;
1050         memset(&wol->sopass, 0, sizeof(wol->sopass));
1051 }
1052
1053 static int efx_ef10_set_wol(struct efx_nic *efx, u32 type)
1054 {
1055         if (type != 0)
1056                 return -EINVAL;
1057         return 0;
1058 }
1059
1060 static void efx_ef10_mcdi_request(struct efx_nic *efx,
1061                                   const efx_dword_t *hdr, size_t hdr_len,
1062                                   const efx_dword_t *sdu, size_t sdu_len)
1063 {
1064         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1065         u8 *pdu = nic_data->mcdi_buf.addr;
1066
1067         memcpy(pdu, hdr, hdr_len);
1068         memcpy(pdu + hdr_len, sdu, sdu_len);
1069         wmb();
1070
1071         /* The hardware provides 'low' and 'high' (doorbell) registers
1072          * for passing the 64-bit address of an MCDI request to
1073          * firmware.  However the dwords are swapped by firmware.  The
1074          * least significant bits of the doorbell are then 0 for all
1075          * MCDI requests due to alignment.
1076          */
1077         _efx_writed(efx, cpu_to_le32((u64)nic_data->mcdi_buf.dma_addr >> 32),
1078                     ER_DZ_MC_DB_LWRD);
1079         _efx_writed(efx, cpu_to_le32((u32)nic_data->mcdi_buf.dma_addr),
1080                     ER_DZ_MC_DB_HWRD);
1081 }
1082
1083 static bool efx_ef10_mcdi_poll_response(struct efx_nic *efx)
1084 {
1085         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1086         const efx_dword_t hdr = *(const efx_dword_t *)nic_data->mcdi_buf.addr;
1087
1088         rmb();
1089         return EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE);
1090 }
1091
1092 static void
1093 efx_ef10_mcdi_read_response(struct efx_nic *efx, efx_dword_t *outbuf,
1094                             size_t offset, size_t outlen)
1095 {
1096         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1097         const u8 *pdu = nic_data->mcdi_buf.addr;
1098
1099         memcpy(outbuf, pdu + offset, outlen);
1100 }
1101
1102 static int efx_ef10_mcdi_poll_reboot(struct efx_nic *efx)
1103 {
1104         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1105         int rc;
1106
1107         rc = efx_ef10_get_warm_boot_count(efx);
1108         if (rc < 0) {
1109                 /* The firmware is presumably in the process of
1110                  * rebooting.  However, we are supposed to report each
1111                  * reboot just once, so we must only do that once we
1112                  * can read and store the updated warm boot count.
1113                  */
1114                 return 0;
1115         }
1116
1117         if (rc == nic_data->warm_boot_count)
1118                 return 0;
1119
1120         nic_data->warm_boot_count = rc;
1121
1122         /* All our allocations have been reset */
1123         efx_ef10_reset_mc_allocations(efx);
1124
1125         /* The datapath firmware might have been changed */
1126         nic_data->must_check_datapath_caps = true;
1127
1128         /* MAC statistics have been cleared on the NIC; clear the local
1129          * statistic that we update with efx_update_diff_stat().
1130          */
1131         nic_data->stats[EF10_STAT_rx_bad_bytes] = 0;
1132
1133         return -EIO;
1134 }
1135
1136 /* Handle an MSI interrupt
1137  *
1138  * Handle an MSI hardware interrupt.  This routine schedules event
1139  * queue processing.  No interrupt acknowledgement cycle is necessary.
1140  * Also, we never need to check that the interrupt is for us, since
1141  * MSI interrupts cannot be shared.
1142  */
1143 static irqreturn_t efx_ef10_msi_interrupt(int irq, void *dev_id)
1144 {
1145         struct efx_msi_context *context = dev_id;
1146         struct efx_nic *efx = context->efx;
1147
1148         netif_vdbg(efx, intr, efx->net_dev,
1149                    "IRQ %d on CPU %d\n", irq, raw_smp_processor_id());
1150
1151         if (likely(ACCESS_ONCE(efx->irq_soft_enabled))) {
1152                 /* Note test interrupts */
1153                 if (context->index == efx->irq_level)
1154                         efx->last_irq_cpu = raw_smp_processor_id();
1155
1156                 /* Schedule processing of the channel */
1157                 efx_schedule_channel_irq(efx->channel[context->index]);
1158         }
1159
1160         return IRQ_HANDLED;
1161 }
1162
1163 static irqreturn_t efx_ef10_legacy_interrupt(int irq, void *dev_id)
1164 {
1165         struct efx_nic *efx = dev_id;
1166         bool soft_enabled = ACCESS_ONCE(efx->irq_soft_enabled);
1167         struct efx_channel *channel;
1168         efx_dword_t reg;
1169         u32 queues;
1170
1171         /* Read the ISR which also ACKs the interrupts */
1172         efx_readd(efx, &reg, ER_DZ_BIU_INT_ISR);
1173         queues = EFX_DWORD_FIELD(reg, ERF_DZ_ISR_REG);
1174
1175         if (queues == 0)
1176                 return IRQ_NONE;
1177
1178         if (likely(soft_enabled)) {
1179                 /* Note test interrupts */
1180                 if (queues & (1U << efx->irq_level))
1181                         efx->last_irq_cpu = raw_smp_processor_id();
1182
1183                 efx_for_each_channel(channel, efx) {
1184                         if (queues & 1)
1185                                 efx_schedule_channel_irq(channel);
1186                         queues >>= 1;
1187                 }
1188         }
1189
1190         netif_vdbg(efx, intr, efx->net_dev,
1191                    "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n",
1192                    irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg));
1193
1194         return IRQ_HANDLED;
1195 }
1196
1197 static void efx_ef10_irq_test_generate(struct efx_nic *efx)
1198 {
1199         MCDI_DECLARE_BUF(inbuf, MC_CMD_TRIGGER_INTERRUPT_IN_LEN);
1200
1201         BUILD_BUG_ON(MC_CMD_TRIGGER_INTERRUPT_OUT_LEN != 0);
1202
1203         MCDI_SET_DWORD(inbuf, TRIGGER_INTERRUPT_IN_INTR_LEVEL, efx->irq_level);
1204         (void) efx_mcdi_rpc(efx, MC_CMD_TRIGGER_INTERRUPT,
1205                             inbuf, sizeof(inbuf), NULL, 0, NULL);
1206 }
1207
1208 static int efx_ef10_tx_probe(struct efx_tx_queue *tx_queue)
1209 {
1210         return efx_nic_alloc_buffer(tx_queue->efx, &tx_queue->txd.buf,
1211                                     (tx_queue->ptr_mask + 1) *
1212                                     sizeof(efx_qword_t),
1213                                     GFP_KERNEL);
1214 }
1215
1216 /* This writes to the TX_DESC_WPTR and also pushes data */
1217 static inline void efx_ef10_push_tx_desc(struct efx_tx_queue *tx_queue,
1218                                          const efx_qword_t *txd)
1219 {
1220         unsigned int write_ptr;
1221         efx_oword_t reg;
1222
1223         write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
1224         EFX_POPULATE_OWORD_1(reg, ERF_DZ_TX_DESC_WPTR, write_ptr);
1225         reg.qword[0] = *txd;
1226         efx_writeo_page(tx_queue->efx, &reg,
1227                         ER_DZ_TX_DESC_UPD, tx_queue->queue);
1228 }
1229
1230 static void efx_ef10_tx_init(struct efx_tx_queue *tx_queue)
1231 {
1232         MCDI_DECLARE_BUF(inbuf, MC_CMD_INIT_TXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 /
1233                                                        EFX_BUF_SIZE));
1234         MCDI_DECLARE_BUF(outbuf, MC_CMD_INIT_TXQ_OUT_LEN);
1235         bool csum_offload = tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD;
1236         size_t entries = tx_queue->txd.buf.len / EFX_BUF_SIZE;
1237         struct efx_channel *channel = tx_queue->channel;
1238         struct efx_nic *efx = tx_queue->efx;
1239         size_t inlen, outlen;
1240         dma_addr_t dma_addr;
1241         efx_qword_t *txd;
1242         int rc;
1243         int i;
1244
1245         MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_SIZE, tx_queue->ptr_mask + 1);
1246         MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_TARGET_EVQ, channel->channel);
1247         MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_LABEL, tx_queue->queue);
1248         MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_INSTANCE, tx_queue->queue);
1249         MCDI_POPULATE_DWORD_2(inbuf, INIT_TXQ_IN_FLAGS,
1250                               INIT_TXQ_IN_FLAG_IP_CSUM_DIS, !csum_offload,
1251                               INIT_TXQ_IN_FLAG_TCP_CSUM_DIS, !csum_offload);
1252         MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_OWNER_ID, 0);
1253         MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_PORT_ID, EVB_PORT_ID_ASSIGNED);
1254
1255         dma_addr = tx_queue->txd.buf.dma_addr;
1256
1257         netif_dbg(efx, hw, efx->net_dev, "pushing TXQ %d. %zu entries (%llx)\n",
1258                   tx_queue->queue, entries, (u64)dma_addr);
1259
1260         for (i = 0; i < entries; ++i) {
1261                 MCDI_SET_ARRAY_QWORD(inbuf, INIT_TXQ_IN_DMA_ADDR, i, dma_addr);
1262                 dma_addr += EFX_BUF_SIZE;
1263         }
1264
1265         inlen = MC_CMD_INIT_TXQ_IN_LEN(entries);
1266
1267         rc = efx_mcdi_rpc(efx, MC_CMD_INIT_TXQ, inbuf, inlen,
1268                           outbuf, sizeof(outbuf), &outlen);
1269         if (rc)
1270                 goto fail;
1271
1272         /* A previous user of this TX queue might have set us up the
1273          * bomb by writing a descriptor to the TX push collector but
1274          * not the doorbell.  (Each collector belongs to a port, not a
1275          * queue or function, so cannot easily be reset.)  We must
1276          * attempt to push a no-op descriptor in its place.
1277          */
1278         tx_queue->buffer[0].flags = EFX_TX_BUF_OPTION;
1279         tx_queue->insert_count = 1;
1280         txd = efx_tx_desc(tx_queue, 0);
1281         EFX_POPULATE_QWORD_4(*txd,
1282                              ESF_DZ_TX_DESC_IS_OPT, true,
1283                              ESF_DZ_TX_OPTION_TYPE,
1284                              ESE_DZ_TX_OPTION_DESC_CRC_CSUM,
1285                              ESF_DZ_TX_OPTION_UDP_TCP_CSUM, csum_offload,
1286                              ESF_DZ_TX_OPTION_IP_CSUM, csum_offload);
1287         tx_queue->write_count = 1;
1288         wmb();
1289         efx_ef10_push_tx_desc(tx_queue, txd);
1290
1291         return;
1292
1293 fail:
1294         netdev_WARN(efx->net_dev, "failed to initialise TXQ %d\n",
1295                     tx_queue->queue);
1296 }
1297
1298 static void efx_ef10_tx_fini(struct efx_tx_queue *tx_queue)
1299 {
1300         MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_TXQ_IN_LEN);
1301         MCDI_DECLARE_BUF(outbuf, MC_CMD_FINI_TXQ_OUT_LEN);
1302         struct efx_nic *efx = tx_queue->efx;
1303         size_t outlen;
1304         int rc;
1305
1306         MCDI_SET_DWORD(inbuf, FINI_TXQ_IN_INSTANCE,
1307                        tx_queue->queue);
1308
1309         rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_TXQ, inbuf, sizeof(inbuf),
1310                           outbuf, sizeof(outbuf), &outlen);
1311
1312         if (rc && rc != -EALREADY)
1313                 goto fail;
1314
1315         return;
1316
1317 fail:
1318         efx_mcdi_display_error(efx, MC_CMD_FINI_TXQ, MC_CMD_FINI_TXQ_IN_LEN,
1319                                outbuf, outlen, rc);
1320 }
1321
1322 static void efx_ef10_tx_remove(struct efx_tx_queue *tx_queue)
1323 {
1324         efx_nic_free_buffer(tx_queue->efx, &tx_queue->txd.buf);
1325 }
1326
1327 /* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
1328 static inline void efx_ef10_notify_tx_desc(struct efx_tx_queue *tx_queue)
1329 {
1330         unsigned int write_ptr;
1331         efx_dword_t reg;
1332
1333         write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
1334         EFX_POPULATE_DWORD_1(reg, ERF_DZ_TX_DESC_WPTR_DWORD, write_ptr);
1335         efx_writed_page(tx_queue->efx, &reg,
1336                         ER_DZ_TX_DESC_UPD_DWORD, tx_queue->queue);
1337 }
1338
1339 static void efx_ef10_tx_write(struct efx_tx_queue *tx_queue)
1340 {
1341         unsigned int old_write_count = tx_queue->write_count;
1342         struct efx_tx_buffer *buffer;
1343         unsigned int write_ptr;
1344         efx_qword_t *txd;
1345
1346         BUG_ON(tx_queue->write_count == tx_queue->insert_count);
1347
1348         do {
1349                 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
1350                 buffer = &tx_queue->buffer[write_ptr];
1351                 txd = efx_tx_desc(tx_queue, write_ptr);
1352                 ++tx_queue->write_count;
1353
1354                 /* Create TX descriptor ring entry */
1355                 if (buffer->flags & EFX_TX_BUF_OPTION) {
1356                         *txd = buffer->option;
1357                 } else {
1358                         BUILD_BUG_ON(EFX_TX_BUF_CONT != 1);
1359                         EFX_POPULATE_QWORD_3(
1360                                 *txd,
1361                                 ESF_DZ_TX_KER_CONT,
1362                                 buffer->flags & EFX_TX_BUF_CONT,
1363                                 ESF_DZ_TX_KER_BYTE_CNT, buffer->len,
1364                                 ESF_DZ_TX_KER_BUF_ADDR, buffer->dma_addr);
1365                 }
1366         } while (tx_queue->write_count != tx_queue->insert_count);
1367
1368         wmb(); /* Ensure descriptors are written before they are fetched */
1369
1370         if (efx_nic_may_push_tx_desc(tx_queue, old_write_count)) {
1371                 txd = efx_tx_desc(tx_queue,
1372                                   old_write_count & tx_queue->ptr_mask);
1373                 efx_ef10_push_tx_desc(tx_queue, txd);
1374                 ++tx_queue->pushes;
1375         } else {
1376                 efx_ef10_notify_tx_desc(tx_queue);
1377         }
1378 }
1379
1380 static int efx_ef10_alloc_rss_context(struct efx_nic *efx, u32 *context)
1381 {
1382         MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN);
1383         MCDI_DECLARE_BUF(outbuf, MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN);
1384         size_t outlen;
1385         int rc;
1386
1387         MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID,
1388                        EVB_PORT_ID_ASSIGNED);
1389         MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_TYPE,
1390                        MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE);
1391         MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_NUM_QUEUES,
1392                        EFX_MAX_CHANNELS);
1393
1394         rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_ALLOC, inbuf, sizeof(inbuf),
1395                 outbuf, sizeof(outbuf), &outlen);
1396         if (rc != 0)
1397                 return rc;
1398
1399         if (outlen < MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN)
1400                 return -EIO;
1401
1402         *context = MCDI_DWORD(outbuf, RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID);
1403
1404         return 0;
1405 }
1406
1407 static void efx_ef10_free_rss_context(struct efx_nic *efx, u32 context)
1408 {
1409         MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_FREE_IN_LEN);
1410         int rc;
1411
1412         MCDI_SET_DWORD(inbuf, RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID,
1413                        context);
1414
1415         rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_FREE, inbuf, sizeof(inbuf),
1416                             NULL, 0, NULL);
1417         WARN_ON(rc != 0);
1418 }
1419
1420 static int efx_ef10_populate_rss_table(struct efx_nic *efx, u32 context)
1421 {
1422         MCDI_DECLARE_BUF(tablebuf, MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN);
1423         MCDI_DECLARE_BUF(keybuf, MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN);
1424         int i, rc;
1425
1426         MCDI_SET_DWORD(tablebuf, RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID,
1427                        context);
1428         BUILD_BUG_ON(ARRAY_SIZE(efx->rx_indir_table) !=
1429                      MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_LEN);
1430
1431         for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); ++i)
1432                 MCDI_PTR(tablebuf,
1433                          RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE)[i] =
1434                                 (u8) efx->rx_indir_table[i];
1435
1436         rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_TABLE, tablebuf,
1437                           sizeof(tablebuf), NULL, 0, NULL);
1438         if (rc != 0)
1439                 return rc;
1440
1441         MCDI_SET_DWORD(keybuf, RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID,
1442                        context);
1443         BUILD_BUG_ON(ARRAY_SIZE(efx->rx_hash_key) !=
1444                      MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN);
1445         for (i = 0; i < ARRAY_SIZE(efx->rx_hash_key); ++i)
1446                 MCDI_PTR(keybuf, RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY)[i] =
1447                         efx->rx_hash_key[i];
1448
1449         return efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_KEY, keybuf,
1450                             sizeof(keybuf), NULL, 0, NULL);
1451 }
1452
1453 static void efx_ef10_rx_free_indir_table(struct efx_nic *efx)
1454 {
1455         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1456
1457         if (nic_data->rx_rss_context != EFX_EF10_RSS_CONTEXT_INVALID)
1458                 efx_ef10_free_rss_context(efx, nic_data->rx_rss_context);
1459         nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
1460 }
1461
1462 static void efx_ef10_rx_push_rss_config(struct efx_nic *efx)
1463 {
1464         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1465         int rc;
1466
1467         netif_dbg(efx, drv, efx->net_dev, "pushing RSS config\n");
1468
1469         if (nic_data->rx_rss_context == EFX_EF10_RSS_CONTEXT_INVALID) {
1470                 rc = efx_ef10_alloc_rss_context(efx, &nic_data->rx_rss_context);
1471                 if (rc != 0)
1472                         goto fail;
1473         }
1474
1475         rc = efx_ef10_populate_rss_table(efx, nic_data->rx_rss_context);
1476         if (rc != 0)
1477                 goto fail;
1478
1479         return;
1480
1481 fail:
1482         netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
1483 }
1484
1485 static int efx_ef10_rx_probe(struct efx_rx_queue *rx_queue)
1486 {
1487         return efx_nic_alloc_buffer(rx_queue->efx, &rx_queue->rxd.buf,
1488                                     (rx_queue->ptr_mask + 1) *
1489                                     sizeof(efx_qword_t),
1490                                     GFP_KERNEL);
1491 }
1492
1493 static void efx_ef10_rx_init(struct efx_rx_queue *rx_queue)
1494 {
1495         MCDI_DECLARE_BUF(inbuf,
1496                          MC_CMD_INIT_RXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 /
1497                                                 EFX_BUF_SIZE));
1498         MCDI_DECLARE_BUF(outbuf, MC_CMD_INIT_RXQ_OUT_LEN);
1499         struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
1500         size_t entries = rx_queue->rxd.buf.len / EFX_BUF_SIZE;
1501         struct efx_nic *efx = rx_queue->efx;
1502         size_t inlen, outlen;
1503         dma_addr_t dma_addr;
1504         int rc;
1505         int i;
1506
1507         rx_queue->scatter_n = 0;
1508         rx_queue->scatter_len = 0;
1509
1510         MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_SIZE, rx_queue->ptr_mask + 1);
1511         MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_TARGET_EVQ, channel->channel);
1512         MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_LABEL, efx_rx_queue_index(rx_queue));
1513         MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_INSTANCE,
1514                        efx_rx_queue_index(rx_queue));
1515         MCDI_POPULATE_DWORD_2(inbuf, INIT_RXQ_IN_FLAGS,
1516                               INIT_RXQ_IN_FLAG_PREFIX, 1,
1517                               INIT_RXQ_IN_FLAG_TIMESTAMP, 1);
1518         MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_OWNER_ID, 0);
1519         MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_PORT_ID, EVB_PORT_ID_ASSIGNED);
1520
1521         dma_addr = rx_queue->rxd.buf.dma_addr;
1522
1523         netif_dbg(efx, hw, efx->net_dev, "pushing RXQ %d. %zu entries (%llx)\n",
1524                   efx_rx_queue_index(rx_queue), entries, (u64)dma_addr);
1525
1526         for (i = 0; i < entries; ++i) {
1527                 MCDI_SET_ARRAY_QWORD(inbuf, INIT_RXQ_IN_DMA_ADDR, i, dma_addr);
1528                 dma_addr += EFX_BUF_SIZE;
1529         }
1530
1531         inlen = MC_CMD_INIT_RXQ_IN_LEN(entries);
1532
1533         rc = efx_mcdi_rpc(efx, MC_CMD_INIT_RXQ, inbuf, inlen,
1534                           outbuf, sizeof(outbuf), &outlen);
1535         if (rc)
1536                 netdev_WARN(efx->net_dev, "failed to initialise RXQ %d\n",
1537                             efx_rx_queue_index(rx_queue));
1538 }
1539
1540 static void efx_ef10_rx_fini(struct efx_rx_queue *rx_queue)
1541 {
1542         MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_RXQ_IN_LEN);
1543         MCDI_DECLARE_BUF(outbuf, MC_CMD_FINI_RXQ_OUT_LEN);
1544         struct efx_nic *efx = rx_queue->efx;
1545         size_t outlen;
1546         int rc;
1547
1548         MCDI_SET_DWORD(inbuf, FINI_RXQ_IN_INSTANCE,
1549                        efx_rx_queue_index(rx_queue));
1550
1551         rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_RXQ, inbuf, sizeof(inbuf),
1552                           outbuf, sizeof(outbuf), &outlen);
1553
1554         if (rc && rc != -EALREADY)
1555                 goto fail;
1556
1557         return;
1558
1559 fail:
1560         efx_mcdi_display_error(efx, MC_CMD_FINI_RXQ, MC_CMD_FINI_RXQ_IN_LEN,
1561                                outbuf, outlen, rc);
1562 }
1563
1564 static void efx_ef10_rx_remove(struct efx_rx_queue *rx_queue)
1565 {
1566         efx_nic_free_buffer(rx_queue->efx, &rx_queue->rxd.buf);
1567 }
1568
1569 /* This creates an entry in the RX descriptor queue */
1570 static inline void
1571 efx_ef10_build_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index)
1572 {
1573         struct efx_rx_buffer *rx_buf;
1574         efx_qword_t *rxd;
1575
1576         rxd = efx_rx_desc(rx_queue, index);
1577         rx_buf = efx_rx_buffer(rx_queue, index);
1578         EFX_POPULATE_QWORD_2(*rxd,
1579                              ESF_DZ_RX_KER_BYTE_CNT, rx_buf->len,
1580                              ESF_DZ_RX_KER_BUF_ADDR, rx_buf->dma_addr);
1581 }
1582
1583 static void efx_ef10_rx_write(struct efx_rx_queue *rx_queue)
1584 {
1585         struct efx_nic *efx = rx_queue->efx;
1586         unsigned int write_count;
1587         efx_dword_t reg;
1588
1589         /* Firmware requires that RX_DESC_WPTR be a multiple of 8 */
1590         write_count = rx_queue->added_count & ~7;
1591         if (rx_queue->notified_count == write_count)
1592                 return;
1593
1594         do
1595                 efx_ef10_build_rx_desc(
1596                         rx_queue,
1597                         rx_queue->notified_count & rx_queue->ptr_mask);
1598         while (++rx_queue->notified_count != write_count);
1599
1600         wmb();
1601         EFX_POPULATE_DWORD_1(reg, ERF_DZ_RX_DESC_WPTR,
1602                              write_count & rx_queue->ptr_mask);
1603         efx_writed_page(efx, &reg, ER_DZ_RX_DESC_UPD,
1604                         efx_rx_queue_index(rx_queue));
1605 }
1606
1607 static efx_mcdi_async_completer efx_ef10_rx_defer_refill_complete;
1608
1609 static void efx_ef10_rx_defer_refill(struct efx_rx_queue *rx_queue)
1610 {
1611         struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
1612         MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
1613         efx_qword_t event;
1614
1615         EFX_POPULATE_QWORD_2(event,
1616                              ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV,
1617                              ESF_DZ_EV_DATA, EFX_EF10_REFILL);
1618
1619         MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
1620
1621         /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
1622          * already swapped the data to little-endian order.
1623          */
1624         memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
1625                sizeof(efx_qword_t));
1626
1627         efx_mcdi_rpc_async(channel->efx, MC_CMD_DRIVER_EVENT,
1628                            inbuf, sizeof(inbuf), 0,
1629                            efx_ef10_rx_defer_refill_complete, 0);
1630 }
1631
1632 static void
1633 efx_ef10_rx_defer_refill_complete(struct efx_nic *efx, unsigned long cookie,
1634                                   int rc, efx_dword_t *outbuf,
1635                                   size_t outlen_actual)
1636 {
1637         /* nothing to do */
1638 }
1639
1640 static int efx_ef10_ev_probe(struct efx_channel *channel)
1641 {
1642         return efx_nic_alloc_buffer(channel->efx, &channel->eventq.buf,
1643                                     (channel->eventq_mask + 1) *
1644                                     sizeof(efx_qword_t),
1645                                     GFP_KERNEL);
1646 }
1647
1648 static int efx_ef10_ev_init(struct efx_channel *channel)
1649 {
1650         MCDI_DECLARE_BUF(inbuf,
1651                          MC_CMD_INIT_EVQ_IN_LEN(EFX_MAX_EVQ_SIZE * 8 /
1652                                                 EFX_BUF_SIZE));
1653         MCDI_DECLARE_BUF(outbuf, MC_CMD_INIT_EVQ_OUT_LEN);
1654         size_t entries = channel->eventq.buf.len / EFX_BUF_SIZE;
1655         struct efx_nic *efx = channel->efx;
1656         struct efx_ef10_nic_data *nic_data;
1657         bool supports_rx_merge;
1658         size_t inlen, outlen;
1659         dma_addr_t dma_addr;
1660         int rc;
1661         int i;
1662
1663         nic_data = efx->nic_data;
1664         supports_rx_merge =
1665                 !!(nic_data->datapath_caps &
1666                    1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN);
1667
1668         /* Fill event queue with all ones (i.e. empty events) */
1669         memset(channel->eventq.buf.addr, 0xff, channel->eventq.buf.len);
1670
1671         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_SIZE, channel->eventq_mask + 1);
1672         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_INSTANCE, channel->channel);
1673         /* INIT_EVQ expects index in vector table, not absolute */
1674         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_IRQ_NUM, channel->channel);
1675         MCDI_POPULATE_DWORD_4(inbuf, INIT_EVQ_IN_FLAGS,
1676                               INIT_EVQ_IN_FLAG_INTERRUPTING, 1,
1677                               INIT_EVQ_IN_FLAG_RX_MERGE, 1,
1678                               INIT_EVQ_IN_FLAG_TX_MERGE, 1,
1679                               INIT_EVQ_IN_FLAG_CUT_THRU, !supports_rx_merge);
1680         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_MODE,
1681                        MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS);
1682         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_LOAD, 0);
1683         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_RELOAD, 0);
1684         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_MODE,
1685                        MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS);
1686         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_THRSHLD, 0);
1687
1688         dma_addr = channel->eventq.buf.dma_addr;
1689         for (i = 0; i < entries; ++i) {
1690                 MCDI_SET_ARRAY_QWORD(inbuf, INIT_EVQ_IN_DMA_ADDR, i, dma_addr);
1691                 dma_addr += EFX_BUF_SIZE;
1692         }
1693
1694         inlen = MC_CMD_INIT_EVQ_IN_LEN(entries);
1695
1696         rc = efx_mcdi_rpc(efx, MC_CMD_INIT_EVQ, inbuf, inlen,
1697                           outbuf, sizeof(outbuf), &outlen);
1698         /* IRQ return is ignored */
1699         return rc;
1700 }
1701
1702 static void efx_ef10_ev_fini(struct efx_channel *channel)
1703 {
1704         MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_EVQ_IN_LEN);
1705         MCDI_DECLARE_BUF(outbuf, MC_CMD_FINI_EVQ_OUT_LEN);
1706         struct efx_nic *efx = channel->efx;
1707         size_t outlen;
1708         int rc;
1709
1710         MCDI_SET_DWORD(inbuf, FINI_EVQ_IN_INSTANCE, channel->channel);
1711
1712         rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_EVQ, inbuf, sizeof(inbuf),
1713                           outbuf, sizeof(outbuf), &outlen);
1714
1715         if (rc && rc != -EALREADY)
1716                 goto fail;
1717
1718         return;
1719
1720 fail:
1721         efx_mcdi_display_error(efx, MC_CMD_FINI_EVQ, MC_CMD_FINI_EVQ_IN_LEN,
1722                                outbuf, outlen, rc);
1723 }
1724
1725 static void efx_ef10_ev_remove(struct efx_channel *channel)
1726 {
1727         efx_nic_free_buffer(channel->efx, &channel->eventq.buf);
1728 }
1729
1730 static void efx_ef10_handle_rx_wrong_queue(struct efx_rx_queue *rx_queue,
1731                                            unsigned int rx_queue_label)
1732 {
1733         struct efx_nic *efx = rx_queue->efx;
1734
1735         netif_info(efx, hw, efx->net_dev,
1736                    "rx event arrived on queue %d labeled as queue %u\n",
1737                    efx_rx_queue_index(rx_queue), rx_queue_label);
1738
1739         efx_schedule_reset(efx, RESET_TYPE_DISABLE);
1740 }
1741
1742 static void
1743 efx_ef10_handle_rx_bad_lbits(struct efx_rx_queue *rx_queue,
1744                              unsigned int actual, unsigned int expected)
1745 {
1746         unsigned int dropped = (actual - expected) & rx_queue->ptr_mask;
1747         struct efx_nic *efx = rx_queue->efx;
1748
1749         netif_info(efx, hw, efx->net_dev,
1750                    "dropped %d events (index=%d expected=%d)\n",
1751                    dropped, actual, expected);
1752
1753         efx_schedule_reset(efx, RESET_TYPE_DISABLE);
1754 }
1755
1756 /* partially received RX was aborted. clean up. */
1757 static void efx_ef10_handle_rx_abort(struct efx_rx_queue *rx_queue)
1758 {
1759         unsigned int rx_desc_ptr;
1760
1761         netif_dbg(rx_queue->efx, hw, rx_queue->efx->net_dev,
1762                   "scattered RX aborted (dropping %u buffers)\n",
1763                   rx_queue->scatter_n);
1764
1765         rx_desc_ptr = rx_queue->removed_count & rx_queue->ptr_mask;
1766
1767         efx_rx_packet(rx_queue, rx_desc_ptr, rx_queue->scatter_n,
1768                       0, EFX_RX_PKT_DISCARD);
1769
1770         rx_queue->removed_count += rx_queue->scatter_n;
1771         rx_queue->scatter_n = 0;
1772         rx_queue->scatter_len = 0;
1773         ++efx_rx_queue_channel(rx_queue)->n_rx_nodesc_trunc;
1774 }
1775
1776 static int efx_ef10_handle_rx_event(struct efx_channel *channel,
1777                                     const efx_qword_t *event)
1778 {
1779         unsigned int rx_bytes, next_ptr_lbits, rx_queue_label, rx_l4_class;
1780         unsigned int n_descs, n_packets, i;
1781         struct efx_nic *efx = channel->efx;
1782         struct efx_rx_queue *rx_queue;
1783         bool rx_cont;
1784         u16 flags = 0;
1785
1786         if (unlikely(ACCESS_ONCE(efx->reset_pending)))
1787                 return 0;
1788
1789         /* Basic packet information */
1790         rx_bytes = EFX_QWORD_FIELD(*event, ESF_DZ_RX_BYTES);
1791         next_ptr_lbits = EFX_QWORD_FIELD(*event, ESF_DZ_RX_DSC_PTR_LBITS);
1792         rx_queue_label = EFX_QWORD_FIELD(*event, ESF_DZ_RX_QLABEL);
1793         rx_l4_class = EFX_QWORD_FIELD(*event, ESF_DZ_RX_L4_CLASS);
1794         rx_cont = EFX_QWORD_FIELD(*event, ESF_DZ_RX_CONT);
1795
1796         if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_DROP_EVENT))
1797                 netdev_WARN(efx->net_dev, "saw RX_DROP_EVENT: event="
1798                             EFX_QWORD_FMT "\n",
1799                             EFX_QWORD_VAL(*event));
1800
1801         rx_queue = efx_channel_get_rx_queue(channel);
1802
1803         if (unlikely(rx_queue_label != efx_rx_queue_index(rx_queue)))
1804                 efx_ef10_handle_rx_wrong_queue(rx_queue, rx_queue_label);
1805
1806         n_descs = ((next_ptr_lbits - rx_queue->removed_count) &
1807                    ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1));
1808
1809         if (n_descs != rx_queue->scatter_n + 1) {
1810                 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1811
1812                 /* detect rx abort */
1813                 if (unlikely(n_descs == rx_queue->scatter_n)) {
1814                         if (rx_queue->scatter_n == 0 || rx_bytes != 0)
1815                                 netdev_WARN(efx->net_dev,
1816                                             "invalid RX abort: scatter_n=%u event="
1817                                             EFX_QWORD_FMT "\n",
1818                                             rx_queue->scatter_n,
1819                                             EFX_QWORD_VAL(*event));
1820                         efx_ef10_handle_rx_abort(rx_queue);
1821                         return 0;
1822                 }
1823
1824                 /* Check that RX completion merging is valid, i.e.
1825                  * the current firmware supports it and this is a
1826                  * non-scattered packet.
1827                  */
1828                 if (!(nic_data->datapath_caps &
1829                       (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN)) ||
1830                     rx_queue->scatter_n != 0 || rx_cont) {
1831                         efx_ef10_handle_rx_bad_lbits(
1832                                 rx_queue, next_ptr_lbits,
1833                                 (rx_queue->removed_count +
1834                                  rx_queue->scatter_n + 1) &
1835                                 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1));
1836                         return 0;
1837                 }
1838
1839                 /* Merged completion for multiple non-scattered packets */
1840                 rx_queue->scatter_n = 1;
1841                 rx_queue->scatter_len = 0;
1842                 n_packets = n_descs;
1843                 ++channel->n_rx_merge_events;
1844                 channel->n_rx_merge_packets += n_packets;
1845                 flags |= EFX_RX_PKT_PREFIX_LEN;
1846         } else {
1847                 ++rx_queue->scatter_n;
1848                 rx_queue->scatter_len += rx_bytes;
1849                 if (rx_cont)
1850                         return 0;
1851                 n_packets = 1;
1852         }
1853
1854         if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_RX_ECRC_ERR)))
1855                 flags |= EFX_RX_PKT_DISCARD;
1856
1857         if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_RX_IPCKSUM_ERR))) {
1858                 channel->n_rx_ip_hdr_chksum_err += n_packets;
1859         } else if (unlikely(EFX_QWORD_FIELD(*event,
1860                                             ESF_DZ_RX_TCPUDP_CKSUM_ERR))) {
1861                 channel->n_rx_tcp_udp_chksum_err += n_packets;
1862         } else if (rx_l4_class == ESE_DZ_L4_CLASS_TCP ||
1863                    rx_l4_class == ESE_DZ_L4_CLASS_UDP) {
1864                 flags |= EFX_RX_PKT_CSUMMED;
1865         }
1866
1867         if (rx_l4_class == ESE_DZ_L4_CLASS_TCP)
1868                 flags |= EFX_RX_PKT_TCP;
1869
1870         channel->irq_mod_score += 2 * n_packets;
1871
1872         /* Handle received packet(s) */
1873         for (i = 0; i < n_packets; i++) {
1874                 efx_rx_packet(rx_queue,
1875                               rx_queue->removed_count & rx_queue->ptr_mask,
1876                               rx_queue->scatter_n, rx_queue->scatter_len,
1877                               flags);
1878                 rx_queue->removed_count += rx_queue->scatter_n;
1879         }
1880
1881         rx_queue->scatter_n = 0;
1882         rx_queue->scatter_len = 0;
1883
1884         return n_packets;
1885 }
1886
1887 static int
1888 efx_ef10_handle_tx_event(struct efx_channel *channel, efx_qword_t *event)
1889 {
1890         struct efx_nic *efx = channel->efx;
1891         struct efx_tx_queue *tx_queue;
1892         unsigned int tx_ev_desc_ptr;
1893         unsigned int tx_ev_q_label;
1894         int tx_descs = 0;
1895
1896         if (unlikely(ACCESS_ONCE(efx->reset_pending)))
1897                 return 0;
1898
1899         if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_TX_DROP_EVENT)))
1900                 return 0;
1901
1902         /* Transmit completion */
1903         tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, ESF_DZ_TX_DESCR_INDX);
1904         tx_ev_q_label = EFX_QWORD_FIELD(*event, ESF_DZ_TX_QLABEL);
1905         tx_queue = efx_channel_get_tx_queue(channel,
1906                                             tx_ev_q_label % EFX_TXQ_TYPES);
1907         tx_descs = ((tx_ev_desc_ptr + 1 - tx_queue->read_count) &
1908                     tx_queue->ptr_mask);
1909         efx_xmit_done(tx_queue, tx_ev_desc_ptr & tx_queue->ptr_mask);
1910
1911         return tx_descs;
1912 }
1913
1914 static void
1915 efx_ef10_handle_driver_event(struct efx_channel *channel, efx_qword_t *event)
1916 {
1917         struct efx_nic *efx = channel->efx;
1918         int subcode;
1919
1920         subcode = EFX_QWORD_FIELD(*event, ESF_DZ_DRV_SUB_CODE);
1921
1922         switch (subcode) {
1923         case ESE_DZ_DRV_TIMER_EV:
1924         case ESE_DZ_DRV_WAKE_UP_EV:
1925                 break;
1926         case ESE_DZ_DRV_START_UP_EV:
1927                 /* event queue init complete. ok. */
1928                 break;
1929         default:
1930                 netif_err(efx, hw, efx->net_dev,
1931                           "channel %d unknown driver event type %d"
1932                           " (data " EFX_QWORD_FMT ")\n",
1933                           channel->channel, subcode,
1934                           EFX_QWORD_VAL(*event));
1935
1936         }
1937 }
1938
1939 static void efx_ef10_handle_driver_generated_event(struct efx_channel *channel,
1940                                                    efx_qword_t *event)
1941 {
1942         struct efx_nic *efx = channel->efx;
1943         u32 subcode;
1944
1945         subcode = EFX_QWORD_FIELD(*event, EFX_DWORD_0);
1946
1947         switch (subcode) {
1948         case EFX_EF10_TEST:
1949                 channel->event_test_cpu = raw_smp_processor_id();
1950                 break;
1951         case EFX_EF10_REFILL:
1952                 /* The queue must be empty, so we won't receive any rx
1953                  * events, so efx_process_channel() won't refill the
1954                  * queue. Refill it here
1955                  */
1956                 efx_fast_push_rx_descriptors(&channel->rx_queue, true);
1957                 break;
1958         default:
1959                 netif_err(efx, hw, efx->net_dev,
1960                           "channel %d unknown driver event type %u"
1961                           " (data " EFX_QWORD_FMT ")\n",
1962                           channel->channel, (unsigned) subcode,
1963                           EFX_QWORD_VAL(*event));
1964         }
1965 }
1966
1967 static int efx_ef10_ev_process(struct efx_channel *channel, int quota)
1968 {
1969         struct efx_nic *efx = channel->efx;
1970         efx_qword_t event, *p_event;
1971         unsigned int read_ptr;
1972         int ev_code;
1973         int tx_descs = 0;
1974         int spent = 0;
1975
1976         if (quota <= 0)
1977                 return spent;
1978
1979         read_ptr = channel->eventq_read_ptr;
1980
1981         for (;;) {
1982                 p_event = efx_event(channel, read_ptr);
1983                 event = *p_event;
1984
1985                 if (!efx_event_present(&event))
1986                         break;
1987
1988                 EFX_SET_QWORD(*p_event);
1989
1990                 ++read_ptr;
1991
1992                 ev_code = EFX_QWORD_FIELD(event, ESF_DZ_EV_CODE);
1993
1994                 netif_vdbg(efx, drv, efx->net_dev,
1995                            "processing event on %d " EFX_QWORD_FMT "\n",
1996                            channel->channel, EFX_QWORD_VAL(event));
1997
1998                 switch (ev_code) {
1999                 case ESE_DZ_EV_CODE_MCDI_EV:
2000                         efx_mcdi_process_event(channel, &event);
2001                         break;
2002                 case ESE_DZ_EV_CODE_RX_EV:
2003                         spent += efx_ef10_handle_rx_event(channel, &event);
2004                         if (spent >= quota) {
2005                                 /* XXX can we split a merged event to
2006                                  * avoid going over-quota?
2007                                  */
2008                                 spent = quota;
2009                                 goto out;
2010                         }
2011                         break;
2012                 case ESE_DZ_EV_CODE_TX_EV:
2013                         tx_descs += efx_ef10_handle_tx_event(channel, &event);
2014                         if (tx_descs > efx->txq_entries) {
2015                                 spent = quota;
2016                                 goto out;
2017                         } else if (++spent == quota) {
2018                                 goto out;
2019                         }
2020                         break;
2021                 case ESE_DZ_EV_CODE_DRIVER_EV:
2022                         efx_ef10_handle_driver_event(channel, &event);
2023                         if (++spent == quota)
2024                                 goto out;
2025                         break;
2026                 case EFX_EF10_DRVGEN_EV:
2027                         efx_ef10_handle_driver_generated_event(channel, &event);
2028                         break;
2029                 default:
2030                         netif_err(efx, hw, efx->net_dev,
2031                                   "channel %d unknown event type %d"
2032                                   " (data " EFX_QWORD_FMT ")\n",
2033                                   channel->channel, ev_code,
2034                                   EFX_QWORD_VAL(event));
2035                 }
2036         }
2037
2038 out:
2039         channel->eventq_read_ptr = read_ptr;
2040         return spent;
2041 }
2042
2043 static void efx_ef10_ev_read_ack(struct efx_channel *channel)
2044 {
2045         struct efx_nic *efx = channel->efx;
2046         efx_dword_t rptr;
2047
2048         if (EFX_EF10_WORKAROUND_35388(efx)) {
2049                 BUILD_BUG_ON(EFX_MIN_EVQ_SIZE <
2050                              (1 << ERF_DD_EVQ_IND_RPTR_WIDTH));
2051                 BUILD_BUG_ON(EFX_MAX_EVQ_SIZE >
2052                              (1 << 2 * ERF_DD_EVQ_IND_RPTR_WIDTH));
2053
2054                 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS,
2055                                      EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH,
2056                                      ERF_DD_EVQ_IND_RPTR,
2057                                      (channel->eventq_read_ptr &
2058                                       channel->eventq_mask) >>
2059                                      ERF_DD_EVQ_IND_RPTR_WIDTH);
2060                 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT,
2061                                 channel->channel);
2062                 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS,
2063                                      EFE_DD_EVQ_IND_RPTR_FLAGS_LOW,
2064                                      ERF_DD_EVQ_IND_RPTR,
2065                                      channel->eventq_read_ptr &
2066                                      ((1 << ERF_DD_EVQ_IND_RPTR_WIDTH) - 1));
2067                 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT,
2068                                 channel->channel);
2069         } else {
2070                 EFX_POPULATE_DWORD_1(rptr, ERF_DZ_EVQ_RPTR,
2071                                      channel->eventq_read_ptr &
2072                                      channel->eventq_mask);
2073                 efx_writed_page(efx, &rptr, ER_DZ_EVQ_RPTR, channel->channel);
2074         }
2075 }
2076
2077 static void efx_ef10_ev_test_generate(struct efx_channel *channel)
2078 {
2079         MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
2080         struct efx_nic *efx = channel->efx;
2081         efx_qword_t event;
2082         int rc;
2083
2084         EFX_POPULATE_QWORD_2(event,
2085                              ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV,
2086                              ESF_DZ_EV_DATA, EFX_EF10_TEST);
2087
2088         MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
2089
2090         /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
2091          * already swapped the data to little-endian order.
2092          */
2093         memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
2094                sizeof(efx_qword_t));
2095
2096         rc = efx_mcdi_rpc(efx, MC_CMD_DRIVER_EVENT, inbuf, sizeof(inbuf),
2097                           NULL, 0, NULL);
2098         if (rc != 0)
2099                 goto fail;
2100
2101         return;
2102
2103 fail:
2104         WARN_ON(true);
2105         netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
2106 }
2107
2108 void efx_ef10_handle_drain_event(struct efx_nic *efx)
2109 {
2110         if (atomic_dec_and_test(&efx->active_queues))
2111                 wake_up(&efx->flush_wq);
2112
2113         WARN_ON(atomic_read(&efx->active_queues) < 0);
2114 }
2115
2116 static int efx_ef10_fini_dmaq(struct efx_nic *efx)
2117 {
2118         struct efx_ef10_nic_data *nic_data = efx->nic_data;
2119         struct efx_channel *channel;
2120         struct efx_tx_queue *tx_queue;
2121         struct efx_rx_queue *rx_queue;
2122         int pending;
2123
2124         /* If the MC has just rebooted, the TX/RX queues will have already been
2125          * torn down, but efx->active_queues needs to be set to zero.
2126          */
2127         if (nic_data->must_realloc_vis) {
2128                 atomic_set(&efx->active_queues, 0);
2129                 return 0;
2130         }
2131
2132         /* Do not attempt to write to the NIC during EEH recovery */
2133         if (efx->state != STATE_RECOVERY) {
2134                 efx_for_each_channel(channel, efx) {
2135                         efx_for_each_channel_rx_queue(rx_queue, channel)
2136                                 efx_ef10_rx_fini(rx_queue);
2137                         efx_for_each_channel_tx_queue(tx_queue, channel)
2138                                 efx_ef10_tx_fini(tx_queue);
2139                 }
2140
2141                 wait_event_timeout(efx->flush_wq,
2142                                    atomic_read(&efx->active_queues) == 0,
2143                                    msecs_to_jiffies(EFX_MAX_FLUSH_TIME));
2144                 pending = atomic_read(&efx->active_queues);
2145                 if (pending) {
2146                         netif_err(efx, hw, efx->net_dev, "failed to flush %d queues\n",
2147                                   pending);
2148                         return -ETIMEDOUT;
2149                 }
2150         }
2151
2152         return 0;
2153 }
2154
2155 static void efx_ef10_prepare_flr(struct efx_nic *efx)
2156 {
2157         atomic_set(&efx->active_queues, 0);
2158 }
2159
2160 static bool efx_ef10_filter_equal(const struct efx_filter_spec *left,
2161                                   const struct efx_filter_spec *right)
2162 {
2163         if ((left->match_flags ^ right->match_flags) |
2164             ((left->flags ^ right->flags) &
2165              (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)))
2166                 return false;
2167
2168         return memcmp(&left->outer_vid, &right->outer_vid,
2169                       sizeof(struct efx_filter_spec) -
2170                       offsetof(struct efx_filter_spec, outer_vid)) == 0;
2171 }
2172
2173 static unsigned int efx_ef10_filter_hash(const struct efx_filter_spec *spec)
2174 {
2175         BUILD_BUG_ON(offsetof(struct efx_filter_spec, outer_vid) & 3);
2176         return jhash2((const u32 *)&spec->outer_vid,
2177                       (sizeof(struct efx_filter_spec) -
2178                        offsetof(struct efx_filter_spec, outer_vid)) / 4,
2179                       0);
2180         /* XXX should we randomise the initval? */
2181 }
2182
2183 /* Decide whether a filter should be exclusive or else should allow
2184  * delivery to additional recipients.  Currently we decide that
2185  * filters for specific local unicast MAC and IP addresses are
2186  * exclusive.
2187  */
2188 static bool efx_ef10_filter_is_exclusive(const struct efx_filter_spec *spec)
2189 {
2190         if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC &&
2191             !is_multicast_ether_addr(spec->loc_mac))
2192                 return true;
2193
2194         if ((spec->match_flags &
2195              (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) ==
2196             (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) {
2197                 if (spec->ether_type == htons(ETH_P_IP) &&
2198                     !ipv4_is_multicast(spec->loc_host[0]))
2199                         return true;
2200                 if (spec->ether_type == htons(ETH_P_IPV6) &&
2201                     ((const u8 *)spec->loc_host)[0] != 0xff)
2202                         return true;
2203         }
2204
2205         return false;
2206 }
2207
2208 static struct efx_filter_spec *
2209 efx_ef10_filter_entry_spec(const struct efx_ef10_filter_table *table,
2210                            unsigned int filter_idx)
2211 {
2212         return (struct efx_filter_spec *)(table->entry[filter_idx].spec &
2213                                           ~EFX_EF10_FILTER_FLAGS);
2214 }
2215
2216 static unsigned int
2217 efx_ef10_filter_entry_flags(const struct efx_ef10_filter_table *table,
2218                            unsigned int filter_idx)
2219 {
2220         return table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAGS;
2221 }
2222
2223 static void
2224 efx_ef10_filter_set_entry(struct efx_ef10_filter_table *table,
2225                           unsigned int filter_idx,
2226                           const struct efx_filter_spec *spec,
2227                           unsigned int flags)
2228 {
2229         table->entry[filter_idx].spec = (unsigned long)spec | flags;
2230 }
2231
2232 static void efx_ef10_filter_push_prep(struct efx_nic *efx,
2233                                       const struct efx_filter_spec *spec,
2234                                       efx_dword_t *inbuf, u64 handle,
2235                                       bool replacing)
2236 {
2237         struct efx_ef10_nic_data *nic_data = efx->nic_data;
2238
2239         memset(inbuf, 0, MC_CMD_FILTER_OP_IN_LEN);
2240
2241         if (replacing) {
2242                 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
2243                                MC_CMD_FILTER_OP_IN_OP_REPLACE);
2244                 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE, handle);
2245         } else {
2246                 u32 match_fields = 0;
2247
2248                 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
2249                                efx_ef10_filter_is_exclusive(spec) ?
2250                                MC_CMD_FILTER_OP_IN_OP_INSERT :
2251                                MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE);
2252
2253                 /* Convert match flags and values.  Unlike almost
2254                  * everything else in MCDI, these fields are in
2255                  * network byte order.
2256                  */
2257                 if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC_IG)
2258                         match_fields |=
2259                                 is_multicast_ether_addr(spec->loc_mac) ?
2260                                 1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_LBN :
2261                                 1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_LBN;
2262 #define COPY_FIELD(gen_flag, gen_field, mcdi_field)                          \
2263                 if (spec->match_flags & EFX_FILTER_MATCH_ ## gen_flag) {     \
2264                         match_fields |=                                      \
2265                                 1 << MC_CMD_FILTER_OP_IN_MATCH_ ##           \
2266                                 mcdi_field ## _LBN;                          \
2267                         BUILD_BUG_ON(                                        \
2268                                 MC_CMD_FILTER_OP_IN_ ## mcdi_field ## _LEN < \
2269                                 sizeof(spec->gen_field));                    \
2270                         memcpy(MCDI_PTR(inbuf, FILTER_OP_IN_ ## mcdi_field), \
2271                                &spec->gen_field, sizeof(spec->gen_field));   \
2272                 }
2273                 COPY_FIELD(REM_HOST, rem_host, SRC_IP);
2274                 COPY_FIELD(LOC_HOST, loc_host, DST_IP);
2275                 COPY_FIELD(REM_MAC, rem_mac, SRC_MAC);
2276                 COPY_FIELD(REM_PORT, rem_port, SRC_PORT);
2277                 COPY_FIELD(LOC_MAC, loc_mac, DST_MAC);
2278                 COPY_FIELD(LOC_PORT, loc_port, DST_PORT);
2279                 COPY_FIELD(ETHER_TYPE, ether_type, ETHER_TYPE);
2280                 COPY_FIELD(INNER_VID, inner_vid, INNER_VLAN);
2281                 COPY_FIELD(OUTER_VID, outer_vid, OUTER_VLAN);
2282                 COPY_FIELD(IP_PROTO, ip_proto, IP_PROTO);
2283 #undef COPY_FIELD
2284                 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_MATCH_FIELDS,
2285                                match_fields);
2286         }
2287
2288         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_PORT_ID, EVB_PORT_ID_ASSIGNED);
2289         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_DEST,
2290                        spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ?
2291                        MC_CMD_FILTER_OP_IN_RX_DEST_DROP :
2292                        MC_CMD_FILTER_OP_IN_RX_DEST_HOST);
2293         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_TX_DEST,
2294                        MC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT);
2295         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_QUEUE,
2296                        spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ?
2297                        0 : spec->dmaq_id);
2298         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_MODE,
2299                        (spec->flags & EFX_FILTER_FLAG_RX_RSS) ?
2300                        MC_CMD_FILTER_OP_IN_RX_MODE_RSS :
2301                        MC_CMD_FILTER_OP_IN_RX_MODE_SIMPLE);
2302         if (spec->flags & EFX_FILTER_FLAG_RX_RSS)
2303                 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_CONTEXT,
2304                                spec->rss_context !=
2305                                EFX_FILTER_RSS_CONTEXT_DEFAULT ?
2306                                spec->rss_context : nic_data->rx_rss_context);
2307 }
2308
2309 static int efx_ef10_filter_push(struct efx_nic *efx,
2310                                 const struct efx_filter_spec *spec,
2311                                 u64 *handle, bool replacing)
2312 {
2313         MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
2314         MCDI_DECLARE_BUF(outbuf, MC_CMD_FILTER_OP_OUT_LEN);
2315         int rc;
2316
2317         efx_ef10_filter_push_prep(efx, spec, inbuf, *handle, replacing);
2318         rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
2319                           outbuf, sizeof(outbuf), NULL);
2320         if (rc == 0)
2321                 *handle = MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE);
2322         if (rc == -ENOSPC)
2323                 rc = -EBUSY; /* to match efx_farch_filter_insert() */
2324         return rc;
2325 }
2326
2327 static int efx_ef10_filter_rx_match_pri(struct efx_ef10_filter_table *table,
2328                                         enum efx_filter_match_flags match_flags)
2329 {
2330         unsigned int match_pri;
2331
2332         for (match_pri = 0;
2333              match_pri < table->rx_match_count;
2334              match_pri++)
2335                 if (table->rx_match_flags[match_pri] == match_flags)
2336                         return match_pri;
2337
2338         return -EPROTONOSUPPORT;
2339 }
2340
2341 static s32 efx_ef10_filter_insert(struct efx_nic *efx,
2342                                   struct efx_filter_spec *spec,
2343                                   bool replace_equal)
2344 {
2345         struct efx_ef10_filter_table *table = efx->filter_state;
2346         DECLARE_BITMAP(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT);
2347         struct efx_filter_spec *saved_spec;
2348         unsigned int match_pri, hash;
2349         unsigned int priv_flags;
2350         bool replacing = false;
2351         int ins_index = -1;
2352         DEFINE_WAIT(wait);
2353         bool is_mc_recip;
2354         s32 rc;
2355
2356         /* For now, only support RX filters */
2357         if ((spec->flags & (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)) !=
2358             EFX_FILTER_FLAG_RX)
2359                 return -EINVAL;
2360
2361         rc = efx_ef10_filter_rx_match_pri(table, spec->match_flags);
2362         if (rc < 0)
2363                 return rc;
2364         match_pri = rc;
2365
2366         hash = efx_ef10_filter_hash(spec);
2367         is_mc_recip = efx_filter_is_mc_recipient(spec);
2368         if (is_mc_recip)
2369                 bitmap_zero(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT);
2370
2371         /* Find any existing filters with the same match tuple or
2372          * else a free slot to insert at.  If any of them are busy,
2373          * we have to wait and retry.
2374          */
2375         for (;;) {
2376                 unsigned int depth = 1;
2377                 unsigned int i;
2378
2379                 spin_lock_bh(&efx->filter_lock);
2380
2381                 for (;;) {
2382                         i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
2383                         saved_spec = efx_ef10_filter_entry_spec(table, i);
2384
2385                         if (!saved_spec) {
2386                                 if (ins_index < 0)
2387                                         ins_index = i;
2388                         } else if (efx_ef10_filter_equal(spec, saved_spec)) {
2389                                 if (table->entry[i].spec &
2390                                     EFX_EF10_FILTER_FLAG_BUSY)
2391                                         break;
2392                                 if (spec->priority < saved_spec->priority &&
2393                                     spec->priority != EFX_FILTER_PRI_AUTO) {
2394                                         rc = -EPERM;
2395                                         goto out_unlock;
2396                                 }
2397                                 if (!is_mc_recip) {
2398                                         /* This is the only one */
2399                                         if (spec->priority ==
2400                                             saved_spec->priority &&
2401                                             !replace_equal) {
2402                                                 rc = -EEXIST;
2403                                                 goto out_unlock;
2404                                         }
2405                                         ins_index = i;
2406                                         goto found;
2407                                 } else if (spec->priority >
2408                                            saved_spec->priority ||
2409                                            (spec->priority ==
2410                                             saved_spec->priority &&
2411                                             replace_equal)) {
2412                                         if (ins_index < 0)
2413                                                 ins_index = i;
2414                                         else
2415                                                 __set_bit(depth, mc_rem_map);
2416                                 }
2417                         }
2418
2419                         /* Once we reach the maximum search depth, use
2420                          * the first suitable slot or return -EBUSY if
2421                          * there was none
2422                          */
2423                         if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) {
2424                                 if (ins_index < 0) {
2425                                         rc = -EBUSY;
2426                                         goto out_unlock;
2427                                 }
2428                                 goto found;
2429                         }
2430
2431                         ++depth;
2432                 }
2433
2434                 prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE);
2435                 spin_unlock_bh(&efx->filter_lock);
2436                 schedule();
2437         }
2438
2439 found:
2440         /* Create a software table entry if necessary, and mark it
2441          * busy.  We might yet fail to insert, but any attempt to
2442          * insert a conflicting filter while we're waiting for the
2443          * firmware must find the busy entry.
2444          */
2445         saved_spec = efx_ef10_filter_entry_spec(table, ins_index);
2446         if (saved_spec) {
2447                 if (spec->priority == EFX_FILTER_PRI_AUTO &&
2448                     saved_spec->priority >= EFX_FILTER_PRI_AUTO) {
2449                         /* Just make sure it won't be removed */
2450                         if (saved_spec->priority > EFX_FILTER_PRI_AUTO)
2451                                 saved_spec->flags |= EFX_FILTER_FLAG_RX_OVER_AUTO;
2452                         table->entry[ins_index].spec &=
2453                                 ~EFX_EF10_FILTER_FLAG_AUTO_OLD;
2454                         rc = ins_index;
2455                         goto out_unlock;
2456                 }
2457                 replacing = true;
2458                 priv_flags = efx_ef10_filter_entry_flags(table, ins_index);
2459         } else {
2460                 saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC);
2461                 if (!saved_spec) {
2462                         rc = -ENOMEM;
2463                         goto out_unlock;
2464                 }
2465                 *saved_spec = *spec;
2466                 priv_flags = 0;
2467         }
2468         efx_ef10_filter_set_entry(table, ins_index, saved_spec,
2469                                   priv_flags | EFX_EF10_FILTER_FLAG_BUSY);
2470
2471         /* Mark lower-priority multicast recipients busy prior to removal */
2472         if (is_mc_recip) {
2473                 unsigned int depth, i;
2474
2475                 for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) {
2476                         i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
2477                         if (test_bit(depth, mc_rem_map))
2478                                 table->entry[i].spec |=
2479                                         EFX_EF10_FILTER_FLAG_BUSY;
2480                 }
2481         }
2482
2483         spin_unlock_bh(&efx->filter_lock);
2484
2485         rc = efx_ef10_filter_push(efx, spec, &table->entry[ins_index].handle,
2486                                   replacing);
2487
2488         /* Finalise the software table entry */
2489         spin_lock_bh(&efx->filter_lock);
2490         if (rc == 0) {
2491                 if (replacing) {
2492                         /* Update the fields that may differ */
2493                         if (saved_spec->priority == EFX_FILTER_PRI_AUTO)
2494                                 saved_spec->flags |=
2495                                         EFX_FILTER_FLAG_RX_OVER_AUTO;
2496                         saved_spec->priority = spec->priority;
2497                         saved_spec->flags &= EFX_FILTER_FLAG_RX_OVER_AUTO;
2498                         saved_spec->flags |= spec->flags;
2499                         saved_spec->rss_context = spec->rss_context;
2500                         saved_spec->dmaq_id = spec->dmaq_id;
2501                 }
2502         } else if (!replacing) {
2503                 kfree(saved_spec);
2504                 saved_spec = NULL;
2505         }
2506         efx_ef10_filter_set_entry(table, ins_index, saved_spec, priv_flags);
2507
2508         /* Remove and finalise entries for lower-priority multicast
2509          * recipients
2510          */
2511         if (is_mc_recip) {
2512                 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
2513                 unsigned int depth, i;
2514
2515                 memset(inbuf, 0, sizeof(inbuf));
2516
2517                 for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) {
2518                         if (!test_bit(depth, mc_rem_map))
2519                                 continue;
2520
2521                         i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
2522                         saved_spec = efx_ef10_filter_entry_spec(table, i);
2523                         priv_flags = efx_ef10_filter_entry_flags(table, i);
2524
2525                         if (rc == 0) {
2526                                 spin_unlock_bh(&efx->filter_lock);
2527                                 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
2528                                                MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
2529                                 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
2530                                                table->entry[i].handle);
2531                                 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP,
2532                                                   inbuf, sizeof(inbuf),
2533                                                   NULL, 0, NULL);
2534                                 spin_lock_bh(&efx->filter_lock);
2535                         }
2536
2537                         if (rc == 0) {
2538                                 kfree(saved_spec);
2539                                 saved_spec = NULL;
2540                                 priv_flags = 0;
2541                         } else {
2542                                 priv_flags &= ~EFX_EF10_FILTER_FLAG_BUSY;
2543                         }
2544                         efx_ef10_filter_set_entry(table, i, saved_spec,
2545                                                   priv_flags);
2546                 }
2547         }
2548
2549         /* If successful, return the inserted filter ID */
2550         if (rc == 0)
2551                 rc = match_pri * HUNT_FILTER_TBL_ROWS + ins_index;
2552
2553         wake_up_all(&table->waitq);
2554 out_unlock:
2555         spin_unlock_bh(&efx->filter_lock);
2556         finish_wait(&table->waitq, &wait);
2557         return rc;
2558 }
2559
2560 static void efx_ef10_filter_update_rx_scatter(struct efx_nic *efx)
2561 {
2562         /* no need to do anything here on EF10 */
2563 }
2564
2565 /* Remove a filter.
2566  * If !by_index, remove by ID
2567  * If by_index, remove by index
2568  * Filter ID may come from userland and must be range-checked.
2569  */
2570 static int efx_ef10_filter_remove_internal(struct efx_nic *efx,
2571                                            unsigned int priority_mask,
2572                                            u32 filter_id, bool by_index)
2573 {
2574         unsigned int filter_idx = filter_id % HUNT_FILTER_TBL_ROWS;
2575         struct efx_ef10_filter_table *table = efx->filter_state;
2576         MCDI_DECLARE_BUF(inbuf,
2577                          MC_CMD_FILTER_OP_IN_HANDLE_OFST +
2578                          MC_CMD_FILTER_OP_IN_HANDLE_LEN);
2579         struct efx_filter_spec *spec;
2580         DEFINE_WAIT(wait);
2581         int rc;
2582
2583         /* Find the software table entry and mark it busy.  Don't
2584          * remove it yet; any attempt to update while we're waiting
2585          * for the firmware must find the busy entry.
2586          */
2587         for (;;) {
2588                 spin_lock_bh(&efx->filter_lock);
2589                 if (!(table->entry[filter_idx].spec &
2590                       EFX_EF10_FILTER_FLAG_BUSY))
2591                         break;
2592                 prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE);
2593                 spin_unlock_bh(&efx->filter_lock);
2594                 schedule();
2595         }
2596
2597         spec = efx_ef10_filter_entry_spec(table, filter_idx);
2598         if (!spec ||
2599             (!by_index &&
2600              efx_ef10_filter_rx_match_pri(table, spec->match_flags) !=
2601              filter_id / HUNT_FILTER_TBL_ROWS)) {
2602                 rc = -ENOENT;
2603                 goto out_unlock;
2604         }
2605
2606         if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO &&
2607             priority_mask == (1U << EFX_FILTER_PRI_AUTO)) {
2608                 /* Just remove flags */
2609                 spec->flags &= ~EFX_FILTER_FLAG_RX_OVER_AUTO;
2610                 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_AUTO_OLD;
2611                 rc = 0;
2612                 goto out_unlock;
2613         }
2614
2615         if (!(priority_mask & (1U << spec->priority))) {
2616                 rc = -ENOENT;
2617                 goto out_unlock;
2618         }
2619
2620         table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
2621         spin_unlock_bh(&efx->filter_lock);
2622
2623         if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO) {
2624                 /* Reset to an automatic filter */
2625
2626                 struct efx_filter_spec new_spec = *spec;
2627
2628                 new_spec.priority = EFX_FILTER_PRI_AUTO;
2629                 new_spec.flags = (EFX_FILTER_FLAG_RX |
2630                                   EFX_FILTER_FLAG_RX_RSS);
2631                 new_spec.dmaq_id = 0;
2632                 new_spec.rss_context = EFX_FILTER_RSS_CONTEXT_DEFAULT;
2633                 rc = efx_ef10_filter_push(efx, &new_spec,
2634                                           &table->entry[filter_idx].handle,
2635                                           true);
2636
2637                 spin_lock_bh(&efx->filter_lock);
2638                 if (rc == 0)
2639                         *spec = new_spec;
2640         } else {
2641                 /* Really remove the filter */
2642
2643                 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
2644                                efx_ef10_filter_is_exclusive(spec) ?
2645                                MC_CMD_FILTER_OP_IN_OP_REMOVE :
2646                                MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
2647                 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
2648                                table->entry[filter_idx].handle);
2649                 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP,
2650                                   inbuf, sizeof(inbuf), NULL, 0, NULL);
2651
2652                 spin_lock_bh(&efx->filter_lock);
2653                 if (rc == 0) {
2654                         kfree(spec);
2655                         efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
2656                 }
2657         }
2658
2659         table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY;
2660         wake_up_all(&table->waitq);
2661 out_unlock:
2662         spin_unlock_bh(&efx->filter_lock);
2663         finish_wait(&table->waitq, &wait);
2664         return rc;
2665 }
2666
2667 static int efx_ef10_filter_remove_safe(struct efx_nic *efx,
2668                                        enum efx_filter_priority priority,
2669                                        u32 filter_id)
2670 {
2671         return efx_ef10_filter_remove_internal(efx, 1U << priority,
2672                                                filter_id, false);
2673 }
2674
2675 static int efx_ef10_filter_get_safe(struct efx_nic *efx,
2676                                     enum efx_filter_priority priority,
2677                                     u32 filter_id, struct efx_filter_spec *spec)
2678 {
2679         unsigned int filter_idx = filter_id % HUNT_FILTER_TBL_ROWS;
2680         struct efx_ef10_filter_table *table = efx->filter_state;
2681         const struct efx_filter_spec *saved_spec;
2682         int rc;
2683
2684         spin_lock_bh(&efx->filter_lock);
2685         saved_spec = efx_ef10_filter_entry_spec(table, filter_idx);
2686         if (saved_spec && saved_spec->priority == priority &&
2687             efx_ef10_filter_rx_match_pri(table, saved_spec->match_flags) ==
2688             filter_id / HUNT_FILTER_TBL_ROWS) {
2689                 *spec = *saved_spec;
2690                 rc = 0;
2691         } else {
2692                 rc = -ENOENT;
2693         }
2694         spin_unlock_bh(&efx->filter_lock);
2695         return rc;
2696 }
2697
2698 static int efx_ef10_filter_clear_rx(struct efx_nic *efx,
2699                                      enum efx_filter_priority priority)
2700 {
2701         unsigned int priority_mask;
2702         unsigned int i;
2703         int rc;
2704
2705         priority_mask = (((1U << (priority + 1)) - 1) &
2706                          ~(1U << EFX_FILTER_PRI_AUTO));
2707
2708         for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) {
2709                 rc = efx_ef10_filter_remove_internal(efx, priority_mask,
2710                                                      i, true);
2711                 if (rc && rc != -ENOENT)
2712                         return rc;
2713         }
2714
2715         return 0;
2716 }
2717
2718 static u32 efx_ef10_filter_count_rx_used(struct efx_nic *efx,
2719                                          enum efx_filter_priority priority)
2720 {
2721         struct efx_ef10_filter_table *table = efx->filter_state;
2722         unsigned int filter_idx;
2723         s32 count = 0;
2724
2725         spin_lock_bh(&efx->filter_lock);
2726         for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
2727                 if (table->entry[filter_idx].spec &&
2728                     efx_ef10_filter_entry_spec(table, filter_idx)->priority ==
2729                     priority)
2730                         ++count;
2731         }
2732         spin_unlock_bh(&efx->filter_lock);
2733         return count;
2734 }
2735
2736 static u32 efx_ef10_filter_get_rx_id_limit(struct efx_nic *efx)
2737 {
2738         struct efx_ef10_filter_table *table = efx->filter_state;
2739
2740         return table->rx_match_count * HUNT_FILTER_TBL_ROWS;
2741 }
2742
2743 static s32 efx_ef10_filter_get_rx_ids(struct efx_nic *efx,
2744                                       enum efx_filter_priority priority,
2745                                       u32 *buf, u32 size)
2746 {
2747         struct efx_ef10_filter_table *table = efx->filter_state;
2748         struct efx_filter_spec *spec;
2749         unsigned int filter_idx;
2750         s32 count = 0;
2751
2752         spin_lock_bh(&efx->filter_lock);
2753         for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
2754                 spec = efx_ef10_filter_entry_spec(table, filter_idx);
2755                 if (spec && spec->priority == priority) {
2756                         if (count == size) {
2757                                 count = -EMSGSIZE;
2758                                 break;
2759                         }
2760                         buf[count++] = (efx_ef10_filter_rx_match_pri(
2761                                                 table, spec->match_flags) *
2762                                         HUNT_FILTER_TBL_ROWS +
2763                                         filter_idx);
2764                 }
2765         }
2766         spin_unlock_bh(&efx->filter_lock);
2767         return count;
2768 }
2769
2770 #ifdef CONFIG_RFS_ACCEL
2771
2772 static efx_mcdi_async_completer efx_ef10_filter_rfs_insert_complete;
2773
2774 static s32 efx_ef10_filter_rfs_insert(struct efx_nic *efx,
2775                                       struct efx_filter_spec *spec)
2776 {
2777         struct efx_ef10_filter_table *table = efx->filter_state;
2778         MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
2779         struct efx_filter_spec *saved_spec;
2780         unsigned int hash, i, depth = 1;
2781         bool replacing = false;
2782         int ins_index = -1;
2783         u64 cookie;
2784         s32 rc;
2785
2786         /* Must be an RX filter without RSS and not for a multicast
2787          * destination address (RFS only works for connected sockets).
2788          * These restrictions allow us to pass only a tiny amount of
2789          * data through to the completion function.
2790          */
2791         EFX_WARN_ON_PARANOID(spec->flags !=
2792                              (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_RX_SCATTER));
2793         EFX_WARN_ON_PARANOID(spec->priority != EFX_FILTER_PRI_HINT);
2794         EFX_WARN_ON_PARANOID(efx_filter_is_mc_recipient(spec));
2795
2796         hash = efx_ef10_filter_hash(spec);
2797
2798         spin_lock_bh(&efx->filter_lock);
2799
2800         /* Find any existing filter with the same match tuple or else
2801          * a free slot to insert at.  If an existing filter is busy,
2802          * we have to give up.
2803          */
2804         for (;;) {
2805                 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
2806                 saved_spec = efx_ef10_filter_entry_spec(table, i);
2807
2808                 if (!saved_spec) {
2809                         if (ins_index < 0)
2810                                 ins_index = i;
2811                 } else if (efx_ef10_filter_equal(spec, saved_spec)) {
2812                         if (table->entry[i].spec & EFX_EF10_FILTER_FLAG_BUSY) {
2813                                 rc = -EBUSY;
2814                                 goto fail_unlock;
2815                         }
2816                         if (spec->priority < saved_spec->priority) {
2817                                 rc = -EPERM;
2818                                 goto fail_unlock;
2819                         }
2820                         ins_index = i;
2821                         break;
2822                 }
2823
2824                 /* Once we reach the maximum search depth, use the
2825                  * first suitable slot or return -EBUSY if there was
2826                  * none
2827                  */
2828                 if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) {
2829                         if (ins_index < 0) {
2830                                 rc = -EBUSY;
2831                                 goto fail_unlock;
2832                         }
2833                         break;
2834                 }
2835
2836                 ++depth;
2837         }
2838
2839         /* Create a software table entry if necessary, and mark it
2840          * busy.  We might yet fail to insert, but any attempt to
2841          * insert a conflicting filter while we're waiting for the
2842          * firmware must find the busy entry.
2843          */
2844         saved_spec = efx_ef10_filter_entry_spec(table, ins_index);
2845         if (saved_spec) {
2846                 replacing = true;
2847         } else {
2848                 saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC);
2849                 if (!saved_spec) {
2850                         rc = -ENOMEM;
2851                         goto fail_unlock;
2852                 }
2853                 *saved_spec = *spec;
2854         }
2855         efx_ef10_filter_set_entry(table, ins_index, saved_spec,
2856                                   EFX_EF10_FILTER_FLAG_BUSY);
2857
2858         spin_unlock_bh(&efx->filter_lock);
2859
2860         /* Pack up the variables needed on completion */
2861         cookie = replacing << 31 | ins_index << 16 | spec->dmaq_id;
2862
2863         efx_ef10_filter_push_prep(efx, spec, inbuf,
2864                                   table->entry[ins_index].handle, replacing);
2865         efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
2866                            MC_CMD_FILTER_OP_OUT_LEN,
2867                            efx_ef10_filter_rfs_insert_complete, cookie);
2868
2869         return ins_index;
2870
2871 fail_unlock:
2872         spin_unlock_bh(&efx->filter_lock);
2873         return rc;
2874 }
2875
2876 static void
2877 efx_ef10_filter_rfs_insert_complete(struct efx_nic *efx, unsigned long cookie,
2878                                     int rc, efx_dword_t *outbuf,
2879                                     size_t outlen_actual)
2880 {
2881         struct efx_ef10_filter_table *table = efx->filter_state;
2882         unsigned int ins_index, dmaq_id;
2883         struct efx_filter_spec *spec;
2884         bool replacing;
2885
2886         /* Unpack the cookie */
2887         replacing = cookie >> 31;
2888         ins_index = (cookie >> 16) & (HUNT_FILTER_TBL_ROWS - 1);
2889         dmaq_id = cookie & 0xffff;
2890
2891         spin_lock_bh(&efx->filter_lock);
2892         spec = efx_ef10_filter_entry_spec(table, ins_index);
2893         if (rc == 0) {
2894                 table->entry[ins_index].handle =
2895                         MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE);
2896                 if (replacing)
2897                         spec->dmaq_id = dmaq_id;
2898         } else if (!replacing) {
2899                 kfree(spec);
2900                 spec = NULL;
2901         }
2902         efx_ef10_filter_set_entry(table, ins_index, spec, 0);
2903         spin_unlock_bh(&efx->filter_lock);
2904
2905         wake_up_all(&table->waitq);
2906 }
2907
2908 static void
2909 efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx,
2910                                     unsigned long filter_idx,
2911                                     int rc, efx_dword_t *outbuf,
2912                                     size_t outlen_actual);
2913
2914 static bool efx_ef10_filter_rfs_expire_one(struct efx_nic *efx, u32 flow_id,
2915                                            unsigned int filter_idx)
2916 {
2917         struct efx_ef10_filter_table *table = efx->filter_state;
2918         struct efx_filter_spec *spec =
2919                 efx_ef10_filter_entry_spec(table, filter_idx);
2920         MCDI_DECLARE_BUF(inbuf,
2921                          MC_CMD_FILTER_OP_IN_HANDLE_OFST +
2922                          MC_CMD_FILTER_OP_IN_HANDLE_LEN);
2923
2924         if (!spec ||
2925             (table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAG_BUSY) ||
2926             spec->priority != EFX_FILTER_PRI_HINT ||
2927             !rps_may_expire_flow(efx->net_dev, spec->dmaq_id,
2928                                  flow_id, filter_idx))
2929                 return false;
2930
2931         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
2932                        MC_CMD_FILTER_OP_IN_OP_REMOVE);
2933         MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
2934                        table->entry[filter_idx].handle);
2935         if (efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf), 0,
2936                                efx_ef10_filter_rfs_expire_complete, filter_idx))
2937                 return false;
2938
2939         table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
2940         return true;
2941 }
2942
2943 static void
2944 efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx,
2945                                     unsigned long filter_idx,
2946                                     int rc, efx_dword_t *outbuf,
2947                                     size_t outlen_actual)
2948 {
2949         struct efx_ef10_filter_table *table = efx->filter_state;
2950         struct efx_filter_spec *spec =
2951                 efx_ef10_filter_entry_spec(table, filter_idx);
2952
2953         spin_lock_bh(&efx->filter_lock);
2954         if (rc == 0) {
2955                 kfree(spec);
2956                 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
2957         }
2958         table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY;
2959         wake_up_all(&table->waitq);
2960         spin_unlock_bh(&efx->filter_lock);
2961 }
2962
2963 #endif /* CONFIG_RFS_ACCEL */
2964
2965 static int efx_ef10_filter_match_flags_from_mcdi(u32 mcdi_flags)
2966 {
2967         int match_flags = 0;
2968
2969 #define MAP_FLAG(gen_flag, mcdi_field) {                                \
2970                 u32 old_mcdi_flags = mcdi_flags;                        \
2971                 mcdi_flags &= ~(1 << MC_CMD_FILTER_OP_IN_MATCH_ ##      \
2972                                 mcdi_field ## _LBN);                    \
2973                 if (mcdi_flags != old_mcdi_flags)                       \
2974                         match_flags |= EFX_FILTER_MATCH_ ## gen_flag;   \
2975         }
2976         MAP_FLAG(LOC_MAC_IG, UNKNOWN_UCAST_DST);
2977         MAP_FLAG(LOC_MAC_IG, UNKNOWN_MCAST_DST);
2978         MAP_FLAG(REM_HOST, SRC_IP);
2979         MAP_FLAG(LOC_HOST, DST_IP);
2980         MAP_FLAG(REM_MAC, SRC_MAC);
2981         MAP_FLAG(REM_PORT, SRC_PORT);
2982         MAP_FLAG(LOC_MAC, DST_MAC);
2983         MAP_FLAG(LOC_PORT, DST_PORT);
2984         MAP_FLAG(ETHER_TYPE, ETHER_TYPE);
2985         MAP_FLAG(INNER_VID, INNER_VLAN);
2986         MAP_FLAG(OUTER_VID, OUTER_VLAN);
2987         MAP_FLAG(IP_PROTO, IP_PROTO);
2988 #undef MAP_FLAG
2989
2990         /* Did we map them all? */
2991         if (mcdi_flags)
2992                 return -EINVAL;
2993
2994         return match_flags;
2995 }
2996
2997 static int efx_ef10_filter_table_probe(struct efx_nic *efx)
2998 {
2999         MCDI_DECLARE_BUF(inbuf, MC_CMD_GET_PARSER_DISP_INFO_IN_LEN);
3000         MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX);
3001         unsigned int pd_match_pri, pd_match_count;
3002         struct efx_ef10_filter_table *table;
3003         size_t outlen;
3004         int rc;
3005
3006         table = kzalloc(sizeof(*table), GFP_KERNEL);
3007         if (!table)
3008                 return -ENOMEM;
3009
3010         /* Find out which RX filter types are supported, and their priorities */
3011         MCDI_SET_DWORD(inbuf, GET_PARSER_DISP_INFO_IN_OP,
3012                        MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_RX_MATCHES);
3013         rc = efx_mcdi_rpc(efx, MC_CMD_GET_PARSER_DISP_INFO,
3014                           inbuf, sizeof(inbuf), outbuf, sizeof(outbuf),
3015                           &outlen);
3016         if (rc)
3017                 goto fail;
3018         pd_match_count = MCDI_VAR_ARRAY_LEN(
3019                 outlen, GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES);
3020         table->rx_match_count = 0;
3021
3022         for (pd_match_pri = 0; pd_match_pri < pd_match_count; pd_match_pri++) {
3023                 u32 mcdi_flags =
3024                         MCDI_ARRAY_DWORD(
3025                                 outbuf,
3026                                 GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES,
3027                                 pd_match_pri);
3028                 rc = efx_ef10_filter_match_flags_from_mcdi(mcdi_flags);
3029                 if (rc < 0) {
3030                         netif_dbg(efx, probe, efx->net_dev,
3031                                   "%s: fw flags %#x pri %u not supported in driver\n",
3032                                   __func__, mcdi_flags, pd_match_pri);
3033                 } else {
3034                         netif_dbg(efx, probe, efx->net_dev,
3035                                   "%s: fw flags %#x pri %u supported as driver flags %#x pri %u\n",
3036                                   __func__, mcdi_flags, pd_match_pri,
3037                                   rc, table->rx_match_count);
3038                         table->rx_match_flags[table->rx_match_count++] = rc;
3039                 }
3040         }
3041
3042         table->entry = vzalloc(HUNT_FILTER_TBL_ROWS * sizeof(*table->entry));
3043         if (!table->entry) {
3044                 rc = -ENOMEM;
3045                 goto fail;
3046         }
3047
3048         efx->filter_state = table;
3049         init_waitqueue_head(&table->waitq);
3050         return 0;
3051
3052 fail:
3053         kfree(table);
3054         return rc;
3055 }
3056
3057 static void efx_ef10_filter_table_restore(struct efx_nic *efx)
3058 {
3059         struct efx_ef10_filter_table *table = efx->filter_state;
3060         struct efx_ef10_nic_data *nic_data = efx->nic_data;
3061         struct efx_filter_spec *spec;
3062         unsigned int filter_idx;
3063         bool failed = false;
3064         int rc;
3065
3066         if (!nic_data->must_restore_filters)
3067                 return;
3068
3069         spin_lock_bh(&efx->filter_lock);
3070
3071         for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
3072                 spec = efx_ef10_filter_entry_spec(table, filter_idx);
3073                 if (!spec)
3074                         continue;
3075
3076                 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
3077                 spin_unlock_bh(&efx->filter_lock);
3078
3079                 rc = efx_ef10_filter_push(efx, spec,
3080                                           &table->entry[filter_idx].handle,
3081                                           false);
3082                 if (rc)
3083                         failed = true;
3084
3085                 spin_lock_bh(&efx->filter_lock);
3086                 if (rc) {
3087                         kfree(spec);
3088                         efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
3089                 } else {
3090                         table->entry[filter_idx].spec &=
3091                                 ~EFX_EF10_FILTER_FLAG_BUSY;
3092                 }
3093         }
3094
3095         spin_unlock_bh(&efx->filter_lock);
3096
3097         if (failed)
3098                 netif_err(efx, hw, efx->net_dev,
3099                           "unable to restore all filters\n");
3100         else
3101                 nic_data->must_restore_filters = false;
3102 }
3103
3104 static void efx_ef10_filter_table_remove(struct efx_nic *efx)
3105 {
3106         struct efx_ef10_filter_table *table = efx->filter_state;
3107         MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
3108         struct efx_filter_spec *spec;
3109         unsigned int filter_idx;
3110         int rc;
3111
3112         for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
3113                 spec = efx_ef10_filter_entry_spec(table, filter_idx);
3114                 if (!spec)
3115                         continue;
3116
3117                 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3118                                efx_ef10_filter_is_exclusive(spec) ?
3119                                MC_CMD_FILTER_OP_IN_OP_REMOVE :
3120                                MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
3121                 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
3122                                table->entry[filter_idx].handle);
3123                 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
3124                                   NULL, 0, NULL);
3125                 if (rc)
3126                         netdev_WARN(efx->net_dev,
3127                                     "filter_idx=%#x handle=%#llx\n",
3128                                     filter_idx,
3129                                     table->entry[filter_idx].handle);
3130                 kfree(spec);
3131         }
3132
3133         vfree(table->entry);
3134         kfree(table);
3135 }
3136
3137 static void efx_ef10_filter_sync_rx_mode(struct efx_nic *efx)
3138 {
3139         struct efx_ef10_filter_table *table = efx->filter_state;
3140         struct net_device *net_dev = efx->net_dev;
3141         struct efx_filter_spec spec;
3142         bool remove_failed = false;
3143         struct netdev_hw_addr *uc;
3144         struct netdev_hw_addr *mc;
3145         unsigned int filter_idx;
3146         int i, n, rc;
3147
3148         if (!efx_dev_registered(efx))
3149                 return;
3150
3151         /* Mark old filters that may need to be removed */
3152         spin_lock_bh(&efx->filter_lock);
3153         n = table->dev_uc_count < 0 ? 1 : table->dev_uc_count;
3154         for (i = 0; i < n; i++) {
3155                 filter_idx = table->dev_uc_list[i].id % HUNT_FILTER_TBL_ROWS;
3156                 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_AUTO_OLD;
3157         }
3158         n = table->dev_mc_count < 0 ? 1 : table->dev_mc_count;
3159         for (i = 0; i < n; i++) {
3160                 filter_idx = table->dev_mc_list[i].id % HUNT_FILTER_TBL_ROWS;
3161                 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_AUTO_OLD;
3162         }
3163         spin_unlock_bh(&efx->filter_lock);
3164
3165         /* Copy/convert the address lists; add the primary station
3166          * address and broadcast address
3167          */
3168         netif_addr_lock_bh(net_dev);
3169         if (net_dev->flags & IFF_PROMISC ||
3170             netdev_uc_count(net_dev) >= EFX_EF10_FILTER_DEV_UC_MAX) {
3171                 table->dev_uc_count = -1;
3172         } else {
3173                 table->dev_uc_count = 1 + netdev_uc_count(net_dev);
3174                 ether_addr_copy(table->dev_uc_list[0].addr, net_dev->dev_addr);
3175                 i = 1;
3176                 netdev_for_each_uc_addr(uc, net_dev) {
3177                         ether_addr_copy(table->dev_uc_list[i].addr, uc->addr);
3178                         i++;
3179                 }
3180         }
3181         if (net_dev->flags & (IFF_PROMISC | IFF_ALLMULTI) ||
3182             netdev_mc_count(net_dev) >= EFX_EF10_FILTER_DEV_MC_MAX) {
3183                 table->dev_mc_count = -1;
3184         } else {
3185                 table->dev_mc_count = 1 + netdev_mc_count(net_dev);
3186                 eth_broadcast_addr(table->dev_mc_list[0].addr);
3187                 i = 1;
3188                 netdev_for_each_mc_addr(mc, net_dev) {
3189                         ether_addr_copy(table->dev_mc_list[i].addr, mc->addr);
3190                         i++;
3191                 }
3192         }
3193         netif_addr_unlock_bh(net_dev);
3194
3195         /* Insert/renew unicast filters */
3196         if (table->dev_uc_count >= 0) {
3197                 for (i = 0; i < table->dev_uc_count; i++) {
3198                         efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO,
3199                                            EFX_FILTER_FLAG_RX_RSS,
3200                                            0);
3201                         efx_filter_set_eth_local(&spec, EFX_FILTER_VID_UNSPEC,
3202                                                  table->dev_uc_list[i].addr);
3203                         rc = efx_ef10_filter_insert(efx, &spec, true);
3204                         if (rc < 0) {
3205                                 /* Fall back to unicast-promisc */
3206                                 while (i--)
3207                                         efx_ef10_filter_remove_safe(
3208                                                 efx, EFX_FILTER_PRI_AUTO,
3209                                                 table->dev_uc_list[i].id);
3210                                 table->dev_uc_count = -1;
3211                                 break;
3212                         }
3213                         table->dev_uc_list[i].id = rc;
3214                 }
3215         }
3216         if (table->dev_uc_count < 0) {
3217                 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO,
3218                                    EFX_FILTER_FLAG_RX_RSS,
3219                                    0);
3220                 efx_filter_set_uc_def(&spec);
3221                 rc = efx_ef10_filter_insert(efx, &spec, true);
3222                 if (rc < 0) {
3223                         WARN_ON(1);
3224                         table->dev_uc_count = 0;
3225                 } else {
3226                         table->dev_uc_list[0].id = rc;
3227                 }
3228         }
3229
3230         /* Insert/renew multicast filters */
3231         if (table->dev_mc_count >= 0) {
3232                 for (i = 0; i < table->dev_mc_count; i++) {
3233                         efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO,
3234                                            EFX_FILTER_FLAG_RX_RSS,
3235                                            0);
3236                         efx_filter_set_eth_local(&spec, EFX_FILTER_VID_UNSPEC,
3237                                                  table->dev_mc_list[i].addr);
3238                         rc = efx_ef10_filter_insert(efx, &spec, true);
3239                         if (rc < 0) {
3240                                 /* Fall back to multicast-promisc */
3241                                 while (i--)
3242                                         efx_ef10_filter_remove_safe(
3243                                                 efx, EFX_FILTER_PRI_AUTO,
3244                                                 table->dev_mc_list[i].id);
3245                                 table->dev_mc_count = -1;
3246                                 break;
3247                         }
3248                         table->dev_mc_list[i].id = rc;
3249                 }
3250         }
3251         if (table->dev_mc_count < 0) {
3252                 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO,
3253                                    EFX_FILTER_FLAG_RX_RSS,
3254                                    0);
3255                 efx_filter_set_mc_def(&spec);
3256                 rc = efx_ef10_filter_insert(efx, &spec, true);
3257                 if (rc < 0) {
3258                         WARN_ON(1);
3259                         table->dev_mc_count = 0;
3260                 } else {
3261                         table->dev_mc_list[0].id = rc;
3262                 }
3263         }
3264
3265         /* Remove filters that weren't renewed.  Since nothing else
3266          * changes the AUTO_OLD flag or removes these filters, we
3267          * don't need to hold the filter_lock while scanning for
3268          * these filters.
3269          */
3270         for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) {
3271                 if (ACCESS_ONCE(table->entry[i].spec) &
3272                     EFX_EF10_FILTER_FLAG_AUTO_OLD) {
3273                         if (efx_ef10_filter_remove_internal(
3274                                     efx, 1U << EFX_FILTER_PRI_AUTO,
3275                                     i, true) < 0)
3276                                 remove_failed = true;
3277                 }
3278         }
3279         WARN_ON(remove_failed);
3280 }
3281
3282 static int efx_ef10_mac_reconfigure(struct efx_nic *efx)
3283 {
3284         efx_ef10_filter_sync_rx_mode(efx);
3285
3286         return efx_mcdi_set_mac(efx);
3287 }
3288
3289 static int efx_ef10_start_bist(struct efx_nic *efx, u32 bist_type)
3290 {
3291         MCDI_DECLARE_BUF(inbuf, MC_CMD_START_BIST_IN_LEN);
3292
3293         MCDI_SET_DWORD(inbuf, START_BIST_IN_TYPE, bist_type);
3294         return efx_mcdi_rpc(efx, MC_CMD_START_BIST, inbuf, sizeof(inbuf),
3295                             NULL, 0, NULL);
3296 }
3297
3298 /* MC BISTs follow a different poll mechanism to phy BISTs.
3299  * The BIST is done in the poll handler on the MC, and the MCDI command
3300  * will block until the BIST is done.
3301  */
3302 static int efx_ef10_poll_bist(struct efx_nic *efx)
3303 {
3304         int rc;
3305         MCDI_DECLARE_BUF(outbuf, MC_CMD_POLL_BIST_OUT_LEN);
3306         size_t outlen;
3307         u32 result;
3308
3309         rc = efx_mcdi_rpc(efx, MC_CMD_POLL_BIST, NULL, 0,
3310                            outbuf, sizeof(outbuf), &outlen);
3311         if (rc != 0)
3312                 return rc;
3313
3314         if (outlen < MC_CMD_POLL_BIST_OUT_LEN)
3315                 return -EIO;
3316
3317         result = MCDI_DWORD(outbuf, POLL_BIST_OUT_RESULT);
3318         switch (result) {
3319         case MC_CMD_POLL_BIST_PASSED:
3320                 netif_dbg(efx, hw, efx->net_dev, "BIST passed.\n");
3321                 return 0;
3322         case MC_CMD_POLL_BIST_TIMEOUT:
3323                 netif_err(efx, hw, efx->net_dev, "BIST timed out\n");
3324                 return -EIO;
3325         case MC_CMD_POLL_BIST_FAILED:
3326                 netif_err(efx, hw, efx->net_dev, "BIST failed.\n");
3327                 return -EIO;
3328         default:
3329                 netif_err(efx, hw, efx->net_dev,
3330                           "BIST returned unknown result %u", result);
3331                 return -EIO;
3332         }
3333 }
3334
3335 static int efx_ef10_run_bist(struct efx_nic *efx, u32 bist_type)
3336 {
3337         int rc;
3338
3339         netif_dbg(efx, drv, efx->net_dev, "starting BIST type %u\n", bist_type);
3340
3341         rc = efx_ef10_start_bist(efx, bist_type);
3342         if (rc != 0)
3343                 return rc;
3344
3345         return efx_ef10_poll_bist(efx);
3346 }
3347
3348 static int
3349 efx_ef10_test_chip(struct efx_nic *efx, struct efx_self_tests *tests)
3350 {
3351         int rc, rc2;
3352
3353         efx_reset_down(efx, RESET_TYPE_WORLD);
3354
3355         rc = efx_mcdi_rpc(efx, MC_CMD_ENABLE_OFFLINE_BIST,
3356                           NULL, 0, NULL, 0, NULL);
3357         if (rc != 0)
3358                 goto out;
3359
3360         tests->memory = efx_ef10_run_bist(efx, MC_CMD_MC_MEM_BIST) ? -1 : 1;
3361         tests->registers = efx_ef10_run_bist(efx, MC_CMD_REG_BIST) ? -1 : 1;
3362
3363         rc = efx_mcdi_reset(efx, RESET_TYPE_WORLD);
3364
3365 out:
3366         rc2 = efx_reset_up(efx, RESET_TYPE_WORLD, rc == 0);
3367         return rc ? rc : rc2;
3368 }
3369
3370 #ifdef CONFIG_SFC_MTD
3371
3372 struct efx_ef10_nvram_type_info {
3373         u16 type, type_mask;
3374         u8 port;
3375         const char *name;
3376 };
3377
3378 static const struct efx_ef10_nvram_type_info efx_ef10_nvram_types[] = {
3379         { NVRAM_PARTITION_TYPE_MC_FIRMWARE,        0,    0, "sfc_mcfw" },
3380         { NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP, 0,    0, "sfc_mcfw_backup" },
3381         { NVRAM_PARTITION_TYPE_EXPANSION_ROM,      0,    0, "sfc_exp_rom" },
3382         { NVRAM_PARTITION_TYPE_STATIC_CONFIG,      0,    0, "sfc_static_cfg" },
3383         { NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG,     0,    0, "sfc_dynamic_cfg" },
3384         { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0, 0,   0, "sfc_exp_rom_cfg" },
3385         { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1, 0,   1, "sfc_exp_rom_cfg" },
3386         { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2, 0,   2, "sfc_exp_rom_cfg" },
3387         { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3, 0,   3, "sfc_exp_rom_cfg" },
3388         { NVRAM_PARTITION_TYPE_LICENSE,            0,    0, "sfc_license" },
3389         { NVRAM_PARTITION_TYPE_PHY_MIN,            0xff, 0, "sfc_phy_fw" },
3390 };
3391
3392 static int efx_ef10_mtd_probe_partition(struct efx_nic *efx,
3393                                         struct efx_mcdi_mtd_partition *part,
3394                                         unsigned int type)
3395 {
3396         MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_METADATA_IN_LEN);
3397         MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_METADATA_OUT_LENMAX);
3398         const struct efx_ef10_nvram_type_info *info;
3399         size_t size, erase_size, outlen;
3400         bool protected;
3401         int rc;
3402
3403         for (info = efx_ef10_nvram_types; ; info++) {
3404                 if (info ==
3405                     efx_ef10_nvram_types + ARRAY_SIZE(efx_ef10_nvram_types))
3406                         return -ENODEV;
3407                 if ((type & ~info->type_mask) == info->type)
3408                         break;
3409         }
3410         if (info->port != efx_port_num(efx))
3411                 return -ENODEV;
3412
3413         rc = efx_mcdi_nvram_info(efx, type, &size, &erase_size, &protected);
3414         if (rc)
3415                 return rc;
3416         if (protected)
3417                 return -ENODEV; /* hide it */
3418
3419         part->nvram_type = type;
3420
3421         MCDI_SET_DWORD(inbuf, NVRAM_METADATA_IN_TYPE, type);
3422         rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_METADATA, inbuf, sizeof(inbuf),
3423                           outbuf, sizeof(outbuf), &outlen);
3424         if (rc)
3425                 return rc;
3426         if (outlen < MC_CMD_NVRAM_METADATA_OUT_LENMIN)
3427                 return -EIO;
3428         if (MCDI_DWORD(outbuf, NVRAM_METADATA_OUT_FLAGS) &
3429             (1 << MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN))
3430                 part->fw_subtype = MCDI_DWORD(outbuf,
3431                                               NVRAM_METADATA_OUT_SUBTYPE);
3432
3433         part->common.dev_type_name = "EF10 NVRAM manager";
3434         part->common.type_name = info->name;
3435
3436         part->common.mtd.type = MTD_NORFLASH;
3437         part->common.mtd.flags = MTD_CAP_NORFLASH;
3438         part->common.mtd.size = size;
3439         part->common.mtd.erasesize = erase_size;
3440
3441         return 0;
3442 }
3443
3444 static int efx_ef10_mtd_probe(struct efx_nic *efx)
3445 {
3446         MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX);
3447         struct efx_mcdi_mtd_partition *parts;
3448         size_t outlen, n_parts_total, i, n_parts;
3449         unsigned int type;
3450         int rc;
3451
3452         ASSERT_RTNL();
3453
3454         BUILD_BUG_ON(MC_CMD_NVRAM_PARTITIONS_IN_LEN != 0);
3455         rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_PARTITIONS, NULL, 0,
3456                           outbuf, sizeof(outbuf), &outlen);
3457         if (rc)
3458                 return rc;
3459         if (outlen < MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN)
3460                 return -EIO;
3461
3462         n_parts_total = MCDI_DWORD(outbuf, NVRAM_PARTITIONS_OUT_NUM_PARTITIONS);
3463         if (n_parts_total >
3464             MCDI_VAR_ARRAY_LEN(outlen, NVRAM_PARTITIONS_OUT_TYPE_ID))
3465                 return -EIO;
3466
3467         parts = kcalloc(n_parts_total, sizeof(*parts), GFP_KERNEL);
3468         if (!parts)
3469                 return -ENOMEM;
3470
3471         n_parts = 0;
3472         for (i = 0; i < n_parts_total; i++) {
3473                 type = MCDI_ARRAY_DWORD(outbuf, NVRAM_PARTITIONS_OUT_TYPE_ID,
3474                                         i);
3475                 rc = efx_ef10_mtd_probe_partition(efx, &parts[n_parts], type);
3476                 if (rc == 0)
3477                         n_parts++;
3478                 else if (rc != -ENODEV)
3479                         goto fail;
3480         }
3481
3482         rc = efx_mtd_add(efx, &parts[0].common, n_parts, sizeof(*parts));
3483 fail:
3484         if (rc)
3485                 kfree(parts);
3486         return rc;
3487 }
3488
3489 #endif /* CONFIG_SFC_MTD */
3490
3491 static void efx_ef10_ptp_write_host_time(struct efx_nic *efx, u32 host_time)
3492 {
3493         _efx_writed(efx, cpu_to_le32(host_time), ER_DZ_MC_DB_LWRD);
3494 }
3495
3496 static int efx_ef10_rx_enable_timestamping(struct efx_channel *channel,
3497                                            bool temp)
3498 {
3499         MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_LEN);
3500         int rc;
3501
3502         if (channel->sync_events_state == SYNC_EVENTS_REQUESTED ||
3503             channel->sync_events_state == SYNC_EVENTS_VALID ||
3504             (temp && channel->sync_events_state == SYNC_EVENTS_DISABLED))
3505                 return 0;
3506         channel->sync_events_state = SYNC_EVENTS_REQUESTED;
3507
3508         MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE);
3509         MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0);
3510         MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE,
3511                        channel->channel);
3512
3513         rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP,
3514                           inbuf, sizeof(inbuf), NULL, 0, NULL);
3515
3516         if (rc != 0)
3517                 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT :
3518                                                     SYNC_EVENTS_DISABLED;
3519
3520         return rc;
3521 }
3522
3523 static int efx_ef10_rx_disable_timestamping(struct efx_channel *channel,
3524                                             bool temp)
3525 {
3526         MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_LEN);
3527         int rc;
3528
3529         if (channel->sync_events_state == SYNC_EVENTS_DISABLED ||
3530             (temp && channel->sync_events_state == SYNC_EVENTS_QUIESCENT))
3531                 return 0;
3532         if (channel->sync_events_state == SYNC_EVENTS_QUIESCENT) {
3533                 channel->sync_events_state = SYNC_EVENTS_DISABLED;
3534                 return 0;
3535         }
3536         channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT :
3537                                             SYNC_EVENTS_DISABLED;
3538
3539         MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE);
3540         MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0);
3541         MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL,
3542                        MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE);
3543         MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE,
3544                        channel->channel);
3545
3546         rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP,
3547                           inbuf, sizeof(inbuf), NULL, 0, NULL);
3548
3549         return rc;
3550 }
3551
3552 static int efx_ef10_ptp_set_ts_sync_events(struct efx_nic *efx, bool en,
3553                                            bool temp)
3554 {
3555         int (*set)(struct efx_channel *channel, bool temp);
3556         struct efx_channel *channel;
3557
3558         set = en ?
3559               efx_ef10_rx_enable_timestamping :
3560               efx_ef10_rx_disable_timestamping;
3561
3562         efx_for_each_channel(channel, efx) {
3563                 int rc = set(channel, temp);
3564                 if (en && rc != 0) {
3565                         efx_ef10_ptp_set_ts_sync_events(efx, false, temp);
3566                         return rc;
3567                 }
3568         }
3569
3570         return 0;
3571 }
3572
3573 static int efx_ef10_ptp_set_ts_config(struct efx_nic *efx,
3574                                       struct hwtstamp_config *init)
3575 {
3576         int rc;
3577
3578         switch (init->rx_filter) {
3579         case HWTSTAMP_FILTER_NONE:
3580                 efx_ef10_ptp_set_ts_sync_events(efx, false, false);
3581                 /* if TX timestamping is still requested then leave PTP on */
3582                 return efx_ptp_change_mode(efx,
3583                                            init->tx_type != HWTSTAMP_TX_OFF, 0);
3584         case HWTSTAMP_FILTER_ALL:
3585         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
3586         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
3587         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
3588         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
3589         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
3590         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
3591         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
3592         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
3593         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
3594         case HWTSTAMP_FILTER_PTP_V2_EVENT:
3595         case HWTSTAMP_FILTER_PTP_V2_SYNC:
3596         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
3597                 init->rx_filter = HWTSTAMP_FILTER_ALL;
3598                 rc = efx_ptp_change_mode(efx, true, 0);
3599                 if (!rc)
3600                         rc = efx_ef10_ptp_set_ts_sync_events(efx, true, false);
3601                 if (rc)
3602                         efx_ptp_change_mode(efx, false, 0);
3603                 return rc;
3604         default:
3605                 return -ERANGE;
3606         }
3607 }
3608
3609 const struct efx_nic_type efx_hunt_a0_nic_type = {
3610         .mem_map_size = efx_ef10_mem_map_size,
3611         .probe = efx_ef10_probe,
3612         .remove = efx_ef10_remove,
3613         .dimension_resources = efx_ef10_dimension_resources,
3614         .init = efx_ef10_init_nic,
3615         .fini = efx_port_dummy_op_void,
3616         .map_reset_reason = efx_mcdi_map_reset_reason,
3617         .map_reset_flags = efx_ef10_map_reset_flags,
3618         .reset = efx_ef10_reset,
3619         .probe_port = efx_mcdi_port_probe,
3620         .remove_port = efx_mcdi_port_remove,
3621         .fini_dmaq = efx_ef10_fini_dmaq,
3622         .prepare_flr = efx_ef10_prepare_flr,
3623         .finish_flr = efx_port_dummy_op_void,
3624         .describe_stats = efx_ef10_describe_stats,
3625         .update_stats = efx_ef10_update_stats,
3626         .start_stats = efx_mcdi_mac_start_stats,
3627         .pull_stats = efx_mcdi_mac_pull_stats,
3628         .stop_stats = efx_mcdi_mac_stop_stats,
3629         .set_id_led = efx_mcdi_set_id_led,
3630         .push_irq_moderation = efx_ef10_push_irq_moderation,
3631         .reconfigure_mac = efx_ef10_mac_reconfigure,
3632         .check_mac_fault = efx_mcdi_mac_check_fault,
3633         .reconfigure_port = efx_mcdi_port_reconfigure,
3634         .get_wol = efx_ef10_get_wol,
3635         .set_wol = efx_ef10_set_wol,
3636         .resume_wol = efx_port_dummy_op_void,
3637         .test_chip = efx_ef10_test_chip,
3638         .test_nvram = efx_mcdi_nvram_test_all,
3639         .mcdi_request = efx_ef10_mcdi_request,
3640         .mcdi_poll_response = efx_ef10_mcdi_poll_response,
3641         .mcdi_read_response = efx_ef10_mcdi_read_response,
3642         .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot,
3643         .irq_enable_master = efx_port_dummy_op_void,
3644         .irq_test_generate = efx_ef10_irq_test_generate,
3645         .irq_disable_non_ev = efx_port_dummy_op_void,
3646         .irq_handle_msi = efx_ef10_msi_interrupt,
3647         .irq_handle_legacy = efx_ef10_legacy_interrupt,
3648         .tx_probe = efx_ef10_tx_probe,
3649         .tx_init = efx_ef10_tx_init,
3650         .tx_remove = efx_ef10_tx_remove,
3651         .tx_write = efx_ef10_tx_write,
3652         .rx_push_rss_config = efx_ef10_rx_push_rss_config,
3653         .rx_probe = efx_ef10_rx_probe,
3654         .rx_init = efx_ef10_rx_init,
3655         .rx_remove = efx_ef10_rx_remove,
3656         .rx_write = efx_ef10_rx_write,
3657         .rx_defer_refill = efx_ef10_rx_defer_refill,
3658         .ev_probe = efx_ef10_ev_probe,
3659         .ev_init = efx_ef10_ev_init,
3660         .ev_fini = efx_ef10_ev_fini,
3661         .ev_remove = efx_ef10_ev_remove,
3662         .ev_process = efx_ef10_ev_process,
3663         .ev_read_ack = efx_ef10_ev_read_ack,
3664         .ev_test_generate = efx_ef10_ev_test_generate,
3665         .filter_table_probe = efx_ef10_filter_table_probe,
3666         .filter_table_restore = efx_ef10_filter_table_restore,
3667         .filter_table_remove = efx_ef10_filter_table_remove,
3668         .filter_update_rx_scatter = efx_ef10_filter_update_rx_scatter,
3669         .filter_insert = efx_ef10_filter_insert,
3670         .filter_remove_safe = efx_ef10_filter_remove_safe,
3671         .filter_get_safe = efx_ef10_filter_get_safe,
3672         .filter_clear_rx = efx_ef10_filter_clear_rx,
3673         .filter_count_rx_used = efx_ef10_filter_count_rx_used,
3674         .filter_get_rx_id_limit = efx_ef10_filter_get_rx_id_limit,
3675         .filter_get_rx_ids = efx_ef10_filter_get_rx_ids,
3676 #ifdef CONFIG_RFS_ACCEL
3677         .filter_rfs_insert = efx_ef10_filter_rfs_insert,
3678         .filter_rfs_expire_one = efx_ef10_filter_rfs_expire_one,
3679 #endif
3680 #ifdef CONFIG_SFC_MTD
3681         .mtd_probe = efx_ef10_mtd_probe,
3682         .mtd_rename = efx_mcdi_mtd_rename,
3683         .mtd_read = efx_mcdi_mtd_read,
3684         .mtd_erase = efx_mcdi_mtd_erase,
3685         .mtd_write = efx_mcdi_mtd_write,
3686         .mtd_sync = efx_mcdi_mtd_sync,
3687 #endif
3688         .ptp_write_host_time = efx_ef10_ptp_write_host_time,
3689         .ptp_set_ts_sync_events = efx_ef10_ptp_set_ts_sync_events,
3690         .ptp_set_ts_config = efx_ef10_ptp_set_ts_config,
3691
3692         .revision = EFX_REV_HUNT_A0,
3693         .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH),
3694         .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE,
3695         .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST,
3696         .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST,
3697         .can_rx_scatter = true,
3698         .always_rx_scatter = true,
3699         .max_interrupt_mode = EFX_INT_MODE_MSIX,
3700         .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH,
3701         .offload_features = (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
3702                              NETIF_F_RXHASH | NETIF_F_NTUPLE),
3703         .mcdi_max_ver = 2,
3704         .max_rx_ip_filters = HUNT_FILTER_TBL_ROWS,
3705         .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE |
3706                             1 << HWTSTAMP_FILTER_ALL,
3707 };