drivers/net/ethernet/sfc/ef10.c

   1 /****************************************************************************
   2  * Driver for Solarflare network controllers and boards
   3  * Copyright 2012-2013 Solarflare Communications Inc.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 as published
   7  * by the Free Software Foundation, incorporated herein by reference.
   8  */
   9
  10 #include "net_driver.h"
  11 #include "ef10_regs.h"
  12 #include "io.h"
  13 #include "mcdi.h"
  14 #include "mcdi_pcol.h"
  15 #include "nic.h"
  16 #include "workarounds.h"
  17 #include "selftest.h"
  18 #include "ef10_sriov.h"
  19 #include <linux/in.h>
  20 #include <linux/jhash.h>
  21 #include <linux/wait.h>
  22 #include <linux/workqueue.h>
  23
  24 /* Hardware control for EF10 architecture including 'Huntington'. */
  25
  26 #define EFX_EF10_DRVGEN_EV              7
  27 enum {
  28         EFX_EF10_TEST = 1,
  29         EFX_EF10_REFILL,
  30 };
  31
  32 /* The reserved RSS context value */
  33 #define EFX_EF10_RSS_CONTEXT_INVALID    0xffffffff
  34 /* The maximum size of a shared RSS context */
  35 /* TODO: this should really be from the mcdi protocol export */
  36 #define EFX_EF10_MAX_SHARED_RSS_CONTEXT_SIZE 64UL
  37
  38 /* The filter table(s) are managed by firmware and we have write-only
  39  * access.  When removing filters we must identify them to the
  40  * firmware by a 64-bit handle, but this is too wide for Linux kernel
  41  * interfaces (32-bit for RX NFC, 16-bit for RFS).  Also, we need to
  42  * be able to tell in advance whether a requested insertion will
  43  * replace an existing filter.  Therefore we maintain a software hash
  44  * table, which should be at least as large as the hardware hash
  45  * table.
  46  *
  47  * Huntington has a single 8K filter table shared between all filter
  48  * types and both ports.
  49  */
  50 #define HUNT_FILTER_TBL_ROWS 8192
  51
  52 #define EFX_EF10_FILTER_ID_INVALID 0xffff
  53 struct efx_ef10_dev_addr {
  54         u8 addr[ETH_ALEN];
  55         u16 id;
  56 };
  57
  58 struct efx_ef10_filter_table {
  59 /* The RX match field masks supported by this fw & hw, in order of priority */
  60         enum efx_filter_match_flags rx_match_flags[
  61                 MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MAXNUM];
  62         unsigned int rx_match_count;
  63
  64         struct {
  65                 unsigned long spec;     /* pointer to spec plus flag bits */
  66 /* BUSY flag indicates that an update is in progress.  AUTO_OLD is
  67  * used to mark and sweep MAC filters for the device address lists.
  68  */
  69 #define EFX_EF10_FILTER_FLAG_BUSY       1UL
  70 #define EFX_EF10_FILTER_FLAG_AUTO_OLD   2UL
  71 #define EFX_EF10_FILTER_FLAGS           3UL
  72                 u64 handle;             /* firmware handle */
  73         } *entry;
  74         wait_queue_head_t waitq;
  75 /* Shadow of net_device address lists, guarded by mac_lock */
  76 #define EFX_EF10_FILTER_DEV_UC_MAX      32
  77 #define EFX_EF10_FILTER_DEV_MC_MAX      256
  78         struct efx_ef10_dev_addr dev_uc_list[EFX_EF10_FILTER_DEV_UC_MAX];
  79         struct efx_ef10_dev_addr dev_mc_list[EFX_EF10_FILTER_DEV_MC_MAX];
  80         int dev_uc_count;
  81         int dev_mc_count;
  82 /* Indices (like efx_ef10_dev_addr.id) for promisc/allmulti filters */
  83         u16 ucdef_id;
  84         u16 bcast_id;
  85         u16 mcdef_id;
  86 };
  87
  88 /* An arbitrary search limit for the software hash table */
  89 #define EFX_EF10_FILTER_SEARCH_LIMIT 200
  90
  91 static void efx_ef10_rx_free_indir_table(struct efx_nic *efx);
  92 static void efx_ef10_filter_table_remove(struct efx_nic *efx);
  93
  94 static int efx_ef10_get_warm_boot_count(struct efx_nic *efx)
  95 {
  96         efx_dword_t reg;
  97
  98         efx_readd(efx, &reg, ER_DZ_BIU_MC_SFT_STATUS);
  99         return EFX_DWORD_FIELD(reg, EFX_WORD_1) == 0xb007 ?
 100                 EFX_DWORD_FIELD(reg, EFX_WORD_0) : -EIO;
 101 }
 102
 103 static unsigned int efx_ef10_mem_map_size(struct efx_nic *efx)
 104 {
 105         int bar;
 106
 107         bar = efx->type->mem_bar;
 108         return resource_size(&efx->pci_dev->resource[bar]);
 109 }
 110
 111 static bool efx_ef10_is_vf(struct efx_nic *efx)
 112 {
 113         return efx->type->is_vf;
 114 }
 115
 116 static int efx_ef10_get_pf_index(struct efx_nic *efx)
 117 {
 118         MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_FUNCTION_INFO_OUT_LEN);
 119         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 120         size_t outlen;
 121         int rc;
 122
 123         rc = efx_mcdi_rpc(efx, MC_CMD_GET_FUNCTION_INFO, NULL, 0, outbuf,
 124                           sizeof(outbuf), &outlen);
 125         if (rc)
 126                 return rc;
 127         if (outlen < sizeof(outbuf))
 128                 return -EIO;
 129
 130         nic_data->pf_index = MCDI_DWORD(outbuf, GET_FUNCTION_INFO_OUT_PF);
 131         return 0;
 132 }
 133
 134 #ifdef CONFIG_SFC_SRIOV
 135 static int efx_ef10_get_vf_index(struct efx_nic *efx)
 136 {
 137         MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_FUNCTION_INFO_OUT_LEN);
 138         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 139         size_t outlen;
 140         int rc;
 141
 142         rc = efx_mcdi_rpc(efx, MC_CMD_GET_FUNCTION_INFO, NULL, 0, outbuf,
 143                           sizeof(outbuf), &outlen);
 144         if (rc)
 145                 return rc;
 146         if (outlen < sizeof(outbuf))
 147                 return -EIO;
 148
 149         nic_data->vf_index = MCDI_DWORD(outbuf, GET_FUNCTION_INFO_OUT_VF);
 150         return 0;
 151 }
 152 #endif
 153
 154 static int efx_ef10_init_datapath_caps(struct efx_nic *efx)
 155 {
 156         MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CAPABILITIES_OUT_LEN);
 157         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 158         size_t outlen;
 159         int rc;
 160
 161         BUILD_BUG_ON(MC_CMD_GET_CAPABILITIES_IN_LEN != 0);
 162
 163         rc = efx_mcdi_rpc(efx, MC_CMD_GET_CAPABILITIES, NULL, 0,
 164                           outbuf, sizeof(outbuf), &outlen);
 165         if (rc)
 166                 return rc;
 167         if (outlen < sizeof(outbuf)) {
 168                 netif_err(efx, drv, efx->net_dev,
 169                           "unable to read datapath firmware capabilities\n");
 170                 return -EIO;
 171         }
 172
 173         nic_data->datapath_caps =
 174                 MCDI_DWORD(outbuf, GET_CAPABILITIES_OUT_FLAGS1);
 175
 176         /* record the DPCPU firmware IDs to determine VEB vswitching support.
 177          */
 178         nic_data->rx_dpcpu_fw_id =
 179                 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID);
 180         nic_data->tx_dpcpu_fw_id =
 181                 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID);
 182
 183         if (!(nic_data->datapath_caps &
 184               (1 << MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN))) {
 185                 netif_err(efx, drv, efx->net_dev,
 186                           "current firmware does not support TSO\n");
 187                 return -ENODEV;
 188         }
 189
 190         if (!(nic_data->datapath_caps &
 191               (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN))) {
 192                 netif_err(efx, probe, efx->net_dev,
 193                           "current firmware does not support an RX prefix\n");
 194                 return -ENODEV;
 195         }
 196
 197         return 0;
 198 }
 199
 200 static int efx_ef10_get_sysclk_freq(struct efx_nic *efx)
 201 {
 202         MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CLOCK_OUT_LEN);
 203         int rc;
 204
 205         rc = efx_mcdi_rpc(efx, MC_CMD_GET_CLOCK, NULL, 0,
 206                           outbuf, sizeof(outbuf), NULL);
 207         if (rc)
 208                 return rc;
 209         rc = MCDI_DWORD(outbuf, GET_CLOCK_OUT_SYS_FREQ);
 210         return rc > 0 ? rc : -ERANGE;
 211 }
 212
 213 static int efx_ef10_get_mac_address_pf(struct efx_nic *efx, u8 *mac_address)
 214 {
 215         MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_MAC_ADDRESSES_OUT_LEN);
 216         size_t outlen;
 217         int rc;
 218
 219         BUILD_BUG_ON(MC_CMD_GET_MAC_ADDRESSES_IN_LEN != 0);
 220
 221         rc = efx_mcdi_rpc(efx, MC_CMD_GET_MAC_ADDRESSES, NULL, 0,
 222                           outbuf, sizeof(outbuf), &outlen);
 223         if (rc)
 224                 return rc;
 225         if (outlen < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN)
 226                 return -EIO;
 227
 228         ether_addr_copy(mac_address,
 229                         MCDI_PTR(outbuf, GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE));
 230         return 0;
 231 }
 232
 233 static int efx_ef10_get_mac_address_vf(struct efx_nic *efx, u8 *mac_address)
 234 {
 235         MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN);
 236         MCDI_DECLARE_BUF(outbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX);
 237         size_t outlen;
 238         int num_addrs, rc;
 239
 240         MCDI_SET_DWORD(inbuf, VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID,
 241                        EVB_PORT_ID_ASSIGNED);
 242         rc = efx_mcdi_rpc(efx, MC_CMD_VPORT_GET_MAC_ADDRESSES, inbuf,
 243                           sizeof(inbuf), outbuf, sizeof(outbuf), &outlen);
 244
 245         if (rc)
 246                 return rc;
 247         if (outlen < MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN)
 248                 return -EIO;
 249
 250         num_addrs = MCDI_DWORD(outbuf,
 251                                VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT);
 252
 253         WARN_ON(num_addrs != 1);
 254
 255         ether_addr_copy(mac_address,
 256                         MCDI_PTR(outbuf, VPORT_GET_MAC_ADDRESSES_OUT_MACADDR));
 257
 258         return 0;
 259 }
 260
 261 static ssize_t efx_ef10_show_link_control_flag(struct device *dev,
 262                                                struct device_attribute *attr,
 263                                                char *buf)
 264 {
 265         struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
 266
 267         return sprintf(buf, "%d\n",
 268                        ((efx->mcdi->fn_flags) &
 269                         (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL))
 270                        ? 1 : 0);
 271 }
 272
 273 static ssize_t efx_ef10_show_primary_flag(struct device *dev,
 274                                           struct device_attribute *attr,
 275                                           char *buf)
 276 {
 277         struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
 278
 279         return sprintf(buf, "%d\n",
 280                        ((efx->mcdi->fn_flags) &
 281                         (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY))
 282                        ? 1 : 0);
 283 }
 284
 285 static DEVICE_ATTR(link_control_flag, 0444, efx_ef10_show_link_control_flag,
 286                    NULL);
 287 static DEVICE_ATTR(primary_flag, 0444, efx_ef10_show_primary_flag, NULL);
 288
 289 static int efx_ef10_probe(struct efx_nic *efx)
 290 {
 291         struct efx_ef10_nic_data *nic_data;
 292         struct net_device *net_dev = efx->net_dev;
 293         int i, rc;
 294
 295         /* We can have one VI for each 8K region.  However, until we
 296          * use TX option descriptors we need two TX queues per channel.
 297          */
 298         efx->max_channels = min_t(unsigned int,
 299                                   EFX_MAX_CHANNELS,
 300                                   efx_ef10_mem_map_size(efx) /
 301                                   (EFX_VI_PAGE_SIZE * EFX_TXQ_TYPES));
 302         efx->max_tx_channels = efx->max_channels;
 303         if (WARN_ON(efx->max_channels == 0))
 304                 return -EIO;
 305
 306         nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
 307         if (!nic_data)
 308                 return -ENOMEM;
 309         efx->nic_data = nic_data;
 310
 311         /* we assume later that we can copy from this buffer in dwords */
 312         BUILD_BUG_ON(MCDI_CTL_SDU_LEN_MAX_V2 % 4);
 313
 314         rc = efx_nic_alloc_buffer(efx, &nic_data->mcdi_buf,
 315                                   8 + MCDI_CTL_SDU_LEN_MAX_V2, GFP_KERNEL);
 316         if (rc)
 317                 goto fail1;
 318
 319         /* Get the MC's warm boot count.  In case it's rebooting right
 320          * now, be prepared to retry.
 321          */
 322         i = 0;
 323         for (;;) {
 324                 rc = efx_ef10_get_warm_boot_count(efx);
 325                 if (rc >= 0)
 326                         break;
 327                 if (++i == 5)
 328                         goto fail2;
 329                 ssleep(1);
 330         }
 331         nic_data->warm_boot_count = rc;
 332
 333         nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
 334
 335         nic_data->vport_id = EVB_PORT_ID_ASSIGNED;
 336
 337         /* In case we're recovering from a crash (kexec), we want to
 338          * cancel any outstanding request by the previous user of this
 339          * function.  We send a special message using the least
 340          * significant bits of the 'high' (doorbell) register.
 341          */
 342         _efx_writed(efx, cpu_to_le32(1), ER_DZ_MC_DB_HWRD);
 343
 344         rc = efx_mcdi_init(efx);
 345         if (rc)
 346                 goto fail2;
 347
 348         /* Reset (most) configuration for this function */
 349         rc = efx_mcdi_reset(efx, RESET_TYPE_ALL);
 350         if (rc)
 351                 goto fail3;
 352
 353         /* Enable event logging */
 354         rc = efx_mcdi_log_ctrl(efx, true, false, 0);
 355         if (rc)
 356                 goto fail3;
 357
 358         rc = device_create_file(&efx->pci_dev->dev,
 359                                 &dev_attr_link_control_flag);
 360         if (rc)
 361                 goto fail3;
 362
 363         rc = device_create_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
 364         if (rc)
 365                 goto fail4;
 366
 367         rc = efx_ef10_get_pf_index(efx);
 368         if (rc)
 369                 goto fail5;
 370
 371         rc = efx_ef10_init_datapath_caps(efx);
 372         if (rc < 0)
 373                 goto fail5;
 374
 375         efx->rx_packet_len_offset =
 376                 ES_DZ_RX_PREFIX_PKTLEN_OFST - ES_DZ_RX_PREFIX_SIZE;
 377
 378         rc = efx_mcdi_port_get_number(efx);
 379         if (rc < 0)
 380                 goto fail5;
 381         efx->port_num = rc;
 382         net_dev->dev_port = rc;
 383
 384         rc = efx->type->get_mac_address(efx, efx->net_dev->perm_addr);
 385         if (rc)
 386                 goto fail5;
 387
 388         rc = efx_ef10_get_sysclk_freq(efx);
 389         if (rc < 0)
 390                 goto fail5;
 391         efx->timer_quantum_ns = 1536000 / rc; /* 1536 cycles */
 392
 393         /* Check whether firmware supports bug 35388 workaround.
 394          * First try to enable it, then if we get EPERM, just
 395          * ask if it's already enabled
 396          */
 397         rc = efx_mcdi_set_workaround(efx, MC_CMD_WORKAROUND_BUG35388, true, NULL);
 398         if (rc == 0) {
 399                 nic_data->workaround_35388 = true;
 400         } else if (rc == -EPERM) {
 401                 unsigned int enabled;
 402
 403                 rc = efx_mcdi_get_workarounds(efx, NULL, &enabled);
 404                 if (rc)
 405                         goto fail3;
 406                 nic_data->workaround_35388 = enabled &
 407                         MC_CMD_GET_WORKAROUNDS_OUT_BUG35388;
 408         } else if (rc != -ENOSYS && rc != -ENOENT) {
 409                 goto fail5;
 410         }
 411         netif_dbg(efx, probe, efx->net_dev,
 412                   "workaround for bug 35388 is %sabled\n",
 413                   nic_data->workaround_35388 ? "en" : "dis");
 414
 415         rc = efx_mcdi_mon_probe(efx);
 416         if (rc && rc != -EPERM)
 417                 goto fail5;
 418
 419         efx_ptp_probe(efx, NULL);
 420
 421 #ifdef CONFIG_SFC_SRIOV
 422         if ((efx->pci_dev->physfn) && (!efx->pci_dev->is_physfn)) {
 423                 struct pci_dev *pci_dev_pf = efx->pci_dev->physfn;
 424                 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
 425
 426                 efx_pf->type->get_mac_address(efx_pf, nic_data->port_id);
 427         } else
 428 #endif
 429                 ether_addr_copy(nic_data->port_id, efx->net_dev->perm_addr);
 430
 431         return 0;
 432
 433 fail5:
 434         device_remove_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
 435 fail4:
 436         device_remove_file(&efx->pci_dev->dev, &dev_attr_link_control_flag);
 437 fail3:
 438         efx_mcdi_fini(efx);
 439 fail2:
 440         efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
 441 fail1:
 442         kfree(nic_data);
 443         efx->nic_data = NULL;
 444         return rc;
 445 }
 446
 447 static int efx_ef10_free_vis(struct efx_nic *efx)
 448 {
 449         MCDI_DECLARE_BUF_ERR(outbuf);
 450         size_t outlen;
 451         int rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FREE_VIS, NULL, 0,
 452                                     outbuf, sizeof(outbuf), &outlen);
 453
 454         /* -EALREADY means nothing to free, so ignore */
 455         if (rc == -EALREADY)
 456                 rc = 0;
 457         if (rc)
 458                 efx_mcdi_display_error(efx, MC_CMD_FREE_VIS, 0, outbuf, outlen,
 459                                        rc);
 460         return rc;
 461 }
 462
 463 #ifdef EFX_USE_PIO
 464
 465 static void efx_ef10_free_piobufs(struct efx_nic *efx)
 466 {
 467         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 468         MCDI_DECLARE_BUF(inbuf, MC_CMD_FREE_PIOBUF_IN_LEN);
 469         unsigned int i;
 470         int rc;
 471
 472         BUILD_BUG_ON(MC_CMD_FREE_PIOBUF_OUT_LEN != 0);
 473
 474         for (i = 0; i < nic_data->n_piobufs; i++) {
 475                 MCDI_SET_DWORD(inbuf, FREE_PIOBUF_IN_PIOBUF_HANDLE,
 476                                nic_data->piobuf_handle[i]);
 477                 rc = efx_mcdi_rpc(efx, MC_CMD_FREE_PIOBUF, inbuf, sizeof(inbuf),
 478                                   NULL, 0, NULL);
 479                 WARN_ON(rc);
 480         }
 481
 482         nic_data->n_piobufs = 0;
 483 }
 484
 485 static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n)
 486 {
 487         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 488         MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_PIOBUF_OUT_LEN);
 489         unsigned int i;
 490         size_t outlen;
 491         int rc = 0;
 492
 493         BUILD_BUG_ON(MC_CMD_ALLOC_PIOBUF_IN_LEN != 0);
 494
 495         for (i = 0; i < n; i++) {
 496                 rc = efx_mcdi_rpc(efx, MC_CMD_ALLOC_PIOBUF, NULL, 0,
 497                                   outbuf, sizeof(outbuf), &outlen);
 498                 if (rc)
 499                         break;
 500                 if (outlen < MC_CMD_ALLOC_PIOBUF_OUT_LEN) {
 501                         rc = -EIO;
 502                         break;
 503                 }
 504                 nic_data->piobuf_handle[i] =
 505                         MCDI_DWORD(outbuf, ALLOC_PIOBUF_OUT_PIOBUF_HANDLE);
 506                 netif_dbg(efx, probe, efx->net_dev,
 507                           "allocated PIO buffer %u handle %x\n", i,
 508                           nic_data->piobuf_handle[i]);
 509         }
 510
 511         nic_data->n_piobufs = i;
 512         if (rc)
 513                 efx_ef10_free_piobufs(efx);
 514         return rc;
 515 }
 516
 517 static int efx_ef10_link_piobufs(struct efx_nic *efx)
 518 {
 519         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 520         _MCDI_DECLARE_BUF(inbuf,
 521                           max(MC_CMD_LINK_PIOBUF_IN_LEN,
 522                               MC_CMD_UNLINK_PIOBUF_IN_LEN));
 523         struct efx_channel *channel;
 524         struct efx_tx_queue *tx_queue;
 525         unsigned int offset, index;
 526         int rc;
 527
 528         BUILD_BUG_ON(MC_CMD_LINK_PIOBUF_OUT_LEN != 0);
 529         BUILD_BUG_ON(MC_CMD_UNLINK_PIOBUF_OUT_LEN != 0);
 530
 531         memset(inbuf, 0, sizeof(inbuf));
 532
 533         /* Link a buffer to each VI in the write-combining mapping */
 534         for (index = 0; index < nic_data->n_piobufs; ++index) {
 535                 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_PIOBUF_HANDLE,
 536                                nic_data->piobuf_handle[index]);
 537                 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_TXQ_INSTANCE,
 538                                nic_data->pio_write_vi_base + index);
 539                 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF,
 540                                   inbuf, MC_CMD_LINK_PIOBUF_IN_LEN,
 541                                   NULL, 0, NULL);
 542                 if (rc) {
 543                         netif_err(efx, drv, efx->net_dev,
 544                                   "failed to link VI %u to PIO buffer %u (%d)\n",
 545                                   nic_data->pio_write_vi_base + index, index,
 546                                   rc);
 547                         goto fail;
 548                 }
 549                 netif_dbg(efx, probe, efx->net_dev,
 550                           "linked VI %u to PIO buffer %u\n",
 551                           nic_data->pio_write_vi_base + index, index);
 552         }
 553
 554         /* Link a buffer to each TX queue */
 555         efx_for_each_channel(channel, efx) {
 556                 efx_for_each_channel_tx_queue(tx_queue, channel) {
 557                         /* We assign the PIO buffers to queues in
 558                          * reverse order to allow for the following
 559                          * special case.
 560                          */
 561                         offset = ((efx->tx_channel_offset + efx->n_tx_channels -
 562                                    tx_queue->channel->channel - 1) *
 563                                   efx_piobuf_size);
 564                         index = offset / ER_DZ_TX_PIOBUF_SIZE;
 565                         offset = offset % ER_DZ_TX_PIOBUF_SIZE;
 566
 567                         /* When the host page size is 4K, the first
 568                          * host page in the WC mapping may be within
 569                          * the same VI page as the last TX queue.  We
 570                          * can only link one buffer to each VI.
 571                          */
 572                         if (tx_queue->queue == nic_data->pio_write_vi_base) {
 573                                 BUG_ON(index != 0);
 574                                 rc = 0;
 575                         } else {
 576                                 MCDI_SET_DWORD(inbuf,
 577                                                LINK_PIOBUF_IN_PIOBUF_HANDLE,
 578                                                nic_data->piobuf_handle[index]);
 579                                 MCDI_SET_DWORD(inbuf,
 580                                                LINK_PIOBUF_IN_TXQ_INSTANCE,
 581                                                tx_queue->queue);
 582                                 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF,
 583                                                   inbuf, MC_CMD_LINK_PIOBUF_IN_LEN,
 584                                                   NULL, 0, NULL);
 585                         }
 586
 587                         if (rc) {
 588                                 /* This is non-fatal; the TX path just
 589                                  * won't use PIO for this queue
 590                                  */
 591                                 netif_err(efx, drv, efx->net_dev,
 592                                           "failed to link VI %u to PIO buffer %u (%d)\n",
 593                                           tx_queue->queue, index, rc);
 594                                 tx_queue->piobuf = NULL;
 595                         } else {
 596                                 tx_queue->piobuf =
 597                                         nic_data->pio_write_base +
 598                                         index * EFX_VI_PAGE_SIZE + offset;
 599                                 tx_queue->piobuf_offset = offset;
 600                                 netif_dbg(efx, probe, efx->net_dev,
 601                                           "linked VI %u to PIO buffer %u offset %x addr %p\n",
 602                                           tx_queue->queue, index,
 603                                           tx_queue->piobuf_offset,
 604                                           tx_queue->piobuf);
 605                         }
 606                 }
 607         }
 608
 609         return 0;
 610
 611 fail:
 612         while (index--) {
 613                 MCDI_SET_DWORD(inbuf, UNLINK_PIOBUF_IN_TXQ_INSTANCE,
 614                                nic_data->pio_write_vi_base + index);
 615                 efx_mcdi_rpc(efx, MC_CMD_UNLINK_PIOBUF,
 616                              inbuf, MC_CMD_UNLINK_PIOBUF_IN_LEN,
 617                              NULL, 0, NULL);
 618         }
 619         return rc;
 620 }
 621
 622 #else /* !EFX_USE_PIO */
 623
 624 static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n)
 625 {
 626         return n == 0 ? 0 : -ENOBUFS;
 627 }
 628
 629 static int efx_ef10_link_piobufs(struct efx_nic *efx)
 630 {
 631         return 0;
 632 }
 633
 634 static void efx_ef10_free_piobufs(struct efx_nic *efx)
 635 {
 636 }
 637
 638 #endif /* EFX_USE_PIO */
 639
 640 static void efx_ef10_remove(struct efx_nic *efx)
 641 {
 642         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 643         int rc;
 644
 645 #ifdef CONFIG_SFC_SRIOV
 646         struct efx_ef10_nic_data *nic_data_pf;
 647         struct pci_dev *pci_dev_pf;
 648         struct efx_nic *efx_pf;
 649         struct ef10_vf *vf;
 650
 651         if (efx->pci_dev->is_virtfn) {
 652                 pci_dev_pf = efx->pci_dev->physfn;
 653                 if (pci_dev_pf) {
 654                         efx_pf = pci_get_drvdata(pci_dev_pf);
 655                         nic_data_pf = efx_pf->nic_data;
 656                         vf = nic_data_pf->vf + nic_data->vf_index;
 657                         vf->efx = NULL;
 658                 } else
 659                         netif_info(efx, drv, efx->net_dev,
 660                                    "Could not get the PF id from VF\n");
 661         }
 662 #endif
 663
 664         efx_ptp_remove(efx);
 665
 666         efx_mcdi_mon_remove(efx);
 667
 668         efx_ef10_rx_free_indir_table(efx);
 669
 670         if (nic_data->wc_membase)
 671                 iounmap(nic_data->wc_membase);
 672
 673         rc = efx_ef10_free_vis(efx);
 674         WARN_ON(rc != 0);
 675
 676         if (!nic_data->must_restore_piobufs)
 677                 efx_ef10_free_piobufs(efx);
 678
 679         device_remove_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
 680         device_remove_file(&efx->pci_dev->dev, &dev_attr_link_control_flag);
 681
 682         efx_mcdi_fini(efx);
 683         efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
 684         kfree(nic_data);
 685 }
 686
 687 static int efx_ef10_probe_pf(struct efx_nic *efx)
 688 {
 689         return efx_ef10_probe(efx);
 690 }
 691
 692 int efx_ef10_vadaptor_alloc(struct efx_nic *efx, unsigned int port_id)
 693 {
 694         MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_ALLOC_IN_LEN);
 695
 696         MCDI_SET_DWORD(inbuf, VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID, port_id);
 697         return efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_ALLOC, inbuf, sizeof(inbuf),
 698                             NULL, 0, NULL);
 699 }
 700
 701 int efx_ef10_vadaptor_free(struct efx_nic *efx, unsigned int port_id)
 702 {
 703         MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_FREE_IN_LEN);
 704
 705         MCDI_SET_DWORD(inbuf, VADAPTOR_FREE_IN_UPSTREAM_PORT_ID, port_id);
 706         return efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_FREE, inbuf, sizeof(inbuf),
 707                             NULL, 0, NULL);
 708 }
 709
 710 int efx_ef10_vport_add_mac(struct efx_nic *efx,
 711                            unsigned int port_id, u8 *mac)
 712 {
 713         MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_LEN);
 714
 715         MCDI_SET_DWORD(inbuf, VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID, port_id);
 716         ether_addr_copy(MCDI_PTR(inbuf, VPORT_ADD_MAC_ADDRESS_IN_MACADDR), mac);
 717
 718         return efx_mcdi_rpc(efx, MC_CMD_VPORT_ADD_MAC_ADDRESS, inbuf,
 719                             sizeof(inbuf), NULL, 0, NULL);
 720 }
 721
 722 int efx_ef10_vport_del_mac(struct efx_nic *efx,
 723                            unsigned int port_id, u8 *mac)
 724 {
 725         MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_LEN);
 726
 727         MCDI_SET_DWORD(inbuf, VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID, port_id);
 728         ether_addr_copy(MCDI_PTR(inbuf, VPORT_DEL_MAC_ADDRESS_IN_MACADDR), mac);
 729
 730         return efx_mcdi_rpc(efx, MC_CMD_VPORT_DEL_MAC_ADDRESS, inbuf,
 731                             sizeof(inbuf), NULL, 0, NULL);
 732 }
 733
 734 #ifdef CONFIG_SFC_SRIOV
 735 static int efx_ef10_probe_vf(struct efx_nic *efx)
 736 {
 737         int rc;
 738         struct pci_dev *pci_dev_pf;
 739
 740         /* If the parent PF has no VF data structure, it doesn't know about this
 741          * VF so fail probe.  The VF needs to be re-created.  This can happen
 742          * if the PF driver is unloaded while the VF is assigned to a guest.
 743          */
 744         pci_dev_pf = efx->pci_dev->physfn;
 745         if (pci_dev_pf) {
 746                 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
 747                 struct efx_ef10_nic_data *nic_data_pf = efx_pf->nic_data;
 748
 749                 if (!nic_data_pf->vf) {
 750                         netif_info(efx, drv, efx->net_dev,
 751                                    "The VF cannot link to its parent PF; "
 752                                    "please destroy and re-create the VF\n");
 753                         return -EBUSY;
 754                 }
 755         }
 756
 757         rc = efx_ef10_probe(efx);
 758         if (rc)
 759                 return rc;
 760
 761         rc = efx_ef10_get_vf_index(efx);
 762         if (rc)
 763                 goto fail;
 764
 765         if (efx->pci_dev->is_virtfn) {
 766                 if (efx->pci_dev->physfn) {
 767                         struct efx_nic *efx_pf =
 768                                 pci_get_drvdata(efx->pci_dev->physfn);
 769                         struct efx_ef10_nic_data *nic_data_p = efx_pf->nic_data;
 770                         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 771
 772                         nic_data_p->vf[nic_data->vf_index].efx = efx;
 773                         nic_data_p->vf[nic_data->vf_index].pci_dev =
 774                                 efx->pci_dev;
 775                 } else
 776                         netif_info(efx, drv, efx->net_dev,
 777                                    "Could not get the PF id from VF\n");
 778         }
 779
 780         return 0;
 781
 782 fail:
 783         efx_ef10_remove(efx);
 784         return rc;
 785 }
 786 #else
 787 static int efx_ef10_probe_vf(struct efx_nic *efx __attribute__ ((unused)))
 788 {
 789         return 0;
 790 }
 791 #endif
 792
 793 static int efx_ef10_alloc_vis(struct efx_nic *efx,
 794                               unsigned int min_vis, unsigned int max_vis)
 795 {
 796         MCDI_DECLARE_BUF(inbuf, MC_CMD_ALLOC_VIS_IN_LEN);
 797         MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_VIS_OUT_LEN);
 798         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 799         size_t outlen;
 800         int rc;
 801
 802         MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MIN_VI_COUNT, min_vis);
 803         MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MAX_VI_COUNT, max_vis);
 804         rc = efx_mcdi_rpc(efx, MC_CMD_ALLOC_VIS, inbuf, sizeof(inbuf),
 805                           outbuf, sizeof(outbuf), &outlen);
 806         if (rc != 0)
 807                 return rc;
 808
 809         if (outlen < MC_CMD_ALLOC_VIS_OUT_LEN)
 810                 return -EIO;
 811
 812         netif_dbg(efx, drv, efx->net_dev, "base VI is A0x%03x\n",
 813                   MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE));
 814
 815         nic_data->vi_base = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE);
 816         nic_data->n_allocated_vis = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_COUNT);
 817         return 0;
 818 }
 819
 820 /* Note that the failure path of this function does not free
 821  * resources, as this will be done by efx_ef10_remove().
 822  */
 823 static int efx_ef10_dimension_resources(struct efx_nic *efx)
 824 {
 825         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 826         unsigned int uc_mem_map_size, wc_mem_map_size;
 827         unsigned int min_vis = max(EFX_TXQ_TYPES,
 828                                    efx_separate_tx_channels ? 2 : 1);
 829         unsigned int channel_vis, pio_write_vi_base, max_vis;
 830         void __iomem *membase;
 831         int rc;
 832
 833         channel_vis = max(efx->n_channels, efx->n_tx_channels * EFX_TXQ_TYPES);
 834
 835 #ifdef EFX_USE_PIO
 836         /* Try to allocate PIO buffers if wanted and if the full
 837          * number of PIO buffers would be sufficient to allocate one
 838          * copy-buffer per TX channel.  Failure is non-fatal, as there
 839          * are only a small number of PIO buffers shared between all
 840          * functions of the controller.
 841          */
 842         if (efx_piobuf_size != 0 &&
 843             ER_DZ_TX_PIOBUF_SIZE / efx_piobuf_size * EF10_TX_PIOBUF_COUNT >=
 844             efx->n_tx_channels) {
 845                 unsigned int n_piobufs =
 846                         DIV_ROUND_UP(efx->n_tx_channels,
 847                                      ER_DZ_TX_PIOBUF_SIZE / efx_piobuf_size);
 848
 849                 rc = efx_ef10_alloc_piobufs(efx, n_piobufs);
 850                 if (rc)
 851                         netif_err(efx, probe, efx->net_dev,
 852                                   "failed to allocate PIO buffers (%d)\n", rc);
 853                 else
 854                         netif_dbg(efx, probe, efx->net_dev,
 855                                   "allocated %u PIO buffers\n", n_piobufs);
 856         }
 857 #else
 858         nic_data->n_piobufs = 0;
 859 #endif
 860
 861         /* PIO buffers should be mapped with write-combining enabled,
 862          * and we want to make single UC and WC mappings rather than
 863          * several of each (in fact that's the only option if host
 864          * page size is >4K).  So we may allocate some extra VIs just
 865          * for writing PIO buffers through.
 866          *
 867          * The UC mapping contains (channel_vis - 1) complete VIs and the
 868          * first half of the next VI.  Then the WC mapping begins with
 869          * the second half of this last VI.
 870          */
 871         uc_mem_map_size = PAGE_ALIGN((channel_vis - 1) * EFX_VI_PAGE_SIZE +
 872                                      ER_DZ_TX_PIOBUF);
 873         if (nic_data->n_piobufs) {
 874                 /* pio_write_vi_base rounds down to give the number of complete
 875                  * VIs inside the UC mapping.
 876                  */
 877                 pio_write_vi_base = uc_mem_map_size / EFX_VI_PAGE_SIZE;
 878                 wc_mem_map_size = (PAGE_ALIGN((pio_write_vi_base +
 879                                                nic_data->n_piobufs) *
 880                                               EFX_VI_PAGE_SIZE) -
 881                                    uc_mem_map_size);
 882                 max_vis = pio_write_vi_base + nic_data->n_piobufs;
 883         } else {
 884                 pio_write_vi_base = 0;
 885                 wc_mem_map_size = 0;
 886                 max_vis = channel_vis;
 887         }
 888
 889         /* In case the last attached driver failed to free VIs, do it now */
 890         rc = efx_ef10_free_vis(efx);
 891         if (rc != 0)
 892                 return rc;
 893
 894         rc = efx_ef10_alloc_vis(efx, min_vis, max_vis);
 895         if (rc != 0)
 896                 return rc;
 897
 898         if (nic_data->n_allocated_vis < channel_vis) {
 899                 netif_info(efx, drv, efx->net_dev,
 900                            "Could not allocate enough VIs to satisfy RSS"
 901                            " requirements. Performance may not be optimal.\n");
 902                 /* We didn't get the VIs to populate our channels.
 903                  * We could keep what we got but then we'd have more
 904                  * interrupts than we need.
 905                  * Instead calculate new max_channels and restart
 906                  */
 907                 efx->max_channels = nic_data->n_allocated_vis;
 908                 efx->max_tx_channels =
 909                         nic_data->n_allocated_vis / EFX_TXQ_TYPES;
 910
 911                 efx_ef10_free_vis(efx);
 912                 return -EAGAIN;
 913         }
 914
 915         /* If we didn't get enough VIs to map all the PIO buffers, free the
 916          * PIO buffers
 917          */
 918         if (nic_data->n_piobufs &&
 919             nic_data->n_allocated_vis <
 920             pio_write_vi_base + nic_data->n_piobufs) {
 921                 netif_dbg(efx, probe, efx->net_dev,
 922                           "%u VIs are not sufficient to map %u PIO buffers\n",
 923                           nic_data->n_allocated_vis, nic_data->n_piobufs);
 924                 efx_ef10_free_piobufs(efx);
 925         }
 926
 927         /* Shrink the original UC mapping of the memory BAR */
 928         membase = ioremap_nocache(efx->membase_phys, uc_mem_map_size);
 929         if (!membase) {
 930                 netif_err(efx, probe, efx->net_dev,
 931                           "could not shrink memory BAR to %x\n",
 932                           uc_mem_map_size);
 933                 return -ENOMEM;
 934         }
 935         iounmap(efx->membase);
 936         efx->membase = membase;
 937
 938         /* Set up the WC mapping if needed */
 939         if (wc_mem_map_size) {
 940                 nic_data->wc_membase = ioremap_wc(efx->membase_phys +
 941                                                   uc_mem_map_size,
 942                                                   wc_mem_map_size);
 943                 if (!nic_data->wc_membase) {
 944                         netif_err(efx, probe, efx->net_dev,
 945                                   "could not allocate WC mapping of size %x\n",
 946                                   wc_mem_map_size);
 947                         return -ENOMEM;
 948                 }
 949                 nic_data->pio_write_vi_base = pio_write_vi_base;
 950                 nic_data->pio_write_base =
 951                         nic_data->wc_membase +
 952                         (pio_write_vi_base * EFX_VI_PAGE_SIZE + ER_DZ_TX_PIOBUF -
 953                          uc_mem_map_size);
 954
 955                 rc = efx_ef10_link_piobufs(efx);
 956                 if (rc)
 957                         efx_ef10_free_piobufs(efx);
 958         }
 959
 960         netif_dbg(efx, probe, efx->net_dev,
 961                   "memory BAR at %pa (virtual %p+%x UC, %p+%x WC)\n",
 962                   &efx->membase_phys, efx->membase, uc_mem_map_size,
 963                   nic_data->wc_membase, wc_mem_map_size);
 964
 965         return 0;
 966 }
 967
 968 static int efx_ef10_init_nic(struct efx_nic *efx)
 969 {
 970         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 971         int rc;
 972
 973         if (nic_data->must_check_datapath_caps) {
 974                 rc = efx_ef10_init_datapath_caps(efx);
 975                 if (rc)
 976                         return rc;
 977                 nic_data->must_check_datapath_caps = false;
 978         }
 979
 980         if (nic_data->must_realloc_vis) {
 981                 /* We cannot let the number of VIs change now */
 982                 rc = efx_ef10_alloc_vis(efx, nic_data->n_allocated_vis,
 983                                         nic_data->n_allocated_vis);
 984                 if (rc)
 985                         return rc;
 986                 nic_data->must_realloc_vis = false;
 987         }
 988
 989         if (nic_data->must_restore_piobufs && nic_data->n_piobufs) {
 990                 rc = efx_ef10_alloc_piobufs(efx, nic_data->n_piobufs);
 991                 if (rc == 0) {
 992                         rc = efx_ef10_link_piobufs(efx);
 993                         if (rc)
 994                                 efx_ef10_free_piobufs(efx);
 995                 }
 996
 997                 /* Log an error on failure, but this is non-fatal */
 998                 if (rc)
 999                         netif_err(efx, drv, efx->net_dev,
1000                                   "failed to restore PIO buffers (%d)\n", rc);
1001                 nic_data->must_restore_piobufs = false;
1002         }
1003
1004         /* don't fail init if RSS setup doesn't work */
1005         efx->type->rx_push_rss_config(efx, false, efx->rx_indir_table);
1006
1007         return 0;
1008 }
1009
1010 static void efx_ef10_reset_mc_allocations(struct efx_nic *efx)
1011 {
1012         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1013 #ifdef CONFIG_SFC_SRIOV
1014         unsigned int i;
1015 #endif
1016
1017         /* All our allocations have been reset */
1018         nic_data->must_realloc_vis = true;
1019         nic_data->must_restore_filters = true;
1020         nic_data->must_restore_piobufs = true;
1021         nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
1022
1023         /* Driver-created vswitches and vports must be re-created */
1024         nic_data->must_probe_vswitching = true;
1025         nic_data->vport_id = EVB_PORT_ID_ASSIGNED;
1026 #ifdef CONFIG_SFC_SRIOV
1027         if (nic_data->vf)
1028                 for (i = 0; i < efx->vf_count; i++)
1029                         nic_data->vf[i].vport_id = 0;
1030 #endif
1031 }
1032
1033 static enum reset_type efx_ef10_map_reset_reason(enum reset_type reason)
1034 {
1035         if (reason == RESET_TYPE_MC_FAILURE)
1036                 return RESET_TYPE_DATAPATH;
1037
1038         return efx_mcdi_map_reset_reason(reason);
1039 }
1040
1041 static int efx_ef10_map_reset_flags(u32 *flags)
1042 {
1043         enum {
1044                 EF10_RESET_PORT = ((ETH_RESET_MAC | ETH_RESET_PHY) <<
1045                                    ETH_RESET_SHARED_SHIFT),
1046                 EF10_RESET_MC = ((ETH_RESET_DMA | ETH_RESET_FILTER |
1047                                   ETH_RESET_OFFLOAD | ETH_RESET_MAC |
1048                                   ETH_RESET_PHY | ETH_RESET_MGMT) <<
1049                                  ETH_RESET_SHARED_SHIFT)
1050         };
1051
1052         /* We assume for now that our PCI function is permitted to
1053          * reset everything.
1054          */
1055
1056         if ((*flags & EF10_RESET_MC) == EF10_RESET_MC) {
1057                 *flags &= ~EF10_RESET_MC;
1058                 return RESET_TYPE_WORLD;
1059         }
1060
1061         if ((*flags & EF10_RESET_PORT) == EF10_RESET_PORT) {
1062                 *flags &= ~EF10_RESET_PORT;
1063                 return RESET_TYPE_ALL;
1064         }
1065
1066         /* no invisible reset implemented */
1067
1068         return -EINVAL;
1069 }
1070
1071 static int efx_ef10_reset(struct efx_nic *efx, enum reset_type reset_type)
1072 {
1073         int rc = efx_mcdi_reset(efx, reset_type);
1074
1075         /* Unprivileged functions return -EPERM, but need to return success
1076          * here so that the datapath is brought back up.
1077          */
1078         if (reset_type == RESET_TYPE_WORLD && rc == -EPERM)
1079                 rc = 0;
1080
1081         /* If it was a port reset, trigger reallocation of MC resources.
1082          * Note that on an MC reset nothing needs to be done now because we'll
1083          * detect the MC reset later and handle it then.
1084          * For an FLR, we never get an MC reset event, but the MC has reset all
1085          * resources assigned to us, so we have to trigger reallocation now.
1086          */
1087         if ((reset_type == RESET_TYPE_ALL ||
1088              reset_type == RESET_TYPE_MCDI_TIMEOUT) && !rc)
1089                 efx_ef10_reset_mc_allocations(efx);
1090         return rc;
1091 }
1092
1093 #define EF10_DMA_STAT(ext_name, mcdi_name)                      \
1094         [EF10_STAT_ ## ext_name] =                              \
1095         { #ext_name, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
1096 #define EF10_DMA_INVIS_STAT(int_name, mcdi_name)                \
1097         [EF10_STAT_ ## int_name] =                              \
1098         { NULL, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
1099 #define EF10_OTHER_STAT(ext_name)                               \
1100         [EF10_STAT_ ## ext_name] = { #ext_name, 0, 0 }
1101 #define GENERIC_SW_STAT(ext_name)                               \
1102         [GENERIC_STAT_ ## ext_name] = { #ext_name, 0, 0 }
1103
1104 static const struct efx_hw_stat_desc efx_ef10_stat_desc[EF10_STAT_COUNT] = {
1105         EF10_DMA_STAT(port_tx_bytes, TX_BYTES),
1106         EF10_DMA_STAT(port_tx_packets, TX_PKTS),
1107         EF10_DMA_STAT(port_tx_pause, TX_PAUSE_PKTS),
1108         EF10_DMA_STAT(port_tx_control, TX_CONTROL_PKTS),
1109         EF10_DMA_STAT(port_tx_unicast, TX_UNICAST_PKTS),
1110         EF10_DMA_STAT(port_tx_multicast, TX_MULTICAST_PKTS),
1111         EF10_DMA_STAT(port_tx_broadcast, TX_BROADCAST_PKTS),
1112         EF10_DMA_STAT(port_tx_lt64, TX_LT64_PKTS),
1113         EF10_DMA_STAT(port_tx_64, TX_64_PKTS),
1114         EF10_DMA_STAT(port_tx_65_to_127, TX_65_TO_127_PKTS),
1115         EF10_DMA_STAT(port_tx_128_to_255, TX_128_TO_255_PKTS),
1116         EF10_DMA_STAT(port_tx_256_to_511, TX_256_TO_511_PKTS),
1117         EF10_DMA_STAT(port_tx_512_to_1023, TX_512_TO_1023_PKTS),
1118         EF10_DMA_STAT(port_tx_1024_to_15xx, TX_1024_TO_15XX_PKTS),
1119         EF10_DMA_STAT(port_tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS),
1120         EF10_DMA_STAT(port_rx_bytes, RX_BYTES),
1121         EF10_DMA_INVIS_STAT(port_rx_bytes_minus_good_bytes, RX_BAD_BYTES),
1122         EF10_OTHER_STAT(port_rx_good_bytes),
1123         EF10_OTHER_STAT(port_rx_bad_bytes),
1124         EF10_DMA_STAT(port_rx_packets, RX_PKTS),
1125         EF10_DMA_STAT(port_rx_good, RX_GOOD_PKTS),
1126         EF10_DMA_STAT(port_rx_bad, RX_BAD_FCS_PKTS),
1127         EF10_DMA_STAT(port_rx_pause, RX_PAUSE_PKTS),
1128         EF10_DMA_STAT(port_rx_control, RX_CONTROL_PKTS),
1129         EF10_DMA_STAT(port_rx_unicast, RX_UNICAST_PKTS),
1130         EF10_DMA_STAT(port_rx_multicast, RX_MULTICAST_PKTS),
1131         EF10_DMA_STAT(port_rx_broadcast, RX_BROADCAST_PKTS),
1132         EF10_DMA_STAT(port_rx_lt64, RX_UNDERSIZE_PKTS),
1133         EF10_DMA_STAT(port_rx_64, RX_64_PKTS),
1134         EF10_DMA_STAT(port_rx_65_to_127, RX_65_TO_127_PKTS),
1135         EF10_DMA_STAT(port_rx_128_to_255, RX_128_TO_255_PKTS),
1136         EF10_DMA_STAT(port_rx_256_to_511, RX_256_TO_511_PKTS),
1137         EF10_DMA_STAT(port_rx_512_to_1023, RX_512_TO_1023_PKTS),
1138         EF10_DMA_STAT(port_rx_1024_to_15xx, RX_1024_TO_15XX_PKTS),
1139         EF10_DMA_STAT(port_rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS),
1140         EF10_DMA_STAT(port_rx_gtjumbo, RX_GTJUMBO_PKTS),
1141         EF10_DMA_STAT(port_rx_bad_gtjumbo, RX_JABBER_PKTS),
1142         EF10_DMA_STAT(port_rx_overflow, RX_OVERFLOW_PKTS),
1143         EF10_DMA_STAT(port_rx_align_error, RX_ALIGN_ERROR_PKTS),
1144         EF10_DMA_STAT(port_rx_length_error, RX_LENGTH_ERROR_PKTS),
1145         EF10_DMA_STAT(port_rx_nodesc_drops, RX_NODESC_DROPS),
1146         GENERIC_SW_STAT(rx_nodesc_trunc),
1147         GENERIC_SW_STAT(rx_noskb_drops),
1148         EF10_DMA_STAT(port_rx_pm_trunc_bb_overflow, PM_TRUNC_BB_OVERFLOW),
1149         EF10_DMA_STAT(port_rx_pm_discard_bb_overflow, PM_DISCARD_BB_OVERFLOW),
1150         EF10_DMA_STAT(port_rx_pm_trunc_vfifo_full, PM_TRUNC_VFIFO_FULL),
1151         EF10_DMA_STAT(port_rx_pm_discard_vfifo_full, PM_DISCARD_VFIFO_FULL),
1152         EF10_DMA_STAT(port_rx_pm_trunc_qbb, PM_TRUNC_QBB),
1153         EF10_DMA_STAT(port_rx_pm_discard_qbb, PM_DISCARD_QBB),
1154         EF10_DMA_STAT(port_rx_pm_discard_mapping, PM_DISCARD_MAPPING),
1155         EF10_DMA_STAT(port_rx_dp_q_disabled_packets, RXDP_Q_DISABLED_PKTS),
1156         EF10_DMA_STAT(port_rx_dp_di_dropped_packets, RXDP_DI_DROPPED_PKTS),
1157         EF10_DMA_STAT(port_rx_dp_streaming_packets, RXDP_STREAMING_PKTS),
1158         EF10_DMA_STAT(port_rx_dp_hlb_fetch, RXDP_HLB_FETCH_CONDITIONS),
1159         EF10_DMA_STAT(port_rx_dp_hlb_wait, RXDP_HLB_WAIT_CONDITIONS),
1160         EF10_DMA_STAT(rx_unicast, VADAPTER_RX_UNICAST_PACKETS),
1161         EF10_DMA_STAT(rx_unicast_bytes, VADAPTER_RX_UNICAST_BYTES),
1162         EF10_DMA_STAT(rx_multicast, VADAPTER_RX_MULTICAST_PACKETS),
1163         EF10_DMA_STAT(rx_multicast_bytes, VADAPTER_RX_MULTICAST_BYTES),
1164         EF10_DMA_STAT(rx_broadcast, VADAPTER_RX_BROADCAST_PACKETS),
1165         EF10_DMA_STAT(rx_broadcast_bytes, VADAPTER_RX_BROADCAST_BYTES),
1166         EF10_DMA_STAT(rx_bad, VADAPTER_RX_BAD_PACKETS),
1167         EF10_DMA_STAT(rx_bad_bytes, VADAPTER_RX_BAD_BYTES),
1168         EF10_DMA_STAT(rx_overflow, VADAPTER_RX_OVERFLOW),
1169         EF10_DMA_STAT(tx_unicast, VADAPTER_TX_UNICAST_PACKETS),
1170         EF10_DMA_STAT(tx_unicast_bytes, VADAPTER_TX_UNICAST_BYTES),
1171         EF10_DMA_STAT(tx_multicast, VADAPTER_TX_MULTICAST_PACKETS),
1172         EF10_DMA_STAT(tx_multicast_bytes, VADAPTER_TX_MULTICAST_BYTES),
1173         EF10_DMA_STAT(tx_broadcast, VADAPTER_TX_BROADCAST_PACKETS),
1174         EF10_DMA_STAT(tx_broadcast_bytes, VADAPTER_TX_BROADCAST_BYTES),
1175         EF10_DMA_STAT(tx_bad, VADAPTER_TX_BAD_PACKETS),
1176         EF10_DMA_STAT(tx_bad_bytes, VADAPTER_TX_BAD_BYTES),
1177         EF10_DMA_STAT(tx_overflow, VADAPTER_TX_OVERFLOW),
1178 };
1179
1180 #define HUNT_COMMON_STAT_MASK ((1ULL << EF10_STAT_port_tx_bytes) |      \
1181                                (1ULL << EF10_STAT_port_tx_packets) |    \
1182                                (1ULL << EF10_STAT_port_tx_pause) |      \
1183                                (1ULL << EF10_STAT_port_tx_unicast) |    \
1184                                (1ULL << EF10_STAT_port_tx_multicast) |  \
1185                                (1ULL << EF10_STAT_port_tx_broadcast) |  \
1186                                (1ULL << EF10_STAT_port_rx_bytes) |      \
1187                                (1ULL <<                                 \
1188                                 EF10_STAT_port_rx_bytes_minus_good_bytes) | \
1189                                (1ULL << EF10_STAT_port_rx_good_bytes) | \
1190                                (1ULL << EF10_STAT_port_rx_bad_bytes) |  \
1191                                (1ULL << EF10_STAT_port_rx_packets) |    \
1192                                (1ULL << EF10_STAT_port_rx_good) |       \
1193                                (1ULL << EF10_STAT_port_rx_bad) |        \
1194                                (1ULL << EF10_STAT_port_rx_pause) |      \
1195                                (1ULL << EF10_STAT_port_rx_control) |    \
1196                                (1ULL << EF10_STAT_port_rx_unicast) |    \
1197                                (1ULL << EF10_STAT_port_rx_multicast) |  \
1198                                (1ULL << EF10_STAT_port_rx_broadcast) |  \
1199                                (1ULL << EF10_STAT_port_rx_lt64) |       \
1200                                (1ULL << EF10_STAT_port_rx_64) |         \
1201                                (1ULL << EF10_STAT_port_rx_65_to_127) |  \
1202                                (1ULL << EF10_STAT_port_rx_128_to_255) | \
1203                                (1ULL << EF10_STAT_port_rx_256_to_511) | \
1204                                (1ULL << EF10_STAT_port_rx_512_to_1023) |\
1205                                (1ULL << EF10_STAT_port_rx_1024_to_15xx) |\
1206                                (1ULL << EF10_STAT_port_rx_15xx_to_jumbo) |\
1207                                (1ULL << EF10_STAT_port_rx_gtjumbo) |    \
1208                                (1ULL << EF10_STAT_port_rx_bad_gtjumbo) |\
1209                                (1ULL << EF10_STAT_port_rx_overflow) |   \
1210                                (1ULL << EF10_STAT_port_rx_nodesc_drops) |\
1211                                (1ULL << GENERIC_STAT_rx_nodesc_trunc) | \
1212                                (1ULL << GENERIC_STAT_rx_noskb_drops))
1213
1214 /* These statistics are only provided by the 10G MAC.  For a 10G/40G
1215  * switchable port we do not expose these because they might not
1216  * include all the packets they should.
1217  */
1218 #define HUNT_10G_ONLY_STAT_MASK ((1ULL << EF10_STAT_port_tx_control) |  \
1219                                  (1ULL << EF10_STAT_port_tx_lt64) |     \
1220                                  (1ULL << EF10_STAT_port_tx_64) |       \
1221                                  (1ULL << EF10_STAT_port_tx_65_to_127) |\
1222                                  (1ULL << EF10_STAT_port_tx_128_to_255) |\
1223                                  (1ULL << EF10_STAT_port_tx_256_to_511) |\
1224                                  (1ULL << EF10_STAT_port_tx_512_to_1023) |\
1225                                  (1ULL << EF10_STAT_port_tx_1024_to_15xx) |\
1226                                  (1ULL << EF10_STAT_port_tx_15xx_to_jumbo))
1227
1228 /* These statistics are only provided by the 40G MAC.  For a 10G/40G
1229  * switchable port we do expose these because the errors will otherwise
1230  * be silent.
1231  */
1232 #define HUNT_40G_EXTRA_STAT_MASK ((1ULL << EF10_STAT_port_rx_align_error) |\
1233                                   (1ULL << EF10_STAT_port_rx_length_error))
1234
1235 /* These statistics are only provided if the firmware supports the
1236  * capability PM_AND_RXDP_COUNTERS.
1237  */
1238 #define HUNT_PM_AND_RXDP_STAT_MASK (                                    \
1239         (1ULL << EF10_STAT_port_rx_pm_trunc_bb_overflow) |              \
1240         (1ULL << EF10_STAT_port_rx_pm_discard_bb_overflow) |            \
1241         (1ULL << EF10_STAT_port_rx_pm_trunc_vfifo_full) |               \
1242         (1ULL << EF10_STAT_port_rx_pm_discard_vfifo_full) |             \
1243         (1ULL << EF10_STAT_port_rx_pm_trunc_qbb) |                      \
1244         (1ULL << EF10_STAT_port_rx_pm_discard_qbb) |                    \
1245         (1ULL << EF10_STAT_port_rx_pm_discard_mapping) |                \
1246         (1ULL << EF10_STAT_port_rx_dp_q_disabled_packets) |             \
1247         (1ULL << EF10_STAT_port_rx_dp_di_dropped_packets) |             \
1248         (1ULL << EF10_STAT_port_rx_dp_streaming_packets) |              \
1249         (1ULL << EF10_STAT_port_rx_dp_hlb_fetch) |                      \
1250         (1ULL << EF10_STAT_port_rx_dp_hlb_wait))
1251
1252 static u64 efx_ef10_raw_stat_mask(struct efx_nic *efx)
1253 {
1254         u64 raw_mask = HUNT_COMMON_STAT_MASK;
1255         u32 port_caps = efx_mcdi_phy_get_caps(efx);
1256         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1257
1258         if (!(efx->mcdi->fn_flags &
1259               1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL))
1260                 return 0;
1261
1262         if (port_caps & (1 << MC_CMD_PHY_CAP_40000FDX_LBN))
1263                 raw_mask |= HUNT_40G_EXTRA_STAT_MASK;
1264         else
1265                 raw_mask |= HUNT_10G_ONLY_STAT_MASK;
1266
1267         if (nic_data->datapath_caps &
1268             (1 << MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_LBN))
1269                 raw_mask |= HUNT_PM_AND_RXDP_STAT_MASK;
1270
1271         return raw_mask;
1272 }
1273
1274 static void efx_ef10_get_stat_mask(struct efx_nic *efx, unsigned long *mask)
1275 {
1276         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1277         u64 raw_mask[2];
1278
1279         raw_mask[0] = efx_ef10_raw_stat_mask(efx);
1280
1281         /* Only show vadaptor stats when EVB capability is present */
1282         if (nic_data->datapath_caps &
1283             (1 << MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN)) {
1284                 raw_mask[0] |= ~((1ULL << EF10_STAT_rx_unicast) - 1);
1285                 raw_mask[1] = (1ULL << (EF10_STAT_COUNT - 63)) - 1;
1286         } else {
1287                 raw_mask[1] = 0;
1288         }
1289
1290 #if BITS_PER_LONG == 64
1291         mask[0] = raw_mask[0];
1292         mask[1] = raw_mask[1];
1293 #else
1294         mask[0] = raw_mask[0] & 0xffffffff;
1295         mask[1] = raw_mask[0] >> 32;
1296         mask[2] = raw_mask[1] & 0xffffffff;
1297         mask[3] = raw_mask[1] >> 32;
1298 #endif
1299 }
1300
1301 static size_t efx_ef10_describe_stats(struct efx_nic *efx, u8 *names)
1302 {
1303         DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1304
1305         efx_ef10_get_stat_mask(efx, mask);
1306         return efx_nic_describe_stats(efx_ef10_stat_desc, EF10_STAT_COUNT,
1307                                       mask, names);
1308 }
1309
1310 static size_t efx_ef10_update_stats_common(struct efx_nic *efx, u64 *full_stats,
1311                                            struct rtnl_link_stats64 *core_stats)
1312 {
1313         DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1314         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1315         u64 *stats = nic_data->stats;
1316         size_t stats_count = 0, index;
1317
1318         efx_ef10_get_stat_mask(efx, mask);
1319
1320         if (full_stats) {
1321                 for_each_set_bit(index, mask, EF10_STAT_COUNT) {
1322                         if (efx_ef10_stat_desc[index].name) {
1323                                 *full_stats++ = stats[index];
1324                                 ++stats_count;
1325                         }
1326                 }
1327         }
1328
1329         if (!core_stats)
1330                 return stats_count;
1331
1332         if (nic_data->datapath_caps &
1333                         1 << MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN) {
1334                 /* Use vadaptor stats. */
1335                 core_stats->rx_packets = stats[EF10_STAT_rx_unicast] +
1336                                          stats[EF10_STAT_rx_multicast] +
1337                                          stats[EF10_STAT_rx_broadcast];
1338                 core_stats->tx_packets = stats[EF10_STAT_tx_unicast] +
1339                                          stats[EF10_STAT_tx_multicast] +
1340                                          stats[EF10_STAT_tx_broadcast];
1341                 core_stats->rx_bytes = stats[EF10_STAT_rx_unicast_bytes] +
1342                                        stats[EF10_STAT_rx_multicast_bytes] +
1343                                        stats[EF10_STAT_rx_broadcast_bytes];
1344                 core_stats->tx_bytes = stats[EF10_STAT_tx_unicast_bytes] +
1345                                        stats[EF10_STAT_tx_multicast_bytes] +
1346                                        stats[EF10_STAT_tx_broadcast_bytes];
1347                 core_stats->rx_dropped = stats[GENERIC_STAT_rx_nodesc_trunc] +
1348                                          stats[GENERIC_STAT_rx_noskb_drops];
1349                 core_stats->multicast = stats[EF10_STAT_rx_multicast];
1350                 core_stats->rx_crc_errors = stats[EF10_STAT_rx_bad];
1351                 core_stats->rx_fifo_errors = stats[EF10_STAT_rx_overflow];
1352                 core_stats->rx_errors = core_stats->rx_crc_errors;
1353                 core_stats->tx_errors = stats[EF10_STAT_tx_bad];
1354         } else {
1355                 /* Use port stats. */
1356                 core_stats->rx_packets = stats[EF10_STAT_port_rx_packets];
1357                 core_stats->tx_packets = stats[EF10_STAT_port_tx_packets];
1358                 core_stats->rx_bytes = stats[EF10_STAT_port_rx_bytes];
1359                 core_stats->tx_bytes = stats[EF10_STAT_port_tx_bytes];
1360                 core_stats->rx_dropped = stats[EF10_STAT_port_rx_nodesc_drops] +
1361                                          stats[GENERIC_STAT_rx_nodesc_trunc] +
1362                                          stats[GENERIC_STAT_rx_noskb_drops];
1363                 core_stats->multicast = stats[EF10_STAT_port_rx_multicast];
1364                 core_stats->rx_length_errors =
1365                                 stats[EF10_STAT_port_rx_gtjumbo] +
1366                                 stats[EF10_STAT_port_rx_length_error];
1367                 core_stats->rx_crc_errors = stats[EF10_STAT_port_rx_bad];
1368                 core_stats->rx_frame_errors =
1369                                 stats[EF10_STAT_port_rx_align_error];
1370                 core_stats->rx_fifo_errors = stats[EF10_STAT_port_rx_overflow];
1371                 core_stats->rx_errors = (core_stats->rx_length_errors +
1372                                          core_stats->rx_crc_errors +
1373                                          core_stats->rx_frame_errors);
1374         }
1375
1376         return stats_count;
1377 }
1378
1379 static int efx_ef10_try_update_nic_stats_pf(struct efx_nic *efx)
1380 {
1381         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1382         DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1383         __le64 generation_start, generation_end;
1384         u64 *stats = nic_data->stats;
1385         __le64 *dma_stats;
1386
1387         efx_ef10_get_stat_mask(efx, mask);
1388
1389         dma_stats = efx->stats_buffer.addr;
1390         nic_data = efx->nic_data;
1391
1392         generation_end = dma_stats[MC_CMD_MAC_GENERATION_END];
1393         if (generation_end == EFX_MC_STATS_GENERATION_INVALID)
1394                 return 0;
1395         rmb();
1396         efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask,
1397                              stats, efx->stats_buffer.addr, false);
1398         rmb();
1399         generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
1400         if (generation_end != generation_start)
1401                 return -EAGAIN;
1402
1403         /* Update derived statistics */
1404         efx_nic_fix_nodesc_drop_stat(efx,
1405                                      &stats[EF10_STAT_port_rx_nodesc_drops]);
1406         stats[EF10_STAT_port_rx_good_bytes] =
1407                 stats[EF10_STAT_port_rx_bytes] -
1408                 stats[EF10_STAT_port_rx_bytes_minus_good_bytes];
1409         efx_update_diff_stat(&stats[EF10_STAT_port_rx_bad_bytes],
1410                              stats[EF10_STAT_port_rx_bytes_minus_good_bytes]);
1411         efx_update_sw_stats(efx, stats);
1412         return 0;
1413 }
1414
1415
1416 static size_t efx_ef10_update_stats_pf(struct efx_nic *efx, u64 *full_stats,
1417                                        struct rtnl_link_stats64 *core_stats)
1418 {
1419         int retry;
1420
1421         /* If we're unlucky enough to read statistics during the DMA, wait
1422          * up to 10ms for it to finish (typically takes <500us)
1423          */
1424         for (retry = 0; retry < 100; ++retry) {
1425                 if (efx_ef10_try_update_nic_stats_pf(efx) == 0)
1426                         break;
1427                 udelay(100);
1428         }
1429
1430         return efx_ef10_update_stats_common(efx, full_stats, core_stats);
1431 }
1432
1433 static int efx_ef10_try_update_nic_stats_vf(struct efx_nic *efx)
1434 {
1435         MCDI_DECLARE_BUF(inbuf, MC_CMD_MAC_STATS_IN_LEN);
1436         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1437         DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1438         __le64 generation_start, generation_end;
1439         u64 *stats = nic_data->stats;
1440         u32 dma_len = MC_CMD_MAC_NSTATS * sizeof(u64);
1441         struct efx_buffer stats_buf;
1442         __le64 *dma_stats;
1443         int rc;
1444
1445         spin_unlock_bh(&efx->stats_lock);
1446
1447         if (in_interrupt()) {
1448                 /* If in atomic context, cannot update stats.  Just update the
1449                  * software stats and return so the caller can continue.
1450                  */
1451                 spin_lock_bh(&efx->stats_lock);
1452                 efx_update_sw_stats(efx, stats);
1453                 return 0;
1454         }
1455
1456         efx_ef10_get_stat_mask(efx, mask);
1457
1458         rc = efx_nic_alloc_buffer(efx, &stats_buf, dma_len, GFP_ATOMIC);
1459         if (rc) {
1460                 spin_lock_bh(&efx->stats_lock);
1461                 return rc;
1462         }
1463
1464         dma_stats = stats_buf.addr;
1465         dma_stats[MC_CMD_MAC_GENERATION_END] = EFX_MC_STATS_GENERATION_INVALID;
1466
1467         MCDI_SET_QWORD(inbuf, MAC_STATS_IN_DMA_ADDR, stats_buf.dma_addr);
1468         MCDI_POPULATE_DWORD_1(inbuf, MAC_STATS_IN_CMD,
1469                               MAC_STATS_IN_DMA, 1);
1470         MCDI_SET_DWORD(inbuf, MAC_STATS_IN_DMA_LEN, dma_len);
1471         MCDI_SET_DWORD(inbuf, MAC_STATS_IN_PORT_ID, EVB_PORT_ID_ASSIGNED);
1472
1473         rc = efx_mcdi_rpc_quiet(efx, MC_CMD_MAC_STATS, inbuf, sizeof(inbuf),
1474                                 NULL, 0, NULL);
1475         spin_lock_bh(&efx->stats_lock);
1476         if (rc) {
1477                 /* Expect ENOENT if DMA queues have not been set up */
1478                 if (rc != -ENOENT || atomic_read(&efx->active_queues))
1479                         efx_mcdi_display_error(efx, MC_CMD_MAC_STATS,
1480                                                sizeof(inbuf), NULL, 0, rc);
1481                 goto out;
1482         }
1483
1484         generation_end = dma_stats[MC_CMD_MAC_GENERATION_END];
1485         if (generation_end == EFX_MC_STATS_GENERATION_INVALID) {
1486                 WARN_ON_ONCE(1);
1487                 goto out;
1488         }
1489         rmb();
1490         efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask,
1491                              stats, stats_buf.addr, false);
1492         rmb();
1493         generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
1494         if (generation_end != generation_start) {
1495                 rc = -EAGAIN;
1496                 goto out;
1497         }
1498
1499         efx_update_sw_stats(efx, stats);
1500 out:
1501         efx_nic_free_buffer(efx, &stats_buf);
1502         return rc;
1503 }
1504
1505 static size_t efx_ef10_update_stats_vf(struct efx_nic *efx, u64 *full_stats,
1506                                        struct rtnl_link_stats64 *core_stats)
1507 {
1508         if (efx_ef10_try_update_nic_stats_vf(efx))
1509                 return 0;
1510
1511         return efx_ef10_update_stats_common(efx, full_stats, core_stats);
1512 }
1513
1514 static void efx_ef10_push_irq_moderation(struct efx_channel *channel)
1515 {
1516         struct efx_nic *efx = channel->efx;
1517         unsigned int mode, value;
1518         efx_dword_t timer_cmd;
1519
1520         if (channel->irq_moderation) {
1521                 mode = 3;
1522                 value = channel->irq_moderation - 1;
1523         } else {
1524                 mode = 0;
1525                 value = 0;
1526         }
1527
1528         if (EFX_EF10_WORKAROUND_35388(efx)) {
1529                 EFX_POPULATE_DWORD_3(timer_cmd, ERF_DD_EVQ_IND_TIMER_FLAGS,
1530                                      EFE_DD_EVQ_IND_TIMER_FLAGS,
1531                                      ERF_DD_EVQ_IND_TIMER_MODE, mode,
1532                                      ERF_DD_EVQ_IND_TIMER_VAL, value);
1533                 efx_writed_page(efx, &timer_cmd, ER_DD_EVQ_INDIRECT,
1534                                 channel->channel);
1535         } else {
1536                 EFX_POPULATE_DWORD_2(timer_cmd, ERF_DZ_TC_TIMER_MODE, mode,
1537                                      ERF_DZ_TC_TIMER_VAL, value);
1538                 efx_writed_page(efx, &timer_cmd, ER_DZ_EVQ_TMR,
1539                                 channel->channel);
1540         }
1541 }
1542
1543 static void efx_ef10_get_wol_vf(struct efx_nic *efx,
1544                                 struct ethtool_wolinfo *wol) {}
1545
1546 static int efx_ef10_set_wol_vf(struct efx_nic *efx, u32 type)
1547 {
1548         return -EOPNOTSUPP;
1549 }
1550
1551 static void efx_ef10_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol)
1552 {
1553         wol->supported = 0;
1554         wol->wolopts = 0;
1555         memset(&wol->sopass, 0, sizeof(wol->sopass));
1556 }
1557
1558 static int efx_ef10_set_wol(struct efx_nic *efx, u32 type)
1559 {
1560         if (type != 0)
1561                 return -EINVAL;
1562         return 0;
1563 }
1564
1565 static void efx_ef10_mcdi_request(struct efx_nic *efx,
1566                                   const efx_dword_t *hdr, size_t hdr_len,
1567                                   const efx_dword_t *sdu, size_t sdu_len)
1568 {
1569         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1570         u8 *pdu = nic_data->mcdi_buf.addr;
1571
1572         memcpy(pdu, hdr, hdr_len);
1573         memcpy(pdu + hdr_len, sdu, sdu_len);
1574         wmb();
1575
1576         /* The hardware provides 'low' and 'high' (doorbell) registers
1577          * for passing the 64-bit address of an MCDI request to
1578          * firmware.  However the dwords are swapped by firmware.  The
1579          * least significant bits of the doorbell are then 0 for all
1580          * MCDI requests due to alignment.
1581          */
1582         _efx_writed(efx, cpu_to_le32((u64)nic_data->mcdi_buf.dma_addr >> 32),
1583                     ER_DZ_MC_DB_LWRD);
1584         _efx_writed(efx, cpu_to_le32((u32)nic_data->mcdi_buf.dma_addr),
1585                     ER_DZ_MC_DB_HWRD);
1586 }
1587
1588 static bool efx_ef10_mcdi_poll_response(struct efx_nic *efx)
1589 {
1590         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1591         const efx_dword_t hdr = *(const efx_dword_t *)nic_data->mcdi_buf.addr;
1592
1593         rmb();
1594         return EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE);
1595 }
1596
1597 static void
1598 efx_ef10_mcdi_read_response(struct efx_nic *efx, efx_dword_t *outbuf,
1599                             size_t offset, size_t outlen)
1600 {
1601         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1602         const u8 *pdu = nic_data->mcdi_buf.addr;
1603
1604         memcpy(outbuf, pdu + offset, outlen);
1605 }
1606
1607 static void efx_ef10_mcdi_reboot_detected(struct efx_nic *efx)
1608 {
1609         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1610
1611         /* All our allocations have been reset */
1612         efx_ef10_reset_mc_allocations(efx);
1613
1614         /* The datapath firmware might have been changed */
1615         nic_data->must_check_datapath_caps = true;
1616
1617         /* MAC statistics have been cleared on the NIC; clear the local
1618          * statistic that we update with efx_update_diff_stat().
1619          */
1620         nic_data->stats[EF10_STAT_port_rx_bad_bytes] = 0;
1621 }
1622
1623 static int efx_ef10_mcdi_poll_reboot(struct efx_nic *efx)
1624 {
1625         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1626         int rc;
1627
1628         rc = efx_ef10_get_warm_boot_count(efx);
1629         if (rc < 0) {
1630                 /* The firmware is presumably in the process of
1631                  * rebooting.  However, we are supposed to report each
1632                  * reboot just once, so we must only do that once we
1633                  * can read and store the updated warm boot count.
1634                  */
1635                 return 0;
1636         }
1637
1638         if (rc == nic_data->warm_boot_count)
1639                 return 0;
1640
1641         nic_data->warm_boot_count = rc;
1642         efx_ef10_mcdi_reboot_detected(efx);
1643
1644         return -EIO;
1645 }
1646
1647 /* Handle an MSI interrupt
1648  *
1649  * Handle an MSI hardware interrupt.  This routine schedules event
1650  * queue processing.  No interrupt acknowledgement cycle is necessary.
1651  * Also, we never need to check that the interrupt is for us, since
1652  * MSI interrupts cannot be shared.
1653  */
1654 static irqreturn_t efx_ef10_msi_interrupt(int irq, void *dev_id)
1655 {
1656         struct efx_msi_context *context = dev_id;
1657         struct efx_nic *efx = context->efx;
1658
1659         netif_vdbg(efx, intr, efx->net_dev,
1660                    "IRQ %d on CPU %d\n", irq, raw_smp_processor_id());
1661
1662         if (likely(ACCESS_ONCE(efx->irq_soft_enabled))) {
1663                 /* Note test interrupts */
1664                 if (context->index == efx->irq_level)
1665                         efx->last_irq_cpu = raw_smp_processor_id();
1666
1667                 /* Schedule processing of the channel */
1668                 efx_schedule_channel_irq(efx->channel[context->index]);
1669         }
1670
1671         return IRQ_HANDLED;
1672 }
1673
1674 static irqreturn_t efx_ef10_legacy_interrupt(int irq, void *dev_id)
1675 {
1676         struct efx_nic *efx = dev_id;
1677         bool soft_enabled = ACCESS_ONCE(efx->irq_soft_enabled);
1678         struct efx_channel *channel;
1679         efx_dword_t reg;
1680         u32 queues;
1681
1682         /* Read the ISR which also ACKs the interrupts */
1683         efx_readd(efx, &reg, ER_DZ_BIU_INT_ISR);
1684         queues = EFX_DWORD_FIELD(reg, ERF_DZ_ISR_REG);
1685
1686         if (queues == 0)
1687                 return IRQ_NONE;
1688
1689         if (likely(soft_enabled)) {
1690                 /* Note test interrupts */
1691                 if (queues & (1U << efx->irq_level))
1692                         efx->last_irq_cpu = raw_smp_processor_id();
1693
1694                 efx_for_each_channel(channel, efx) {
1695                         if (queues & 1)
1696                                 efx_schedule_channel_irq(channel);
1697                         queues >>= 1;
1698                 }
1699         }
1700
1701         netif_vdbg(efx, intr, efx->net_dev,
1702                    "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n",
1703                    irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg));
1704
1705         return IRQ_HANDLED;
1706 }
1707
1708 static void efx_ef10_irq_test_generate(struct efx_nic *efx)
1709 {
1710         MCDI_DECLARE_BUF(inbuf, MC_CMD_TRIGGER_INTERRUPT_IN_LEN);
1711
1712         BUILD_BUG_ON(MC_CMD_TRIGGER_INTERRUPT_OUT_LEN != 0);
1713
1714         MCDI_SET_DWORD(inbuf, TRIGGER_INTERRUPT_IN_INTR_LEVEL, efx->irq_level);
1715         (void) efx_mcdi_rpc(efx, MC_CMD_TRIGGER_INTERRUPT,
1716                             inbuf, sizeof(inbuf), NULL, 0, NULL);
1717 }
1718
1719 static int efx_ef10_tx_probe(struct efx_tx_queue *tx_queue)
1720 {
1721         return efx_nic_alloc_buffer(tx_queue->efx, &tx_queue->txd.buf,
1722                                     (tx_queue->ptr_mask + 1) *
1723                                     sizeof(efx_qword_t),
1724                                     GFP_KERNEL);
1725 }
1726
1727 /* This writes to the TX_DESC_WPTR and also pushes data */
1728 static inline void efx_ef10_push_tx_desc(struct efx_tx_queue *tx_queue,
1729                                          const efx_qword_t *txd)
1730 {
1731         unsigned int write_ptr;
1732         efx_oword_t reg;
1733
1734         write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
1735         EFX_POPULATE_OWORD_1(reg, ERF_DZ_TX_DESC_WPTR, write_ptr);
1736         reg.qword[0] = *txd;
1737         efx_writeo_page(tx_queue->efx, &reg,
1738                         ER_DZ_TX_DESC_UPD, tx_queue->queue);
1739 }
1740
1741 static void efx_ef10_tx_init(struct efx_tx_queue *tx_queue)
1742 {
1743         MCDI_DECLARE_BUF(inbuf, MC_CMD_INIT_TXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 /
1744                                                        EFX_BUF_SIZE));
1745         bool csum_offload = tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD;
1746         size_t entries = tx_queue->txd.buf.len / EFX_BUF_SIZE;
1747         struct efx_channel *channel = tx_queue->channel;
1748         struct efx_nic *efx = tx_queue->efx;
1749         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1750         size_t inlen;
1751         dma_addr_t dma_addr;
1752         efx_qword_t *txd;
1753         int rc;
1754         int i;
1755         BUILD_BUG_ON(MC_CMD_INIT_TXQ_OUT_LEN != 0);
1756
1757         MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_SIZE, tx_queue->ptr_mask + 1);
1758         MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_TARGET_EVQ, channel->channel);
1759         MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_LABEL, tx_queue->queue);
1760         MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_INSTANCE, tx_queue->queue);
1761         MCDI_POPULATE_DWORD_2(inbuf, INIT_TXQ_IN_FLAGS,
1762                               INIT_TXQ_IN_FLAG_IP_CSUM_DIS, !csum_offload,
1763                               INIT_TXQ_IN_FLAG_TCP_CSUM_DIS, !csum_offload);
1764         MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_OWNER_ID, 0);
1765         MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_PORT_ID, nic_data->vport_id);
1766
1767         dma_addr = tx_queue->txd.buf.dma_addr;
1768
1769         netif_dbg(efx, hw, efx->net_dev, "pushing TXQ %d. %zu entries (%llx)\n",
1770                   tx_queue->queue, entries, (u64)dma_addr);
1771
1772         for (i = 0; i < entries; ++i) {
1773                 MCDI_SET_ARRAY_QWORD(inbuf, INIT_TXQ_IN_DMA_ADDR, i, dma_addr);
1774                 dma_addr += EFX_BUF_SIZE;
1775         }
1776
1777         inlen = MC_CMD_INIT_TXQ_IN_LEN(entries);
1778
1779         rc = efx_mcdi_rpc(efx, MC_CMD_INIT_TXQ, inbuf, inlen,
1780                           NULL, 0, NULL);
1781         if (rc)
1782                 goto fail;
1783
1784         /* A previous user of this TX queue might have set us up the
1785          * bomb by writing a descriptor to the TX push collector but
1786          * not the doorbell.  (Each collector belongs to a port, not a
1787          * queue or function, so cannot easily be reset.)  We must
1788          * attempt to push a no-op descriptor in its place.
1789          */
1790         tx_queue->buffer[0].flags = EFX_TX_BUF_OPTION;
1791         tx_queue->insert_count = 1;
1792         txd = efx_tx_desc(tx_queue, 0);
1793         EFX_POPULATE_QWORD_4(*txd,
1794                              ESF_DZ_TX_DESC_IS_OPT, true,
1795                              ESF_DZ_TX_OPTION_TYPE,
1796                              ESE_DZ_TX_OPTION_DESC_CRC_CSUM,
1797                              ESF_DZ_TX_OPTION_UDP_TCP_CSUM, csum_offload,
1798                              ESF_DZ_TX_OPTION_IP_CSUM, csum_offload);
1799         tx_queue->write_count = 1;
1800         wmb();
1801         efx_ef10_push_tx_desc(tx_queue, txd);
1802
1803         return;
1804
1805 fail:
1806         netdev_WARN(efx->net_dev, "failed to initialise TXQ %d\n",
1807                     tx_queue->queue);
1808 }
1809
1810 static void efx_ef10_tx_fini(struct efx_tx_queue *tx_queue)
1811 {
1812         MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_TXQ_IN_LEN);
1813         MCDI_DECLARE_BUF_ERR(outbuf);
1814         struct efx_nic *efx = tx_queue->efx;
1815         size_t outlen;
1816         int rc;
1817
1818         MCDI_SET_DWORD(inbuf, FINI_TXQ_IN_INSTANCE,
1819                        tx_queue->queue);
1820
1821         rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_TXQ, inbuf, sizeof(inbuf),
1822                           outbuf, sizeof(outbuf), &outlen);
1823
1824         if (rc && rc != -EALREADY)
1825                 goto fail;
1826
1827         return;
1828
1829 fail:
1830         efx_mcdi_display_error(efx, MC_CMD_FINI_TXQ, MC_CMD_FINI_TXQ_IN_LEN,
1831                                outbuf, outlen, rc);
1832 }
1833
1834 static void efx_ef10_tx_remove(struct efx_tx_queue *tx_queue)
1835 {
1836         efx_nic_free_buffer(tx_queue->efx, &tx_queue->txd.buf);
1837 }
1838
1839 /* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
1840 static inline void efx_ef10_notify_tx_desc(struct efx_tx_queue *tx_queue)
1841 {
1842         unsigned int write_ptr;
1843         efx_dword_t reg;
1844
1845         write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
1846         EFX_POPULATE_DWORD_1(reg, ERF_DZ_TX_DESC_WPTR_DWORD, write_ptr);
1847         efx_writed_page(tx_queue->efx, &reg,
1848                         ER_DZ_TX_DESC_UPD_DWORD, tx_queue->queue);
1849 }
1850
1851 static void efx_ef10_tx_write(struct efx_tx_queue *tx_queue)
1852 {
1853         unsigned int old_write_count = tx_queue->write_count;
1854         struct efx_tx_buffer *buffer;
1855         unsigned int write_ptr;
1856         efx_qword_t *txd;
1857
1858         BUG_ON(tx_queue->write_count == tx_queue->insert_count);
1859
1860         do {
1861                 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
1862                 buffer = &tx_queue->buffer[write_ptr];
1863                 txd = efx_tx_desc(tx_queue, write_ptr);
1864                 ++tx_queue->write_count;
1865
1866                 /* Create TX descriptor ring entry */
1867                 if (buffer->flags & EFX_TX_BUF_OPTION) {
1868                         *txd = buffer->option;
1869                 } else {
1870                         BUILD_BUG_ON(EFX_TX_BUF_CONT != 1);
1871                         EFX_POPULATE_QWORD_3(
1872                                 *txd,
1873                                 ESF_DZ_TX_KER_CONT,
1874                                 buffer->flags & EFX_TX_BUF_CONT,
1875                                 ESF_DZ_TX_KER_BYTE_CNT, buffer->len,
1876                                 ESF_DZ_TX_KER_BUF_ADDR, buffer->dma_addr);
1877                 }
1878         } while (tx_queue->write_count != tx_queue->insert_count);
1879
1880         wmb(); /* Ensure descriptors are written before they are fetched */
1881
1882         if (efx_nic_may_push_tx_desc(tx_queue, old_write_count)) {
1883                 txd = efx_tx_desc(tx_queue,
1884                                   old_write_count & tx_queue->ptr_mask);
1885                 efx_ef10_push_tx_desc(tx_queue, txd);
1886                 ++tx_queue->pushes;
1887         } else {
1888                 efx_ef10_notify_tx_desc(tx_queue);
1889         }
1890 }
1891
1892 static int efx_ef10_alloc_rss_context(struct efx_nic *efx, u32 *context,
1893                                       bool exclusive, unsigned *context_size)
1894 {
1895         MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN);
1896         MCDI_DECLARE_BUF(outbuf, MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN);
1897         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1898         size_t outlen;
1899         int rc;
1900         u32 alloc_type = exclusive ?
1901                                 MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE :
1902                                 MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_SHARED;
1903         unsigned rss_spread = exclusive ?
1904                                 efx->rss_spread :
1905                                 min(rounddown_pow_of_two(efx->rss_spread),
1906                                     EFX_EF10_MAX_SHARED_RSS_CONTEXT_SIZE);
1907
1908         if (!exclusive && rss_spread == 1) {
1909                 *context = EFX_EF10_RSS_CONTEXT_INVALID;
1910                 if (context_size)
1911                         *context_size = 1;
1912                 return 0;
1913         }
1914
1915         MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID,
1916                        nic_data->vport_id);
1917         MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_TYPE, alloc_type);
1918         MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_NUM_QUEUES, rss_spread);
1919
1920         rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_ALLOC, inbuf, sizeof(inbuf),
1921                 outbuf, sizeof(outbuf), &outlen);
1922         if (rc != 0)
1923                 return rc;
1924
1925         if (outlen < MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN)
1926                 return -EIO;
1927
1928         *context = MCDI_DWORD(outbuf, RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID);
1929
1930         if (context_size)
1931                 *context_size = rss_spread;
1932
1933         return 0;
1934 }
1935
1936 static void efx_ef10_free_rss_context(struct efx_nic *efx, u32 context)
1937 {
1938         MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_FREE_IN_LEN);
1939         int rc;
1940
1941         MCDI_SET_DWORD(inbuf, RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID,
1942                        context);
1943
1944         rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_FREE, inbuf, sizeof(inbuf),
1945                             NULL, 0, NULL);
1946         WARN_ON(rc != 0);
1947 }
1948
1949 static int efx_ef10_populate_rss_table(struct efx_nic *efx, u32 context,
1950                                        const u32 *rx_indir_table)
1951 {
1952         MCDI_DECLARE_BUF(tablebuf, MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN);
1953         MCDI_DECLARE_BUF(keybuf, MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN);
1954         int i, rc;
1955
1956         MCDI_SET_DWORD(tablebuf, RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID,
1957                        context);
1958         BUILD_BUG_ON(ARRAY_SIZE(efx->rx_indir_table) !=
1959                      MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_LEN);
1960
1961         for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); ++i)
1962                 MCDI_PTR(tablebuf,
1963                          RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE)[i] =
1964                                 (u8) rx_indir_table[i];
1965
1966         rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_TABLE, tablebuf,
1967                           sizeof(tablebuf), NULL, 0, NULL);
1968         if (rc != 0)
1969                 return rc;
1970
1971         MCDI_SET_DWORD(keybuf, RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID,
1972                        context);
1973         BUILD_BUG_ON(ARRAY_SIZE(efx->rx_hash_key) !=
1974                      MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN);
1975         for (i = 0; i < ARRAY_SIZE(efx->rx_hash_key); ++i)
1976                 MCDI_PTR(keybuf, RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY)[i] =
1977                         efx->rx_hash_key[i];
1978
1979         return efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_KEY, keybuf,
1980                             sizeof(keybuf), NULL, 0, NULL);
1981 }
1982
1983 static void efx_ef10_rx_free_indir_table(struct efx_nic *efx)
1984 {
1985         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1986
1987         if (nic_data->rx_rss_context != EFX_EF10_RSS_CONTEXT_INVALID)
1988                 efx_ef10_free_rss_context(efx, nic_data->rx_rss_context);
1989         nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
1990 }
1991
1992 static int efx_ef10_rx_push_shared_rss_config(struct efx_nic *efx,
1993                                               unsigned *context_size)
1994 {
1995         u32 new_rx_rss_context;
1996         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1997         int rc = efx_ef10_alloc_rss_context(efx, &new_rx_rss_context,
1998                                             false, context_size);
1999
2000         if (rc != 0)
2001                 return rc;
2002
2003         nic_data->rx_rss_context = new_rx_rss_context;
2004         nic_data->rx_rss_context_exclusive = false;
2005         efx_set_default_rx_indir_table(efx);
2006         return 0;
2007 }
2008
2009 static int efx_ef10_rx_push_exclusive_rss_config(struct efx_nic *efx,
2010                                                  const u32 *rx_indir_table)
2011 {
2012         struct efx_ef10_nic_data *nic_data = efx->nic_data;
2013         int rc;
2014         u32 new_rx_rss_context;
2015
2016         if (nic_data->rx_rss_context == EFX_EF10_RSS_CONTEXT_INVALID ||
2017             !nic_data->rx_rss_context_exclusive) {
2018                 rc = efx_ef10_alloc_rss_context(efx, &new_rx_rss_context,
2019                                                 true, NULL);
2020                 if (rc == -EOPNOTSUPP)
2021                         return rc;
2022                 else if (rc != 0)
2023                         goto fail1;
2024         } else {
2025                 new_rx_rss_context = nic_data->rx_rss_context;
2026         }
2027
2028         rc = efx_ef10_populate_rss_table(efx, new_rx_rss_context,
2029                                          rx_indir_table);
2030         if (rc != 0)
2031                 goto fail2;
2032
2033         if (nic_data->rx_rss_context != new_rx_rss_context)
2034                 efx_ef10_rx_free_indir_table(efx);
2035         nic_data->rx_rss_context = new_rx_rss_context;
2036         nic_data->rx_rss_context_exclusive = true;
2037         if (rx_indir_table != efx->rx_indir_table)
2038                 memcpy(efx->rx_indir_table, rx_indir_table,
2039                        sizeof(efx->rx_indir_table));
2040         return 0;
2041
2042 fail2:
2043         if (new_rx_rss_context != nic_data->rx_rss_context)
2044                 efx_ef10_free_rss_context(efx, new_rx_rss_context);
2045 fail1:
2046         netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
2047         return rc;
2048 }
2049
2050 static int efx_ef10_pf_rx_push_rss_config(struct efx_nic *efx, bool user,
2051                                           const u32 *rx_indir_table)
2052 {
2053         int rc;
2054
2055         if (efx->rss_spread == 1)
2056                 return 0;
2057
2058         rc = efx_ef10_rx_push_exclusive_rss_config(efx, rx_indir_table);
2059
2060         if (rc == -ENOBUFS && !user) {
2061                 unsigned context_size;
2062                 bool mismatch = false;
2063                 size_t i;
2064
2065                 for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table) && !mismatch;
2066                      i++)
2067                         mismatch = rx_indir_table[i] !=
2068                                 ethtool_rxfh_indir_default(i, efx->rss_spread);
2069
2070                 rc = efx_ef10_rx_push_shared_rss_config(efx, &context_size);
2071                 if (rc == 0) {
2072                         if (context_size != efx->rss_spread)
2073                                 netif_warn(efx, probe, efx->net_dev,
2074                                            "Could not allocate an exclusive RSS"
2075                                            " context; allocated a shared one of"
2076                                            " different size."
2077                                            " Wanted %u, got %u.\n",
2078                                            efx->rss_spread, context_size);
2079                         else if (mismatch)
2080                                 netif_warn(efx, probe, efx->net_dev,
2081                                            "Could not allocate an exclusive RSS"
2082                                            " context; allocated a shared one but"
2083                                            " could not apply custom"
2084                                            " indirection.\n");
2085                         else
2086                                 netif_info(efx, probe, efx->net_dev,
2087                                            "Could not allocate an exclusive RSS"
2088                                            " context; allocated a shared one.\n");
2089                 }
2090         }
2091         return rc;
2092 }
2093
2094 static int efx_ef10_vf_rx_push_rss_config(struct efx_nic *efx, bool user,
2095                                           const u32 *rx_indir_table
2096                                           __attribute__ ((unused)))
2097 {
2098         struct efx_ef10_nic_data *nic_data = efx->nic_data;
2099
2100         if (user)
2101                 return -EOPNOTSUPP;
2102         if (nic_data->rx_rss_context != EFX_EF10_RSS_CONTEXT_INVALID)
2103                 return 0;
2104         return efx_ef10_rx_push_shared_rss_config(efx, NULL);
2105 }
2106
2107 static int efx_ef10_rx_probe(struct efx_rx_queue *rx_queue)
2108 {
2109         return efx_nic_alloc_buffer(rx_queue->efx, &rx_queue->rxd.buf,
2110                                     (rx_queue->ptr_mask + 1) *
2111                                     sizeof(efx_qword_t),
2112                                     GFP_KERNEL);
2113 }
2114
2115 static void efx_ef10_rx_init(struct efx_rx_queue *rx_queue)
2116 {
2117         MCDI_DECLARE_BUF(inbuf,
2118                          MC_CMD_INIT_RXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 /
2119                                                 EFX_BUF_SIZE));
2120         struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
2121         size_t entries = rx_queue->rxd.buf.len / EFX_BUF_SIZE;
2122         struct efx_nic *efx = rx_queue->efx;
2123         struct efx_ef10_nic_data *nic_data = efx->nic_data;
2124         size_t inlen;
2125         dma_addr_t dma_addr;
2126         int rc;
2127         int i;
2128         BUILD_BUG_ON(MC_CMD_INIT_RXQ_OUT_LEN != 0);
2129
2130         rx_queue->scatter_n = 0;
2131         rx_queue->scatter_len = 0;
2132
2133         MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_SIZE, rx_queue->ptr_mask + 1);
2134         MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_TARGET_EVQ, channel->channel);
2135         MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_LABEL, efx_rx_queue_index(rx_queue));
2136         MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_INSTANCE,
2137                        efx_rx_queue_index(rx_queue));
2138         MCDI_POPULATE_DWORD_2(inbuf, INIT_RXQ_IN_FLAGS,
2139                               INIT_RXQ_IN_FLAG_PREFIX, 1,
2140                               INIT_RXQ_IN_FLAG_TIMESTAMP, 1);
2141         MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_OWNER_ID, 0);
2142         MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_PORT_ID, nic_data->vport_id);
2143
2144         dma_addr = rx_queue->rxd.buf.dma_addr;
2145
2146         netif_dbg(efx, hw, efx->net_dev, "pushing RXQ %d. %zu entries (%llx)\n",
2147                   efx_rx_queue_index(rx_queue), entries, (u64)dma_addr);
2148
2149         for (i = 0; i < entries; ++i) {
2150                 MCDI_SET_ARRAY_QWORD(inbuf, INIT_RXQ_IN_DMA_ADDR, i, dma_addr);
2151                 dma_addr += EFX_BUF_SIZE;
2152         }
2153
2154         inlen = MC_CMD_INIT_RXQ_IN_LEN(entries);
2155
2156         rc = efx_mcdi_rpc(efx, MC_CMD_INIT_RXQ, inbuf, inlen,
2157                           NULL, 0, NULL);
2158         if (rc)
2159                 netdev_WARN(efx->net_dev, "failed to initialise RXQ %d\n",
2160                             efx_rx_queue_index(rx_queue));
2161 }
2162
2163 static void efx_ef10_rx_fini(struct efx_rx_queue *rx_queue)
2164 {
2165         MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_RXQ_IN_LEN);
2166         MCDI_DECLARE_BUF_ERR(outbuf);
2167         struct efx_nic *efx = rx_queue->efx;
2168         size_t outlen;
2169         int rc;
2170
2171         MCDI_SET_DWORD(inbuf, FINI_RXQ_IN_INSTANCE,
2172                        efx_rx_queue_index(rx_queue));
2173
2174         rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_RXQ, inbuf, sizeof(inbuf),
2175                           outbuf, sizeof(outbuf), &outlen);
2176
2177         if (rc && rc != -EALREADY)
2178                 goto fail;
2179
2180         return;
2181
2182 fail:
2183         efx_mcdi_display_error(efx, MC_CMD_FINI_RXQ, MC_CMD_FINI_RXQ_IN_LEN,
2184                                outbuf, outlen, rc);
2185 }
2186
2187 static void efx_ef10_rx_remove(struct efx_rx_queue *rx_queue)
2188 {
2189         efx_nic_free_buffer(rx_queue->efx, &rx_queue->rxd.buf);
2190 }
2191
2192 /* This creates an entry in the RX descriptor queue */
2193 static inline void
2194 efx_ef10_build_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index)
2195 {
2196         struct efx_rx_buffer *rx_buf;
2197         efx_qword_t *rxd;
2198
2199         rxd = efx_rx_desc(rx_queue, index);
2200         rx_buf = efx_rx_buffer(rx_queue, index);
2201         EFX_POPULATE_QWORD_2(*rxd,
2202                              ESF_DZ_RX_KER_BYTE_CNT, rx_buf->len,
2203                              ESF_DZ_RX_KER_BUF_ADDR, rx_buf->dma_addr);
2204 }
2205
2206 static void efx_ef10_rx_write(struct efx_rx_queue *rx_queue)
2207 {
2208         struct efx_nic *efx = rx_queue->efx;
2209         unsigned int write_count;
2210         efx_dword_t reg;
2211
2212         /* Firmware requires that RX_DESC_WPTR be a multiple of 8 */
2213         write_count = rx_queue->added_count & ~7;
2214         if (rx_queue->notified_count == write_count)
2215                 return;
2216
2217         do
2218                 efx_ef10_build_rx_desc(
2219                         rx_queue,
2220                         rx_queue->notified_count & rx_queue->ptr_mask);
2221         while (++rx_queue->notified_count != write_count);
2222
2223         wmb();
2224         EFX_POPULATE_DWORD_1(reg, ERF_DZ_RX_DESC_WPTR,
2225                              write_count & rx_queue->ptr_mask);
2226         efx_writed_page(efx, &reg, ER_DZ_RX_DESC_UPD,
2227                         efx_rx_queue_index(rx_queue));
2228 }
2229
2230 static efx_mcdi_async_completer efx_ef10_rx_defer_refill_complete;
2231
2232 static void efx_ef10_rx_defer_refill(struct efx_rx_queue *rx_queue)
2233 {
2234         struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
2235         MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
2236         efx_qword_t event;
2237
2238         EFX_POPULATE_QWORD_2(event,
2239                              ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV,
2240                              ESF_DZ_EV_DATA, EFX_EF10_REFILL);
2241
2242         MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
2243
2244         /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
2245          * already swapped the data to little-endian order.
2246          */
2247         memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
2248                sizeof(efx_qword_t));
2249
2250         efx_mcdi_rpc_async(channel->efx, MC_CMD_DRIVER_EVENT,
2251                            inbuf, sizeof(inbuf), 0,
2252                            efx_ef10_rx_defer_refill_complete, 0);
2253 }
2254
2255 static void
2256 efx_ef10_rx_defer_refill_complete(struct efx_nic *efx, unsigned long cookie,
2257                                   int rc, efx_dword_t *outbuf,
2258                                   size_t outlen_actual)
2259 {
2260         /* nothing to do */
2261 }
2262
2263 static int efx_ef10_ev_probe(struct efx_channel *channel)
2264 {
2265         return efx_nic_alloc_buffer(channel->efx, &channel->eventq.buf,
2266                                     (channel->eventq_mask + 1) *
2267                                     sizeof(efx_qword_t),
2268                                     GFP_KERNEL);
2269 }
2270
2271 static void efx_ef10_ev_fini(struct efx_channel *channel)
2272 {
2273         MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_EVQ_IN_LEN);
2274         MCDI_DECLARE_BUF_ERR(outbuf);
2275         struct efx_nic *efx = channel->efx;
2276         size_t outlen;
2277         int rc;
2278
2279         MCDI_SET_DWORD(inbuf, FINI_EVQ_IN_INSTANCE, channel->channel);
2280
2281         rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_EVQ, inbuf, sizeof(inbuf),
2282                           outbuf, sizeof(outbuf), &outlen);
2283
2284         if (rc && rc != -EALREADY)
2285                 goto fail;
2286
2287         return;
2288
2289 fail:
2290         efx_mcdi_display_error(efx, MC_CMD_FINI_EVQ, MC_CMD_FINI_EVQ_IN_LEN,
2291                                outbuf, outlen, rc);
2292 }
2293
2294 static int efx_ef10_ev_init(struct efx_channel *channel)
2295 {
2296         MCDI_DECLARE_BUF(inbuf,
2297                          MC_CMD_INIT_EVQ_IN_LEN(EFX_MAX_EVQ_SIZE * 8 /
2298                                                 EFX_BUF_SIZE));
2299         MCDI_DECLARE_BUF(outbuf, MC_CMD_INIT_EVQ_OUT_LEN);
2300         size_t entries = channel->eventq.buf.len / EFX_BUF_SIZE;
2301         struct efx_nic *efx = channel->efx;
2302         struct efx_ef10_nic_data *nic_data;
2303         bool supports_rx_merge;
2304         size_t inlen, outlen;
2305         unsigned int enabled, implemented;
2306         dma_addr_t dma_addr;
2307         int rc;
2308         int i;
2309
2310         nic_data = efx->nic_data;
2311         supports_rx_merge =
2312                 !!(nic_data->datapath_caps &
2313                    1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN);
2314
2315         /* Fill event queue with all ones (i.e. empty events) */
2316         memset(channel->eventq.buf.addr, 0xff, channel->eventq.buf.len);
2317
2318         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_SIZE, channel->eventq_mask + 1);
2319         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_INSTANCE, channel->channel);
2320         /* INIT_EVQ expects index in vector table, not absolute */
2321         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_IRQ_NUM, channel->channel);
2322         MCDI_POPULATE_DWORD_4(inbuf, INIT_EVQ_IN_FLAGS,
2323                               INIT_EVQ_IN_FLAG_INTERRUPTING, 1,
2324                               INIT_EVQ_IN_FLAG_RX_MERGE, 1,
2325                               INIT_EVQ_IN_FLAG_TX_MERGE, 1,
2326                               INIT_EVQ_IN_FLAG_CUT_THRU, !supports_rx_merge);
2327         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_MODE,
2328                        MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS);
2329         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_LOAD, 0);
2330         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_RELOAD, 0);
2331         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_MODE,
2332                        MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS);
2333         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_THRSHLD, 0);
2334
2335         dma_addr = channel->eventq.buf.dma_addr;
2336         for (i = 0; i < entries; ++i) {
2337                 MCDI_SET_ARRAY_QWORD(inbuf, INIT_EVQ_IN_DMA_ADDR, i, dma_addr);
2338                 dma_addr += EFX_BUF_SIZE;
2339         }
2340
2341         inlen = MC_CMD_INIT_EVQ_IN_LEN(entries);
2342
2343         rc = efx_mcdi_rpc(efx, MC_CMD_INIT_EVQ, inbuf, inlen,
2344                           outbuf, sizeof(outbuf), &outlen);
2345         /* IRQ return is ignored */
2346         if (channel->channel || rc)
2347                 return rc;
2348
2349         /* Successfully created event queue on channel 0 */
2350         rc = efx_mcdi_get_workarounds(efx, &implemented, &enabled);
2351         if (rc == -ENOSYS) {
2352                 /* GET_WORKAROUNDS was implemented before the bug26807
2353                  * workaround, thus the latter must be unavailable in this fw
2354                  */
2355                 nic_data->workaround_26807 = false;
2356                 rc = 0;
2357         } else if (rc) {
2358                 goto fail;
2359         } else {
2360                 nic_data->workaround_26807 =
2361                         !!(enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG26807);
2362
2363                 if (implemented & MC_CMD_GET_WORKAROUNDS_OUT_BUG26807 &&
2364                     !nic_data->workaround_26807) {
2365                         unsigned int flags;
2366
2367                         rc = efx_mcdi_set_workaround(efx,
2368                                                      MC_CMD_WORKAROUND_BUG26807,
2369                                                      true, &flags);
2370
2371                         if (!rc) {
2372                                 if (flags &
2373                                     1 << MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN) {
2374                                         netif_info(efx, drv, efx->net_dev,
2375                                                    "other functions on NIC have been reset\n");
2376                                         /* MC's boot count has incremented */
2377                                         ++nic_data->warm_boot_count;
2378                                 }
2379                                 nic_data->workaround_26807 = true;
2380                         } else if (rc == -EPERM) {
2381                                 rc = 0;
2382                         }
2383                 }
2384         }
2385
2386         if (!rc)
2387                 return 0;
2388
2389 fail:
2390         efx_ef10_ev_fini(channel);
2391         return rc;
2392 }
2393
2394 static void efx_ef10_ev_remove(struct efx_channel *channel)
2395 {
2396         efx_nic_free_buffer(channel->efx, &channel->eventq.buf);
2397 }
2398
2399 static void efx_ef10_handle_rx_wrong_queue(struct efx_rx_queue *rx_queue,
2400                                            unsigned int rx_queue_label)
2401 {
2402         struct efx_nic *efx = rx_queue->efx;
2403
2404         netif_info(efx, hw, efx->net_dev,
2405                    "rx event arrived on queue %d labeled as queue %u\n",
2406                    efx_rx_queue_index(rx_queue), rx_queue_label);
2407
2408         efx_schedule_reset(efx, RESET_TYPE_DISABLE);
2409 }
2410
2411 static void
2412 efx_ef10_handle_rx_bad_lbits(struct efx_rx_queue *rx_queue,
2413                              unsigned int actual, unsigned int expected)
2414 {
2415         unsigned int dropped = (actual - expected) & rx_queue->ptr_mask;
2416         struct efx_nic *efx = rx_queue->efx;
2417
2418         netif_info(efx, hw, efx->net_dev,
2419                    "dropped %d events (index=%d expected=%d)\n",
2420                    dropped, actual, expected);
2421
2422         efx_schedule_reset(efx, RESET_TYPE_DISABLE);
2423 }
2424
2425 /* partially received RX was aborted. clean up. */
2426 static void efx_ef10_handle_rx_abort(struct efx_rx_queue *rx_queue)
2427 {
2428         unsigned int rx_desc_ptr;
2429
2430         netif_dbg(rx_queue->efx, hw, rx_queue->efx->net_dev,
2431                   "scattered RX aborted (dropping %u buffers)\n",
2432                   rx_queue->scatter_n);
2433
2434         rx_desc_ptr = rx_queue->removed_count & rx_queue->ptr_mask;
2435
2436         efx_rx_packet(rx_queue, rx_desc_ptr, rx_queue->scatter_n,
2437                       0, EFX_RX_PKT_DISCARD);
2438
2439         rx_queue->removed_count += rx_queue->scatter_n;
2440         rx_queue->scatter_n = 0;
2441         rx_queue->scatter_len = 0;
2442         ++efx_rx_queue_channel(rx_queue)->n_rx_nodesc_trunc;
2443 }
2444
2445 static int efx_ef10_handle_rx_event(struct efx_channel *channel,
2446                                     const efx_qword_t *event)
2447 {
2448         unsigned int rx_bytes, next_ptr_lbits, rx_queue_label, rx_l4_class;
2449         unsigned int n_descs, n_packets, i;
2450         struct efx_nic *efx = channel->efx;
2451         struct efx_rx_queue *rx_queue;
2452         bool rx_cont;
2453         u16 flags = 0;
2454
2455         if (unlikely(ACCESS_ONCE(efx->reset_pending)))
2456                 return 0;
2457
2458         /* Basic packet information */
2459         rx_bytes = EFX_QWORD_FIELD(*event, ESF_DZ_RX_BYTES);
2460         next_ptr_lbits = EFX_QWORD_FIELD(*event, ESF_DZ_RX_DSC_PTR_LBITS);
2461         rx_queue_label = EFX_QWORD_FIELD(*event, ESF_DZ_RX_QLABEL);
2462         rx_l4_class = EFX_QWORD_FIELD(*event, ESF_DZ_RX_L4_CLASS);
2463         rx_cont = EFX_QWORD_FIELD(*event, ESF_DZ_RX_CONT);
2464
2465         if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_DROP_EVENT))
2466                 netdev_WARN(efx->net_dev, "saw RX_DROP_EVENT: event="
2467                             EFX_QWORD_FMT "\n",
2468                             EFX_QWORD_VAL(*event));
2469
2470         rx_queue = efx_channel_get_rx_queue(channel);
2471
2472         if (unlikely(rx_queue_label != efx_rx_queue_index(rx_queue)))
2473                 efx_ef10_handle_rx_wrong_queue(rx_queue, rx_queue_label);
2474
2475         n_descs = ((next_ptr_lbits - rx_queue->removed_count) &
2476                    ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1));
2477
2478         if (n_descs != rx_queue->scatter_n + 1) {
2479                 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2480
2481                 /* detect rx abort */
2482                 if (unlikely(n_descs == rx_queue->scatter_n)) {
2483                         if (rx_queue->scatter_n == 0 || rx_bytes != 0)
2484                                 netdev_WARN(efx->net_dev,
2485                                             "invalid RX abort: scatter_n=%u event="
2486                                             EFX_QWORD_FMT "\n",
2487                                             rx_queue->scatter_n,
2488                                             EFX_QWORD_VAL(*event));
2489                         efx_ef10_handle_rx_abort(rx_queue);
2490                         return 0;
2491                 }
2492
2493                 /* Check that RX completion merging is valid, i.e.
2494                  * the current firmware supports it and this is a
2495                  * non-scattered packet.
2496                  */
2497                 if (!(nic_data->datapath_caps &
2498                       (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN)) ||
2499                     rx_queue->scatter_n != 0 || rx_cont) {
2500                         efx_ef10_handle_rx_bad_lbits(
2501                                 rx_queue, next_ptr_lbits,
2502                                 (rx_queue->removed_count +
2503                                  rx_queue->scatter_n + 1) &
2504                                 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1));
2505                         return 0;
2506                 }
2507
2508                 /* Merged completion for multiple non-scattered packets */
2509                 rx_queue->scatter_n = 1;
2510                 rx_queue->scatter_len = 0;
2511                 n_packets = n_descs;
2512                 ++channel->n_rx_merge_events;
2513                 channel->n_rx_merge_packets += n_packets;
2514                 flags |= EFX_RX_PKT_PREFIX_LEN;
2515         } else {
2516                 ++rx_queue->scatter_n;
2517                 rx_queue->scatter_len += rx_bytes;
2518                 if (rx_cont)
2519                         return 0;
2520                 n_packets = 1;
2521         }
2522
2523         if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_RX_ECRC_ERR)))
2524                 flags |= EFX_RX_PKT_DISCARD;
2525
2526         if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_RX_IPCKSUM_ERR))) {
2527                 channel->n_rx_ip_hdr_chksum_err += n_packets;
2528         } else if (unlikely(EFX_QWORD_FIELD(*event,
2529                                             ESF_DZ_RX_TCPUDP_CKSUM_ERR))) {
2530                 channel->n_rx_tcp_udp_chksum_err += n_packets;
2531         } else if (rx_l4_class == ESE_DZ_L4_CLASS_TCP ||
2532                    rx_l4_class == ESE_DZ_L4_CLASS_UDP) {
2533                 flags |= EFX_RX_PKT_CSUMMED;
2534         }
2535
2536         if (rx_l4_class == ESE_DZ_L4_CLASS_TCP)
2537                 flags |= EFX_RX_PKT_TCP;
2538
2539         channel->irq_mod_score += 2 * n_packets;
2540
2541         /* Handle received packet(s) */
2542         for (i = 0; i < n_packets; i++) {
2543                 efx_rx_packet(rx_queue,
2544                               rx_queue->removed_count & rx_queue->ptr_mask,
2545                               rx_queue->scatter_n, rx_queue->scatter_len,
2546                               flags);
2547                 rx_queue->removed_count += rx_queue->scatter_n;
2548         }
2549
2550         rx_queue->scatter_n = 0;
2551         rx_queue->scatter_len = 0;
2552
2553         return n_packets;
2554 }
2555
2556 static int
2557 efx_ef10_handle_tx_event(struct efx_channel *channel, efx_qword_t *event)
2558 {
2559         struct efx_nic *efx = channel->efx;
2560         struct efx_tx_queue *tx_queue;
2561         unsigned int tx_ev_desc_ptr;
2562         unsigned int tx_ev_q_label;
2563         int tx_descs = 0;
2564
2565         if (unlikely(ACCESS_ONCE(efx->reset_pending)))
2566                 return 0;
2567
2568         if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_TX_DROP_EVENT)))
2569                 return 0;
2570
2571         /* Transmit completion */
2572         tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, ESF_DZ_TX_DESCR_INDX);
2573         tx_ev_q_label = EFX_QWORD_FIELD(*event, ESF_DZ_TX_QLABEL);
2574         tx_queue = efx_channel_get_tx_queue(channel,
2575                                             tx_ev_q_label % EFX_TXQ_TYPES);
2576         tx_descs = ((tx_ev_desc_ptr + 1 - tx_queue->read_count) &
2577                     tx_queue->ptr_mask);
2578         efx_xmit_done(tx_queue, tx_ev_desc_ptr & tx_queue->ptr_mask);
2579
2580         return tx_descs;
2581 }
2582
2583 static void
2584 efx_ef10_handle_driver_event(struct efx_channel *channel, efx_qword_t *event)
2585 {
2586         struct efx_nic *efx = channel->efx;
2587         int subcode;
2588
2589         subcode = EFX_QWORD_FIELD(*event, ESF_DZ_DRV_SUB_CODE);
2590
2591         switch (subcode) {
2592         case ESE_DZ_DRV_TIMER_EV:
2593         case ESE_DZ_DRV_WAKE_UP_EV:
2594                 break;
2595         case ESE_DZ_DRV_START_UP_EV:
2596                 /* event queue init complete. ok. */
2597                 break;
2598         default:
2599                 netif_err(efx, hw, efx->net_dev,
2600                           "channel %d unknown driver event type %d"
2601                           " (data " EFX_QWORD_FMT ")\n",
2602                           channel->channel, subcode,
2603                           EFX_QWORD_VAL(*event));
2604
2605         }
2606 }
2607
2608 static void efx_ef10_handle_driver_generated_event(struct efx_channel *channel,
2609                                                    efx_qword_t *event)
2610 {
2611         struct efx_nic *efx = channel->efx;
2612         u32 subcode;
2613
2614         subcode = EFX_QWORD_FIELD(*event, EFX_DWORD_0);
2615
2616         switch (subcode) {
2617         case EFX_EF10_TEST:
2618                 channel->event_test_cpu = raw_smp_processor_id();
2619                 break;
2620         case EFX_EF10_REFILL:
2621                 /* The queue must be empty, so we won't receive any rx
2622                  * events, so efx_process_channel() won't refill the
2623                  * queue. Refill it here
2624                  */
2625                 efx_fast_push_rx_descriptors(&channel->rx_queue, true);
2626                 break;
2627         default:
2628                 netif_err(efx, hw, efx->net_dev,
2629                           "channel %d unknown driver event type %u"
2630                           " (data " EFX_QWORD_FMT ")\n",
2631                           channel->channel, (unsigned) subcode,
2632                           EFX_QWORD_VAL(*event));
2633         }
2634 }
2635
2636 static int efx_ef10_ev_process(struct efx_channel *channel, int quota)
2637 {
2638         struct efx_nic *efx = channel->efx;
2639         efx_qword_t event, *p_event;
2640         unsigned int read_ptr;
2641         int ev_code;
2642         int tx_descs = 0;
2643         int spent = 0;
2644
2645         if (quota <= 0)
2646                 return spent;
2647
2648         read_ptr = channel->eventq_read_ptr;
2649
2650         for (;;) {
2651                 p_event = efx_event(channel, read_ptr);
2652                 event = *p_event;
2653
2654                 if (!efx_event_present(&event))
2655                         break;
2656
2657                 EFX_SET_QWORD(*p_event);
2658
2659                 ++read_ptr;
2660
2661                 ev_code = EFX_QWORD_FIELD(event, ESF_DZ_EV_CODE);
2662
2663                 netif_vdbg(efx, drv, efx->net_dev,
2664                            "processing event on %d " EFX_QWORD_FMT "\n",
2665                            channel->channel, EFX_QWORD_VAL(event));
2666
2667                 switch (ev_code) {
2668                 case ESE_DZ_EV_CODE_MCDI_EV:
2669                         efx_mcdi_process_event(channel, &event);
2670                         break;
2671                 case ESE_DZ_EV_CODE_RX_EV:
2672                         spent += efx_ef10_handle_rx_event(channel, &event);
2673                         if (spent >= quota) {
2674                                 /* XXX can we split a merged event to
2675                                  * avoid going over-quota?
2676                                  */
2677                                 spent = quota;
2678                                 goto out;
2679                         }
2680                         break;
2681                 case ESE_DZ_EV_CODE_TX_EV:
2682                         tx_descs += efx_ef10_handle_tx_event(channel, &event);
2683                         if (tx_descs > efx->txq_entries) {
2684                                 spent = quota;
2685                                 goto out;
2686                         } else if (++spent == quota) {
2687                                 goto out;
2688                         }
2689                         break;
2690                 case ESE_DZ_EV_CODE_DRIVER_EV:
2691                         efx_ef10_handle_driver_event(channel, &event);
2692                         if (++spent == quota)
2693                                 goto out;
2694                         break;
2695                 case EFX_EF10_DRVGEN_EV:
2696                         efx_ef10_handle_driver_generated_event(channel, &event);
2697                         break;
2698                 default:
2699                         netif_err(efx, hw, efx->net_dev,
2700                                   "channel %d unknown event type %d"
2701                                   " (data " EFX_QWORD_FMT ")\n",
2702                                   channel->channel, ev_code,
2703                                   EFX_QWORD_VAL(event));
2704                 }
2705         }
2706
2707 out:
2708         channel->eventq_read_ptr = read_ptr;
2709         return spent;
2710 }
2711
2712 static void efx_ef10_ev_read_ack(struct efx_channel *channel)
2713 {
2714         struct efx_nic *efx = channel->efx;
2715         efx_dword_t rptr;
2716
2717         if (EFX_EF10_WORKAROUND_35388(efx)) {
2718                 BUILD_BUG_ON(EFX_MIN_EVQ_SIZE <
2719                              (1 << ERF_DD_EVQ_IND_RPTR_WIDTH));
2720                 BUILD_BUG_ON(EFX_MAX_EVQ_SIZE >
2721                              (1 << 2 * ERF_DD_EVQ_IND_RPTR_WIDTH));
2722
2723                 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS,
2724                                      EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH,
2725                                      ERF_DD_EVQ_IND_RPTR,
2726                                      (channel->eventq_read_ptr &
2727                                       channel->eventq_mask) >>
2728                                      ERF_DD_EVQ_IND_RPTR_WIDTH);
2729                 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT,
2730                                 channel->channel);
2731                 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS,
2732                                      EFE_DD_EVQ_IND_RPTR_FLAGS_LOW,
2733                                      ERF_DD_EVQ_IND_RPTR,
2734                                      channel->eventq_read_ptr &
2735                                      ((1 << ERF_DD_EVQ_IND_RPTR_WIDTH) - 1));
2736                 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT,
2737                                 channel->channel);
2738         } else {
2739                 EFX_POPULATE_DWORD_1(rptr, ERF_DZ_EVQ_RPTR,
2740                                      channel->eventq_read_ptr &
2741                                      channel->eventq_mask);
2742                 efx_writed_page(efx, &rptr, ER_DZ_EVQ_RPTR, channel->channel);
2743         }
2744 }
2745
2746 static void efx_ef10_ev_test_generate(struct efx_channel *channel)
2747 {
2748         MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
2749         struct efx_nic *efx = channel->efx;
2750         efx_qword_t event;
2751         int rc;
2752
2753         EFX_POPULATE_QWORD_2(event,
2754                              ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV,
2755                              ESF_DZ_EV_DATA, EFX_EF10_TEST);
2756
2757         MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
2758
2759         /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
2760          * already swapped the data to little-endian order.
2761          */
2762         memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
2763                sizeof(efx_qword_t));
2764
2765         rc = efx_mcdi_rpc(efx, MC_CMD_DRIVER_EVENT, inbuf, sizeof(inbuf),
2766                           NULL, 0, NULL);
2767         if (rc != 0)
2768                 goto fail;
2769
2770         return;
2771
2772 fail:
2773         WARN_ON(true);
2774         netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
2775 }
2776
2777 void efx_ef10_handle_drain_event(struct efx_nic *efx)
2778 {
2779         if (atomic_dec_and_test(&efx->active_queues))
2780                 wake_up(&efx->flush_wq);
2781
2782         WARN_ON(atomic_read(&efx->active_queues) < 0);
2783 }
2784
2785 static int efx_ef10_fini_dmaq(struct efx_nic *efx)
2786 {
2787         struct efx_ef10_nic_data *nic_data = efx->nic_data;
2788         struct efx_channel *channel;
2789         struct efx_tx_queue *tx_queue;
2790         struct efx_rx_queue *rx_queue;
2791         int pending;
2792
2793         /* If the MC has just rebooted, the TX/RX queues will have already been
2794          * torn down, but efx->active_queues needs to be set to zero.
2795          */
2796         if (nic_data->must_realloc_vis) {
2797                 atomic_set(&efx->active_queues, 0);
2798                 return 0;
2799         }
2800
2801         /* Do not attempt to write to the NIC during EEH recovery */
2802         if (efx->state != STATE_RECOVERY) {
2803                 efx_for_each_channel(channel, efx) {
2804                         efx_for_each_channel_rx_queue(rx_queue, channel)
2805                                 efx_ef10_rx_fini(rx_queue);
2806                         efx_for_each_channel_tx_queue(tx_queue, channel)
2807                                 efx_ef10_tx_fini(tx_queue);
2808                 }
2809
2810                 wait_event_timeout(efx->flush_wq,
2811                                    atomic_read(&efx->active_queues) == 0,
2812                                    msecs_to_jiffies(EFX_MAX_FLUSH_TIME));
2813                 pending = atomic_read(&efx->active_queues);
2814                 if (pending) {
2815                         netif_err(efx, hw, efx->net_dev, "failed to flush %d queues\n",
2816                                   pending);
2817                         return -ETIMEDOUT;
2818                 }
2819         }
2820
2821         return 0;
2822 }
2823
2824 static void efx_ef10_prepare_flr(struct efx_nic *efx)
2825 {
2826         atomic_set(&efx->active_queues, 0);
2827 }
2828
2829 static bool efx_ef10_filter_equal(const struct efx_filter_spec *left,
2830                                   const struct efx_filter_spec *right)
2831 {
2832         if ((left->match_flags ^ right->match_flags) |
2833             ((left->flags ^ right->flags) &
2834              (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)))
2835                 return false;
2836
2837         return memcmp(&left->outer_vid, &right->outer_vid,
2838                       sizeof(struct efx_filter_spec) -
2839                       offsetof(struct efx_filter_spec, outer_vid)) == 0;
2840 }
2841
2842 static unsigned int efx_ef10_filter_hash(const struct efx_filter_spec *spec)
2843 {
2844         BUILD_BUG_ON(offsetof(struct efx_filter_spec, outer_vid) & 3);
2845         return jhash2((const u32 *)&spec->outer_vid,
2846                       (sizeof(struct efx_filter_spec) -
2847                        offsetof(struct efx_filter_spec, outer_vid)) / 4,
2848                       0);
2849         /* XXX should we randomise the initval? */
2850 }
2851
2852 /* Decide whether a filter should be exclusive or else should allow
2853  * delivery to additional recipients.  Currently we decide that
2854  * filters for specific local unicast MAC and IP addresses are
2855  * exclusive.
2856  */
2857 static bool efx_ef10_filter_is_exclusive(const struct efx_filter_spec *spec)
2858 {
2859         if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC &&
2860             !is_multicast_ether_addr(spec->loc_mac))
2861                 return true;
2862
2863         if ((spec->match_flags &
2864              (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) ==
2865             (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) {
2866                 if (spec->ether_type == htons(ETH_P_IP) &&
2867                     !ipv4_is_multicast(spec->loc_host[0]))
2868                         return true;
2869                 if (spec->ether_type == htons(ETH_P_IPV6) &&
2870                     ((const u8 *)spec->loc_host)[0] != 0xff)
2871                         return true;
2872         }
2873
2874         return false;
2875 }
2876
2877 static struct efx_filter_spec *
2878 efx_ef10_filter_entry_spec(const struct efx_ef10_filter_table *table,
2879                            unsigned int filter_idx)
2880 {
2881         return (struct efx_filter_spec *)(table->entry[filter_idx].spec &
2882                                           ~EFX_EF10_FILTER_FLAGS);
2883 }
2884
2885 static unsigned int
2886 efx_ef10_filter_entry_flags(const struct efx_ef10_filter_table *table,
2887                            unsigned int filter_idx)
2888 {
2889         return table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAGS;
2890 }
2891
2892 static void
2893 efx_ef10_filter_set_entry(struct efx_ef10_filter_table *table,
2894                           unsigned int filter_idx,
2895                           const struct efx_filter_spec *spec,
2896                           unsigned int flags)
2897 {
2898         table->entry[filter_idx].spec = (unsigned long)spec | flags;
2899 }
2900
2901 static void efx_ef10_filter_push_prep(struct efx_nic *efx,
2902                                       const struct efx_filter_spec *spec,
2903                                       efx_dword_t *inbuf, u64 handle,
2904                                       bool replacing)
2905 {
2906         struct efx_ef10_nic_data *nic_data = efx->nic_data;
2907
2908         memset(inbuf, 0, MC_CMD_FILTER_OP_IN_LEN);
2909
2910         if (replacing) {
2911                 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
2912                                MC_CMD_FILTER_OP_IN_OP_REPLACE);
2913                 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE, handle);
2914         } else {
2915                 u32 match_fields = 0;
2916
2917                 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
2918                                efx_ef10_filter_is_exclusive(spec) ?
2919                                MC_CMD_FILTER_OP_IN_OP_INSERT :
2920                                MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE);
2921
2922                 /* Convert match flags and values.  Unlike almost
2923                  * everything else in MCDI, these fields are in
2924                  * network byte order.
2925                  */
2926                 if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC_IG)
2927                         match_fields |=
2928                                 is_multicast_ether_addr(spec->loc_mac) ?
2929                                 1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_LBN :
2930                                 1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_LBN;
2931 #define COPY_FIELD(gen_flag, gen_field, mcdi_field)                          \
2932                 if (spec->match_flags & EFX_FILTER_MATCH_ ## gen_flag) {     \
2933                         match_fields |=                                      \
2934                                 1 << MC_CMD_FILTER_OP_IN_MATCH_ ##           \
2935                                 mcdi_field ## _LBN;                          \
2936                         BUILD_BUG_ON(                                        \
2937                                 MC_CMD_FILTER_OP_IN_ ## mcdi_field ## _LEN < \
2938                                 sizeof(spec->gen_field));                    \
2939                         memcpy(MCDI_PTR(inbuf, FILTER_OP_IN_ ## mcdi_field), \
2940                                &spec->gen_field, sizeof(spec->gen_field));   \
2941                 }
2942                 COPY_FIELD(REM_HOST, rem_host, SRC_IP);
2943                 COPY_FIELD(LOC_HOST, loc_host, DST_IP);
2944                 COPY_FIELD(REM_MAC, rem_mac, SRC_MAC);
2945                 COPY_FIELD(REM_PORT, rem_port, SRC_PORT);
2946                 COPY_FIELD(LOC_MAC, loc_mac, DST_MAC);
2947                 COPY_FIELD(LOC_PORT, loc_port, DST_PORT);
2948                 COPY_FIELD(ETHER_TYPE, ether_type, ETHER_TYPE);
2949                 COPY_FIELD(INNER_VID, inner_vid, INNER_VLAN);
2950                 COPY_FIELD(OUTER_VID, outer_vid, OUTER_VLAN);
2951                 COPY_FIELD(IP_PROTO, ip_proto, IP_PROTO);
2952 #undef COPY_FIELD
2953                 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_MATCH_FIELDS,
2954                                match_fields);
2955         }
2956
2957         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_PORT_ID, nic_data->vport_id);
2958         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_DEST,
2959                        spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ?
2960                        MC_CMD_FILTER_OP_IN_RX_DEST_DROP :
2961                        MC_CMD_FILTER_OP_IN_RX_DEST_HOST);
2962         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_TX_DOMAIN, 0);
2963         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_TX_DEST,
2964                        MC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT);
2965         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_QUEUE,
2966                        spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ?
2967                        0 : spec->dmaq_id);
2968         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_MODE,
2969                        (spec->flags & EFX_FILTER_FLAG_RX_RSS) ?
2970                        MC_CMD_FILTER_OP_IN_RX_MODE_RSS :
2971                        MC_CMD_FILTER_OP_IN_RX_MODE_SIMPLE);
2972         if (spec->flags & EFX_FILTER_FLAG_RX_RSS)
2973                 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_CONTEXT,
2974                                spec->rss_context !=
2975                                EFX_FILTER_RSS_CONTEXT_DEFAULT ?
2976                                spec->rss_context : nic_data->rx_rss_context);
2977 }
2978
2979 static int efx_ef10_filter_push(struct efx_nic *efx,
2980                                 const struct efx_filter_spec *spec,
2981                                 u64 *handle, bool replacing)
2982 {
2983         MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
2984         MCDI_DECLARE_BUF(outbuf, MC_CMD_FILTER_OP_OUT_LEN);
2985         int rc;
2986
2987         efx_ef10_filter_push_prep(efx, spec, inbuf, *handle, replacing);
2988         rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
2989                           outbuf, sizeof(outbuf), NULL);
2990         if (rc == 0)
2991                 *handle = MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE);
2992         if (rc == -ENOSPC)
2993                 rc = -EBUSY; /* to match efx_farch_filter_insert() */
2994         return rc;
2995 }
2996
2997 static int efx_ef10_filter_rx_match_pri(struct efx_ef10_filter_table *table,
2998                                         enum efx_filter_match_flags match_flags)
2999 {
3000         unsigned int match_pri;
3001
3002         for (match_pri = 0;
3003              match_pri < table->rx_match_count;
3004              match_pri++)
3005                 if (table->rx_match_flags[match_pri] == match_flags)
3006                         return match_pri;
3007
3008         return -EPROTONOSUPPORT;
3009 }
3010
3011 static s32 efx_ef10_filter_insert(struct efx_nic *efx,
3012                                   struct efx_filter_spec *spec,
3013                                   bool replace_equal)
3014 {
3015         struct efx_ef10_filter_table *table = efx->filter_state;
3016         DECLARE_BITMAP(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT);
3017         struct efx_filter_spec *saved_spec;
3018         unsigned int match_pri, hash;
3019         unsigned int priv_flags;
3020         bool replacing = false;
3021         int ins_index = -1;
3022         DEFINE_WAIT(wait);
3023         bool is_mc_recip;
3024         s32 rc;
3025
3026         /* For now, only support RX filters */
3027         if ((spec->flags & (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)) !=
3028             EFX_FILTER_FLAG_RX)
3029                 return -EINVAL;
3030
3031         rc = efx_ef10_filter_rx_match_pri(table, spec->match_flags);
3032         if (rc < 0)
3033                 return rc;
3034         match_pri = rc;
3035
3036         hash = efx_ef10_filter_hash(spec);
3037         is_mc_recip = efx_filter_is_mc_recipient(spec);
3038         if (is_mc_recip)
3039                 bitmap_zero(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT);
3040
3041         /* Find any existing filters with the same match tuple or
3042          * else a free slot to insert at.  If any of them are busy,
3043          * we have to wait and retry.
3044          */
3045         for (;;) {
3046                 unsigned int depth = 1;
3047                 unsigned int i;
3048
3049                 spin_lock_bh(&efx->filter_lock);
3050
3051                 for (;;) {
3052                         i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
3053                         saved_spec = efx_ef10_filter_entry_spec(table, i);
3054
3055                         if (!saved_spec) {
3056                                 if (ins_index < 0)
3057                                         ins_index = i;
3058                         } else if (efx_ef10_filter_equal(spec, saved_spec)) {
3059                                 if (table->entry[i].spec &
3060                                     EFX_EF10_FILTER_FLAG_BUSY)
3061                                         break;
3062                                 if (spec->priority < saved_spec->priority &&
3063                                     spec->priority != EFX_FILTER_PRI_AUTO) {
3064                                         rc = -EPERM;
3065                                         goto out_unlock;
3066                                 }
3067                                 if (!is_mc_recip) {
3068                                         /* This is the only one */
3069                                         if (spec->priority ==
3070                                             saved_spec->priority &&
3071                                             !replace_equal) {
3072                                                 rc = -EEXIST;
3073                                                 goto out_unlock;
3074                                         }
3075                                         ins_index = i;
3076                                         goto found;
3077                                 } else if (spec->priority >
3078                                            saved_spec->priority ||
3079                                            (spec->priority ==
3080                                             saved_spec->priority &&
3081                                             replace_equal)) {
3082                                         if (ins_index < 0)
3083                                                 ins_index = i;
3084                                         else
3085                                                 __set_bit(depth, mc_rem_map);
3086                                 }
3087                         }
3088
3089                         /* Once we reach the maximum search depth, use
3090                          * the first suitable slot or return -EBUSY if
3091                          * there was none
3092                          */
3093                         if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) {
3094                                 if (ins_index < 0) {
3095                                         rc = -EBUSY;
3096                                         goto out_unlock;
3097                                 }
3098                                 goto found;
3099                         }
3100
3101                         ++depth;
3102                 }
3103
3104                 prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE);
3105                 spin_unlock_bh(&efx->filter_lock);
3106                 schedule();
3107         }
3108
3109 found:
3110         /* Create a software table entry if necessary, and mark it
3111          * busy.  We might yet fail to insert, but any attempt to
3112          * insert a conflicting filter while we're waiting for the
3113          * firmware must find the busy entry.
3114          */
3115         saved_spec = efx_ef10_filter_entry_spec(table, ins_index);
3116         if (saved_spec) {
3117                 if (spec->priority == EFX_FILTER_PRI_AUTO &&
3118                     saved_spec->priority >= EFX_FILTER_PRI_AUTO) {
3119                         /* Just make sure it won't be removed */
3120                         if (saved_spec->priority > EFX_FILTER_PRI_AUTO)
3121                                 saved_spec->flags |= EFX_FILTER_FLAG_RX_OVER_AUTO;
3122                         table->entry[ins_index].spec &=
3123                                 ~EFX_EF10_FILTER_FLAG_AUTO_OLD;
3124                         rc = ins_index;
3125                         goto out_unlock;
3126                 }
3127                 replacing = true;
3128                 priv_flags = efx_ef10_filter_entry_flags(table, ins_index);
3129         } else {
3130                 saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC);
3131                 if (!saved_spec) {
3132                         rc = -ENOMEM;
3133                         goto out_unlock;
3134                 }
3135                 *saved_spec = *spec;
3136                 priv_flags = 0;
3137         }
3138         efx_ef10_filter_set_entry(table, ins_index, saved_spec,
3139                                   priv_flags | EFX_EF10_FILTER_FLAG_BUSY);
3140
3141         /* Mark lower-priority multicast recipients busy prior to removal */
3142         if (is_mc_recip) {
3143                 unsigned int depth, i;
3144
3145                 for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) {
3146                         i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
3147                         if (test_bit(depth, mc_rem_map))
3148                                 table->entry[i].spec |=
3149                                         EFX_EF10_FILTER_FLAG_BUSY;
3150                 }
3151         }
3152
3153         spin_unlock_bh(&efx->filter_lock);
3154
3155         rc = efx_ef10_filter_push(efx, spec, &table->entry[ins_index].handle,
3156                                   replacing);
3157
3158         /* Finalise the software table entry */
3159         spin_lock_bh(&efx->filter_lock);
3160         if (rc == 0) {
3161                 if (replacing) {
3162                         /* Update the fields that may differ */
3163                         if (saved_spec->priority == EFX_FILTER_PRI_AUTO)
3164                                 saved_spec->flags |=
3165                                         EFX_FILTER_FLAG_RX_OVER_AUTO;
3166                         saved_spec->priority = spec->priority;
3167                         saved_spec->flags &= EFX_FILTER_FLAG_RX_OVER_AUTO;
3168                         saved_spec->flags |= spec->flags;
3169                         saved_spec->rss_context = spec->rss_context;
3170                         saved_spec->dmaq_id = spec->dmaq_id;
3171                 }
3172         } else if (!replacing) {
3173                 kfree(saved_spec);
3174                 saved_spec = NULL;
3175         }
3176         efx_ef10_filter_set_entry(table, ins_index, saved_spec, priv_flags);
3177
3178         /* Remove and finalise entries for lower-priority multicast
3179          * recipients
3180          */
3181         if (is_mc_recip) {
3182                 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
3183                 unsigned int depth, i;
3184
3185                 memset(inbuf, 0, sizeof(inbuf));
3186
3187                 for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) {
3188                         if (!test_bit(depth, mc_rem_map))
3189                                 continue;
3190
3191                         i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
3192                         saved_spec = efx_ef10_filter_entry_spec(table, i);
3193                         priv_flags = efx_ef10_filter_entry_flags(table, i);
3194
3195                         if (rc == 0) {
3196                                 spin_unlock_bh(&efx->filter_lock);
3197                                 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3198                                                MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
3199                                 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
3200                                                table->entry[i].handle);
3201                                 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP,
3202                                                   inbuf, sizeof(inbuf),
3203                                                   NULL, 0, NULL);
3204                                 spin_lock_bh(&efx->filter_lock);
3205                         }
3206
3207                         if (rc == 0) {
3208                                 kfree(saved_spec);
3209                                 saved_spec = NULL;
3210                                 priv_flags = 0;
3211                         } else {
3212                                 priv_flags &= ~EFX_EF10_FILTER_FLAG_BUSY;
3213                         }
3214                         efx_ef10_filter_set_entry(table, i, saved_spec,
3215                                                   priv_flags);
3216                 }
3217         }
3218
3219         /* If successful, return the inserted filter ID */
3220         if (rc == 0)
3221                 rc = match_pri * HUNT_FILTER_TBL_ROWS + ins_index;
3222
3223         wake_up_all(&table->waitq);
3224 out_unlock:
3225         spin_unlock_bh(&efx->filter_lock);
3226         finish_wait(&table->waitq, &wait);
3227         return rc;
3228 }
3229
3230 static void efx_ef10_filter_update_rx_scatter(struct efx_nic *efx)
3231 {
3232         /* no need to do anything here on EF10 */
3233 }
3234
3235 /* Remove a filter.
3236  * If !by_index, remove by ID
3237  * If by_index, remove by index
3238  * Filter ID may come from userland and must be range-checked.
3239  */
3240 static int efx_ef10_filter_remove_internal(struct efx_nic *efx,
3241                                            unsigned int priority_mask,
3242                                            u32 filter_id, bool by_index)
3243 {
3244         unsigned int filter_idx = filter_id % HUNT_FILTER_TBL_ROWS;
3245         struct efx_ef10_filter_table *table = efx->filter_state;
3246         MCDI_DECLARE_BUF(inbuf,
3247                          MC_CMD_FILTER_OP_IN_HANDLE_OFST +
3248                          MC_CMD_FILTER_OP_IN_HANDLE_LEN);
3249         struct efx_filter_spec *spec;
3250         DEFINE_WAIT(wait);
3251         int rc;
3252
3253         /* Find the software table entry and mark it busy.  Don't
3254          * remove it yet; any attempt to update while we're waiting
3255          * for the firmware must find the busy entry.
3256          */
3257         for (;;) {
3258                 spin_lock_bh(&efx->filter_lock);
3259                 if (!(table->entry[filter_idx].spec &
3260                       EFX_EF10_FILTER_FLAG_BUSY))
3261                         break;
3262                 prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE);
3263                 spin_unlock_bh(&efx->filter_lock);
3264                 schedule();
3265         }
3266
3267         spec = efx_ef10_filter_entry_spec(table, filter_idx);
3268         if (!spec ||
3269             (!by_index &&
3270              efx_ef10_filter_rx_match_pri(table, spec->match_flags) !=
3271              filter_id / HUNT_FILTER_TBL_ROWS)) {
3272                 rc = -ENOENT;
3273                 goto out_unlock;
3274         }
3275
3276         if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO &&
3277             priority_mask == (1U << EFX_FILTER_PRI_AUTO)) {
3278                 /* Just remove flags */
3279                 spec->flags &= ~EFX_FILTER_FLAG_RX_OVER_AUTO;
3280                 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_AUTO_OLD;
3281                 rc = 0;
3282                 goto out_unlock;
3283         }
3284
3285         if (!(priority_mask & (1U << spec->priority))) {
3286                 rc = -ENOENT;
3287                 goto out_unlock;
3288         }
3289
3290         table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
3291         spin_unlock_bh(&efx->filter_lock);
3292
3293         if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO) {
3294                 /* Reset to an automatic filter */
3295
3296                 struct efx_filter_spec new_spec = *spec;
3297
3298                 new_spec.priority = EFX_FILTER_PRI_AUTO;
3299                 new_spec.flags = (EFX_FILTER_FLAG_RX |
3300                                   EFX_FILTER_FLAG_RX_RSS);
3301                 new_spec.dmaq_id = 0;
3302                 new_spec.rss_context = EFX_FILTER_RSS_CONTEXT_DEFAULT;
3303                 rc = efx_ef10_filter_push(efx, &new_spec,
3304                                           &table->entry[filter_idx].handle,
3305                                           true);
3306
3307                 spin_lock_bh(&efx->filter_lock);
3308                 if (rc == 0)
3309                         *spec = new_spec;
3310         } else {
3311                 /* Really remove the filter */
3312
3313                 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3314                                efx_ef10_filter_is_exclusive(spec) ?
3315                                MC_CMD_FILTER_OP_IN_OP_REMOVE :
3316                                MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
3317                 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
3318                                table->entry[filter_idx].handle);
3319                 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP,
3320                                   inbuf, sizeof(inbuf), NULL, 0, NULL);
3321
3322                 spin_lock_bh(&efx->filter_lock);
3323                 if (rc == 0) {
3324                         kfree(spec);
3325                         efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
3326                 }
3327         }
3328
3329         table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY;
3330         wake_up_all(&table->waitq);
3331 out_unlock:
3332         spin_unlock_bh(&efx->filter_lock);
3333         finish_wait(&table->waitq, &wait);
3334         return rc;
3335 }
3336
3337 static int efx_ef10_filter_remove_safe(struct efx_nic *efx,
3338                                        enum efx_filter_priority priority,
3339                                        u32 filter_id)
3340 {
3341         return efx_ef10_filter_remove_internal(efx, 1U << priority,
3342                                                filter_id, false);
3343 }
3344
3345 static u32 efx_ef10_filter_get_unsafe_id(struct efx_nic *efx, u32 filter_id)
3346 {
3347         return filter_id % HUNT_FILTER_TBL_ROWS;
3348 }
3349
3350 static int efx_ef10_filter_remove_unsafe(struct efx_nic *efx,
3351                                          enum efx_filter_priority priority,
3352                                          u32 filter_id)
3353 {
3354         return efx_ef10_filter_remove_internal(efx, 1U << priority,
3355                                                filter_id, true);
3356 }
3357
3358 static int efx_ef10_filter_get_safe(struct efx_nic *efx,
3359                                     enum efx_filter_priority priority,
3360                                     u32 filter_id, struct efx_filter_spec *spec)
3361 {
3362         unsigned int filter_idx = filter_id % HUNT_FILTER_TBL_ROWS;
3363         struct efx_ef10_filter_table *table = efx->filter_state;
3364         const struct efx_filter_spec *saved_spec;
3365         int rc;
3366
3367         spin_lock_bh(&efx->filter_lock);
3368         saved_spec = efx_ef10_filter_entry_spec(table, filter_idx);
3369         if (saved_spec && saved_spec->priority == priority &&
3370             efx_ef10_filter_rx_match_pri(table, saved_spec->match_flags) ==
3371             filter_id / HUNT_FILTER_TBL_ROWS) {
3372                 *spec = *saved_spec;
3373                 rc = 0;
3374         } else {
3375                 rc = -ENOENT;
3376         }
3377         spin_unlock_bh(&efx->filter_lock);
3378         return rc;
3379 }
3380
3381 static int efx_ef10_filter_clear_rx(struct efx_nic *efx,
3382                                      enum efx_filter_priority priority)
3383 {
3384         unsigned int priority_mask;
3385         unsigned int i;
3386         int rc;
3387
3388         priority_mask = (((1U << (priority + 1)) - 1) &
3389                          ~(1U << EFX_FILTER_PRI_AUTO));
3390
3391         for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) {
3392                 rc = efx_ef10_filter_remove_internal(efx, priority_mask,
3393                                                      i, true);
3394                 if (rc && rc != -ENOENT)
3395                         return rc;
3396         }
3397
3398         return 0;
3399 }
3400
3401 static u32 efx_ef10_filter_count_rx_used(struct efx_nic *efx,
3402                                          enum efx_filter_priority priority)
3403 {
3404         struct efx_ef10_filter_table *table = efx->filter_state;
3405         unsigned int filter_idx;
3406         s32 count = 0;
3407
3408         spin_lock_bh(&efx->filter_lock);
3409         for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
3410                 if (table->entry[filter_idx].spec &&
3411                     efx_ef10_filter_entry_spec(table, filter_idx)->priority ==
3412                     priority)
3413                         ++count;
3414         }
3415         spin_unlock_bh(&efx->filter_lock);
3416         return count;
3417 }
3418
3419 static u32 efx_ef10_filter_get_rx_id_limit(struct efx_nic *efx)
3420 {
3421         struct efx_ef10_filter_table *table = efx->filter_state;
3422
3423         return table->rx_match_count * HUNT_FILTER_TBL_ROWS;
3424 }
3425
3426 static s32 efx_ef10_filter_get_rx_ids(struct efx_nic *efx,
3427                                       enum efx_filter_priority priority,
3428                                       u32 *buf, u32 size)
3429 {
3430         struct efx_ef10_filter_table *table = efx->filter_state;
3431         struct efx_filter_spec *spec;
3432         unsigned int filter_idx;
3433         s32 count = 0;
3434
3435         spin_lock_bh(&efx->filter_lock);
3436         for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
3437                 spec = efx_ef10_filter_entry_spec(table, filter_idx);
3438                 if (spec && spec->priority == priority) {
3439                         if (count == size) {
3440                                 count = -EMSGSIZE;
3441                                 break;
3442                         }
3443                         buf[count++] = (efx_ef10_filter_rx_match_pri(
3444                                                 table, spec->match_flags) *
3445                                         HUNT_FILTER_TBL_ROWS +
3446                                         filter_idx);
3447                 }
3448         }
3449         spin_unlock_bh(&efx->filter_lock);
3450         return count;
3451 }
3452
3453 #ifdef CONFIG_RFS_ACCEL
3454
3455 static efx_mcdi_async_completer efx_ef10_filter_rfs_insert_complete;
3456
3457 static s32 efx_ef10_filter_rfs_insert(struct efx_nic *efx,
3458                                       struct efx_filter_spec *spec)
3459 {
3460         struct efx_ef10_filter_table *table = efx->filter_state;
3461         MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
3462         struct efx_filter_spec *saved_spec;
3463         unsigned int hash, i, depth = 1;
3464         bool replacing = false;
3465         int ins_index = -1;
3466         u64 cookie;
3467         s32 rc;
3468
3469         /* Must be an RX filter without RSS and not for a multicast
3470          * destination address (RFS only works for connected sockets).
3471          * These restrictions allow us to pass only a tiny amount of
3472          * data through to the completion function.
3473          */
3474         EFX_WARN_ON_PARANOID(spec->flags !=
3475                              (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_RX_SCATTER));
3476         EFX_WARN_ON_PARANOID(spec->priority != EFX_FILTER_PRI_HINT);
3477         EFX_WARN_ON_PARANOID(efx_filter_is_mc_recipient(spec));
3478
3479         hash = efx_ef10_filter_hash(spec);
3480
3481         spin_lock_bh(&efx->filter_lock);
3482
3483         /* Find any existing filter with the same match tuple or else
3484          * a free slot to insert at.  If an existing filter is busy,
3485          * we have to give up.
3486          */
3487         for (;;) {
3488                 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
3489                 saved_spec = efx_ef10_filter_entry_spec(table, i);
3490
3491                 if (!saved_spec) {
3492                         if (ins_index < 0)
3493                                 ins_index = i;
3494                 } else if (efx_ef10_filter_equal(spec, saved_spec)) {
3495                         if (table->entry[i].spec & EFX_EF10_FILTER_FLAG_BUSY) {
3496                                 rc = -EBUSY;
3497                                 goto fail_unlock;
3498                         }
3499                         if (spec->priority < saved_spec->priority) {
3500                                 rc = -EPERM;
3501                                 goto fail_unlock;
3502                         }
3503                         ins_index = i;
3504                         break;
3505                 }
3506
3507                 /* Once we reach the maximum search depth, use the
3508                  * first suitable slot or return -EBUSY if there was
3509                  * none
3510                  */
3511                 if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) {
3512                         if (ins_index < 0) {
3513                                 rc = -EBUSY;
3514                                 goto fail_unlock;
3515                         }
3516                         break;
3517                 }
3518
3519                 ++depth;
3520         }
3521
3522         /* Create a software table entry if necessary, and mark it
3523          * busy.  We might yet fail to insert, but any attempt to
3524          * insert a conflicting filter while we're waiting for the
3525          * firmware must find the busy entry.
3526          */
3527         saved_spec = efx_ef10_filter_entry_spec(table, ins_index);
3528         if (saved_spec) {
3529                 replacing = true;
3530         } else {
3531                 saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC);
3532                 if (!saved_spec) {
3533                         rc = -ENOMEM;
3534                         goto fail_unlock;
3535                 }
3536                 *saved_spec = *spec;
3537         }
3538         efx_ef10_filter_set_entry(table, ins_index, saved_spec,
3539                                   EFX_EF10_FILTER_FLAG_BUSY);
3540
3541         spin_unlock_bh(&efx->filter_lock);
3542
3543         /* Pack up the variables needed on completion */
3544         cookie = replacing << 31 | ins_index << 16 | spec->dmaq_id;
3545
3546         efx_ef10_filter_push_prep(efx, spec, inbuf,
3547                                   table->entry[ins_index].handle, replacing);
3548         efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
3549                            MC_CMD_FILTER_OP_OUT_LEN,
3550                            efx_ef10_filter_rfs_insert_complete, cookie);
3551
3552         return ins_index;
3553
3554 fail_unlock:
3555         spin_unlock_bh(&efx->filter_lock);
3556         return rc;
3557 }
3558
3559 static void
3560 efx_ef10_filter_rfs_insert_complete(struct efx_nic *efx, unsigned long cookie,
3561                                     int rc, efx_dword_t *outbuf,
3562                                     size_t outlen_actual)
3563 {
3564         struct efx_ef10_filter_table *table = efx->filter_state;
3565         unsigned int ins_index, dmaq_id;
3566         struct efx_filter_spec *spec;
3567         bool replacing;
3568
3569         /* Unpack the cookie */
3570         replacing = cookie >> 31;
3571         ins_index = (cookie >> 16) & (HUNT_FILTER_TBL_ROWS - 1);
3572         dmaq_id = cookie & 0xffff;
3573
3574         spin_lock_bh(&efx->filter_lock);
3575         spec = efx_ef10_filter_entry_spec(table, ins_index);
3576         if (rc == 0) {
3577                 table->entry[ins_index].handle =
3578                         MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE);
3579                 if (replacing)
3580                         spec->dmaq_id = dmaq_id;
3581         } else if (!replacing) {
3582                 kfree(spec);
3583                 spec = NULL;
3584         }
3585         efx_ef10_filter_set_entry(table, ins_index, spec, 0);
3586         spin_unlock_bh(&efx->filter_lock);
3587
3588         wake_up_all(&table->waitq);
3589 }
3590
3591 static void
3592 efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx,
3593                                     unsigned long filter_idx,
3594                                     int rc, efx_dword_t *outbuf,
3595                                     size_t outlen_actual);
3596
3597 static bool efx_ef10_filter_rfs_expire_one(struct efx_nic *efx, u32 flow_id,
3598                                            unsigned int filter_idx)
3599 {
3600         struct efx_ef10_filter_table *table = efx->filter_state;
3601         struct efx_filter_spec *spec =
3602                 efx_ef10_filter_entry_spec(table, filter_idx);
3603         MCDI_DECLARE_BUF(inbuf,
3604                          MC_CMD_FILTER_OP_IN_HANDLE_OFST +
3605                          MC_CMD_FILTER_OP_IN_HANDLE_LEN);
3606
3607         if (!spec ||
3608             (table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAG_BUSY) ||
3609             spec->priority != EFX_FILTER_PRI_HINT ||
3610             !rps_may_expire_flow(efx->net_dev, spec->dmaq_id,
3611                                  flow_id, filter_idx))
3612                 return false;
3613
3614         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3615                        MC_CMD_FILTER_OP_IN_OP_REMOVE);
3616         MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
3617                        table->entry[filter_idx].handle);
3618         if (efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf), 0,
3619                                efx_ef10_filter_rfs_expire_complete, filter_idx))
3620                 return false;
3621
3622         table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
3623         return true;
3624 }
3625
3626 static void
3627 efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx,
3628                                     unsigned long filter_idx,
3629                                     int rc, efx_dword_t *outbuf,
3630                                     size_t outlen_actual)
3631 {
3632         struct efx_ef10_filter_table *table = efx->filter_state;
3633         struct efx_filter_spec *spec =
3634                 efx_ef10_filter_entry_spec(table, filter_idx);
3635
3636         spin_lock_bh(&efx->filter_lock);
3637         if (rc == 0) {
3638                 kfree(spec);
3639                 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
3640         }
3641         table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY;
3642         wake_up_all(&table->waitq);
3643         spin_unlock_bh(&efx->filter_lock);
3644 }
3645
3646 #endif /* CONFIG_RFS_ACCEL */
3647
3648 static int efx_ef10_filter_match_flags_from_mcdi(u32 mcdi_flags)
3649 {
3650         int match_flags = 0;
3651
3652 #define MAP_FLAG(gen_flag, mcdi_field) {                                \
3653                 u32 old_mcdi_flags = mcdi_flags;                        \
3654                 mcdi_flags &= ~(1 << MC_CMD_FILTER_OP_IN_MATCH_ ##      \
3655                                 mcdi_field ## _LBN);                    \
3656                 if (mcdi_flags != old_mcdi_flags)                       \
3657                         match_flags |= EFX_FILTER_MATCH_ ## gen_flag;   \
3658         }
3659         MAP_FLAG(LOC_MAC_IG, UNKNOWN_UCAST_DST);
3660         MAP_FLAG(LOC_MAC_IG, UNKNOWN_MCAST_DST);
3661         MAP_FLAG(REM_HOST, SRC_IP);
3662         MAP_FLAG(LOC_HOST, DST_IP);
3663         MAP_FLAG(REM_MAC, SRC_MAC);
3664         MAP_FLAG(REM_PORT, SRC_PORT);
3665         MAP_FLAG(LOC_MAC, DST_MAC);
3666         MAP_FLAG(LOC_PORT, DST_PORT);
3667         MAP_FLAG(ETHER_TYPE, ETHER_TYPE);
3668         MAP_FLAG(INNER_VID, INNER_VLAN);
3669         MAP_FLAG(OUTER_VID, OUTER_VLAN);
3670         MAP_FLAG(IP_PROTO, IP_PROTO);
3671 #undef MAP_FLAG
3672
3673         /* Did we map them all? */
3674         if (mcdi_flags)
3675                 return -EINVAL;
3676
3677         return match_flags;
3678 }
3679
3680 static int efx_ef10_filter_table_probe(struct efx_nic *efx)
3681 {
3682         MCDI_DECLARE_BUF(inbuf, MC_CMD_GET_PARSER_DISP_INFO_IN_LEN);
3683         MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX);
3684         unsigned int pd_match_pri, pd_match_count;
3685         struct efx_ef10_filter_table *table;
3686         size_t outlen;
3687         int rc;
3688
3689         table = kzalloc(sizeof(*table), GFP_KERNEL);
3690         if (!table)
3691                 return -ENOMEM;
3692
3693         /* Find out which RX filter types are supported, and their priorities */
3694         MCDI_SET_DWORD(inbuf, GET_PARSER_DISP_INFO_IN_OP,
3695                        MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_RX_MATCHES);
3696         rc = efx_mcdi_rpc(efx, MC_CMD_GET_PARSER_DISP_INFO,
3697                           inbuf, sizeof(inbuf), outbuf, sizeof(outbuf),
3698                           &outlen);
3699         if (rc)
3700                 goto fail;
3701         pd_match_count = MCDI_VAR_ARRAY_LEN(
3702                 outlen, GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES);
3703         table->rx_match_count = 0;
3704
3705         for (pd_match_pri = 0; pd_match_pri < pd_match_count; pd_match_pri++) {
3706                 u32 mcdi_flags =
3707                         MCDI_ARRAY_DWORD(
3708                                 outbuf,
3709                                 GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES,
3710                                 pd_match_pri);
3711                 rc = efx_ef10_filter_match_flags_from_mcdi(mcdi_flags);
3712                 if (rc < 0) {
3713                         netif_dbg(efx, probe, efx->net_dev,
3714                                   "%s: fw flags %#x pri %u not supported in driver\n",
3715                                   __func__, mcdi_flags, pd_match_pri);
3716                 } else {
3717                         netif_dbg(efx, probe, efx->net_dev,
3718                                   "%s: fw flags %#x pri %u supported as driver flags %#x pri %u\n",
3719                                   __func__, mcdi_flags, pd_match_pri,
3720                                   rc, table->rx_match_count);
3721                         table->rx_match_flags[table->rx_match_count++] = rc;
3722                 }
3723         }
3724
3725         table->entry = vzalloc(HUNT_FILTER_TBL_ROWS * sizeof(*table->entry));
3726         if (!table->entry) {
3727                 rc = -ENOMEM;
3728                 goto fail;
3729         }
3730
3731         table->ucdef_id = EFX_EF10_FILTER_ID_INVALID;
3732         table->bcast_id = EFX_EF10_FILTER_ID_INVALID;
3733         table->mcdef_id = EFX_EF10_FILTER_ID_INVALID;
3734
3735         efx->filter_state = table;
3736         init_waitqueue_head(&table->waitq);
3737         return 0;
3738
3739 fail:
3740         kfree(table);
3741         return rc;
3742 }
3743
3744 /* Caller must hold efx->filter_sem for read if race against
3745  * efx_ef10_filter_table_remove() is possible
3746  */
3747 static void efx_ef10_filter_table_restore(struct efx_nic *efx)
3748 {
3749         struct efx_ef10_filter_table *table = efx->filter_state;
3750         struct efx_ef10_nic_data *nic_data = efx->nic_data;
3751         struct efx_filter_spec *spec;
3752         unsigned int filter_idx;
3753         bool failed = false;
3754         int rc;
3755
3756         WARN_ON(!rwsem_is_locked(&efx->filter_sem));
3757
3758         if (!nic_data->must_restore_filters)
3759                 return;
3760
3761         if (!table)
3762                 return;
3763
3764         spin_lock_bh(&efx->filter_lock);
3765
3766         for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
3767                 spec = efx_ef10_filter_entry_spec(table, filter_idx);
3768                 if (!spec)
3769                         continue;
3770
3771                 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
3772                 spin_unlock_bh(&efx->filter_lock);
3773
3774                 rc = efx_ef10_filter_push(efx, spec,
3775                                           &table->entry[filter_idx].handle,
3776                                           false);
3777                 if (rc)
3778                         failed = true;
3779
3780                 spin_lock_bh(&efx->filter_lock);
3781                 if (rc) {
3782                         kfree(spec);
3783                         efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
3784                 } else {
3785                         table->entry[filter_idx].spec &=
3786                                 ~EFX_EF10_FILTER_FLAG_BUSY;
3787                 }
3788         }
3789
3790         spin_unlock_bh(&efx->filter_lock);
3791
3792         if (failed)
3793                 netif_err(efx, hw, efx->net_dev,
3794                           "unable to restore all filters\n");
3795         else
3796                 nic_data->must_restore_filters = false;
3797 }
3798
3799 /* Caller must hold efx->filter_sem for write */
3800 static void efx_ef10_filter_table_remove(struct efx_nic *efx)
3801 {
3802         struct efx_ef10_filter_table *table = efx->filter_state;
3803         MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
3804         struct efx_filter_spec *spec;
3805         unsigned int filter_idx;
3806         int rc;
3807
3808         efx->filter_state = NULL;
3809         if (!table)
3810                 return;
3811
3812         for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
3813                 spec = efx_ef10_filter_entry_spec(table, filter_idx);
3814                 if (!spec)
3815                         continue;
3816
3817                 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3818                                efx_ef10_filter_is_exclusive(spec) ?
3819                                MC_CMD_FILTER_OP_IN_OP_REMOVE :
3820                                MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
3821                 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
3822                                table->entry[filter_idx].handle);
3823                 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
3824                                   NULL, 0, NULL);
3825                 if (rc)
3826                         netdev_WARN(efx->net_dev,
3827                                     "filter_idx=%#x handle=%#llx\n",
3828                                     filter_idx,
3829                                     table->entry[filter_idx].handle);
3830                 kfree(spec);
3831         }
3832
3833         vfree(table->entry);
3834         kfree(table);
3835 }
3836
3837 #define EFX_EF10_FILTER_DO_MARK_OLD(id) \
3838                 if (id != EFX_EF10_FILTER_ID_INVALID) { \
3839                         filter_idx = efx_ef10_filter_get_unsafe_id(efx, id); \
3840                         WARN_ON(!table->entry[filter_idx].spec); \
3841                         table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_AUTO_OLD; \
3842                 }
3843 static void efx_ef10_filter_mark_old(struct efx_nic *efx)
3844 {
3845         struct efx_ef10_filter_table *table = efx->filter_state;
3846         unsigned int filter_idx, i;
3847
3848         if (!table)
3849                 return;
3850
3851         /* Mark old filters that may need to be removed */
3852         spin_lock_bh(&efx->filter_lock);
3853         for (i = 0; i < table->dev_uc_count; i++)
3854                 EFX_EF10_FILTER_DO_MARK_OLD(table->dev_uc_list[i].id);
3855         for (i = 0; i < table->dev_mc_count; i++)
3856                 EFX_EF10_FILTER_DO_MARK_OLD(table->dev_mc_list[i].id);
3857         EFX_EF10_FILTER_DO_MARK_OLD(table->ucdef_id);
3858         EFX_EF10_FILTER_DO_MARK_OLD(table->bcast_id);
3859         EFX_EF10_FILTER_DO_MARK_OLD(table->mcdef_id);
3860         spin_unlock_bh(&efx->filter_lock);
3861 }
3862 #undef EFX_EF10_FILTER_DO_MARK_OLD
3863
3864 static void efx_ef10_filter_uc_addr_list(struct efx_nic *efx, bool *promisc)
3865 {
3866         struct efx_ef10_filter_table *table = efx->filter_state;
3867         struct net_device *net_dev = efx->net_dev;
3868         struct netdev_hw_addr *uc;
3869         int addr_count;
3870         unsigned int i;
3871
3872         table->ucdef_id = EFX_EF10_FILTER_ID_INVALID;
3873         addr_count = netdev_uc_count(net_dev);
3874         if (net_dev->flags & IFF_PROMISC)
3875                 *promisc = true;
3876         table->dev_uc_count = 1 + addr_count;
3877         ether_addr_copy(table->dev_uc_list[0].addr, net_dev->dev_addr);
3878         i = 1;
3879         netdev_for_each_uc_addr(uc, net_dev) {
3880                 if (i >= EFX_EF10_FILTER_DEV_UC_MAX) {
3881                         *promisc = true;
3882                         break;
3883                 }
3884                 ether_addr_copy(table->dev_uc_list[i].addr, uc->addr);
3885                 table->dev_uc_list[i].id = EFX_EF10_FILTER_ID_INVALID;
3886                 i++;
3887         }
3888 }
3889
3890 static void efx_ef10_filter_mc_addr_list(struct efx_nic *efx, bool *promisc)
3891 {
3892         struct efx_ef10_filter_table *table = efx->filter_state;
3893         struct net_device *net_dev = efx->net_dev;
3894         struct netdev_hw_addr *mc;
3895         unsigned int i, addr_count;
3896
3897         table->mcdef_id = EFX_EF10_FILTER_ID_INVALID;
3898         table->bcast_id = EFX_EF10_FILTER_ID_INVALID;
3899         if (net_dev->flags & (IFF_PROMISC | IFF_ALLMULTI))
3900                 *promisc = true;
3901
3902         addr_count = netdev_mc_count(net_dev);
3903         i = 0;
3904         netdev_for_each_mc_addr(mc, net_dev) {
3905                 if (i >= EFX_EF10_FILTER_DEV_MC_MAX) {
3906                         *promisc = true;
3907                         break;
3908                 }
3909                 ether_addr_copy(table->dev_mc_list[i].addr, mc->addr);
3910                 table->dev_mc_list[i].id = EFX_EF10_FILTER_ID_INVALID;
3911                 i++;
3912         }
3913
3914         table->dev_mc_count = i;
3915 }
3916
3917 static int efx_ef10_filter_insert_addr_list(struct efx_nic *efx,
3918                                              bool multicast, bool rollback)
3919 {
3920         struct efx_ef10_filter_table *table = efx->filter_state;
3921         struct efx_ef10_dev_addr *addr_list;
3922         struct efx_filter_spec spec;
3923         u8 baddr[ETH_ALEN];
3924         unsigned int i, j;
3925         int addr_count;
3926         int rc;
3927
3928         if (multicast) {
3929                 addr_list = table->dev_mc_list;
3930                 addr_count = table->dev_mc_count;
3931         } else {
3932                 addr_list = table->dev_uc_list;
3933                 addr_count = table->dev_uc_count;
3934         }
3935
3936         /* Insert/renew filters */
3937         for (i = 0; i < addr_count; i++) {
3938                 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO,
3939                                    EFX_FILTER_FLAG_RX_RSS,
3940                                    0);
3941                 efx_filter_set_eth_local(&spec, EFX_FILTER_VID_UNSPEC,
3942                                          addr_list[i].addr);
3943                 rc = efx_ef10_filter_insert(efx, &spec, true);
3944                 if (rc < 0) {
3945                         if (rollback) {
3946                                 netif_info(efx, drv, efx->net_dev,
3947                                            "efx_ef10_filter_insert failed rc=%d\n",
3948                                            rc);
3949                                 /* Fall back to promiscuous */
3950                                 for (j = 0; j < i; j++) {
3951                                         if (addr_list[j].id == EFX_EF10_FILTER_ID_INVALID)
3952                                                 continue;
3953                                         efx_ef10_filter_remove_unsafe(
3954                                                 efx, EFX_FILTER_PRI_AUTO,
3955                                                 addr_list[j].id);
3956                                         addr_list[j].id = EFX_EF10_FILTER_ID_INVALID;
3957                                 }
3958                                 return rc;
3959                         } else {
3960                                 /* mark as not inserted, and carry on */
3961                                 rc = EFX_EF10_FILTER_ID_INVALID;
3962                         }
3963                 }
3964                 addr_list[i].id = efx_ef10_filter_get_unsafe_id(efx, rc);
3965         }
3966
3967         if (multicast && rollback) {
3968                 /* Also need an Ethernet broadcast filter */
3969                 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO,
3970                                    EFX_FILTER_FLAG_RX_RSS,
3971                                    0);
3972                 eth_broadcast_addr(baddr);
3973                 efx_filter_set_eth_local(&spec, EFX_FILTER_VID_UNSPEC, baddr);
3974                 rc = efx_ef10_filter_insert(efx, &spec, true);
3975                 if (rc < 0) {
3976                         netif_warn(efx, drv, efx->net_dev,
3977                                    "Broadcast filter insert failed rc=%d\n", rc);
3978                         /* Fall back to promiscuous */
3979                         for (j = 0; j < i; j++) {
3980                                 if (addr_list[j].id == EFX_EF10_FILTER_ID_INVALID)
3981                                         continue;
3982                                 efx_ef10_filter_remove_unsafe(
3983                                         efx, EFX_FILTER_PRI_AUTO,
3984                                         addr_list[j].id);
3985                                 addr_list[j].id = EFX_EF10_FILTER_ID_INVALID;
3986                         }
3987                         return rc;
3988                 } else {
3989                         table->bcast_id = efx_ef10_filter_get_unsafe_id(efx, rc);
3990                 }
3991         }
3992
3993         return 0;
3994 }
3995
3996 static int efx_ef10_filter_insert_def(struct efx_nic *efx, bool multicast,
3997                                       bool rollback)
3998 {
3999         struct efx_ef10_filter_table *table = efx->filter_state;
4000         struct efx_ef10_nic_data *nic_data = efx->nic_data;
4001         struct efx_filter_spec spec;
4002         u8 baddr[ETH_ALEN];
4003         int rc;
4004
4005         efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO,
4006                            EFX_FILTER_FLAG_RX_RSS,
4007                            0);
4008
4009         if (multicast)
4010                 efx_filter_set_mc_def(&spec);
4011         else
4012                 efx_filter_set_uc_def(&spec);
4013
4014         rc = efx_ef10_filter_insert(efx, &spec, true);
4015         if (rc < 0) {
4016                 netif_warn(efx, drv, efx->net_dev,
4017                            "%scast mismatch filter insert failed rc=%d\n",
4018                            multicast ? "Multi" : "Uni", rc);
4019         } else if (multicast) {
4020                 table->mcdef_id = efx_ef10_filter_get_unsafe_id(efx, rc);
4021                 if (!nic_data->workaround_26807) {
4022                         /* Also need an Ethernet broadcast filter */
4023                         efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO,
4024                                            EFX_FILTER_FLAG_RX_RSS,
4025                                            0);
4026                         eth_broadcast_addr(baddr);
4027                         efx_filter_set_eth_local(&spec, EFX_FILTER_VID_UNSPEC,
4028                                                  baddr);
4029                         rc = efx_ef10_filter_insert(efx, &spec, true);
4030                         if (rc < 0) {
4031                                 netif_warn(efx, drv, efx->net_dev,
4032                                            "Broadcast filter insert failed rc=%d\n",
4033                                            rc);
4034                                 if (rollback) {
4035                                         /* Roll back the mc_def filter */
4036                                         efx_ef10_filter_remove_unsafe(
4037                                                         efx, EFX_FILTER_PRI_AUTO,
4038                                                         table->mcdef_id);
4039                                         table->mcdef_id = EFX_EF10_FILTER_ID_INVALID;
4040                                         return rc;
4041                                 }
4042                         } else {
4043                                 table->bcast_id = efx_ef10_filter_get_unsafe_id(efx, rc);
4044                         }
4045                 }
4046                 rc = 0;
4047         } else {
4048                 table->ucdef_id = rc;
4049                 rc = 0;
4050         }
4051         return rc;
4052 }
4053
4054 /* Remove filters that weren't renewed.  Since nothing else changes the AUTO_OLD
4055  * flag or removes these filters, we don't need to hold the filter_lock while
4056  * scanning for these filters.
4057  */
4058 static void efx_ef10_filter_remove_old(struct efx_nic *efx)
4059 {
4060         struct efx_ef10_filter_table *table = efx->filter_state;
4061         bool remove_failed = false;
4062         int i;
4063
4064         for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) {
4065                 if (ACCESS_ONCE(table->entry[i].spec) &
4066                     EFX_EF10_FILTER_FLAG_AUTO_OLD) {
4067                         if (efx_ef10_filter_remove_internal(
4068                                     efx, 1U << EFX_FILTER_PRI_AUTO,
4069                                     i, true) < 0)
4070                                 remove_failed = true;
4071                 }
4072         }
4073         WARN_ON(remove_failed);
4074 }
4075
4076 static int efx_ef10_vport_set_mac_address(struct efx_nic *efx)
4077 {
4078         struct efx_ef10_nic_data *nic_data = efx->nic_data;
4079         u8 mac_old[ETH_ALEN];
4080         int rc, rc2;
4081
4082         /* Only reconfigure a PF-created vport */
4083         if (is_zero_ether_addr(nic_data->vport_mac))
4084                 return 0;
4085
4086         efx_device_detach_sync(efx);
4087         efx_net_stop(efx->net_dev);
4088         down_write(&efx->filter_sem);
4089         efx_ef10_filter_table_remove(efx);
4090         up_write(&efx->filter_sem);
4091
4092         rc = efx_ef10_vadaptor_free(efx, nic_data->vport_id);
4093         if (rc)
4094                 goto restore_filters;
4095
4096         ether_addr_copy(mac_old, nic_data->vport_mac);
4097         rc = efx_ef10_vport_del_mac(efx, nic_data->vport_id,
4098                                     nic_data->vport_mac);
4099         if (rc)
4100                 goto restore_vadaptor;
4101
4102         rc = efx_ef10_vport_add_mac(efx, nic_data->vport_id,
4103                                     efx->net_dev->dev_addr);
4104         if (!rc) {
4105                 ether_addr_copy(nic_data->vport_mac, efx->net_dev->dev_addr);
4106         } else {
4107                 rc2 = efx_ef10_vport_add_mac(efx, nic_data->vport_id, mac_old);
4108                 if (rc2) {
4109                         /* Failed to add original MAC, so clear vport_mac */
4110                         eth_zero_addr(nic_data->vport_mac);
4111                         goto reset_nic;
4112                 }
4113         }
4114
4115 restore_vadaptor:
4116         rc2 = efx_ef10_vadaptor_alloc(efx, nic_data->vport_id);
4117         if (rc2)
4118                 goto reset_nic;
4119 restore_filters:
4120         down_write(&efx->filter_sem);
4121         rc2 = efx_ef10_filter_table_probe(efx);
4122         up_write(&efx->filter_sem);
4123         if (rc2)
4124                 goto reset_nic;
4125
4126         rc2 = efx_net_open(efx->net_dev);
4127         if (rc2)
4128                 goto reset_nic;
4129
4130         netif_device_attach(efx->net_dev);
4131
4132         return rc;
4133
4134 reset_nic:
4135         netif_err(efx, drv, efx->net_dev,
4136                   "Failed to restore when changing MAC address - scheduling reset\n");
4137         efx_schedule_reset(efx, RESET_TYPE_DATAPATH);
4138
4139         return rc ? rc : rc2;
4140 }
4141
4142 /* Caller must hold efx->filter_sem for read if race against
4143  * efx_ef10_filter_table_remove() is possible
4144  */
4145 static void efx_ef10_filter_sync_rx_mode(struct efx_nic *efx)
4146 {
4147         struct efx_ef10_filter_table *table = efx->filter_state;
4148         struct efx_ef10_nic_data *nic_data = efx->nic_data;
4149         struct net_device *net_dev = efx->net_dev;
4150         bool uc_promisc = false, mc_promisc = false;
4151
4152         if (!efx_dev_registered(efx))
4153                 return;
4154
4155         if (!table)
4156                 return;
4157
4158         efx_ef10_filter_mark_old(efx);
4159
4160         /* Copy/convert the address lists; add the primary station
4161          * address and broadcast address
4162          */
4163         netif_addr_lock_bh(net_dev);
4164         efx_ef10_filter_uc_addr_list(efx, &uc_promisc);
4165         efx_ef10_filter_mc_addr_list(efx, &mc_promisc);
4166         netif_addr_unlock_bh(net_dev);
4167
4168         /* Insert/renew unicast filters */
4169         if (uc_promisc) {
4170                 efx_ef10_filter_insert_def(efx, false, false);
4171                 efx_ef10_filter_insert_addr_list(efx, false, false);
4172         } else {
4173                 /* If any of the filters failed to insert, fall back to
4174                  * promiscuous mode - add in the uc_def filter.  But keep
4175                  * our individual unicast filters.
4176                  */
4177                 if (efx_ef10_filter_insert_addr_list(efx, false, false))
4178                         efx_ef10_filter_insert_def(efx, false, false);
4179         }
4180
4181         /* Insert/renew multicast filters */
4182         /* If changing promiscuous state with cascaded multicast filters, remove
4183          * old filters first, so that packets are dropped rather than duplicated
4184          */
4185         if (nic_data->workaround_26807 && efx->mc_promisc != mc_promisc)
4186                 efx_ef10_filter_remove_old(efx);
4187         if (mc_promisc) {
4188                 if (nic_data->workaround_26807) {
4189                         /* If we failed to insert promiscuous filters, rollback
4190                          * and fall back to individual multicast filters
4191                          */
4192                         if (efx_ef10_filter_insert_def(efx, true, true)) {
4193                                 /* Changing promisc state, so remove old filters */
4194                                 efx_ef10_filter_remove_old(efx);
4195                                 efx_ef10_filter_insert_addr_list(efx, true, false);
4196                         }
4197                 } else {
4198                         /* If we failed to insert promiscuous filters, don't
4199                          * rollback.  Regardless, also insert the mc_list
4200                          */
4201                         efx_ef10_filter_insert_def(efx, true, false);
4202                         efx_ef10_filter_insert_addr_list(efx, true, false);
4203                 }
4204         } else {
4205                 /* If any filters failed to insert, rollback and fall back to
4206                  * promiscuous mode - mc_def filter and maybe broadcast.  If
4207                  * that fails, roll back again and insert as many of our
4208                  * individual multicast filters as we can.
4209                  */
4210                 if (efx_ef10_filter_insert_addr_list(efx, true, true)) {
4211                         /* Changing promisc state, so remove old filters */
4212                         if (nic_data->workaround_26807)
4213                                 efx_ef10_filter_remove_old(efx);
4214                         if (efx_ef10_filter_insert_def(efx, true, true))
4215                                 efx_ef10_filter_insert_addr_list(efx, true, false);
4216                 }
4217         }
4218
4219         efx_ef10_filter_remove_old(efx);
4220         efx->mc_promisc = mc_promisc;
4221 }
4222
4223 static int efx_ef10_set_mac_address(struct efx_nic *efx)
4224 {
4225         MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_SET_MAC_IN_LEN);
4226         struct efx_ef10_nic_data *nic_data = efx->nic_data;
4227         bool was_enabled = efx->port_enabled;
4228         int rc;
4229
4230         efx_device_detach_sync(efx);
4231         efx_net_stop(efx->net_dev);
4232         down_write(&efx->filter_sem);
4233         efx_ef10_filter_table_remove(efx);
4234
4235         ether_addr_copy(MCDI_PTR(inbuf, VADAPTOR_SET_MAC_IN_MACADDR),
4236                         efx->net_dev->dev_addr);
4237         MCDI_SET_DWORD(inbuf, VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID,
4238                        nic_data->vport_id);
4239         rc = efx_mcdi_rpc_quiet(efx, MC_CMD_VADAPTOR_SET_MAC, inbuf,
4240                                 sizeof(inbuf), NULL, 0, NULL);
4241
4242         efx_ef10_filter_table_probe(efx);
4243         up_write(&efx->filter_sem);
4244         if (was_enabled)
4245                 efx_net_open(efx->net_dev);
4246         netif_device_attach(efx->net_dev);
4247
4248 #ifdef CONFIG_SFC_SRIOV
4249         if (efx->pci_dev->is_virtfn && efx->pci_dev->physfn) {
4250                 struct pci_dev *pci_dev_pf = efx->pci_dev->physfn;
4251
4252                 if (rc == -EPERM) {
4253                         struct efx_nic *efx_pf;
4254
4255                         /* Switch to PF and change MAC address on vport */
4256                         efx_pf = pci_get_drvdata(pci_dev_pf);
4257
4258                         rc = efx_ef10_sriov_set_vf_mac(efx_pf,
4259                                                        nic_data->vf_index,
4260                                                        efx->net_dev->dev_addr);
4261                 } else if (!rc) {
4262                         struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
4263                         struct efx_ef10_nic_data *nic_data = efx_pf->nic_data;
4264                         unsigned int i;
4265
4266                         /* MAC address successfully changed by VF (with MAC
4267                          * spoofing) so update the parent PF if possible.
4268                          */
4269                         for (i = 0; i < efx_pf->vf_count; ++i) {
4270                                 struct ef10_vf *vf = nic_data->vf + i;
4271
4272                                 if (vf->efx == efx) {
4273                                         ether_addr_copy(vf->mac,
4274                                                         efx->net_dev->dev_addr);
4275                                         return 0;
4276                                 }
4277                         }
4278                 }
4279         } else
4280 #endif
4281         if (rc == -EPERM) {
4282                 netif_err(efx, drv, efx->net_dev,
4283                           "Cannot change MAC address; use sfboot to enable"
4284                           " mac-spoofing on this interface\n");
4285         } else if (rc == -ENOSYS && !efx_ef10_is_vf(efx)) {
4286                 /* If the active MCFW does not support MC_CMD_VADAPTOR_SET_MAC
4287                  * fall-back to the method of changing the MAC address on the
4288                  * vport.  This only applies to PFs because such versions of
4289                  * MCFW do not support VFs.
4290                  */
4291                 rc = efx_ef10_vport_set_mac_address(efx);
4292         } else {
4293                 efx_mcdi_display_error(efx, MC_CMD_VADAPTOR_SET_MAC,
4294                                        sizeof(inbuf), NULL, 0, rc);
4295         }
4296
4297         return rc;
4298 }
4299
4300 static int efx_ef10_mac_reconfigure(struct efx_nic *efx)
4301 {
4302         efx_ef10_filter_sync_rx_mode(efx);
4303
4304         return efx_mcdi_set_mac(efx);
4305 }
4306
4307 static int efx_ef10_mac_reconfigure_vf(struct efx_nic *efx)
4308 {
4309         efx_ef10_filter_sync_rx_mode(efx);
4310
4311         return 0;
4312 }
4313
4314 static int efx_ef10_start_bist(struct efx_nic *efx, u32 bist_type)
4315 {
4316         MCDI_DECLARE_BUF(inbuf, MC_CMD_START_BIST_IN_LEN);
4317
4318         MCDI_SET_DWORD(inbuf, START_BIST_IN_TYPE, bist_type);
4319         return efx_mcdi_rpc(efx, MC_CMD_START_BIST, inbuf, sizeof(inbuf),
4320                             NULL, 0, NULL);
4321 }
4322
4323 /* MC BISTs follow a different poll mechanism to phy BISTs.
4324  * The BIST is done in the poll handler on the MC, and the MCDI command
4325  * will block until the BIST is done.
4326  */
4327 static int efx_ef10_poll_bist(struct efx_nic *efx)
4328 {
4329         int rc;
4330         MCDI_DECLARE_BUF(outbuf, MC_CMD_POLL_BIST_OUT_LEN);
4331         size_t outlen;
4332         u32 result;
4333
4334         rc = efx_mcdi_rpc(efx, MC_CMD_POLL_BIST, NULL, 0,
4335                            outbuf, sizeof(outbuf), &outlen);
4336         if (rc != 0)
4337                 return rc;
4338
4339         if (outlen < MC_CMD_POLL_BIST_OUT_LEN)
4340                 return -EIO;
4341
4342         result = MCDI_DWORD(outbuf, POLL_BIST_OUT_RESULT);
4343         switch (result) {
4344         case MC_CMD_POLL_BIST_PASSED:
4345                 netif_dbg(efx, hw, efx->net_dev, "BIST passed.\n");
4346                 return 0;
4347         case MC_CMD_POLL_BIST_TIMEOUT:
4348                 netif_err(efx, hw, efx->net_dev, "BIST timed out\n");
4349                 return -EIO;
4350         case MC_CMD_POLL_BIST_FAILED:
4351                 netif_err(efx, hw, efx->net_dev, "BIST failed.\n");
4352                 return -EIO;
4353         default:
4354                 netif_err(efx, hw, efx->net_dev,
4355                           "BIST returned unknown result %u", result);
4356                 return -EIO;
4357         }
4358 }
4359
4360 static int efx_ef10_run_bist(struct efx_nic *efx, u32 bist_type)
4361 {
4362         int rc;
4363
4364         netif_dbg(efx, drv, efx->net_dev, "starting BIST type %u\n", bist_type);
4365
4366         rc = efx_ef10_start_bist(efx, bist_type);
4367         if (rc != 0)
4368                 return rc;
4369
4370         return efx_ef10_poll_bist(efx);
4371 }
4372
4373 static int
4374 efx_ef10_test_chip(struct efx_nic *efx, struct efx_self_tests *tests)
4375 {
4376         int rc, rc2;
4377
4378         efx_reset_down(efx, RESET_TYPE_WORLD);
4379
4380         rc = efx_mcdi_rpc(efx, MC_CMD_ENABLE_OFFLINE_BIST,
4381                           NULL, 0, NULL, 0, NULL);
4382         if (rc != 0)
4383                 goto out;
4384
4385         tests->memory = efx_ef10_run_bist(efx, MC_CMD_MC_MEM_BIST) ? -1 : 1;
4386         tests->registers = efx_ef10_run_bist(efx, MC_CMD_REG_BIST) ? -1 : 1;
4387
4388         rc = efx_mcdi_reset(efx, RESET_TYPE_WORLD);
4389
4390 out:
4391         if (rc == -EPERM)
4392                 rc = 0;
4393         rc2 = efx_reset_up(efx, RESET_TYPE_WORLD, rc == 0);
4394         return rc ? rc : rc2;
4395 }
4396
4397 #ifdef CONFIG_SFC_MTD
4398
4399 struct efx_ef10_nvram_type_info {
4400         u16 type, type_mask;
4401         u8 port;
4402         const char *name;
4403 };
4404
4405 static const struct efx_ef10_nvram_type_info efx_ef10_nvram_types[] = {
4406         { NVRAM_PARTITION_TYPE_MC_FIRMWARE,        0,    0, "sfc_mcfw" },
4407         { NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP, 0,    0, "sfc_mcfw_backup" },
4408         { NVRAM_PARTITION_TYPE_EXPANSION_ROM,      0,    0, "sfc_exp_rom" },
4409         { NVRAM_PARTITION_TYPE_STATIC_CONFIG,      0,    0, "sfc_static_cfg" },
4410         { NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG,     0,    0, "sfc_dynamic_cfg" },
4411         { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0, 0,   0, "sfc_exp_rom_cfg" },
4412         { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1, 0,   1, "sfc_exp_rom_cfg" },
4413         { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2, 0,   2, "sfc_exp_rom_cfg" },
4414         { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3, 0,   3, "sfc_exp_rom_cfg" },
4415         { NVRAM_PARTITION_TYPE_LICENSE,            0,    0, "sfc_license" },
4416         { NVRAM_PARTITION_TYPE_PHY_MIN,            0xff, 0, "sfc_phy_fw" },
4417 };
4418
4419 static int efx_ef10_mtd_probe_partition(struct efx_nic *efx,
4420                                         struct efx_mcdi_mtd_partition *part,
4421                                         unsigned int type)
4422 {
4423         MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_METADATA_IN_LEN);
4424         MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_METADATA_OUT_LENMAX);
4425         const struct efx_ef10_nvram_type_info *info;
4426         size_t size, erase_size, outlen;
4427         bool protected;
4428         int rc;
4429
4430         for (info = efx_ef10_nvram_types; ; info++) {
4431                 if (info ==
4432                     efx_ef10_nvram_types + ARRAY_SIZE(efx_ef10_nvram_types))
4433                         return -ENODEV;
4434                 if ((type & ~info->type_mask) == info->type)
4435                         break;
4436         }
4437         if (info->port != efx_port_num(efx))
4438                 return -ENODEV;
4439
4440         rc = efx_mcdi_nvram_info(efx, type, &size, &erase_size, &protected);
4441         if (rc)
4442                 return rc;
4443         if (protected)
4444                 return -ENODEV; /* hide it */
4445
4446         part->nvram_type = type;
4447
4448         MCDI_SET_DWORD(inbuf, NVRAM_METADATA_IN_TYPE, type);
4449         rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_METADATA, inbuf, sizeof(inbuf),
4450                           outbuf, sizeof(outbuf), &outlen);
4451         if (rc)
4452                 return rc;
4453         if (outlen < MC_CMD_NVRAM_METADATA_OUT_LENMIN)
4454                 return -EIO;
4455         if (MCDI_DWORD(outbuf, NVRAM_METADATA_OUT_FLAGS) &
4456             (1 << MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN))
4457                 part->fw_subtype = MCDI_DWORD(outbuf,
4458                                               NVRAM_METADATA_OUT_SUBTYPE);
4459
4460         part->common.dev_type_name = "EF10 NVRAM manager";
4461         part->common.type_name = info->name;
4462
4463         part->common.mtd.type = MTD_NORFLASH;
4464         part->common.mtd.flags = MTD_CAP_NORFLASH;
4465         part->common.mtd.size = size;
4466         part->common.mtd.erasesize = erase_size;
4467
4468         return 0;
4469 }
4470
4471 static int efx_ef10_mtd_probe(struct efx_nic *efx)
4472 {
4473         MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX);
4474         struct efx_mcdi_mtd_partition *parts;
4475         size_t outlen, n_parts_total, i, n_parts;
4476         unsigned int type;
4477         int rc;
4478
4479         ASSERT_RTNL();
4480
4481         BUILD_BUG_ON(MC_CMD_NVRAM_PARTITIONS_IN_LEN != 0);
4482         rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_PARTITIONS, NULL, 0,
4483                           outbuf, sizeof(outbuf), &outlen);
4484         if (rc)
4485                 return rc;
4486         if (outlen < MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN)
4487                 return -EIO;
4488
4489         n_parts_total = MCDI_DWORD(outbuf, NVRAM_PARTITIONS_OUT_NUM_PARTITIONS);
4490         if (n_parts_total >
4491             MCDI_VAR_ARRAY_LEN(outlen, NVRAM_PARTITIONS_OUT_TYPE_ID))
4492                 return -EIO;
4493
4494         parts = kcalloc(n_parts_total, sizeof(*parts), GFP_KERNEL);
4495         if (!parts)
4496                 return -ENOMEM;
4497
4498         n_parts = 0;
4499         for (i = 0; i < n_parts_total; i++) {
4500                 type = MCDI_ARRAY_DWORD(outbuf, NVRAM_PARTITIONS_OUT_TYPE_ID,
4501                                         i);
4502                 rc = efx_ef10_mtd_probe_partition(efx, &parts[n_parts], type);
4503                 if (rc == 0)
4504                         n_parts++;
4505                 else if (rc != -ENODEV)
4506                         goto fail;
4507         }
4508
4509         rc = efx_mtd_add(efx, &parts[0].common, n_parts, sizeof(*parts));
4510 fail:
4511         if (rc)
4512                 kfree(parts);
4513         return rc;
4514 }
4515
4516 #endif /* CONFIG_SFC_MTD */
4517
4518 static void efx_ef10_ptp_write_host_time(struct efx_nic *efx, u32 host_time)
4519 {
4520         _efx_writed(efx, cpu_to_le32(host_time), ER_DZ_MC_DB_LWRD);
4521 }
4522
4523 static void efx_ef10_ptp_write_host_time_vf(struct efx_nic *efx,
4524                                             u32 host_time) {}
4525
4526 static int efx_ef10_rx_enable_timestamping(struct efx_channel *channel,
4527                                            bool temp)
4528 {
4529         MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_LEN);
4530         int rc;
4531
4532         if (channel->sync_events_state == SYNC_EVENTS_REQUESTED ||
4533             channel->sync_events_state == SYNC_EVENTS_VALID ||
4534             (temp && channel->sync_events_state == SYNC_EVENTS_DISABLED))
4535                 return 0;
4536         channel->sync_events_state = SYNC_EVENTS_REQUESTED;
4537
4538         MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE);
4539         MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0);
4540         MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE,
4541                        channel->channel);
4542
4543         rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP,
4544                           inbuf, sizeof(inbuf), NULL, 0, NULL);
4545
4546         if (rc != 0)
4547                 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT :
4548                                                     SYNC_EVENTS_DISABLED;
4549
4550         return rc;
4551 }
4552
4553 static int efx_ef10_rx_disable_timestamping(struct efx_channel *channel,
4554                                             bool temp)
4555 {
4556         MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_LEN);
4557         int rc;
4558
4559         if (channel->sync_events_state == SYNC_EVENTS_DISABLED ||
4560             (temp && channel->sync_events_state == SYNC_EVENTS_QUIESCENT))
4561                 return 0;
4562         if (channel->sync_events_state == SYNC_EVENTS_QUIESCENT) {
4563                 channel->sync_events_state = SYNC_EVENTS_DISABLED;
4564                 return 0;
4565         }
4566         channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT :
4567                                             SYNC_EVENTS_DISABLED;
4568
4569         MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE);
4570         MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0);
4571         MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL,
4572                        MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE);
4573         MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE,
4574                        channel->channel);
4575
4576         rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP,
4577                           inbuf, sizeof(inbuf), NULL, 0, NULL);
4578
4579         return rc;
4580 }
4581
4582 static int efx_ef10_ptp_set_ts_sync_events(struct efx_nic *efx, bool en,
4583                                            bool temp)
4584 {
4585         int (*set)(struct efx_channel *channel, bool temp);
4586         struct efx_channel *channel;
4587
4588         set = en ?
4589               efx_ef10_rx_enable_timestamping :
4590               efx_ef10_rx_disable_timestamping;
4591
4592         efx_for_each_channel(channel, efx) {
4593                 int rc = set(channel, temp);
4594                 if (en && rc != 0) {
4595                         efx_ef10_ptp_set_ts_sync_events(efx, false, temp);
4596                         return rc;
4597                 }
4598         }
4599
4600         return 0;
4601 }
4602
4603 static int efx_ef10_ptp_set_ts_config_vf(struct efx_nic *efx,
4604                                          struct hwtstamp_config *init)
4605 {
4606         return -EOPNOTSUPP;
4607 }
4608
4609 static int efx_ef10_ptp_set_ts_config(struct efx_nic *efx,
4610                                       struct hwtstamp_config *init)
4611 {
4612         int rc;
4613
4614         switch (init->rx_filter) {
4615         case HWTSTAMP_FILTER_NONE:
4616                 efx_ef10_ptp_set_ts_sync_events(efx, false, false);
4617                 /* if TX timestamping is still requested then leave PTP on */
4618                 return efx_ptp_change_mode(efx,
4619                                            init->tx_type != HWTSTAMP_TX_OFF, 0);
4620         case HWTSTAMP_FILTER_ALL:
4621         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
4622         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
4623         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
4624         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
4625         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
4626         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
4627         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
4628         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
4629         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
4630         case HWTSTAMP_FILTER_PTP_V2_EVENT:
4631         case HWTSTAMP_FILTER_PTP_V2_SYNC:
4632         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
4633                 init->rx_filter = HWTSTAMP_FILTER_ALL;
4634                 rc = efx_ptp_change_mode(efx, true, 0);
4635                 if (!rc)
4636                         rc = efx_ef10_ptp_set_ts_sync_events(efx, true, false);
4637                 if (rc)
4638                         efx_ptp_change_mode(efx, false, 0);
4639                 return rc;
4640         default:
4641                 return -ERANGE;
4642         }
4643 }
4644
4645 const struct efx_nic_type efx_hunt_a0_vf_nic_type = {
4646         .is_vf = true,
4647         .mem_bar = EFX_MEM_VF_BAR,
4648         .mem_map_size = efx_ef10_mem_map_size,
4649         .probe = efx_ef10_probe_vf,
4650         .remove = efx_ef10_remove,
4651         .dimension_resources = efx_ef10_dimension_resources,
4652         .init = efx_ef10_init_nic,
4653         .fini = efx_port_dummy_op_void,
4654         .map_reset_reason = efx_ef10_map_reset_reason,
4655         .map_reset_flags = efx_ef10_map_reset_flags,
4656         .reset = efx_ef10_reset,
4657         .probe_port = efx_mcdi_port_probe,
4658         .remove_port = efx_mcdi_port_remove,
4659         .fini_dmaq = efx_ef10_fini_dmaq,
4660         .prepare_flr = efx_ef10_prepare_flr,
4661         .finish_flr = efx_port_dummy_op_void,
4662         .describe_stats = efx_ef10_describe_stats,
4663         .update_stats = efx_ef10_update_stats_vf,
4664         .start_stats = efx_port_dummy_op_void,
4665         .pull_stats = efx_port_dummy_op_void,
4666         .stop_stats = efx_port_dummy_op_void,
4667         .set_id_led = efx_mcdi_set_id_led,
4668         .push_irq_moderation = efx_ef10_push_irq_moderation,
4669         .reconfigure_mac = efx_ef10_mac_reconfigure_vf,
4670         .check_mac_fault = efx_mcdi_mac_check_fault,
4671         .reconfigure_port = efx_mcdi_port_reconfigure,
4672         .get_wol = efx_ef10_get_wol_vf,
4673         .set_wol = efx_ef10_set_wol_vf,
4674         .resume_wol = efx_port_dummy_op_void,
4675         .mcdi_request = efx_ef10_mcdi_request,
4676         .mcdi_poll_response = efx_ef10_mcdi_poll_response,
4677         .mcdi_read_response = efx_ef10_mcdi_read_response,
4678         .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot,
4679         .mcdi_reboot_detected = efx_ef10_mcdi_reboot_detected,
4680         .irq_enable_master = efx_port_dummy_op_void,
4681         .irq_test_generate = efx_ef10_irq_test_generate,
4682         .irq_disable_non_ev = efx_port_dummy_op_void,
4683         .irq_handle_msi = efx_ef10_msi_interrupt,
4684         .irq_handle_legacy = efx_ef10_legacy_interrupt,
4685         .tx_probe = efx_ef10_tx_probe,
4686         .tx_init = efx_ef10_tx_init,
4687         .tx_remove = efx_ef10_tx_remove,
4688         .tx_write = efx_ef10_tx_write,
4689         .rx_push_rss_config = efx_ef10_vf_rx_push_rss_config,
4690         .rx_probe = efx_ef10_rx_probe,
4691         .rx_init = efx_ef10_rx_init,
4692         .rx_remove = efx_ef10_rx_remove,
4693         .rx_write = efx_ef10_rx_write,
4694         .rx_defer_refill = efx_ef10_rx_defer_refill,
4695         .ev_probe = efx_ef10_ev_probe,
4696         .ev_init = efx_ef10_ev_init,
4697         .ev_fini = efx_ef10_ev_fini,
4698         .ev_remove = efx_ef10_ev_remove,
4699         .ev_process = efx_ef10_ev_process,
4700         .ev_read_ack = efx_ef10_ev_read_ack,
4701         .ev_test_generate = efx_ef10_ev_test_generate,
4702         .filter_table_probe = efx_ef10_filter_table_probe,
4703         .filter_table_restore = efx_ef10_filter_table_restore,
4704         .filter_table_remove = efx_ef10_filter_table_remove,
4705         .filter_update_rx_scatter = efx_ef10_filter_update_rx_scatter,
4706         .filter_insert = efx_ef10_filter_insert,
4707         .filter_remove_safe = efx_ef10_filter_remove_safe,
4708         .filter_get_safe = efx_ef10_filter_get_safe,
4709         .filter_clear_rx = efx_ef10_filter_clear_rx,
4710         .filter_count_rx_used = efx_ef10_filter_count_rx_used,
4711         .filter_get_rx_id_limit = efx_ef10_filter_get_rx_id_limit,
4712         .filter_get_rx_ids = efx_ef10_filter_get_rx_ids,
4713 #ifdef CONFIG_RFS_ACCEL
4714         .filter_rfs_insert = efx_ef10_filter_rfs_insert,
4715         .filter_rfs_expire_one = efx_ef10_filter_rfs_expire_one,
4716 #endif
4717 #ifdef CONFIG_SFC_MTD
4718         .mtd_probe = efx_port_dummy_op_int,
4719 #endif
4720         .ptp_write_host_time = efx_ef10_ptp_write_host_time_vf,
4721         .ptp_set_ts_config = efx_ef10_ptp_set_ts_config_vf,
4722 #ifdef CONFIG_SFC_SRIOV
4723         .vswitching_probe = efx_ef10_vswitching_probe_vf,
4724         .vswitching_restore = efx_ef10_vswitching_restore_vf,
4725         .vswitching_remove = efx_ef10_vswitching_remove_vf,
4726         .sriov_get_phys_port_id = efx_ef10_sriov_get_phys_port_id,
4727 #endif
4728         .get_mac_address = efx_ef10_get_mac_address_vf,
4729         .set_mac_address = efx_ef10_set_mac_address,
4730
4731         .revision = EFX_REV_HUNT_A0,
4732         .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH),
4733         .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE,
4734         .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST,
4735         .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST,
4736         .can_rx_scatter = true,
4737         .always_rx_scatter = true,
4738         .max_interrupt_mode = EFX_INT_MODE_MSIX,
4739         .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH,
4740         .offload_features = (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
4741                              NETIF_F_RXHASH | NETIF_F_NTUPLE),
4742         .mcdi_max_ver = 2,
4743         .max_rx_ip_filters = HUNT_FILTER_TBL_ROWS,
4744         .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE |
4745                             1 << HWTSTAMP_FILTER_ALL,
4746 };
4747
4748 const struct efx_nic_type efx_hunt_a0_nic_type = {
4749         .is_vf = false,
4750         .mem_bar = EFX_MEM_BAR,
4751         .mem_map_size = efx_ef10_mem_map_size,
4752         .probe = efx_ef10_probe_pf,
4753         .remove = efx_ef10_remove,
4754         .dimension_resources = efx_ef10_dimension_resources,
4755         .init = efx_ef10_init_nic,
4756         .fini = efx_port_dummy_op_void,
4757         .map_reset_reason = efx_ef10_map_reset_reason,
4758         .map_reset_flags = efx_ef10_map_reset_flags,
4759         .reset = efx_ef10_reset,
4760         .probe_port = efx_mcdi_port_probe,
4761         .remove_port = efx_mcdi_port_remove,
4762         .fini_dmaq = efx_ef10_fini_dmaq,
4763         .prepare_flr = efx_ef10_prepare_flr,
4764         .finish_flr = efx_port_dummy_op_void,
4765         .describe_stats = efx_ef10_describe_stats,
4766         .update_stats = efx_ef10_update_stats_pf,
4767         .start_stats = efx_mcdi_mac_start_stats,
4768         .pull_stats = efx_mcdi_mac_pull_stats,
4769         .stop_stats = efx_mcdi_mac_stop_stats,
4770         .set_id_led = efx_mcdi_set_id_led,
4771         .push_irq_moderation = efx_ef10_push_irq_moderation,
4772         .reconfigure_mac = efx_ef10_mac_reconfigure,
4773         .check_mac_fault = efx_mcdi_mac_check_fault,
4774         .reconfigure_port = efx_mcdi_port_reconfigure,
4775         .get_wol = efx_ef10_get_wol,
4776         .set_wol = efx_ef10_set_wol,
4777         .resume_wol = efx_port_dummy_op_void,
4778         .test_chip = efx_ef10_test_chip,
4779         .test_nvram = efx_mcdi_nvram_test_all,
4780         .mcdi_request = efx_ef10_mcdi_request,
4781         .mcdi_poll_response = efx_ef10_mcdi_poll_response,
4782         .mcdi_read_response = efx_ef10_mcdi_read_response,
4783         .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot,
4784         .mcdi_reboot_detected = efx_ef10_mcdi_reboot_detected,
4785         .irq_enable_master = efx_port_dummy_op_void,
4786         .irq_test_generate = efx_ef10_irq_test_generate,
4787         .irq_disable_non_ev = efx_port_dummy_op_void,
4788         .irq_handle_msi = efx_ef10_msi_interrupt,
4789         .irq_handle_legacy = efx_ef10_legacy_interrupt,
4790         .tx_probe = efx_ef10_tx_probe,
4791         .tx_init = efx_ef10_tx_init,
4792         .tx_remove = efx_ef10_tx_remove,
4793         .tx_write = efx_ef10_tx_write,
4794         .rx_push_rss_config = efx_ef10_pf_rx_push_rss_config,
4795         .rx_probe = efx_ef10_rx_probe,
4796         .rx_init = efx_ef10_rx_init,
4797         .rx_remove = efx_ef10_rx_remove,
4798         .rx_write = efx_ef10_rx_write,
4799         .rx_defer_refill = efx_ef10_rx_defer_refill,
4800         .ev_probe = efx_ef10_ev_probe,
4801         .ev_init = efx_ef10_ev_init,
4802         .ev_fini = efx_ef10_ev_fini,
4803         .ev_remove = efx_ef10_ev_remove,
4804         .ev_process = efx_ef10_ev_process,
4805         .ev_read_ack = efx_ef10_ev_read_ack,
4806         .ev_test_generate = efx_ef10_ev_test_generate,
4807         .filter_table_probe = efx_ef10_filter_table_probe,
4808         .filter_table_restore = efx_ef10_filter_table_restore,
4809         .filter_table_remove = efx_ef10_filter_table_remove,
4810         .filter_update_rx_scatter = efx_ef10_filter_update_rx_scatter,
4811         .filter_insert = efx_ef10_filter_insert,
4812         .filter_remove_safe = efx_ef10_filter_remove_safe,
4813         .filter_get_safe = efx_ef10_filter_get_safe,
4814         .filter_clear_rx = efx_ef10_filter_clear_rx,
4815         .filter_count_rx_used = efx_ef10_filter_count_rx_used,
4816         .filter_get_rx_id_limit = efx_ef10_filter_get_rx_id_limit,
4817         .filter_get_rx_ids = efx_ef10_filter_get_rx_ids,
4818 #ifdef CONFIG_RFS_ACCEL
4819         .filter_rfs_insert = efx_ef10_filter_rfs_insert,
4820         .filter_rfs_expire_one = efx_ef10_filter_rfs_expire_one,
4821 #endif
4822 #ifdef CONFIG_SFC_MTD
4823         .mtd_probe = efx_ef10_mtd_probe,
4824         .mtd_rename = efx_mcdi_mtd_rename,
4825         .mtd_read = efx_mcdi_mtd_read,
4826         .mtd_erase = efx_mcdi_mtd_erase,
4827         .mtd_write = efx_mcdi_mtd_write,
4828         .mtd_sync = efx_mcdi_mtd_sync,
4829 #endif
4830         .ptp_write_host_time = efx_ef10_ptp_write_host_time,
4831         .ptp_set_ts_sync_events = efx_ef10_ptp_set_ts_sync_events,
4832         .ptp_set_ts_config = efx_ef10_ptp_set_ts_config,
4833 #ifdef CONFIG_SFC_SRIOV
4834         .sriov_configure = efx_ef10_sriov_configure,
4835         .sriov_init = efx_ef10_sriov_init,
4836         .sriov_fini = efx_ef10_sriov_fini,
4837         .sriov_wanted = efx_ef10_sriov_wanted,
4838         .sriov_reset = efx_ef10_sriov_reset,
4839         .sriov_flr = efx_ef10_sriov_flr,
4840         .sriov_set_vf_mac = efx_ef10_sriov_set_vf_mac,
4841         .sriov_set_vf_vlan = efx_ef10_sriov_set_vf_vlan,
4842         .sriov_set_vf_spoofchk = efx_ef10_sriov_set_vf_spoofchk,
4843         .sriov_get_vf_config = efx_ef10_sriov_get_vf_config,
4844         .sriov_set_vf_link_state = efx_ef10_sriov_set_vf_link_state,
4845         .vswitching_probe = efx_ef10_vswitching_probe_pf,
4846         .vswitching_restore = efx_ef10_vswitching_restore_pf,
4847         .vswitching_remove = efx_ef10_vswitching_remove_pf,
4848 #endif
4849         .get_mac_address = efx_ef10_get_mac_address_pf,
4850         .set_mac_address = efx_ef10_set_mac_address,
4851
4852         .revision = EFX_REV_HUNT_A0,
4853         .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH),
4854         .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE,
4855         .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST,
4856         .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST,
4857         .can_rx_scatter = true,
4858         .always_rx_scatter = true,
4859         .max_interrupt_mode = EFX_INT_MODE_MSIX,
4860         .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH,
4861         .offload_features = (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
4862                              NETIF_F_RXHASH | NETIF_F_NTUPLE),
4863         .mcdi_max_ver = 2,
4864         .max_rx_ip_filters = HUNT_FILTER_TBL_ROWS,
4865         .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE |
4866                             1 << HWTSTAMP_FILTER_ALL,
4867 };