1 /****************************************************************************
2 * Driver for Solarflare network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2005-2013 Solarflare Communications Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
11 /* Common definitions for all Efx net driver code */
13 #ifndef EFX_NET_DRIVER_H
14 #define EFX_NET_DRIVER_H
16 #include <linux/netdevice.h>
17 #include <linux/etherdevice.h>
18 #include <linux/ethtool.h>
19 #include <linux/if_vlan.h>
20 #include <linux/timer.h>
21 #include <linux/mdio.h>
22 #include <linux/list.h>
23 #include <linux/pci.h>
24 #include <linux/device.h>
25 #include <linux/highmem.h>
26 #include <linux/workqueue.h>
27 #include <linux/mutex.h>
28 #include <linux/vmalloc.h>
29 #include <linux/i2c.h>
30 #include <linux/mtd/mtd.h>
31 #include <net/busy_poll.h>
37 /**************************************************************************
41 **************************************************************************/
43 #define EFX_DRIVER_VERSION "4.0"
46 #define EFX_BUG_ON_PARANOID(x) BUG_ON(x)
47 #define EFX_WARN_ON_PARANOID(x) WARN_ON(x)
49 #define EFX_BUG_ON_PARANOID(x) do {} while (0)
50 #define EFX_WARN_ON_PARANOID(x) do {} while (0)
53 /**************************************************************************
57 **************************************************************************/
59 #define EFX_MAX_CHANNELS 32U
60 #define EFX_MAX_RX_QUEUES EFX_MAX_CHANNELS
61 #define EFX_EXTRA_CHANNEL_IOV 0
62 #define EFX_EXTRA_CHANNEL_PTP 1
63 #define EFX_MAX_EXTRA_CHANNELS 2U
65 /* Checksum generation is a per-queue option in hardware, so each
66 * queue visible to the networking core is backed by two hardware TX
68 #define EFX_MAX_TX_TC 2
69 #define EFX_MAX_CORE_TX_QUEUES (EFX_MAX_TX_TC * EFX_MAX_CHANNELS)
70 #define EFX_TXQ_TYPE_OFFLOAD 1 /* flag */
71 #define EFX_TXQ_TYPE_HIGHPRI 2 /* flag */
72 #define EFX_TXQ_TYPES 4
73 #define EFX_MAX_TX_QUEUES (EFX_TXQ_TYPES * EFX_MAX_CHANNELS)
75 /* Maximum possible MTU the driver supports */
76 #define EFX_MAX_MTU (9 * 1024)
78 /* Size of an RX scatter buffer. Small enough to pack 2 into a 4K page,
79 * and should be a multiple of the cache line size.
81 #define EFX_RX_USR_BUF_SIZE (2048 - 256)
83 /* If possible, we should ensure cache line alignment at start and end
84 * of every buffer. Otherwise, we just need to ensure 4-byte
85 * alignment of the network header.
88 #define EFX_RX_BUF_ALIGNMENT L1_CACHE_BYTES
90 #define EFX_RX_BUF_ALIGNMENT 4
93 /* Forward declare Precision Time Protocol (PTP) support structure. */
95 struct hwtstamp_config;
97 struct efx_self_tests;
100 * struct efx_buffer - A general-purpose DMA buffer
101 * @addr: host base address of the buffer
102 * @dma_addr: DMA base address of the buffer
103 * @len: Buffer length, in bytes
105 * The NIC uses these buffers for its interrupt status registers and
115 * struct efx_special_buffer - DMA buffer entered into buffer table
116 * @buf: Standard &struct efx_buffer
117 * @index: Buffer index within controller;s buffer table
118 * @entries: Number of buffer table entries
120 * The NIC has a buffer table that maps buffers of size %EFX_BUF_SIZE.
121 * Event and descriptor rings are addressed via one or more buffer
122 * table entries (and so can be physically non-contiguous, although we
123 * currently do not take advantage of that). On Falcon and Siena we
124 * have to take care of allocating and initialising the entries
125 * ourselves. On later hardware this is managed by the firmware and
126 * @index and @entries are left as 0.
128 struct efx_special_buffer {
129 struct efx_buffer buf;
131 unsigned int entries;
135 * struct efx_tx_buffer - buffer state for a TX descriptor
136 * @skb: When @flags & %EFX_TX_BUF_SKB, the associated socket buffer to be
137 * freed when descriptor completes
138 * @heap_buf: When @flags & %EFX_TX_BUF_HEAP, the associated heap buffer to be
139 * freed when descriptor completes.
140 * @option: When @flags & %EFX_TX_BUF_OPTION, a NIC-specific option descriptor.
141 * @dma_addr: DMA address of the fragment.
142 * @flags: Flags for allocation and DMA mapping type
143 * @len: Length of this fragment.
144 * This field is zero when the queue slot is empty.
145 * @unmap_len: Length of this fragment to unmap
146 * @dma_offset: Offset of @dma_addr from the address of the backing DMA mapping.
147 * Only valid if @unmap_len != 0.
149 struct efx_tx_buffer {
151 const struct sk_buff *skb;
158 unsigned short flags;
160 unsigned short unmap_len;
161 unsigned short dma_offset;
163 #define EFX_TX_BUF_CONT 1 /* not last descriptor of packet */
164 #define EFX_TX_BUF_SKB 2 /* buffer is last part of skb */
165 #define EFX_TX_BUF_HEAP 4 /* buffer was allocated with kmalloc() */
166 #define EFX_TX_BUF_MAP_SINGLE 8 /* buffer was mapped with dma_map_single() */
167 #define EFX_TX_BUF_OPTION 0x10 /* empty buffer for option descriptor */
170 * struct efx_tx_queue - An Efx TX queue
172 * This is a ring buffer of TX fragments.
173 * Since the TX completion path always executes on the same
174 * CPU and the xmit path can operate on different CPUs,
175 * performance is increased by ensuring that the completion
176 * path and the xmit path operate on different cache lines.
177 * This is particularly important if the xmit path is always
178 * executing on one CPU which is different from the completion
179 * path. There is also a cache line for members which are
180 * read but not written on the fast path.
182 * @efx: The associated Efx NIC
183 * @queue: DMA queue number
184 * @channel: The associated channel
185 * @core_txq: The networking core TX queue structure
186 * @buffer: The software buffer ring
187 * @tsoh_page: Array of pages of TSO header buffers
188 * @txd: The hardware descriptor ring
189 * @ptr_mask: The size of the ring minus 1.
190 * @piobuf: PIO buffer region for this TX queue (shared with its partner).
191 * Size of the region is efx_piobuf_size.
192 * @piobuf_offset: Buffer offset to be specified in PIO descriptors
193 * @initialised: Has hardware queue been initialised?
194 * @read_count: Current read pointer.
195 * This is the number of buffers that have been removed from both rings.
196 * @old_write_count: The value of @write_count when last checked.
197 * This is here for performance reasons. The xmit path will
198 * only get the up-to-date value of @write_count if this
199 * variable indicates that the queue is empty. This is to
200 * avoid cache-line ping-pong between the xmit path and the
202 * @merge_events: Number of TX merged completion events
203 * @insert_count: Current insert pointer
204 * This is the number of buffers that have been added to the
206 * @write_count: Current write pointer
207 * This is the number of buffers that have been added to the
209 * @old_read_count: The value of read_count when last checked.
210 * This is here for performance reasons. The xmit path will
211 * only get the up-to-date value of read_count if this
212 * variable indicates that the queue is full. This is to
213 * avoid cache-line ping-pong between the xmit path and the
215 * @tso_bursts: Number of times TSO xmit invoked by kernel
216 * @tso_long_headers: Number of packets with headers too long for standard
218 * @tso_packets: Number of packets via the TSO xmit path
219 * @pushes: Number of times the TX push feature has been used
220 * @pio_packets: Number of times the TX PIO feature has been used
221 * @empty_read_count: If the completion path has seen the queue as empty
222 * and the transmission path has not yet checked this, the value of
223 * @read_count bitwise-added to %EFX_EMPTY_COUNT_VALID; otherwise 0.
225 struct efx_tx_queue {
226 /* Members which don't change on the fast path */
227 struct efx_nic *efx ____cacheline_aligned_in_smp;
229 struct efx_channel *channel;
230 struct netdev_queue *core_txq;
231 struct efx_tx_buffer *buffer;
232 struct efx_buffer *tsoh_page;
233 struct efx_special_buffer txd;
234 unsigned int ptr_mask;
235 void __iomem *piobuf;
236 unsigned int piobuf_offset;
239 /* Members used mainly on the completion path */
240 unsigned int read_count ____cacheline_aligned_in_smp;
241 unsigned int old_write_count;
242 unsigned int merge_events;
244 /* Members used only on the xmit path */
245 unsigned int insert_count ____cacheline_aligned_in_smp;
246 unsigned int write_count;
247 unsigned int old_read_count;
248 unsigned int tso_bursts;
249 unsigned int tso_long_headers;
250 unsigned int tso_packets;
252 unsigned int pio_packets;
253 /* Statistics to supplement MAC stats */
254 unsigned long tx_packets;
256 /* Members shared between paths and sometimes updated */
257 unsigned int empty_read_count ____cacheline_aligned_in_smp;
258 #define EFX_EMPTY_COUNT_VALID 0x80000000
259 atomic_t flush_outstanding;
263 * struct efx_rx_buffer - An Efx RX data buffer
264 * @dma_addr: DMA base address of the buffer
265 * @page: The associated page buffer.
266 * Will be %NULL if the buffer slot is currently free.
267 * @page_offset: If pending: offset in @page of DMA base address.
268 * If completed: offset in @page of Ethernet header.
269 * @len: If pending: length for DMA descriptor.
270 * If completed: received length, excluding hash prefix.
271 * @flags: Flags for buffer and packet state. These are only set on the
272 * first buffer of a scattered packet.
274 struct efx_rx_buffer {
281 #define EFX_RX_BUF_LAST_IN_PAGE 0x0001
282 #define EFX_RX_PKT_CSUMMED 0x0002
283 #define EFX_RX_PKT_DISCARD 0x0004
284 #define EFX_RX_PKT_TCP 0x0040
285 #define EFX_RX_PKT_PREFIX_LEN 0x0080 /* length is in prefix only */
288 * struct efx_rx_page_state - Page-based rx buffer state
290 * Inserted at the start of every page allocated for receive buffers.
291 * Used to facilitate sharing dma mappings between recycled rx buffers
292 * and those passed up to the kernel.
294 * @dma_addr: The dma address of this page.
296 struct efx_rx_page_state {
299 unsigned int __pad[0] ____cacheline_aligned;
303 * struct efx_rx_queue - An Efx RX queue
304 * @efx: The associated Efx NIC
305 * @core_index: Index of network core RX queue. Will be >= 0 iff this
306 * is associated with a real RX queue.
307 * @buffer: The software buffer ring
308 * @rxd: The hardware descriptor ring
309 * @ptr_mask: The size of the ring minus 1.
310 * @refill_enabled: Enable refill whenever fill level is low
311 * @flush_pending: Set when a RX flush is pending. Has the same lifetime as
312 * @rxq_flush_pending.
313 * @added_count: Number of buffers added to the receive queue.
314 * @notified_count: Number of buffers given to NIC (<= @added_count).
315 * @removed_count: Number of buffers removed from the receive queue.
316 * @scatter_n: Used by NIC specific receive code.
317 * @scatter_len: Used by NIC specific receive code.
318 * @page_ring: The ring to store DMA mapped pages for reuse.
319 * @page_add: Counter to calculate the write pointer for the recycle ring.
320 * @page_remove: Counter to calculate the read pointer for the recycle ring.
321 * @page_recycle_count: The number of pages that have been recycled.
322 * @page_recycle_failed: The number of pages that couldn't be recycled because
323 * the kernel still held a reference to them.
324 * @page_recycle_full: The number of pages that were released because the
325 * recycle ring was full.
326 * @page_ptr_mask: The number of pages in the RX recycle ring minus 1.
327 * @max_fill: RX descriptor maximum fill level (<= ring size)
328 * @fast_fill_trigger: RX descriptor fill level that will trigger a fast fill
330 * @min_fill: RX descriptor minimum non-zero fill level.
331 * This records the minimum fill level observed when a ring
332 * refill was triggered.
333 * @recycle_count: RX buffer recycle counter.
334 * @slow_fill: Timer used to defer efx_nic_generate_fill_event().
336 struct efx_rx_queue {
339 struct efx_rx_buffer *buffer;
340 struct efx_special_buffer rxd;
341 unsigned int ptr_mask;
345 unsigned int added_count;
346 unsigned int notified_count;
347 unsigned int removed_count;
348 unsigned int scatter_n;
349 unsigned int scatter_len;
350 struct page **page_ring;
351 unsigned int page_add;
352 unsigned int page_remove;
353 unsigned int page_recycle_count;
354 unsigned int page_recycle_failed;
355 unsigned int page_recycle_full;
356 unsigned int page_ptr_mask;
357 unsigned int max_fill;
358 unsigned int fast_fill_trigger;
359 unsigned int min_fill;
360 unsigned int min_overfill;
361 unsigned int recycle_count;
362 struct timer_list slow_fill;
363 unsigned int slow_fill_count;
364 /* Statistics to supplement MAC stats */
365 unsigned long rx_packets;
368 enum efx_sync_events_state {
369 SYNC_EVENTS_DISABLED = 0,
370 SYNC_EVENTS_QUIESCENT,
371 SYNC_EVENTS_REQUESTED,
376 * struct efx_channel - An Efx channel
378 * A channel comprises an event queue, at least one TX queue, at least
379 * one RX queue, and an associated tasklet for processing the event
382 * @efx: Associated Efx NIC
383 * @channel: Channel instance number
384 * @type: Channel type definition
385 * @eventq_init: Event queue initialised flag
386 * @enabled: Channel enabled indicator
387 * @irq: IRQ number (MSI and MSI-X only)
388 * @irq_moderation: IRQ moderation value (in hardware ticks)
389 * @napi_dev: Net device used with NAPI
390 * @napi_str: NAPI control structure
391 * @state: state for NAPI vs busy polling
392 * @state_lock: lock protecting @state
393 * @eventq: Event queue buffer
394 * @eventq_mask: Event queue pointer mask
395 * @eventq_read_ptr: Event queue read pointer
396 * @event_test_cpu: Last CPU to handle interrupt or test event for this channel
397 * @irq_count: Number of IRQs since last adaptive moderation decision
398 * @irq_mod_score: IRQ moderation score
399 * @n_rx_tobe_disc: Count of RX_TOBE_DISC errors
400 * @n_rx_ip_hdr_chksum_err: Count of RX IP header checksum errors
401 * @n_rx_tcp_udp_chksum_err: Count of RX TCP and UDP checksum errors
402 * @n_rx_mcast_mismatch: Count of unmatched multicast frames
403 * @n_rx_frm_trunc: Count of RX_FRM_TRUNC errors
404 * @n_rx_overlength: Count of RX_OVERLENGTH errors
405 * @n_skbuff_leaks: Count of skbuffs leaked due to RX overrun
406 * @n_rx_nodesc_trunc: Number of RX packets truncated and then dropped due to
407 * lack of descriptors
408 * @n_rx_merge_events: Number of RX merged completion events
409 * @n_rx_merge_packets: Number of RX packets completed by merged events
410 * @rx_pkt_n_frags: Number of fragments in next packet to be delivered by
411 * __efx_rx_packet(), or zero if there is none
412 * @rx_pkt_index: Ring index of first buffer for next packet to be delivered
413 * by __efx_rx_packet(), if @rx_pkt_n_frags != 0
414 * @rx_queue: RX queue for this channel
415 * @tx_queue: TX queues for this channel
416 * @sync_events_state: Current state of sync events on this channel
417 * @sync_timestamp_major: Major part of the last ptp sync event
418 * @sync_timestamp_minor: Minor part of the last ptp sync event
423 const struct efx_channel_type *type;
427 unsigned int irq_moderation;
428 struct net_device *napi_dev;
429 struct napi_struct napi_str;
430 #ifdef CONFIG_NET_RX_BUSY_POLL
432 spinlock_t state_lock;
433 #define EFX_CHANNEL_STATE_IDLE 0
434 #define EFX_CHANNEL_STATE_NAPI (1 << 0) /* NAPI owns this channel */
435 #define EFX_CHANNEL_STATE_POLL (1 << 1) /* poll owns this channel */
436 #define EFX_CHANNEL_STATE_DISABLED (1 << 2) /* channel is disabled */
437 #define EFX_CHANNEL_STATE_NAPI_YIELD (1 << 3) /* NAPI yielded this channel */
438 #define EFX_CHANNEL_STATE_POLL_YIELD (1 << 4) /* poll yielded this channel */
439 #define EFX_CHANNEL_OWNED \
440 (EFX_CHANNEL_STATE_NAPI | EFX_CHANNEL_STATE_POLL)
441 #define EFX_CHANNEL_LOCKED \
442 (EFX_CHANNEL_OWNED | EFX_CHANNEL_STATE_DISABLED)
443 #define EFX_CHANNEL_USER_PEND \
444 (EFX_CHANNEL_STATE_POLL | EFX_CHANNEL_STATE_POLL_YIELD)
445 #endif /* CONFIG_NET_RX_BUSY_POLL */
446 struct efx_special_buffer eventq;
447 unsigned int eventq_mask;
448 unsigned int eventq_read_ptr;
451 unsigned int irq_count;
452 unsigned int irq_mod_score;
453 #ifdef CONFIG_RFS_ACCEL
454 unsigned int rfs_filters_added;
457 unsigned n_rx_tobe_disc;
458 unsigned n_rx_ip_hdr_chksum_err;
459 unsigned n_rx_tcp_udp_chksum_err;
460 unsigned n_rx_mcast_mismatch;
461 unsigned n_rx_frm_trunc;
462 unsigned n_rx_overlength;
463 unsigned n_skbuff_leaks;
464 unsigned int n_rx_nodesc_trunc;
465 unsigned int n_rx_merge_events;
466 unsigned int n_rx_merge_packets;
468 unsigned int rx_pkt_n_frags;
469 unsigned int rx_pkt_index;
471 struct efx_rx_queue rx_queue;
472 struct efx_tx_queue tx_queue[EFX_TXQ_TYPES];
474 enum efx_sync_events_state sync_events_state;
475 u32 sync_timestamp_major;
476 u32 sync_timestamp_minor;
479 #ifdef CONFIG_NET_RX_BUSY_POLL
480 static inline void efx_channel_init_lock(struct efx_channel *channel)
482 spin_lock_init(&channel->state_lock);
485 /* Called from the device poll routine to get ownership of a channel. */
486 static inline bool efx_channel_lock_napi(struct efx_channel *channel)
490 spin_lock_bh(&channel->state_lock);
491 if (channel->state & EFX_CHANNEL_LOCKED) {
492 WARN_ON(channel->state & EFX_CHANNEL_STATE_NAPI);
493 channel->state |= EFX_CHANNEL_STATE_NAPI_YIELD;
496 /* we don't care if someone yielded */
497 channel->state = EFX_CHANNEL_STATE_NAPI;
499 spin_unlock_bh(&channel->state_lock);
503 static inline void efx_channel_unlock_napi(struct efx_channel *channel)
505 spin_lock_bh(&channel->state_lock);
506 WARN_ON(channel->state &
507 (EFX_CHANNEL_STATE_POLL | EFX_CHANNEL_STATE_NAPI_YIELD));
509 channel->state &= EFX_CHANNEL_STATE_DISABLED;
510 spin_unlock_bh(&channel->state_lock);
513 /* Called from efx_busy_poll(). */
514 static inline bool efx_channel_lock_poll(struct efx_channel *channel)
518 spin_lock_bh(&channel->state_lock);
519 if ((channel->state & EFX_CHANNEL_LOCKED)) {
520 channel->state |= EFX_CHANNEL_STATE_POLL_YIELD;
523 /* preserve yield marks */
524 channel->state |= EFX_CHANNEL_STATE_POLL;
526 spin_unlock_bh(&channel->state_lock);
530 /* Returns true if NAPI tried to get the channel while it was locked. */
531 static inline void efx_channel_unlock_poll(struct efx_channel *channel)
533 spin_lock_bh(&channel->state_lock);
534 WARN_ON(channel->state & EFX_CHANNEL_STATE_NAPI);
536 /* will reset state to idle, unless channel is disabled */
537 channel->state &= EFX_CHANNEL_STATE_DISABLED;
538 spin_unlock_bh(&channel->state_lock);
541 /* True if a socket is polling, even if it did not get the lock. */
542 static inline bool efx_channel_busy_polling(struct efx_channel *channel)
544 WARN_ON(!(channel->state & EFX_CHANNEL_OWNED));
545 return channel->state & EFX_CHANNEL_USER_PEND;
548 static inline void efx_channel_enable(struct efx_channel *channel)
550 spin_lock_bh(&channel->state_lock);
551 channel->state = EFX_CHANNEL_STATE_IDLE;
552 spin_unlock_bh(&channel->state_lock);
555 /* False if the channel is currently owned. */
556 static inline bool efx_channel_disable(struct efx_channel *channel)
560 spin_lock_bh(&channel->state_lock);
561 if (channel->state & EFX_CHANNEL_OWNED)
563 channel->state |= EFX_CHANNEL_STATE_DISABLED;
564 spin_unlock_bh(&channel->state_lock);
569 #else /* CONFIG_NET_RX_BUSY_POLL */
571 static inline void efx_channel_init_lock(struct efx_channel *channel)
575 static inline bool efx_channel_lock_napi(struct efx_channel *channel)
580 static inline void efx_channel_unlock_napi(struct efx_channel *channel)
584 static inline bool efx_channel_lock_poll(struct efx_channel *channel)
589 static inline void efx_channel_unlock_poll(struct efx_channel *channel)
593 static inline bool efx_channel_busy_polling(struct efx_channel *channel)
598 static inline void efx_channel_enable(struct efx_channel *channel)
602 static inline bool efx_channel_disable(struct efx_channel *channel)
606 #endif /* CONFIG_NET_RX_BUSY_POLL */
609 * struct efx_msi_context - Context for each MSI
610 * @efx: The associated NIC
611 * @index: Index of the channel/IRQ
612 * @name: Name of the channel/IRQ
614 * Unlike &struct efx_channel, this is never reallocated and is always
615 * safe for the IRQ handler to access.
617 struct efx_msi_context {
620 char name[IFNAMSIZ + 6];
624 * struct efx_channel_type - distinguishes traffic and extra channels
625 * @handle_no_channel: Handle failure to allocate an extra channel
626 * @pre_probe: Set up extra state prior to initialisation
627 * @post_remove: Tear down extra state after finalisation, if allocated.
628 * May be called on channels that have not been probed.
629 * @get_name: Generate the channel's name (used for its IRQ handler)
630 * @copy: Copy the channel state prior to reallocation. May be %NULL if
631 * reallocation is not supported.
632 * @receive_skb: Handle an skb ready to be passed to netif_receive_skb()
633 * @keep_eventq: Flag for whether event queue should be kept initialised
634 * while the device is stopped
636 struct efx_channel_type {
637 void (*handle_no_channel)(struct efx_nic *);
638 int (*pre_probe)(struct efx_channel *);
639 void (*post_remove)(struct efx_channel *);
640 void (*get_name)(struct efx_channel *, char *buf, size_t len);
641 struct efx_channel *(*copy)(const struct efx_channel *);
642 bool (*receive_skb)(struct efx_channel *, struct sk_buff *);
652 #define STRING_TABLE_LOOKUP(val, member) \
653 ((val) < member ## _max) ? member ## _names[val] : "(invalid)"
655 extern const char *const efx_loopback_mode_names[];
656 extern const unsigned int efx_loopback_mode_max;
657 #define LOOPBACK_MODE(efx) \
658 STRING_TABLE_LOOKUP((efx)->loopback_mode, efx_loopback_mode)
660 extern const char *const efx_reset_type_names[];
661 extern const unsigned int efx_reset_type_max;
662 #define RESET_TYPE(type) \
663 STRING_TABLE_LOOKUP(type, efx_reset_type)
666 /* Be careful if altering to correct macro below */
667 EFX_INT_MODE_MSIX = 0,
668 EFX_INT_MODE_MSI = 1,
669 EFX_INT_MODE_LEGACY = 2,
670 EFX_INT_MODE_MAX /* Insert any new items before this */
672 #define EFX_INT_MODE_USE_MSI(x) (((x)->interrupt_mode) <= EFX_INT_MODE_MSI)
675 STATE_UNINIT = 0, /* device being probed/removed or is frozen */
676 STATE_READY = 1, /* hardware ready and netdev registered */
677 STATE_DISABLED = 2, /* device disabled due to hardware errors */
678 STATE_RECOVERY = 3, /* device recovering from PCI error */
681 /* Forward declaration */
684 /* Pseudo bit-mask flow control field */
685 #define EFX_FC_RX FLOW_CTRL_RX
686 #define EFX_FC_TX FLOW_CTRL_TX
687 #define EFX_FC_AUTO 4
690 * struct efx_link_state - Current state of the link
692 * @fd: Link is full-duplex
693 * @fc: Actual flow control flags
694 * @speed: Link speed (Mbps)
696 struct efx_link_state {
703 static inline bool efx_link_state_equal(const struct efx_link_state *left,
704 const struct efx_link_state *right)
706 return left->up == right->up && left->fd == right->fd &&
707 left->fc == right->fc && left->speed == right->speed;
711 * struct efx_phy_operations - Efx PHY operations table
712 * @probe: Probe PHY and initialise efx->mdio.mode_support, efx->mdio.mmds,
713 * efx->loopback_modes.
714 * @init: Initialise PHY
715 * @fini: Shut down PHY
716 * @reconfigure: Reconfigure PHY (e.g. for new link parameters)
717 * @poll: Update @link_state and report whether it changed.
718 * Serialised by the mac_lock.
719 * @get_settings: Get ethtool settings. Serialised by the mac_lock.
720 * @set_settings: Set ethtool settings. Serialised by the mac_lock.
721 * @set_npage_adv: Set abilities advertised in (Extended) Next Page
722 * (only needed where AN bit is set in mmds)
723 * @test_alive: Test that PHY is 'alive' (online)
724 * @test_name: Get the name of a PHY-specific test/result
725 * @run_tests: Run tests and record results as appropriate (offline).
726 * Flags are the ethtool tests flags.
728 struct efx_phy_operations {
729 int (*probe) (struct efx_nic *efx);
730 int (*init) (struct efx_nic *efx);
731 void (*fini) (struct efx_nic *efx);
732 void (*remove) (struct efx_nic *efx);
733 int (*reconfigure) (struct efx_nic *efx);
734 bool (*poll) (struct efx_nic *efx);
735 void (*get_settings) (struct efx_nic *efx,
736 struct ethtool_cmd *ecmd);
737 int (*set_settings) (struct efx_nic *efx,
738 struct ethtool_cmd *ecmd);
739 void (*set_npage_adv) (struct efx_nic *efx, u32);
740 int (*test_alive) (struct efx_nic *efx);
741 const char *(*test_name) (struct efx_nic *efx, unsigned int index);
742 int (*run_tests) (struct efx_nic *efx, int *results, unsigned flags);
743 int (*get_module_eeprom) (struct efx_nic *efx,
744 struct ethtool_eeprom *ee,
746 int (*get_module_info) (struct efx_nic *efx,
747 struct ethtool_modinfo *modinfo);
751 * enum efx_phy_mode - PHY operating mode flags
752 * @PHY_MODE_NORMAL: on and should pass traffic
753 * @PHY_MODE_TX_DISABLED: on with TX disabled
754 * @PHY_MODE_LOW_POWER: set to low power through MDIO
755 * @PHY_MODE_OFF: switched off through external control
756 * @PHY_MODE_SPECIAL: on but will not pass traffic
760 PHY_MODE_TX_DISABLED = 1,
761 PHY_MODE_LOW_POWER = 2,
763 PHY_MODE_SPECIAL = 8,
766 static inline bool efx_phy_mode_disabled(enum efx_phy_mode mode)
768 return !!(mode & ~PHY_MODE_TX_DISABLED);
772 * struct efx_hw_stat_desc - Description of a hardware statistic
773 * @name: Name of the statistic as visible through ethtool, or %NULL if
774 * it should not be exposed
775 * @dma_width: Width in bits (0 for non-DMA statistics)
776 * @offset: Offset within stats (ignored for non-DMA statistics)
778 struct efx_hw_stat_desc {
784 /* Number of bits used in a multicast filter hash address */
785 #define EFX_MCAST_HASH_BITS 8
787 /* Number of (single-bit) entries in a multicast filter hash */
788 #define EFX_MCAST_HASH_ENTRIES (1 << EFX_MCAST_HASH_BITS)
790 /* An Efx multicast filter hash */
791 union efx_multicast_hash {
792 u8 byte[EFX_MCAST_HASH_ENTRIES / 8];
793 efx_oword_t oword[EFX_MCAST_HASH_ENTRIES / sizeof(efx_oword_t) / 8];
800 * struct efx_nic - an Efx NIC
801 * @name: Device name (net device name or bus id before net device registered)
802 * @pci_dev: The PCI device
803 * @node: List node for maintaning primary/secondary function lists
804 * @primary: &struct efx_nic instance for the primary function of this
805 * controller. May be the same structure, and may be %NULL if no
806 * primary function is bound. Serialised by rtnl_lock.
807 * @secondary_list: List of &struct efx_nic instances for the secondary PCI
808 * functions of the controller, if this is for the primary function.
809 * Serialised by rtnl_lock.
810 * @type: Controller type attributes
811 * @legacy_irq: IRQ number
812 * @workqueue: Workqueue for port reconfigures and the HW monitor.
813 * Work items do not hold and must not acquire RTNL.
814 * @workqueue_name: Name of workqueue
815 * @reset_work: Scheduled reset workitem
816 * @membase_phys: Memory BAR value as physical address
817 * @membase: Memory BAR value
818 * @interrupt_mode: Interrupt mode
819 * @timer_quantum_ns: Interrupt timer quantum, in nanoseconds
820 * @irq_rx_adaptive: Adaptive IRQ moderation enabled for RX event queues
821 * @irq_rx_moderation: IRQ moderation time for RX event queues
822 * @msg_enable: Log message enable flags
823 * @state: Device state number (%STATE_*). Serialised by the rtnl_lock.
824 * @reset_pending: Bitmask for pending resets
825 * @tx_queue: TX DMA queues
826 * @rx_queue: RX DMA queues
828 * @msi_context: Context for each MSI
829 * @extra_channel_types: Types of extra (non-traffic) channels that
830 * should be allocated for this NIC
831 * @rxq_entries: Size of receive queues requested by user.
832 * @txq_entries: Size of transmit queues requested by user.
833 * @txq_stop_thresh: TX queue fill level at or above which we stop it.
834 * @txq_wake_thresh: TX queue fill level at or below which we wake it.
835 * @tx_dc_base: Base qword address in SRAM of TX queue descriptor caches
836 * @rx_dc_base: Base qword address in SRAM of RX queue descriptor caches
837 * @sram_lim_qw: Qword address limit of SRAM
838 * @next_buffer_table: First available buffer table id
839 * @n_channels: Number of channels in use
840 * @n_rx_channels: Number of channels used for RX (= number of RX queues)
841 * @n_tx_channels: Number of channels used for TX
842 * @rx_ip_align: RX DMA address offset to have IP header aligned in
843 * in accordance with NET_IP_ALIGN
844 * @rx_dma_len: Current maximum RX DMA length
845 * @rx_buffer_order: Order (log2) of number of pages for each RX buffer
846 * @rx_buffer_truesize: Amortised allocation size of an RX buffer,
847 * for use in sk_buff::truesize
848 * @rx_prefix_size: Size of RX prefix before packet data
849 * @rx_packet_hash_offset: Offset of RX flow hash from start of packet data
850 * (valid only if @rx_prefix_size != 0; always negative)
851 * @rx_packet_len_offset: Offset of RX packet length from start of packet data
852 * (valid only for NICs that set %EFX_RX_PKT_PREFIX_LEN; always negative)
853 * @rx_packet_ts_offset: Offset of timestamp from start of packet data
854 * (valid only if channel->sync_timestamps_enabled; always negative)
855 * @rx_hash_key: Toeplitz hash key for RSS
856 * @rx_indir_table: Indirection table for RSS
857 * @rx_scatter: Scatter mode enabled for receives
858 * @int_error_count: Number of internal errors seen recently
859 * @int_error_expire: Time at which error count will be expired
860 * @irq_soft_enabled: Are IRQs soft-enabled? If not, IRQ handler will
861 * acknowledge but do nothing else.
862 * @irq_status: Interrupt status buffer
863 * @irq_zero_count: Number of legacy IRQs seen with queue flags == 0
864 * @irq_level: IRQ level/index for IRQs not triggered by an event queue
865 * @selftest_work: Work item for asynchronous self-test
866 * @mtd_list: List of MTDs attached to the NIC
867 * @nic_data: Hardware dependent state
868 * @mcdi: Management-Controller-to-Driver Interface state
869 * @mac_lock: MAC access lock. Protects @port_enabled, @phy_mode,
870 * efx_monitor() and efx_reconfigure_port()
871 * @port_enabled: Port enabled indicator.
872 * Serialises efx_stop_all(), efx_start_all(), efx_monitor() and
873 * efx_mac_work() with kernel interfaces. Safe to read under any
874 * one of the rtnl_lock, mac_lock, or netif_tx_lock, but all three must
875 * be held to modify it.
876 * @port_initialized: Port initialized?
877 * @net_dev: Operating system network device. Consider holding the rtnl lock
878 * @stats_buffer: DMA buffer for statistics
879 * @phy_type: PHY type
880 * @phy_op: PHY interface
881 * @phy_data: PHY private data (including PHY-specific stats)
882 * @mdio: PHY MDIO interface
883 * @mdio_bus: PHY MDIO bus ID (only used by Siena)
884 * @phy_mode: PHY operating mode. Serialised by @mac_lock.
885 * @link_advertising: Autonegotiation advertising flags
886 * @link_state: Current state of the link
887 * @n_link_state_changes: Number of times the link has changed state
888 * @unicast_filter: Flag for Falcon-arch simple unicast filter.
889 * Protected by @mac_lock.
890 * @multicast_hash: Multicast hash table for Falcon-arch.
891 * Protected by @mac_lock.
892 * @wanted_fc: Wanted flow control flags
893 * @fc_disable: When non-zero flow control is disabled. Typically used to
894 * ensure that network back pressure doesn't delay dma queue flushes.
895 * Serialised by the rtnl lock.
896 * @mac_work: Work item for changing MAC promiscuity and multicast hash
897 * @loopback_mode: Loopback status
898 * @loopback_modes: Supported loopback mode bitmask
899 * @loopback_selftest: Offline self-test private state
900 * @filter_lock: Filter table lock
901 * @filter_state: Architecture-dependent filter table state
902 * @rps_flow_id: Flow IDs of filters allocated for accelerated RFS,
903 * indexed by filter ID
904 * @rps_expire_index: Next index to check for expiry in @rps_flow_id
905 * @active_queues: Count of RX and TX queues that haven't been flushed and drained.
906 * @rxq_flush_pending: Count of number of receive queues that need to be flushed.
907 * Decremented when the efx_flush_rx_queue() is called.
908 * @rxq_flush_outstanding: Count of number of RX flushes started but not yet
909 * completed (either success or failure). Not used when MCDI is used to
910 * flush receive queues.
911 * @flush_wq: wait queue used by efx_nic_flush_queues() to wait for flush completions.
912 * @vf: Array of &struct efx_vf objects.
913 * @vf_count: Number of VFs intended to be enabled.
914 * @vf_init_count: Number of VFs that have been fully initialised.
915 * @vi_scale: log2 number of vnics per VF.
916 * @ptp_data: PTP state data
917 * @vpd_sn: Serial number read from VPD
918 * @monitor_work: Hardware monitor workitem
919 * @biu_lock: BIU (bus interface unit) lock
920 * @last_irq_cpu: Last CPU to handle a possible test interrupt. This
921 * field is used by efx_test_interrupts() to verify that an
922 * interrupt has occurred.
923 * @stats_lock: Statistics update lock. Must be held when calling
924 * efx_nic_type::{update,start,stop}_stats.
925 * @n_rx_noskb_drops: Count of RX packets dropped due to failure to allocate an skb
927 * This is stored in the private area of the &struct net_device.
930 /* The following fields should be written very rarely */
933 struct list_head node;
934 struct efx_nic *primary;
935 struct list_head secondary_list;
936 struct pci_dev *pci_dev;
937 unsigned int port_num;
938 const struct efx_nic_type *type;
940 bool eeh_disabled_legacy_irq;
941 struct workqueue_struct *workqueue;
942 char workqueue_name[16];
943 struct work_struct reset_work;
944 resource_size_t membase_phys;
945 void __iomem *membase;
947 enum efx_int_mode interrupt_mode;
948 unsigned int timer_quantum_ns;
949 bool irq_rx_adaptive;
950 unsigned int irq_rx_moderation;
953 enum nic_state state;
954 unsigned long reset_pending;
956 struct efx_channel *channel[EFX_MAX_CHANNELS];
957 struct efx_msi_context msi_context[EFX_MAX_CHANNELS];
958 const struct efx_channel_type *
959 extra_channel_type[EFX_MAX_EXTRA_CHANNELS];
961 unsigned rxq_entries;
962 unsigned txq_entries;
963 unsigned int txq_stop_thresh;
964 unsigned int txq_wake_thresh;
968 unsigned sram_lim_qw;
969 unsigned next_buffer_table;
971 unsigned int max_channels;
973 unsigned n_rx_channels;
975 unsigned tx_channel_offset;
976 unsigned n_tx_channels;
977 unsigned int rx_ip_align;
978 unsigned int rx_dma_len;
979 unsigned int rx_buffer_order;
980 unsigned int rx_buffer_truesize;
981 unsigned int rx_page_buf_step;
982 unsigned int rx_bufs_per_page;
983 unsigned int rx_pages_per_batch;
984 unsigned int rx_prefix_size;
985 int rx_packet_hash_offset;
986 int rx_packet_len_offset;
987 int rx_packet_ts_offset;
989 u32 rx_indir_table[128];
992 unsigned int_error_count;
993 unsigned long int_error_expire;
995 bool irq_soft_enabled;
996 struct efx_buffer irq_status;
997 unsigned irq_zero_count;
999 struct delayed_work selftest_work;
1001 #ifdef CONFIG_SFC_MTD
1002 struct list_head mtd_list;
1006 struct efx_mcdi_data *mcdi;
1008 struct mutex mac_lock;
1009 struct work_struct mac_work;
1012 bool mc_bist_for_other_fn;
1013 bool port_initialized;
1014 struct net_device *net_dev;
1016 struct efx_buffer stats_buffer;
1017 u64 rx_nodesc_drops_total;
1018 u64 rx_nodesc_drops_while_down;
1019 bool rx_nodesc_drops_prev_state;
1021 unsigned int phy_type;
1022 const struct efx_phy_operations *phy_op;
1024 struct mdio_if_info mdio;
1025 unsigned int mdio_bus;
1026 enum efx_phy_mode phy_mode;
1028 u32 link_advertising;
1029 struct efx_link_state link_state;
1030 unsigned int n_link_state_changes;
1032 bool unicast_filter;
1033 union efx_multicast_hash multicast_hash;
1035 unsigned fc_disable;
1038 enum efx_loopback_mode loopback_mode;
1041 void *loopback_selftest;
1043 spinlock_t filter_lock;
1045 #ifdef CONFIG_RFS_ACCEL
1047 unsigned int rps_expire_index;
1050 atomic_t active_queues;
1051 atomic_t rxq_flush_pending;
1052 atomic_t rxq_flush_outstanding;
1053 wait_queue_head_t flush_wq;
1055 #ifdef CONFIG_SFC_SRIOV
1058 unsigned vf_init_count;
1062 struct efx_ptp_data *ptp_data;
1066 /* The following fields may be written more often */
1068 struct delayed_work monitor_work ____cacheline_aligned_in_smp;
1069 spinlock_t biu_lock;
1071 spinlock_t stats_lock;
1072 atomic_t n_rx_noskb_drops;
1075 static inline int efx_dev_registered(struct efx_nic *efx)
1077 return efx->net_dev->reg_state == NETREG_REGISTERED;
1080 static inline unsigned int efx_port_num(struct efx_nic *efx)
1082 return efx->port_num;
1085 struct efx_mtd_partition {
1086 struct list_head node;
1087 struct mtd_info mtd;
1088 const char *dev_type_name;
1089 const char *type_name;
1090 char name[IFNAMSIZ + 20];
1094 * struct efx_nic_type - Efx device type definition
1095 * @mem_map_size: Get memory BAR mapped size
1096 * @probe: Probe the controller
1097 * @remove: Free resources allocated by probe()
1098 * @init: Initialise the controller
1099 * @dimension_resources: Dimension controller resources (buffer table,
1100 * and VIs once the available interrupt resources are clear)
1101 * @fini: Shut down the controller
1102 * @monitor: Periodic function for polling link state and hardware monitor
1103 * @map_reset_reason: Map ethtool reset reason to a reset method
1104 * @map_reset_flags: Map ethtool reset flags to a reset method, if possible
1105 * @reset: Reset the controller hardware and possibly the PHY. This will
1106 * be called while the controller is uninitialised.
1107 * @probe_port: Probe the MAC and PHY
1108 * @remove_port: Free resources allocated by probe_port()
1109 * @handle_global_event: Handle a "global" event (may be %NULL)
1110 * @fini_dmaq: Flush and finalise DMA queues (RX and TX queues)
1111 * @prepare_flush: Prepare the hardware for flushing the DMA queues
1112 * (for Falcon architecture)
1113 * @finish_flush: Clean up after flushing the DMA queues (for Falcon
1115 * @prepare_flr: Prepare for an FLR
1116 * @finish_flr: Clean up after an FLR
1117 * @describe_stats: Describe statistics for ethtool
1118 * @update_stats: Update statistics not provided by event handling.
1119 * Either argument may be %NULL.
1120 * @start_stats: Start the regular fetching of statistics
1121 * @pull_stats: Pull stats from the NIC and wait until they arrive.
1122 * @stop_stats: Stop the regular fetching of statistics
1123 * @set_id_led: Set state of identifying LED or revert to automatic function
1124 * @push_irq_moderation: Apply interrupt moderation value
1125 * @reconfigure_port: Push loopback/power/txdis changes to the MAC and PHY
1126 * @prepare_enable_fc_tx: Prepare MAC to enable pause frame TX (may be %NULL)
1127 * @reconfigure_mac: Push MAC address, MTU, flow control and filter settings
1128 * to the hardware. Serialised by the mac_lock.
1129 * @check_mac_fault: Check MAC fault state. True if fault present.
1130 * @get_wol: Get WoL configuration from driver state
1131 * @set_wol: Push WoL configuration to the NIC
1132 * @resume_wol: Synchronise WoL state between driver and MC (e.g. after resume)
1133 * @test_chip: Test registers. May use efx_farch_test_registers(), and is
1134 * expected to reset the NIC.
1135 * @test_nvram: Test validity of NVRAM contents
1136 * @mcdi_request: Send an MCDI request with the given header and SDU.
1137 * The SDU length may be any value from 0 up to the protocol-
1138 * defined maximum, but its buffer will be padded to a multiple
1140 * @mcdi_poll_response: Test whether an MCDI response is available.
1141 * @mcdi_read_response: Read the MCDI response PDU. The offset will
1142 * be a multiple of 4. The length may not be, but the buffer
1143 * will be padded so it is safe to round up.
1144 * @mcdi_poll_reboot: Test whether the MCDI has rebooted. If so,
1145 * return an appropriate error code for aborting any current
1146 * request; otherwise return 0.
1147 * @irq_enable_master: Enable IRQs on the NIC. Each event queue must
1148 * be separately enabled after this.
1149 * @irq_test_generate: Generate a test IRQ
1150 * @irq_disable_non_ev: Disable non-event IRQs on the NIC. Each event
1151 * queue must be separately disabled before this.
1152 * @irq_handle_msi: Handle MSI for a channel. The @dev_id argument is
1153 * a pointer to the &struct efx_msi_context for the channel.
1154 * @irq_handle_legacy: Handle legacy interrupt. The @dev_id argument
1155 * is a pointer to the &struct efx_nic.
1156 * @tx_probe: Allocate resources for TX queue
1157 * @tx_init: Initialise TX queue on the NIC
1158 * @tx_remove: Free resources for TX queue
1159 * @tx_write: Write TX descriptors and doorbell
1160 * @rx_push_rss_config: Write RSS hash key and indirection table to the NIC
1161 * @rx_probe: Allocate resources for RX queue
1162 * @rx_init: Initialise RX queue on the NIC
1163 * @rx_remove: Free resources for RX queue
1164 * @rx_write: Write RX descriptors and doorbell
1165 * @rx_defer_refill: Generate a refill reminder event
1166 * @ev_probe: Allocate resources for event queue
1167 * @ev_init: Initialise event queue on the NIC
1168 * @ev_fini: Deinitialise event queue on the NIC
1169 * @ev_remove: Free resources for event queue
1170 * @ev_process: Process events for a queue, up to the given NAPI quota
1171 * @ev_read_ack: Acknowledge read events on a queue, rearming its IRQ
1172 * @ev_test_generate: Generate a test event
1173 * @filter_table_probe: Probe filter capabilities and set up filter software state
1174 * @filter_table_restore: Restore filters removed from hardware
1175 * @filter_table_remove: Remove filters from hardware and tear down software state
1176 * @filter_update_rx_scatter: Update filters after change to rx scatter setting
1177 * @filter_insert: add or replace a filter
1178 * @filter_remove_safe: remove a filter by ID, carefully
1179 * @filter_get_safe: retrieve a filter by ID, carefully
1180 * @filter_clear_rx: Remove all RX filters whose priority is less than or
1181 * equal to the given priority and is not %EFX_FILTER_PRI_AUTO
1182 * @filter_count_rx_used: Get the number of filters in use at a given priority
1183 * @filter_get_rx_id_limit: Get maximum value of a filter id, plus 1
1184 * @filter_get_rx_ids: Get list of RX filters at a given priority
1185 * @filter_rfs_insert: Add or replace a filter for RFS. This must be
1186 * atomic. The hardware change may be asynchronous but should
1187 * not be delayed for long. It may fail if this can't be done
1189 * @filter_rfs_expire_one: Consider expiring a filter inserted for RFS.
1190 * This must check whether the specified table entry is used by RFS
1191 * and that rps_may_expire_flow() returns true for it.
1192 * @mtd_probe: Probe and add MTD partitions associated with this net device,
1193 * using efx_mtd_add()
1194 * @mtd_rename: Set an MTD partition name using the net device name
1195 * @mtd_read: Read from an MTD partition
1196 * @mtd_erase: Erase part of an MTD partition
1197 * @mtd_write: Write to an MTD partition
1198 * @mtd_sync: Wait for write-back to complete on MTD partition. This
1199 * also notifies the driver that a writer has finished using this
1201 * @ptp_write_host_time: Send host time to MC as part of sync protocol
1202 * @ptp_set_ts_sync_events: Enable or disable sync events for inline RX
1203 * timestamping, possibly only temporarily for the purposes of a reset.
1204 * @ptp_set_ts_config: Set hardware timestamp configuration. The flags
1205 * and tx_type will already have been validated but this operation
1206 * must validate and update rx_filter.
1207 * @revision: Hardware architecture revision
1208 * @txd_ptr_tbl_base: TX descriptor ring base address
1209 * @rxd_ptr_tbl_base: RX descriptor ring base address
1210 * @buf_tbl_base: Buffer table base address
1211 * @evq_ptr_tbl_base: Event queue pointer table base address
1212 * @evq_rptr_tbl_base: Event queue read-pointer table base address
1213 * @max_dma_mask: Maximum possible DMA mask
1214 * @rx_prefix_size: Size of RX prefix before packet data
1215 * @rx_hash_offset: Offset of RX flow hash within prefix
1216 * @rx_ts_offset: Offset of timestamp within prefix
1217 * @rx_buffer_padding: Size of padding at end of RX packet
1218 * @can_rx_scatter: NIC is able to scatter packets to multiple buffers
1219 * @always_rx_scatter: NIC will always scatter packets to multiple buffers
1220 * @max_interrupt_mode: Highest capability interrupt mode supported
1221 * from &enum efx_init_mode.
1222 * @timer_period_max: Maximum period of interrupt timer (in ticks)
1223 * @offload_features: net_device feature flags for protocol offload
1224 * features implemented in hardware
1225 * @mcdi_max_ver: Maximum MCDI version supported
1226 * @hwtstamp_filters: Mask of hardware timestamp filter types supported
1228 struct efx_nic_type {
1229 unsigned int (*mem_map_size)(struct efx_nic *efx);
1230 int (*probe)(struct efx_nic *efx);
1231 void (*remove)(struct efx_nic *efx);
1232 int (*init)(struct efx_nic *efx);
1233 int (*dimension_resources)(struct efx_nic *efx);
1234 void (*fini)(struct efx_nic *efx);
1235 void (*monitor)(struct efx_nic *efx);
1236 enum reset_type (*map_reset_reason)(enum reset_type reason);
1237 int (*map_reset_flags)(u32 *flags);
1238 int (*reset)(struct efx_nic *efx, enum reset_type method);
1239 int (*probe_port)(struct efx_nic *efx);
1240 void (*remove_port)(struct efx_nic *efx);
1241 bool (*handle_global_event)(struct efx_channel *channel, efx_qword_t *);
1242 int (*fini_dmaq)(struct efx_nic *efx);
1243 void (*prepare_flush)(struct efx_nic *efx);
1244 void (*finish_flush)(struct efx_nic *efx);
1245 void (*prepare_flr)(struct efx_nic *efx);
1246 void (*finish_flr)(struct efx_nic *efx);
1247 size_t (*describe_stats)(struct efx_nic *efx, u8 *names);
1248 size_t (*update_stats)(struct efx_nic *efx, u64 *full_stats,
1249 struct rtnl_link_stats64 *core_stats);
1250 void (*start_stats)(struct efx_nic *efx);
1251 void (*pull_stats)(struct efx_nic *efx);
1252 void (*stop_stats)(struct efx_nic *efx);
1253 void (*set_id_led)(struct efx_nic *efx, enum efx_led_mode mode);
1254 void (*push_irq_moderation)(struct efx_channel *channel);
1255 int (*reconfigure_port)(struct efx_nic *efx);
1256 void (*prepare_enable_fc_tx)(struct efx_nic *efx);
1257 int (*reconfigure_mac)(struct efx_nic *efx);
1258 bool (*check_mac_fault)(struct efx_nic *efx);
1259 void (*get_wol)(struct efx_nic *efx, struct ethtool_wolinfo *wol);
1260 int (*set_wol)(struct efx_nic *efx, u32 type);
1261 void (*resume_wol)(struct efx_nic *efx);
1262 int (*test_chip)(struct efx_nic *efx, struct efx_self_tests *tests);
1263 int (*test_nvram)(struct efx_nic *efx);
1264 void (*mcdi_request)(struct efx_nic *efx,
1265 const efx_dword_t *hdr, size_t hdr_len,
1266 const efx_dword_t *sdu, size_t sdu_len);
1267 bool (*mcdi_poll_response)(struct efx_nic *efx);
1268 void (*mcdi_read_response)(struct efx_nic *efx, efx_dword_t *pdu,
1269 size_t pdu_offset, size_t pdu_len);
1270 int (*mcdi_poll_reboot)(struct efx_nic *efx);
1271 void (*irq_enable_master)(struct efx_nic *efx);
1272 void (*irq_test_generate)(struct efx_nic *efx);
1273 void (*irq_disable_non_ev)(struct efx_nic *efx);
1274 irqreturn_t (*irq_handle_msi)(int irq, void *dev_id);
1275 irqreturn_t (*irq_handle_legacy)(int irq, void *dev_id);
1276 int (*tx_probe)(struct efx_tx_queue *tx_queue);
1277 void (*tx_init)(struct efx_tx_queue *tx_queue);
1278 void (*tx_remove)(struct efx_tx_queue *tx_queue);
1279 void (*tx_write)(struct efx_tx_queue *tx_queue);
1280 void (*rx_push_rss_config)(struct efx_nic *efx);
1281 int (*rx_probe)(struct efx_rx_queue *rx_queue);
1282 void (*rx_init)(struct efx_rx_queue *rx_queue);
1283 void (*rx_remove)(struct efx_rx_queue *rx_queue);
1284 void (*rx_write)(struct efx_rx_queue *rx_queue);
1285 void (*rx_defer_refill)(struct efx_rx_queue *rx_queue);
1286 int (*ev_probe)(struct efx_channel *channel);
1287 int (*ev_init)(struct efx_channel *channel);
1288 void (*ev_fini)(struct efx_channel *channel);
1289 void (*ev_remove)(struct efx_channel *channel);
1290 int (*ev_process)(struct efx_channel *channel, int quota);
1291 void (*ev_read_ack)(struct efx_channel *channel);
1292 void (*ev_test_generate)(struct efx_channel *channel);
1293 int (*filter_table_probe)(struct efx_nic *efx);
1294 void (*filter_table_restore)(struct efx_nic *efx);
1295 void (*filter_table_remove)(struct efx_nic *efx);
1296 void (*filter_update_rx_scatter)(struct efx_nic *efx);
1297 s32 (*filter_insert)(struct efx_nic *efx,
1298 struct efx_filter_spec *spec, bool replace);
1299 int (*filter_remove_safe)(struct efx_nic *efx,
1300 enum efx_filter_priority priority,
1302 int (*filter_get_safe)(struct efx_nic *efx,
1303 enum efx_filter_priority priority,
1304 u32 filter_id, struct efx_filter_spec *);
1305 int (*filter_clear_rx)(struct efx_nic *efx,
1306 enum efx_filter_priority priority);
1307 u32 (*filter_count_rx_used)(struct efx_nic *efx,
1308 enum efx_filter_priority priority);
1309 u32 (*filter_get_rx_id_limit)(struct efx_nic *efx);
1310 s32 (*filter_get_rx_ids)(struct efx_nic *efx,
1311 enum efx_filter_priority priority,
1312 u32 *buf, u32 size);
1313 #ifdef CONFIG_RFS_ACCEL
1314 s32 (*filter_rfs_insert)(struct efx_nic *efx,
1315 struct efx_filter_spec *spec);
1316 bool (*filter_rfs_expire_one)(struct efx_nic *efx, u32 flow_id,
1317 unsigned int index);
1319 #ifdef CONFIG_SFC_MTD
1320 int (*mtd_probe)(struct efx_nic *efx);
1321 void (*mtd_rename)(struct efx_mtd_partition *part);
1322 int (*mtd_read)(struct mtd_info *mtd, loff_t start, size_t len,
1323 size_t *retlen, u8 *buffer);
1324 int (*mtd_erase)(struct mtd_info *mtd, loff_t start, size_t len);
1325 int (*mtd_write)(struct mtd_info *mtd, loff_t start, size_t len,
1326 size_t *retlen, const u8 *buffer);
1327 int (*mtd_sync)(struct mtd_info *mtd);
1329 void (*ptp_write_host_time)(struct efx_nic *efx, u32 host_time);
1330 int (*ptp_set_ts_sync_events)(struct efx_nic *efx, bool en, bool temp);
1331 int (*ptp_set_ts_config)(struct efx_nic *efx,
1332 struct hwtstamp_config *init);
1333 int (*sriov_init)(struct efx_nic *efx);
1334 void (*sriov_fini)(struct efx_nic *efx);
1335 void (*sriov_mac_address_changed)(struct efx_nic *efx);
1336 bool (*sriov_wanted)(struct efx_nic *efx);
1337 void (*sriov_reset)(struct efx_nic *efx);
1338 void (*sriov_flr)(struct efx_nic *efx, unsigned vf_i);
1339 int (*sriov_set_vf_mac)(struct efx_nic *efx, int vf_i, u8 *mac);
1340 int (*sriov_set_vf_vlan)(struct efx_nic *efx, int vf_i, u16 vlan,
1342 int (*sriov_set_vf_spoofchk)(struct efx_nic *efx, int vf_i,
1344 int (*sriov_get_vf_config)(struct efx_nic *efx, int vf_i,
1345 struct ifla_vf_info *ivi);
1348 unsigned int txd_ptr_tbl_base;
1349 unsigned int rxd_ptr_tbl_base;
1350 unsigned int buf_tbl_base;
1351 unsigned int evq_ptr_tbl_base;
1352 unsigned int evq_rptr_tbl_base;
1354 unsigned int rx_prefix_size;
1355 unsigned int rx_hash_offset;
1356 unsigned int rx_ts_offset;
1357 unsigned int rx_buffer_padding;
1358 bool can_rx_scatter;
1359 bool always_rx_scatter;
1360 unsigned int max_interrupt_mode;
1361 unsigned int timer_period_max;
1362 netdev_features_t offload_features;
1364 unsigned int max_rx_ip_filters;
1365 u32 hwtstamp_filters;
1368 /**************************************************************************
1370 * Prototypes and inline functions
1372 *************************************************************************/
1374 static inline struct efx_channel *
1375 efx_get_channel(struct efx_nic *efx, unsigned index)
1377 EFX_BUG_ON_PARANOID(index >= efx->n_channels);
1378 return efx->channel[index];
1381 /* Iterate over all used channels */
1382 #define efx_for_each_channel(_channel, _efx) \
1383 for (_channel = (_efx)->channel[0]; \
1385 _channel = (_channel->channel + 1 < (_efx)->n_channels) ? \
1386 (_efx)->channel[_channel->channel + 1] : NULL)
1388 /* Iterate over all used channels in reverse */
1389 #define efx_for_each_channel_rev(_channel, _efx) \
1390 for (_channel = (_efx)->channel[(_efx)->n_channels - 1]; \
1392 _channel = _channel->channel ? \
1393 (_efx)->channel[_channel->channel - 1] : NULL)
1395 static inline struct efx_tx_queue *
1396 efx_get_tx_queue(struct efx_nic *efx, unsigned index, unsigned type)
1398 EFX_BUG_ON_PARANOID(index >= efx->n_tx_channels ||
1399 type >= EFX_TXQ_TYPES);
1400 return &efx->channel[efx->tx_channel_offset + index]->tx_queue[type];
1403 static inline bool efx_channel_has_tx_queues(struct efx_channel *channel)
1405 return channel->channel - channel->efx->tx_channel_offset <
1406 channel->efx->n_tx_channels;
1409 static inline struct efx_tx_queue *
1410 efx_channel_get_tx_queue(struct efx_channel *channel, unsigned type)
1412 EFX_BUG_ON_PARANOID(!efx_channel_has_tx_queues(channel) ||
1413 type >= EFX_TXQ_TYPES);
1414 return &channel->tx_queue[type];
1417 static inline bool efx_tx_queue_used(struct efx_tx_queue *tx_queue)
1419 return !(tx_queue->efx->net_dev->num_tc < 2 &&
1420 tx_queue->queue & EFX_TXQ_TYPE_HIGHPRI);
1423 /* Iterate over all TX queues belonging to a channel */
1424 #define efx_for_each_channel_tx_queue(_tx_queue, _channel) \
1425 if (!efx_channel_has_tx_queues(_channel)) \
1428 for (_tx_queue = (_channel)->tx_queue; \
1429 _tx_queue < (_channel)->tx_queue + EFX_TXQ_TYPES && \
1430 efx_tx_queue_used(_tx_queue); \
1433 /* Iterate over all possible TX queues belonging to a channel */
1434 #define efx_for_each_possible_channel_tx_queue(_tx_queue, _channel) \
1435 if (!efx_channel_has_tx_queues(_channel)) \
1438 for (_tx_queue = (_channel)->tx_queue; \
1439 _tx_queue < (_channel)->tx_queue + EFX_TXQ_TYPES; \
1442 static inline bool efx_channel_has_rx_queue(struct efx_channel *channel)
1444 return channel->rx_queue.core_index >= 0;
1447 static inline struct efx_rx_queue *
1448 efx_channel_get_rx_queue(struct efx_channel *channel)
1450 EFX_BUG_ON_PARANOID(!efx_channel_has_rx_queue(channel));
1451 return &channel->rx_queue;
1454 /* Iterate over all RX queues belonging to a channel */
1455 #define efx_for_each_channel_rx_queue(_rx_queue, _channel) \
1456 if (!efx_channel_has_rx_queue(_channel)) \
1459 for (_rx_queue = &(_channel)->rx_queue; \
1463 static inline struct efx_channel *
1464 efx_rx_queue_channel(struct efx_rx_queue *rx_queue)
1466 return container_of(rx_queue, struct efx_channel, rx_queue);
1469 static inline int efx_rx_queue_index(struct efx_rx_queue *rx_queue)
1471 return efx_rx_queue_channel(rx_queue)->channel;
1474 /* Returns a pointer to the specified receive buffer in the RX
1477 static inline struct efx_rx_buffer *efx_rx_buffer(struct efx_rx_queue *rx_queue,
1480 return &rx_queue->buffer[index];
1484 * EFX_MAX_FRAME_LEN - calculate maximum frame length
1486 * This calculates the maximum frame length that will be used for a
1487 * given MTU. The frame length will be equal to the MTU plus a
1488 * constant amount of header space and padding. This is the quantity
1489 * that the net driver will program into the MAC as the maximum frame
1492 * The 10G MAC requires 8-byte alignment on the frame
1493 * length, so we round up to the nearest 8.
1495 * Re-clocking by the XGXS on RX can reduce an IPG to 32 bits (half an
1496 * XGMII cycle). If the frame length reaches the maximum value in the
1497 * same cycle, the XMAC can miss the IPG altogether. We work around
1498 * this by adding a further 16 bytes.
1500 #define EFX_MAX_FRAME_LEN(mtu) \
1501 ((((mtu) + ETH_HLEN + VLAN_HLEN + 4/* FCS */ + 7) & ~7) + 16)
1503 static inline bool efx_xmit_with_hwtstamp(struct sk_buff *skb)
1505 return skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP;
1507 static inline void efx_xmit_hwtstamp_pending(struct sk_buff *skb)
1509 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1512 #endif /* EFX_NET_DRIVER_H */