1 /*******************************************************************************
2 STMMAC Common Header File
4 Copyright (C) 2007-2009 STMicroelectronics Ltd
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
22 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
23 *******************************************************************************/
28 #include <linux/etherdevice.h>
29 #include <linux/netdevice.h>
30 #include <linux/phy.h>
31 #include <linux/module.h>
32 #include <linux/init.h>
33 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
34 #define STMMAC_VLAN_TAG_USED
35 #include <linux/if_vlan.h>
41 #undef CHIP_DEBUG_PRINT
42 /* Turn-on extra printk debug for MAC core, dma and descriptors */
43 /* #define CHIP_DEBUG_PRINT */
45 #ifdef CHIP_DEBUG_PRINT
46 #define CHIP_DBG(fmt, args...) printk(fmt, ## args)
48 #define CHIP_DBG(fmt, args...) do { } while (0)
51 /* Synopsys Core versions */
52 #define DWMAC_CORE_3_40 0x34
53 #define DWMAC_CORE_3_50 0x35
55 #undef FRAME_FILTER_DEBUG
56 /* #define FRAME_FILTER_DEBUG */
58 struct stmmac_extra_stats {
60 unsigned long tx_underflow ____cacheline_aligned;
61 unsigned long tx_carrier;
62 unsigned long tx_losscarrier;
63 unsigned long vlan_tag;
64 unsigned long tx_deferred;
65 unsigned long tx_vlan;
66 unsigned long tx_jabber;
67 unsigned long tx_frame_flushed;
68 unsigned long tx_payload_error;
69 unsigned long tx_ip_header_error;
71 unsigned long rx_desc;
72 unsigned long sa_filter_fail;
73 unsigned long overflow_error;
74 unsigned long ipc_csum_error;
75 unsigned long rx_collision;
77 unsigned long dribbling_bit;
78 unsigned long rx_length;
80 unsigned long rx_multicast;
81 unsigned long rx_gmac_overflow;
82 unsigned long rx_watchdog;
83 unsigned long da_rx_filter_fail;
84 unsigned long sa_rx_filter_fail;
85 unsigned long rx_missed_cntr;
86 unsigned long rx_overflow_cntr;
87 unsigned long rx_vlan;
88 /* Tx/Rx IRQ error info */
89 unsigned long tx_undeflow_irq;
90 unsigned long tx_process_stopped_irq;
91 unsigned long tx_jabber_irq;
92 unsigned long rx_overflow_irq;
93 unsigned long rx_buf_unav_irq;
94 unsigned long rx_process_stopped_irq;
95 unsigned long rx_watchdog_irq;
96 unsigned long tx_early_irq;
97 unsigned long fatal_bus_error_irq;
98 /* Tx/Rx IRQ Events */
99 unsigned long rx_early_irq;
100 unsigned long threshold;
101 unsigned long tx_pkt_n;
102 unsigned long rx_pkt_n;
103 unsigned long normal_irq_n;
104 unsigned long rx_normal_irq_n;
105 unsigned long napi_poll;
106 unsigned long tx_normal_irq_n;
107 unsigned long tx_clean;
108 unsigned long tx_reset_ic_bit;
109 unsigned long irq_receive_pmt_irq_n;
111 unsigned long mmc_tx_irq_n;
112 unsigned long mmc_rx_irq_n;
113 unsigned long mmc_rx_csum_offload_irq_n;
115 unsigned long irq_tx_path_in_lpi_mode_n;
116 unsigned long irq_tx_path_exit_lpi_mode_n;
117 unsigned long irq_rx_path_in_lpi_mode_n;
118 unsigned long irq_rx_path_exit_lpi_mode_n;
119 unsigned long phy_eee_wakeup_error_n;
120 /* Extended RDES status */
121 unsigned long ip_hdr_err;
122 unsigned long ip_payload_err;
123 unsigned long ip_csum_bypassed;
124 unsigned long ipv4_pkt_rcvd;
125 unsigned long ipv6_pkt_rcvd;
126 unsigned long rx_msg_type_ext_no_ptp;
127 unsigned long rx_msg_type_sync;
128 unsigned long rx_msg_type_follow_up;
129 unsigned long rx_msg_type_delay_req;
130 unsigned long rx_msg_type_delay_resp;
131 unsigned long rx_msg_type_pdelay_req;
132 unsigned long rx_msg_type_pdelay_resp;
133 unsigned long rx_msg_type_pdelay_follow_up;
134 unsigned long ptp_frame_type;
135 unsigned long ptp_ver;
136 unsigned long timestamp_dropped;
137 unsigned long av_pkt_rcvd;
138 unsigned long av_tagged_pkt_rcvd;
139 unsigned long vlan_tag_priority_val;
140 unsigned long l3_filter_match;
141 unsigned long l4_filter_match;
142 unsigned long l3_l4_filter_no_match;
144 unsigned long irq_pcs_ane_n;
145 unsigned long irq_pcs_link_n;
146 unsigned long irq_rgmii_n;
147 unsigned long pcs_link;
148 unsigned long pcs_duplex;
149 unsigned long pcs_speed;
152 /* CSR Frequency Access Defines*/
153 #define CSR_F_35M 35000000
154 #define CSR_F_60M 60000000
155 #define CSR_F_100M 100000000
156 #define CSR_F_150M 150000000
157 #define CSR_F_250M 250000000
158 #define CSR_F_300M 300000000
160 #define MAC_CSR_H_FRQ_MASK 0x20
162 #define HASH_TABLE_SIZE 64
163 #define PAUSE_TIME 0x200
165 /* Flow Control defines */
169 #define FLOW_AUTO (FLOW_TX | FLOW_RX)
172 #define STMMAC_PCS_RGMII (1 << 0)
173 #define STMMAC_PCS_SGMII (1 << 1)
174 #define STMMAC_PCS_TBI (1 << 2)
175 #define STMMAC_PCS_RTBI (1 << 3)
177 #define SF_DMA_MODE 1 /* DMA STORE-AND-FORWARD Operation Mode */
179 /* DAM HW feature register fields */
180 #define DMA_HW_FEAT_MIISEL 0x00000001 /* 10/100 Mbps Support */
181 #define DMA_HW_FEAT_GMIISEL 0x00000002 /* 1000 Mbps Support */
182 #define DMA_HW_FEAT_HDSEL 0x00000004 /* Half-Duplex Support */
183 #define DMA_HW_FEAT_EXTHASHEN 0x00000008 /* Expanded DA Hash Filter */
184 #define DMA_HW_FEAT_HASHSEL 0x00000010 /* HASH Filter */
185 #define DMA_HW_FEAT_ADDMACADRSEL 0x00000020 /* Multiple MAC Addr Reg */
186 #define DMA_HW_FEAT_PCSSEL 0x00000040 /* PCS registers */
187 #define DMA_HW_FEAT_L3L4FLTREN 0x00000080 /* Layer 3 & Layer 4 Feature */
188 #define DMA_HW_FEAT_SMASEL 0x00000100 /* SMA(MDIO) Interface */
189 #define DMA_HW_FEAT_RWKSEL 0x00000200 /* PMT Remote Wakeup */
190 #define DMA_HW_FEAT_MGKSEL 0x00000400 /* PMT Magic Packet */
191 #define DMA_HW_FEAT_MMCSEL 0x00000800 /* RMON Module */
192 #define DMA_HW_FEAT_TSVER1SEL 0x00001000 /* Only IEEE 1588-2002 Timestamp */
193 #define DMA_HW_FEAT_TSVER2SEL 0x00002000 /* IEEE 1588-2008 Adv Timestamp */
194 #define DMA_HW_FEAT_EEESEL 0x00004000 /* Energy Efficient Ethernet */
195 #define DMA_HW_FEAT_AVSEL 0x00008000 /* AV Feature */
196 #define DMA_HW_FEAT_TXCOESEL 0x00010000 /* Checksum Offload in Tx */
197 #define DMA_HW_FEAT_RXTYP1COE 0x00020000 /* IP csum Offload(Type 1) in Rx */
198 #define DMA_HW_FEAT_RXTYP2COE 0x00040000 /* IP csum Offload(Type 2) in Rx */
199 #define DMA_HW_FEAT_RXFIFOSIZE 0x00080000 /* Rx FIFO > 2048 Bytes */
200 #define DMA_HW_FEAT_RXCHCNT 0x00300000 /* No. of additional Rx Channels */
201 #define DMA_HW_FEAT_TXCHCNT 0x00c00000 /* No. of additional Tx Channels */
202 #define DMA_HW_FEAT_ENHDESSEL 0x01000000 /* Alternate (Enhanced Descriptor) */
203 #define DMA_HW_FEAT_INTTSEN 0x02000000 /* Timestamping with Internal
205 #define DMA_HW_FEAT_FLEXIPPSEN 0x04000000 /* Flexible PPS Output */
206 #define DMA_HW_FEAT_SAVLANINS 0x08000000 /* Source Addr or VLAN Insertion */
207 #define DMA_HW_FEAT_ACTPHYIF 0x70000000 /* Active/selected PHY interface */
208 #define DEFAULT_DMA_PBL 8
210 /* Max/Min RI Watchdog Timer count value */
211 #define MAX_DMA_RIWT 0xff
212 #define MIN_DMA_RIWT 0x20
213 /* Tx coalesce parameters */
214 #define STMMAC_COAL_TX_TIMER 40000
215 #define STMMAC_MAX_COAL_TX_TICK 100000
216 #define STMMAC_TX_MAX_FRAMES 256
217 #define STMMAC_TX_FRAMES 64
219 enum rx_frame_status { /* IPC status */
226 enum dma_irq_status {
228 tx_hard_error_bump_tc = 0x2,
233 #define CORE_IRQ_TX_PATH_IN_LPI_MODE (1 << 1)
234 #define CORE_IRQ_TX_PATH_EXIT_LPI_MODE (1 << 2)
235 #define CORE_IRQ_RX_PATH_IN_LPI_MODE (1 << 3)
236 #define CORE_IRQ_RX_PATH_EXIT_LPI_MODE (1 << 4)
238 #define CORE_PCS_ANE_COMPLETE (1 << 5)
239 #define CORE_PCS_LINK_STATUS (1 << 6)
240 #define CORE_RGMII_IRQ (1 << 7)
245 unsigned int lp_pause;
246 unsigned int lp_duplex;
249 #define STMMAC_PCS_PAUSE 1
250 #define STMMAC_PCS_ASYM_PAUSE 2
252 /* DMA HW capabilities */
253 struct dma_features {
254 unsigned int mbps_10_100;
255 unsigned int mbps_1000;
256 unsigned int half_duplex;
257 unsigned int hash_filter;
258 unsigned int multi_addr;
260 unsigned int sma_mdio;
261 unsigned int pmt_remote_wake_up;
262 unsigned int pmt_magic_frame;
265 unsigned int time_stamp;
267 unsigned int atime_stamp;
268 /* 802.3az - Energy-Efficient Ethernet (EEE) */
273 unsigned int rx_coe_type1;
274 unsigned int rx_coe_type2;
275 unsigned int rxfifo_over_2048;
276 /* TX and RX number of channels */
277 unsigned int number_rx_channel;
278 unsigned int number_tx_channel;
279 /* Alternate (enhanced) DESC mode*/
280 unsigned int enh_desc;
283 /* GMAC TX FIFO is 8K, Rx FIFO is 16K */
284 #define BUF_SIZE_16KiB 16384
285 #define BUF_SIZE_8KiB 8192
286 #define BUF_SIZE_4KiB 4096
287 #define BUF_SIZE_2KiB 2048
289 /* Power Down and WOL */
290 #define PMT_NOT_SUPPORTED 0
291 #define PMT_SUPPORTED 1
293 /* Common MAC defines */
294 #define MAC_CTRL_REG 0x00000000 /* MAC Control */
295 #define MAC_ENABLE_TX 0x00000008 /* Transmitter Enable */
296 #define MAC_RNABLE_RX 0x00000004 /* Receiver Enable */
298 /* Default LPI timers */
299 #define STMMAC_DEFAULT_LIT_LS_TIMER 0x3E8
300 #define STMMAC_DEFAULT_TWT_LS_TIMER 0x0
302 #define STMMAC_CHAIN_MODE 0x1
303 #define STMMAC_RING_MODE 0x2
305 struct stmmac_desc_ops {
306 /* DMA RX descriptor ring initialization */
307 void (*init_rx_desc) (struct dma_desc *p, int disable_rx_ic, int mode,
309 /* DMA TX descriptor ring initialization */
310 void (*init_tx_desc) (struct dma_desc *p, int mode, int end);
312 /* Invoked by the xmit function to prepare the tx descriptor */
313 void (*prepare_tx_desc) (struct dma_desc *p, int is_fs, int len,
314 int csum_flag, int mode);
315 /* Set/get the owner of the descriptor */
316 void (*set_tx_owner) (struct dma_desc *p);
317 int (*get_tx_owner) (struct dma_desc *p);
318 /* Invoked by the xmit function to close the tx descriptor */
319 void (*close_tx_desc) (struct dma_desc *p);
320 /* Clean the tx descriptor as soon as the tx irq is received */
321 void (*release_tx_desc) (struct dma_desc *p, int mode);
322 /* Clear interrupt on tx frame completion. When this bit is
323 * set an interrupt happens as soon as the frame is transmitted */
324 void (*clear_tx_ic) (struct dma_desc *p);
325 /* Last tx segment reports the transmit status */
326 int (*get_tx_ls) (struct dma_desc *p);
327 /* Return the transmit status looking at the TDES1 */
328 int (*tx_status) (void *data, struct stmmac_extra_stats *x,
329 struct dma_desc *p, void __iomem *ioaddr);
330 /* Get the buffer size from the descriptor */
331 int (*get_tx_len) (struct dma_desc *p);
332 /* Handle extra events on specific interrupts hw dependent */
333 int (*get_rx_owner) (struct dma_desc *p);
334 void (*set_rx_owner) (struct dma_desc *p);
335 /* Get the receive frame size */
336 int (*get_rx_frame_len) (struct dma_desc *p, int rx_coe_type);
337 /* Return the reception status looking at the RDES1 */
338 int (*rx_status) (void *data, struct stmmac_extra_stats *x,
340 void (*rx_extended_status) (void *data, struct stmmac_extra_stats *x,
341 struct dma_extended_desc *p);
342 /* Set tx timestamp enable bit */
343 void (*enable_tx_timestamp) (struct dma_desc *p);
344 /* get tx timestamp status */
345 int (*get_tx_timestamp_status) (struct dma_desc *p);
346 /* get timestamp value */
347 u64 (*get_timestamp) (void *desc, u32 ats);
348 /* get rx timestamp status */
349 int (*get_rx_timestamp_status) (void *desc, u32 ats);
352 struct stmmac_dma_ops {
353 /* DMA core initialization */
354 int (*init) (void __iomem *ioaddr, int pbl, int fb, int mb,
355 int burst_len, u32 dma_tx, u32 dma_rx, int atds);
356 /* Dump DMA registers */
357 void (*dump_regs) (void __iomem *ioaddr);
358 /* Set tx/rx threshold in the csr6 register
359 * An invalid value enables the store-and-forward mode */
360 void (*dma_mode) (void __iomem *ioaddr, int txmode, int rxmode);
361 /* To track extra statistic (if supported) */
362 void (*dma_diagnostic_fr) (void *data, struct stmmac_extra_stats *x,
363 void __iomem *ioaddr);
364 void (*enable_dma_transmission) (void __iomem *ioaddr);
365 void (*enable_dma_irq) (void __iomem *ioaddr);
366 void (*disable_dma_irq) (void __iomem *ioaddr);
367 void (*start_tx) (void __iomem *ioaddr);
368 void (*stop_tx) (void __iomem *ioaddr);
369 void (*start_rx) (void __iomem *ioaddr);
370 void (*stop_rx) (void __iomem *ioaddr);
371 int (*dma_interrupt) (void __iomem *ioaddr,
372 struct stmmac_extra_stats *x);
373 /* If supported then get the optional core features */
374 unsigned int (*get_hw_feature) (void __iomem *ioaddr);
375 /* Program the HW RX Watchdog */
376 void (*rx_watchdog) (void __iomem *ioaddr, u32 riwt);
380 /* MAC core initialization */
381 void (*core_init) (void __iomem *ioaddr) ____cacheline_aligned;
382 /* Enable and verify that the IPC module is supported */
383 int (*rx_ipc) (void __iomem *ioaddr);
384 /* Dump MAC registers */
385 void (*dump_regs) (void __iomem *ioaddr);
386 /* Handle extra events on specific interrupts hw dependent */
387 int (*host_irq_status) (void __iomem *ioaddr,
388 struct stmmac_extra_stats *x);
389 /* Multicast filter setting */
390 void (*set_filter) (struct net_device *dev, int id);
391 /* Flow control setting */
392 void (*flow_ctrl) (void __iomem *ioaddr, unsigned int duplex,
393 unsigned int fc, unsigned int pause_time);
394 /* Set power management mode (e.g. magic frame) */
395 void (*pmt) (void __iomem *ioaddr, unsigned long mode);
396 /* Set/Get Unicast MAC addresses */
397 void (*set_umac_addr) (void __iomem *ioaddr, unsigned char *addr,
399 void (*get_umac_addr) (void __iomem *ioaddr, unsigned char *addr,
401 void (*set_eee_mode) (void __iomem *ioaddr);
402 void (*reset_eee_mode) (void __iomem *ioaddr);
403 void (*set_eee_timer) (void __iomem *ioaddr, int ls, int tw);
404 void (*set_eee_pls) (void __iomem *ioaddr, int link);
405 void (*ctrl_ane) (void __iomem *ioaddr, bool restart);
406 void (*get_adv) (void __iomem *ioaddr, struct rgmii_adv *adv);
409 struct stmmac_hwtimestamp {
410 void (*config_hw_tstamping) (void __iomem *ioaddr, u32 data);
411 void (*config_sub_second_increment) (void __iomem *ioaddr);
412 int (*init_systime) (void __iomem *ioaddr, u32 sec, u32 nsec);
413 int (*config_addend)(void __iomem *ioaddr, u32 addend);
423 unsigned int addr; /* MII Address */
424 unsigned int data; /* MII Data */
427 struct stmmac_ring_mode_ops {
428 unsigned int (*is_jumbo_frm) (int len, int ehn_desc);
429 unsigned int (*jumbo_frm) (void *priv, struct sk_buff *skb, int csum);
430 void (*refill_desc3) (void *priv, struct dma_desc *p);
431 void (*init_desc3) (struct dma_desc *p);
432 void (*clean_desc3) (void *priv, struct dma_desc *p);
433 int (*set_16kib_bfsize) (int mtu);
436 struct stmmac_chain_mode_ops {
437 void (*init) (void *des, dma_addr_t phy_addr, unsigned int size,
438 unsigned int extend_desc);
439 unsigned int (*is_jumbo_frm) (int len, int ehn_desc);
440 unsigned int (*jumbo_frm) (void *priv, struct sk_buff *skb, int csum);
441 void (*refill_desc3) (void *priv, struct dma_desc *p);
442 void (*clean_desc3) (void *priv, struct dma_desc *p);
445 struct mac_device_info {
446 const struct stmmac_ops *mac;
447 const struct stmmac_desc_ops *desc;
448 const struct stmmac_dma_ops *dma;
449 const struct stmmac_ring_mode_ops *ring;
450 const struct stmmac_chain_mode_ops *chain;
451 const struct stmmac_hwtimestamp *ptp;
452 struct mii_regs mii; /* MII register Addresses */
453 struct mac_link link;
454 unsigned int synopsys_uid;
457 struct mac_device_info *dwmac1000_setup(void __iomem *ioaddr);
458 struct mac_device_info *dwmac100_setup(void __iomem *ioaddr);
460 extern void stmmac_set_mac_addr(void __iomem *ioaddr, u8 addr[6],
461 unsigned int high, unsigned int low);
462 extern void stmmac_get_mac_addr(void __iomem *ioaddr, unsigned char *addr,
463 unsigned int high, unsigned int low);
465 extern void stmmac_set_mac(void __iomem *ioaddr, bool enable);
467 extern void dwmac_dma_flush_tx_fifo(void __iomem *ioaddr);
468 extern const struct stmmac_ring_mode_ops ring_mode_ops;
469 extern const struct stmmac_chain_mode_ops chain_mode_ops;
471 #endif /* __COMMON_H__ */