1 /*******************************************************************************
2 STMMAC Common Header File
4 Copyright (C) 2007-2009 STMicroelectronics Ltd
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
22 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
23 *******************************************************************************/
28 #include <linux/etherdevice.h>
29 #include <linux/netdevice.h>
30 #include <linux/phy.h>
31 #include <linux/module.h>
32 #include <linux/init.h>
33 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
34 #define STMMAC_VLAN_TAG_USED
35 #include <linux/if_vlan.h>
41 #undef CHIP_DEBUG_PRINT
42 /* Turn-on extra printk debug for MAC core, dma and descriptors */
43 /* #define CHIP_DEBUG_PRINT */
45 #ifdef CHIP_DEBUG_PRINT
46 #define CHIP_DBG(fmt, args...) printk(fmt, ## args)
48 #define CHIP_DBG(fmt, args...) do { } while (0)
51 /* Synopsys Core versions */
52 #define DWMAC_CORE_3_40 0x34
53 #define DWMAC_CORE_3_50 0x35
55 #undef FRAME_FILTER_DEBUG
56 /* #define FRAME_FILTER_DEBUG */
58 struct stmmac_extra_stats {
60 unsigned long tx_underflow ____cacheline_aligned;
61 unsigned long tx_carrier;
62 unsigned long tx_losscarrier;
63 unsigned long vlan_tag;
64 unsigned long tx_deferred;
65 unsigned long tx_vlan;
66 unsigned long tx_jabber;
67 unsigned long tx_frame_flushed;
68 unsigned long tx_payload_error;
69 unsigned long tx_ip_header_error;
71 unsigned long rx_desc;
72 unsigned long sa_filter_fail;
73 unsigned long overflow_error;
74 unsigned long ipc_csum_error;
75 unsigned long rx_collision;
77 unsigned long dribbling_bit;
78 unsigned long rx_length;
80 unsigned long rx_multicast;
81 unsigned long rx_gmac_overflow;
82 unsigned long rx_watchdog;
83 unsigned long da_rx_filter_fail;
84 unsigned long sa_rx_filter_fail;
85 unsigned long rx_missed_cntr;
86 unsigned long rx_overflow_cntr;
87 unsigned long rx_vlan;
88 /* Tx/Rx IRQ error info */
89 unsigned long tx_undeflow_irq;
90 unsigned long tx_process_stopped_irq;
91 unsigned long tx_jabber_irq;
92 unsigned long rx_overflow_irq;
93 unsigned long rx_buf_unav_irq;
94 unsigned long rx_process_stopped_irq;
95 unsigned long rx_watchdog_irq;
96 unsigned long tx_early_irq;
97 unsigned long fatal_bus_error_irq;
98 /* Tx/Rx IRQ Events */
99 unsigned long rx_early_irq;
100 unsigned long threshold;
101 unsigned long tx_pkt_n;
102 unsigned long rx_pkt_n;
103 unsigned long normal_irq_n;
104 unsigned long rx_normal_irq_n;
105 unsigned long napi_poll;
106 unsigned long tx_normal_irq_n;
107 unsigned long tx_clean;
108 unsigned long tx_reset_ic_bit;
109 unsigned long irq_receive_pmt_irq_n;
111 unsigned long mmc_tx_irq_n;
112 unsigned long mmc_rx_irq_n;
113 unsigned long mmc_rx_csum_offload_irq_n;
115 unsigned long irq_tx_path_in_lpi_mode_n;
116 unsigned long irq_tx_path_exit_lpi_mode_n;
117 unsigned long irq_rx_path_in_lpi_mode_n;
118 unsigned long irq_rx_path_exit_lpi_mode_n;
119 unsigned long phy_eee_wakeup_error_n;
122 /* CSR Frequency Access Defines*/
123 #define CSR_F_35M 35000000
124 #define CSR_F_60M 60000000
125 #define CSR_F_100M 100000000
126 #define CSR_F_150M 150000000
127 #define CSR_F_250M 250000000
128 #define CSR_F_300M 300000000
130 #define MAC_CSR_H_FRQ_MASK 0x20
132 #define HASH_TABLE_SIZE 64
133 #define PAUSE_TIME 0x200
135 /* Flow Control defines */
139 #define FLOW_AUTO (FLOW_TX | FLOW_RX)
141 #define SF_DMA_MODE 1 /* DMA STORE-AND-FORWARD Operation Mode */
143 /* DAM HW feature register fields */
144 #define DMA_HW_FEAT_MIISEL 0x00000001 /* 10/100 Mbps Support */
145 #define DMA_HW_FEAT_GMIISEL 0x00000002 /* 1000 Mbps Support */
146 #define DMA_HW_FEAT_HDSEL 0x00000004 /* Half-Duplex Support */
147 #define DMA_HW_FEAT_EXTHASHEN 0x00000008 /* Expanded DA Hash Filter */
148 #define DMA_HW_FEAT_HASHSEL 0x00000010 /* HASH Filter */
149 #define DMA_HW_FEAT_ADDMACADRSEL 0x00000020 /* Multiple MAC Addr Reg */
150 #define DMA_HW_FEAT_PCSSEL 0x00000040 /* PCS registers */
151 #define DMA_HW_FEAT_L3L4FLTREN 0x00000080 /* Layer 3 & Layer 4 Feature */
152 #define DMA_HW_FEAT_SMASEL 0x00000100 /* SMA(MDIO) Interface */
153 #define DMA_HW_FEAT_RWKSEL 0x00000200 /* PMT Remote Wakeup */
154 #define DMA_HW_FEAT_MGKSEL 0x00000400 /* PMT Magic Packet */
155 #define DMA_HW_FEAT_MMCSEL 0x00000800 /* RMON Module */
156 #define DMA_HW_FEAT_TSVER1SEL 0x00001000 /* Only IEEE 1588-2002 Timestamp */
157 #define DMA_HW_FEAT_TSVER2SEL 0x00002000 /* IEEE 1588-2008 Adv Timestamp */
158 #define DMA_HW_FEAT_EEESEL 0x00004000 /* Energy Efficient Ethernet */
159 #define DMA_HW_FEAT_AVSEL 0x00008000 /* AV Feature */
160 #define DMA_HW_FEAT_TXCOESEL 0x00010000 /* Checksum Offload in Tx */
161 #define DMA_HW_FEAT_RXTYP1COE 0x00020000 /* IP csum Offload(Type 1) in Rx */
162 #define DMA_HW_FEAT_RXTYP2COE 0x00040000 /* IP csum Offload(Type 2) in Rx */
163 #define DMA_HW_FEAT_RXFIFOSIZE 0x00080000 /* Rx FIFO > 2048 Bytes */
164 #define DMA_HW_FEAT_RXCHCNT 0x00300000 /* No. of additional Rx Channels */
165 #define DMA_HW_FEAT_TXCHCNT 0x00c00000 /* No. of additional Tx Channels */
166 #define DMA_HW_FEAT_ENHDESSEL 0x01000000 /* Alternate (Enhanced Descriptor) */
167 #define DMA_HW_FEAT_INTTSEN 0x02000000 /* Timestamping with Internal
169 #define DMA_HW_FEAT_FLEXIPPSEN 0x04000000 /* Flexible PPS Output */
170 #define DMA_HW_FEAT_SAVLANINS 0x08000000 /* Source Addr or VLAN Insertion */
171 #define DMA_HW_FEAT_ACTPHYIF 0x70000000 /* Active/selected PHY interface */
172 #define DEFAULT_DMA_PBL 8
174 /* Max/Min RI Watchdog Timer count value */
175 #define MAX_DMA_RIWT 0xff
176 #define MIN_DMA_RIWT 0x20
177 /* Tx coalesce parameters */
178 #define STMMAC_COAL_TX_TIMER 40000
179 #define STMMAC_MAX_COAL_TX_TICK 100000
180 #define STMMAC_TX_MAX_FRAMES 256
181 #define STMMAC_TX_FRAMES 64
183 enum rx_frame_status { /* IPC status */
190 enum dma_irq_status {
192 tx_hard_error_bump_tc = 0x2,
197 enum core_specific_irq_mask {
200 core_mmc_rx_csum_offload_irq = 4,
201 core_irq_receive_pmt_irq = 8,
202 core_irq_tx_path_in_lpi_mode = 16,
203 core_irq_tx_path_exit_lpi_mode = 32,
204 core_irq_rx_path_in_lpi_mode = 64,
205 core_irq_rx_path_exit_lpi_mode = 128,
208 /* DMA HW capabilities */
209 struct dma_features {
210 unsigned int mbps_10_100;
211 unsigned int mbps_1000;
212 unsigned int half_duplex;
213 unsigned int hash_filter;
214 unsigned int multi_addr;
216 unsigned int sma_mdio;
217 unsigned int pmt_remote_wake_up;
218 unsigned int pmt_magic_frame;
221 unsigned int time_stamp;
223 unsigned int atime_stamp;
224 /* 802.3az - Energy-Efficient Ethernet (EEE) */
229 unsigned int rx_coe_type1;
230 unsigned int rx_coe_type2;
231 unsigned int rxfifo_over_2048;
232 /* TX and RX number of channels */
233 unsigned int number_rx_channel;
234 unsigned int number_tx_channel;
235 /* Alternate (enhanced) DESC mode*/
236 unsigned int enh_desc;
239 /* GMAC TX FIFO is 8K, Rx FIFO is 16K */
240 #define BUF_SIZE_16KiB 16384
241 #define BUF_SIZE_8KiB 8192
242 #define BUF_SIZE_4KiB 4096
243 #define BUF_SIZE_2KiB 2048
245 /* Power Down and WOL */
246 #define PMT_NOT_SUPPORTED 0
247 #define PMT_SUPPORTED 1
249 /* Common MAC defines */
250 #define MAC_CTRL_REG 0x00000000 /* MAC Control */
251 #define MAC_ENABLE_TX 0x00000008 /* Transmitter Enable */
252 #define MAC_RNABLE_RX 0x00000004 /* Receiver Enable */
254 /* Default LPI timers */
255 #define STMMAC_DEFAULT_LIT_LS_TIMER 0x3E8
256 #define STMMAC_DEFAULT_TWT_LS_TIMER 0x0
258 struct stmmac_desc_ops {
259 /* DMA RX descriptor ring initialization */
260 void (*init_rx_desc) (struct dma_desc *p, unsigned int ring_size,
262 /* DMA TX descriptor ring initialization */
263 void (*init_tx_desc) (struct dma_desc *p, unsigned int ring_size);
265 /* Invoked by the xmit function to prepare the tx descriptor */
266 void (*prepare_tx_desc) (struct dma_desc *p, int is_fs, int len,
268 /* Set/get the owner of the descriptor */
269 void (*set_tx_owner) (struct dma_desc *p);
270 int (*get_tx_owner) (struct dma_desc *p);
271 /* Invoked by the xmit function to close the tx descriptor */
272 void (*close_tx_desc) (struct dma_desc *p);
273 /* Clean the tx descriptor as soon as the tx irq is received */
274 void (*release_tx_desc) (struct dma_desc *p);
275 /* Clear interrupt on tx frame completion. When this bit is
276 * set an interrupt happens as soon as the frame is transmitted */
277 void (*clear_tx_ic) (struct dma_desc *p);
278 /* Last tx segment reports the transmit status */
279 int (*get_tx_ls) (struct dma_desc *p);
280 /* Return the transmit status looking at the TDES1 */
281 int (*tx_status) (void *data, struct stmmac_extra_stats *x,
282 struct dma_desc *p, void __iomem *ioaddr);
283 /* Get the buffer size from the descriptor */
284 int (*get_tx_len) (struct dma_desc *p);
285 /* Handle extra events on specific interrupts hw dependent */
286 int (*get_rx_owner) (struct dma_desc *p);
287 void (*set_rx_owner) (struct dma_desc *p);
288 /* Get the receive frame size */
289 int (*get_rx_frame_len) (struct dma_desc *p, int rx_coe_type);
290 /* Return the reception status looking at the RDES1 */
291 int (*rx_status) (void *data, struct stmmac_extra_stats *x,
295 struct stmmac_dma_ops {
296 /* DMA core initialization */
297 int (*init) (void __iomem *ioaddr, int pbl, int fb, int mb,
298 int burst_len, u32 dma_tx, u32 dma_rx);
299 /* Dump DMA registers */
300 void (*dump_regs) (void __iomem *ioaddr);
301 /* Set tx/rx threshold in the csr6 register
302 * An invalid value enables the store-and-forward mode */
303 void (*dma_mode) (void __iomem *ioaddr, int txmode, int rxmode);
304 /* To track extra statistic (if supported) */
305 void (*dma_diagnostic_fr) (void *data, struct stmmac_extra_stats *x,
306 void __iomem *ioaddr);
307 void (*enable_dma_transmission) (void __iomem *ioaddr);
308 void (*enable_dma_irq) (void __iomem *ioaddr);
309 void (*disable_dma_irq) (void __iomem *ioaddr);
310 void (*start_tx) (void __iomem *ioaddr);
311 void (*stop_tx) (void __iomem *ioaddr);
312 void (*start_rx) (void __iomem *ioaddr);
313 void (*stop_rx) (void __iomem *ioaddr);
314 int (*dma_interrupt) (void __iomem *ioaddr,
315 struct stmmac_extra_stats *x);
316 /* If supported then get the optional core features */
317 unsigned int (*get_hw_feature) (void __iomem *ioaddr);
318 /* Program the HW RX Watchdog */
319 void (*rx_watchdog) (void __iomem *ioaddr, u32 riwt);
323 /* MAC core initialization */
324 void (*core_init) (void __iomem *ioaddr) ____cacheline_aligned;
325 /* Enable and verify that the IPC module is supported */
326 int (*rx_ipc) (void __iomem *ioaddr);
327 /* Dump MAC registers */
328 void (*dump_regs) (void __iomem *ioaddr);
329 /* Handle extra events on specific interrupts hw dependent */
330 int (*host_irq_status) (void __iomem *ioaddr);
331 /* Multicast filter setting */
332 void (*set_filter) (struct net_device *dev, int id);
333 /* Flow control setting */
334 void (*flow_ctrl) (void __iomem *ioaddr, unsigned int duplex,
335 unsigned int fc, unsigned int pause_time);
336 /* Set power management mode (e.g. magic frame) */
337 void (*pmt) (void __iomem *ioaddr, unsigned long mode);
338 /* Set/Get Unicast MAC addresses */
339 void (*set_umac_addr) (void __iomem *ioaddr, unsigned char *addr,
341 void (*get_umac_addr) (void __iomem *ioaddr, unsigned char *addr,
343 void (*set_eee_mode) (void __iomem *ioaddr);
344 void (*reset_eee_mode) (void __iomem *ioaddr);
345 void (*set_eee_timer) (void __iomem *ioaddr, int ls, int tw);
346 void (*set_eee_pls) (void __iomem *ioaddr, int link);
356 unsigned int addr; /* MII Address */
357 unsigned int data; /* MII Data */
360 struct stmmac_ring_mode_ops {
361 unsigned int (*is_jumbo_frm) (int len, int ehn_desc);
362 unsigned int (*jumbo_frm) (void *priv, struct sk_buff *skb, int csum);
363 void (*refill_desc3) (int bfsize, struct dma_desc *p);
364 void (*init_desc3) (int des3_as_data_buf, struct dma_desc *p);
365 void (*init_dma_chain) (struct dma_desc *des, dma_addr_t phy_addr,
367 void (*clean_desc3) (struct dma_desc *p);
368 int (*set_16kib_bfsize) (int mtu);
371 struct mac_device_info {
372 const struct stmmac_ops *mac;
373 const struct stmmac_desc_ops *desc;
374 const struct stmmac_dma_ops *dma;
375 const struct stmmac_ring_mode_ops *ring;
376 struct mii_regs mii; /* MII register Addresses */
377 struct mac_link link;
378 unsigned int synopsys_uid;
381 struct mac_device_info *dwmac1000_setup(void __iomem *ioaddr);
382 struct mac_device_info *dwmac100_setup(void __iomem *ioaddr);
384 extern void stmmac_set_mac_addr(void __iomem *ioaddr, u8 addr[6],
385 unsigned int high, unsigned int low);
386 extern void stmmac_get_mac_addr(void __iomem *ioaddr, unsigned char *addr,
387 unsigned int high, unsigned int low);
389 extern void stmmac_set_mac(void __iomem *ioaddr, bool enable);
391 extern void dwmac_dma_flush_tx_fifo(void __iomem *ioaddr);
392 extern const struct stmmac_ring_mode_ops ring_mode_ops;
394 #endif /* __COMMON_H__ */