1 /*******************************************************************************
2 STMMAC Common Header File
4 Copyright (C) 2007-2009 STMicroelectronics Ltd
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
22 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
23 *******************************************************************************/
28 #include <linux/etherdevice.h>
29 #include <linux/netdevice.h>
30 #include <linux/phy.h>
31 #include <linux/module.h>
32 #include <linux/init.h>
33 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
34 #define STMMAC_VLAN_TAG_USED
35 #include <linux/if_vlan.h>
41 #undef CHIP_DEBUG_PRINT
42 /* Turn-on extra printk debug for MAC core, dma and descriptors */
43 /* #define CHIP_DEBUG_PRINT */
45 #ifdef CHIP_DEBUG_PRINT
46 #define CHIP_DBG(fmt, args...) printk(fmt, ## args)
48 #define CHIP_DBG(fmt, args...) do { } while (0)
51 /* Synopsys Core versions */
52 #define DWMAC_CORE_3_40 0x34
53 #define DWMAC_CORE_3_50 0x35
55 #undef FRAME_FILTER_DEBUG
56 /* #define FRAME_FILTER_DEBUG */
58 struct stmmac_extra_stats {
60 unsigned long tx_underflow ____cacheline_aligned;
61 unsigned long tx_carrier;
62 unsigned long tx_losscarrier;
63 unsigned long vlan_tag;
64 unsigned long tx_deferred;
65 unsigned long tx_vlan;
66 unsigned long tx_jabber;
67 unsigned long tx_frame_flushed;
68 unsigned long tx_payload_error;
69 unsigned long tx_ip_header_error;
71 unsigned long rx_desc;
72 unsigned long sa_filter_fail;
73 unsigned long overflow_error;
74 unsigned long ipc_csum_error;
75 unsigned long rx_collision;
77 unsigned long dribbling_bit;
78 unsigned long rx_length;
80 unsigned long rx_multicast;
81 unsigned long rx_gmac_overflow;
82 unsigned long rx_watchdog;
83 unsigned long da_rx_filter_fail;
84 unsigned long sa_rx_filter_fail;
85 unsigned long rx_missed_cntr;
86 unsigned long rx_overflow_cntr;
87 unsigned long rx_vlan;
88 /* Tx/Rx IRQ error info */
89 unsigned long tx_undeflow_irq;
90 unsigned long tx_process_stopped_irq;
91 unsigned long tx_jabber_irq;
92 unsigned long rx_overflow_irq;
93 unsigned long rx_buf_unav_irq;
94 unsigned long rx_process_stopped_irq;
95 unsigned long rx_watchdog_irq;
96 unsigned long tx_early_irq;
97 unsigned long fatal_bus_error_irq;
98 /* Tx/Rx IRQ Events */
99 unsigned long rx_early_irq;
100 unsigned long threshold;
101 unsigned long tx_pkt_n;
102 unsigned long rx_pkt_n;
103 unsigned long normal_irq_n;
104 unsigned long rx_normal_irq_n;
105 unsigned long napi_poll;
106 unsigned long tx_normal_irq_n;
107 unsigned long tx_clean;
108 unsigned long tx_reset_ic_bit;
109 unsigned long irq_receive_pmt_irq_n;
111 unsigned long mmc_tx_irq_n;
112 unsigned long mmc_rx_irq_n;
113 unsigned long mmc_rx_csum_offload_irq_n;
115 unsigned long irq_tx_path_in_lpi_mode_n;
116 unsigned long irq_tx_path_exit_lpi_mode_n;
117 unsigned long irq_rx_path_in_lpi_mode_n;
118 unsigned long irq_rx_path_exit_lpi_mode_n;
119 unsigned long phy_eee_wakeup_error_n;
120 /* Extended RDES status */
121 unsigned long ip_hdr_err;
122 unsigned long ip_payload_err;
123 unsigned long ip_csum_bypassed;
124 unsigned long ipv4_pkt_rcvd;
125 unsigned long ipv6_pkt_rcvd;
126 unsigned long rx_msg_type_ext_no_ptp;
127 unsigned long rx_msg_type_sync;
128 unsigned long rx_msg_type_follow_up;
129 unsigned long rx_msg_type_delay_req;
130 unsigned long rx_msg_type_delay_resp;
131 unsigned long rx_msg_type_pdelay_req;
132 unsigned long rx_msg_type_pdelay_resp;
133 unsigned long rx_msg_type_pdelay_follow_up;
134 unsigned long ptp_frame_type;
135 unsigned long ptp_ver;
136 unsigned long timestamp_dropped;
137 unsigned long av_pkt_rcvd;
138 unsigned long av_tagged_pkt_rcvd;
139 unsigned long vlan_tag_priority_val;
140 unsigned long l3_filter_match;
141 unsigned long l4_filter_match;
142 unsigned long l3_l4_filter_no_match;
145 /* CSR Frequency Access Defines*/
146 #define CSR_F_35M 35000000
147 #define CSR_F_60M 60000000
148 #define CSR_F_100M 100000000
149 #define CSR_F_150M 150000000
150 #define CSR_F_250M 250000000
151 #define CSR_F_300M 300000000
153 #define MAC_CSR_H_FRQ_MASK 0x20
155 #define HASH_TABLE_SIZE 64
156 #define PAUSE_TIME 0x200
158 /* Flow Control defines */
162 #define FLOW_AUTO (FLOW_TX | FLOW_RX)
164 #define SF_DMA_MODE 1 /* DMA STORE-AND-FORWARD Operation Mode */
166 /* DAM HW feature register fields */
167 #define DMA_HW_FEAT_MIISEL 0x00000001 /* 10/100 Mbps Support */
168 #define DMA_HW_FEAT_GMIISEL 0x00000002 /* 1000 Mbps Support */
169 #define DMA_HW_FEAT_HDSEL 0x00000004 /* Half-Duplex Support */
170 #define DMA_HW_FEAT_EXTHASHEN 0x00000008 /* Expanded DA Hash Filter */
171 #define DMA_HW_FEAT_HASHSEL 0x00000010 /* HASH Filter */
172 #define DMA_HW_FEAT_ADDMACADRSEL 0x00000020 /* Multiple MAC Addr Reg */
173 #define DMA_HW_FEAT_PCSSEL 0x00000040 /* PCS registers */
174 #define DMA_HW_FEAT_L3L4FLTREN 0x00000080 /* Layer 3 & Layer 4 Feature */
175 #define DMA_HW_FEAT_SMASEL 0x00000100 /* SMA(MDIO) Interface */
176 #define DMA_HW_FEAT_RWKSEL 0x00000200 /* PMT Remote Wakeup */
177 #define DMA_HW_FEAT_MGKSEL 0x00000400 /* PMT Magic Packet */
178 #define DMA_HW_FEAT_MMCSEL 0x00000800 /* RMON Module */
179 #define DMA_HW_FEAT_TSVER1SEL 0x00001000 /* Only IEEE 1588-2002 Timestamp */
180 #define DMA_HW_FEAT_TSVER2SEL 0x00002000 /* IEEE 1588-2008 Adv Timestamp */
181 #define DMA_HW_FEAT_EEESEL 0x00004000 /* Energy Efficient Ethernet */
182 #define DMA_HW_FEAT_AVSEL 0x00008000 /* AV Feature */
183 #define DMA_HW_FEAT_TXCOESEL 0x00010000 /* Checksum Offload in Tx */
184 #define DMA_HW_FEAT_RXTYP1COE 0x00020000 /* IP csum Offload(Type 1) in Rx */
185 #define DMA_HW_FEAT_RXTYP2COE 0x00040000 /* IP csum Offload(Type 2) in Rx */
186 #define DMA_HW_FEAT_RXFIFOSIZE 0x00080000 /* Rx FIFO > 2048 Bytes */
187 #define DMA_HW_FEAT_RXCHCNT 0x00300000 /* No. of additional Rx Channels */
188 #define DMA_HW_FEAT_TXCHCNT 0x00c00000 /* No. of additional Tx Channels */
189 #define DMA_HW_FEAT_ENHDESSEL 0x01000000 /* Alternate (Enhanced Descriptor) */
190 #define DMA_HW_FEAT_INTTSEN 0x02000000 /* Timestamping with Internal
192 #define DMA_HW_FEAT_FLEXIPPSEN 0x04000000 /* Flexible PPS Output */
193 #define DMA_HW_FEAT_SAVLANINS 0x08000000 /* Source Addr or VLAN Insertion */
194 #define DMA_HW_FEAT_ACTPHYIF 0x70000000 /* Active/selected PHY interface */
195 #define DEFAULT_DMA_PBL 8
197 /* Max/Min RI Watchdog Timer count value */
198 #define MAX_DMA_RIWT 0xff
199 #define MIN_DMA_RIWT 0x20
200 /* Tx coalesce parameters */
201 #define STMMAC_COAL_TX_TIMER 40000
202 #define STMMAC_MAX_COAL_TX_TICK 100000
203 #define STMMAC_TX_MAX_FRAMES 256
204 #define STMMAC_TX_FRAMES 64
206 enum rx_frame_status { /* IPC status */
213 enum dma_irq_status {
215 tx_hard_error_bump_tc = 0x2,
220 enum core_specific_irq_mask {
223 core_mmc_rx_csum_offload_irq = 4,
224 core_irq_receive_pmt_irq = 8,
225 core_irq_tx_path_in_lpi_mode = 16,
226 core_irq_tx_path_exit_lpi_mode = 32,
227 core_irq_rx_path_in_lpi_mode = 64,
228 core_irq_rx_path_exit_lpi_mode = 128,
231 /* DMA HW capabilities */
232 struct dma_features {
233 unsigned int mbps_10_100;
234 unsigned int mbps_1000;
235 unsigned int half_duplex;
236 unsigned int hash_filter;
237 unsigned int multi_addr;
239 unsigned int sma_mdio;
240 unsigned int pmt_remote_wake_up;
241 unsigned int pmt_magic_frame;
244 unsigned int time_stamp;
246 unsigned int atime_stamp;
247 /* 802.3az - Energy-Efficient Ethernet (EEE) */
252 unsigned int rx_coe_type1;
253 unsigned int rx_coe_type2;
254 unsigned int rxfifo_over_2048;
255 /* TX and RX number of channels */
256 unsigned int number_rx_channel;
257 unsigned int number_tx_channel;
258 /* Alternate (enhanced) DESC mode*/
259 unsigned int enh_desc;
262 /* GMAC TX FIFO is 8K, Rx FIFO is 16K */
263 #define BUF_SIZE_16KiB 16384
264 #define BUF_SIZE_8KiB 8192
265 #define BUF_SIZE_4KiB 4096
266 #define BUF_SIZE_2KiB 2048
268 /* Power Down and WOL */
269 #define PMT_NOT_SUPPORTED 0
270 #define PMT_SUPPORTED 1
272 /* Common MAC defines */
273 #define MAC_CTRL_REG 0x00000000 /* MAC Control */
274 #define MAC_ENABLE_TX 0x00000008 /* Transmitter Enable */
275 #define MAC_RNABLE_RX 0x00000004 /* Receiver Enable */
277 /* Default LPI timers */
278 #define STMMAC_DEFAULT_LIT_LS_TIMER 0x3E8
279 #define STMMAC_DEFAULT_TWT_LS_TIMER 0x0
281 #define STMMAC_CHAIN_MODE 0x1
282 #define STMMAC_RING_MODE 0x2
284 struct stmmac_desc_ops {
285 /* DMA RX descriptor ring initialization */
286 void (*init_rx_desc) (struct dma_desc *p, int disable_rx_ic, int mode,
288 /* DMA TX descriptor ring initialization */
289 void (*init_tx_desc) (struct dma_desc *p, int mode, int end);
291 /* Invoked by the xmit function to prepare the tx descriptor */
292 void (*prepare_tx_desc) (struct dma_desc *p, int is_fs, int len,
293 int csum_flag, int mode);
294 /* Set/get the owner of the descriptor */
295 void (*set_tx_owner) (struct dma_desc *p);
296 int (*get_tx_owner) (struct dma_desc *p);
297 /* Invoked by the xmit function to close the tx descriptor */
298 void (*close_tx_desc) (struct dma_desc *p);
299 /* Clean the tx descriptor as soon as the tx irq is received */
300 void (*release_tx_desc) (struct dma_desc *p, int mode);
301 /* Clear interrupt on tx frame completion. When this bit is
302 * set an interrupt happens as soon as the frame is transmitted */
303 void (*clear_tx_ic) (struct dma_desc *p);
304 /* Last tx segment reports the transmit status */
305 int (*get_tx_ls) (struct dma_desc *p);
306 /* Return the transmit status looking at the TDES1 */
307 int (*tx_status) (void *data, struct stmmac_extra_stats *x,
308 struct dma_desc *p, void __iomem *ioaddr);
309 /* Get the buffer size from the descriptor */
310 int (*get_tx_len) (struct dma_desc *p);
311 /* Handle extra events on specific interrupts hw dependent */
312 int (*get_rx_owner) (struct dma_desc *p);
313 void (*set_rx_owner) (struct dma_desc *p);
314 /* Get the receive frame size */
315 int (*get_rx_frame_len) (struct dma_desc *p, int rx_coe_type);
316 /* Return the reception status looking at the RDES1 */
317 int (*rx_status) (void *data, struct stmmac_extra_stats *x,
319 void (*rx_extended_status) (void *data, struct stmmac_extra_stats *x,
320 struct dma_extended_desc *p);
323 struct stmmac_dma_ops {
324 /* DMA core initialization */
325 int (*init) (void __iomem *ioaddr, int pbl, int fb, int mb,
326 int burst_len, u32 dma_tx, u32 dma_rx, int atds);
327 /* Dump DMA registers */
328 void (*dump_regs) (void __iomem *ioaddr);
329 /* Set tx/rx threshold in the csr6 register
330 * An invalid value enables the store-and-forward mode */
331 void (*dma_mode) (void __iomem *ioaddr, int txmode, int rxmode);
332 /* To track extra statistic (if supported) */
333 void (*dma_diagnostic_fr) (void *data, struct stmmac_extra_stats *x,
334 void __iomem *ioaddr);
335 void (*enable_dma_transmission) (void __iomem *ioaddr);
336 void (*enable_dma_irq) (void __iomem *ioaddr);
337 void (*disable_dma_irq) (void __iomem *ioaddr);
338 void (*start_tx) (void __iomem *ioaddr);
339 void (*stop_tx) (void __iomem *ioaddr);
340 void (*start_rx) (void __iomem *ioaddr);
341 void (*stop_rx) (void __iomem *ioaddr);
342 int (*dma_interrupt) (void __iomem *ioaddr,
343 struct stmmac_extra_stats *x);
344 /* If supported then get the optional core features */
345 unsigned int (*get_hw_feature) (void __iomem *ioaddr);
346 /* Program the HW RX Watchdog */
347 void (*rx_watchdog) (void __iomem *ioaddr, u32 riwt);
351 /* MAC core initialization */
352 void (*core_init) (void __iomem *ioaddr) ____cacheline_aligned;
353 /* Enable and verify that the IPC module is supported */
354 int (*rx_ipc) (void __iomem *ioaddr);
355 /* Dump MAC registers */
356 void (*dump_regs) (void __iomem *ioaddr);
357 /* Handle extra events on specific interrupts hw dependent */
358 int (*host_irq_status) (void __iomem *ioaddr);
359 /* Multicast filter setting */
360 void (*set_filter) (struct net_device *dev, int id);
361 /* Flow control setting */
362 void (*flow_ctrl) (void __iomem *ioaddr, unsigned int duplex,
363 unsigned int fc, unsigned int pause_time);
364 /* Set power management mode (e.g. magic frame) */
365 void (*pmt) (void __iomem *ioaddr, unsigned long mode);
366 /* Set/Get Unicast MAC addresses */
367 void (*set_umac_addr) (void __iomem *ioaddr, unsigned char *addr,
369 void (*get_umac_addr) (void __iomem *ioaddr, unsigned char *addr,
371 void (*set_eee_mode) (void __iomem *ioaddr);
372 void (*reset_eee_mode) (void __iomem *ioaddr);
373 void (*set_eee_timer) (void __iomem *ioaddr, int ls, int tw);
374 void (*set_eee_pls) (void __iomem *ioaddr, int link);
384 unsigned int addr; /* MII Address */
385 unsigned int data; /* MII Data */
388 struct stmmac_ring_mode_ops {
389 unsigned int (*is_jumbo_frm) (int len, int ehn_desc);
390 unsigned int (*jumbo_frm) (void *priv, struct sk_buff *skb, int csum);
391 void (*refill_desc3) (int bfsize, struct dma_desc *p);
392 void (*init_desc3) (struct dma_desc *p);
393 void (*clean_desc3) (struct dma_desc *p);
394 int (*set_16kib_bfsize) (int mtu);
397 struct stmmac_chain_mode_ops {
398 void (*init) (void *des, dma_addr_t phy_addr, unsigned int size,
399 unsigned int extend_desc);
400 unsigned int (*is_jumbo_frm) (int len, int ehn_desc);
401 unsigned int (*jumbo_frm) (void *priv, struct sk_buff *skb, int csum);
404 struct mac_device_info {
405 const struct stmmac_ops *mac;
406 const struct stmmac_desc_ops *desc;
407 const struct stmmac_dma_ops *dma;
408 const struct stmmac_ring_mode_ops *ring;
409 const struct stmmac_chain_mode_ops *chain;
410 struct mii_regs mii; /* MII register Addresses */
411 struct mac_link link;
412 unsigned int synopsys_uid;
415 struct mac_device_info *dwmac1000_setup(void __iomem *ioaddr);
416 struct mac_device_info *dwmac100_setup(void __iomem *ioaddr);
418 extern void stmmac_set_mac_addr(void __iomem *ioaddr, u8 addr[6],
419 unsigned int high, unsigned int low);
420 extern void stmmac_get_mac_addr(void __iomem *ioaddr, unsigned char *addr,
421 unsigned int high, unsigned int low);
423 extern void stmmac_set_mac(void __iomem *ioaddr, bool enable);
425 extern void dwmac_dma_flush_tx_fifo(void __iomem *ioaddr);
426 extern const struct stmmac_ring_mode_ops ring_mode_ops;
427 extern const struct stmmac_chain_mode_ops chain_mode_ops;
429 #endif /* __COMMON_H__ */