1 /*******************************************************************************
2 Header File to describe the DMA descriptors.
3 Enhanced descriptors have been in case of DWMAC1000 Cores.
5 This program is free software; you can redistribute it and/or modify it
6 under the terms and conditions of the GNU General Public License,
7 version 2, as published by the Free Software Foundation.
9 This program is distributed in the hope it will be useful, but WITHOUT
10 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 You should have received a copy of the GNU General Public License along with
15 this program; if not, write to the Free Software Foundation, Inc.,
16 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 The full GNU General Public License is included in this distribution in
19 the file called "COPYING".
21 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
22 *******************************************************************************/
27 /* Basic descriptor structure for normal and alternate descriptors */
29 /* Receive descriptor */
33 u32 payload_csum_error:1;
37 u32 receive_watchdog:1;
41 u32 last_descriptor:1;
42 u32 first_descriptor:1;
47 u32 descriptor_error:1;
56 u32 second_address_chained:1;
68 u32 receive_watchdog:1;
72 u32 last_descriptor:1;
73 u32 first_descriptor:1;
78 u32 descriptor_error:1;
86 u32 second_address_chained:1;
91 } erx; /* -- enhanced -- */
93 /* Transmit descriptor */
97 u32 underflow_error:1;
98 u32 excessive_deferral:1;
99 u32 collision_count:4;
101 u32 excessive_collisions:1;
102 u32 late_collision:1;
107 u32 jabber_timeout:1;
109 u32 ip_header_error:1;
110 u32 time_stamp_status:1;
116 u32 time_stamp_enable:1;
117 u32 disable_padding:1;
118 u32 second_address_chained:1;
121 u32 checksum_insertion:2;
129 u32 underflow_error:1;
130 u32 excessive_deferral:1;
131 u32 collision_count:4;
133 u32 excessive_collisions:1;
134 u32 late_collision:1;
139 u32 jabber_timeout:1;
141 u32 ip_header_error:1;
142 u32 time_stamp_status:1;
144 u32 second_address_chained:1;
146 u32 checksum_insertion:2;
148 u32 time_stamp_enable:1;
149 u32 disable_padding:1;
160 } etx; /* -- enhanced -- */
168 /* Extended descriptor structure (supported by new SYNP GMAC generations) */
169 struct dma_extended_desc {
170 struct dma_desc basic;
173 u32 ip_payload_type:3;
175 u32 ip_payload_err:1;
176 u32 ip_csum_bypassed:1;
180 u32 ptp_frame_type:1;
182 u32 timestamp_dropped:1;
185 u32 av_tagged_pkt_rcvd:1;
186 u32 vlan_tag_priority_val:3;
188 u32 l3_filter_match:1;
189 u32 l4_filter_match:1;
190 u32 l3_l4_filter_no_match:2;
197 unsigned int des5; /* Reserved */
198 unsigned int des6; /* Tx/Rx Timestamp Low */
199 unsigned int des7; /* Tx/Rx Timestamp High */
202 /* Transmit checksum insertion control */
203 enum tdes_csum_insertion {
204 cic_disabled = 0, /* Checksum Insertion Control */
205 cic_only_ip = 1, /* Only IP header */
206 /* IP header but pseudoheader is not calculated */
207 cic_no_pseudoheader = 2,
208 cic_full = 3, /* IP header and pseudoheader */
211 /* Extended RDES4 definitions */
212 #define RDES_EXT_NO_PTP 0
213 #define RDES_EXT_SYNC 0x1
214 #define RDES_EXT_FOLLOW_UP 0x2
215 #define RDES_EXT_DELAY_REQ 0x3
216 #define RDES_EXT_DELAY_RESP 0x4
217 #define RDES_EXT_PDELAY_REQ 0x5
218 #define RDES_EXT_PDELAY_RESP 0x6
219 #define RDES_EXT_PDELAY_FOLLOW_UP 0x7
221 #endif /* __DESCS_H__ */