drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c

   1 /**
   2  * dwmac-rk.c - Rockchip RK3288 DWMAC specific glue layer
   3  *
   4  * Copyright (C) 2014 Chen-Zhi (Roger Chen)
   5  *
   6  * Chen-Zhi (Roger Chen)  <roger.chen@rock-chips.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #include <linux/stmmac.h>
  20 #include <linux/bitops.h>
  21 #include <linux/clk.h>
  22 #include <linux/phy.h>
  23 #include <linux/of_net.h>
  24 #include <linux/gpio.h>
  25 #include <linux/module.h>
  26 #include <linux/of_gpio.h>
  27 #include <linux/of_device.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/regulator/consumer.h>
  30 #include <linux/delay.h>
  31 #include <linux/mfd/syscon.h>
  32 #include <linux/regmap.h>
  33 #include <linux/pm_runtime.h>
  34 #include <linux/soc/rockchip/rk_vendor_storage.h>
  35 #include "stmmac_platform.h"
  36
  37 struct rk_priv_data;
  38 struct rk_gmac_ops {
  39         void (*set_to_rgmii)(struct rk_priv_data *bsp_priv,
  40                              int tx_delay, int rx_delay);
  41         void (*set_to_rmii)(struct rk_priv_data *bsp_priv);
  42         void (*set_rgmii_speed)(struct rk_priv_data *bsp_priv, int speed);
  43         void (*set_rmii_speed)(struct rk_priv_data *bsp_priv, int speed);
  44 };
  45
  46 struct rk_priv_data {
  47         struct platform_device *pdev;
  48         int phy_iface;
  49         struct regulator *regulator;
  50         const struct rk_gmac_ops *ops;
  51
  52         bool clk_enabled;
  53         bool clock_input;
  54
  55         struct clk *clk_mac;
  56         struct clk *gmac_clkin;
  57         struct clk *mac_clk_rx;
  58         struct clk *mac_clk_tx;
  59         struct clk *clk_mac_ref;
  60         struct clk *clk_mac_refout;
  61         struct clk *aclk_mac;
  62         struct clk *pclk_mac;
  63
  64         int tx_delay;
  65         int rx_delay;
  66
  67         struct regmap *grf;
  68 };
  69
  70 #define HIWORD_UPDATE(val, mask, shift) \
  71                 ((val) << (shift) | (mask) << ((shift) + 16))
  72
  73 #define GRF_BIT(nr)     (BIT(nr) | BIT(nr+16))
  74 #define GRF_CLR_BIT(nr) (BIT(nr+16))
  75
  76 #define RK3228_GRF_MAC_CON0     0x0900
  77 #define RK3228_GRF_MAC_CON1     0x0904
  78
  79 /* RK3228_GRF_MAC_CON0 */
  80 #define RK3228_GMAC_CLK_RX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 7)
  81 #define RK3228_GMAC_CLK_TX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 0)
  82
  83 /* RK3228_GRF_MAC_CON1 */
  84 #define RK3228_GMAC_PHY_INTF_SEL_RGMII  \
  85                 (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6))
  86 #define RK3228_GMAC_PHY_INTF_SEL_RMII   \
  87                 (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6))
  88 #define RK3228_GMAC_FLOW_CTRL           GRF_BIT(3)
  89 #define RK3228_GMAC_FLOW_CTRL_CLR       GRF_CLR_BIT(3)
  90 #define RK3228_GMAC_SPEED_10M           GRF_CLR_BIT(2)
  91 #define RK3228_GMAC_SPEED_100M          GRF_BIT(2)
  92 #define RK3228_GMAC_RMII_CLK_25M        GRF_BIT(7)
  93 #define RK3228_GMAC_RMII_CLK_2_5M       GRF_CLR_BIT(7)
  94 #define RK3228_GMAC_CLK_125M            (GRF_CLR_BIT(8) | GRF_CLR_BIT(9))
  95 #define RK3228_GMAC_CLK_25M             (GRF_BIT(8) | GRF_BIT(9))
  96 #define RK3228_GMAC_CLK_2_5M            (GRF_CLR_BIT(8) | GRF_BIT(9))
  97 #define RK3228_GMAC_RMII_MODE           GRF_BIT(10)
  98 #define RK3228_GMAC_RMII_MODE_CLR       GRF_CLR_BIT(10)
  99 #define RK3228_GMAC_TXCLK_DLY_ENABLE    GRF_BIT(0)
 100 #define RK3228_GMAC_TXCLK_DLY_DISABLE   GRF_CLR_BIT(0)
 101 #define RK3228_GMAC_RXCLK_DLY_ENABLE    GRF_BIT(1)
 102 #define RK3228_GMAC_RXCLK_DLY_DISABLE   GRF_CLR_BIT(1)
 103
 104 static void rk3228_set_to_rgmii(struct rk_priv_data *bsp_priv,
 105                                 int tx_delay, int rx_delay)
 106 {
 107         struct device *dev = &bsp_priv->pdev->dev;
 108
 109         if (IS_ERR(bsp_priv->grf)) {
 110                 dev_err(dev, "Missing rockchip,grf property\n");
 111                 return;
 112         }
 113
 114         regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
 115                      RK3228_GMAC_PHY_INTF_SEL_RGMII |
 116                      RK3228_GMAC_RMII_MODE_CLR |
 117                      RK3228_GMAC_RXCLK_DLY_ENABLE |
 118                      RK3228_GMAC_TXCLK_DLY_ENABLE);
 119
 120         regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON0,
 121                      RK3228_GMAC_CLK_RX_DL_CFG(rx_delay) |
 122                      RK3228_GMAC_CLK_TX_DL_CFG(tx_delay));
 123 }
 124
 125 static void rk3228_set_to_rmii(struct rk_priv_data *bsp_priv)
 126 {
 127         struct device *dev = &bsp_priv->pdev->dev;
 128
 129         if (IS_ERR(bsp_priv->grf)) {
 130                 dev_err(dev, "Missing rockchip,grf property\n");
 131                 return;
 132         }
 133
 134         regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
 135                      RK3228_GMAC_PHY_INTF_SEL_RMII |
 136                      RK3228_GMAC_RMII_MODE);
 137
 138         /* set MAC to RMII mode */
 139         regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, GRF_BIT(11));
 140 }
 141
 142 static void rk3228_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
 143 {
 144         struct device *dev = &bsp_priv->pdev->dev;
 145
 146         if (IS_ERR(bsp_priv->grf)) {
 147                 dev_err(dev, "Missing rockchip,grf property\n");
 148                 return;
 149         }
 150
 151         if (speed == 10)
 152                 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
 153                              RK3228_GMAC_CLK_2_5M);
 154         else if (speed == 100)
 155                 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
 156                              RK3228_GMAC_CLK_25M);
 157         else if (speed == 1000)
 158                 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
 159                              RK3228_GMAC_CLK_125M);
 160         else
 161                 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
 162 }
 163
 164 static void rk3228_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
 165 {
 166         struct device *dev = &bsp_priv->pdev->dev;
 167
 168         if (IS_ERR(bsp_priv->grf)) {
 169                 dev_err(dev, "Missing rockchip,grf property\n");
 170                 return;
 171         }
 172
 173         if (speed == 10)
 174                 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
 175                              RK3228_GMAC_RMII_CLK_2_5M |
 176                              RK3228_GMAC_SPEED_10M);
 177         else if (speed == 100)
 178                 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
 179                              RK3228_GMAC_RMII_CLK_25M |
 180                              RK3228_GMAC_SPEED_100M);
 181         else
 182                 dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
 183 }
 184
 185 static const struct rk_gmac_ops rk3228_ops = {
 186         .set_to_rgmii = rk3228_set_to_rgmii,
 187         .set_to_rmii = rk3228_set_to_rmii,
 188         .set_rgmii_speed = rk3228_set_rgmii_speed,
 189         .set_rmii_speed = rk3228_set_rmii_speed,
 190 };
 191
 192 #define RK3288_GRF_SOC_CON1     0x0248
 193 #define RK3288_GRF_SOC_CON3     0x0250
 194
 195 /*RK3288_GRF_SOC_CON1*/
 196 #define RK3288_GMAC_PHY_INTF_SEL_RGMII  (GRF_BIT(6) | GRF_CLR_BIT(7) | \
 197                                          GRF_CLR_BIT(8))
 198 #define RK3288_GMAC_PHY_INTF_SEL_RMII   (GRF_CLR_BIT(6) | GRF_CLR_BIT(7) | \
 199                                          GRF_BIT(8))
 200 #define RK3288_GMAC_FLOW_CTRL           GRF_BIT(9)
 201 #define RK3288_GMAC_FLOW_CTRL_CLR       GRF_CLR_BIT(9)
 202 #define RK3288_GMAC_SPEED_10M           GRF_CLR_BIT(10)
 203 #define RK3288_GMAC_SPEED_100M          GRF_BIT(10)
 204 #define RK3288_GMAC_RMII_CLK_25M        GRF_BIT(11)
 205 #define RK3288_GMAC_RMII_CLK_2_5M       GRF_CLR_BIT(11)
 206 #define RK3288_GMAC_CLK_125M            (GRF_CLR_BIT(12) | GRF_CLR_BIT(13))
 207 #define RK3288_GMAC_CLK_25M             (GRF_BIT(12) | GRF_BIT(13))
 208 #define RK3288_GMAC_CLK_2_5M            (GRF_CLR_BIT(12) | GRF_BIT(13))
 209 #define RK3288_GMAC_RMII_MODE           GRF_BIT(14)
 210 #define RK3288_GMAC_RMII_MODE_CLR       GRF_CLR_BIT(14)
 211
 212 /*RK3288_GRF_SOC_CON3*/
 213 #define RK3288_GMAC_TXCLK_DLY_ENABLE    GRF_BIT(14)
 214 #define RK3288_GMAC_TXCLK_DLY_DISABLE   GRF_CLR_BIT(14)
 215 #define RK3288_GMAC_RXCLK_DLY_ENABLE    GRF_BIT(15)
 216 #define RK3288_GMAC_RXCLK_DLY_DISABLE   GRF_CLR_BIT(15)
 217 #define RK3288_GMAC_CLK_RX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 7)
 218 #define RK3288_GMAC_CLK_TX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 0)
 219
 220 static void rk3288_set_to_rgmii(struct rk_priv_data *bsp_priv,
 221                                 int tx_delay, int rx_delay)
 222 {
 223         struct device *dev = &bsp_priv->pdev->dev;
 224
 225         if (IS_ERR(bsp_priv->grf)) {
 226                 dev_err(dev, "Missing rockchip,grf property\n");
 227                 return;
 228         }
 229
 230         regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
 231                      RK3288_GMAC_PHY_INTF_SEL_RGMII |
 232                      RK3288_GMAC_RMII_MODE_CLR);
 233         regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON3,
 234                      RK3288_GMAC_RXCLK_DLY_ENABLE |
 235                      RK3288_GMAC_TXCLK_DLY_ENABLE |
 236                      RK3288_GMAC_CLK_RX_DL_CFG(rx_delay) |
 237                      RK3288_GMAC_CLK_TX_DL_CFG(tx_delay));
 238 }
 239
 240 static void rk3288_set_to_rmii(struct rk_priv_data *bsp_priv)
 241 {
 242         struct device *dev = &bsp_priv->pdev->dev;
 243
 244         if (IS_ERR(bsp_priv->grf)) {
 245                 dev_err(dev, "Missing rockchip,grf property\n");
 246                 return;
 247         }
 248
 249         regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
 250                      RK3288_GMAC_PHY_INTF_SEL_RMII | RK3288_GMAC_RMII_MODE);
 251 }
 252
 253 static void rk3288_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
 254 {
 255         struct device *dev = &bsp_priv->pdev->dev;
 256
 257         if (IS_ERR(bsp_priv->grf)) {
 258                 dev_err(dev, "Missing rockchip,grf property\n");
 259                 return;
 260         }
 261
 262         if (speed == 10)
 263                 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
 264                              RK3288_GMAC_CLK_2_5M);
 265         else if (speed == 100)
 266                 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
 267                              RK3288_GMAC_CLK_25M);
 268         else if (speed == 1000)
 269                 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
 270                              RK3288_GMAC_CLK_125M);
 271         else
 272                 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
 273 }
 274
 275 static void rk3288_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
 276 {
 277         struct device *dev = &bsp_priv->pdev->dev;
 278
 279         if (IS_ERR(bsp_priv->grf)) {
 280                 dev_err(dev, "Missing rockchip,grf property\n");
 281                 return;
 282         }
 283
 284         if (speed == 10) {
 285                 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
 286                              RK3288_GMAC_RMII_CLK_2_5M |
 287                              RK3288_GMAC_SPEED_10M);
 288         } else if (speed == 100) {
 289                 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
 290                              RK3288_GMAC_RMII_CLK_25M |
 291                              RK3288_GMAC_SPEED_100M);
 292         } else {
 293                 dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
 294         }
 295 }
 296
 297 static const struct rk_gmac_ops rk3288_ops = {
 298         .set_to_rgmii = rk3288_set_to_rgmii,
 299         .set_to_rmii = rk3288_set_to_rmii,
 300         .set_rgmii_speed = rk3288_set_rgmii_speed,
 301         .set_rmii_speed = rk3288_set_rmii_speed,
 302 };
 303
 304 #define RK3366_GRF_SOC_CON6     0x0418
 305 #define RK3366_GRF_SOC_CON7     0x041c
 306
 307 /* RK3366_GRF_SOC_CON6 */
 308 #define RK3366_GMAC_PHY_INTF_SEL_RGMII  (GRF_BIT(9) | GRF_CLR_BIT(10) | \
 309                                          GRF_CLR_BIT(11))
 310 #define RK3366_GMAC_PHY_INTF_SEL_RMII   (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \
 311                                          GRF_BIT(11))
 312 #define RK3366_GMAC_FLOW_CTRL           GRF_BIT(8)
 313 #define RK3366_GMAC_FLOW_CTRL_CLR       GRF_CLR_BIT(8)
 314 #define RK3366_GMAC_SPEED_10M           GRF_CLR_BIT(7)
 315 #define RK3366_GMAC_SPEED_100M          GRF_BIT(7)
 316 #define RK3366_GMAC_RMII_CLK_25M        GRF_BIT(3)
 317 #define RK3366_GMAC_RMII_CLK_2_5M       GRF_CLR_BIT(3)
 318 #define RK3366_GMAC_CLK_125M            (GRF_CLR_BIT(4) | GRF_CLR_BIT(5))
 319 #define RK3366_GMAC_CLK_25M             (GRF_BIT(4) | GRF_BIT(5))
 320 #define RK3366_GMAC_CLK_2_5M            (GRF_CLR_BIT(4) | GRF_BIT(5))
 321 #define RK3366_GMAC_RMII_MODE           GRF_BIT(6)
 322 #define RK3366_GMAC_RMII_MODE_CLR       GRF_CLR_BIT(6)
 323
 324 /* RK3366_GRF_SOC_CON7 */
 325 #define RK3366_GMAC_TXCLK_DLY_ENABLE    GRF_BIT(7)
 326 #define RK3366_GMAC_TXCLK_DLY_DISABLE   GRF_CLR_BIT(7)
 327 #define RK3366_GMAC_RXCLK_DLY_ENABLE    GRF_BIT(15)
 328 #define RK3366_GMAC_RXCLK_DLY_DISABLE   GRF_CLR_BIT(15)
 329 #define RK3366_GMAC_CLK_RX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 8)
 330 #define RK3366_GMAC_CLK_TX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 0)
 331
 332 static void rk3366_set_to_rgmii(struct rk_priv_data *bsp_priv,
 333                                 int tx_delay, int rx_delay)
 334 {
 335         struct device *dev = &bsp_priv->pdev->dev;
 336
 337         if (IS_ERR(bsp_priv->grf)) {
 338                 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
 339                 return;
 340         }
 341
 342         regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
 343                      RK3366_GMAC_PHY_INTF_SEL_RGMII |
 344                      RK3366_GMAC_RMII_MODE_CLR);
 345         regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON7,
 346                      RK3366_GMAC_RXCLK_DLY_ENABLE |
 347                      RK3366_GMAC_TXCLK_DLY_ENABLE |
 348                      RK3366_GMAC_CLK_RX_DL_CFG(rx_delay) |
 349                      RK3366_GMAC_CLK_TX_DL_CFG(tx_delay));
 350 }
 351
 352 static void rk3366_set_to_rmii(struct rk_priv_data *bsp_priv)
 353 {
 354         struct device *dev = &bsp_priv->pdev->dev;
 355
 356         if (IS_ERR(bsp_priv->grf)) {
 357                 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
 358                 return;
 359         }
 360
 361         regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
 362                      RK3366_GMAC_PHY_INTF_SEL_RMII | RK3366_GMAC_RMII_MODE);
 363 }
 364
 365 static void rk3366_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
 366 {
 367         struct device *dev = &bsp_priv->pdev->dev;
 368
 369         if (IS_ERR(bsp_priv->grf)) {
 370                 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
 371                 return;
 372         }
 373
 374         if (speed == 10)
 375                 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
 376                              RK3366_GMAC_CLK_2_5M);
 377         else if (speed == 100)
 378                 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
 379                              RK3366_GMAC_CLK_25M);
 380         else if (speed == 1000)
 381                 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
 382                              RK3366_GMAC_CLK_125M);
 383         else
 384                 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
 385 }
 386
 387 static void rk3366_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
 388 {
 389         struct device *dev = &bsp_priv->pdev->dev;
 390
 391         if (IS_ERR(bsp_priv->grf)) {
 392                 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
 393                 return;
 394         }
 395
 396         if (speed == 10) {
 397                 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
 398                              RK3366_GMAC_RMII_CLK_2_5M |
 399                              RK3366_GMAC_SPEED_10M);
 400         } else if (speed == 100) {
 401                 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
 402                              RK3366_GMAC_RMII_CLK_25M |
 403                              RK3366_GMAC_SPEED_100M);
 404         } else {
 405                 dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
 406         }
 407 }
 408
 409 static const struct rk_gmac_ops rk3366_ops = {
 410         .set_to_rgmii = rk3366_set_to_rgmii,
 411         .set_to_rmii = rk3366_set_to_rmii,
 412         .set_rgmii_speed = rk3366_set_rgmii_speed,
 413         .set_rmii_speed = rk3366_set_rmii_speed,
 414 };
 415
 416 #define RK3368_GRF_SOC_CON15    0x043c
 417 #define RK3368_GRF_SOC_CON16    0x0440
 418
 419 /* RK3368_GRF_SOC_CON15 */
 420 #define RK3368_GMAC_PHY_INTF_SEL_RGMII  (GRF_BIT(9) | GRF_CLR_BIT(10) | \
 421                                          GRF_CLR_BIT(11))
 422 #define RK3368_GMAC_PHY_INTF_SEL_RMII   (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \
 423                                          GRF_BIT(11))
 424 #define RK3368_GMAC_FLOW_CTRL           GRF_BIT(8)
 425 #define RK3368_GMAC_FLOW_CTRL_CLR       GRF_CLR_BIT(8)
 426 #define RK3368_GMAC_SPEED_10M           GRF_CLR_BIT(7)
 427 #define RK3368_GMAC_SPEED_100M          GRF_BIT(7)
 428 #define RK3368_GMAC_RMII_CLK_25M        GRF_BIT(3)
 429 #define RK3368_GMAC_RMII_CLK_2_5M       GRF_CLR_BIT(3)
 430 #define RK3368_GMAC_CLK_125M            (GRF_CLR_BIT(4) | GRF_CLR_BIT(5))
 431 #define RK3368_GMAC_CLK_25M             (GRF_BIT(4) | GRF_BIT(5))
 432 #define RK3368_GMAC_CLK_2_5M            (GRF_CLR_BIT(4) | GRF_BIT(5))
 433 #define RK3368_GMAC_RMII_MODE           GRF_BIT(6)
 434 #define RK3368_GMAC_RMII_MODE_CLR       GRF_CLR_BIT(6)
 435
 436 /* RK3368_GRF_SOC_CON16 */
 437 #define RK3368_GMAC_TXCLK_DLY_ENABLE    GRF_BIT(7)
 438 #define RK3368_GMAC_TXCLK_DLY_DISABLE   GRF_CLR_BIT(7)
 439 #define RK3368_GMAC_RXCLK_DLY_ENABLE    GRF_BIT(15)
 440 #define RK3368_GMAC_RXCLK_DLY_DISABLE   GRF_CLR_BIT(15)
 441 #define RK3368_GMAC_CLK_RX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 8)
 442 #define RK3368_GMAC_CLK_TX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 0)
 443
 444 static void rk3368_set_to_rgmii(struct rk_priv_data *bsp_priv,
 445                                 int tx_delay, int rx_delay)
 446 {
 447         struct device *dev = &bsp_priv->pdev->dev;
 448
 449         if (IS_ERR(bsp_priv->grf)) {
 450                 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
 451                 return;
 452         }
 453
 454         regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
 455                      RK3368_GMAC_PHY_INTF_SEL_RGMII |
 456                      RK3368_GMAC_RMII_MODE_CLR);
 457         regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON16,
 458                      RK3368_GMAC_RXCLK_DLY_ENABLE |
 459                      RK3368_GMAC_TXCLK_DLY_ENABLE |
 460                      RK3368_GMAC_CLK_RX_DL_CFG(rx_delay) |
 461                      RK3368_GMAC_CLK_TX_DL_CFG(tx_delay));
 462 }
 463
 464 static void rk3368_set_to_rmii(struct rk_priv_data *bsp_priv)
 465 {
 466         struct device *dev = &bsp_priv->pdev->dev;
 467
 468         if (IS_ERR(bsp_priv->grf)) {
 469                 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
 470                 return;
 471         }
 472
 473         regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
 474                      RK3368_GMAC_PHY_INTF_SEL_RMII | RK3368_GMAC_RMII_MODE);
 475 }
 476
 477 static void rk3368_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
 478 {
 479         struct device *dev = &bsp_priv->pdev->dev;
 480
 481         if (IS_ERR(bsp_priv->grf)) {
 482                 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
 483                 return;
 484         }
 485
 486         if (speed == 10)
 487                 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
 488                              RK3368_GMAC_CLK_2_5M);
 489         else if (speed == 100)
 490                 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
 491                              RK3368_GMAC_CLK_25M);
 492         else if (speed == 1000)
 493                 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
 494                              RK3368_GMAC_CLK_125M);
 495         else
 496                 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
 497 }
 498
 499 static void rk3368_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
 500 {
 501         struct device *dev = &bsp_priv->pdev->dev;
 502
 503         if (IS_ERR(bsp_priv->grf)) {
 504                 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
 505                 return;
 506         }
 507
 508         if (speed == 10) {
 509                 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
 510                              RK3368_GMAC_RMII_CLK_2_5M |
 511                              RK3368_GMAC_SPEED_10M);
 512         } else if (speed == 100) {
 513                 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
 514                              RK3368_GMAC_RMII_CLK_25M |
 515                              RK3368_GMAC_SPEED_100M);
 516         } else {
 517                 dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
 518         }
 519 }
 520
 521 static const struct rk_gmac_ops rk3368_ops = {
 522         .set_to_rgmii = rk3368_set_to_rgmii,
 523         .set_to_rmii = rk3368_set_to_rmii,
 524         .set_rgmii_speed = rk3368_set_rgmii_speed,
 525         .set_rmii_speed = rk3368_set_rmii_speed,
 526 };
 527
 528 #define RK3399_GRF_SOC_CON5     0xc214
 529 #define RK3399_GRF_SOC_CON6     0xc218
 530
 531 /* RK3399_GRF_SOC_CON5 */
 532 #define RK3399_GMAC_PHY_INTF_SEL_RGMII  (GRF_BIT(9) | GRF_CLR_BIT(10) | \
 533                                          GRF_CLR_BIT(11))
 534 #define RK3399_GMAC_PHY_INTF_SEL_RMII   (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \
 535                                          GRF_BIT(11))
 536 #define RK3399_GMAC_FLOW_CTRL           GRF_BIT(8)
 537 #define RK3399_GMAC_FLOW_CTRL_CLR       GRF_CLR_BIT(8)
 538 #define RK3399_GMAC_SPEED_10M           GRF_CLR_BIT(7)
 539 #define RK3399_GMAC_SPEED_100M          GRF_BIT(7)
 540 #define RK3399_GMAC_RMII_CLK_25M        GRF_BIT(3)
 541 #define RK3399_GMAC_RMII_CLK_2_5M       GRF_CLR_BIT(3)
 542 #define RK3399_GMAC_CLK_125M            (GRF_CLR_BIT(4) | GRF_CLR_BIT(5))
 543 #define RK3399_GMAC_CLK_25M             (GRF_BIT(4) | GRF_BIT(5))
 544 #define RK3399_GMAC_CLK_2_5M            (GRF_CLR_BIT(4) | GRF_BIT(5))
 545 #define RK3399_GMAC_RMII_MODE           GRF_BIT(6)
 546 #define RK3399_GMAC_RMII_MODE_CLR       GRF_CLR_BIT(6)
 547
 548 /* RK3399_GRF_SOC_CON6 */
 549 #define RK3399_GMAC_TXCLK_DLY_ENABLE    GRF_BIT(7)
 550 #define RK3399_GMAC_TXCLK_DLY_DISABLE   GRF_CLR_BIT(7)
 551 #define RK3399_GMAC_RXCLK_DLY_ENABLE    GRF_BIT(15)
 552 #define RK3399_GMAC_RXCLK_DLY_DISABLE   GRF_CLR_BIT(15)
 553 #define RK3399_GMAC_CLK_RX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 8)
 554 #define RK3399_GMAC_CLK_TX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 0)
 555
 556 static void rk3399_set_to_rgmii(struct rk_priv_data *bsp_priv,
 557                                 int tx_delay, int rx_delay)
 558 {
 559         struct device *dev = &bsp_priv->pdev->dev;
 560
 561         if (IS_ERR(bsp_priv->grf)) {
 562                 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
 563                 return;
 564         }
 565
 566         regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
 567                      RK3399_GMAC_PHY_INTF_SEL_RGMII |
 568                      RK3399_GMAC_RMII_MODE_CLR);
 569         regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON6,
 570                      RK3399_GMAC_RXCLK_DLY_ENABLE |
 571                      RK3399_GMAC_TXCLK_DLY_ENABLE |
 572                      RK3399_GMAC_CLK_RX_DL_CFG(rx_delay) |
 573                      RK3399_GMAC_CLK_TX_DL_CFG(tx_delay));
 574 }
 575
 576 static void rk3399_set_to_rmii(struct rk_priv_data *bsp_priv)
 577 {
 578         struct device *dev = &bsp_priv->pdev->dev;
 579
 580         if (IS_ERR(bsp_priv->grf)) {
 581                 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
 582                 return;
 583         }
 584
 585         regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
 586                      RK3399_GMAC_PHY_INTF_SEL_RMII | RK3399_GMAC_RMII_MODE);
 587 }
 588
 589 static void rk3399_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
 590 {
 591         struct device *dev = &bsp_priv->pdev->dev;
 592
 593         if (IS_ERR(bsp_priv->grf)) {
 594                 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
 595                 return;
 596         }
 597
 598         if (speed == 10)
 599                 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
 600                              RK3399_GMAC_CLK_2_5M);
 601         else if (speed == 100)
 602                 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
 603                              RK3399_GMAC_CLK_25M);
 604         else if (speed == 1000)
 605                 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
 606                              RK3399_GMAC_CLK_125M);
 607         else
 608                 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
 609 }
 610
 611 static void rk3399_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
 612 {
 613         struct device *dev = &bsp_priv->pdev->dev;
 614
 615         if (IS_ERR(bsp_priv->grf)) {
 616                 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
 617                 return;
 618         }
 619
 620         if (speed == 10) {
 621                 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
 622                              RK3399_GMAC_RMII_CLK_2_5M |
 623                              RK3399_GMAC_SPEED_10M);
 624         } else if (speed == 100) {
 625                 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
 626                              RK3399_GMAC_RMII_CLK_25M |
 627                              RK3399_GMAC_SPEED_100M);
 628         } else {
 629                 dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
 630         }
 631 }
 632
 633 static const struct rk_gmac_ops rk3399_ops = {
 634         .set_to_rgmii = rk3399_set_to_rgmii,
 635         .set_to_rmii = rk3399_set_to_rmii,
 636         .set_rgmii_speed = rk3399_set_rgmii_speed,
 637         .set_rmii_speed = rk3399_set_rmii_speed,
 638 };
 639
 640 static int gmac_clk_init(struct rk_priv_data *bsp_priv)
 641 {
 642         struct device *dev = &bsp_priv->pdev->dev;
 643
 644         bsp_priv->clk_enabled = false;
 645
 646         bsp_priv->mac_clk_rx = devm_clk_get(dev, "mac_clk_rx");
 647         if (IS_ERR(bsp_priv->mac_clk_rx))
 648                 dev_err(dev, "cannot get clock %s\n",
 649                         "mac_clk_rx");
 650
 651         bsp_priv->mac_clk_tx = devm_clk_get(dev, "mac_clk_tx");
 652         if (IS_ERR(bsp_priv->mac_clk_tx))
 653                 dev_err(dev, "cannot get clock %s\n",
 654                         "mac_clk_tx");
 655
 656         bsp_priv->aclk_mac = devm_clk_get(dev, "aclk_mac");
 657         if (IS_ERR(bsp_priv->aclk_mac))
 658                 dev_err(dev, "cannot get clock %s\n",
 659                         "aclk_mac");
 660
 661         bsp_priv->pclk_mac = devm_clk_get(dev, "pclk_mac");
 662         if (IS_ERR(bsp_priv->pclk_mac))
 663                 dev_err(dev, "cannot get clock %s\n",
 664                         "pclk_mac");
 665
 666         bsp_priv->clk_mac = devm_clk_get(dev, "stmmaceth");
 667         if (IS_ERR(bsp_priv->clk_mac))
 668                 dev_err(dev, "cannot get clock %s\n",
 669                         "stmmaceth");
 670
 671         if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII) {
 672                 bsp_priv->clk_mac_ref = devm_clk_get(dev, "clk_mac_ref");
 673                 if (IS_ERR(bsp_priv->clk_mac_ref))
 674                         dev_err(dev, "cannot get clock %s\n",
 675                                 "clk_mac_ref");
 676
 677                 if (!bsp_priv->clock_input) {
 678                         bsp_priv->clk_mac_refout =
 679                                 devm_clk_get(dev, "clk_mac_refout");
 680                         if (IS_ERR(bsp_priv->clk_mac_refout))
 681                                 dev_err(dev, "cannot get clock %s\n",
 682                                         "clk_mac_refout");
 683                 }
 684         }
 685
 686         if (bsp_priv->clock_input) {
 687                 dev_info(dev, "clock input from PHY\n");
 688         } else {
 689                 if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII)
 690                         clk_set_rate(bsp_priv->clk_mac, 50000000);
 691         }
 692
 693         return 0;
 694 }
 695
 696 static int gmac_clk_enable(struct rk_priv_data *bsp_priv, bool enable)
 697 {
 698         int phy_iface = bsp_priv->phy_iface;
 699
 700         if (enable) {
 701                 if (!bsp_priv->clk_enabled) {
 702                         if (phy_iface == PHY_INTERFACE_MODE_RMII) {
 703                                 if (!IS_ERR(bsp_priv->mac_clk_rx))
 704                                         clk_prepare_enable(
 705                                                 bsp_priv->mac_clk_rx);
 706
 707                                 if (!IS_ERR(bsp_priv->clk_mac_ref))
 708                                         clk_prepare_enable(
 709                                                 bsp_priv->clk_mac_ref);
 710
 711                                 if (!IS_ERR(bsp_priv->clk_mac_refout))
 712                                         clk_prepare_enable(
 713                                                 bsp_priv->clk_mac_refout);
 714                         }
 715
 716                         if (!IS_ERR(bsp_priv->aclk_mac))
 717                                 clk_prepare_enable(bsp_priv->aclk_mac);
 718
 719                         if (!IS_ERR(bsp_priv->pclk_mac))
 720                                 clk_prepare_enable(bsp_priv->pclk_mac);
 721
 722                         if (!IS_ERR(bsp_priv->mac_clk_tx))
 723                                 clk_prepare_enable(bsp_priv->mac_clk_tx);
 724
 725                         /**
 726                          * if (!IS_ERR(bsp_priv->clk_mac))
 727                          *      clk_prepare_enable(bsp_priv->clk_mac);
 728                          */
 729                         mdelay(5);
 730                         bsp_priv->clk_enabled = true;
 731                 }
 732         } else {
 733                 if (bsp_priv->clk_enabled) {
 734                         if (phy_iface == PHY_INTERFACE_MODE_RMII) {
 735                                 if (!IS_ERR(bsp_priv->mac_clk_rx))
 736                                         clk_disable_unprepare(
 737                                                 bsp_priv->mac_clk_rx);
 738
 739                                 if (!IS_ERR(bsp_priv->clk_mac_ref))
 740                                         clk_disable_unprepare(
 741                                                 bsp_priv->clk_mac_ref);
 742
 743                                 if (!IS_ERR(bsp_priv->clk_mac_refout))
 744                                         clk_disable_unprepare(
 745                                                 bsp_priv->clk_mac_refout);
 746                         }
 747
 748                         if (!IS_ERR(bsp_priv->aclk_mac))
 749                                 clk_disable_unprepare(bsp_priv->aclk_mac);
 750
 751                         if (!IS_ERR(bsp_priv->pclk_mac))
 752                                 clk_disable_unprepare(bsp_priv->pclk_mac);
 753
 754                         if (!IS_ERR(bsp_priv->mac_clk_tx))
 755                                 clk_disable_unprepare(bsp_priv->mac_clk_tx);
 756                         /**
 757                          * if (!IS_ERR(bsp_priv->clk_mac))
 758                          *      clk_disable_unprepare(bsp_priv->clk_mac);
 759                          */
 760                         bsp_priv->clk_enabled = false;
 761                 }
 762         }
 763
 764         return 0;
 765 }
 766
 767 static int phy_power_on(struct rk_priv_data *bsp_priv, bool enable)
 768 {
 769         struct regulator *ldo = bsp_priv->regulator;
 770         int ret;
 771         struct device *dev = &bsp_priv->pdev->dev;
 772
 773         if (!ldo) {
 774                 dev_err(dev, "no regulator found\n");
 775                 return -1;
 776         }
 777
 778         if (enable) {
 779                 ret = regulator_enable(ldo);
 780                 if (ret)
 781                         dev_err(dev, "fail to enable phy-supply\n");
 782         } else {
 783                 ret = regulator_disable(ldo);
 784                 if (ret)
 785                         dev_err(dev, "fail to disable phy-supply\n");
 786         }
 787
 788         return 0;
 789 }
 790
 791 static struct rk_priv_data *rk_gmac_setup(struct platform_device *pdev,
 792                                           const struct rk_gmac_ops *ops)
 793 {
 794         struct rk_priv_data *bsp_priv;
 795         struct device *dev = &pdev->dev;
 796         int ret;
 797         const char *strings = NULL;
 798         int value;
 799
 800         bsp_priv = devm_kzalloc(dev, sizeof(*bsp_priv), GFP_KERNEL);
 801         if (!bsp_priv)
 802                 return ERR_PTR(-ENOMEM);
 803
 804         bsp_priv->phy_iface = of_get_phy_mode(dev->of_node);
 805         bsp_priv->ops = ops;
 806
 807         bsp_priv->regulator = devm_regulator_get_optional(dev, "phy");
 808         if (IS_ERR(bsp_priv->regulator)) {
 809                 if (PTR_ERR(bsp_priv->regulator) == -EPROBE_DEFER) {
 810                         dev_err(dev, "phy regulator is not available yet, deferred probing\n");
 811                         return ERR_PTR(-EPROBE_DEFER);
 812                 }
 813                 dev_err(dev, "no regulator found\n");
 814                 bsp_priv->regulator = NULL;
 815         }
 816
 817         ret = of_property_read_string(dev->of_node, "clock_in_out", &strings);
 818         if (ret) {
 819                 dev_err(dev, "Can not read property: clock_in_out.\n");
 820                 bsp_priv->clock_input = true;
 821         } else {
 822                 dev_info(dev, "clock input or output? (%s).\n",
 823                          strings);
 824                 if (!strcmp(strings, "input"))
 825                         bsp_priv->clock_input = true;
 826                 else
 827                         bsp_priv->clock_input = false;
 828         }
 829
 830         ret = of_property_read_u32(dev->of_node, "tx_delay", &value);
 831         if (ret) {
 832                 bsp_priv->tx_delay = 0x30;
 833                 dev_err(dev, "Can not read property: tx_delay.");
 834                 dev_err(dev, "set tx_delay to 0x%x\n",
 835                         bsp_priv->tx_delay);
 836         } else {
 837                 dev_info(dev, "TX delay(0x%x).\n", value);
 838                 bsp_priv->tx_delay = value;
 839         }
 840
 841         ret = of_property_read_u32(dev->of_node, "rx_delay", &value);
 842         if (ret) {
 843                 bsp_priv->rx_delay = 0x10;
 844                 dev_err(dev, "Can not read property: rx_delay.");
 845                 dev_err(dev, "set rx_delay to 0x%x\n",
 846                         bsp_priv->rx_delay);
 847         } else {
 848                 dev_info(dev, "RX delay(0x%x).\n", value);
 849                 bsp_priv->rx_delay = value;
 850         }
 851
 852         bsp_priv->grf = syscon_regmap_lookup_by_phandle(dev->of_node,
 853                                                         "rockchip,grf");
 854         bsp_priv->pdev = pdev;
 855
 856         gmac_clk_init(bsp_priv);
 857
 858         return bsp_priv;
 859 }
 860
 861 static int rk_gmac_init(struct platform_device *pdev, void *priv)
 862 {
 863         struct rk_priv_data *bsp_priv = priv;
 864         int ret;
 865         struct device *dev = &pdev->dev;
 866
 867         /*rmii or rgmii*/
 868         if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RGMII) {
 869                 dev_info(dev, "init for RGMII\n");
 870                 bsp_priv->ops->set_to_rgmii(bsp_priv, bsp_priv->tx_delay,
 871                                             bsp_priv->rx_delay);
 872         } else if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII) {
 873                 dev_info(dev, "init for RMII\n");
 874                 bsp_priv->ops->set_to_rmii(bsp_priv);
 875         } else {
 876                 dev_err(dev, "NO interface defined!\n");
 877         }
 878
 879         ret = phy_power_on(bsp_priv, true);
 880         if (ret)
 881                 return ret;
 882
 883         ret = gmac_clk_enable(bsp_priv, true);
 884         if (ret)
 885                 return ret;
 886
 887         pm_runtime_enable(&pdev->dev);
 888         pm_runtime_get_sync(&pdev->dev);
 889
 890         return 0;
 891 }
 892
 893 static void rk_gmac_exit(struct platform_device *pdev, void *priv)
 894 {
 895         struct rk_priv_data *gmac = priv;
 896
 897         pm_runtime_put_sync(&pdev->dev);
 898         pm_runtime_disable(&pdev->dev);
 899
 900         phy_power_on(gmac, false);
 901         gmac_clk_enable(gmac, false);
 902 }
 903
 904 static void rk_fix_speed(void *priv, unsigned int speed)
 905 {
 906         struct rk_priv_data *bsp_priv = priv;
 907         struct device *dev = &bsp_priv->pdev->dev;
 908
 909         if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RGMII)
 910                 bsp_priv->ops->set_rgmii_speed(bsp_priv, speed);
 911         else if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII)
 912                 bsp_priv->ops->set_rmii_speed(bsp_priv, speed);
 913         else
 914                 dev_err(dev, "unsupported interface %d", bsp_priv->phy_iface);
 915 }
 916
 917 void rk_get_eth_addr_vendor(void *priv, unsigned char *addr)
 918 {
 919         int ret;
 920         struct rk_priv_data *bsp_priv = priv;
 921         struct device *dev = &bsp_priv->pdev->dev;
 922
 923         ret = rk_vendor_read(LAN_MAC_ID, addr, 6);
 924         if (ret != 6 || is_zero_ether_addr(addr)) {
 925                 dev_err(dev, "%s: rk_vendor_read eth mac address failed (%d)",
 926                                         __func__, ret);
 927                 random_ether_addr(addr);
 928                 dev_err(dev, "%s: generate random eth mac address: %02x:%02x:%02x:%02x:%02x:%02x",
 929                                         __func__, addr[0], addr[1], addr[2],
 930                                         addr[3], addr[4], addr[5]);
 931                 ret = rk_vendor_write(LAN_MAC_ID, addr, 6);
 932                 if (ret != 0)
 933                         dev_err(dev, "%s: rk_vendor_write eth mac address failed (%d)",
 934                                         __func__, ret);
 935         } else {
 936                 dev_err(dev, "%s: rk_vendor_read eth mac address: %02x:%02x:%02x:%02x:%02x:%02x",
 937                                         __func__, addr[0], addr[1], addr[2],
 938                                         addr[3], addr[4], addr[5]);
 939         }
 940 }
 941
 942 static int rk_gmac_probe(struct platform_device *pdev)
 943 {
 944         struct plat_stmmacenet_data *plat_dat;
 945         struct stmmac_resources stmmac_res;
 946         const struct rk_gmac_ops *data;
 947         int ret;
 948
 949         data = of_device_get_match_data(&pdev->dev);
 950         if (!data) {
 951                 dev_err(&pdev->dev, "no of match data provided\n");
 952                 return -EINVAL;
 953         }
 954
 955         ret = stmmac_get_platform_resources(pdev, &stmmac_res);
 956         if (ret)
 957                 return ret;
 958
 959         plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac);
 960         if (IS_ERR(plat_dat))
 961                 return PTR_ERR(plat_dat);
 962
 963         plat_dat->has_gmac = true;
 964         plat_dat->init = rk_gmac_init;
 965         plat_dat->exit = rk_gmac_exit;
 966         plat_dat->fix_mac_speed = rk_fix_speed;
 967         plat_dat->get_eth_addr = rk_get_eth_addr_vendor;
 968
 969         plat_dat->bsp_priv = rk_gmac_setup(pdev, data);
 970         if (IS_ERR(plat_dat->bsp_priv))
 971                 return PTR_ERR(plat_dat->bsp_priv);
 972
 973         ret = rk_gmac_init(pdev, plat_dat->bsp_priv);
 974         if (ret)
 975                 return ret;
 976
 977         return stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);
 978 }
 979
 980 static const struct of_device_id rk_gmac_dwmac_match[] = {
 981         { .compatible = "rockchip,rk3228-gmac", .data = &rk3228_ops },
 982         { .compatible = "rockchip,rk3288-gmac", .data = &rk3288_ops },
 983         { .compatible = "rockchip,rk3366-gmac", .data = &rk3366_ops },
 984         { .compatible = "rockchip,rk3368-gmac", .data = &rk3368_ops },
 985         { .compatible = "rockchip,rk3399-gmac", .data = &rk3399_ops },
 986         { }
 987 };
 988 MODULE_DEVICE_TABLE(of, rk_gmac_dwmac_match);
 989
 990 static struct platform_driver rk_gmac_dwmac_driver = {
 991         .probe  = rk_gmac_probe,
 992         .remove = stmmac_pltfr_remove,
 993         .driver = {
 994                 .name           = "rk_gmac-dwmac",
 995                 .pm             = &stmmac_pltfr_pm_ops,
 996                 .of_match_table = rk_gmac_dwmac_match,
 997         },
 998 };
 999 module_platform_driver(rk_gmac_dwmac_driver);
1000
1001 MODULE_AUTHOR("Chen-Zhi (Roger Chen) <roger.chen@rock-chips.com>");
1002 MODULE_DESCRIPTION("Rockchip RK3288 DWMAC specific glue layer");
1003 MODULE_LICENSE("GPL");