drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c

   1 /**
   2  * dwmac-rk.c - Rockchip RK3288 DWMAC specific glue layer
   3  *
   4  * Copyright (C) 2014 Chen-Zhi (Roger Chen)
   5  *
   6  * Chen-Zhi (Roger Chen)  <roger.chen@rock-chips.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #include <linux/stmmac.h>
  20 #include <linux/bitops.h>
  21 #include <linux/clk.h>
  22 #include <linux/phy.h>
  23 #include <linux/of_net.h>
  24 #include <linux/gpio.h>
  25 #include <linux/module.h>
  26 #include <linux/of_gpio.h>
  27 #include <linux/of_device.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/regulator/consumer.h>
  30 #include <linux/delay.h>
  31 #include <linux/mfd/syscon.h>
  32 #include <linux/regmap.h>
  33 #include <linux/pm_runtime.h>
  34 #include <linux/soc/rockchip/rk_vendor_storage.h>
  35 #include "stmmac_platform.h"
  36
  37 struct rk_priv_data;
  38 struct rk_gmac_ops {
  39         void (*set_to_rgmii)(struct rk_priv_data *bsp_priv,
  40                              int tx_delay, int rx_delay);
  41         void (*set_to_rmii)(struct rk_priv_data *bsp_priv);
  42         void (*set_rgmii_speed)(struct rk_priv_data *bsp_priv, int speed);
  43         void (*set_rmii_speed)(struct rk_priv_data *bsp_priv, int speed);
  44 };
  45
  46 struct rk_priv_data {
  47         struct platform_device *pdev;
  48         int phy_iface;
  49         struct regulator *regulator;
  50         const struct rk_gmac_ops *ops;
  51
  52         bool clk_enabled;
  53         bool clock_input;
  54
  55         struct clk *clk_mac;
  56         struct clk *gmac_clkin;
  57         struct clk *mac_clk_rx;
  58         struct clk *mac_clk_tx;
  59         struct clk *clk_mac_ref;
  60         struct clk *clk_mac_refout;
  61         struct clk *aclk_mac;
  62         struct clk *pclk_mac;
  63
  64         int tx_delay;
  65         int rx_delay;
  66
  67         struct regmap *grf;
  68 };
  69
  70 #define HIWORD_UPDATE(val, mask, shift) \
  71                 ((val) << (shift) | (mask) << ((shift) + 16))
  72
  73 #define GRF_BIT(nr)     (BIT(nr) | BIT(nr+16))
  74 #define GRF_CLR_BIT(nr) (BIT(nr+16))
  75
  76 #define DELAY_ENABLE(soc, tx, rx) \
  77         (((tx) ? soc##_GMAC_TXCLK_DLY_ENABLE : soc##_GMAC_TXCLK_DLY_DISABLE) | \
  78          ((rx) ? soc##_GMAC_RXCLK_DLY_ENABLE : soc##_GMAC_RXCLK_DLY_DISABLE))
  79
  80 #define RK3228_GRF_MAC_CON0     0x0900
  81 #define RK3228_GRF_MAC_CON1     0x0904
  82
  83 /* RK3228_GRF_MAC_CON0 */
  84 #define RK3228_GMAC_CLK_RX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 7)
  85 #define RK3228_GMAC_CLK_TX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 0)
  86
  87 /* RK3228_GRF_MAC_CON1 */
  88 #define RK3228_GMAC_PHY_INTF_SEL_RGMII  \
  89                 (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6))
  90 #define RK3228_GMAC_PHY_INTF_SEL_RMII   \
  91                 (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6))
  92 #define RK3228_GMAC_FLOW_CTRL           GRF_BIT(3)
  93 #define RK3228_GMAC_FLOW_CTRL_CLR       GRF_CLR_BIT(3)
  94 #define RK3228_GMAC_SPEED_10M           GRF_CLR_BIT(2)
  95 #define RK3228_GMAC_SPEED_100M          GRF_BIT(2)
  96 #define RK3228_GMAC_RMII_CLK_25M        GRF_BIT(7)
  97 #define RK3228_GMAC_RMII_CLK_2_5M       GRF_CLR_BIT(7)
  98 #define RK3228_GMAC_CLK_125M            (GRF_CLR_BIT(8) | GRF_CLR_BIT(9))
  99 #define RK3228_GMAC_CLK_25M             (GRF_BIT(8) | GRF_BIT(9))
 100 #define RK3228_GMAC_CLK_2_5M            (GRF_CLR_BIT(8) | GRF_BIT(9))
 101 #define RK3228_GMAC_RMII_MODE           GRF_BIT(10)
 102 #define RK3228_GMAC_RMII_MODE_CLR       GRF_CLR_BIT(10)
 103 #define RK3228_GMAC_TXCLK_DLY_ENABLE    GRF_BIT(0)
 104 #define RK3228_GMAC_TXCLK_DLY_DISABLE   GRF_CLR_BIT(0)
 105 #define RK3228_GMAC_RXCLK_DLY_ENABLE    GRF_BIT(1)
 106 #define RK3228_GMAC_RXCLK_DLY_DISABLE   GRF_CLR_BIT(1)
 107
 108 static void rk3228_set_to_rgmii(struct rk_priv_data *bsp_priv,
 109                                 int tx_delay, int rx_delay)
 110 {
 111         struct device *dev = &bsp_priv->pdev->dev;
 112
 113         if (IS_ERR(bsp_priv->grf)) {
 114                 dev_err(dev, "Missing rockchip,grf property\n");
 115                 return;
 116         }
 117
 118         regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
 119                      RK3228_GMAC_PHY_INTF_SEL_RGMII |
 120                      RK3228_GMAC_RMII_MODE_CLR |
 121                      DELAY_ENABLE(RK3228, tx_delay, rx_delay));
 122
 123         regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON0,
 124                      RK3228_GMAC_CLK_RX_DL_CFG(rx_delay) |
 125                      RK3228_GMAC_CLK_TX_DL_CFG(tx_delay));
 126 }
 127
 128 static void rk3228_set_to_rmii(struct rk_priv_data *bsp_priv)
 129 {
 130         struct device *dev = &bsp_priv->pdev->dev;
 131
 132         if (IS_ERR(bsp_priv->grf)) {
 133                 dev_err(dev, "Missing rockchip,grf property\n");
 134                 return;
 135         }
 136
 137         regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
 138                      RK3228_GMAC_PHY_INTF_SEL_RMII |
 139                      RK3228_GMAC_RMII_MODE);
 140
 141         /* set MAC to RMII mode */
 142         regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, GRF_BIT(11));
 143 }
 144
 145 static void rk3228_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
 146 {
 147         struct device *dev = &bsp_priv->pdev->dev;
 148
 149         if (IS_ERR(bsp_priv->grf)) {
 150                 dev_err(dev, "Missing rockchip,grf property\n");
 151                 return;
 152         }
 153
 154         if (speed == 10)
 155                 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
 156                              RK3228_GMAC_CLK_2_5M);
 157         else if (speed == 100)
 158                 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
 159                              RK3228_GMAC_CLK_25M);
 160         else if (speed == 1000)
 161                 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
 162                              RK3228_GMAC_CLK_125M);
 163         else
 164                 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
 165 }
 166
 167 static void rk3228_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
 168 {
 169         struct device *dev = &bsp_priv->pdev->dev;
 170
 171         if (IS_ERR(bsp_priv->grf)) {
 172                 dev_err(dev, "Missing rockchip,grf property\n");
 173                 return;
 174         }
 175
 176         if (speed == 10)
 177                 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
 178                              RK3228_GMAC_RMII_CLK_2_5M |
 179                              RK3228_GMAC_SPEED_10M);
 180         else if (speed == 100)
 181                 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
 182                              RK3228_GMAC_RMII_CLK_25M |
 183                              RK3228_GMAC_SPEED_100M);
 184         else
 185                 dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
 186 }
 187
 188 static const struct rk_gmac_ops rk3228_ops = {
 189         .set_to_rgmii = rk3228_set_to_rgmii,
 190         .set_to_rmii = rk3228_set_to_rmii,
 191         .set_rgmii_speed = rk3228_set_rgmii_speed,
 192         .set_rmii_speed = rk3228_set_rmii_speed,
 193 };
 194
 195 #define RK3288_GRF_SOC_CON1     0x0248
 196 #define RK3288_GRF_SOC_CON3     0x0250
 197
 198 /*RK3288_GRF_SOC_CON1*/
 199 #define RK3288_GMAC_PHY_INTF_SEL_RGMII  (GRF_BIT(6) | GRF_CLR_BIT(7) | \
 200                                          GRF_CLR_BIT(8))
 201 #define RK3288_GMAC_PHY_INTF_SEL_RMII   (GRF_CLR_BIT(6) | GRF_CLR_BIT(7) | \
 202                                          GRF_BIT(8))
 203 #define RK3288_GMAC_FLOW_CTRL           GRF_BIT(9)
 204 #define RK3288_GMAC_FLOW_CTRL_CLR       GRF_CLR_BIT(9)
 205 #define RK3288_GMAC_SPEED_10M           GRF_CLR_BIT(10)
 206 #define RK3288_GMAC_SPEED_100M          GRF_BIT(10)
 207 #define RK3288_GMAC_RMII_CLK_25M        GRF_BIT(11)
 208 #define RK3288_GMAC_RMII_CLK_2_5M       GRF_CLR_BIT(11)
 209 #define RK3288_GMAC_CLK_125M            (GRF_CLR_BIT(12) | GRF_CLR_BIT(13))
 210 #define RK3288_GMAC_CLK_25M             (GRF_BIT(12) | GRF_BIT(13))
 211 #define RK3288_GMAC_CLK_2_5M            (GRF_CLR_BIT(12) | GRF_BIT(13))
 212 #define RK3288_GMAC_RMII_MODE           GRF_BIT(14)
 213 #define RK3288_GMAC_RMII_MODE_CLR       GRF_CLR_BIT(14)
 214
 215 /*RK3288_GRF_SOC_CON3*/
 216 #define RK3288_GMAC_TXCLK_DLY_ENABLE    GRF_BIT(14)
 217 #define RK3288_GMAC_TXCLK_DLY_DISABLE   GRF_CLR_BIT(14)
 218 #define RK3288_GMAC_RXCLK_DLY_ENABLE    GRF_BIT(15)
 219 #define RK3288_GMAC_RXCLK_DLY_DISABLE   GRF_CLR_BIT(15)
 220 #define RK3288_GMAC_CLK_RX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 7)
 221 #define RK3288_GMAC_CLK_TX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 0)
 222
 223 static void rk3288_set_to_rgmii(struct rk_priv_data *bsp_priv,
 224                                 int tx_delay, int rx_delay)
 225 {
 226         struct device *dev = &bsp_priv->pdev->dev;
 227
 228         if (IS_ERR(bsp_priv->grf)) {
 229                 dev_err(dev, "Missing rockchip,grf property\n");
 230                 return;
 231         }
 232
 233         regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
 234                      RK3288_GMAC_PHY_INTF_SEL_RGMII |
 235                      RK3288_GMAC_RMII_MODE_CLR);
 236         regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON3,
 237                      DELAY_ENABLE(RK3288, tx_delay, rx_delay) |
 238                      RK3288_GMAC_CLK_RX_DL_CFG(rx_delay) |
 239                      RK3288_GMAC_CLK_TX_DL_CFG(tx_delay));
 240 }
 241
 242 static void rk3288_set_to_rmii(struct rk_priv_data *bsp_priv)
 243 {
 244         struct device *dev = &bsp_priv->pdev->dev;
 245
 246         if (IS_ERR(bsp_priv->grf)) {
 247                 dev_err(dev, "Missing rockchip,grf property\n");
 248                 return;
 249         }
 250
 251         regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
 252                      RK3288_GMAC_PHY_INTF_SEL_RMII | RK3288_GMAC_RMII_MODE);
 253 }
 254
 255 static void rk3288_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
 256 {
 257         struct device *dev = &bsp_priv->pdev->dev;
 258
 259         if (IS_ERR(bsp_priv->grf)) {
 260                 dev_err(dev, "Missing rockchip,grf property\n");
 261                 return;
 262         }
 263
 264         if (speed == 10)
 265                 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
 266                              RK3288_GMAC_CLK_2_5M);
 267         else if (speed == 100)
 268                 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
 269                              RK3288_GMAC_CLK_25M);
 270         else if (speed == 1000)
 271                 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
 272                              RK3288_GMAC_CLK_125M);
 273         else
 274                 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
 275 }
 276
 277 static void rk3288_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
 278 {
 279         struct device *dev = &bsp_priv->pdev->dev;
 280
 281         if (IS_ERR(bsp_priv->grf)) {
 282                 dev_err(dev, "Missing rockchip,grf property\n");
 283                 return;
 284         }
 285
 286         if (speed == 10) {
 287                 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
 288                              RK3288_GMAC_RMII_CLK_2_5M |
 289                              RK3288_GMAC_SPEED_10M);
 290         } else if (speed == 100) {
 291                 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
 292                              RK3288_GMAC_RMII_CLK_25M |
 293                              RK3288_GMAC_SPEED_100M);
 294         } else {
 295                 dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
 296         }
 297 }
 298
 299 static const struct rk_gmac_ops rk3288_ops = {
 300         .set_to_rgmii = rk3288_set_to_rgmii,
 301         .set_to_rmii = rk3288_set_to_rmii,
 302         .set_rgmii_speed = rk3288_set_rgmii_speed,
 303         .set_rmii_speed = rk3288_set_rmii_speed,
 304 };
 305
 306 #define RK3328_GRF_MAC_CON0     0x0900
 307 #define RK3328_GRF_MAC_CON1     0x0904
 308
 309 /* RK3328_GRF_MAC_CON0 */
 310 #define RK3328_GMAC_CLK_RX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 7)
 311 #define RK3328_GMAC_CLK_TX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 0)
 312
 313 /* RK3328_GRF_MAC_CON1 */
 314 #define RK3328_GMAC_PHY_INTF_SEL_RGMII  \
 315                 (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6))
 316 #define RK3328_GMAC_PHY_INTF_SEL_RMII   \
 317                 (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6))
 318 #define RK3328_GMAC_FLOW_CTRL           GRF_BIT(3)
 319 #define RK3328_GMAC_FLOW_CTRL_CLR       GRF_CLR_BIT(3)
 320 #define RK3328_GMAC_SPEED_10M           GRF_CLR_BIT(2)
 321 #define RK3328_GMAC_SPEED_100M          GRF_BIT(2)
 322 #define RK3328_GMAC_RMII_CLK_25M        GRF_BIT(7)
 323 #define RK3328_GMAC_RMII_CLK_2_5M       GRF_CLR_BIT(7)
 324 #define RK3328_GMAC_CLK_125M            (GRF_CLR_BIT(11) | GRF_CLR_BIT(12))
 325 #define RK3328_GMAC_CLK_25M             (GRF_BIT(11) | GRF_BIT(12))
 326 #define RK3328_GMAC_CLK_2_5M            (GRF_CLR_BIT(11) | GRF_BIT(12))
 327 #define RK3328_GMAC_RMII_MODE           GRF_BIT(9)
 328 #define RK3328_GMAC_RMII_MODE_CLR       GRF_CLR_BIT(9)
 329 #define RK3328_GMAC_TXCLK_DLY_ENABLE    GRF_BIT(0)
 330 #define RK3328_GMAC_TXCLK_DLY_DISABLE   GRF_CLR_BIT(0)
 331 #define RK3328_GMAC_RXCLK_DLY_ENABLE    GRF_BIT(1)
 332 #define RK3328_GMAC_RXCLK_DLY_DISABLE   GRF_CLR_BIT(0)
 333
 334 static void rk3328_set_to_rgmii(struct rk_priv_data *bsp_priv,
 335                                 int tx_delay, int rx_delay)
 336 {
 337         struct device *dev = &bsp_priv->pdev->dev;
 338
 339         if (IS_ERR(bsp_priv->grf)) {
 340                 dev_err(dev, "Missing rockchip,grf property\n");
 341                 return;
 342         }
 343
 344         regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
 345                      RK3328_GMAC_PHY_INTF_SEL_RGMII |
 346                      RK3328_GMAC_RMII_MODE_CLR |
 347                      RK3328_GMAC_RXCLK_DLY_ENABLE |
 348                      RK3328_GMAC_TXCLK_DLY_ENABLE);
 349
 350         regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON0,
 351                      RK3328_GMAC_CLK_RX_DL_CFG(rx_delay) |
 352                      RK3328_GMAC_CLK_TX_DL_CFG(tx_delay));
 353 }
 354
 355 static void rk3328_set_to_rmii(struct rk_priv_data *bsp_priv)
 356 {
 357         struct device *dev = &bsp_priv->pdev->dev;
 358
 359         if (IS_ERR(bsp_priv->grf)) {
 360                 dev_err(dev, "Missing rockchip,grf property\n");
 361                 return;
 362         }
 363
 364         regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
 365                      RK3328_GMAC_PHY_INTF_SEL_RMII |
 366                      RK3328_GMAC_RMII_MODE);
 367
 368         /* set MAC to RMII mode */
 369         regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1, GRF_BIT(11));
 370 }
 371
 372 static void rk3328_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
 373 {
 374         struct device *dev = &bsp_priv->pdev->dev;
 375
 376         if (IS_ERR(bsp_priv->grf)) {
 377                 dev_err(dev, "Missing rockchip,grf property\n");
 378                 return;
 379         }
 380
 381         if (speed == 10)
 382                 regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
 383                              RK3328_GMAC_CLK_2_5M);
 384         else if (speed == 100)
 385                 regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
 386                              RK3328_GMAC_CLK_25M);
 387         else if (speed == 1000)
 388                 regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
 389                              RK3328_GMAC_CLK_125M);
 390         else
 391                 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
 392 }
 393
 394 static void rk3328_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
 395 {
 396         struct device *dev = &bsp_priv->pdev->dev;
 397
 398         if (IS_ERR(bsp_priv->grf)) {
 399                 dev_err(dev, "Missing rockchip,grf property\n");
 400                 return;
 401         }
 402
 403         if (speed == 10)
 404                 regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
 405                              RK3328_GMAC_RMII_CLK_2_5M |
 406                              RK3328_GMAC_SPEED_10M);
 407         else if (speed == 100)
 408                 regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
 409                              RK3328_GMAC_RMII_CLK_25M |
 410                              RK3328_GMAC_SPEED_100M);
 411         else
 412                 dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
 413 }
 414
 415 static const struct rk_gmac_ops rk3328_ops = {
 416         .set_to_rgmii = rk3328_set_to_rgmii,
 417         .set_to_rmii = rk3328_set_to_rmii,
 418         .set_rgmii_speed = rk3328_set_rgmii_speed,
 419         .set_rmii_speed = rk3328_set_rmii_speed,
 420 };
 421
 422 #define RK3366_GRF_SOC_CON6     0x0418
 423 #define RK3366_GRF_SOC_CON7     0x041c
 424
 425 /* RK3366_GRF_SOC_CON6 */
 426 #define RK3366_GMAC_PHY_INTF_SEL_RGMII  (GRF_BIT(9) | GRF_CLR_BIT(10) | \
 427                                          GRF_CLR_BIT(11))
 428 #define RK3366_GMAC_PHY_INTF_SEL_RMII   (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \
 429                                          GRF_BIT(11))
 430 #define RK3366_GMAC_FLOW_CTRL           GRF_BIT(8)
 431 #define RK3366_GMAC_FLOW_CTRL_CLR       GRF_CLR_BIT(8)
 432 #define RK3366_GMAC_SPEED_10M           GRF_CLR_BIT(7)
 433 #define RK3366_GMAC_SPEED_100M          GRF_BIT(7)
 434 #define RK3366_GMAC_RMII_CLK_25M        GRF_BIT(3)
 435 #define RK3366_GMAC_RMII_CLK_2_5M       GRF_CLR_BIT(3)
 436 #define RK3366_GMAC_CLK_125M            (GRF_CLR_BIT(4) | GRF_CLR_BIT(5))
 437 #define RK3366_GMAC_CLK_25M             (GRF_BIT(4) | GRF_BIT(5))
 438 #define RK3366_GMAC_CLK_2_5M            (GRF_CLR_BIT(4) | GRF_BIT(5))
 439 #define RK3366_GMAC_RMII_MODE           GRF_BIT(6)
 440 #define RK3366_GMAC_RMII_MODE_CLR       GRF_CLR_BIT(6)
 441
 442 /* RK3366_GRF_SOC_CON7 */
 443 #define RK3366_GMAC_TXCLK_DLY_ENABLE    GRF_BIT(7)
 444 #define RK3366_GMAC_TXCLK_DLY_DISABLE   GRF_CLR_BIT(7)
 445 #define RK3366_GMAC_RXCLK_DLY_ENABLE    GRF_BIT(15)
 446 #define RK3366_GMAC_RXCLK_DLY_DISABLE   GRF_CLR_BIT(15)
 447 #define RK3366_GMAC_CLK_RX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 8)
 448 #define RK3366_GMAC_CLK_TX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 0)
 449
 450 static void rk3366_set_to_rgmii(struct rk_priv_data *bsp_priv,
 451                                 int tx_delay, int rx_delay)
 452 {
 453         struct device *dev = &bsp_priv->pdev->dev;
 454
 455         if (IS_ERR(bsp_priv->grf)) {
 456                 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
 457                 return;
 458         }
 459
 460         regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
 461                      RK3366_GMAC_PHY_INTF_SEL_RGMII |
 462                      RK3366_GMAC_RMII_MODE_CLR);
 463         regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON7,
 464                      DELAY_ENABLE(RK3366, tx_delay, rx_delay) |
 465                      RK3366_GMAC_CLK_RX_DL_CFG(rx_delay) |
 466                      RK3366_GMAC_CLK_TX_DL_CFG(tx_delay));
 467 }
 468
 469 static void rk3366_set_to_rmii(struct rk_priv_data *bsp_priv)
 470 {
 471         struct device *dev = &bsp_priv->pdev->dev;
 472
 473         if (IS_ERR(bsp_priv->grf)) {
 474                 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
 475                 return;
 476         }
 477
 478         regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
 479                      RK3366_GMAC_PHY_INTF_SEL_RMII | RK3366_GMAC_RMII_MODE);
 480 }
 481
 482 static void rk3366_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
 483 {
 484         struct device *dev = &bsp_priv->pdev->dev;
 485
 486         if (IS_ERR(bsp_priv->grf)) {
 487                 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
 488                 return;
 489         }
 490
 491         if (speed == 10)
 492                 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
 493                              RK3366_GMAC_CLK_2_5M);
 494         else if (speed == 100)
 495                 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
 496                              RK3366_GMAC_CLK_25M);
 497         else if (speed == 1000)
 498                 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
 499                              RK3366_GMAC_CLK_125M);
 500         else
 501                 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
 502 }
 503
 504 static void rk3366_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
 505 {
 506         struct device *dev = &bsp_priv->pdev->dev;
 507
 508         if (IS_ERR(bsp_priv->grf)) {
 509                 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
 510                 return;
 511         }
 512
 513         if (speed == 10) {
 514                 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
 515                              RK3366_GMAC_RMII_CLK_2_5M |
 516                              RK3366_GMAC_SPEED_10M);
 517         } else if (speed == 100) {
 518                 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
 519                              RK3366_GMAC_RMII_CLK_25M |
 520                              RK3366_GMAC_SPEED_100M);
 521         } else {
 522                 dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
 523         }
 524 }
 525
 526 static const struct rk_gmac_ops rk3366_ops = {
 527         .set_to_rgmii = rk3366_set_to_rgmii,
 528         .set_to_rmii = rk3366_set_to_rmii,
 529         .set_rgmii_speed = rk3366_set_rgmii_speed,
 530         .set_rmii_speed = rk3366_set_rmii_speed,
 531 };
 532
 533 #define RK3368_GRF_SOC_CON15    0x043c
 534 #define RK3368_GRF_SOC_CON16    0x0440
 535
 536 /* RK3368_GRF_SOC_CON15 */
 537 #define RK3368_GMAC_PHY_INTF_SEL_RGMII  (GRF_BIT(9) | GRF_CLR_BIT(10) | \
 538                                          GRF_CLR_BIT(11))
 539 #define RK3368_GMAC_PHY_INTF_SEL_RMII   (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \
 540                                          GRF_BIT(11))
 541 #define RK3368_GMAC_FLOW_CTRL           GRF_BIT(8)
 542 #define RK3368_GMAC_FLOW_CTRL_CLR       GRF_CLR_BIT(8)
 543 #define RK3368_GMAC_SPEED_10M           GRF_CLR_BIT(7)
 544 #define RK3368_GMAC_SPEED_100M          GRF_BIT(7)
 545 #define RK3368_GMAC_RMII_CLK_25M        GRF_BIT(3)
 546 #define RK3368_GMAC_RMII_CLK_2_5M       GRF_CLR_BIT(3)
 547 #define RK3368_GMAC_CLK_125M            (GRF_CLR_BIT(4) | GRF_CLR_BIT(5))
 548 #define RK3368_GMAC_CLK_25M             (GRF_BIT(4) | GRF_BIT(5))
 549 #define RK3368_GMAC_CLK_2_5M            (GRF_CLR_BIT(4) | GRF_BIT(5))
 550 #define RK3368_GMAC_RMII_MODE           GRF_BIT(6)
 551 #define RK3368_GMAC_RMII_MODE_CLR       GRF_CLR_BIT(6)
 552
 553 /* RK3368_GRF_SOC_CON16 */
 554 #define RK3368_GMAC_TXCLK_DLY_ENABLE    GRF_BIT(7)
 555 #define RK3368_GMAC_TXCLK_DLY_DISABLE   GRF_CLR_BIT(7)
 556 #define RK3368_GMAC_RXCLK_DLY_ENABLE    GRF_BIT(15)
 557 #define RK3368_GMAC_RXCLK_DLY_DISABLE   GRF_CLR_BIT(15)
 558 #define RK3368_GMAC_CLK_RX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 8)
 559 #define RK3368_GMAC_CLK_TX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 0)
 560
 561 static void rk3368_set_to_rgmii(struct rk_priv_data *bsp_priv,
 562                                 int tx_delay, int rx_delay)
 563 {
 564         struct device *dev = &bsp_priv->pdev->dev;
 565
 566         if (IS_ERR(bsp_priv->grf)) {
 567                 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
 568                 return;
 569         }
 570
 571         regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
 572                      RK3368_GMAC_PHY_INTF_SEL_RGMII |
 573                      RK3368_GMAC_RMII_MODE_CLR);
 574         regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON16,
 575                      DELAY_ENABLE(RK3368, tx_delay, rx_delay) |
 576                      RK3368_GMAC_CLK_RX_DL_CFG(rx_delay) |
 577                      RK3368_GMAC_CLK_TX_DL_CFG(tx_delay));
 578 }
 579
 580 static void rk3368_set_to_rmii(struct rk_priv_data *bsp_priv)
 581 {
 582         struct device *dev = &bsp_priv->pdev->dev;
 583
 584         if (IS_ERR(bsp_priv->grf)) {
 585                 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
 586                 return;
 587         }
 588
 589         regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
 590                      RK3368_GMAC_PHY_INTF_SEL_RMII | RK3368_GMAC_RMII_MODE);
 591 }
 592
 593 static void rk3368_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
 594 {
 595         struct device *dev = &bsp_priv->pdev->dev;
 596
 597         if (IS_ERR(bsp_priv->grf)) {
 598                 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
 599                 return;
 600         }
 601
 602         if (speed == 10)
 603                 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
 604                              RK3368_GMAC_CLK_2_5M);
 605         else if (speed == 100)
 606                 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
 607                              RK3368_GMAC_CLK_25M);
 608         else if (speed == 1000)
 609                 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
 610                              RK3368_GMAC_CLK_125M);
 611         else
 612                 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
 613 }
 614
 615 static void rk3368_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
 616 {
 617         struct device *dev = &bsp_priv->pdev->dev;
 618
 619         if (IS_ERR(bsp_priv->grf)) {
 620                 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
 621                 return;
 622         }
 623
 624         if (speed == 10) {
 625                 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
 626                              RK3368_GMAC_RMII_CLK_2_5M |
 627                              RK3368_GMAC_SPEED_10M);
 628         } else if (speed == 100) {
 629                 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
 630                              RK3368_GMAC_RMII_CLK_25M |
 631                              RK3368_GMAC_SPEED_100M);
 632         } else {
 633                 dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
 634         }
 635 }
 636
 637 static const struct rk_gmac_ops rk3368_ops = {
 638         .set_to_rgmii = rk3368_set_to_rgmii,
 639         .set_to_rmii = rk3368_set_to_rmii,
 640         .set_rgmii_speed = rk3368_set_rgmii_speed,
 641         .set_rmii_speed = rk3368_set_rmii_speed,
 642 };
 643
 644 #define RK3399_GRF_SOC_CON5     0xc214
 645 #define RK3399_GRF_SOC_CON6     0xc218
 646
 647 /* RK3399_GRF_SOC_CON5 */
 648 #define RK3399_GMAC_PHY_INTF_SEL_RGMII  (GRF_BIT(9) | GRF_CLR_BIT(10) | \
 649                                          GRF_CLR_BIT(11))
 650 #define RK3399_GMAC_PHY_INTF_SEL_RMII   (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \
 651                                          GRF_BIT(11))
 652 #define RK3399_GMAC_FLOW_CTRL           GRF_BIT(8)
 653 #define RK3399_GMAC_FLOW_CTRL_CLR       GRF_CLR_BIT(8)
 654 #define RK3399_GMAC_SPEED_10M           GRF_CLR_BIT(7)
 655 #define RK3399_GMAC_SPEED_100M          GRF_BIT(7)
 656 #define RK3399_GMAC_RMII_CLK_25M        GRF_BIT(3)
 657 #define RK3399_GMAC_RMII_CLK_2_5M       GRF_CLR_BIT(3)
 658 #define RK3399_GMAC_CLK_125M            (GRF_CLR_BIT(4) | GRF_CLR_BIT(5))
 659 #define RK3399_GMAC_CLK_25M             (GRF_BIT(4) | GRF_BIT(5))
 660 #define RK3399_GMAC_CLK_2_5M            (GRF_CLR_BIT(4) | GRF_BIT(5))
 661 #define RK3399_GMAC_RMII_MODE           GRF_BIT(6)
 662 #define RK3399_GMAC_RMII_MODE_CLR       GRF_CLR_BIT(6)
 663
 664 /* RK3399_GRF_SOC_CON6 */
 665 #define RK3399_GMAC_TXCLK_DLY_ENABLE    GRF_BIT(7)
 666 #define RK3399_GMAC_TXCLK_DLY_DISABLE   GRF_CLR_BIT(7)
 667 #define RK3399_GMAC_RXCLK_DLY_ENABLE    GRF_BIT(15)
 668 #define RK3399_GMAC_RXCLK_DLY_DISABLE   GRF_CLR_BIT(15)
 669 #define RK3399_GMAC_CLK_RX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 8)
 670 #define RK3399_GMAC_CLK_TX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 0)
 671
 672 static void rk3399_set_to_rgmii(struct rk_priv_data *bsp_priv,
 673                                 int tx_delay, int rx_delay)
 674 {
 675         struct device *dev = &bsp_priv->pdev->dev;
 676
 677         if (IS_ERR(bsp_priv->grf)) {
 678                 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
 679                 return;
 680         }
 681
 682         regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
 683                      RK3399_GMAC_PHY_INTF_SEL_RGMII |
 684                      RK3399_GMAC_RMII_MODE_CLR);
 685         regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON6,
 686                      DELAY_ENABLE(RK3399, tx_delay, rx_delay) |
 687                      RK3399_GMAC_CLK_RX_DL_CFG(rx_delay) |
 688                      RK3399_GMAC_CLK_TX_DL_CFG(tx_delay));
 689 }
 690
 691 static void rk3399_set_to_rmii(struct rk_priv_data *bsp_priv)
 692 {
 693         struct device *dev = &bsp_priv->pdev->dev;
 694
 695         if (IS_ERR(bsp_priv->grf)) {
 696                 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
 697                 return;
 698         }
 699
 700         regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
 701                      RK3399_GMAC_PHY_INTF_SEL_RMII | RK3399_GMAC_RMII_MODE);
 702 }
 703
 704 static void rk3399_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
 705 {
 706         struct device *dev = &bsp_priv->pdev->dev;
 707
 708         if (IS_ERR(bsp_priv->grf)) {
 709                 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
 710                 return;
 711         }
 712
 713         if (speed == 10)
 714                 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
 715                              RK3399_GMAC_CLK_2_5M);
 716         else if (speed == 100)
 717                 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
 718                              RK3399_GMAC_CLK_25M);
 719         else if (speed == 1000)
 720                 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
 721                              RK3399_GMAC_CLK_125M);
 722         else
 723                 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
 724 }
 725
 726 static void rk3399_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
 727 {
 728         struct device *dev = &bsp_priv->pdev->dev;
 729
 730         if (IS_ERR(bsp_priv->grf)) {
 731                 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
 732                 return;
 733         }
 734
 735         if (speed == 10) {
 736                 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
 737                              RK3399_GMAC_RMII_CLK_2_5M |
 738                              RK3399_GMAC_SPEED_10M);
 739         } else if (speed == 100) {
 740                 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
 741                              RK3399_GMAC_RMII_CLK_25M |
 742                              RK3399_GMAC_SPEED_100M);
 743         } else {
 744                 dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
 745         }
 746 }
 747
 748 static const struct rk_gmac_ops rk3399_ops = {
 749         .set_to_rgmii = rk3399_set_to_rgmii,
 750         .set_to_rmii = rk3399_set_to_rmii,
 751         .set_rgmii_speed = rk3399_set_rgmii_speed,
 752         .set_rmii_speed = rk3399_set_rmii_speed,
 753 };
 754
 755 static int gmac_clk_init(struct rk_priv_data *bsp_priv)
 756 {
 757         struct device *dev = &bsp_priv->pdev->dev;
 758
 759         bsp_priv->clk_enabled = false;
 760
 761         bsp_priv->mac_clk_rx = devm_clk_get(dev, "mac_clk_rx");
 762         if (IS_ERR(bsp_priv->mac_clk_rx))
 763                 dev_err(dev, "cannot get clock %s\n",
 764                         "mac_clk_rx");
 765
 766         bsp_priv->mac_clk_tx = devm_clk_get(dev, "mac_clk_tx");
 767         if (IS_ERR(bsp_priv->mac_clk_tx))
 768                 dev_err(dev, "cannot get clock %s\n",
 769                         "mac_clk_tx");
 770
 771         bsp_priv->aclk_mac = devm_clk_get(dev, "aclk_mac");
 772         if (IS_ERR(bsp_priv->aclk_mac))
 773                 dev_err(dev, "cannot get clock %s\n",
 774                         "aclk_mac");
 775
 776         bsp_priv->pclk_mac = devm_clk_get(dev, "pclk_mac");
 777         if (IS_ERR(bsp_priv->pclk_mac))
 778                 dev_err(dev, "cannot get clock %s\n",
 779                         "pclk_mac");
 780
 781         bsp_priv->clk_mac = devm_clk_get(dev, "stmmaceth");
 782         if (IS_ERR(bsp_priv->clk_mac))
 783                 dev_err(dev, "cannot get clock %s\n",
 784                         "stmmaceth");
 785
 786         if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII) {
 787                 bsp_priv->clk_mac_ref = devm_clk_get(dev, "clk_mac_ref");
 788                 if (IS_ERR(bsp_priv->clk_mac_ref))
 789                         dev_err(dev, "cannot get clock %s\n",
 790                                 "clk_mac_ref");
 791
 792                 if (!bsp_priv->clock_input) {
 793                         bsp_priv->clk_mac_refout =
 794                                 devm_clk_get(dev, "clk_mac_refout");
 795                         if (IS_ERR(bsp_priv->clk_mac_refout))
 796                                 dev_err(dev, "cannot get clock %s\n",
 797                                         "clk_mac_refout");
 798                 }
 799         }
 800
 801         if (bsp_priv->clock_input) {
 802                 dev_info(dev, "clock input from PHY\n");
 803         } else {
 804                 if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII)
 805                         clk_set_rate(bsp_priv->clk_mac, 50000000);
 806         }
 807
 808         return 0;
 809 }
 810
 811 static int gmac_clk_enable(struct rk_priv_data *bsp_priv, bool enable)
 812 {
 813         int phy_iface = bsp_priv->phy_iface;
 814
 815         if (enable) {
 816                 if (!bsp_priv->clk_enabled) {
 817                         if (phy_iface == PHY_INTERFACE_MODE_RMII) {
 818                                 if (!IS_ERR(bsp_priv->mac_clk_rx))
 819                                         clk_prepare_enable(
 820                                                 bsp_priv->mac_clk_rx);
 821
 822                                 if (!IS_ERR(bsp_priv->clk_mac_ref))
 823                                         clk_prepare_enable(
 824                                                 bsp_priv->clk_mac_ref);
 825
 826                                 if (!IS_ERR(bsp_priv->clk_mac_refout))
 827                                         clk_prepare_enable(
 828                                                 bsp_priv->clk_mac_refout);
 829                         }
 830
 831                         if (!IS_ERR(bsp_priv->aclk_mac))
 832                                 clk_prepare_enable(bsp_priv->aclk_mac);
 833
 834                         if (!IS_ERR(bsp_priv->pclk_mac))
 835                                 clk_prepare_enable(bsp_priv->pclk_mac);
 836
 837                         if (!IS_ERR(bsp_priv->mac_clk_tx))
 838                                 clk_prepare_enable(bsp_priv->mac_clk_tx);
 839
 840                         /**
 841                          * if (!IS_ERR(bsp_priv->clk_mac))
 842                          *      clk_prepare_enable(bsp_priv->clk_mac);
 843                          */
 844                         mdelay(5);
 845                         bsp_priv->clk_enabled = true;
 846                 }
 847         } else {
 848                 if (bsp_priv->clk_enabled) {
 849                         if (phy_iface == PHY_INTERFACE_MODE_RMII) {
 850                                 if (!IS_ERR(bsp_priv->mac_clk_rx))
 851                                         clk_disable_unprepare(
 852                                                 bsp_priv->mac_clk_rx);
 853
 854                                 if (!IS_ERR(bsp_priv->clk_mac_ref))
 855                                         clk_disable_unprepare(
 856                                                 bsp_priv->clk_mac_ref);
 857
 858                                 if (!IS_ERR(bsp_priv->clk_mac_refout))
 859                                         clk_disable_unprepare(
 860                                                 bsp_priv->clk_mac_refout);
 861                         }
 862
 863                         if (!IS_ERR(bsp_priv->aclk_mac))
 864                                 clk_disable_unprepare(bsp_priv->aclk_mac);
 865
 866                         if (!IS_ERR(bsp_priv->pclk_mac))
 867                                 clk_disable_unprepare(bsp_priv->pclk_mac);
 868
 869                         if (!IS_ERR(bsp_priv->mac_clk_tx))
 870                                 clk_disable_unprepare(bsp_priv->mac_clk_tx);
 871                         /**
 872                          * if (!IS_ERR(bsp_priv->clk_mac))
 873                          *      clk_disable_unprepare(bsp_priv->clk_mac);
 874                          */
 875                         bsp_priv->clk_enabled = false;
 876                 }
 877         }
 878
 879         return 0;
 880 }
 881
 882 static int phy_power_on(struct rk_priv_data *bsp_priv, bool enable)
 883 {
 884         struct regulator *ldo = bsp_priv->regulator;
 885         int ret;
 886         struct device *dev = &bsp_priv->pdev->dev;
 887
 888         if (!ldo) {
 889                 dev_err(dev, "no regulator found\n");
 890                 return -1;
 891         }
 892
 893         if (enable) {
 894                 ret = regulator_enable(ldo);
 895                 if (ret)
 896                         dev_err(dev, "fail to enable phy-supply\n");
 897         } else {
 898                 ret = regulator_disable(ldo);
 899                 if (ret)
 900                         dev_err(dev, "fail to disable phy-supply\n");
 901         }
 902
 903         return 0;
 904 }
 905
 906 static struct rk_priv_data *rk_gmac_setup(struct platform_device *pdev,
 907                                           const struct rk_gmac_ops *ops)
 908 {
 909         struct rk_priv_data *bsp_priv;
 910         struct device *dev = &pdev->dev;
 911         int ret;
 912         const char *strings = NULL;
 913         int value;
 914
 915         bsp_priv = devm_kzalloc(dev, sizeof(*bsp_priv), GFP_KERNEL);
 916         if (!bsp_priv)
 917                 return ERR_PTR(-ENOMEM);
 918
 919         bsp_priv->phy_iface = of_get_phy_mode(dev->of_node);
 920         bsp_priv->ops = ops;
 921
 922         bsp_priv->regulator = devm_regulator_get_optional(dev, "phy");
 923         if (IS_ERR(bsp_priv->regulator)) {
 924                 if (PTR_ERR(bsp_priv->regulator) == -EPROBE_DEFER) {
 925                         dev_err(dev, "phy regulator is not available yet, deferred probing\n");
 926                         return ERR_PTR(-EPROBE_DEFER);
 927                 }
 928                 dev_err(dev, "no regulator found\n");
 929                 bsp_priv->regulator = NULL;
 930         }
 931
 932         ret = of_property_read_string(dev->of_node, "clock_in_out", &strings);
 933         if (ret) {
 934                 dev_err(dev, "Can not read property: clock_in_out.\n");
 935                 bsp_priv->clock_input = true;
 936         } else {
 937                 dev_info(dev, "clock input or output? (%s).\n",
 938                          strings);
 939                 if (!strcmp(strings, "input"))
 940                         bsp_priv->clock_input = true;
 941                 else
 942                         bsp_priv->clock_input = false;
 943         }
 944
 945         ret = of_property_read_u32(dev->of_node, "tx_delay", &value);
 946         if (ret) {
 947                 bsp_priv->tx_delay = 0x30;
 948                 dev_err(dev, "Can not read property: tx_delay.");
 949                 dev_err(dev, "set tx_delay to 0x%x\n",
 950                         bsp_priv->tx_delay);
 951         } else {
 952                 dev_info(dev, "TX delay(0x%x).\n", value);
 953                 bsp_priv->tx_delay = value;
 954         }
 955
 956         ret = of_property_read_u32(dev->of_node, "rx_delay", &value);
 957         if (ret) {
 958                 bsp_priv->rx_delay = 0x10;
 959                 dev_err(dev, "Can not read property: rx_delay.");
 960                 dev_err(dev, "set rx_delay to 0x%x\n",
 961                         bsp_priv->rx_delay);
 962         } else {
 963                 dev_info(dev, "RX delay(0x%x).\n", value);
 964                 bsp_priv->rx_delay = value;
 965         }
 966
 967         bsp_priv->grf = syscon_regmap_lookup_by_phandle(dev->of_node,
 968                                                         "rockchip,grf");
 969         bsp_priv->pdev = pdev;
 970
 971         gmac_clk_init(bsp_priv);
 972
 973         return bsp_priv;
 974 }
 975
 976 static int rk_gmac_init(struct platform_device *pdev, void *priv)
 977 {
 978         struct rk_priv_data *bsp_priv = priv;
 979         int ret;
 980         struct device *dev = &pdev->dev;
 981
 982         /*rmii or rgmii*/
 983         switch (bsp_priv->phy_iface) {
 984         case PHY_INTERFACE_MODE_RGMII:
 985                 dev_info(dev, "init for RGMII\n");
 986                 bsp_priv->ops->set_to_rgmii(bsp_priv, bsp_priv->tx_delay,
 987                                             bsp_priv->rx_delay);
 988                 break;
 989         case PHY_INTERFACE_MODE_RGMII_ID:
 990                 dev_info(dev, "init for RGMII_ID\n");
 991                 bsp_priv->ops->set_to_rgmii(bsp_priv, 0, 0);
 992                 break;
 993         case PHY_INTERFACE_MODE_RGMII_RXID:
 994                 dev_info(dev, "init for RGMII_RXID\n");
 995                 bsp_priv->ops->set_to_rgmii(bsp_priv, bsp_priv->tx_delay, 0);
 996                 break;
 997         case PHY_INTERFACE_MODE_RGMII_TXID:
 998                 dev_info(dev, "init for RGMII_TXID\n");
 999                 bsp_priv->ops->set_to_rgmii(bsp_priv, 0, bsp_priv->rx_delay);
1000                 break;
1001         case PHY_INTERFACE_MODE_RMII:
1002                 dev_info(dev, "init for RMII\n");
1003                 bsp_priv->ops->set_to_rmii(bsp_priv);
1004                 break;
1005         default:
1006                 dev_err(dev, "NO interface defined!\n");
1007         }
1008
1009         ret = phy_power_on(bsp_priv, true);
1010         if (ret)
1011                 return ret;
1012
1013         ret = gmac_clk_enable(bsp_priv, true);
1014         if (ret)
1015                 return ret;
1016
1017         pm_runtime_enable(&pdev->dev);
1018         pm_runtime_get_sync(&pdev->dev);
1019
1020         return 0;
1021 }
1022
1023 static void rk_gmac_exit(struct platform_device *pdev, void *priv)
1024 {
1025         struct rk_priv_data *gmac = priv;
1026
1027         pm_runtime_put_sync(&pdev->dev);
1028         pm_runtime_disable(&pdev->dev);
1029
1030         phy_power_on(gmac, false);
1031         gmac_clk_enable(gmac, false);
1032 }
1033
1034 static void rk_fix_speed(void *priv, unsigned int speed)
1035 {
1036         struct rk_priv_data *bsp_priv = priv;
1037         struct device *dev = &bsp_priv->pdev->dev;
1038
1039         switch (bsp_priv->phy_iface) {
1040         case PHY_INTERFACE_MODE_RGMII:
1041         case PHY_INTERFACE_MODE_RGMII_ID:
1042         case PHY_INTERFACE_MODE_RGMII_RXID:
1043         case PHY_INTERFACE_MODE_RGMII_TXID:
1044                 bsp_priv->ops->set_rgmii_speed(bsp_priv, speed);
1045                 break;
1046         case PHY_INTERFACE_MODE_RMII:
1047                 bsp_priv->ops->set_rmii_speed(bsp_priv, speed);
1048                 break;
1049         default:
1050                 dev_err(dev, "unsupported interface %d", bsp_priv->phy_iface);
1051         }
1052 }
1053
1054 void __weak rk_devinfo_get_eth_mac(u8 *mac)
1055 {
1056 }
1057
1058 void rk_get_eth_addr(void *priv, unsigned char *addr)
1059 {
1060         int ret;
1061         struct rk_priv_data *bsp_priv = priv;
1062         struct device *dev = &bsp_priv->pdev->dev;
1063
1064         rk_devinfo_get_eth_mac(addr);
1065         if (is_valid_ether_addr(addr))
1066                 goto out;
1067
1068         ret = rk_vendor_read(LAN_MAC_ID, addr, 6);
1069         if (ret != 6 || is_zero_ether_addr(addr)) {
1070                 dev_err(dev, "%s: rk_vendor_read eth mac address failed (%d)",
1071                                         __func__, ret);
1072                 random_ether_addr(addr);
1073                 dev_err(dev, "%s: generate random eth mac address: %02x:%02x:%02x:%02x:%02x:%02x",
1074                                         __func__, addr[0], addr[1], addr[2],
1075                                         addr[3], addr[4], addr[5]);
1076                 ret = rk_vendor_write(LAN_MAC_ID, addr, 6);
1077                 if (ret != 0)
1078                         dev_err(dev, "%s: rk_vendor_write eth mac address failed (%d)",
1079                                         __func__, ret);
1080         }
1081
1082 out:
1083         dev_dbg(dev, "%s: mac address: %02x:%02x:%02x:%02x:%02x:%02x",
1084                                 __func__, addr[0], addr[1], addr[2],
1085                                 addr[3], addr[4], addr[5]);
1086 }
1087
1088 static int rk_gmac_probe(struct platform_device *pdev)
1089 {
1090         struct plat_stmmacenet_data *plat_dat;
1091         struct stmmac_resources stmmac_res;
1092         const struct rk_gmac_ops *data;
1093         int ret;
1094
1095         data = of_device_get_match_data(&pdev->dev);
1096         if (!data) {
1097                 dev_err(&pdev->dev, "no of match data provided\n");
1098                 return -EINVAL;
1099         }
1100
1101         ret = stmmac_get_platform_resources(pdev, &stmmac_res);
1102         if (ret)
1103                 return ret;
1104
1105         plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac);
1106         if (IS_ERR(plat_dat))
1107                 return PTR_ERR(plat_dat);
1108
1109         plat_dat->has_gmac = true;
1110         plat_dat->init = rk_gmac_init;
1111         plat_dat->exit = rk_gmac_exit;
1112         plat_dat->fix_mac_speed = rk_fix_speed;
1113         plat_dat->get_eth_addr = rk_get_eth_addr;
1114
1115         plat_dat->bsp_priv = rk_gmac_setup(pdev, data);
1116         if (IS_ERR(plat_dat->bsp_priv))
1117                 return PTR_ERR(plat_dat->bsp_priv);
1118
1119         ret = rk_gmac_init(pdev, plat_dat->bsp_priv);
1120         if (ret)
1121                 return ret;
1122
1123         return stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);
1124 }
1125
1126 static const struct of_device_id rk_gmac_dwmac_match[] = {
1127         { .compatible = "rockchip,rk3228-gmac", .data = &rk3228_ops },
1128         { .compatible = "rockchip,rk3288-gmac", .data = &rk3288_ops },
1129         { .compatible = "rockchip,rk3328-gmac", .data = &rk3328_ops },
1130         { .compatible = "rockchip,rk3366-gmac", .data = &rk3366_ops },
1131         { .compatible = "rockchip,rk3368-gmac", .data = &rk3368_ops },
1132         { .compatible = "rockchip,rk3399-gmac", .data = &rk3399_ops },
1133         { }
1134 };
1135 MODULE_DEVICE_TABLE(of, rk_gmac_dwmac_match);
1136
1137 static struct platform_driver rk_gmac_dwmac_driver = {
1138         .probe  = rk_gmac_probe,
1139         .remove = stmmac_pltfr_remove,
1140         .driver = {
1141                 .name           = "rk_gmac-dwmac",
1142                 .pm             = &stmmac_pltfr_pm_ops,
1143                 .of_match_table = rk_gmac_dwmac_match,
1144         },
1145 };
1146 module_platform_driver(rk_gmac_dwmac_driver);
1147
1148 MODULE_AUTHOR("Chen-Zhi (Roger Chen) <roger.chen@rock-chips.com>");
1149 MODULE_DESCRIPTION("Rockchip RK3288 DWMAC specific glue layer");
1150 MODULE_LICENSE("GPL");