drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c

   1 /*******************************************************************************
   2   This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
   3   DWC Ether MAC 10/100/1000 Universal version 3.41a  has been used for
   4   developing this code.
   5
   6   This only implements the mac core functions for this chip.
   7
   8   Copyright (C) 2007-2009  STMicroelectronics Ltd
   9
  10   This program is free software; you can redistribute it and/or modify it
  11   under the terms and conditions of the GNU General Public License,
  12   version 2, as published by the Free Software Foundation.
  13
  14   This program is distributed in the hope it will be useful, but WITHOUT
  15   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  17   more details.
  18
  19   You should have received a copy of the GNU General Public License along with
  20   this program; if not, write to the Free Software Foundation, Inc.,
  21   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  22
  23   The full GNU General Public License is included in this distribution in
  24   the file called "COPYING".
  25
  26   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
  27 *******************************************************************************/
  28
  29 #include <linux/crc32.h>
  30 #include <linux/slab.h>
  31 #include <linux/ethtool.h>
  32 #include <asm/io.h>
  33 #include "dwmac1000.h"
  34
  35 static void dwmac1000_core_init(void __iomem *ioaddr)
  36 {
  37         u32 value = readl(ioaddr + GMAC_CONTROL);
  38         value |= GMAC_CORE_INIT;
  39         writel(value, ioaddr + GMAC_CONTROL);
  40
  41         /* Mask GMAC interrupts */
  42         writel(0x207, ioaddr + GMAC_INT_MASK);
  43
  44 #ifdef STMMAC_VLAN_TAG_USED
  45         /* Tag detection without filtering */
  46         writel(0x0, ioaddr + GMAC_VLAN_TAG);
  47 #endif
  48 }
  49
  50 static int dwmac1000_rx_ipc_enable(void __iomem *ioaddr)
  51 {
  52         u32 value = readl(ioaddr + GMAC_CONTROL);
  53
  54         value |= GMAC_CONTROL_IPC;
  55         writel(value, ioaddr + GMAC_CONTROL);
  56
  57         value = readl(ioaddr + GMAC_CONTROL);
  58
  59         return !!(value & GMAC_CONTROL_IPC);
  60 }
  61
  62 static void dwmac1000_dump_regs(void __iomem *ioaddr)
  63 {
  64         int i;
  65         pr_info("\tDWMAC1000 regs (base addr = 0x%p)\n", ioaddr);
  66
  67         for (i = 0; i < 55; i++) {
  68                 int offset = i * 4;
  69                 pr_info("\tReg No. %d (offset 0x%x): 0x%08x\n", i,
  70                         offset, readl(ioaddr + offset));
  71         }
  72 }
  73
  74 static void dwmac1000_set_umac_addr(void __iomem *ioaddr, unsigned char *addr,
  75                                 unsigned int reg_n)
  76 {
  77         stmmac_set_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
  78                                 GMAC_ADDR_LOW(reg_n));
  79 }
  80
  81 static void dwmac1000_get_umac_addr(void __iomem *ioaddr, unsigned char *addr,
  82                                 unsigned int reg_n)
  83 {
  84         stmmac_get_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
  85                                 GMAC_ADDR_LOW(reg_n));
  86 }
  87
  88 static void dwmac1000_set_filter(struct net_device *dev, int id)
  89 {
  90         void __iomem *ioaddr = (void __iomem *) dev->base_addr;
  91         unsigned int value = 0;
  92         unsigned int perfect_addr_number;
  93
  94         CHIP_DBG(KERN_INFO "%s: # mcasts %d, # unicast %d\n",
  95                  __func__, netdev_mc_count(dev), netdev_uc_count(dev));
  96
  97         if (dev->flags & IFF_PROMISC)
  98                 value = GMAC_FRAME_FILTER_PR;
  99         else if ((netdev_mc_count(dev) > HASH_TABLE_SIZE)
 100                    || (dev->flags & IFF_ALLMULTI)) {
 101                 value = GMAC_FRAME_FILTER_PM;   /* pass all multi */
 102                 writel(0xffffffff, ioaddr + GMAC_HASH_HIGH);
 103                 writel(0xffffffff, ioaddr + GMAC_HASH_LOW);
 104         } else if (!netdev_mc_empty(dev)) {
 105                 u32 mc_filter[2];
 106                 struct netdev_hw_addr *ha;
 107
 108                 /* Hash filter for multicast */
 109                 value = GMAC_FRAME_FILTER_HMC;
 110
 111                 memset(mc_filter, 0, sizeof(mc_filter));
 112                 netdev_for_each_mc_addr(ha, dev) {
 113                         /* The upper 6 bits of the calculated CRC are used to
 114                            index the contens of the hash table */
 115                         int bit_nr =
 116                             bitrev32(~crc32_le(~0, ha->addr, 6)) >> 26;
 117                         /* The most significant bit determines the register to
 118                          * use (H/L) while the other 5 bits determine the bit
 119                          * within the register. */
 120                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
 121                 }
 122                 writel(mc_filter[0], ioaddr + GMAC_HASH_LOW);
 123                 writel(mc_filter[1], ioaddr + GMAC_HASH_HIGH);
 124         }
 125
 126         /* Extra 16 regs are available in cores newer than the 3.40. */
 127         if (id > DWMAC_CORE_3_40)
 128                 perfect_addr_number = GMAC_MAX_PERFECT_ADDRESSES;
 129         else
 130                 perfect_addr_number = GMAC_MAX_PERFECT_ADDRESSES / 2;
 131
 132         /* Handle multiple unicast addresses (perfect filtering)*/
 133         if (netdev_uc_count(dev) > perfect_addr_number)
 134                 /* Switch to promiscuous mode is more than 16 addrs
 135                    are required */
 136                 value |= GMAC_FRAME_FILTER_PR;
 137         else {
 138                 int reg = 1;
 139                 struct netdev_hw_addr *ha;
 140
 141                 netdev_for_each_uc_addr(ha, dev) {
 142                         dwmac1000_set_umac_addr(ioaddr, ha->addr, reg);
 143                         reg++;
 144                 }
 145         }
 146
 147 #ifdef FRAME_FILTER_DEBUG
 148         /* Enable Receive all mode (to debug filtering_fail errors) */
 149         value |= GMAC_FRAME_FILTER_RA;
 150 #endif
 151         writel(value, ioaddr + GMAC_FRAME_FILTER);
 152
 153         CHIP_DBG(KERN_INFO "\tFrame Filter reg: 0x%08x\n\tHash regs: "
 154             "HI 0x%08x, LO 0x%08x\n", readl(ioaddr + GMAC_FRAME_FILTER),
 155             readl(ioaddr + GMAC_HASH_HIGH), readl(ioaddr + GMAC_HASH_LOW));
 156 }
 157
 158 static void dwmac1000_flow_ctrl(void __iomem *ioaddr, unsigned int duplex,
 159                            unsigned int fc, unsigned int pause_time)
 160 {
 161         unsigned int flow = 0;
 162
 163         CHIP_DBG(KERN_DEBUG "GMAC Flow-Control:\n");
 164         if (fc & FLOW_RX) {
 165                 CHIP_DBG(KERN_DEBUG "\tReceive Flow-Control ON\n");
 166                 flow |= GMAC_FLOW_CTRL_RFE;
 167         }
 168         if (fc & FLOW_TX) {
 169                 CHIP_DBG(KERN_DEBUG "\tTransmit Flow-Control ON\n");
 170                 flow |= GMAC_FLOW_CTRL_TFE;
 171         }
 172
 173         if (duplex) {
 174                 CHIP_DBG(KERN_DEBUG "\tduplex mode: PAUSE %d\n", pause_time);
 175                 flow |= (pause_time << GMAC_FLOW_CTRL_PT_SHIFT);
 176         }
 177
 178         writel(flow, ioaddr + GMAC_FLOW_CTRL);
 179 }
 180
 181 static void dwmac1000_pmt(void __iomem *ioaddr, unsigned long mode)
 182 {
 183         unsigned int pmt = 0;
 184
 185         if (mode & WAKE_MAGIC) {
 186                 CHIP_DBG(KERN_DEBUG "GMAC: WOL Magic frame\n");
 187                 pmt |= power_down | magic_pkt_en;
 188         }
 189         if (mode & WAKE_UCAST) {
 190                 CHIP_DBG(KERN_DEBUG "GMAC: WOL on global unicast\n");
 191                 pmt |= global_unicast;
 192         }
 193
 194         writel(pmt, ioaddr + GMAC_PMT);
 195 }
 196
 197 static int dwmac1000_irq_status(void __iomem *ioaddr,
 198                                 struct stmmac_extra_stats *x)
 199 {
 200         u32 intr_status = readl(ioaddr + GMAC_INT_STATUS);
 201         int ret = 0;
 202
 203         /* Not used events (e.g. MMC interrupts) are not handled. */
 204         if ((intr_status & mmc_tx_irq)) {
 205                 CHIP_DBG(KERN_INFO "GMAC: MMC tx interrupt: 0x%08x\n",
 206                     readl(ioaddr + GMAC_MMC_TX_INTR));
 207                 x->mmc_tx_irq_n++;
 208         }
 209         if (unlikely(intr_status & mmc_rx_irq)) {
 210                 CHIP_DBG(KERN_INFO "GMAC: MMC rx interrupt: 0x%08x\n",
 211                     readl(ioaddr + GMAC_MMC_RX_INTR));
 212                 x->mmc_rx_irq_n++;
 213         }
 214         if (unlikely(intr_status & mmc_rx_csum_offload_irq)) {
 215                 CHIP_DBG(KERN_INFO "GMAC: MMC rx csum offload: 0x%08x\n",
 216                     readl(ioaddr + GMAC_MMC_RX_CSUM_OFFLOAD));
 217                 x->mmc_rx_csum_offload_irq_n++;
 218         }
 219         if (unlikely(intr_status & pmt_irq)) {
 220                 CHIP_DBG(KERN_INFO "GMAC: received Magic frame\n");
 221                 /* clear the PMT bits 5 and 6 by reading the PMT
 222                  * status register. */
 223                 readl(ioaddr + GMAC_PMT);
 224                 x->irq_receive_pmt_irq_n++;
 225         }
 226         /* MAC trx/rx EEE LPI entry/exit interrupts */
 227         if (intr_status & lpiis_irq) {
 228                 /* Clean LPI interrupt by reading the Reg 12 */
 229                 ret = readl(ioaddr + LPI_CTRL_STATUS);
 230
 231                 if (ret & LPI_CTRL_STATUS_TLPIEN) {
 232                         CHIP_DBG(KERN_INFO "GMAC TX entered in LPI\n");
 233                         x->irq_tx_path_in_lpi_mode_n++;
 234                 }
 235                 if (ret & LPI_CTRL_STATUS_TLPIEX) {
 236                         CHIP_DBG(KERN_INFO "GMAC TX exit from LPI\n");
 237                         x->irq_tx_path_exit_lpi_mode_n++;
 238                 }
 239                 if (ret & LPI_CTRL_STATUS_RLPIEN) {
 240                         CHIP_DBG(KERN_INFO "GMAC RX entered in LPI\n");
 241                         x->irq_rx_path_in_lpi_mode_n++;
 242                 }
 243                 if (ret & LPI_CTRL_STATUS_RLPIEX) {
 244                         CHIP_DBG(KERN_INFO "GMAC RX exit from LPI\n");
 245                         x->irq_rx_path_exit_lpi_mode_n++;
 246                 }
 247         }
 248
 249         if ((intr_status & pcs_ane_irq) || (intr_status & pcs_link_irq)) {
 250                 CHIP_DBG(KERN_INFO "GMAC PCS ANE IRQ\n");
 251                 readl(ioaddr + GMAC_AN_STATUS);
 252                 x->irq_pcs_ane_n++;
 253         }
 254         if (intr_status & rgmii_irq) {
 255                 u32 status  = readl(ioaddr + GMAC_S_R_GMII);
 256                 CHIP_DBG(KERN_INFO "GMAC RGMII/SGMII interrupt\n");
 257                 x->irq_rgmii_n++;
 258
 259                 /* Save and dump the link status. */
 260                 if (status & GMAC_S_R_GMII_LINK) {
 261                         int speed_value = (status & GMAC_S_R_GMII_SPEED) >>
 262                                           GMAC_S_R_GMII_SPEED_SHIFT;
 263                         x->pcs_duplex = (status & GMAC_S_R_GMII_MODE);
 264
 265                         if (speed_value == GMAC_S_R_GMII_SPEED_125)
 266                                 x->pcs_speed = SPEED_1000;
 267                         else if (speed_value == GMAC_S_R_GMII_SPEED_25)
 268                                 x->pcs_speed = SPEED_100;
 269                         else
 270                                 x->pcs_speed = SPEED_10;
 271
 272                         x->pcs_link = 1;
 273                         pr_debug("Link is Up - %d/%s\n", (int) x->pcs_speed,
 274                                  x->pcs_duplex ? "Full" : "Half");
 275                 } else {
 276                         x->pcs_link = 0;
 277                         pr_debug("Link is Down\n");
 278                 }
 279         }
 280
 281         return ret;
 282 }
 283
 284 static void  dwmac1000_set_eee_mode(void __iomem *ioaddr)
 285 {
 286         u32 value;
 287
 288         /* Enable the link status receive on RGMII, SGMII ore SMII
 289          * receive path and instruct the transmit to enter in LPI
 290          * state. */
 291         value = readl(ioaddr + LPI_CTRL_STATUS);
 292         value |= LPI_CTRL_STATUS_LPIEN | LPI_CTRL_STATUS_LPITXA;
 293         writel(value, ioaddr + LPI_CTRL_STATUS);
 294 }
 295
 296 static void  dwmac1000_reset_eee_mode(void __iomem *ioaddr)
 297 {
 298         u32 value;
 299
 300         value = readl(ioaddr + LPI_CTRL_STATUS);
 301         value &= ~(LPI_CTRL_STATUS_LPIEN | LPI_CTRL_STATUS_LPITXA);
 302         writel(value, ioaddr + LPI_CTRL_STATUS);
 303 }
 304
 305 static void  dwmac1000_set_eee_pls(void __iomem *ioaddr, int link)
 306 {
 307         u32 value;
 308
 309         value = readl(ioaddr + LPI_CTRL_STATUS);
 310
 311         if (link)
 312                 value |= LPI_CTRL_STATUS_PLS;
 313         else
 314                 value &= ~LPI_CTRL_STATUS_PLS;
 315
 316         writel(value, ioaddr + LPI_CTRL_STATUS);
 317 }
 318
 319 static void  dwmac1000_set_eee_timer(void __iomem *ioaddr, int ls, int tw)
 320 {
 321         int value = ((tw & 0xffff)) | ((ls & 0x7ff) << 16);
 322
 323         /* Program the timers in the LPI timer control register:
 324          * LS: minimum time (ms) for which the link
 325          *  status from PHY should be ok before transmitting
 326          *  the LPI pattern.
 327          * TW: minimum time (us) for which the core waits
 328          *  after it has stopped transmitting the LPI pattern.
 329          */
 330         writel(value, ioaddr + LPI_TIMER_CTRL);
 331 }
 332
 333 static void dwmac1000_ctrl_ane(void __iomem *ioaddr, bool restart)
 334 {
 335         u32 value;
 336
 337         value = readl(ioaddr + GMAC_AN_CTRL);
 338         /* auto negotiation enable and External Loopback enable */
 339         value = GMAC_AN_CTRL_ANE | GMAC_AN_CTRL_ELE;
 340
 341         if (restart)
 342                 value |= GMAC_AN_CTRL_RAN;
 343
 344         writel(value, ioaddr + GMAC_AN_CTRL);
 345 }
 346
 347 static void dwmac1000_get_adv(void __iomem *ioaddr, struct rgmii_adv *adv)
 348 {
 349         u32 value = readl(ioaddr + GMAC_ANE_ADV);
 350
 351         if (value & GMAC_ANE_FD)
 352                 adv->duplex = DUPLEX_FULL;
 353         if (value & GMAC_ANE_HD)
 354                 adv->duplex |= DUPLEX_HALF;
 355
 356         adv->pause = (value & GMAC_ANE_PSE) >> GMAC_ANE_PSE_SHIFT;
 357
 358         value = readl(ioaddr + GMAC_ANE_LPA);
 359
 360         if (value & GMAC_ANE_FD)
 361                 adv->lp_duplex = DUPLEX_FULL;
 362         if (value & GMAC_ANE_HD)
 363                 adv->lp_duplex = DUPLEX_HALF;
 364
 365         adv->lp_pause = (value & GMAC_ANE_PSE) >> GMAC_ANE_PSE_SHIFT;
 366 }
 367
 368 static const struct stmmac_ops dwmac1000_ops = {
 369         .core_init = dwmac1000_core_init,
 370         .rx_ipc = dwmac1000_rx_ipc_enable,
 371         .dump_regs = dwmac1000_dump_regs,
 372         .host_irq_status = dwmac1000_irq_status,
 373         .set_filter = dwmac1000_set_filter,
 374         .flow_ctrl = dwmac1000_flow_ctrl,
 375         .pmt = dwmac1000_pmt,
 376         .set_umac_addr = dwmac1000_set_umac_addr,
 377         .get_umac_addr = dwmac1000_get_umac_addr,
 378         .set_eee_mode =  dwmac1000_set_eee_mode,
 379         .reset_eee_mode =  dwmac1000_reset_eee_mode,
 380         .set_eee_timer =  dwmac1000_set_eee_timer,
 381         .set_eee_pls =  dwmac1000_set_eee_pls,
 382         .ctrl_ane = dwmac1000_ctrl_ane,
 383         .get_adv = dwmac1000_get_adv,
 384 };
 385
 386 struct mac_device_info *dwmac1000_setup(void __iomem *ioaddr)
 387 {
 388         struct mac_device_info *mac;
 389         u32 hwid = readl(ioaddr + GMAC_VERSION);
 390
 391         mac = kzalloc(sizeof(const struct mac_device_info), GFP_KERNEL);
 392         if (!mac)
 393                 return NULL;
 394
 395         mac->mac = &dwmac1000_ops;
 396         mac->dma = &dwmac1000_dma_ops;
 397
 398         mac->link.port = GMAC_CONTROL_PS;
 399         mac->link.duplex = GMAC_CONTROL_DM;
 400         mac->link.speed = GMAC_CONTROL_FES;
 401         mac->mii.addr = GMAC_MII_ADDR;
 402         mac->mii.data = GMAC_MII_DATA;
 403         mac->synopsys_uid = hwid;
 404
 405         return mac;
 406 }