1 /*******************************************************************************
2 This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
3 DWC Ether MAC 10/100/1000 Universal version 3.41a has been used for
6 This contains the functions to handle the dma.
8 Copyright (C) 2007-2009 STMicroelectronics Ltd
10 This program is free software; you can redistribute it and/or modify it
11 under the terms and conditions of the GNU General Public License,
12 version 2, as published by the Free Software Foundation.
14 This program is distributed in the hope it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 You should have received a copy of the GNU General Public License along with
20 this program; if not, write to the Free Software Foundation, Inc.,
21 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
23 The full GNU General Public License is included in this distribution in
24 the file called "COPYING".
26 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
27 *******************************************************************************/
30 #include "dwmac1000.h"
31 #include "dwmac_dma.h"
33 static int dwmac1000_dma_init(void __iomem *ioaddr, int pbl, int fb, int mb,
34 int burst_len, u32 dma_tx, u32 dma_rx, int atds)
36 u32 value = readl(ioaddr + DMA_BUS_MODE);
40 value |= DMA_BUS_MODE_SFT_RESET;
41 writel(value, ioaddr + DMA_BUS_MODE);
44 if (!(readl(ioaddr + DMA_BUS_MODE) & DMA_BUS_MODE_SFT_RESET))
52 * Set the DMA PBL (Programmable Burst Length) mode
53 * Before stmmac core 3.50 this mode bit was 4xPBL, and
54 * post 3.5 mode bit acts as 8*PBL.
55 * For core rev < 3.5, when the core is set for 4xPBL mode, the
56 * DMA transfers the data in 4, 8, 16, 32, 64 & 128 beats
57 * depending on pbl value.
58 * For core rev > 3.5, when the core is set for 8xPBL mode, the
59 * DMA transfers the data in 8, 16, 32, 64, 128 & 256 beats
60 * depending on pbl value.
62 value = DMA_BUS_MODE_PBL | ((pbl << DMA_BUS_MODE_PBL_SHIFT) |
63 (pbl << DMA_BUS_MODE_RPBL_SHIFT));
65 /* Set the Fixed burst mode */
67 value |= DMA_BUS_MODE_FB;
69 /* Mixed Burst has no effect when fb is set */
71 value |= DMA_BUS_MODE_MB;
73 #ifdef CONFIG_STMMAC_DA
74 value |= DMA_BUS_MODE_DA; /* Rx has priority over tx */
78 value |= DMA_BUS_MODE_ATDS;
80 writel(value, ioaddr + DMA_BUS_MODE);
82 /* In case of GMAC AXI configuration, program the DMA_AXI_BUS_MODE
83 * for supported bursts.
85 * Note: This is applicable only for revision GMACv3.61a. For
86 * older version this register is reserved and shall have no
90 * For Fixed Burst Mode: if we directly write 0xFF to this
91 * register using the configurations pass from platform code,
92 * this would ensure that all bursts supported by core are set
93 * and those which are not supported would remain ineffective.
95 * For Non Fixed Burst Mode: provide the maximum value of the
96 * burst length. Any burst equal or below the provided burst
97 * length would be allowed to perform.
99 writel(burst_len, ioaddr + DMA_AXI_BUS_MODE);
101 /* Mask interrupts by writing to CSR7 */
102 writel(DMA_INTR_DEFAULT_MASK, ioaddr + DMA_INTR_ENA);
104 /* RX/TX descriptor base address lists must be written into
105 * DMA CSR3 and CSR4, respectively
107 writel(dma_tx, ioaddr + DMA_TX_BASE_ADDR);
108 writel(dma_rx, ioaddr + DMA_RCV_BASE_ADDR);
113 static void dwmac1000_dma_operation_mode(void __iomem *ioaddr, int txmode,
116 u32 csr6 = readl(ioaddr + DMA_CONTROL);
118 if (txmode == SF_DMA_MODE) {
119 CHIP_DBG(KERN_DEBUG "GMAC: enable TX store and forward mode\n");
120 /* Transmit COE type 2 cannot be done in cut-through mode. */
121 csr6 |= DMA_CONTROL_TSF;
122 /* Operating on second frame increase the performance
123 * especially when transmit store-and-forward is used.
125 csr6 |= DMA_CONTROL_OSF;
127 CHIP_DBG(KERN_DEBUG "GMAC: disabling TX SF (threshold %d)\n",
129 csr6 &= ~DMA_CONTROL_TSF;
130 csr6 &= DMA_CONTROL_TC_TX_MASK;
131 /* Set the transmit threshold */
133 csr6 |= DMA_CONTROL_TTC_32;
134 else if (txmode <= 64)
135 csr6 |= DMA_CONTROL_TTC_64;
136 else if (txmode <= 128)
137 csr6 |= DMA_CONTROL_TTC_128;
138 else if (txmode <= 192)
139 csr6 |= DMA_CONTROL_TTC_192;
141 csr6 |= DMA_CONTROL_TTC_256;
144 if (rxmode == SF_DMA_MODE) {
145 CHIP_DBG(KERN_DEBUG "GMAC: enable RX store and forward mode\n");
146 csr6 |= DMA_CONTROL_RSF;
148 CHIP_DBG(KERN_DEBUG "GMAC: disable RX SF mode (threshold %d)\n",
150 csr6 &= ~DMA_CONTROL_RSF;
151 csr6 &= DMA_CONTROL_TC_RX_MASK;
153 csr6 |= DMA_CONTROL_RTC_32;
154 else if (rxmode <= 64)
155 csr6 |= DMA_CONTROL_RTC_64;
156 else if (rxmode <= 96)
157 csr6 |= DMA_CONTROL_RTC_96;
159 csr6 |= DMA_CONTROL_RTC_128;
162 writel(csr6, ioaddr + DMA_CONTROL);
165 static void dwmac1000_dump_dma_regs(void __iomem *ioaddr)
168 pr_info(" DMA registers\n");
169 for (i = 0; i < 22; i++) {
170 if ((i < 9) || (i > 17)) {
172 pr_err("\t Reg No. %d (offset 0x%x): 0x%08x\n", i,
173 (DMA_BUS_MODE + offset),
174 readl(ioaddr + DMA_BUS_MODE + offset));
179 static unsigned int dwmac1000_get_hw_feature(void __iomem *ioaddr)
181 return readl(ioaddr + DMA_HW_FEATURE);
184 static void dwmac1000_rx_watchdog(void __iomem *ioaddr, u32 riwt)
186 writel(riwt, ioaddr + DMA_RX_WATCHDOG);
189 const struct stmmac_dma_ops dwmac1000_dma_ops = {
190 .init = dwmac1000_dma_init,
191 .dump_regs = dwmac1000_dump_dma_regs,
192 .dma_mode = dwmac1000_dma_operation_mode,
193 .enable_dma_transmission = dwmac_enable_dma_transmission,
194 .enable_dma_irq = dwmac_enable_dma_irq,
195 .disable_dma_irq = dwmac_disable_dma_irq,
196 .start_tx = dwmac_dma_start_tx,
197 .stop_tx = dwmac_dma_stop_tx,
198 .start_rx = dwmac_dma_start_rx,
199 .stop_rx = dwmac_dma_stop_rx,
200 .dma_interrupt = dwmac_dma_interrupt,
201 .get_hw_feature = dwmac1000_get_hw_feature,
202 .rx_watchdog = dwmac1000_rx_watchdog,