drivers/net/ethernet/stmicro/stmmac/stmmac_main.c

   1 /*******************************************************************************
   2   This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
   3   ST Ethernet IPs are built around a Synopsys IP Core.
   4
   5         Copyright(C) 2007-2011 STMicroelectronics Ltd
   6
   7   This program is free software; you can redistribute it and/or modify it
   8   under the terms and conditions of the GNU General Public License,
   9   version 2, as published by the Free Software Foundation.
  10
  11   This program is distributed in the hope it will be useful, but WITHOUT
  12   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14   more details.
  15
  16   You should have received a copy of the GNU General Public License along with
  17   this program; if not, write to the Free Software Foundation, Inc.,
  18   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  19
  20   The full GNU General Public License is included in this distribution in
  21   the file called "COPYING".
  22
  23   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
  24
  25   Documentation available at:
  26         http://www.stlinux.com
  27   Support available at:
  28         https://bugzilla.stlinux.com/
  29 *******************************************************************************/
  30
  31 #include <linux/clk.h>
  32 #include <linux/kernel.h>
  33 #include <linux/interrupt.h>
  34 #include <linux/ip.h>
  35 #include <linux/tcp.h>
  36 #include <linux/skbuff.h>
  37 #include <linux/ethtool.h>
  38 #include <linux/if_ether.h>
  39 #include <linux/crc32.h>
  40 #include <linux/mii.h>
  41 #include <linux/if.h>
  42 #include <linux/if_vlan.h>
  43 #include <linux/dma-mapping.h>
  44 #include <linux/slab.h>
  45 #include <linux/prefetch.h>
  46 #ifdef CONFIG_STMMAC_DEBUG_FS
  47 #include <linux/debugfs.h>
  48 #include <linux/seq_file.h>
  49 #endif
  50 #include "stmmac.h"
  51
  52 #undef STMMAC_DEBUG
  53 /*#define STMMAC_DEBUG*/
  54 #ifdef STMMAC_DEBUG
  55 #define DBG(nlevel, klevel, fmt, args...) \
  56                 ((void)(netif_msg_##nlevel(priv) && \
  57                 printk(KERN_##klevel fmt, ## args)))
  58 #else
  59 #define DBG(nlevel, klevel, fmt, args...) do { } while (0)
  60 #endif
  61
  62 #undef STMMAC_RX_DEBUG
  63 /*#define STMMAC_RX_DEBUG*/
  64 #ifdef STMMAC_RX_DEBUG
  65 #define RX_DBG(fmt, args...)  printk(fmt, ## args)
  66 #else
  67 #define RX_DBG(fmt, args...)  do { } while (0)
  68 #endif
  69
  70 #undef STMMAC_XMIT_DEBUG
  71 /*#define STMMAC_XMIT_DEBUG*/
  72 #ifdef STMMAC_XMIT_DEBUG
  73 #define TX_DBG(fmt, args...)  printk(fmt, ## args)
  74 #else
  75 #define TX_DBG(fmt, args...)  do { } while (0)
  76 #endif
  77
  78 #define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x)
  79 #define JUMBO_LEN       9000
  80
  81 /* Module parameters */
  82 #define TX_TIMEO 5000 /* default 5 seconds */
  83 static int watchdog = TX_TIMEO;
  84 module_param(watchdog, int, S_IRUGO | S_IWUSR);
  85 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds");
  86
  87 static int debug = -1;          /* -1: default, 0: no output, 16:  all */
  88 module_param(debug, int, S_IRUGO | S_IWUSR);
  89 MODULE_PARM_DESC(debug, "Message Level (0: no output, 16: all)");
  90
  91 int phyaddr = -1;
  92 module_param(phyaddr, int, S_IRUGO);
  93 MODULE_PARM_DESC(phyaddr, "Physical device address");
  94
  95 #define DMA_TX_SIZE 256
  96 static int dma_txsize = DMA_TX_SIZE;
  97 module_param(dma_txsize, int, S_IRUGO | S_IWUSR);
  98 MODULE_PARM_DESC(dma_txsize, "Number of descriptors in the TX list");
  99
 100 #define DMA_RX_SIZE 256
 101 static int dma_rxsize = DMA_RX_SIZE;
 102 module_param(dma_rxsize, int, S_IRUGO | S_IWUSR);
 103 MODULE_PARM_DESC(dma_rxsize, "Number of descriptors in the RX list");
 104
 105 static int flow_ctrl = FLOW_OFF;
 106 module_param(flow_ctrl, int, S_IRUGO | S_IWUSR);
 107 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]");
 108
 109 static int pause = PAUSE_TIME;
 110 module_param(pause, int, S_IRUGO | S_IWUSR);
 111 MODULE_PARM_DESC(pause, "Flow Control Pause Time");
 112
 113 #define TC_DEFAULT 64
 114 static int tc = TC_DEFAULT;
 115 module_param(tc, int, S_IRUGO | S_IWUSR);
 116 MODULE_PARM_DESC(tc, "DMA threshold control value");
 117
 118 #define DMA_BUFFER_SIZE BUF_SIZE_2KiB
 119 static int buf_sz = DMA_BUFFER_SIZE;
 120 module_param(buf_sz, int, S_IRUGO | S_IWUSR);
 121 MODULE_PARM_DESC(buf_sz, "DMA buffer size");
 122
 123 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
 124                                       NETIF_MSG_LINK | NETIF_MSG_IFUP |
 125                                       NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);
 126
 127 #define STMMAC_DEFAULT_LPI_TIMER        1000
 128 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER;
 129 module_param(eee_timer, int, S_IRUGO | S_IWUSR);
 130 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec");
 131 #define STMMAC_LPI_TIMER(x) (jiffies + msecs_to_jiffies(x))
 132
 133 /* By default the driver will use the ring mode to manage tx and rx descriptors
 134  * but passing this value so user can force to use the chain instead of the ring
 135  */
 136 static unsigned int chain_mode;
 137 module_param(chain_mode, int, S_IRUGO);
 138 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode");
 139
 140 static irqreturn_t stmmac_interrupt(int irq, void *dev_id);
 141
 142 #ifdef CONFIG_STMMAC_DEBUG_FS
 143 static int stmmac_init_fs(struct net_device *dev);
 144 static void stmmac_exit_fs(void);
 145 #endif
 146
 147 #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x))
 148
 149 /**
 150  * stmmac_verify_args - verify the driver parameters.
 151  * Description: it verifies if some wrong parameter is passed to the driver.
 152  * Note that wrong parameters are replaced with the default values.
 153  */
 154 static void stmmac_verify_args(void)
 155 {
 156         if (unlikely(watchdog < 0))
 157                 watchdog = TX_TIMEO;
 158         if (unlikely(dma_rxsize < 0))
 159                 dma_rxsize = DMA_RX_SIZE;
 160         if (unlikely(dma_txsize < 0))
 161                 dma_txsize = DMA_TX_SIZE;
 162         if (unlikely((buf_sz < DMA_BUFFER_SIZE) || (buf_sz > BUF_SIZE_16KiB)))
 163                 buf_sz = DMA_BUFFER_SIZE;
 164         if (unlikely(flow_ctrl > 1))
 165                 flow_ctrl = FLOW_AUTO;
 166         else if (likely(flow_ctrl < 0))
 167                 flow_ctrl = FLOW_OFF;
 168         if (unlikely((pause < 0) || (pause > 0xffff)))
 169                 pause = PAUSE_TIME;
 170         if (eee_timer < 0)
 171                 eee_timer = STMMAC_DEFAULT_LPI_TIMER;
 172 }
 173
 174 static void stmmac_clk_csr_set(struct stmmac_priv *priv)
 175 {
 176         u32 clk_rate;
 177
 178         clk_rate = clk_get_rate(priv->stmmac_clk);
 179
 180         /* Platform provided default clk_csr would be assumed valid
 181          * for all other cases except for the below mentioned ones. */
 182         if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) {
 183                 if (clk_rate < CSR_F_35M)
 184                         priv->clk_csr = STMMAC_CSR_20_35M;
 185                 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M))
 186                         priv->clk_csr = STMMAC_CSR_35_60M;
 187                 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M))
 188                         priv->clk_csr = STMMAC_CSR_60_100M;
 189                 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M))
 190                         priv->clk_csr = STMMAC_CSR_100_150M;
 191                 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M))
 192                         priv->clk_csr = STMMAC_CSR_150_250M;
 193                 else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M))
 194                         priv->clk_csr = STMMAC_CSR_250_300M;
 195         } /* For values higher than the IEEE 802.3 specified frequency
 196            * we can not estimate the proper divider as it is not known
 197            * the frequency of clk_csr_i. So we do not change the default
 198            * divider. */
 199 }
 200
 201 #if defined(STMMAC_XMIT_DEBUG) || defined(STMMAC_RX_DEBUG)
 202 static void print_pkt(unsigned char *buf, int len)
 203 {
 204         int j;
 205         pr_info("len = %d byte, buf addr: 0x%p", len, buf);
 206         for (j = 0; j < len; j++) {
 207                 if ((j % 16) == 0)
 208                         pr_info("\n %03x:", j);
 209                 pr_info(" %02x", buf[j]);
 210         }
 211         pr_info("\n");
 212 }
 213 #endif
 214
 215 /* minimum number of free TX descriptors required to wake up TX process */
 216 #define STMMAC_TX_THRESH(x)     (x->dma_tx_size/4)
 217
 218 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv)
 219 {
 220         return priv->dirty_tx + priv->dma_tx_size - priv->cur_tx - 1;
 221 }
 222
 223 /* On some ST platforms, some HW system configuraton registers have to be
 224  * set according to the link speed negotiated.
 225  */
 226 static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv *priv)
 227 {
 228         struct phy_device *phydev = priv->phydev;
 229
 230         if (likely(priv->plat->fix_mac_speed))
 231                 priv->plat->fix_mac_speed(priv->plat->bsp_priv,
 232                                           phydev->speed);
 233 }
 234
 235 static void stmmac_enable_eee_mode(struct stmmac_priv *priv)
 236 {
 237         /* Check and enter in LPI mode */
 238         if ((priv->dirty_tx == priv->cur_tx) &&
 239             (priv->tx_path_in_lpi_mode == false))
 240                 priv->hw->mac->set_eee_mode(priv->ioaddr);
 241 }
 242
 243 void stmmac_disable_eee_mode(struct stmmac_priv *priv)
 244 {
 245         /* Exit and disable EEE in case of we are are in LPI state. */
 246         priv->hw->mac->reset_eee_mode(priv->ioaddr);
 247         del_timer_sync(&priv->eee_ctrl_timer);
 248         priv->tx_path_in_lpi_mode = false;
 249 }
 250
 251 /**
 252  * stmmac_eee_ctrl_timer
 253  * @arg : data hook
 254  * Description:
 255  *  If there is no data transfer and if we are not in LPI state,
 256  *  then MAC Transmitter can be moved to LPI state.
 257  */
 258 static void stmmac_eee_ctrl_timer(unsigned long arg)
 259 {
 260         struct stmmac_priv *priv = (struct stmmac_priv *)arg;
 261
 262         stmmac_enable_eee_mode(priv);
 263         mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_TIMER(eee_timer));
 264 }
 265
 266 /**
 267  * stmmac_eee_init
 268  * @priv: private device pointer
 269  * Description:
 270  *  If the EEE support has been enabled while configuring the driver,
 271  *  if the GMAC actually supports the EEE (from the HW cap reg) and the
 272  *  phy can also manage EEE, so enable the LPI state and start the timer
 273  *  to verify if the tx path can enter in LPI state.
 274  */
 275 bool stmmac_eee_init(struct stmmac_priv *priv)
 276 {
 277         bool ret = false;
 278
 279         /* MAC core supports the EEE feature. */
 280         if (priv->dma_cap.eee) {
 281                 /* Check if the PHY supports EEE */
 282                 if (phy_init_eee(priv->phydev, 1))
 283                         goto out;
 284
 285                 priv->eee_active = 1;
 286                 init_timer(&priv->eee_ctrl_timer);
 287                 priv->eee_ctrl_timer.function = stmmac_eee_ctrl_timer;
 288                 priv->eee_ctrl_timer.data = (unsigned long)priv;
 289                 priv->eee_ctrl_timer.expires = STMMAC_LPI_TIMER(eee_timer);
 290                 add_timer(&priv->eee_ctrl_timer);
 291
 292                 priv->hw->mac->set_eee_timer(priv->ioaddr,
 293                                              STMMAC_DEFAULT_LIT_LS_TIMER,
 294                                              priv->tx_lpi_timer);
 295
 296                 pr_info("stmmac: Energy-Efficient Ethernet initialized\n");
 297
 298                 ret = true;
 299         }
 300 out:
 301         return ret;
 302 }
 303
 304 static void stmmac_eee_adjust(struct stmmac_priv *priv)
 305 {
 306         /* When the EEE has been already initialised we have to
 307          * modify the PLS bit in the LPI ctrl & status reg according
 308          * to the PHY link status. For this reason.
 309          */
 310         if (priv->eee_enabled)
 311                 priv->hw->mac->set_eee_pls(priv->ioaddr, priv->phydev->link);
 312 }
 313
 314 /**
 315  * stmmac_adjust_link
 316  * @dev: net device structure
 317  * Description: it adjusts the link parameters.
 318  */
 319 static void stmmac_adjust_link(struct net_device *dev)
 320 {
 321         struct stmmac_priv *priv = netdev_priv(dev);
 322         struct phy_device *phydev = priv->phydev;
 323         unsigned long flags;
 324         int new_state = 0;
 325         unsigned int fc = priv->flow_ctrl, pause_time = priv->pause;
 326
 327         if (phydev == NULL)
 328                 return;
 329
 330         DBG(probe, DEBUG, "stmmac_adjust_link: called.  address %d link %d\n",
 331             phydev->addr, phydev->link);
 332
 333         spin_lock_irqsave(&priv->lock, flags);
 334
 335         if (phydev->link) {
 336                 u32 ctrl = readl(priv->ioaddr + MAC_CTRL_REG);
 337
 338                 /* Now we make sure that we can be in full duplex mode.
 339                  * If not, we operate in half-duplex mode. */
 340                 if (phydev->duplex != priv->oldduplex) {
 341                         new_state = 1;
 342                         if (!(phydev->duplex))
 343                                 ctrl &= ~priv->hw->link.duplex;
 344                         else
 345                                 ctrl |= priv->hw->link.duplex;
 346                         priv->oldduplex = phydev->duplex;
 347                 }
 348                 /* Flow Control operation */
 349                 if (phydev->pause)
 350                         priv->hw->mac->flow_ctrl(priv->ioaddr, phydev->duplex,
 351                                                  fc, pause_time);
 352
 353                 if (phydev->speed != priv->speed) {
 354                         new_state = 1;
 355                         switch (phydev->speed) {
 356                         case 1000:
 357                                 if (likely(priv->plat->has_gmac))
 358                                         ctrl &= ~priv->hw->link.port;
 359                                         stmmac_hw_fix_mac_speed(priv);
 360                                 break;
 361                         case 100:
 362                         case 10:
 363                                 if (priv->plat->has_gmac) {
 364                                         ctrl |= priv->hw->link.port;
 365                                         if (phydev->speed == SPEED_100) {
 366                                                 ctrl |= priv->hw->link.speed;
 367                                         } else {
 368                                                 ctrl &= ~(priv->hw->link.speed);
 369                                         }
 370                                 } else {
 371                                         ctrl &= ~priv->hw->link.port;
 372                                 }
 373                                 stmmac_hw_fix_mac_speed(priv);
 374                                 break;
 375                         default:
 376                                 if (netif_msg_link(priv))
 377                                         pr_warning("%s: Speed (%d) is not 10"
 378                                        " or 100!\n", dev->name, phydev->speed);
 379                                 break;
 380                         }
 381
 382                         priv->speed = phydev->speed;
 383                 }
 384
 385                 writel(ctrl, priv->ioaddr + MAC_CTRL_REG);
 386
 387                 if (!priv->oldlink) {
 388                         new_state = 1;
 389                         priv->oldlink = 1;
 390                 }
 391         } else if (priv->oldlink) {
 392                 new_state = 1;
 393                 priv->oldlink = 0;
 394                 priv->speed = 0;
 395                 priv->oldduplex = -1;
 396         }
 397
 398         if (new_state && netif_msg_link(priv))
 399                 phy_print_status(phydev);
 400
 401         stmmac_eee_adjust(priv);
 402
 403         spin_unlock_irqrestore(&priv->lock, flags);
 404
 405         DBG(probe, DEBUG, "stmmac_adjust_link: exiting\n");
 406 }
 407
 408 static void stmmac_check_pcs_mode(struct stmmac_priv *priv)
 409 {
 410         int interface = priv->plat->interface;
 411
 412         if (priv->dma_cap.pcs) {
 413                 if ((interface & PHY_INTERFACE_MODE_RGMII) ||
 414                     (interface & PHY_INTERFACE_MODE_RGMII_ID) ||
 415                     (interface & PHY_INTERFACE_MODE_RGMII_RXID) ||
 416                     (interface & PHY_INTERFACE_MODE_RGMII_TXID)) {
 417                         pr_debug("STMMAC: PCS RGMII support enable\n");
 418                         priv->pcs = STMMAC_PCS_RGMII;
 419                 } else if (interface & PHY_INTERFACE_MODE_SGMII) {
 420                         pr_debug("STMMAC: PCS SGMII support enable\n");
 421                         priv->pcs = STMMAC_PCS_SGMII;
 422                 }
 423         }
 424 }
 425
 426 /**
 427  * stmmac_init_phy - PHY initialization
 428  * @dev: net device structure
 429  * Description: it initializes the driver's PHY state, and attaches the PHY
 430  * to the mac driver.
 431  *  Return value:
 432  *  0 on success
 433  */
 434 static int stmmac_init_phy(struct net_device *dev)
 435 {
 436         struct stmmac_priv *priv = netdev_priv(dev);
 437         struct phy_device *phydev;
 438         char phy_id_fmt[MII_BUS_ID_SIZE + 3];
 439         char bus_id[MII_BUS_ID_SIZE];
 440         int interface = priv->plat->interface;
 441         priv->oldlink = 0;
 442         priv->speed = 0;
 443         priv->oldduplex = -1;
 444
 445         if (priv->plat->phy_bus_name)
 446                 snprintf(bus_id, MII_BUS_ID_SIZE, "%s-%x",
 447                                 priv->plat->phy_bus_name, priv->plat->bus_id);
 448         else
 449                 snprintf(bus_id, MII_BUS_ID_SIZE, "stmmac-%x",
 450                                 priv->plat->bus_id);
 451
 452         snprintf(phy_id_fmt, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id,
 453                  priv->plat->phy_addr);
 454         pr_debug("stmmac_init_phy:  trying to attach to %s\n", phy_id_fmt);
 455
 456         phydev = phy_connect(dev, phy_id_fmt, &stmmac_adjust_link, interface);
 457
 458         if (IS_ERR(phydev)) {
 459                 pr_err("%s: Could not attach to PHY\n", dev->name);
 460                 return PTR_ERR(phydev);
 461         }
 462
 463         /* Stop Advertising 1000BASE Capability if interface is not GMII */
 464         if ((interface == PHY_INTERFACE_MODE_MII) ||
 465             (interface == PHY_INTERFACE_MODE_RMII))
 466                 phydev->advertising &= ~(SUPPORTED_1000baseT_Half |
 467                                          SUPPORTED_1000baseT_Full);
 468
 469         /*
 470          * Broken HW is sometimes missing the pull-up resistor on the
 471          * MDIO line, which results in reads to non-existent devices returning
 472          * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent
 473          * device as well.
 474          * Note: phydev->phy_id is the result of reading the UID PHY registers.
 475          */
 476         if (phydev->phy_id == 0) {
 477                 phy_disconnect(phydev);
 478                 return -ENODEV;
 479         }
 480         pr_debug("stmmac_init_phy:  %s: attached to PHY (UID 0x%x)"
 481                  " Link = %d\n", dev->name, phydev->phy_id, phydev->link);
 482
 483         priv->phydev = phydev;
 484
 485         return 0;
 486 }
 487
 488 /**
 489  * stmmac_display_ring
 490  * @p: pointer to the ring.
 491  * @size: size of the ring.
 492  * Description: display the control/status and buffer descriptors.
 493  */
 494 static void stmmac_display_ring(void *head, int size, int extend_desc)
 495 {
 496         int i;
 497         struct dma_extended_desc *ep = (struct dma_extended_desc *) head;
 498         struct dma_desc *p = (struct dma_desc *) head;
 499
 500         for (i = 0; i < size; i++) {
 501                 u64 x;
 502                 if (extend_desc) {
 503                         x = *(u64 *) ep;
 504                         pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
 505                                 i, (unsigned int) virt_to_phys(ep),
 506                                 (unsigned int) x, (unsigned int) (x >> 32),
 507                                 ep->basic.des2, ep->basic.des3);
 508                         ep++;
 509                 } else {
 510                         x = *(u64 *) p;
 511                         pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x",
 512                                 i, (unsigned int) virt_to_phys(p),
 513                                 (unsigned int) x, (unsigned int) (x >> 32),
 514                                 p->des2, p->des3);
 515                         p++;
 516                 }
 517                 pr_info("\n");
 518         }
 519 }
 520
 521 static void stmmac_display_rings(struct stmmac_priv *priv)
 522 {
 523         unsigned int txsize = priv->dma_tx_size;
 524         unsigned int rxsize = priv->dma_rx_size;
 525
 526         if (priv->extend_desc) {
 527                 pr_info("Extended RX descriptor ring:\n");
 528                 stmmac_display_ring((void *) priv->dma_erx, rxsize, 1);
 529                 pr_info("Extended TX descriptor ring:\n");
 530                 stmmac_display_ring((void *) priv->dma_etx, txsize, 1);
 531         } else {
 532                 pr_info("RX descriptor ring:\n");
 533                 stmmac_display_ring((void *)priv->dma_rx, rxsize, 0);
 534                 pr_info("TX descriptor ring:\n");
 535                 stmmac_display_ring((void *)priv->dma_tx, txsize, 0);
 536         }
 537 }
 538
 539 static int stmmac_set_bfsize(int mtu, int bufsize)
 540 {
 541         int ret = bufsize;
 542
 543         if (mtu >= BUF_SIZE_4KiB)
 544                 ret = BUF_SIZE_8KiB;
 545         else if (mtu >= BUF_SIZE_2KiB)
 546                 ret = BUF_SIZE_4KiB;
 547         else if (mtu >= DMA_BUFFER_SIZE)
 548                 ret = BUF_SIZE_2KiB;
 549         else
 550                 ret = DMA_BUFFER_SIZE;
 551
 552         return ret;
 553 }
 554
 555 static void stmmac_clear_descriptors(struct stmmac_priv *priv)
 556 {
 557         int i;
 558         unsigned int txsize = priv->dma_tx_size;
 559         unsigned int rxsize = priv->dma_rx_size;
 560
 561         /* Clear the Rx/Tx descriptors */
 562         for (i = 0; i < rxsize; i++)
 563                 if (priv->extend_desc)
 564                         priv->hw->desc->init_rx_desc(&priv->dma_erx[i].basic,
 565                                                      priv->use_riwt, priv->mode,
 566                                                      (i == rxsize - 1));
 567                 else
 568                         priv->hw->desc->init_rx_desc(&priv->dma_rx[i],
 569                                                      priv->use_riwt, priv->mode,
 570                                                      (i == rxsize - 1));
 571         for (i = 0; i < txsize; i++)
 572                 if (priv->extend_desc)
 573                         priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic,
 574                                                      priv->mode,
 575                                                      (i == txsize - 1));
 576                 else
 577                         priv->hw->desc->init_tx_desc(&priv->dma_tx[i],
 578                                                      priv->mode,
 579                                                      (i == txsize - 1));
 580 }
 581
 582 static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p,
 583                                   int i)
 584 {
 585         struct sk_buff *skb;
 586
 587         skb = __netdev_alloc_skb(priv->dev, priv->dma_buf_sz + NET_IP_ALIGN,
 588                                  GFP_KERNEL);
 589         if (unlikely(skb == NULL)) {
 590                 pr_err("%s: Rx init fails; skb is NULL\n", __func__);
 591                 return 1;
 592         }
 593         skb_reserve(skb, NET_IP_ALIGN);
 594         priv->rx_skbuff[i] = skb;
 595         priv->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data,
 596                                                 priv->dma_buf_sz,
 597                                                 DMA_FROM_DEVICE);
 598
 599         p->des2 = priv->rx_skbuff_dma[i];
 600
 601         if ((priv->mode == STMMAC_RING_MODE) &&
 602             (priv->dma_buf_sz == BUF_SIZE_16KiB))
 603                 priv->hw->ring->init_desc3(p);
 604
 605         return 0;
 606 }
 607
 608 /**
 609  * init_dma_desc_rings - init the RX/TX descriptor rings
 610  * @dev: net device structure
 611  * Description:  this function initializes the DMA RX/TX descriptors
 612  * and allocates the socket buffers. It suppors the chained and ring
 613  * modes.
 614  */
 615 static void init_dma_desc_rings(struct net_device *dev)
 616 {
 617         int i;
 618         struct stmmac_priv *priv = netdev_priv(dev);
 619         unsigned int txsize = priv->dma_tx_size;
 620         unsigned int rxsize = priv->dma_rx_size;
 621         unsigned int bfsize = 0;
 622
 623         /* Set the max buffer size according to the DESC mode
 624          * and the MTU. Note that RING mode allows 16KiB bsize. */
 625         if (priv->mode == STMMAC_RING_MODE)
 626                 bfsize = priv->hw->ring->set_16kib_bfsize(dev->mtu);
 627
 628         if (bfsize < BUF_SIZE_16KiB)
 629                 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz);
 630
 631         DBG(probe, INFO, "stmmac: txsize %d, rxsize %d, bfsize %d\n",
 632             txsize, rxsize, bfsize);
 633
 634         if (priv->extend_desc) {
 635                 priv->dma_erx = dma_alloc_coherent(priv->device, rxsize *
 636                                                    sizeof(struct
 637                                                           dma_extended_desc),
 638                                                    &priv->dma_rx_phy,
 639                                                    GFP_KERNEL);
 640                 priv->dma_etx = dma_alloc_coherent(priv->device, txsize *
 641                                                    sizeof(struct
 642                                                           dma_extended_desc),
 643                                                    &priv->dma_tx_phy,
 644                                                    GFP_KERNEL);
 645                 if ((!priv->dma_erx) || (!priv->dma_etx))
 646                         return;
 647         } else {
 648                 priv->dma_rx = dma_alloc_coherent(priv->device, rxsize *
 649                                                   sizeof(struct dma_desc),
 650                                                   &priv->dma_rx_phy,
 651                                                   GFP_KERNEL);
 652                 priv->dma_tx = dma_alloc_coherent(priv->device, txsize *
 653                                                   sizeof(struct dma_desc),
 654                                                   &priv->dma_tx_phy,
 655                                                   GFP_KERNEL);
 656                 if ((!priv->dma_rx) || (!priv->dma_tx))
 657                         return;
 658         }
 659
 660         priv->rx_skbuff_dma = kmalloc_array(rxsize, sizeof(dma_addr_t),
 661                                             GFP_KERNEL);
 662         priv->rx_skbuff = kmalloc_array(rxsize, sizeof(struct sk_buff *),
 663                                         GFP_KERNEL);
 664         priv->tx_skbuff_dma = kmalloc_array(txsize, sizeof(dma_addr_t),
 665                                         GFP_KERNEL);
 666         priv->tx_skbuff = kmalloc_array(txsize, sizeof(struct sk_buff *),
 667                                         GFP_KERNEL);
 668         if (netif_msg_drv(priv))
 669                 pr_debug("(%s) dma_rx_phy=0x%08x dma_tx_phy=0x%08x\n", __func__,
 670                          (u32) priv->dma_rx_phy, (u32) priv->dma_tx_phy);
 671
 672         /* RX INITIALIZATION */
 673         DBG(probe, INFO, "stmmac: SKB addresses:\nskb\t\tskb data\tdma data\n");
 674         for (i = 0; i < rxsize; i++) {
 675                 struct dma_desc *p;
 676                 if (priv->extend_desc)
 677                         p = &((priv->dma_erx + i)->basic);
 678                 else
 679                         p = priv->dma_rx + i;
 680
 681                 if (stmmac_init_rx_buffers(priv, p, i))
 682                         break;
 683
 684                 DBG(probe, INFO, "[%p]\t[%p]\t[%x]\n", priv->rx_skbuff[i],
 685                         priv->rx_skbuff[i]->data, priv->rx_skbuff_dma[i]);
 686         }
 687         priv->cur_rx = 0;
 688         priv->dirty_rx = (unsigned int)(i - rxsize);
 689         priv->dma_buf_sz = bfsize;
 690         buf_sz = bfsize;
 691
 692         /* Setup the chained descriptor addresses */
 693         if (priv->mode == STMMAC_CHAIN_MODE) {
 694                 if (priv->extend_desc) {
 695                         priv->hw->chain->init(priv->dma_erx, priv->dma_rx_phy,
 696                                               rxsize, 1);
 697                         priv->hw->chain->init(priv->dma_etx, priv->dma_tx_phy,
 698                                               txsize, 1);
 699                 } else {
 700                         priv->hw->chain->init(priv->dma_rx, priv->dma_rx_phy,
 701                                               rxsize, 0);
 702                         priv->hw->chain->init(priv->dma_tx, priv->dma_tx_phy,
 703                                               txsize, 0);
 704                 }
 705         }
 706
 707         /* TX INITIALIZATION */
 708         for (i = 0; i < txsize; i++) {
 709                 struct dma_desc *p;
 710                 if (priv->extend_desc)
 711                         p = &((priv->dma_etx + i)->basic);
 712                 else
 713                         p = priv->dma_tx + i;
 714                 p->des2 = 0;
 715                 priv->tx_skbuff_dma[i] = 0;
 716                 priv->tx_skbuff[i] = NULL;
 717         }
 718
 719         priv->dirty_tx = 0;
 720         priv->cur_tx = 0;
 721
 722         stmmac_clear_descriptors(priv);
 723
 724         if (netif_msg_hw(priv))
 725                 stmmac_display_rings(priv);
 726 }
 727
 728 static void dma_free_rx_skbufs(struct stmmac_priv *priv)
 729 {
 730         int i;
 731
 732         for (i = 0; i < priv->dma_rx_size; i++) {
 733                 if (priv->rx_skbuff[i]) {
 734                         dma_unmap_single(priv->device, priv->rx_skbuff_dma[i],
 735                                          priv->dma_buf_sz, DMA_FROM_DEVICE);
 736                         dev_kfree_skb_any(priv->rx_skbuff[i]);
 737                 }
 738                 priv->rx_skbuff[i] = NULL;
 739         }
 740 }
 741
 742 static void dma_free_tx_skbufs(struct stmmac_priv *priv)
 743 {
 744         int i;
 745
 746         for (i = 0; i < priv->dma_tx_size; i++) {
 747                 if (priv->tx_skbuff[i] != NULL) {
 748                         struct dma_desc *p;
 749                         if (priv->extend_desc)
 750                                 p = &((priv->dma_etx + i)->basic);
 751                         else
 752                                 p = priv->dma_tx + i;
 753
 754                         if (priv->tx_skbuff_dma[i])
 755                                 dma_unmap_single(priv->device,
 756                                                  priv->tx_skbuff_dma[i],
 757                                                  priv->hw->desc->get_tx_len(p),
 758                                                  DMA_TO_DEVICE);
 759                         dev_kfree_skb_any(priv->tx_skbuff[i]);
 760                         priv->tx_skbuff[i] = NULL;
 761                         priv->tx_skbuff_dma[i] = 0;
 762                 }
 763         }
 764 }
 765
 766 static void free_dma_desc_resources(struct stmmac_priv *priv)
 767 {
 768         /* Release the DMA TX/RX socket buffers */
 769         dma_free_rx_skbufs(priv);
 770         dma_free_tx_skbufs(priv);
 771
 772         /* Free the region of consistent memory previously allocated for
 773          * the DMA */
 774         if (!priv->extend_desc) {
 775                 dma_free_coherent(priv->device,
 776                                   priv->dma_tx_size * sizeof(struct dma_desc),
 777                                   priv->dma_tx, priv->dma_tx_phy);
 778                 dma_free_coherent(priv->device,
 779                                   priv->dma_rx_size * sizeof(struct dma_desc),
 780                                   priv->dma_rx, priv->dma_rx_phy);
 781         } else {
 782                 dma_free_coherent(priv->device, priv->dma_tx_size *
 783                                   sizeof(struct dma_extended_desc),
 784                                   priv->dma_etx, priv->dma_tx_phy);
 785                 dma_free_coherent(priv->device, priv->dma_rx_size *
 786                                   sizeof(struct dma_extended_desc),
 787                                   priv->dma_erx, priv->dma_rx_phy);
 788         }
 789         kfree(priv->rx_skbuff_dma);
 790         kfree(priv->rx_skbuff);
 791         kfree(priv->tx_skbuff_dma);
 792         kfree(priv->tx_skbuff);
 793 }
 794
 795 /**
 796  *  stmmac_dma_operation_mode - HW DMA operation mode
 797  *  @priv : pointer to the private device structure.
 798  *  Description: it sets the DMA operation mode: tx/rx DMA thresholds
 799  *  or Store-And-Forward capability.
 800  */
 801 static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
 802 {
 803         if (likely(priv->plat->force_sf_dma_mode ||
 804                 ((priv->plat->tx_coe) && (!priv->no_csum_insertion)))) {
 805                 /*
 806                  * In case of GMAC, SF mode can be enabled
 807                  * to perform the TX COE in HW. This depends on:
 808                  * 1) TX COE if actually supported
 809                  * 2) There is no bugged Jumbo frame support
 810                  *    that needs to not insert csum in the TDES.
 811                  */
 812                 priv->hw->dma->dma_mode(priv->ioaddr,
 813                                         SF_DMA_MODE, SF_DMA_MODE);
 814                 tc = SF_DMA_MODE;
 815         } else
 816                 priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE);
 817 }
 818
 819 /**
 820  * stmmac_tx_clean:
 821  * @priv: private data pointer
 822  * Description: it reclaims resources after transmission completes.
 823  */
 824 static void stmmac_tx_clean(struct stmmac_priv *priv)
 825 {
 826         unsigned int txsize = priv->dma_tx_size;
 827
 828         spin_lock(&priv->tx_lock);
 829
 830         priv->xstats.tx_clean++;
 831
 832         while (priv->dirty_tx != priv->cur_tx) {
 833                 int last;
 834                 unsigned int entry = priv->dirty_tx % txsize;
 835                 struct sk_buff *skb = priv->tx_skbuff[entry];
 836                 struct dma_desc *p;
 837
 838                 if (priv->extend_desc)
 839                         p = (struct dma_desc *) (priv->dma_etx + entry);
 840                 else
 841                         p = priv->dma_tx + entry;
 842
 843                 /* Check if the descriptor is owned by the DMA. */
 844                 if (priv->hw->desc->get_tx_owner(p))
 845                         break;
 846
 847                 /* Verify tx error by looking at the last segment. */
 848                 last = priv->hw->desc->get_tx_ls(p);
 849                 if (likely(last)) {
 850                         int tx_error =
 851                                 priv->hw->desc->tx_status(&priv->dev->stats,
 852                                                           &priv->xstats, p,
 853                                                           priv->ioaddr);
 854                         if (likely(tx_error == 0)) {
 855                                 priv->dev->stats.tx_packets++;
 856                                 priv->xstats.tx_pkt_n++;
 857                         } else
 858                                 priv->dev->stats.tx_errors++;
 859                 }
 860                 TX_DBG("%s: curr %d, dirty %d\n", __func__,
 861                         priv->cur_tx, priv->dirty_tx);
 862
 863                 if (likely(priv->tx_skbuff_dma[entry])) {
 864                         dma_unmap_single(priv->device,
 865                                          priv->tx_skbuff_dma[entry],
 866                                          priv->hw->desc->get_tx_len(p),
 867                                          DMA_TO_DEVICE);
 868                         priv->tx_skbuff_dma[entry] = 0;
 869                 }
 870                 if (priv->mode == STMMAC_RING_MODE)
 871                         priv->hw->ring->clean_desc3(p);
 872
 873                 if (likely(skb != NULL)) {
 874                         dev_kfree_skb(skb);
 875                         priv->tx_skbuff[entry] = NULL;
 876                 }
 877
 878                 priv->hw->desc->release_tx_desc(p, priv->mode);
 879
 880                 priv->dirty_tx++;
 881         }
 882         if (unlikely(netif_queue_stopped(priv->dev) &&
 883                      stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv))) {
 884                 netif_tx_lock(priv->dev);
 885                 if (netif_queue_stopped(priv->dev) &&
 886                      stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv)) {
 887                         TX_DBG("%s: restart transmit\n", __func__);
 888                         netif_wake_queue(priv->dev);
 889                 }
 890                 netif_tx_unlock(priv->dev);
 891         }
 892
 893         if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) {
 894                 stmmac_enable_eee_mode(priv);
 895                 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_TIMER(eee_timer));
 896         }
 897         spin_unlock(&priv->tx_lock);
 898 }
 899
 900 static inline void stmmac_enable_dma_irq(struct stmmac_priv *priv)
 901 {
 902         priv->hw->dma->enable_dma_irq(priv->ioaddr);
 903 }
 904
 905 static inline void stmmac_disable_dma_irq(struct stmmac_priv *priv)
 906 {
 907         priv->hw->dma->disable_dma_irq(priv->ioaddr);
 908 }
 909
 910
 911 /**
 912  * stmmac_tx_err:
 913  * @priv: pointer to the private device structure
 914  * Description: it cleans the descriptors and restarts the transmission
 915  * in case of errors.
 916  */
 917 static void stmmac_tx_err(struct stmmac_priv *priv)
 918 {
 919         int i;
 920         int txsize = priv->dma_tx_size;
 921         netif_stop_queue(priv->dev);
 922
 923         priv->hw->dma->stop_tx(priv->ioaddr);
 924         dma_free_tx_skbufs(priv);
 925         for (i = 0; i < txsize; i++)
 926                 if (priv->extend_desc)
 927                         priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic,
 928                                                      priv->mode,
 929                                                      (i == txsize - 1));
 930                 else
 931                         priv->hw->desc->init_tx_desc(&priv->dma_tx[i],
 932                                                      priv->mode,
 933                                                      (i == txsize - 1));
 934         priv->dirty_tx = 0;
 935         priv->cur_tx = 0;
 936         priv->hw->dma->start_tx(priv->ioaddr);
 937
 938         priv->dev->stats.tx_errors++;
 939         netif_wake_queue(priv->dev);
 940 }
 941
 942 static void stmmac_dma_interrupt(struct stmmac_priv *priv)
 943 {
 944         int status;
 945
 946         status = priv->hw->dma->dma_interrupt(priv->ioaddr, &priv->xstats);
 947         if (likely((status & handle_rx)) || (status & handle_tx)) {
 948                 if (likely(napi_schedule_prep(&priv->napi))) {
 949                         stmmac_disable_dma_irq(priv);
 950                         __napi_schedule(&priv->napi);
 951                 }
 952         }
 953         if (unlikely(status & tx_hard_error_bump_tc)) {
 954                 /* Try to bump up the dma threshold on this failure */
 955                 if (unlikely(tc != SF_DMA_MODE) && (tc <= 256)) {
 956                         tc += 64;
 957                         priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE);
 958                         priv->xstats.threshold = tc;
 959                 }
 960         } else if (unlikely(status == tx_hard_error))
 961                 stmmac_tx_err(priv);
 962 }
 963
 964 static void stmmac_mmc_setup(struct stmmac_priv *priv)
 965 {
 966         unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET |
 967                             MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET;
 968
 969         /* Mask MMC irq, counters are managed in SW and registers
 970          * are cleared on each READ eventually. */
 971         dwmac_mmc_intr_all_mask(priv->ioaddr);
 972
 973         if (priv->dma_cap.rmon) {
 974                 dwmac_mmc_ctrl(priv->ioaddr, mode);
 975                 memset(&priv->mmc, 0, sizeof(struct stmmac_counters));
 976         } else
 977                 pr_info(" No MAC Management Counters available\n");
 978 }
 979
 980 static u32 stmmac_get_synopsys_id(struct stmmac_priv *priv)
 981 {
 982         u32 hwid = priv->hw->synopsys_uid;
 983
 984         /* Only check valid Synopsys Id because old MAC chips
 985          * have no HW registers where get the ID */
 986         if (likely(hwid)) {
 987                 u32 uid = ((hwid & 0x0000ff00) >> 8);
 988                 u32 synid = (hwid & 0x000000ff);
 989
 990                 pr_info("stmmac - user ID: 0x%x, Synopsys ID: 0x%x\n",
 991                         uid, synid);
 992
 993                 return synid;
 994         }
 995         return 0;
 996 }
 997
 998 /**
 999  * stmmac_selec_desc_mode
1000  * @priv : private structure
1001  * Description: select the Enhanced/Alternate or Normal descriptors
1002  */
1003 static void stmmac_selec_desc_mode(struct stmmac_priv *priv)
1004 {
1005         if (priv->plat->enh_desc) {
1006                 pr_info(" Enhanced/Alternate descriptors\n");
1007
1008                 /* GMAC older than 3.50 has no extended descriptors */
1009                 if (priv->synopsys_id >= DWMAC_CORE_3_50) {
1010                         pr_info("\tEnabled extended descriptors\n");
1011                         priv->extend_desc = 1;
1012                 } else
1013                         pr_warn("Extended descriptors not supported\n");
1014
1015                 priv->hw->desc = &enh_desc_ops;
1016         } else {
1017                 pr_info(" Normal descriptors\n");
1018                 priv->hw->desc = &ndesc_ops;
1019         }
1020 }
1021
1022 /**
1023  * stmmac_get_hw_features
1024  * @priv : private device pointer
1025  * Description:
1026  *  new GMAC chip generations have a new register to indicate the
1027  *  presence of the optional feature/functions.
1028  *  This can be also used to override the value passed through the
1029  *  platform and necessary for old MAC10/100 and GMAC chips.
1030  */
1031 static int stmmac_get_hw_features(struct stmmac_priv *priv)
1032 {
1033         u32 hw_cap = 0;
1034
1035         if (priv->hw->dma->get_hw_feature) {
1036                 hw_cap = priv->hw->dma->get_hw_feature(priv->ioaddr);
1037
1038                 priv->dma_cap.mbps_10_100 = (hw_cap & DMA_HW_FEAT_MIISEL);
1039                 priv->dma_cap.mbps_1000 = (hw_cap & DMA_HW_FEAT_GMIISEL) >> 1;
1040                 priv->dma_cap.half_duplex = (hw_cap & DMA_HW_FEAT_HDSEL) >> 2;
1041                 priv->dma_cap.hash_filter = (hw_cap & DMA_HW_FEAT_HASHSEL) >> 4;
1042                 priv->dma_cap.multi_addr =
1043                         (hw_cap & DMA_HW_FEAT_ADDMACADRSEL) >> 5;
1044                 priv->dma_cap.pcs = (hw_cap & DMA_HW_FEAT_PCSSEL) >> 6;
1045                 priv->dma_cap.sma_mdio = (hw_cap & DMA_HW_FEAT_SMASEL) >> 8;
1046                 priv->dma_cap.pmt_remote_wake_up =
1047                         (hw_cap & DMA_HW_FEAT_RWKSEL) >> 9;
1048                 priv->dma_cap.pmt_magic_frame =
1049                         (hw_cap & DMA_HW_FEAT_MGKSEL) >> 10;
1050                 /* MMC */
1051                 priv->dma_cap.rmon = (hw_cap & DMA_HW_FEAT_MMCSEL) >> 11;
1052                 /* IEEE 1588-2002*/
1053                 priv->dma_cap.time_stamp =
1054                         (hw_cap & DMA_HW_FEAT_TSVER1SEL) >> 12;
1055                 /* IEEE 1588-2008*/
1056                 priv->dma_cap.atime_stamp =
1057                         (hw_cap & DMA_HW_FEAT_TSVER2SEL) >> 13;
1058                 /* 802.3az - Energy-Efficient Ethernet (EEE) */
1059                 priv->dma_cap.eee = (hw_cap & DMA_HW_FEAT_EEESEL) >> 14;
1060                 priv->dma_cap.av = (hw_cap & DMA_HW_FEAT_AVSEL) >> 15;
1061                 /* TX and RX csum */
1062                 priv->dma_cap.tx_coe = (hw_cap & DMA_HW_FEAT_TXCOESEL) >> 16;
1063                 priv->dma_cap.rx_coe_type1 =
1064                         (hw_cap & DMA_HW_FEAT_RXTYP1COE) >> 17;
1065                 priv->dma_cap.rx_coe_type2 =
1066                         (hw_cap & DMA_HW_FEAT_RXTYP2COE) >> 18;
1067                 priv->dma_cap.rxfifo_over_2048 =
1068                         (hw_cap & DMA_HW_FEAT_RXFIFOSIZE) >> 19;
1069                 /* TX and RX number of channels */
1070                 priv->dma_cap.number_rx_channel =
1071                         (hw_cap & DMA_HW_FEAT_RXCHCNT) >> 20;
1072                 priv->dma_cap.number_tx_channel =
1073                         (hw_cap & DMA_HW_FEAT_TXCHCNT) >> 22;
1074                 /* Alternate (enhanced) DESC mode*/
1075                 priv->dma_cap.enh_desc =
1076                         (hw_cap & DMA_HW_FEAT_ENHDESSEL) >> 24;
1077         }
1078
1079         return hw_cap;
1080 }
1081
1082 static void stmmac_check_ether_addr(struct stmmac_priv *priv)
1083 {
1084         /* verify if the MAC address is valid, in case of failures it
1085          * generates a random MAC address */
1086         if (!is_valid_ether_addr(priv->dev->dev_addr)) {
1087                 priv->hw->mac->get_umac_addr((void __iomem *)
1088                                              priv->dev->base_addr,
1089                                              priv->dev->dev_addr, 0);
1090                 if  (!is_valid_ether_addr(priv->dev->dev_addr))
1091                         eth_hw_addr_random(priv->dev);
1092         }
1093         pr_warning("%s: device MAC address %pM\n", priv->dev->name,
1094                                                    priv->dev->dev_addr);
1095 }
1096
1097 static int stmmac_init_dma_engine(struct stmmac_priv *priv)
1098 {
1099         int pbl = DEFAULT_DMA_PBL, fixed_burst = 0, burst_len = 0;
1100         int mixed_burst = 0;
1101         int atds = 0;
1102
1103         /* Some DMA parameters can be passed from the platform;
1104          * in case of these are not passed we keep a default
1105          * (good for all the chips) and init the DMA! */
1106         if (priv->plat->dma_cfg) {
1107                 pbl = priv->plat->dma_cfg->pbl;
1108                 fixed_burst = priv->plat->dma_cfg->fixed_burst;
1109                 mixed_burst = priv->plat->dma_cfg->mixed_burst;
1110                 burst_len = priv->plat->dma_cfg->burst_len;
1111         }
1112
1113         if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE))
1114                 atds = 1;
1115
1116         return priv->hw->dma->init(priv->ioaddr, pbl, fixed_burst, mixed_burst,
1117                                    burst_len, priv->dma_tx_phy,
1118                                    priv->dma_rx_phy, atds);
1119 }
1120
1121 /**
1122  * stmmac_tx_timer:
1123  * @data: data pointer
1124  * Description:
1125  * This is the timer handler to directly invoke the stmmac_tx_clean.
1126  */
1127 static void stmmac_tx_timer(unsigned long data)
1128 {
1129         struct stmmac_priv *priv = (struct stmmac_priv *)data;
1130
1131         stmmac_tx_clean(priv);
1132 }
1133
1134 /**
1135  * stmmac_tx_timer:
1136  * @priv: private data structure
1137  * Description:
1138  * This inits the transmit coalesce parameters: i.e. timer rate,
1139  * timer handler and default threshold used for enabling the
1140  * interrupt on completion bit.
1141  */
1142 static void stmmac_init_tx_coalesce(struct stmmac_priv *priv)
1143 {
1144         priv->tx_coal_frames = STMMAC_TX_FRAMES;
1145         priv->tx_coal_timer = STMMAC_COAL_TX_TIMER;
1146         init_timer(&priv->txtimer);
1147         priv->txtimer.expires = STMMAC_COAL_TIMER(priv->tx_coal_timer);
1148         priv->txtimer.data = (unsigned long)priv;
1149         priv->txtimer.function = stmmac_tx_timer;
1150         add_timer(&priv->txtimer);
1151 }
1152
1153 /**
1154  *  stmmac_open - open entry point of the driver
1155  *  @dev : pointer to the device structure.
1156  *  Description:
1157  *  This function is the open entry point of the driver.
1158  *  Return value:
1159  *  0 on success and an appropriate (-)ve integer as defined in errno.h
1160  *  file on failure.
1161  */
1162 static int stmmac_open(struct net_device *dev)
1163 {
1164         struct stmmac_priv *priv = netdev_priv(dev);
1165         int ret;
1166
1167         clk_prepare_enable(priv->stmmac_clk);
1168
1169         stmmac_check_ether_addr(priv);
1170
1171         if (!priv->pcs) {
1172                 ret = stmmac_init_phy(dev);
1173                 if (ret) {
1174                         pr_err("%s: Cannot attach to PHY (error: %d)\n",
1175                                __func__, ret);
1176                         goto open_error;
1177                 }
1178         }
1179
1180         /* Create and initialize the TX/RX descriptors chains. */
1181         priv->dma_tx_size = STMMAC_ALIGN(dma_txsize);
1182         priv->dma_rx_size = STMMAC_ALIGN(dma_rxsize);
1183         priv->dma_buf_sz = STMMAC_ALIGN(buf_sz);
1184         init_dma_desc_rings(dev);
1185
1186         /* DMA initialization and SW reset */
1187         ret = stmmac_init_dma_engine(priv);
1188         if (ret < 0) {
1189                 pr_err("%s: DMA initialization failed\n", __func__);
1190                 goto open_error;
1191         }
1192
1193         /* Copy the MAC addr into the HW  */
1194         priv->hw->mac->set_umac_addr(priv->ioaddr, dev->dev_addr, 0);
1195
1196         /* If required, perform hw setup of the bus. */
1197         if (priv->plat->bus_setup)
1198                 priv->plat->bus_setup(priv->ioaddr);
1199
1200         /* Initialize the MAC Core */
1201         priv->hw->mac->core_init(priv->ioaddr);
1202
1203         /* Request the IRQ lines */
1204         ret = request_irq(dev->irq, stmmac_interrupt,
1205                          IRQF_SHARED, dev->name, dev);
1206         if (unlikely(ret < 0)) {
1207                 pr_err("%s: ERROR: allocating the IRQ %d (error: %d)\n",
1208                        __func__, dev->irq, ret);
1209                 goto open_error;
1210         }
1211
1212         /* Request the Wake IRQ in case of another line is used for WoL */
1213         if (priv->wol_irq != dev->irq) {
1214                 ret = request_irq(priv->wol_irq, stmmac_interrupt,
1215                                   IRQF_SHARED, dev->name, dev);
1216                 if (unlikely(ret < 0)) {
1217                         pr_err("%s: ERROR: allocating the ext WoL IRQ %d "
1218                                "(error: %d)\n", __func__, priv->wol_irq, ret);
1219                         goto open_error_wolirq;
1220                 }
1221         }
1222
1223         /* Request the IRQ lines */
1224         if (priv->lpi_irq != -ENXIO) {
1225                 ret = request_irq(priv->lpi_irq, stmmac_interrupt, IRQF_SHARED,
1226                                   dev->name, dev);
1227                 if (unlikely(ret < 0)) {
1228                         pr_err("%s: ERROR: allocating the LPI IRQ %d (%d)\n",
1229                                __func__, priv->lpi_irq, ret);
1230                         goto open_error_lpiirq;
1231                 }
1232         }
1233
1234         /* Enable the MAC Rx/Tx */
1235         stmmac_set_mac(priv->ioaddr, true);
1236
1237         /* Set the HW DMA mode and the COE */
1238         stmmac_dma_operation_mode(priv);
1239
1240         /* Extra statistics */
1241         memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats));
1242         priv->xstats.threshold = tc;
1243
1244         stmmac_mmc_setup(priv);
1245
1246 #ifdef CONFIG_STMMAC_DEBUG_FS
1247         ret = stmmac_init_fs(dev);
1248         if (ret < 0)
1249                 pr_warning("%s: failed debugFS registration\n", __func__);
1250 #endif
1251         /* Start the ball rolling... */
1252         DBG(probe, DEBUG, "%s: DMA RX/TX processes started...\n", dev->name);
1253         priv->hw->dma->start_tx(priv->ioaddr);
1254         priv->hw->dma->start_rx(priv->ioaddr);
1255
1256         /* Dump DMA/MAC registers */
1257         if (netif_msg_hw(priv)) {
1258                 priv->hw->mac->dump_regs(priv->ioaddr);
1259                 priv->hw->dma->dump_regs(priv->ioaddr);
1260         }
1261
1262         if (priv->phydev)
1263                 phy_start(priv->phydev);
1264
1265         priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS_TIMER;
1266
1267         /* Using PCS we cannot dial with the phy registers at this stage
1268          * so we do not support extra feature like EEE.
1269          */
1270         if (!priv->pcs)
1271                 priv->eee_enabled = stmmac_eee_init(priv);
1272
1273         stmmac_init_tx_coalesce(priv);
1274
1275         if ((priv->use_riwt) && (priv->hw->dma->rx_watchdog)) {
1276                 priv->rx_riwt = MAX_DMA_RIWT;
1277                 priv->hw->dma->rx_watchdog(priv->ioaddr, MAX_DMA_RIWT);
1278         }
1279
1280         if (priv->pcs && priv->hw->mac->ctrl_ane)
1281                 priv->hw->mac->ctrl_ane(priv->ioaddr, 0);
1282
1283         napi_enable(&priv->napi);
1284         netif_start_queue(dev);
1285
1286         return 0;
1287
1288 open_error_lpiirq:
1289         if (priv->wol_irq != dev->irq)
1290                 free_irq(priv->wol_irq, dev);
1291
1292 open_error_wolirq:
1293         free_irq(dev->irq, dev);
1294
1295 open_error:
1296         if (priv->phydev)
1297                 phy_disconnect(priv->phydev);
1298
1299         clk_disable_unprepare(priv->stmmac_clk);
1300
1301         return ret;
1302 }
1303
1304 /**
1305  *  stmmac_release - close entry point of the driver
1306  *  @dev : device pointer.
1307  *  Description:
1308  *  This is the stop entry point of the driver.
1309  */
1310 static int stmmac_release(struct net_device *dev)
1311 {
1312         struct stmmac_priv *priv = netdev_priv(dev);
1313
1314         if (priv->eee_enabled)
1315                 del_timer_sync(&priv->eee_ctrl_timer);
1316
1317         /* Stop and disconnect the PHY */
1318         if (priv->phydev) {
1319                 phy_stop(priv->phydev);
1320                 phy_disconnect(priv->phydev);
1321                 priv->phydev = NULL;
1322         }
1323
1324         netif_stop_queue(dev);
1325
1326         napi_disable(&priv->napi);
1327
1328         del_timer_sync(&priv->txtimer);
1329
1330         /* Free the IRQ lines */
1331         free_irq(dev->irq, dev);
1332         if (priv->wol_irq != dev->irq)
1333                 free_irq(priv->wol_irq, dev);
1334         if (priv->lpi_irq != -ENXIO)
1335                 free_irq(priv->lpi_irq, dev);
1336
1337         /* Stop TX/RX DMA and clear the descriptors */
1338         priv->hw->dma->stop_tx(priv->ioaddr);
1339         priv->hw->dma->stop_rx(priv->ioaddr);
1340
1341         /* Release and free the Rx/Tx resources */
1342         free_dma_desc_resources(priv);
1343
1344         /* Disable the MAC Rx/Tx */
1345         stmmac_set_mac(priv->ioaddr, false);
1346
1347         netif_carrier_off(dev);
1348
1349 #ifdef CONFIG_STMMAC_DEBUG_FS
1350         stmmac_exit_fs();
1351 #endif
1352         clk_disable_unprepare(priv->stmmac_clk);
1353
1354         return 0;
1355 }
1356
1357 /**
1358  *  stmmac_xmit:
1359  *  @skb : the socket buffer
1360  *  @dev : device pointer
1361  *  Description : Tx entry point of the driver.
1362  */
1363 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
1364 {
1365         struct stmmac_priv *priv = netdev_priv(dev);
1366         unsigned int txsize = priv->dma_tx_size;
1367         unsigned int entry;
1368         int i, csum_insertion = 0, is_jumbo = 0;
1369         int nfrags = skb_shinfo(skb)->nr_frags;
1370         struct dma_desc *desc, *first;
1371         unsigned int nopaged_len = skb_headlen(skb);
1372
1373         if (unlikely(stmmac_tx_avail(priv) < nfrags + 1)) {
1374                 if (!netif_queue_stopped(dev)) {
1375                         netif_stop_queue(dev);
1376                         /* This is a hard error, log it. */
1377                         pr_err("%s: BUG! Tx Ring full when queue awake\n",
1378                                 __func__);
1379                 }
1380                 return NETDEV_TX_BUSY;
1381         }
1382
1383         spin_lock(&priv->tx_lock);
1384
1385         if (priv->tx_path_in_lpi_mode)
1386                 stmmac_disable_eee_mode(priv);
1387
1388         entry = priv->cur_tx % txsize;
1389
1390 #ifdef STMMAC_XMIT_DEBUG
1391         if ((skb->len > ETH_FRAME_LEN) || nfrags)
1392                 pr_debug("stmmac xmit: [entry %d]\n"
1393                          "\tskb addr %p - len: %d - nopaged_len: %d\n"
1394                          "\tn_frags: %d - ip_summed: %d - %s gso\n"
1395                          "\ttx_count_frames %d\n", entry,
1396                          skb, skb->len, nopaged_len, nfrags, skb->ip_summed,
1397                          !skb_is_gso(skb) ? "isn't" : "is",
1398                          priv->tx_count_frames);
1399 #endif
1400
1401         csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL);
1402
1403         if (priv->extend_desc)
1404                 desc = (struct dma_desc *) (priv->dma_etx + entry);
1405         else
1406                 desc = priv->dma_tx + entry;
1407
1408         first = desc;
1409
1410 #ifdef STMMAC_XMIT_DEBUG
1411         if ((nfrags > 0) || (skb->len > ETH_FRAME_LEN))
1412                 pr_debug("\tskb len: %d, nopaged_len: %d,\n"
1413                          "\t\tn_frags: %d, ip_summed: %d\n",
1414                          skb->len, nopaged_len, nfrags, skb->ip_summed);
1415 #endif
1416         priv->tx_skbuff[entry] = skb;
1417
1418         /* To program the descriptors according to the size of the frame */
1419         if (priv->mode == STMMAC_RING_MODE) {
1420                 is_jumbo = priv->hw->ring->is_jumbo_frm(skb->len,
1421                                                         priv->plat->enh_desc);
1422                 if (unlikely(is_jumbo))
1423                         entry = priv->hw->ring->jumbo_frm(priv, skb,
1424                                                           csum_insertion);
1425         } else {
1426                 is_jumbo = priv->hw->chain->is_jumbo_frm(skb->len,
1427                                                         priv->plat->enh_desc);
1428                 if (unlikely(is_jumbo))
1429                         entry = priv->hw->chain->jumbo_frm(priv, skb,
1430                                                            csum_insertion);
1431         }
1432         if (likely(!is_jumbo)) {
1433                 desc->des2 = dma_map_single(priv->device, skb->data,
1434                                         nopaged_len, DMA_TO_DEVICE);
1435                 priv->tx_skbuff_dma[entry] = desc->des2;
1436                 priv->hw->desc->prepare_tx_desc(desc, 1, nopaged_len,
1437                                                 csum_insertion, priv->mode);
1438         } else
1439                 desc = first;
1440
1441         for (i = 0; i < nfrags; i++) {
1442                 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1443                 int len = skb_frag_size(frag);
1444
1445                 entry = (++priv->cur_tx) % txsize;
1446                 if (priv->extend_desc)
1447                         desc = (struct dma_desc *) (priv->dma_etx + entry);
1448                 else
1449                         desc = priv->dma_tx + entry;
1450
1451                 TX_DBG("\t[entry %d] segment len: %d\n", entry, len);
1452                 desc->des2 = skb_frag_dma_map(priv->device, frag, 0, len,
1453                                               DMA_TO_DEVICE);
1454                 priv->tx_skbuff_dma[entry] = desc->des2;
1455                 priv->tx_skbuff[entry] = NULL;
1456                 priv->hw->desc->prepare_tx_desc(desc, 0, len, csum_insertion,
1457                                                 priv->mode);
1458                 wmb();
1459                 priv->hw->desc->set_tx_owner(desc);
1460                 wmb();
1461         }
1462
1463         /* Finalize the latest segment. */
1464         priv->hw->desc->close_tx_desc(desc);
1465
1466         wmb();
1467         /* According to the coalesce parameter the IC bit for the latest
1468          * segment could be reset and the timer re-started to invoke the
1469          * stmmac_tx function. This approach takes care about the fragments.
1470          */
1471         priv->tx_count_frames += nfrags + 1;
1472         if (priv->tx_coal_frames > priv->tx_count_frames) {
1473                 priv->hw->desc->clear_tx_ic(desc);
1474                 priv->xstats.tx_reset_ic_bit++;
1475                 TX_DBG("\t[entry %d]: tx_count_frames %d\n", entry,
1476                        priv->tx_count_frames);
1477                 mod_timer(&priv->txtimer,
1478                           STMMAC_COAL_TIMER(priv->tx_coal_timer));
1479         } else
1480                 priv->tx_count_frames = 0;
1481
1482         /* To avoid raise condition */
1483         priv->hw->desc->set_tx_owner(first);
1484         wmb();
1485
1486         priv->cur_tx++;
1487
1488 #ifdef STMMAC_XMIT_DEBUG
1489         if (netif_msg_pktdata(priv)) {
1490                 pr_info("stmmac xmit: current=%d, dirty=%d, entry=%d, "
1491                        "first=%p, nfrags=%d\n",
1492                        (priv->cur_tx % txsize), (priv->dirty_tx % txsize),
1493                        entry, first, nfrags);
1494                 if (priv->extend_desc)
1495                         stmmac_display_ring((void *)priv->dma_etx, txsize, 1);
1496                 else
1497                         stmmac_display_ring((void *)priv->dma_tx, txsize, 0);
1498
1499                 pr_info(">>> frame to be transmitted: ");
1500                 print_pkt(skb->data, skb->len);
1501         }
1502 #endif
1503         if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) {
1504                 TX_DBG("%s: stop transmitted packets\n", __func__);
1505                 netif_stop_queue(dev);
1506         }
1507
1508         dev->stats.tx_bytes += skb->len;
1509
1510         skb_tx_timestamp(skb);
1511
1512         priv->hw->dma->enable_dma_transmission(priv->ioaddr);
1513
1514         spin_unlock(&priv->tx_lock);
1515
1516         return NETDEV_TX_OK;
1517 }
1518
1519 static inline void stmmac_rx_refill(struct stmmac_priv *priv)
1520 {
1521         unsigned int rxsize = priv->dma_rx_size;
1522         int bfsize = priv->dma_buf_sz;
1523
1524         for (; priv->cur_rx - priv->dirty_rx > 0; priv->dirty_rx++) {
1525                 unsigned int entry = priv->dirty_rx % rxsize;
1526                 struct dma_desc *p;
1527
1528                 if (priv->extend_desc)
1529                         p = (struct dma_desc *) (priv->dma_erx + entry);
1530                 else
1531                         p = priv->dma_rx + entry;
1532
1533                 if (likely(priv->rx_skbuff[entry] == NULL)) {
1534                         struct sk_buff *skb;
1535
1536                         skb = netdev_alloc_skb_ip_align(priv->dev, bfsize);
1537
1538                         if (unlikely(skb == NULL))
1539                                 break;
1540
1541                         priv->rx_skbuff[entry] = skb;
1542                         priv->rx_skbuff_dma[entry] =
1543                             dma_map_single(priv->device, skb->data, bfsize,
1544                                            DMA_FROM_DEVICE);
1545
1546                         p->des2 = priv->rx_skbuff_dma[entry];
1547
1548                         if (unlikely((priv->mode == STMMAC_RING_MODE) &&
1549                                      (priv->plat->has_gmac)))
1550                                 priv->hw->ring->refill_desc3(bfsize, p);
1551
1552                         RX_DBG(KERN_INFO "\trefill entry #%d\n", entry);
1553                 }
1554                 wmb();
1555                 priv->hw->desc->set_rx_owner(p);
1556                 wmb();
1557         }
1558 }
1559
1560 static int stmmac_rx(struct stmmac_priv *priv, int limit)
1561 {
1562         unsigned int rxsize = priv->dma_rx_size;
1563         unsigned int entry = priv->cur_rx % rxsize;
1564         unsigned int next_entry;
1565         unsigned int count = 0;
1566
1567 #ifdef STMMAC_RX_DEBUG
1568         if (netif_msg_hw(priv)) {
1569                 pr_debug(">>> stmmac_rx: descriptor ring:\n");
1570                 if (priv->extend_desc)
1571                         stmmac_display_ring((void *) priv->dma_erx, rxsize, 1);
1572                 else
1573                         stmmac_display_ring((void *)priv->dma_rx, rxsize, 0);
1574         }
1575 #endif
1576         while (count < limit) {
1577                 int status;
1578                 struct dma_desc *p, *p_next;
1579
1580                 if (priv->extend_desc)
1581                         p = (struct dma_desc *) (priv->dma_erx + entry);
1582                 else
1583                         p = priv->dma_rx + entry ;
1584
1585                 if (priv->hw->desc->get_rx_owner(p))
1586                         break;
1587
1588                 count++;
1589
1590                 next_entry = (++priv->cur_rx) % rxsize;
1591                 if (priv->extend_desc)
1592                         p_next = (struct dma_desc *) (priv->dma_erx +
1593                                                       next_entry);
1594                 else
1595                         p_next = priv->dma_rx + next_entry;
1596
1597                 prefetch(p_next);
1598
1599                 /* read the status of the incoming frame */
1600                 status = priv->hw->desc->rx_status(&priv->dev->stats,
1601                                                    &priv->xstats, p);
1602                 if ((priv->extend_desc) && (priv->hw->desc->rx_extended_status))
1603                         priv->hw->desc->rx_extended_status(&priv->dev->stats,
1604                                                            &priv->xstats,
1605                                                            priv->dma_erx +
1606                                                            entry);
1607                 if (unlikely(status == discard_frame))
1608                         priv->dev->stats.rx_errors++;
1609                 else {
1610                         struct sk_buff *skb;
1611                         int frame_len;
1612
1613                         frame_len = priv->hw->desc->get_rx_frame_len(p,
1614                                         priv->plat->rx_coe);
1615                         /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
1616                          * Type frames (LLC/LLC-SNAP) */
1617                         if (unlikely(status != llc_snap))
1618                                 frame_len -= ETH_FCS_LEN;
1619 #ifdef STMMAC_RX_DEBUG
1620                         if (frame_len > ETH_FRAME_LEN)
1621                                 pr_debug("\tRX frame size %d, COE status: %d\n",
1622                                         frame_len, status);
1623
1624                         if (netif_msg_hw(priv))
1625                                 pr_debug("\tdesc: %p [entry %d] buff=0x%x\n",
1626                                         p, entry, p->des2);
1627 #endif
1628                         skb = priv->rx_skbuff[entry];
1629                         if (unlikely(!skb)) {
1630                                 pr_err("%s: Inconsistent Rx descriptor chain\n",
1631                                         priv->dev->name);
1632                                 priv->dev->stats.rx_dropped++;
1633                                 break;
1634                         }
1635                         prefetch(skb->data - NET_IP_ALIGN);
1636                         priv->rx_skbuff[entry] = NULL;
1637
1638                         skb_put(skb, frame_len);
1639                         dma_unmap_single(priv->device,
1640                                          priv->rx_skbuff_dma[entry],
1641                                          priv->dma_buf_sz, DMA_FROM_DEVICE);
1642 #ifdef STMMAC_RX_DEBUG
1643                         if (netif_msg_pktdata(priv)) {
1644                                 pr_info(" frame received (%dbytes)", frame_len);
1645                                 print_pkt(skb->data, frame_len);
1646                         }
1647 #endif
1648                         skb->protocol = eth_type_trans(skb, priv->dev);
1649
1650                         if (unlikely(!priv->plat->rx_coe))
1651                                 skb_checksum_none_assert(skb);
1652                         else
1653                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1654
1655                         napi_gro_receive(&priv->napi, skb);
1656
1657                         priv->dev->stats.rx_packets++;
1658                         priv->dev->stats.rx_bytes += frame_len;
1659                 }
1660                 entry = next_entry;
1661         }
1662
1663         stmmac_rx_refill(priv);
1664
1665         priv->xstats.rx_pkt_n += count;
1666
1667         return count;
1668 }
1669
1670 /**
1671  *  stmmac_poll - stmmac poll method (NAPI)
1672  *  @napi : pointer to the napi structure.
1673  *  @budget : maximum number of packets that the current CPU can receive from
1674  *            all interfaces.
1675  *  Description :
1676  *  To look at the incoming frames and clear the tx resources.
1677  */
1678 static int stmmac_poll(struct napi_struct *napi, int budget)
1679 {
1680         struct stmmac_priv *priv = container_of(napi, struct stmmac_priv, napi);
1681         int work_done = 0;
1682
1683         priv->xstats.napi_poll++;
1684         stmmac_tx_clean(priv);
1685
1686         work_done = stmmac_rx(priv, budget);
1687         if (work_done < budget) {
1688                 napi_complete(napi);
1689                 stmmac_enable_dma_irq(priv);
1690         }
1691         return work_done;
1692 }
1693
1694 /**
1695  *  stmmac_tx_timeout
1696  *  @dev : Pointer to net device structure
1697  *  Description: this function is called when a packet transmission fails to
1698  *   complete within a reasonable time. The driver will mark the error in the
1699  *   netdev structure and arrange for the device to be reset to a sane state
1700  *   in order to transmit a new packet.
1701  */
1702 static void stmmac_tx_timeout(struct net_device *dev)
1703 {
1704         struct stmmac_priv *priv = netdev_priv(dev);
1705
1706         /* Clear Tx resources and restart transmitting again */
1707         stmmac_tx_err(priv);
1708 }
1709
1710 /* Configuration changes (passed on by ifconfig) */
1711 static int stmmac_config(struct net_device *dev, struct ifmap *map)
1712 {
1713         if (dev->flags & IFF_UP)        /* can't act on a running interface */
1714                 return -EBUSY;
1715
1716         /* Don't allow changing the I/O address */
1717         if (map->base_addr != dev->base_addr) {
1718                 pr_warning("%s: can't change I/O address\n", dev->name);
1719                 return -EOPNOTSUPP;
1720         }
1721
1722         /* Don't allow changing the IRQ */
1723         if (map->irq != dev->irq) {
1724                 pr_warning("%s: can't change IRQ number %d\n",
1725                        dev->name, dev->irq);
1726                 return -EOPNOTSUPP;
1727         }
1728
1729         /* ignore other fields */
1730         return 0;
1731 }
1732
1733 /**
1734  *  stmmac_set_rx_mode - entry point for multicast addressing
1735  *  @dev : pointer to the device structure
1736  *  Description:
1737  *  This function is a driver entry point which gets called by the kernel
1738  *  whenever multicast addresses must be enabled/disabled.
1739  *  Return value:
1740  *  void.
1741  */
1742 static void stmmac_set_rx_mode(struct net_device *dev)
1743 {
1744         struct stmmac_priv *priv = netdev_priv(dev);
1745
1746         spin_lock(&priv->lock);
1747         priv->hw->mac->set_filter(dev, priv->synopsys_id);
1748         spin_unlock(&priv->lock);
1749 }
1750
1751 /**
1752  *  stmmac_change_mtu - entry point to change MTU size for the device.
1753  *  @dev : device pointer.
1754  *  @new_mtu : the new MTU size for the device.
1755  *  Description: the Maximum Transfer Unit (MTU) is used by the network layer
1756  *  to drive packet transmission. Ethernet has an MTU of 1500 octets
1757  *  (ETH_DATA_LEN). This value can be changed with ifconfig.
1758  *  Return value:
1759  *  0 on success and an appropriate (-)ve integer as defined in errno.h
1760  *  file on failure.
1761  */
1762 static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
1763 {
1764         struct stmmac_priv *priv = netdev_priv(dev);
1765         int max_mtu;
1766
1767         if (netif_running(dev)) {
1768                 pr_err("%s: must be stopped to change its MTU\n", dev->name);
1769                 return -EBUSY;
1770         }
1771
1772         if (priv->plat->enh_desc)
1773                 max_mtu = JUMBO_LEN;
1774         else
1775                 max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN);
1776
1777         if ((new_mtu < 46) || (new_mtu > max_mtu)) {
1778                 pr_err("%s: invalid MTU, max MTU is: %d\n", dev->name, max_mtu);
1779                 return -EINVAL;
1780         }
1781
1782         dev->mtu = new_mtu;
1783         netdev_update_features(dev);
1784
1785         return 0;
1786 }
1787
1788 static netdev_features_t stmmac_fix_features(struct net_device *dev,
1789         netdev_features_t features)
1790 {
1791         struct stmmac_priv *priv = netdev_priv(dev);
1792
1793         if (priv->plat->rx_coe == STMMAC_RX_COE_NONE)
1794                 features &= ~NETIF_F_RXCSUM;
1795         else if (priv->plat->rx_coe == STMMAC_RX_COE_TYPE1)
1796                 features &= ~NETIF_F_IPV6_CSUM;
1797         if (!priv->plat->tx_coe)
1798                 features &= ~NETIF_F_ALL_CSUM;
1799
1800         /* Some GMAC devices have a bugged Jumbo frame support that
1801          * needs to have the Tx COE disabled for oversized frames
1802          * (due to limited buffer sizes). In this case we disable
1803          * the TX csum insertionin the TDES and not use SF. */
1804         if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN))
1805                 features &= ~NETIF_F_ALL_CSUM;
1806
1807         return features;
1808 }
1809
1810 static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
1811 {
1812         struct net_device *dev = (struct net_device *)dev_id;
1813         struct stmmac_priv *priv = netdev_priv(dev);
1814
1815         if (unlikely(!dev)) {
1816                 pr_err("%s: invalid dev pointer\n", __func__);
1817                 return IRQ_NONE;
1818         }
1819
1820         /* To handle GMAC own interrupts */
1821         if (priv->plat->has_gmac) {
1822                 int status = priv->hw->mac->host_irq_status((void __iomem *)
1823                                                             dev->base_addr,
1824                                                             &priv->xstats);
1825                 if (unlikely(status)) {
1826                         /* For LPI we need to save the tx status */
1827                         if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE)
1828                                 priv->tx_path_in_lpi_mode = true;
1829                         if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE)
1830                                 priv->tx_path_in_lpi_mode = false;
1831                 }
1832         }
1833
1834         /* To handle DMA interrupts */
1835         stmmac_dma_interrupt(priv);
1836
1837         return IRQ_HANDLED;
1838 }
1839
1840 #ifdef CONFIG_NET_POLL_CONTROLLER
1841 /* Polling receive - used by NETCONSOLE and other diagnostic tools
1842  * to allow network I/O with interrupts disabled. */
1843 static void stmmac_poll_controller(struct net_device *dev)
1844 {
1845         disable_irq(dev->irq);
1846         stmmac_interrupt(dev->irq, dev);
1847         enable_irq(dev->irq);
1848 }
1849 #endif
1850
1851 /**
1852  *  stmmac_ioctl - Entry point for the Ioctl
1853  *  @dev: Device pointer.
1854  *  @rq: An IOCTL specefic structure, that can contain a pointer to
1855  *  a proprietary structure used to pass information to the driver.
1856  *  @cmd: IOCTL command
1857  *  Description:
1858  *  Currently there are no special functionality supported in IOCTL, just the
1859  *  phy_mii_ioctl(...) can be invoked.
1860  */
1861 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1862 {
1863         struct stmmac_priv *priv = netdev_priv(dev);
1864         int ret;
1865
1866         if (!netif_running(dev))
1867                 return -EINVAL;
1868
1869         if (!priv->phydev)
1870                 return -EINVAL;
1871
1872         ret = phy_mii_ioctl(priv->phydev, rq, cmd);
1873
1874         return ret;
1875 }
1876
1877 #ifdef CONFIG_STMMAC_DEBUG_FS
1878 static struct dentry *stmmac_fs_dir;
1879 static struct dentry *stmmac_rings_status;
1880 static struct dentry *stmmac_dma_cap;
1881
1882 static void sysfs_display_ring(void *head, int size, int extend_desc,
1883                                 struct seq_file *seq)
1884 {
1885         int i;
1886         struct dma_extended_desc *ep = (struct dma_extended_desc *) head;
1887         struct dma_desc *p = (struct dma_desc *) head;
1888
1889         for (i = 0; i < size; i++) {
1890                 u64 x;
1891                 if (extend_desc) {
1892                         x = *(u64 *) ep;
1893                         seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
1894                                    i, (unsigned int) virt_to_phys(ep),
1895                                    (unsigned int) x, (unsigned int) (x >> 32),
1896                                    ep->basic.des2, ep->basic.des3);
1897                         ep++;
1898                 } else {
1899                         x = *(u64 *) p;
1900                         seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
1901                                    i, (unsigned int) virt_to_phys(ep),
1902                                    (unsigned int) x, (unsigned int) (x >> 32),
1903                                    p->des2, p->des3);
1904                         p++;
1905                 }
1906                 seq_printf(seq, "\n");
1907         }
1908 }
1909
1910 static int stmmac_sysfs_ring_read(struct seq_file *seq, void *v)
1911 {
1912         struct net_device *dev = seq->private;
1913         struct stmmac_priv *priv = netdev_priv(dev);
1914         unsigned int txsize = priv->dma_tx_size;
1915         unsigned int rxsize = priv->dma_rx_size;
1916
1917         if (priv->extend_desc) {
1918                 seq_printf(seq, "Extended RX descriptor ring:\n");
1919                 sysfs_display_ring((void *) priv->dma_erx, rxsize, 1, seq);
1920                 seq_printf(seq, "Extended TX descriptor ring:\n");
1921                 sysfs_display_ring((void *) priv->dma_etx, txsize, 1, seq);
1922         } else {
1923                 seq_printf(seq, "RX descriptor ring:\n");
1924                 sysfs_display_ring((void *)priv->dma_rx, rxsize, 0, seq);
1925                 seq_printf(seq, "TX descriptor ring:\n");
1926                 sysfs_display_ring((void *)priv->dma_tx, txsize, 0, seq);
1927         }
1928
1929         return 0;
1930 }
1931
1932 static int stmmac_sysfs_ring_open(struct inode *inode, struct file *file)
1933 {
1934         return single_open(file, stmmac_sysfs_ring_read, inode->i_private);
1935 }
1936
1937 static const struct file_operations stmmac_rings_status_fops = {
1938         .owner = THIS_MODULE,
1939         .open = stmmac_sysfs_ring_open,
1940         .read = seq_read,
1941         .llseek = seq_lseek,
1942         .release = single_release,
1943 };
1944
1945 static int stmmac_sysfs_dma_cap_read(struct seq_file *seq, void *v)
1946 {
1947         struct net_device *dev = seq->private;
1948         struct stmmac_priv *priv = netdev_priv(dev);
1949
1950         if (!priv->hw_cap_support) {
1951                 seq_printf(seq, "DMA HW features not supported\n");
1952                 return 0;
1953         }
1954
1955         seq_printf(seq, "==============================\n");
1956         seq_printf(seq, "\tDMA HW features\n");
1957         seq_printf(seq, "==============================\n");
1958
1959         seq_printf(seq, "\t10/100 Mbps %s\n",
1960                    (priv->dma_cap.mbps_10_100) ? "Y" : "N");
1961         seq_printf(seq, "\t1000 Mbps %s\n",
1962                    (priv->dma_cap.mbps_1000) ? "Y" : "N");
1963         seq_printf(seq, "\tHalf duple %s\n",
1964                    (priv->dma_cap.half_duplex) ? "Y" : "N");
1965         seq_printf(seq, "\tHash Filter: %s\n",
1966                    (priv->dma_cap.hash_filter) ? "Y" : "N");
1967         seq_printf(seq, "\tMultiple MAC address registers: %s\n",
1968                    (priv->dma_cap.multi_addr) ? "Y" : "N");
1969         seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfatces): %s\n",
1970                    (priv->dma_cap.pcs) ? "Y" : "N");
1971         seq_printf(seq, "\tSMA (MDIO) Interface: %s\n",
1972                    (priv->dma_cap.sma_mdio) ? "Y" : "N");
1973         seq_printf(seq, "\tPMT Remote wake up: %s\n",
1974                    (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N");
1975         seq_printf(seq, "\tPMT Magic Frame: %s\n",
1976                    (priv->dma_cap.pmt_magic_frame) ? "Y" : "N");
1977         seq_printf(seq, "\tRMON module: %s\n",
1978                    (priv->dma_cap.rmon) ? "Y" : "N");
1979         seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n",
1980                    (priv->dma_cap.time_stamp) ? "Y" : "N");
1981         seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp:%s\n",
1982                    (priv->dma_cap.atime_stamp) ? "Y" : "N");
1983         seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE) %s\n",
1984                    (priv->dma_cap.eee) ? "Y" : "N");
1985         seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N");
1986         seq_printf(seq, "\tChecksum Offload in TX: %s\n",
1987                    (priv->dma_cap.tx_coe) ? "Y" : "N");
1988         seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n",
1989                    (priv->dma_cap.rx_coe_type1) ? "Y" : "N");
1990         seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n",
1991                    (priv->dma_cap.rx_coe_type2) ? "Y" : "N");
1992         seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n",
1993                    (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N");
1994         seq_printf(seq, "\tNumber of Additional RX channel: %d\n",
1995                    priv->dma_cap.number_rx_channel);
1996         seq_printf(seq, "\tNumber of Additional TX channel: %d\n",
1997                    priv->dma_cap.number_tx_channel);
1998         seq_printf(seq, "\tEnhanced descriptors: %s\n",
1999                    (priv->dma_cap.enh_desc) ? "Y" : "N");
2000
2001         return 0;
2002 }
2003
2004 static int stmmac_sysfs_dma_cap_open(struct inode *inode, struct file *file)
2005 {
2006         return single_open(file, stmmac_sysfs_dma_cap_read, inode->i_private);
2007 }
2008
2009 static const struct file_operations stmmac_dma_cap_fops = {
2010         .owner = THIS_MODULE,
2011         .open = stmmac_sysfs_dma_cap_open,
2012         .read = seq_read,
2013         .llseek = seq_lseek,
2014         .release = single_release,
2015 };
2016
2017 static int stmmac_init_fs(struct net_device *dev)
2018 {
2019         /* Create debugfs entries */
2020         stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL);
2021
2022         if (!stmmac_fs_dir || IS_ERR(stmmac_fs_dir)) {
2023                 pr_err("ERROR %s, debugfs create directory failed\n",
2024                        STMMAC_RESOURCE_NAME);
2025
2026                 return -ENOMEM;
2027         }
2028
2029         /* Entry to report DMA RX/TX rings */
2030         stmmac_rings_status = debugfs_create_file("descriptors_status",
2031                                            S_IRUGO, stmmac_fs_dir, dev,
2032                                            &stmmac_rings_status_fops);
2033
2034         if (!stmmac_rings_status || IS_ERR(stmmac_rings_status)) {
2035                 pr_info("ERROR creating stmmac ring debugfs file\n");
2036                 debugfs_remove(stmmac_fs_dir);
2037
2038                 return -ENOMEM;
2039         }
2040
2041         /* Entry to report the DMA HW features */
2042         stmmac_dma_cap = debugfs_create_file("dma_cap", S_IRUGO, stmmac_fs_dir,
2043                                              dev, &stmmac_dma_cap_fops);
2044
2045         if (!stmmac_dma_cap || IS_ERR(stmmac_dma_cap)) {
2046                 pr_info("ERROR creating stmmac MMC debugfs file\n");
2047                 debugfs_remove(stmmac_rings_status);
2048                 debugfs_remove(stmmac_fs_dir);
2049
2050                 return -ENOMEM;
2051         }
2052
2053         return 0;
2054 }
2055
2056 static void stmmac_exit_fs(void)
2057 {
2058         debugfs_remove(stmmac_rings_status);
2059         debugfs_remove(stmmac_dma_cap);
2060         debugfs_remove(stmmac_fs_dir);
2061 }
2062 #endif /* CONFIG_STMMAC_DEBUG_FS */
2063
2064 static const struct net_device_ops stmmac_netdev_ops = {
2065         .ndo_open = stmmac_open,
2066         .ndo_start_xmit = stmmac_xmit,
2067         .ndo_stop = stmmac_release,
2068         .ndo_change_mtu = stmmac_change_mtu,
2069         .ndo_fix_features = stmmac_fix_features,
2070         .ndo_set_rx_mode = stmmac_set_rx_mode,
2071         .ndo_tx_timeout = stmmac_tx_timeout,
2072         .ndo_do_ioctl = stmmac_ioctl,
2073         .ndo_set_config = stmmac_config,
2074 #ifdef CONFIG_NET_POLL_CONTROLLER
2075         .ndo_poll_controller = stmmac_poll_controller,
2076 #endif
2077         .ndo_set_mac_address = eth_mac_addr,
2078 };
2079
2080 /**
2081  *  stmmac_hw_init - Init the MAC device
2082  *  @priv : pointer to the private device structure.
2083  *  Description: this function detects which MAC device
2084  *  (GMAC/MAC10-100) has to attached, checks the HW capability
2085  *  (if supported) and sets the driver's features (for example
2086  *  to use the ring or chaine mode or support the normal/enh
2087  *  descriptor structure).
2088  */
2089 static int stmmac_hw_init(struct stmmac_priv *priv)
2090 {
2091         int ret;
2092         struct mac_device_info *mac;
2093
2094         /* Identify the MAC HW device */
2095         if (priv->plat->has_gmac) {
2096                 priv->dev->priv_flags |= IFF_UNICAST_FLT;
2097                 mac = dwmac1000_setup(priv->ioaddr);
2098         } else {
2099                 mac = dwmac100_setup(priv->ioaddr);
2100         }
2101         if (!mac)
2102                 return -ENOMEM;
2103
2104         priv->hw = mac;
2105
2106         /* Get and dump the chip ID */
2107         priv->synopsys_id = stmmac_get_synopsys_id(priv);
2108
2109         /* To use alternate (extended) or normal descriptor structures */
2110         stmmac_selec_desc_mode(priv);
2111
2112         /* To use the chained or ring mode */
2113         if (chain_mode) {
2114                 priv->hw->chain = &chain_mode_ops;
2115                 pr_info(" Chain mode enabled\n");
2116                 priv->mode = STMMAC_CHAIN_MODE;
2117         } else {
2118                 priv->hw->ring = &ring_mode_ops;
2119                 pr_info(" Ring mode enabled\n");
2120                 priv->mode = STMMAC_RING_MODE;
2121         }
2122
2123         /* Get the HW capability (new GMAC newer than 3.50a) */
2124         priv->hw_cap_support = stmmac_get_hw_features(priv);
2125         if (priv->hw_cap_support) {
2126                 pr_info(" DMA HW capability register supported");
2127
2128                 /* We can override some gmac/dma configuration fields: e.g.
2129                  * enh_desc, tx_coe (e.g. that are passed through the
2130                  * platform) with the values from the HW capability
2131                  * register (if supported).
2132                  */
2133                 priv->plat->enh_desc = priv->dma_cap.enh_desc;
2134                 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up;
2135
2136                 priv->plat->tx_coe = priv->dma_cap.tx_coe;
2137
2138                 if (priv->dma_cap.rx_coe_type2)
2139                         priv->plat->rx_coe = STMMAC_RX_COE_TYPE2;
2140                 else if (priv->dma_cap.rx_coe_type1)
2141                         priv->plat->rx_coe = STMMAC_RX_COE_TYPE1;
2142
2143         } else
2144                 pr_info(" No HW DMA feature register supported");
2145
2146         /* Enable the IPC (Checksum Offload) and check if the feature has been
2147          * enabled during the core configuration. */
2148         ret = priv->hw->mac->rx_ipc(priv->ioaddr);
2149         if (!ret) {
2150                 pr_warning(" RX IPC Checksum Offload not configured.\n");
2151                 priv->plat->rx_coe = STMMAC_RX_COE_NONE;
2152         }
2153
2154         if (priv->plat->rx_coe)
2155                 pr_info(" RX Checksum Offload Engine supported (type %d)\n",
2156                         priv->plat->rx_coe);
2157         if (priv->plat->tx_coe)
2158                 pr_info(" TX Checksum insertion supported\n");
2159
2160         if (priv->plat->pmt) {
2161                 pr_info(" Wake-Up On Lan supported\n");
2162                 device_set_wakeup_capable(priv->device, 1);
2163         }
2164
2165         return 0;
2166 }
2167
2168 /**
2169  * stmmac_dvr_probe
2170  * @device: device pointer
2171  * @plat_dat: platform data pointer
2172  * @addr: iobase memory address
2173  * Description: this is the main probe function used to
2174  * call the alloc_etherdev, allocate the priv structure.
2175  */
2176 struct stmmac_priv *stmmac_dvr_probe(struct device *device,
2177                                      struct plat_stmmacenet_data *plat_dat,
2178                                      void __iomem *addr)
2179 {
2180         int ret = 0;
2181         struct net_device *ndev = NULL;
2182         struct stmmac_priv *priv;
2183
2184         ndev = alloc_etherdev(sizeof(struct stmmac_priv));
2185         if (!ndev)
2186                 return NULL;
2187
2188         SET_NETDEV_DEV(ndev, device);
2189
2190         priv = netdev_priv(ndev);
2191         priv->device = device;
2192         priv->dev = ndev;
2193
2194         ether_setup(ndev);
2195
2196         stmmac_set_ethtool_ops(ndev);
2197         priv->pause = pause;
2198         priv->plat = plat_dat;
2199         priv->ioaddr = addr;
2200         priv->dev->base_addr = (unsigned long)addr;
2201
2202         /* Verify driver arguments */
2203         stmmac_verify_args();
2204
2205         /* Override with kernel parameters if supplied XXX CRS XXX
2206          * this needs to have multiple instances */
2207         if ((phyaddr >= 0) && (phyaddr <= 31))
2208                 priv->plat->phy_addr = phyaddr;
2209
2210         /* Init MAC and get the capabilities */
2211         ret = stmmac_hw_init(priv);
2212         if (ret)
2213                 goto error_free_netdev;
2214
2215         ndev->netdev_ops = &stmmac_netdev_ops;
2216
2217         ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2218                             NETIF_F_RXCSUM;
2219         ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA;
2220         ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
2221 #ifdef STMMAC_VLAN_TAG_USED
2222         /* Both mac100 and gmac support receive VLAN tag detection */
2223         ndev->features |= NETIF_F_HW_VLAN_RX;
2224 #endif
2225         priv->msg_enable = netif_msg_init(debug, default_msg_level);
2226
2227         if (flow_ctrl)
2228                 priv->flow_ctrl = FLOW_AUTO;    /* RX/TX pause on */
2229
2230         /* Rx Watchdog is available in the COREs newer than the 3.40.
2231          * In some case, for example on bugged HW this feature
2232          * has to be disable and this can be done by passing the
2233          * riwt_off field from the platform.
2234          */
2235         if ((priv->synopsys_id >= DWMAC_CORE_3_50) && (!priv->plat->riwt_off)) {
2236                 priv->use_riwt = 1;
2237                 pr_info(" Enable RX Mitigation via HW Watchdog Timer\n");
2238         }
2239
2240         netif_napi_add(ndev, &priv->napi, stmmac_poll, 64);
2241
2242         spin_lock_init(&priv->lock);
2243         spin_lock_init(&priv->tx_lock);
2244
2245         ret = register_netdev(ndev);
2246         if (ret) {
2247                 pr_err("%s: ERROR %i registering the device\n", __func__, ret);
2248                 goto error_netdev_register;
2249         }
2250
2251         priv->stmmac_clk = clk_get(priv->device, STMMAC_RESOURCE_NAME);
2252         if (IS_ERR(priv->stmmac_clk)) {
2253                 pr_warning("%s: warning: cannot get CSR clock\n", __func__);
2254                 goto error_clk_get;
2255         }
2256
2257         /* If a specific clk_csr value is passed from the platform
2258          * this means that the CSR Clock Range selection cannot be
2259          * changed at run-time and it is fixed. Viceversa the driver'll try to
2260          * set the MDC clock dynamically according to the csr actual
2261          * clock input.
2262          */
2263         if (!priv->plat->clk_csr)
2264                 stmmac_clk_csr_set(priv);
2265         else
2266                 priv->clk_csr = priv->plat->clk_csr;
2267
2268         stmmac_check_pcs_mode(priv);
2269
2270         if (!priv->pcs) {
2271                 /* MDIO bus Registration */
2272                 ret = stmmac_mdio_register(ndev);
2273                 if (ret < 0) {
2274                         pr_debug("%s: MDIO bus (id: %d) registration failed",
2275                                  __func__, priv->plat->bus_id);
2276                         goto error_mdio_register;
2277                 }
2278         }
2279
2280         return priv;
2281
2282 error_mdio_register:
2283         clk_put(priv->stmmac_clk);
2284 error_clk_get:
2285         unregister_netdev(ndev);
2286 error_netdev_register:
2287         netif_napi_del(&priv->napi);
2288 error_free_netdev:
2289         free_netdev(ndev);
2290
2291         return NULL;
2292 }
2293
2294 /**
2295  * stmmac_dvr_remove
2296  * @ndev: net device pointer
2297  * Description: this function resets the TX/RX processes, disables the MAC RX/TX
2298  * changes the link status, releases the DMA descriptor rings.
2299  */
2300 int stmmac_dvr_remove(struct net_device *ndev)
2301 {
2302         struct stmmac_priv *priv = netdev_priv(ndev);
2303
2304         pr_info("%s:\n\tremoving driver", __func__);
2305
2306         priv->hw->dma->stop_rx(priv->ioaddr);
2307         priv->hw->dma->stop_tx(priv->ioaddr);
2308
2309         stmmac_set_mac(priv->ioaddr, false);
2310         if (!priv->pcs)
2311                 stmmac_mdio_unregister(ndev);
2312         netif_carrier_off(ndev);
2313         unregister_netdev(ndev);
2314         free_netdev(ndev);
2315
2316         return 0;
2317 }
2318
2319 #ifdef CONFIG_PM
2320 int stmmac_suspend(struct net_device *ndev)
2321 {
2322         struct stmmac_priv *priv = netdev_priv(ndev);
2323         unsigned long flags;
2324
2325         if (!ndev || !netif_running(ndev))
2326                 return 0;
2327
2328         if (priv->phydev)
2329                 phy_stop(priv->phydev);
2330
2331         spin_lock_irqsave(&priv->lock, flags);
2332
2333         netif_device_detach(ndev);
2334         netif_stop_queue(ndev);
2335
2336         napi_disable(&priv->napi);
2337
2338         /* Stop TX/RX DMA */
2339         priv->hw->dma->stop_tx(priv->ioaddr);
2340         priv->hw->dma->stop_rx(priv->ioaddr);
2341
2342         stmmac_clear_descriptors(priv);
2343
2344         /* Enable Power down mode by programming the PMT regs */
2345         if (device_may_wakeup(priv->device))
2346                 priv->hw->mac->pmt(priv->ioaddr, priv->wolopts);
2347         else {
2348                 stmmac_set_mac(priv->ioaddr, false);
2349                 /* Disable clock in case of PWM is off */
2350                 clk_disable_unprepare(priv->stmmac_clk);
2351         }
2352         spin_unlock_irqrestore(&priv->lock, flags);
2353         return 0;
2354 }
2355
2356 int stmmac_resume(struct net_device *ndev)
2357 {
2358         struct stmmac_priv *priv = netdev_priv(ndev);
2359         unsigned long flags;
2360
2361         if (!netif_running(ndev))
2362                 return 0;
2363
2364         spin_lock_irqsave(&priv->lock, flags);
2365
2366         /* Power Down bit, into the PM register, is cleared
2367          * automatically as soon as a magic packet or a Wake-up frame
2368          * is received. Anyway, it's better to manually clear
2369          * this bit because it can generate problems while resuming
2370          * from another devices (e.g. serial console). */
2371         if (device_may_wakeup(priv->device))
2372                 priv->hw->mac->pmt(priv->ioaddr, 0);
2373         else
2374                 /* enable the clk prevously disabled */
2375                 clk_prepare_enable(priv->stmmac_clk);
2376
2377         netif_device_attach(ndev);
2378
2379         /* Enable the MAC and DMA */
2380         stmmac_set_mac(priv->ioaddr, true);
2381         priv->hw->dma->start_tx(priv->ioaddr);
2382         priv->hw->dma->start_rx(priv->ioaddr);
2383
2384         napi_enable(&priv->napi);
2385
2386         netif_start_queue(ndev);
2387
2388         spin_unlock_irqrestore(&priv->lock, flags);
2389
2390         if (priv->phydev)
2391                 phy_start(priv->phydev);
2392
2393         return 0;
2394 }
2395
2396 int stmmac_freeze(struct net_device *ndev)
2397 {
2398         if (!ndev || !netif_running(ndev))
2399                 return 0;
2400
2401         return stmmac_release(ndev);
2402 }
2403
2404 int stmmac_restore(struct net_device *ndev)
2405 {
2406         if (!ndev || !netif_running(ndev))
2407                 return 0;
2408
2409         return stmmac_open(ndev);
2410 }
2411 #endif /* CONFIG_PM */
2412
2413 /* Driver can be configured w/ and w/ both PCI and Platf drivers
2414  * depending on the configuration selected.
2415  */
2416 static int __init stmmac_init(void)
2417 {
2418         int ret;
2419
2420         ret = stmmac_register_platform();
2421         if (ret)
2422                 goto err;
2423         ret = stmmac_register_pci();
2424         if (ret)
2425                 goto err_pci;
2426         return 0;
2427 err_pci:
2428         stmmac_unregister_platform();
2429 err:
2430         pr_err("stmmac: driver registration failed\n");
2431         return ret;
2432 }
2433
2434 static void __exit stmmac_exit(void)
2435 {
2436         stmmac_unregister_platform();
2437         stmmac_unregister_pci();
2438 }
2439
2440 module_init(stmmac_init);
2441 module_exit(stmmac_exit);
2442
2443 #ifndef MODULE
2444 static int __init stmmac_cmdline_opt(char *str)
2445 {
2446         char *opt;
2447
2448         if (!str || !*str)
2449                 return -EINVAL;
2450         while ((opt = strsep(&str, ",")) != NULL) {
2451                 if (!strncmp(opt, "debug:", 6)) {
2452                         if (kstrtoint(opt + 6, 0, &debug))
2453                                 goto err;
2454                 } else if (!strncmp(opt, "phyaddr:", 8)) {
2455                         if (kstrtoint(opt + 8, 0, &phyaddr))
2456                                 goto err;
2457                 } else if (!strncmp(opt, "dma_txsize:", 11)) {
2458                         if (kstrtoint(opt + 11, 0, &dma_txsize))
2459                                 goto err;
2460                 } else if (!strncmp(opt, "dma_rxsize:", 11)) {
2461                         if (kstrtoint(opt + 11, 0, &dma_rxsize))
2462                                 goto err;
2463                 } else if (!strncmp(opt, "buf_sz:", 7)) {
2464                         if (kstrtoint(opt + 7, 0, &buf_sz))
2465                                 goto err;
2466                 } else if (!strncmp(opt, "tc:", 3)) {
2467                         if (kstrtoint(opt + 3, 0, &tc))
2468                                 goto err;
2469                 } else if (!strncmp(opt, "watchdog:", 9)) {
2470                         if (kstrtoint(opt + 9, 0, &watchdog))
2471                                 goto err;
2472                 } else if (!strncmp(opt, "flow_ctrl:", 10)) {
2473                         if (kstrtoint(opt + 10, 0, &flow_ctrl))
2474                                 goto err;
2475                 } else if (!strncmp(opt, "pause:", 6)) {
2476                         if (kstrtoint(opt + 6, 0, &pause))
2477                                 goto err;
2478                 } else if (!strncmp(opt, "eee_timer:", 10)) {
2479                         if (kstrtoint(opt + 10, 0, &eee_timer))
2480                                 goto err;
2481                 } else if (!strncmp(opt, "chain_mode:", 11)) {
2482                         if (kstrtoint(opt + 11, 0, &chain_mode))
2483                                 goto err;
2484                 }
2485         }
2486         return 0;
2487
2488 err:
2489         pr_err("%s: ERROR broken module parameter conversion", __func__);
2490         return -EINVAL;
2491 }
2492
2493 __setup("stmmaceth=", stmmac_cmdline_opt);
2494 #endif
2495
2496 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver");
2497 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
2498 MODULE_LICENSE("GPL");