drivers/net/ethernet/stmicro/stmmac/stmmac_main.c

   1 /*******************************************************************************
   2   This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
   3   ST Ethernet IPs are built around a Synopsys IP Core.
   4
   5         Copyright(C) 2007-2011 STMicroelectronics Ltd
   6
   7   This program is free software; you can redistribute it and/or modify it
   8   under the terms and conditions of the GNU General Public License,
   9   version 2, as published by the Free Software Foundation.
  10
  11   This program is distributed in the hope it will be useful, but WITHOUT
  12   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14   more details.
  15
  16   You should have received a copy of the GNU General Public License along with
  17   this program; if not, write to the Free Software Foundation, Inc.,
  18   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  19
  20   The full GNU General Public License is included in this distribution in
  21   the file called "COPYING".
  22
  23   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
  24
  25   Documentation available at:
  26         http://www.stlinux.com
  27   Support available at:
  28         https://bugzilla.stlinux.com/
  29 *******************************************************************************/
  30
  31 #include <linux/clk.h>
  32 #include <linux/kernel.h>
  33 #include <linux/interrupt.h>
  34 #include <linux/ip.h>
  35 #include <linux/tcp.h>
  36 #include <linux/skbuff.h>
  37 #include <linux/ethtool.h>
  38 #include <linux/if_ether.h>
  39 #include <linux/crc32.h>
  40 #include <linux/mii.h>
  41 #include <linux/if.h>
  42 #include <linux/if_vlan.h>
  43 #include <linux/dma-mapping.h>
  44 #include <linux/slab.h>
  45 #include <linux/prefetch.h>
  46 #include <linux/pinctrl/consumer.h>
  47 #ifdef CONFIG_DEBUG_FS
  48 #include <linux/debugfs.h>
  49 #include <linux/seq_file.h>
  50 #endif /* CONFIG_DEBUG_FS */
  51 #include <linux/net_tstamp.h>
  52 #include "stmmac_ptp.h"
  53 #include "stmmac.h"
  54 #include <linux/reset.h>
  55 #include <linux/of_mdio.h>
  56
  57 #define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x)
  58
  59 /* Module parameters */
  60 #define TX_TIMEO        5000
  61 static int watchdog = TX_TIMEO;
  62 module_param(watchdog, int, S_IRUGO | S_IWUSR);
  63 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)");
  64
  65 static int debug = -1;
  66 module_param(debug, int, S_IRUGO | S_IWUSR);
  67 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)");
  68
  69 static int phyaddr = -1;
  70 module_param(phyaddr, int, S_IRUGO);
  71 MODULE_PARM_DESC(phyaddr, "Physical device address");
  72
  73 #define DMA_TX_SIZE 256
  74 static int dma_txsize = DMA_TX_SIZE;
  75 module_param(dma_txsize, int, S_IRUGO | S_IWUSR);
  76 MODULE_PARM_DESC(dma_txsize, "Number of descriptors in the TX list");
  77
  78 #define DMA_RX_SIZE 256
  79 static int dma_rxsize = DMA_RX_SIZE;
  80 module_param(dma_rxsize, int, S_IRUGO | S_IWUSR);
  81 MODULE_PARM_DESC(dma_rxsize, "Number of descriptors in the RX list");
  82
  83 static int flow_ctrl = FLOW_OFF;
  84 module_param(flow_ctrl, int, S_IRUGO | S_IWUSR);
  85 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]");
  86
  87 static int pause = PAUSE_TIME;
  88 module_param(pause, int, S_IRUGO | S_IWUSR);
  89 MODULE_PARM_DESC(pause, "Flow Control Pause Time");
  90
  91 #define TC_DEFAULT 64
  92 static int tc = TC_DEFAULT;
  93 module_param(tc, int, S_IRUGO | S_IWUSR);
  94 MODULE_PARM_DESC(tc, "DMA threshold control value");
  95
  96 #define DEFAULT_BUFSIZE 1536
  97 static int buf_sz = DEFAULT_BUFSIZE;
  98 module_param(buf_sz, int, S_IRUGO | S_IWUSR);
  99 MODULE_PARM_DESC(buf_sz, "DMA buffer size");
 100
 101 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
 102                                       NETIF_MSG_LINK | NETIF_MSG_IFUP |
 103                                       NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);
 104
 105 #define STMMAC_DEFAULT_LPI_TIMER        1000
 106 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER;
 107 module_param(eee_timer, int, S_IRUGO | S_IWUSR);
 108 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec");
 109 #define STMMAC_LPI_T(x) (jiffies + msecs_to_jiffies(x))
 110
 111 /* By default the driver will use the ring mode to manage tx and rx descriptors
 112  * but passing this value so user can force to use the chain instead of the ring
 113  */
 114 static unsigned int chain_mode;
 115 module_param(chain_mode, int, S_IRUGO);
 116 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode");
 117
 118 static irqreturn_t stmmac_interrupt(int irq, void *dev_id);
 119
 120 #ifdef CONFIG_DEBUG_FS
 121 static int stmmac_init_fs(struct net_device *dev);
 122 static void stmmac_exit_fs(struct net_device *dev);
 123 #endif
 124
 125 #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x))
 126
 127 /**
 128  * stmmac_verify_args - verify the driver parameters.
 129  * Description: it checks the driver parameters and set a default in case of
 130  * errors.
 131  */
 132 static void stmmac_verify_args(void)
 133 {
 134         if (unlikely(watchdog < 0))
 135                 watchdog = TX_TIMEO;
 136         if (unlikely(dma_rxsize < 0))
 137                 dma_rxsize = DMA_RX_SIZE;
 138         if (unlikely(dma_txsize < 0))
 139                 dma_txsize = DMA_TX_SIZE;
 140         if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB)))
 141                 buf_sz = DEFAULT_BUFSIZE;
 142         if (unlikely(flow_ctrl > 1))
 143                 flow_ctrl = FLOW_AUTO;
 144         else if (likely(flow_ctrl < 0))
 145                 flow_ctrl = FLOW_OFF;
 146         if (unlikely((pause < 0) || (pause > 0xffff)))
 147                 pause = PAUSE_TIME;
 148         if (eee_timer < 0)
 149                 eee_timer = STMMAC_DEFAULT_LPI_TIMER;
 150 }
 151
 152 /**
 153  * stmmac_clk_csr_set - dynamically set the MDC clock
 154  * @priv: driver private structure
 155  * Description: this is to dynamically set the MDC clock according to the csr
 156  * clock input.
 157  * Note:
 158  *      If a specific clk_csr value is passed from the platform
 159  *      this means that the CSR Clock Range selection cannot be
 160  *      changed at run-time and it is fixed (as reported in the driver
 161  *      documentation). Viceversa the driver will try to set the MDC
 162  *      clock dynamically according to the actual clock input.
 163  */
 164 static void stmmac_clk_csr_set(struct stmmac_priv *priv)
 165 {
 166         u32 clk_rate;
 167
 168         //clk_rate = clk_get_rate(priv->stmmac_clk);
 169         clk_rate = clk_get_rate(priv->pclk);
 170
 171         /* Platform provided default clk_csr would be assumed valid
 172          * for all other cases except for the below mentioned ones.
 173          * For values higher than the IEEE 802.3 specified frequency
 174          * we can not estimate the proper divider as it is not known
 175          * the frequency of clk_csr_i. So we do not change the default
 176          * divider.
 177          */
 178         if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) {
 179                 if (clk_rate < CSR_F_35M)
 180                         priv->clk_csr = STMMAC_CSR_20_35M;
 181                 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M))
 182                         priv->clk_csr = STMMAC_CSR_35_60M;
 183                 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M))
 184                         priv->clk_csr = STMMAC_CSR_60_100M;
 185                 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M))
 186                         priv->clk_csr = STMMAC_CSR_100_150M;
 187                 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M))
 188                         priv->clk_csr = STMMAC_CSR_150_250M;
 189                 else if ((clk_rate >= CSR_F_250M) && (clk_rate <= CSR_F_300M))
 190                         priv->clk_csr = STMMAC_CSR_250_300M;
 191         }
 192 }
 193
 194 static void print_pkt(unsigned char *buf, int len)
 195 {
 196         pr_debug("len = %d byte, buf addr: 0x%p\n", len, buf);
 197         print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len);
 198 }
 199
 200 /* minimum number of free TX descriptors required to wake up TX process */
 201 #define STMMAC_TX_THRESH(x)     (x->dma_tx_size/4)
 202
 203 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv)
 204 {
 205         return priv->dirty_tx + priv->dma_tx_size - priv->cur_tx - 1;
 206 }
 207
 208 /**
 209  * stmmac_hw_fix_mac_speed - callback for speed selection
 210  * @priv: driver private structure
 211  * Description: on some platforms (e.g. ST), some HW system configuraton
 212  * registers have to be set according to the link speed negotiated.
 213  */
 214 static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv *priv)
 215 {
 216         struct phy_device *phydev = priv->phydev;
 217
 218         if (likely(priv->plat->fix_mac_speed))
 219                 priv->plat->fix_mac_speed(priv->plat->bsp_priv, phydev->speed);
 220 }
 221
 222 /**
 223  * stmmac_enable_eee_mode - check and enter in LPI mode
 224  * @priv: driver private structure
 225  * Description: this function is to verify and enter in LPI mode in case of
 226  * EEE.
 227  */
 228 static void stmmac_enable_eee_mode(struct stmmac_priv *priv)
 229 {
 230         /* Check and enter in LPI mode */
 231         if ((priv->dirty_tx == priv->cur_tx) &&
 232             (priv->tx_path_in_lpi_mode == false))
 233                 priv->hw->mac->set_eee_mode(priv->hw);
 234 }
 235
 236 /**
 237  * stmmac_disable_eee_mode - disable and exit from LPI mode
 238  * @priv: driver private structure
 239  * Description: this function is to exit and disable EEE in case of
 240  * LPI state is true. This is called by the xmit.
 241  */
 242 void stmmac_disable_eee_mode(struct stmmac_priv *priv)
 243 {
 244         priv->hw->mac->reset_eee_mode(priv->hw);
 245         del_timer_sync(&priv->eee_ctrl_timer);
 246         priv->tx_path_in_lpi_mode = false;
 247 }
 248
 249 /**
 250  * stmmac_eee_ctrl_timer - EEE TX SW timer.
 251  * @arg : data hook
 252  * Description:
 253  *  if there is no data transfer and if we are not in LPI state,
 254  *  then MAC Transmitter can be moved to LPI state.
 255  */
 256 static void stmmac_eee_ctrl_timer(unsigned long arg)
 257 {
 258         struct stmmac_priv *priv = (struct stmmac_priv *)arg;
 259
 260         stmmac_enable_eee_mode(priv);
 261         mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
 262 }
 263
 264 /**
 265  * stmmac_eee_init - init EEE
 266  * @priv: driver private structure
 267  * Description:
 268  *  if the GMAC supports the EEE (from the HW cap reg) and the phy device
 269  *  can also manage EEE, this function enable the LPI state and start related
 270  *  timer.
 271  */
 272 bool stmmac_eee_init(struct stmmac_priv *priv)
 273 {
 274         char *phy_bus_name = priv->plat->phy_bus_name;
 275         unsigned long flags;
 276         bool ret = false;
 277
 278         /* Using PCS we cannot dial with the phy registers at this stage
 279          * so we do not support extra feature like EEE.
 280          */
 281         if ((priv->pcs == STMMAC_PCS_RGMII) || (priv->pcs == STMMAC_PCS_TBI) ||
 282             (priv->pcs == STMMAC_PCS_RTBI))
 283                 goto out;
 284
 285         /* Never init EEE in case of a switch is attached */
 286         if (phy_bus_name && (!strcmp(phy_bus_name, "fixed")))
 287                 goto out;
 288
 289         /* MAC core supports the EEE feature. */
 290         if (priv->dma_cap.eee) {
 291                 int tx_lpi_timer = priv->tx_lpi_timer;
 292
 293                 /* Check if the PHY supports EEE */
 294                 if (phy_init_eee(priv->phydev, 1)) {
 295                         /* To manage at run-time if the EEE cannot be supported
 296                          * anymore (for example because the lp caps have been
 297                          * changed).
 298                          * In that case the driver disable own timers.
 299                          */
 300                         spin_lock_irqsave(&priv->lock, flags);
 301                         if (priv->eee_active) {
 302                                 pr_debug("stmmac: disable EEE\n");
 303                                 del_timer_sync(&priv->eee_ctrl_timer);
 304                                 priv->hw->mac->set_eee_timer(priv->hw, 0,
 305                                                              tx_lpi_timer);
 306                         }
 307                         priv->eee_active = 0;
 308                         spin_unlock_irqrestore(&priv->lock, flags);
 309                         goto out;
 310                 }
 311                 /* Activate the EEE and start timers */
 312                 spin_lock_irqsave(&priv->lock, flags);
 313                 if (!priv->eee_active) {
 314                         priv->eee_active = 1;
 315                         setup_timer(&priv->eee_ctrl_timer,
 316                                     stmmac_eee_ctrl_timer,
 317                                     (unsigned long)priv);
 318                         mod_timer(&priv->eee_ctrl_timer,
 319                                   STMMAC_LPI_T(eee_timer));
 320
 321                         priv->hw->mac->set_eee_timer(priv->hw,
 322                                                      STMMAC_DEFAULT_LIT_LS,
 323                                                      tx_lpi_timer);
 324                 }
 325                 /* Set HW EEE according to the speed */
 326                 priv->hw->mac->set_eee_pls(priv->hw, priv->phydev->link);
 327
 328                 ret = true;
 329                 spin_unlock_irqrestore(&priv->lock, flags);
 330
 331                 pr_debug("stmmac: Energy-Efficient Ethernet initialized\n");
 332         }
 333 out:
 334         return ret;
 335 }
 336
 337 /* stmmac_get_tx_hwtstamp - get HW TX timestamps
 338  * @priv: driver private structure
 339  * @entry : descriptor index to be used.
 340  * @skb : the socket buffer
 341  * Description :
 342  * This function will read timestamp from the descriptor & pass it to stack.
 343  * and also perform some sanity checks.
 344  */
 345 static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv,
 346                                    unsigned int entry, struct sk_buff *skb)
 347 {
 348         struct skb_shared_hwtstamps shhwtstamp;
 349         u64 ns;
 350         void *desc = NULL;
 351
 352         if (!priv->hwts_tx_en)
 353                 return;
 354
 355         /* exit if skb doesn't support hw tstamp */
 356         if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)))
 357                 return;
 358
 359         if (priv->adv_ts)
 360                 desc = (priv->dma_etx + entry);
 361         else
 362                 desc = (priv->dma_tx + entry);
 363
 364         /* check tx tstamp status */
 365         if (!priv->hw->desc->get_tx_timestamp_status((struct dma_desc *)desc))
 366                 return;
 367
 368         /* get the valid tstamp */
 369         ns = priv->hw->desc->get_timestamp(desc, priv->adv_ts);
 370
 371         memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
 372         shhwtstamp.hwtstamp = ns_to_ktime(ns);
 373         /* pass tstamp to stack */
 374         skb_tstamp_tx(skb, &shhwtstamp);
 375
 376         return;
 377 }
 378
 379 /* stmmac_get_rx_hwtstamp - get HW RX timestamps
 380  * @priv: driver private structure
 381  * @entry : descriptor index to be used.
 382  * @skb : the socket buffer
 383  * Description :
 384  * This function will read received packet's timestamp from the descriptor
 385  * and pass it to stack. It also perform some sanity checks.
 386  */
 387 static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv,
 388                                    unsigned int entry, struct sk_buff *skb)
 389 {
 390         struct skb_shared_hwtstamps *shhwtstamp = NULL;
 391         u64 ns;
 392         void *desc = NULL;
 393
 394         if (!priv->hwts_rx_en)
 395                 return;
 396
 397         if (priv->adv_ts)
 398                 desc = (priv->dma_erx + entry);
 399         else
 400                 desc = (priv->dma_rx + entry);
 401
 402         /* exit if rx tstamp is not valid */
 403         if (!priv->hw->desc->get_rx_timestamp_status(desc, priv->adv_ts))
 404                 return;
 405
 406         /* get valid tstamp */
 407         ns = priv->hw->desc->get_timestamp(desc, priv->adv_ts);
 408         shhwtstamp = skb_hwtstamps(skb);
 409         memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
 410         shhwtstamp->hwtstamp = ns_to_ktime(ns);
 411 }
 412
 413 /**
 414  *  stmmac_hwtstamp_ioctl - control hardware timestamping.
 415  *  @dev: device pointer.
 416  *  @ifr: An IOCTL specefic structure, that can contain a pointer to
 417  *  a proprietary structure used to pass information to the driver.
 418  *  Description:
 419  *  This function configures the MAC to enable/disable both outgoing(TX)
 420  *  and incoming(RX) packets time stamping based on user input.
 421  *  Return Value:
 422  *  0 on success and an appropriate -ve integer on failure.
 423  */
 424 static int stmmac_hwtstamp_ioctl(struct net_device *dev, struct ifreq *ifr)
 425 {
 426         struct stmmac_priv *priv = netdev_priv(dev);
 427         struct hwtstamp_config config;
 428         struct timespec64 now;
 429         u64 temp = 0;
 430         u32 ptp_v2 = 0;
 431         u32 tstamp_all = 0;
 432         u32 ptp_over_ipv4_udp = 0;
 433         u32 ptp_over_ipv6_udp = 0;
 434         u32 ptp_over_ethernet = 0;
 435         u32 snap_type_sel = 0;
 436         u32 ts_master_en = 0;
 437         u32 ts_event_en = 0;
 438         u32 value = 0;
 439
 440         if (!(priv->dma_cap.time_stamp || priv->adv_ts)) {
 441                 netdev_alert(priv->dev, "No support for HW time stamping\n");
 442                 priv->hwts_tx_en = 0;
 443                 priv->hwts_rx_en = 0;
 444
 445                 return -EOPNOTSUPP;
 446         }
 447
 448         if (copy_from_user(&config, ifr->ifr_data,
 449                            sizeof(struct hwtstamp_config)))
 450                 return -EFAULT;
 451
 452         pr_debug("%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n",
 453                  __func__, config.flags, config.tx_type, config.rx_filter);
 454
 455         /* reserved for future extensions */
 456         if (config.flags)
 457                 return -EINVAL;
 458
 459         if (config.tx_type != HWTSTAMP_TX_OFF &&
 460             config.tx_type != HWTSTAMP_TX_ON)
 461                 return -ERANGE;
 462
 463         if (priv->adv_ts) {
 464                 switch (config.rx_filter) {
 465                 case HWTSTAMP_FILTER_NONE:
 466                         /* time stamp no incoming packet at all */
 467                         config.rx_filter = HWTSTAMP_FILTER_NONE;
 468                         break;
 469
 470                 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
 471                         /* PTP v1, UDP, any kind of event packet */
 472                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
 473                         /* take time stamp for all event messages */
 474                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
 475
 476                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 477                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 478                         break;
 479
 480                 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
 481                         /* PTP v1, UDP, Sync packet */
 482                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC;
 483                         /* take time stamp for SYNC messages only */
 484                         ts_event_en = PTP_TCR_TSEVNTENA;
 485
 486                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 487                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 488                         break;
 489
 490                 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
 491                         /* PTP v1, UDP, Delay_req packet */
 492                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ;
 493                         /* take time stamp for Delay_Req messages only */
 494                         ts_master_en = PTP_TCR_TSMSTRENA;
 495                         ts_event_en = PTP_TCR_TSEVNTENA;
 496
 497                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 498                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 499                         break;
 500
 501                 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
 502                         /* PTP v2, UDP, any kind of event packet */
 503                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
 504                         ptp_v2 = PTP_TCR_TSVER2ENA;
 505                         /* take time stamp for all event messages */
 506                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
 507
 508                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 509                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 510                         break;
 511
 512                 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
 513                         /* PTP v2, UDP, Sync packet */
 514                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC;
 515                         ptp_v2 = PTP_TCR_TSVER2ENA;
 516                         /* take time stamp for SYNC messages only */
 517                         ts_event_en = PTP_TCR_TSEVNTENA;
 518
 519                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 520                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 521                         break;
 522
 523                 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
 524                         /* PTP v2, UDP, Delay_req packet */
 525                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ;
 526                         ptp_v2 = PTP_TCR_TSVER2ENA;
 527                         /* take time stamp for Delay_Req messages only */
 528                         ts_master_en = PTP_TCR_TSMSTRENA;
 529                         ts_event_en = PTP_TCR_TSEVNTENA;
 530
 531                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 532                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 533                         break;
 534
 535                 case HWTSTAMP_FILTER_PTP_V2_EVENT:
 536                         /* PTP v2/802.AS1 any layer, any kind of event packet */
 537                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
 538                         ptp_v2 = PTP_TCR_TSVER2ENA;
 539                         /* take time stamp for all event messages */
 540                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
 541
 542                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 543                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 544                         ptp_over_ethernet = PTP_TCR_TSIPENA;
 545                         break;
 546
 547                 case HWTSTAMP_FILTER_PTP_V2_SYNC:
 548                         /* PTP v2/802.AS1, any layer, Sync packet */
 549                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC;
 550                         ptp_v2 = PTP_TCR_TSVER2ENA;
 551                         /* take time stamp for SYNC messages only */
 552                         ts_event_en = PTP_TCR_TSEVNTENA;
 553
 554                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 555                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 556                         ptp_over_ethernet = PTP_TCR_TSIPENA;
 557                         break;
 558
 559                 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
 560                         /* PTP v2/802.AS1, any layer, Delay_req packet */
 561                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ;
 562                         ptp_v2 = PTP_TCR_TSVER2ENA;
 563                         /* take time stamp for Delay_Req messages only */
 564                         ts_master_en = PTP_TCR_TSMSTRENA;
 565                         ts_event_en = PTP_TCR_TSEVNTENA;
 566
 567                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 568                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 569                         ptp_over_ethernet = PTP_TCR_TSIPENA;
 570                         break;
 571
 572                 case HWTSTAMP_FILTER_ALL:
 573                         /* time stamp any incoming packet */
 574                         config.rx_filter = HWTSTAMP_FILTER_ALL;
 575                         tstamp_all = PTP_TCR_TSENALL;
 576                         break;
 577
 578                 default:
 579                         return -ERANGE;
 580                 }
 581         } else {
 582                 switch (config.rx_filter) {
 583                 case HWTSTAMP_FILTER_NONE:
 584                         config.rx_filter = HWTSTAMP_FILTER_NONE;
 585                         break;
 586                 default:
 587                         /* PTP v1, UDP, any kind of event packet */
 588                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
 589                         break;
 590                 }
 591         }
 592         priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1);
 593         priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON;
 594
 595         if (!priv->hwts_tx_en && !priv->hwts_rx_en)
 596                 priv->hw->ptp->config_hw_tstamping(priv->ioaddr, 0);
 597         else {
 598                 value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSCTRLSSR |
 599                          tstamp_all | ptp_v2 | ptp_over_ethernet |
 600                          ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en |
 601                          ts_master_en | snap_type_sel);
 602
 603                 priv->hw->ptp->config_hw_tstamping(priv->ioaddr, value);
 604
 605                 /* program Sub Second Increment reg */
 606                 priv->hw->ptp->config_sub_second_increment(priv->ioaddr);
 607
 608                 /* calculate default added value:
 609                  * formula is :
 610                  * addend = (2^32)/freq_div_ratio;
 611                  * where, freq_div_ratio = clk_ptp_ref_i/50MHz
 612                  * hence, addend = ((2^32) * 50MHz)/clk_ptp_ref_i;
 613                  * NOTE: clk_ptp_ref_i should be >= 50MHz to
 614                  *       achieve 20ns accuracy.
 615                  *
 616                  * 2^x * y == (y << x), hence
 617                  * 2^32 * 50000000 ==> (50000000 << 32)
 618                  */
 619                 temp = (u64) (50000000ULL << 32);
 620                 priv->default_addend = div_u64(temp, priv->clk_ptp_rate);
 621                 priv->hw->ptp->config_addend(priv->ioaddr,
 622                                              priv->default_addend);
 623
 624                 /* initialize system time */
 625                 ktime_get_real_ts64(&now);
 626
 627                 /* lower 32 bits of tv_sec are safe until y2106 */
 628                 priv->hw->ptp->init_systime(priv->ioaddr, (u32)now.tv_sec,
 629                                             now.tv_nsec);
 630         }
 631
 632         return copy_to_user(ifr->ifr_data, &config,
 633                             sizeof(struct hwtstamp_config)) ? -EFAULT : 0;
 634 }
 635
 636 /**
 637  * stmmac_init_ptp - init PTP
 638  * @priv: driver private structure
 639  * Description: this is to verify if the HW supports the PTPv1 or PTPv2.
 640  * This is done by looking at the HW cap. register.
 641  * This function also registers the ptp driver.
 642  */
 643 static int stmmac_init_ptp(struct stmmac_priv *priv)
 644 {
 645         if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp))
 646                 return -EOPNOTSUPP;
 647
 648         /* Fall-back to main clock in case of no PTP ref is passed */
 649         priv->clk_ptp_ref = devm_clk_get(priv->device, "clk_ptp_ref");
 650         if (IS_ERR(priv->clk_ptp_ref)) {
 651                 priv->clk_ptp_rate = clk_get_rate(priv->stmmac_clk);
 652                 priv->clk_ptp_ref = NULL;
 653         } else {
 654                 clk_prepare_enable(priv->clk_ptp_ref);
 655                 priv->clk_ptp_rate = clk_get_rate(priv->clk_ptp_ref);
 656         }
 657
 658         priv->adv_ts = 0;
 659         if (priv->dma_cap.atime_stamp && priv->extend_desc)
 660                 priv->adv_ts = 1;
 661
 662         if (netif_msg_hw(priv) && priv->dma_cap.time_stamp)
 663                 pr_debug("IEEE 1588-2002 Time Stamp supported\n");
 664
 665         if (netif_msg_hw(priv) && priv->adv_ts)
 666                 pr_debug("IEEE 1588-2008 Advanced Time Stamp supported\n");
 667
 668         priv->hw->ptp = &stmmac_ptp;
 669         priv->hwts_tx_en = 0;
 670         priv->hwts_rx_en = 0;
 671
 672         return stmmac_ptp_register(priv);
 673 }
 674
 675 static void stmmac_release_ptp(struct stmmac_priv *priv)
 676 {
 677         if (priv->clk_ptp_ref)
 678                 clk_disable_unprepare(priv->clk_ptp_ref);
 679         stmmac_ptp_unregister(priv);
 680 }
 681
 682 /**
 683  * stmmac_adjust_link - adjusts the link parameters
 684  * @dev: net device structure
 685  * Description: this is the helper called by the physical abstraction layer
 686  * drivers to communicate the phy link status. According the speed and duplex
 687  * this driver can invoke registered glue-logic as well.
 688  * It also invoke the eee initialization because it could happen when switch
 689  * on different networks (that are eee capable).
 690  */
 691 static void stmmac_adjust_link(struct net_device *dev)
 692 {
 693         struct stmmac_priv *priv = netdev_priv(dev);
 694         struct phy_device *phydev = priv->phydev;
 695         unsigned long flags;
 696         int new_state = 0;
 697         unsigned int fc = priv->flow_ctrl, pause_time = priv->pause;
 698
 699         if (phydev == NULL)
 700                 return;
 701
 702         spin_lock_irqsave(&priv->lock, flags);
 703
 704         if (phydev->link) {
 705                 u32 ctrl = readl(priv->ioaddr + MAC_CTRL_REG);
 706
 707                 /* Now we make sure that we can be in full duplex mode.
 708                  * If not, we operate in half-duplex mode. */
 709                 if (phydev->duplex != priv->oldduplex) {
 710                         new_state = 1;
 711                         if (!(phydev->duplex))
 712                                 ctrl &= ~priv->hw->link.duplex;
 713                         else
 714                                 ctrl |= priv->hw->link.duplex;
 715                         priv->oldduplex = phydev->duplex;
 716                 }
 717                 /* Flow Control operation */
 718                 if (phydev->pause)
 719                         priv->hw->mac->flow_ctrl(priv->hw, phydev->duplex,
 720                                                  fc, pause_time);
 721
 722                 if (phydev->speed != priv->speed) {
 723                         new_state = 1;
 724                         switch (phydev->speed) {
 725                         case 1000:
 726                                 if (likely(priv->plat->has_gmac))
 727                                         ctrl &= ~priv->hw->link.port;
 728                                 stmmac_hw_fix_mac_speed(priv);
 729                                 break;
 730                         case 100:
 731                         case 10:
 732                                 if (priv->plat->has_gmac) {
 733                                         ctrl |= priv->hw->link.port;
 734                                         if (phydev->speed == SPEED_100) {
 735                                                 ctrl |= priv->hw->link.speed;
 736                                         } else {
 737                                                 ctrl &= ~(priv->hw->link.speed);
 738                                         }
 739                                 } else {
 740                                         ctrl &= ~priv->hw->link.port;
 741                                 }
 742                                 stmmac_hw_fix_mac_speed(priv);
 743                                 break;
 744                         default:
 745                                 if (netif_msg_link(priv))
 746                                         pr_warn("%s: Speed (%d) not 10/100\n",
 747                                                 dev->name, phydev->speed);
 748                                 break;
 749                         }
 750
 751                         priv->speed = phydev->speed;
 752                 }
 753
 754                 writel(ctrl, priv->ioaddr + MAC_CTRL_REG);
 755
 756                 if (!priv->oldlink) {
 757                         new_state = 1;
 758                         priv->oldlink = 1;
 759                 }
 760         } else if (priv->oldlink) {
 761                 new_state = 1;
 762                 priv->oldlink = 0;
 763                 priv->speed = 0;
 764                 priv->oldduplex = -1;
 765         }
 766
 767         if (new_state && netif_msg_link(priv))
 768                 phy_print_status(phydev);
 769
 770         spin_unlock_irqrestore(&priv->lock, flags);
 771
 772         /* At this stage, it could be needed to setup the EEE or adjust some
 773          * MAC related HW registers.
 774          */
 775         priv->eee_enabled = stmmac_eee_init(priv);
 776 }
 777
 778 /**
 779  * stmmac_check_pcs_mode - verify if RGMII/SGMII is supported
 780  * @priv: driver private structure
 781  * Description: this is to verify if the HW supports the PCS.
 782  * Physical Coding Sublayer (PCS) interface that can be used when the MAC is
 783  * configured for the TBI, RTBI, or SGMII PHY interface.
 784  */
 785 static void stmmac_check_pcs_mode(struct stmmac_priv *priv)
 786 {
 787         int interface = priv->plat->interface;
 788
 789         if (priv->dma_cap.pcs) {
 790                 if ((interface == PHY_INTERFACE_MODE_RGMII) ||
 791                     (interface == PHY_INTERFACE_MODE_RGMII_ID) ||
 792                     (interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
 793                     (interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
 794                         pr_debug("STMMAC: PCS RGMII support enable\n");
 795                         priv->pcs = STMMAC_PCS_RGMII;
 796                 } else if (interface == PHY_INTERFACE_MODE_SGMII) {
 797                         pr_debug("STMMAC: PCS SGMII support enable\n");
 798                         priv->pcs = STMMAC_PCS_SGMII;
 799                 }
 800         }
 801 }
 802
 803 /**
 804  * stmmac_init_phy - PHY initialization
 805  * @dev: net device structure
 806  * Description: it initializes the driver's PHY state, and attaches the PHY
 807  * to the mac driver.
 808  *  Return value:
 809  *  0 on success
 810  */
 811 static int stmmac_init_phy(struct net_device *dev)
 812 {
 813         struct stmmac_priv *priv = netdev_priv(dev);
 814         struct phy_device *phydev;
 815         char phy_id_fmt[MII_BUS_ID_SIZE + 3];
 816         char bus_id[MII_BUS_ID_SIZE];
 817         int interface = priv->plat->interface;
 818         int max_speed = priv->plat->max_speed;
 819         priv->oldlink = 0;
 820         priv->speed = 0;
 821         priv->oldduplex = -1;
 822
 823         if (priv->plat->phy_node) {
 824                 phydev = of_phy_connect(dev, priv->plat->phy_node,
 825                                         &stmmac_adjust_link, 0, interface);
 826         } else {
 827                 if (priv->plat->phy_bus_name)
 828                         snprintf(bus_id, MII_BUS_ID_SIZE, "%s-%x",
 829                                  priv->plat->phy_bus_name, priv->plat->bus_id);
 830                 else
 831                         snprintf(bus_id, MII_BUS_ID_SIZE, "stmmac-%x",
 832                                  priv->plat->bus_id);
 833
 834                 snprintf(phy_id_fmt, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id,
 835                          priv->plat->phy_addr);
 836                 pr_debug("stmmac_init_phy:  trying to attach to %s\n",
 837                          phy_id_fmt);
 838
 839                 phydev = phy_connect(dev, phy_id_fmt, &stmmac_adjust_link,
 840                                      interface);
 841         }
 842
 843         if (IS_ERR_OR_NULL(phydev)) {
 844                 pr_err("%s: Could not attach to PHY\n", dev->name);
 845                 if (!phydev)
 846                         return -ENODEV;
 847
 848                 return PTR_ERR(phydev);
 849         }
 850
 851         /* Stop Advertising 1000BASE Capability if interface is not GMII */
 852         if ((interface == PHY_INTERFACE_MODE_MII) ||
 853             (interface == PHY_INTERFACE_MODE_RMII) ||
 854                 (max_speed < 1000 && max_speed > 0))
 855                 phydev->advertising &= ~(SUPPORTED_1000baseT_Half |
 856                                          SUPPORTED_1000baseT_Full);
 857
 858         /*
 859          * Broken HW is sometimes missing the pull-up resistor on the
 860          * MDIO line, which results in reads to non-existent devices returning
 861          * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent
 862          * device as well.
 863          * Note: phydev->phy_id is the result of reading the UID PHY registers.
 864          */
 865         if (!priv->plat->phy_node && phydev->phy_id == 0) {
 866                 phy_disconnect(phydev);
 867                 return -ENODEV;
 868         }
 869         pr_debug("stmmac_init_phy:  %s: attached to PHY (UID 0x%x)"
 870                  " Link = %d\n", dev->name, phydev->phy_id, phydev->link);
 871
 872         priv->phydev = phydev;
 873
 874         return 0;
 875 }
 876
 877 /**
 878  * stmmac_display_ring - display ring
 879  * @head: pointer to the head of the ring passed.
 880  * @size: size of the ring.
 881  * @extend_desc: to verify if extended descriptors are used.
 882  * Description: display the control/status and buffer descriptors.
 883  */
 884 static void stmmac_display_ring(void *head, int size, int extend_desc)
 885 {
 886         int i;
 887         struct dma_extended_desc *ep = (struct dma_extended_desc *)head;
 888         struct dma_desc *p = (struct dma_desc *)head;
 889
 890         for (i = 0; i < size; i++) {
 891                 u64 x;
 892                 if (extend_desc) {
 893                         x = *(u64 *) ep;
 894                         pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
 895                                 i, (unsigned int)virt_to_phys(ep),
 896                                 (unsigned int)x, (unsigned int)(x >> 32),
 897                                 ep->basic.des2, ep->basic.des3);
 898                         ep++;
 899                 } else {
 900                         x = *(u64 *) p;
 901                         pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x",
 902                                 i, (unsigned int)virt_to_phys(p),
 903                                 (unsigned int)x, (unsigned int)(x >> 32),
 904                                 p->des2, p->des3);
 905                         p++;
 906                 }
 907                 pr_info("\n");
 908         }
 909 }
 910
 911 static void stmmac_display_rings(struct stmmac_priv *priv)
 912 {
 913         unsigned int txsize = priv->dma_tx_size;
 914         unsigned int rxsize = priv->dma_rx_size;
 915
 916         if (priv->extend_desc) {
 917                 pr_info("Extended RX descriptor ring:\n");
 918                 stmmac_display_ring((void *)priv->dma_erx, rxsize, 1);
 919                 pr_info("Extended TX descriptor ring:\n");
 920                 stmmac_display_ring((void *)priv->dma_etx, txsize, 1);
 921         } else {
 922                 pr_info("RX descriptor ring:\n");
 923                 stmmac_display_ring((void *)priv->dma_rx, rxsize, 0);
 924                 pr_info("TX descriptor ring:\n");
 925                 stmmac_display_ring((void *)priv->dma_tx, txsize, 0);
 926         }
 927 }
 928
 929 static int stmmac_set_bfsize(int mtu, int bufsize)
 930 {
 931         int ret = bufsize;
 932
 933         if (mtu >= BUF_SIZE_4KiB)
 934                 ret = BUF_SIZE_8KiB;
 935         else if (mtu >= BUF_SIZE_2KiB)
 936                 ret = BUF_SIZE_4KiB;
 937         else if (mtu > DEFAULT_BUFSIZE)
 938                 ret = BUF_SIZE_2KiB;
 939         else
 940                 ret = DEFAULT_BUFSIZE;
 941
 942         return ret;
 943 }
 944
 945 /**
 946  * stmmac_clear_descriptors - clear descriptors
 947  * @priv: driver private structure
 948  * Description: this function is called to clear the tx and rx descriptors
 949  * in case of both basic and extended descriptors are used.
 950  */
 951 static void stmmac_clear_descriptors(struct stmmac_priv *priv)
 952 {
 953         int i;
 954         unsigned int txsize = priv->dma_tx_size;
 955         unsigned int rxsize = priv->dma_rx_size;
 956
 957         /* Clear the Rx/Tx descriptors */
 958         for (i = 0; i < rxsize; i++)
 959                 if (priv->extend_desc)
 960                         priv->hw->desc->init_rx_desc(&priv->dma_erx[i].basic,
 961                                                      priv->use_riwt, priv->mode,
 962                                                      (i == rxsize - 1));
 963                 else
 964                         priv->hw->desc->init_rx_desc(&priv->dma_rx[i],
 965                                                      priv->use_riwt, priv->mode,
 966                                                      (i == rxsize - 1));
 967         for (i = 0; i < txsize; i++)
 968                 if (priv->extend_desc)
 969                         priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic,
 970                                                      priv->mode,
 971                                                      (i == txsize - 1));
 972                 else
 973                         priv->hw->desc->init_tx_desc(&priv->dma_tx[i],
 974                                                      priv->mode,
 975                                                      (i == txsize - 1));
 976 }
 977
 978 /**
 979  * stmmac_init_rx_buffers - init the RX descriptor buffer.
 980  * @priv: driver private structure
 981  * @p: descriptor pointer
 982  * @i: descriptor index
 983  * @flags: gfp flag.
 984  * Description: this function is called to allocate a receive buffer, perform
 985  * the DMA mapping and init the descriptor.
 986  */
 987 static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p,
 988                                   int i, gfp_t flags)
 989 {
 990         struct sk_buff *skb;
 991
 992         skb = __netdev_alloc_skb_ip_align(priv->dev, priv->dma_buf_sz, flags);
 993         if (!skb) {
 994                 pr_err("%s: Rx init fails; skb is NULL\n", __func__);
 995                 return -ENOMEM;
 996         }
 997         priv->rx_skbuff[i] = skb;
 998         priv->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data,
 999                                                 priv->dma_buf_sz,
1000                                                 DMA_FROM_DEVICE);
1001         if (dma_mapping_error(priv->device, priv->rx_skbuff_dma[i])) {
1002                 pr_err("%s: DMA mapping error\n", __func__);
1003                 dev_kfree_skb_any(skb);
1004                 return -EINVAL;
1005         }
1006
1007         p->des2 = priv->rx_skbuff_dma[i];
1008
1009         if ((priv->hw->mode->init_desc3) &&
1010             (priv->dma_buf_sz == BUF_SIZE_16KiB))
1011                 priv->hw->mode->init_desc3(p);
1012
1013         return 0;
1014 }
1015
1016 static void stmmac_free_rx_buffers(struct stmmac_priv *priv, int i)
1017 {
1018         if (priv->rx_skbuff[i]) {
1019                 dma_unmap_single(priv->device, priv->rx_skbuff_dma[i],
1020                                  priv->dma_buf_sz, DMA_FROM_DEVICE);
1021                 dev_kfree_skb_any(priv->rx_skbuff[i]);
1022         }
1023         priv->rx_skbuff[i] = NULL;
1024 }
1025
1026 /**
1027  * init_dma_desc_rings - init the RX/TX descriptor rings
1028  * @dev: net device structure
1029  * @flags: gfp flag.
1030  * Description: this function initializes the DMA RX/TX descriptors
1031  * and allocates the socket buffers. It suppors the chained and ring
1032  * modes.
1033  */
1034 static int init_dma_desc_rings(struct net_device *dev, gfp_t flags)
1035 {
1036         int i;
1037         struct stmmac_priv *priv = netdev_priv(dev);
1038         unsigned int txsize = priv->dma_tx_size;
1039         unsigned int rxsize = priv->dma_rx_size;
1040         unsigned int bfsize = 0;
1041         int ret = -ENOMEM;
1042
1043         if (priv->hw->mode->set_16kib_bfsize)
1044                 bfsize = priv->hw->mode->set_16kib_bfsize(dev->mtu);
1045
1046         if (bfsize < BUF_SIZE_16KiB)
1047                 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz);
1048
1049         priv->dma_buf_sz = bfsize;
1050
1051         if (netif_msg_probe(priv))
1052                 pr_debug("%s: txsize %d, rxsize %d, bfsize %d\n", __func__,
1053                          txsize, rxsize, bfsize);
1054
1055         if (netif_msg_probe(priv)) {
1056                 pr_debug("(%s) dma_rx_phy=0x%08x dma_tx_phy=0x%08x\n", __func__,
1057                          (u32) priv->dma_rx_phy, (u32) priv->dma_tx_phy);
1058
1059                 /* RX INITIALIZATION */
1060                 pr_debug("\tSKB addresses:\nskb\t\tskb data\tdma data\n");
1061         }
1062         for (i = 0; i < rxsize; i++) {
1063                 struct dma_desc *p;
1064                 if (priv->extend_desc)
1065                         p = &((priv->dma_erx + i)->basic);
1066                 else
1067                         p = priv->dma_rx + i;
1068
1069                 ret = stmmac_init_rx_buffers(priv, p, i, flags);
1070                 if (ret)
1071                         goto err_init_rx_buffers;
1072
1073                 if (netif_msg_probe(priv))
1074                         pr_debug("[%p]\t[%p]\t[%x]\n", priv->rx_skbuff[i],
1075                                  priv->rx_skbuff[i]->data,
1076                                  (unsigned int)priv->rx_skbuff_dma[i]);
1077         }
1078         priv->cur_rx = 0;
1079         priv->dirty_rx = (unsigned int)(i - rxsize);
1080         buf_sz = bfsize;
1081
1082         /* Setup the chained descriptor addresses */
1083         if (priv->mode == STMMAC_CHAIN_MODE) {
1084                 if (priv->extend_desc) {
1085                         priv->hw->mode->init(priv->dma_erx, priv->dma_rx_phy,
1086                                              rxsize, 1);
1087                         priv->hw->mode->init(priv->dma_etx, priv->dma_tx_phy,
1088                                              txsize, 1);
1089                 } else {
1090                         priv->hw->mode->init(priv->dma_rx, priv->dma_rx_phy,
1091                                              rxsize, 0);
1092                         priv->hw->mode->init(priv->dma_tx, priv->dma_tx_phy,
1093                                              txsize, 0);
1094                 }
1095         }
1096
1097         /* TX INITIALIZATION */
1098         for (i = 0; i < txsize; i++) {
1099                 struct dma_desc *p;
1100                 if (priv->extend_desc)
1101                         p = &((priv->dma_etx + i)->basic);
1102                 else
1103                         p = priv->dma_tx + i;
1104                 p->des2 = 0;
1105                 priv->tx_skbuff_dma[i].buf = 0;
1106                 priv->tx_skbuff_dma[i].map_as_page = false;
1107                 priv->tx_skbuff[i] = NULL;
1108         }
1109
1110         priv->dirty_tx = 0;
1111         priv->cur_tx = 0;
1112         netdev_reset_queue(priv->dev);
1113
1114         stmmac_clear_descriptors(priv);
1115
1116         if (netif_msg_hw(priv))
1117                 stmmac_display_rings(priv);
1118
1119         return 0;
1120 err_init_rx_buffers:
1121         while (--i >= 0)
1122                 stmmac_free_rx_buffers(priv, i);
1123         return ret;
1124 }
1125
1126 static void dma_free_rx_skbufs(struct stmmac_priv *priv)
1127 {
1128         int i;
1129
1130         for (i = 0; i < priv->dma_rx_size; i++)
1131                 stmmac_free_rx_buffers(priv, i);
1132 }
1133
1134 static void dma_free_tx_skbufs(struct stmmac_priv *priv)
1135 {
1136         int i;
1137
1138         for (i = 0; i < priv->dma_tx_size; i++) {
1139                 struct dma_desc *p;
1140
1141                 if (priv->extend_desc)
1142                         p = &((priv->dma_etx + i)->basic);
1143                 else
1144                         p = priv->dma_tx + i;
1145
1146                 if (priv->tx_skbuff_dma[i].buf) {
1147                         if (priv->tx_skbuff_dma[i].map_as_page)
1148                                 dma_unmap_page(priv->device,
1149                                                priv->tx_skbuff_dma[i].buf,
1150                                                priv->hw->desc->get_tx_len(p),
1151                                                DMA_TO_DEVICE);
1152                         else
1153                                 dma_unmap_single(priv->device,
1154                                                  priv->tx_skbuff_dma[i].buf,
1155                                                  priv->hw->desc->get_tx_len(p),
1156                                                  DMA_TO_DEVICE);
1157                 }
1158
1159                 if (priv->tx_skbuff[i] != NULL) {
1160                         dev_kfree_skb_any(priv->tx_skbuff[i]);
1161                         priv->tx_skbuff[i] = NULL;
1162                         priv->tx_skbuff_dma[i].buf = 0;
1163                         priv->tx_skbuff_dma[i].map_as_page = false;
1164                 }
1165         }
1166 }
1167
1168 /**
1169  * alloc_dma_desc_resources - alloc TX/RX resources.
1170  * @priv: private structure
1171  * Description: according to which descriptor can be used (extend or basic)
1172  * this function allocates the resources for TX and RX paths. In case of
1173  * reception, for example, it pre-allocated the RX socket buffer in order to
1174  * allow zero-copy mechanism.
1175  */
1176 static int alloc_dma_desc_resources(struct stmmac_priv *priv)
1177 {
1178         unsigned int txsize = priv->dma_tx_size;
1179         unsigned int rxsize = priv->dma_rx_size;
1180         int ret = -ENOMEM;
1181
1182         priv->rx_skbuff_dma = kmalloc_array(rxsize, sizeof(dma_addr_t),
1183                                             GFP_KERNEL);
1184         if (!priv->rx_skbuff_dma)
1185                 return -ENOMEM;
1186
1187         priv->rx_skbuff = kmalloc_array(rxsize, sizeof(struct sk_buff *),
1188                                         GFP_KERNEL);
1189         if (!priv->rx_skbuff)
1190                 goto err_rx_skbuff;
1191
1192         priv->tx_skbuff_dma = kmalloc_array(txsize,
1193                                             sizeof(*priv->tx_skbuff_dma),
1194                                             GFP_KERNEL);
1195         if (!priv->tx_skbuff_dma)
1196                 goto err_tx_skbuff_dma;
1197
1198         priv->tx_skbuff = kmalloc_array(txsize, sizeof(struct sk_buff *),
1199                                         GFP_KERNEL);
1200         if (!priv->tx_skbuff)
1201                 goto err_tx_skbuff;
1202
1203         if (priv->extend_desc) {
1204                 priv->dma_erx = dma_zalloc_coherent(priv->device, rxsize *
1205                                                     sizeof(struct
1206                                                            dma_extended_desc),
1207                                                     &priv->dma_rx_phy,
1208                                                     GFP_KERNEL);
1209                 if (!priv->dma_erx)
1210                         goto err_dma;
1211
1212                 priv->dma_etx = dma_zalloc_coherent(priv->device, txsize *
1213                                                     sizeof(struct
1214                                                            dma_extended_desc),
1215                                                     &priv->dma_tx_phy,
1216                                                     GFP_KERNEL);
1217                 if (!priv->dma_etx) {
1218                         dma_free_coherent(priv->device, priv->dma_rx_size *
1219                                           sizeof(struct dma_extended_desc),
1220                                           priv->dma_erx, priv->dma_rx_phy);
1221                         goto err_dma;
1222                 }
1223         } else {
1224                 priv->dma_rx = dma_zalloc_coherent(priv->device, rxsize *
1225                                                    sizeof(struct dma_desc),
1226                                                    &priv->dma_rx_phy,
1227                                                    GFP_KERNEL);
1228                 if (!priv->dma_rx)
1229                         goto err_dma;
1230
1231                 priv->dma_tx = dma_zalloc_coherent(priv->device, txsize *
1232                                                    sizeof(struct dma_desc),
1233                                                    &priv->dma_tx_phy,
1234                                                    GFP_KERNEL);
1235                 if (!priv->dma_tx) {
1236                         dma_free_coherent(priv->device, priv->dma_rx_size *
1237                                           sizeof(struct dma_desc),
1238                                           priv->dma_rx, priv->dma_rx_phy);
1239                         goto err_dma;
1240                 }
1241         }
1242
1243         return 0;
1244
1245 err_dma:
1246         kfree(priv->tx_skbuff);
1247 err_tx_skbuff:
1248         kfree(priv->tx_skbuff_dma);
1249 err_tx_skbuff_dma:
1250         kfree(priv->rx_skbuff);
1251 err_rx_skbuff:
1252         kfree(priv->rx_skbuff_dma);
1253         return ret;
1254 }
1255
1256 static void free_dma_desc_resources(struct stmmac_priv *priv)
1257 {
1258         /* Release the DMA TX/RX socket buffers */
1259         dma_free_rx_skbufs(priv);
1260         dma_free_tx_skbufs(priv);
1261
1262         /* Free DMA regions of consistent memory previously allocated */
1263         if (!priv->extend_desc) {
1264                 dma_free_coherent(priv->device,
1265                                   priv->dma_tx_size * sizeof(struct dma_desc),
1266                                   priv->dma_tx, priv->dma_tx_phy);
1267                 dma_free_coherent(priv->device,
1268                                   priv->dma_rx_size * sizeof(struct dma_desc),
1269                                   priv->dma_rx, priv->dma_rx_phy);
1270         } else {
1271                 dma_free_coherent(priv->device, priv->dma_tx_size *
1272                                   sizeof(struct dma_extended_desc),
1273                                   priv->dma_etx, priv->dma_tx_phy);
1274                 dma_free_coherent(priv->device, priv->dma_rx_size *
1275                                   sizeof(struct dma_extended_desc),
1276                                   priv->dma_erx, priv->dma_rx_phy);
1277         }
1278         kfree(priv->rx_skbuff_dma);
1279         kfree(priv->rx_skbuff);
1280         kfree(priv->tx_skbuff_dma);
1281         kfree(priv->tx_skbuff);
1282 }
1283
1284 /**
1285  *  stmmac_dma_operation_mode - HW DMA operation mode
1286  *  @priv: driver private structure
1287  *  Description: it is used for configuring the DMA operation mode register in
1288  *  order to program the tx/rx DMA thresholds or Store-And-Forward mode.
1289  */
1290 static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
1291 {
1292         int rxfifosz = priv->plat->rx_fifo_size;
1293
1294         if (priv->plat->force_thresh_dma_mode)
1295                 priv->hw->dma->dma_mode(priv->ioaddr, tc, tc, rxfifosz);
1296         else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) {
1297                 /*
1298                  * In case of GMAC, SF mode can be enabled
1299                  * to perform the TX COE in HW. This depends on:
1300                  * 1) TX COE if actually supported
1301                  * 2) There is no bugged Jumbo frame support
1302                  *    that needs to not insert csum in the TDES.
1303                  */
1304                 priv->hw->dma->dma_mode(priv->ioaddr, SF_DMA_MODE, SF_DMA_MODE,
1305                                         rxfifosz);
1306                 priv->xstats.threshold = SF_DMA_MODE;
1307         } else
1308                 priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE,
1309                                         rxfifosz);
1310 }
1311
1312 /**
1313  * stmmac_tx_clean - to manage the transmission completion
1314  * @priv: driver private structure
1315  * Description: it reclaims the transmit resources after transmission completes.
1316  */
1317 static void stmmac_tx_clean(struct stmmac_priv *priv)
1318 {
1319         unsigned int txsize = priv->dma_tx_size;
1320         unsigned int bytes_compl = 0, pkts_compl = 0;
1321
1322         spin_lock(&priv->tx_lock);
1323
1324         priv->xstats.tx_clean++;
1325
1326         while (priv->dirty_tx != priv->cur_tx) {
1327                 int last;
1328                 unsigned int entry = priv->dirty_tx % txsize;
1329                 struct sk_buff *skb = priv->tx_skbuff[entry];
1330                 struct dma_desc *p;
1331
1332                 if (priv->extend_desc)
1333                         p = (struct dma_desc *)(priv->dma_etx + entry);
1334                 else
1335                         p = priv->dma_tx + entry;
1336
1337                 /* Check if the descriptor is owned by the DMA. */
1338                 if (priv->hw->desc->get_tx_owner(p))
1339                         break;
1340
1341                 /* Verify tx error by looking at the last segment. */
1342                 last = priv->hw->desc->get_tx_ls(p);
1343                 if (likely(last)) {
1344                         int tx_error =
1345                             priv->hw->desc->tx_status(&priv->dev->stats,
1346                                                       &priv->xstats, p,
1347                                                       priv->ioaddr);
1348                         if (likely(tx_error == 0)) {
1349                                 priv->dev->stats.tx_packets++;
1350                                 priv->xstats.tx_pkt_n++;
1351                         } else
1352                                 priv->dev->stats.tx_errors++;
1353
1354                         stmmac_get_tx_hwtstamp(priv, entry, skb);
1355                 }
1356                 if (netif_msg_tx_done(priv))
1357                         pr_debug("%s: curr %d, dirty %d\n", __func__,
1358                                  priv->cur_tx, priv->dirty_tx);
1359
1360                 if (likely(priv->tx_skbuff_dma[entry].buf)) {
1361                         if (priv->tx_skbuff_dma[entry].map_as_page)
1362                                 dma_unmap_page(priv->device,
1363                                                priv->tx_skbuff_dma[entry].buf,
1364                                                priv->hw->desc->get_tx_len(p),
1365                                                DMA_TO_DEVICE);
1366                         else
1367                                 dma_unmap_single(priv->device,
1368                                                  priv->tx_skbuff_dma[entry].buf,
1369                                                  priv->hw->desc->get_tx_len(p),
1370                                                  DMA_TO_DEVICE);
1371                         priv->tx_skbuff_dma[entry].buf = 0;
1372                         priv->tx_skbuff_dma[entry].map_as_page = false;
1373                 }
1374                 priv->hw->mode->clean_desc3(priv, p);
1375
1376                 if (likely(skb != NULL)) {
1377                         pkts_compl++;
1378                         bytes_compl += skb->len;
1379                         dev_consume_skb_any(skb);
1380                         priv->tx_skbuff[entry] = NULL;
1381                 }
1382
1383                 priv->hw->desc->release_tx_desc(p, priv->mode);
1384
1385                 priv->dirty_tx++;
1386         }
1387
1388         netdev_completed_queue(priv->dev, pkts_compl, bytes_compl);
1389
1390         if (unlikely(netif_queue_stopped(priv->dev) &&
1391                      stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv))) {
1392                 netif_tx_lock(priv->dev);
1393                 if (netif_queue_stopped(priv->dev) &&
1394                     stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv)) {
1395                         if (netif_msg_tx_done(priv))
1396                                 pr_debug("%s: restart transmit\n", __func__);
1397                         netif_wake_queue(priv->dev);
1398                 }
1399                 netif_tx_unlock(priv->dev);
1400         }
1401
1402         if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) {
1403                 stmmac_enable_eee_mode(priv);
1404                 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
1405         }
1406         spin_unlock(&priv->tx_lock);
1407 }
1408
1409 static inline void stmmac_enable_dma_irq(struct stmmac_priv *priv)
1410 {
1411         priv->hw->dma->enable_dma_irq(priv->ioaddr);
1412 }
1413
1414 static inline void stmmac_disable_dma_irq(struct stmmac_priv *priv)
1415 {
1416         priv->hw->dma->disable_dma_irq(priv->ioaddr);
1417 }
1418
1419 /**
1420  * stmmac_tx_err - to manage the tx error
1421  * @priv: driver private structure
1422  * Description: it cleans the descriptors and restarts the transmission
1423  * in case of transmission errors.
1424  */
1425 static void stmmac_tx_err(struct stmmac_priv *priv)
1426 {
1427         int i;
1428         int txsize = priv->dma_tx_size;
1429         netif_stop_queue(priv->dev);
1430
1431         priv->hw->dma->stop_tx(priv->ioaddr);
1432         dma_free_tx_skbufs(priv);
1433         for (i = 0; i < txsize; i++)
1434                 if (priv->extend_desc)
1435                         priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic,
1436                                                      priv->mode,
1437                                                      (i == txsize - 1));
1438                 else
1439                         priv->hw->desc->init_tx_desc(&priv->dma_tx[i],
1440                                                      priv->mode,
1441                                                      (i == txsize - 1));
1442         priv->dirty_tx = 0;
1443         priv->cur_tx = 0;
1444         netdev_reset_queue(priv->dev);
1445         priv->hw->dma->start_tx(priv->ioaddr);
1446
1447         priv->dev->stats.tx_errors++;
1448         netif_wake_queue(priv->dev);
1449 }
1450
1451 /**
1452  * stmmac_dma_interrupt - DMA ISR
1453  * @priv: driver private structure
1454  * Description: this is the DMA ISR. It is called by the main ISR.
1455  * It calls the dwmac dma routine and schedule poll method in case of some
1456  * work can be done.
1457  */
1458 static void stmmac_dma_interrupt(struct stmmac_priv *priv)
1459 {
1460         int status;
1461         int rxfifosz = priv->plat->rx_fifo_size;
1462
1463         status = priv->hw->dma->dma_interrupt(priv->ioaddr, &priv->xstats);
1464         if (likely((status & handle_rx)) || (status & handle_tx)) {
1465                 if (likely(napi_schedule_prep(&priv->napi))) {
1466                         stmmac_disable_dma_irq(priv);
1467                         __napi_schedule(&priv->napi);
1468                 }
1469         }
1470         if (unlikely(status & tx_hard_error_bump_tc)) {
1471                 /* Try to bump up the dma threshold on this failure */
1472                 if (unlikely(priv->xstats.threshold != SF_DMA_MODE) &&
1473                     (tc <= 256)) {
1474                         tc += 64;
1475                         if (priv->plat->force_thresh_dma_mode)
1476                                 priv->hw->dma->dma_mode(priv->ioaddr, tc, tc,
1477                                                         rxfifosz);
1478                         else
1479                                 priv->hw->dma->dma_mode(priv->ioaddr, tc,
1480                                                         SF_DMA_MODE, rxfifosz);
1481                         priv->xstats.threshold = tc;
1482                 }
1483         } else if (unlikely(status == tx_hard_error))
1484                 stmmac_tx_err(priv);
1485 }
1486
1487 /**
1488  * stmmac_mmc_setup: setup the Mac Management Counters (MMC)
1489  * @priv: driver private structure
1490  * Description: this masks the MMC irq, in fact, the counters are managed in SW.
1491  */
1492 static void stmmac_mmc_setup(struct stmmac_priv *priv)
1493 {
1494         unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET |
1495             MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET;
1496
1497         dwmac_mmc_intr_all_mask(priv->ioaddr);
1498
1499         if (priv->dma_cap.rmon) {
1500                 dwmac_mmc_ctrl(priv->ioaddr, mode);
1501                 memset(&priv->mmc, 0, sizeof(struct stmmac_counters));
1502         } else
1503                 pr_info(" No MAC Management Counters available\n");
1504 }
1505
1506 /**
1507  * stmmac_get_synopsys_id - return the SYINID.
1508  * @priv: driver private structure
1509  * Description: this simple function is to decode and return the SYINID
1510  * starting from the HW core register.
1511  */
1512 static u32 stmmac_get_synopsys_id(struct stmmac_priv *priv)
1513 {
1514         u32 hwid = priv->hw->synopsys_uid;
1515
1516         /* Check Synopsys Id (not available on old chips) */
1517         if (likely(hwid)) {
1518                 u32 uid = ((hwid & 0x0000ff00) >> 8);
1519                 u32 synid = (hwid & 0x000000ff);
1520
1521                 pr_info("stmmac - user ID: 0x%x, Synopsys ID: 0x%x\n",
1522                         uid, synid);
1523
1524                 return synid;
1525         }
1526         return 0;
1527 }
1528
1529 /**
1530  * stmmac_selec_desc_mode - to select among: normal/alternate/extend descriptors
1531  * @priv: driver private structure
1532  * Description: select the Enhanced/Alternate or Normal descriptors.
1533  * In case of Enhanced/Alternate, it checks if the extended descriptors are
1534  * supported by the HW capability register.
1535  */
1536 static void stmmac_selec_desc_mode(struct stmmac_priv *priv)
1537 {
1538         if (priv->plat->enh_desc) {
1539                 pr_info(" Enhanced/Alternate descriptors\n");
1540
1541                 /* GMAC older than 3.50 has no extended descriptors */
1542                 if (priv->synopsys_id >= DWMAC_CORE_3_50) {
1543                         pr_info("\tEnabled extended descriptors\n");
1544                         priv->extend_desc = 1;
1545                 } else
1546                         pr_warn("Extended descriptors not supported\n");
1547
1548                 priv->hw->desc = &enh_desc_ops;
1549         } else {
1550                 pr_info(" Normal descriptors\n");
1551                 priv->hw->desc = &ndesc_ops;
1552         }
1553 }
1554
1555 /**
1556  * stmmac_get_hw_features - get MAC capabilities from the HW cap. register.
1557  * @priv: driver private structure
1558  * Description:
1559  *  new GMAC chip generations have a new register to indicate the
1560  *  presence of the optional feature/functions.
1561  *  This can be also used to override the value passed through the
1562  *  platform and necessary for old MAC10/100 and GMAC chips.
1563  */
1564 static int stmmac_get_hw_features(struct stmmac_priv *priv)
1565 {
1566         u32 hw_cap = 0;
1567
1568         if (priv->hw->dma->get_hw_feature) {
1569                 hw_cap = priv->hw->dma->get_hw_feature(priv->ioaddr);
1570
1571                 priv->dma_cap.mbps_10_100 = (hw_cap & DMA_HW_FEAT_MIISEL);
1572                 priv->dma_cap.mbps_1000 = (hw_cap & DMA_HW_FEAT_GMIISEL) >> 1;
1573                 priv->dma_cap.half_duplex = (hw_cap & DMA_HW_FEAT_HDSEL) >> 2;
1574                 priv->dma_cap.hash_filter = (hw_cap & DMA_HW_FEAT_HASHSEL) >> 4;
1575                 priv->dma_cap.multi_addr = (hw_cap & DMA_HW_FEAT_ADDMAC) >> 5;
1576                 priv->dma_cap.pcs = (hw_cap & DMA_HW_FEAT_PCSSEL) >> 6;
1577                 priv->dma_cap.sma_mdio = (hw_cap & DMA_HW_FEAT_SMASEL) >> 8;
1578                 priv->dma_cap.pmt_remote_wake_up =
1579                     (hw_cap & DMA_HW_FEAT_RWKSEL) >> 9;
1580                 priv->dma_cap.pmt_magic_frame =
1581                     (hw_cap & DMA_HW_FEAT_MGKSEL) >> 10;
1582                 /* MMC */
1583                 priv->dma_cap.rmon = (hw_cap & DMA_HW_FEAT_MMCSEL) >> 11;
1584                 /* IEEE 1588-2002 */
1585                 priv->dma_cap.time_stamp =
1586                     (hw_cap & DMA_HW_FEAT_TSVER1SEL) >> 12;
1587                 /* IEEE 1588-2008 */
1588                 priv->dma_cap.atime_stamp =
1589                     (hw_cap & DMA_HW_FEAT_TSVER2SEL) >> 13;
1590                 /* 802.3az - Energy-Efficient Ethernet (EEE) */
1591                 priv->dma_cap.eee = (hw_cap & DMA_HW_FEAT_EEESEL) >> 14;
1592                 priv->dma_cap.av = (hw_cap & DMA_HW_FEAT_AVSEL) >> 15;
1593                 /* TX and RX csum */
1594                 priv->dma_cap.tx_coe = (hw_cap & DMA_HW_FEAT_TXCOESEL) >> 16;
1595                 priv->dma_cap.rx_coe_type1 =
1596                     (hw_cap & DMA_HW_FEAT_RXTYP1COE) >> 17;
1597                 priv->dma_cap.rx_coe_type2 =
1598                     (hw_cap & DMA_HW_FEAT_RXTYP2COE) >> 18;
1599                 priv->dma_cap.rxfifo_over_2048 =
1600                     (hw_cap & DMA_HW_FEAT_RXFIFOSIZE) >> 19;
1601                 /* TX and RX number of channels */
1602                 priv->dma_cap.number_rx_channel =
1603                     (hw_cap & DMA_HW_FEAT_RXCHCNT) >> 20;
1604                 priv->dma_cap.number_tx_channel =
1605                     (hw_cap & DMA_HW_FEAT_TXCHCNT) >> 22;
1606                 /* Alternate (enhanced) DESC mode */
1607                 priv->dma_cap.enh_desc = (hw_cap & DMA_HW_FEAT_ENHDESSEL) >> 24;
1608         }
1609
1610         return hw_cap;
1611 }
1612
1613 /**
1614  * stmmac_check_ether_addr - check if the MAC addr is valid
1615  * @priv: driver private structure
1616  * Description:
1617  * it is to verify if the MAC address is valid, in case of failures it
1618  * generates a random MAC address
1619  */
1620 static void stmmac_check_ether_addr(struct stmmac_priv *priv)
1621 {
1622         if (!is_valid_ether_addr(priv->dev->dev_addr)) {
1623                 priv->hw->mac->get_umac_addr(priv->hw,
1624                                              priv->dev->dev_addr, 0);
1625                 if (likely(priv->plat->get_eth_addr))
1626                         priv->plat->get_eth_addr(priv->plat->bsp_priv,
1627                                 priv->dev->dev_addr);
1628                 if (!is_valid_ether_addr(priv->dev->dev_addr))
1629                         eth_hw_addr_random(priv->dev);
1630                 pr_info("%s: device MAC address %pM\n", priv->dev->name,
1631                         priv->dev->dev_addr);
1632         }
1633 }
1634
1635 /**
1636  * stmmac_init_dma_engine - DMA init.
1637  * @priv: driver private structure
1638  * Description:
1639  * It inits the DMA invoking the specific MAC/GMAC callback.
1640  * Some DMA parameters can be passed from the platform;
1641  * in case of these are not passed a default is kept for the MAC or GMAC.
1642  */
1643 static int stmmac_init_dma_engine(struct stmmac_priv *priv)
1644 {
1645         int pbl = DEFAULT_DMA_PBL, fixed_burst = 0, burst_len = 0;
1646         int mixed_burst = 0;
1647         int atds = 0;
1648
1649         if (priv->plat->dma_cfg) {
1650                 pbl = priv->plat->dma_cfg->pbl;
1651                 fixed_burst = priv->plat->dma_cfg->fixed_burst;
1652                 mixed_burst = priv->plat->dma_cfg->mixed_burst;
1653                 burst_len = priv->plat->dma_cfg->burst_len;
1654         }
1655
1656         if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE))
1657                 atds = 1;
1658
1659         return priv->hw->dma->init(priv->ioaddr, pbl, fixed_burst, mixed_burst,
1660                                    burst_len, priv->dma_tx_phy,
1661                                    priv->dma_rx_phy, atds);
1662 }
1663
1664 /**
1665  * stmmac_tx_timer - mitigation sw timer for tx.
1666  * @data: data pointer
1667  * Description:
1668  * This is the timer handler to directly invoke the stmmac_tx_clean.
1669  */
1670 static void stmmac_tx_timer(unsigned long data)
1671 {
1672         struct stmmac_priv *priv = (struct stmmac_priv *)data;
1673
1674         stmmac_tx_clean(priv);
1675 }
1676
1677 /**
1678  * stmmac_init_tx_coalesce - init tx mitigation options.
1679  * @priv: driver private structure
1680  * Description:
1681  * This inits the transmit coalesce parameters: i.e. timer rate,
1682  * timer handler and default threshold used for enabling the
1683  * interrupt on completion bit.
1684  */
1685 static void stmmac_init_tx_coalesce(struct stmmac_priv *priv)
1686 {
1687         priv->tx_coal_frames = STMMAC_TX_FRAMES;
1688         priv->tx_coal_timer = STMMAC_COAL_TX_TIMER;
1689         init_timer(&priv->txtimer);
1690         priv->txtimer.expires = STMMAC_COAL_TIMER(priv->tx_coal_timer);
1691         priv->txtimer.data = (unsigned long)priv;
1692         priv->txtimer.function = stmmac_tx_timer;
1693         add_timer(&priv->txtimer);
1694 }
1695
1696 /**
1697  * stmmac_hw_setup - setup mac in a usable state.
1698  *  @dev : pointer to the device structure.
1699  *  Description:
1700  *  this is the main function to setup the HW in a usable state because the
1701  *  dma engine is reset, the core registers are configured (e.g. AXI,
1702  *  Checksum features, timers). The DMA is ready to start receiving and
1703  *  transmitting.
1704  *  Return value:
1705  *  0 on success and an appropriate (-)ve integer as defined in errno.h
1706  *  file on failure.
1707  */
1708 static int stmmac_hw_setup(struct net_device *dev, bool init_ptp)
1709 {
1710         struct stmmac_priv *priv = netdev_priv(dev);
1711         int ret;
1712
1713         /* DMA initialization and SW reset */
1714         ret = stmmac_init_dma_engine(priv);
1715         if (ret < 0) {
1716                 pr_err("%s: DMA engine initialization failed\n", __func__);
1717                 return ret;
1718         }
1719
1720         /* Copy the MAC addr into the HW  */
1721         priv->hw->mac->set_umac_addr(priv->hw, dev->dev_addr, 0);
1722
1723         /* If required, perform hw setup of the bus. */
1724         if (priv->plat->bus_setup)
1725                 priv->plat->bus_setup(priv->ioaddr);
1726
1727         /* Initialize the MAC Core */
1728         priv->hw->mac->core_init(priv->hw, dev->mtu);
1729
1730         ret = priv->hw->mac->rx_ipc(priv->hw);
1731         if (!ret) {
1732                 pr_warn(" RX IPC Checksum Offload disabled\n");
1733                 priv->plat->rx_coe = STMMAC_RX_COE_NONE;
1734                 priv->hw->rx_csum = 0;
1735         }
1736
1737         /* Enable the MAC Rx/Tx */
1738         stmmac_set_mac(priv->ioaddr, true);
1739
1740         /* Set the HW DMA mode and the COE */
1741         stmmac_dma_operation_mode(priv);
1742
1743         stmmac_mmc_setup(priv);
1744
1745         if (init_ptp) {
1746                 ret = stmmac_init_ptp(priv);
1747                 if (ret && ret != -EOPNOTSUPP)
1748                         pr_warn("%s: failed PTP initialisation\n", __func__);
1749         }
1750
1751 #ifdef CONFIG_DEBUG_FS
1752         if (init_ptp) {
1753                 ret = stmmac_init_fs(dev);
1754                 if (ret < 0)
1755                         pr_warn("%s: failed debugFS registration\n", __func__);
1756         }
1757 #endif
1758         /* Start the ball rolling... */
1759         pr_debug("%s: DMA RX/TX processes started...\n", dev->name);
1760         priv->hw->dma->start_tx(priv->ioaddr);
1761         priv->hw->dma->start_rx(priv->ioaddr);
1762
1763         /* Dump DMA/MAC registers */
1764         if (netif_msg_hw(priv)) {
1765                 priv->hw->mac->dump_regs(priv->hw);
1766                 priv->hw->dma->dump_regs(priv->ioaddr);
1767         }
1768         priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS;
1769
1770         if ((priv->use_riwt) && (priv->hw->dma->rx_watchdog)) {
1771                 priv->rx_riwt = MAX_DMA_RIWT;
1772                 priv->hw->dma->rx_watchdog(priv->ioaddr, MAX_DMA_RIWT);
1773         }
1774
1775         if (priv->pcs && priv->hw->mac->ctrl_ane)
1776                 priv->hw->mac->ctrl_ane(priv->hw, 0);
1777
1778         return 0;
1779 }
1780
1781 /**
1782  *  stmmac_open - open entry point of the driver
1783  *  @dev : pointer to the device structure.
1784  *  Description:
1785  *  This function is the open entry point of the driver.
1786  *  Return value:
1787  *  0 on success and an appropriate (-)ve integer as defined in errno.h
1788  *  file on failure.
1789  */
1790 static int stmmac_open(struct net_device *dev)
1791 {
1792         struct stmmac_priv *priv = netdev_priv(dev);
1793         int ret;
1794
1795         stmmac_check_ether_addr(priv);
1796
1797         if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI &&
1798             priv->pcs != STMMAC_PCS_RTBI) {
1799                 ret = stmmac_init_phy(dev);
1800                 if (ret) {
1801                         pr_err("%s: Cannot attach to PHY (error: %d)\n",
1802                                __func__, ret);
1803                         return ret;
1804                 }
1805         }
1806
1807         /* Extra statistics */
1808         memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats));
1809         priv->xstats.threshold = tc;
1810
1811         /* Create and initialize the TX/RX descriptors chains. */
1812         priv->dma_tx_size = STMMAC_ALIGN(dma_txsize);
1813         priv->dma_rx_size = STMMAC_ALIGN(dma_rxsize);
1814         priv->dma_buf_sz = STMMAC_ALIGN(buf_sz);
1815
1816         ret = alloc_dma_desc_resources(priv);
1817         if (ret < 0) {
1818                 pr_err("%s: DMA descriptors allocation failed\n", __func__);
1819                 goto dma_desc_error;
1820         }
1821
1822         ret = init_dma_desc_rings(dev, GFP_KERNEL);
1823         if (ret < 0) {
1824                 pr_err("%s: DMA descriptors initialization failed\n", __func__);
1825                 goto init_error;
1826         }
1827
1828         ret = stmmac_hw_setup(dev, true);
1829         if (ret < 0) {
1830                 pr_err("%s: Hw setup failed\n", __func__);
1831                 goto init_error;
1832         }
1833
1834         stmmac_init_tx_coalesce(priv);
1835
1836         if (priv->phydev)
1837                 phy_start(priv->phydev);
1838
1839         /* Request the IRQ lines */
1840         ret = request_irq(dev->irq, stmmac_interrupt,
1841                           IRQF_SHARED, dev->name, dev);
1842         if (unlikely(ret < 0)) {
1843                 pr_err("%s: ERROR: allocating the IRQ %d (error: %d)\n",
1844                        __func__, dev->irq, ret);
1845                 goto init_error;
1846         }
1847
1848         /* Request the Wake IRQ in case of another line is used for WoL */
1849         if (priv->wol_irq != dev->irq) {
1850                 ret = request_irq(priv->wol_irq, stmmac_interrupt,
1851                                   IRQF_SHARED, dev->name, dev);
1852                 if (unlikely(ret < 0)) {
1853                         pr_err("%s: ERROR: allocating the WoL IRQ %d (%d)\n",
1854                                __func__, priv->wol_irq, ret);
1855                         goto wolirq_error;
1856                 }
1857         }
1858
1859         /* Request the IRQ lines */
1860         if (priv->lpi_irq > 0) {
1861                 ret = request_irq(priv->lpi_irq, stmmac_interrupt, IRQF_SHARED,
1862                                   dev->name, dev);
1863                 if (unlikely(ret < 0)) {
1864                         pr_err("%s: ERROR: allocating the LPI IRQ %d (%d)\n",
1865                                __func__, priv->lpi_irq, ret);
1866                         goto lpiirq_error;
1867                 }
1868         }
1869
1870         napi_enable(&priv->napi);
1871         netif_start_queue(dev);
1872
1873         return 0;
1874
1875 lpiirq_error:
1876         if (priv->wol_irq != dev->irq)
1877                 free_irq(priv->wol_irq, dev);
1878 wolirq_error:
1879         free_irq(dev->irq, dev);
1880
1881 init_error:
1882         free_dma_desc_resources(priv);
1883 dma_desc_error:
1884         if (priv->phydev)
1885                 phy_disconnect(priv->phydev);
1886
1887         return ret;
1888 }
1889
1890 /**
1891  *  stmmac_release - close entry point of the driver
1892  *  @dev : device pointer.
1893  *  Description:
1894  *  This is the stop entry point of the driver.
1895  */
1896 static int stmmac_release(struct net_device *dev)
1897 {
1898         struct stmmac_priv *priv = netdev_priv(dev);
1899
1900         if (priv->eee_enabled)
1901                 del_timer_sync(&priv->eee_ctrl_timer);
1902
1903         /* Stop and disconnect the PHY */
1904         if (priv->phydev) {
1905                 phy_stop(priv->phydev);
1906                 phy_disconnect(priv->phydev);
1907                 priv->phydev = NULL;
1908         }
1909
1910         netif_stop_queue(dev);
1911
1912         napi_disable(&priv->napi);
1913
1914         del_timer_sync(&priv->txtimer);
1915
1916         /* Free the IRQ lines */
1917         free_irq(dev->irq, dev);
1918         if (priv->wol_irq != dev->irq)
1919                 free_irq(priv->wol_irq, dev);
1920         if (priv->lpi_irq > 0)
1921                 free_irq(priv->lpi_irq, dev);
1922
1923         /* Stop TX/RX DMA and clear the descriptors */
1924         priv->hw->dma->stop_tx(priv->ioaddr);
1925         priv->hw->dma->stop_rx(priv->ioaddr);
1926
1927         /* Release and free the Rx/Tx resources */
1928         free_dma_desc_resources(priv);
1929
1930         /* Disable the MAC Rx/Tx */
1931         stmmac_set_mac(priv->ioaddr, false);
1932
1933         netif_carrier_off(dev);
1934
1935 #ifdef CONFIG_DEBUG_FS
1936         stmmac_exit_fs(dev);
1937 #endif
1938
1939         stmmac_release_ptp(priv);
1940
1941         return 0;
1942 }
1943
1944 /**
1945  *  stmmac_xmit - Tx entry point of the driver
1946  *  @skb : the socket buffer
1947  *  @dev : device pointer
1948  *  Description : this is the tx entry point of the driver.
1949  *  It programs the chain or the ring and supports oversized frames
1950  *  and SG feature.
1951  */
1952 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
1953 {
1954         struct stmmac_priv *priv = netdev_priv(dev);
1955         unsigned int txsize = priv->dma_tx_size;
1956         int entry;
1957         int i, csum_insertion = 0, is_jumbo = 0;
1958         int nfrags = skb_shinfo(skb)->nr_frags;
1959         struct dma_desc *desc, *first;
1960         unsigned int nopaged_len = skb_headlen(skb);
1961         unsigned int enh_desc = priv->plat->enh_desc;
1962
1963         spin_lock(&priv->tx_lock);
1964
1965         if (unlikely(stmmac_tx_avail(priv) < nfrags + 1)) {
1966                 spin_unlock(&priv->tx_lock);
1967                 if (!netif_queue_stopped(dev)) {
1968                         netif_stop_queue(dev);
1969                         /* This is a hard error, log it. */
1970                         pr_err("%s: Tx Ring full when queue awake\n", __func__);
1971                 }
1972                 return NETDEV_TX_BUSY;
1973         }
1974
1975         if (priv->tx_path_in_lpi_mode)
1976                 stmmac_disable_eee_mode(priv);
1977
1978         entry = priv->cur_tx % txsize;
1979
1980         csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL);
1981
1982         if (priv->extend_desc)
1983                 desc = (struct dma_desc *)(priv->dma_etx + entry);
1984         else
1985                 desc = priv->dma_tx + entry;
1986
1987         first = desc;
1988
1989         /* To program the descriptors according to the size of the frame */
1990         if (enh_desc)
1991                 is_jumbo = priv->hw->mode->is_jumbo_frm(skb->len, enh_desc);
1992
1993         if (likely(!is_jumbo)) {
1994                 desc->des2 = dma_map_single(priv->device, skb->data,
1995                                             nopaged_len, DMA_TO_DEVICE);
1996                 if (dma_mapping_error(priv->device, desc->des2))
1997                         goto dma_map_err;
1998                 priv->tx_skbuff_dma[entry].buf = desc->des2;
1999                 priv->hw->desc->prepare_tx_desc(desc, 1, nopaged_len,
2000                                                 csum_insertion, priv->mode);
2001         } else {
2002                 desc = first;
2003                 entry = priv->hw->mode->jumbo_frm(priv, skb, csum_insertion);
2004                 if (unlikely(entry < 0))
2005                         goto dma_map_err;
2006         }
2007
2008         for (i = 0; i < nfrags; i++) {
2009                 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2010                 int len = skb_frag_size(frag);
2011
2012                 priv->tx_skbuff[entry] = NULL;
2013                 entry = (++priv->cur_tx) % txsize;
2014                 if (priv->extend_desc)
2015                         desc = (struct dma_desc *)(priv->dma_etx + entry);
2016                 else
2017                         desc = priv->dma_tx + entry;
2018
2019                 desc->des2 = skb_frag_dma_map(priv->device, frag, 0, len,
2020                                               DMA_TO_DEVICE);
2021                 if (dma_mapping_error(priv->device, desc->des2))
2022                         goto dma_map_err; /* should reuse desc w/o issues */
2023
2024                 priv->tx_skbuff_dma[entry].buf = desc->des2;
2025                 priv->tx_skbuff_dma[entry].map_as_page = true;
2026                 priv->hw->desc->prepare_tx_desc(desc, 0, len, csum_insertion,
2027                                                 priv->mode);
2028                 wmb();
2029                 priv->hw->desc->set_tx_owner(desc);
2030                 wmb();
2031         }
2032
2033         priv->tx_skbuff[entry] = skb;
2034
2035         /* Finalize the latest segment. */
2036         priv->hw->desc->close_tx_desc(desc);
2037
2038         wmb();
2039         /* According to the coalesce parameter the IC bit for the latest
2040          * segment could be reset and the timer re-started to invoke the
2041          * stmmac_tx function. This approach takes care about the fragments.
2042          */
2043         priv->tx_count_frames += nfrags + 1;
2044         if (priv->tx_coal_frames > priv->tx_count_frames) {
2045                 priv->hw->desc->clear_tx_ic(desc);
2046                 priv->xstats.tx_reset_ic_bit++;
2047                 mod_timer(&priv->txtimer,
2048                           STMMAC_COAL_TIMER(priv->tx_coal_timer));
2049         } else
2050                 priv->tx_count_frames = 0;
2051
2052         /* To avoid raise condition */
2053         priv->hw->desc->set_tx_owner(first);
2054         wmb();
2055
2056         priv->cur_tx++;
2057
2058         if (netif_msg_pktdata(priv)) {
2059                 pr_debug("%s: curr %d dirty=%d entry=%d, first=%p, nfrags=%d",
2060                         __func__, (priv->cur_tx % txsize),
2061                         (priv->dirty_tx % txsize), entry, first, nfrags);
2062
2063                 if (priv->extend_desc)
2064                         stmmac_display_ring((void *)priv->dma_etx, txsize, 1);
2065                 else
2066                         stmmac_display_ring((void *)priv->dma_tx, txsize, 0);
2067
2068                 pr_debug(">>> frame to be transmitted: ");
2069                 print_pkt(skb->data, skb->len);
2070         }
2071         if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) {
2072                 if (netif_msg_hw(priv))
2073                         pr_debug("%s: stop transmitted packets\n", __func__);
2074                 netif_stop_queue(dev);
2075         }
2076
2077         dev->stats.tx_bytes += skb->len;
2078
2079         if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
2080                      priv->hwts_tx_en)) {
2081                 /* declare that device is doing timestamping */
2082                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2083                 priv->hw->desc->enable_tx_timestamp(first);
2084         }
2085
2086         if (!priv->hwts_tx_en)
2087                 skb_tx_timestamp(skb);
2088
2089         netdev_sent_queue(dev, skb->len);
2090         priv->hw->dma->enable_dma_transmission(priv->ioaddr);
2091
2092         spin_unlock(&priv->tx_lock);
2093         return NETDEV_TX_OK;
2094
2095 dma_map_err:
2096         spin_unlock(&priv->tx_lock);
2097         dev_err(priv->device, "Tx dma map failed\n");
2098         dev_kfree_skb(skb);
2099         priv->dev->stats.tx_dropped++;
2100         return NETDEV_TX_OK;
2101 }
2102
2103 static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb)
2104 {
2105         struct ethhdr *ehdr;
2106         u16 vlanid;
2107
2108         if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) ==
2109             NETIF_F_HW_VLAN_CTAG_RX &&
2110             !__vlan_get_tag(skb, &vlanid)) {
2111                 /* pop the vlan tag */
2112                 ehdr = (struct ethhdr *)skb->data;
2113                 memmove(skb->data + VLAN_HLEN, ehdr, ETH_ALEN * 2);
2114                 skb_pull(skb, VLAN_HLEN);
2115                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlanid);
2116         }
2117 }
2118
2119
2120 /**
2121  * stmmac_rx_refill - refill used skb preallocated buffers
2122  * @priv: driver private structure
2123  * Description : this is to reallocate the skb for the reception process
2124  * that is based on zero-copy.
2125  */
2126 static inline void stmmac_rx_refill(struct stmmac_priv *priv)
2127 {
2128         unsigned int rxsize = priv->dma_rx_size;
2129         int bfsize = priv->dma_buf_sz;
2130
2131         for (; priv->cur_rx - priv->dirty_rx > 0; priv->dirty_rx++) {
2132                 unsigned int entry = priv->dirty_rx % rxsize;
2133                 struct dma_desc *p;
2134
2135                 if (priv->extend_desc)
2136                         p = (struct dma_desc *)(priv->dma_erx + entry);
2137                 else
2138                         p = priv->dma_rx + entry;
2139
2140                 if (likely(priv->rx_skbuff[entry] == NULL)) {
2141                         struct sk_buff *skb;
2142
2143                         skb = netdev_alloc_skb_ip_align(priv->dev, bfsize);
2144
2145                         if (unlikely(skb == NULL))
2146                                 break;
2147
2148                         priv->rx_skbuff[entry] = skb;
2149                         priv->rx_skbuff_dma[entry] =
2150                             dma_map_single(priv->device, skb->data, bfsize,
2151                                            DMA_FROM_DEVICE);
2152                         if (dma_mapping_error(priv->device,
2153                                               priv->rx_skbuff_dma[entry])) {
2154                                 dev_err(priv->device, "Rx dma map failed\n");
2155                                 dev_kfree_skb(skb);
2156                                 break;
2157                         }
2158                         p->des2 = priv->rx_skbuff_dma[entry];
2159
2160                         priv->hw->mode->refill_desc3(priv, p);
2161
2162                         if (netif_msg_rx_status(priv))
2163                                 pr_debug("\trefill entry #%d\n", entry);
2164                 }
2165                 wmb();
2166                 priv->hw->desc->set_rx_owner(p);
2167                 wmb();
2168         }
2169 }
2170
2171 /**
2172  * stmmac_rx - manage the receive process
2173  * @priv: driver private structure
2174  * @limit: napi bugget.
2175  * Description :  this the function called by the napi poll method.
2176  * It gets all the frames inside the ring.
2177  */
2178 static int stmmac_rx(struct stmmac_priv *priv, int limit)
2179 {
2180         unsigned int rxsize = priv->dma_rx_size;
2181         unsigned int entry = priv->cur_rx % rxsize;
2182         unsigned int next_entry;
2183         unsigned int count = 0;
2184         int coe = priv->hw->rx_csum;
2185
2186         if (netif_msg_rx_status(priv)) {
2187                 pr_debug("%s: descriptor ring:\n", __func__);
2188                 if (priv->extend_desc)
2189                         stmmac_display_ring((void *)priv->dma_erx, rxsize, 1);
2190                 else
2191                         stmmac_display_ring((void *)priv->dma_rx, rxsize, 0);
2192         }
2193         while (count < limit) {
2194                 int status;
2195                 struct dma_desc *p;
2196
2197                 if (priv->extend_desc)
2198                         p = (struct dma_desc *)(priv->dma_erx + entry);
2199                 else
2200                         p = priv->dma_rx + entry;
2201
2202                 if (priv->hw->desc->get_rx_owner(p))
2203                         break;
2204
2205                 count++;
2206
2207                 next_entry = (++priv->cur_rx) % rxsize;
2208                 if (priv->extend_desc)
2209                         prefetch(priv->dma_erx + next_entry);
2210                 else
2211                         prefetch(priv->dma_rx + next_entry);
2212
2213                 /* read the status of the incoming frame */
2214                 status = priv->hw->desc->rx_status(&priv->dev->stats,
2215                                                    &priv->xstats, p);
2216                 if ((priv->extend_desc) && (priv->hw->desc->rx_extended_status))
2217                         priv->hw->desc->rx_extended_status(&priv->dev->stats,
2218                                                            &priv->xstats,
2219                                                            priv->dma_erx +
2220                                                            entry);
2221                 if (unlikely(status == discard_frame)) {
2222                         priv->dev->stats.rx_errors++;
2223                         if (priv->hwts_rx_en && !priv->extend_desc) {
2224                                 /* DESC2 & DESC3 will be overwitten by device
2225                                  * with timestamp value, hence reinitialize
2226                                  * them in stmmac_rx_refill() function so that
2227                                  * device can reuse it.
2228                                  */
2229                                 priv->rx_skbuff[entry] = NULL;
2230                                 dma_unmap_single(priv->device,
2231                                                  priv->rx_skbuff_dma[entry],
2232                                                  priv->dma_buf_sz,
2233                                                  DMA_FROM_DEVICE);
2234                         }
2235                 } else {
2236                         struct sk_buff *skb;
2237                         int frame_len;
2238
2239                         frame_len = priv->hw->desc->get_rx_frame_len(p, coe);
2240
2241                         /*  check if frame_len fits the preallocated memory */
2242                         if (frame_len > priv->dma_buf_sz) {
2243                                 priv->dev->stats.rx_length_errors++;
2244                                 break;
2245                         }
2246
2247                         /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
2248                          * Type frames (LLC/LLC-SNAP)
2249                          */
2250                         if (unlikely(status != llc_snap))
2251                                 frame_len -= ETH_FCS_LEN;
2252
2253                         if (netif_msg_rx_status(priv)) {
2254                                 pr_debug("\tdesc: %p [entry %d] buff=0x%x\n",
2255                                          p, entry, p->des2);
2256                                 if (frame_len > ETH_FRAME_LEN)
2257                                         pr_debug("\tframe size %d, COE: %d\n",
2258                                                  frame_len, status);
2259                         }
2260                         skb = priv->rx_skbuff[entry];
2261                         if (unlikely(!skb)) {
2262                                 pr_err("%s: Inconsistent Rx descriptor chain\n",
2263                                        priv->dev->name);
2264                                 priv->dev->stats.rx_dropped++;
2265                                 break;
2266                         }
2267                         prefetch(skb->data - NET_IP_ALIGN);
2268                         priv->rx_skbuff[entry] = NULL;
2269
2270                         stmmac_get_rx_hwtstamp(priv, entry, skb);
2271
2272                         skb_put(skb, frame_len);
2273                         dma_unmap_single(priv->device,
2274                                          priv->rx_skbuff_dma[entry],
2275                                          priv->dma_buf_sz, DMA_FROM_DEVICE);
2276
2277                         if (netif_msg_pktdata(priv)) {
2278                                 pr_debug("frame received (%dbytes)", frame_len);
2279                                 print_pkt(skb->data, frame_len);
2280                         }
2281
2282                         stmmac_rx_vlan(priv->dev, skb);
2283
2284                         skb->protocol = eth_type_trans(skb, priv->dev);
2285
2286                         if (unlikely(!coe))
2287                                 skb_checksum_none_assert(skb);
2288                         else
2289                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2290
2291                         napi_gro_receive(&priv->napi, skb);
2292
2293                         priv->dev->stats.rx_packets++;
2294                         priv->dev->stats.rx_bytes += frame_len;
2295                 }
2296                 entry = next_entry;
2297         }
2298
2299         stmmac_rx_refill(priv);
2300
2301         priv->xstats.rx_pkt_n += count;
2302
2303         return count;
2304 }
2305
2306 /**
2307  *  stmmac_poll - stmmac poll method (NAPI)
2308  *  @napi : pointer to the napi structure.
2309  *  @budget : maximum number of packets that the current CPU can receive from
2310  *            all interfaces.
2311  *  Description :
2312  *  To look at the incoming frames and clear the tx resources.
2313  */
2314 static int stmmac_poll(struct napi_struct *napi, int budget)
2315 {
2316         struct stmmac_priv *priv = container_of(napi, struct stmmac_priv, napi);
2317         int work_done = 0;
2318
2319         priv->xstats.napi_poll++;
2320         stmmac_tx_clean(priv);
2321
2322         work_done = stmmac_rx(priv, budget);
2323         if (work_done < budget) {
2324                 napi_complete(napi);
2325                 stmmac_enable_dma_irq(priv);
2326         }
2327         return work_done;
2328 }
2329
2330 /**
2331  *  stmmac_tx_timeout
2332  *  @dev : Pointer to net device structure
2333  *  Description: this function is called when a packet transmission fails to
2334  *   complete within a reasonable time. The driver will mark the error in the
2335  *   netdev structure and arrange for the device to be reset to a sane state
2336  *   in order to transmit a new packet.
2337  */
2338 static void stmmac_tx_timeout(struct net_device *dev)
2339 {
2340         struct stmmac_priv *priv = netdev_priv(dev);
2341
2342         /* Clear Tx resources and restart transmitting again */
2343         stmmac_tx_err(priv);
2344 }
2345
2346 /**
2347  *  stmmac_set_rx_mode - entry point for multicast addressing
2348  *  @dev : pointer to the device structure
2349  *  Description:
2350  *  This function is a driver entry point which gets called by the kernel
2351  *  whenever multicast addresses must be enabled/disabled.
2352  *  Return value:
2353  *  void.
2354  */
2355 static void stmmac_set_rx_mode(struct net_device *dev)
2356 {
2357         struct stmmac_priv *priv = netdev_priv(dev);
2358
2359         priv->hw->mac->set_filter(priv->hw, dev);
2360 }
2361
2362 /**
2363  *  stmmac_change_mtu - entry point to change MTU size for the device.
2364  *  @dev : device pointer.
2365  *  @new_mtu : the new MTU size for the device.
2366  *  Description: the Maximum Transfer Unit (MTU) is used by the network layer
2367  *  to drive packet transmission. Ethernet has an MTU of 1500 octets
2368  *  (ETH_DATA_LEN). This value can be changed with ifconfig.
2369  *  Return value:
2370  *  0 on success and an appropriate (-)ve integer as defined in errno.h
2371  *  file on failure.
2372  */
2373 static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
2374 {
2375         struct stmmac_priv *priv = netdev_priv(dev);
2376         int max_mtu;
2377
2378         if (netif_running(dev)) {
2379                 pr_err("%s: must be stopped to change its MTU\n", dev->name);
2380                 return -EBUSY;
2381         }
2382
2383         if (priv->plat->enh_desc)
2384                 max_mtu = JUMBO_LEN;
2385         else
2386                 max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN);
2387
2388         if (priv->plat->maxmtu < max_mtu)
2389                 max_mtu = priv->plat->maxmtu;
2390
2391         if ((new_mtu < 46) || (new_mtu > max_mtu)) {
2392                 pr_err("%s: invalid MTU, max MTU is: %d\n", dev->name, max_mtu);
2393                 return -EINVAL;
2394         }
2395
2396         dev->mtu = new_mtu;
2397         netdev_update_features(dev);
2398
2399         return 0;
2400 }
2401
2402 static netdev_features_t stmmac_fix_features(struct net_device *dev,
2403                                              netdev_features_t features)
2404 {
2405         struct stmmac_priv *priv = netdev_priv(dev);
2406
2407         if (priv->plat->rx_coe == STMMAC_RX_COE_NONE)
2408                 features &= ~NETIF_F_RXCSUM;
2409
2410         if (!priv->plat->tx_coe)
2411                 features &= ~NETIF_F_ALL_CSUM;
2412
2413         /* Some GMAC devices have a bugged Jumbo frame support that
2414          * needs to have the Tx COE disabled for oversized frames
2415          * (due to limited buffer sizes). In this case we disable
2416          * the TX csum insertionin the TDES and not use SF.
2417          */
2418         if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN))
2419                 features &= ~NETIF_F_ALL_CSUM;
2420
2421         return features;
2422 }
2423
2424 static int stmmac_set_features(struct net_device *netdev,
2425                                netdev_features_t features)
2426 {
2427         struct stmmac_priv *priv = netdev_priv(netdev);
2428
2429         /* Keep the COE Type in case of csum is supporting */
2430         if (features & NETIF_F_RXCSUM)
2431                 priv->hw->rx_csum = priv->plat->rx_coe;
2432         else
2433                 priv->hw->rx_csum = 0;
2434         /* No check needed because rx_coe has been set before and it will be
2435          * fixed in case of issue.
2436          */
2437         priv->hw->mac->rx_ipc(priv->hw);
2438
2439         return 0;
2440 }
2441
2442 /**
2443  *  stmmac_interrupt - main ISR
2444  *  @irq: interrupt number.
2445  *  @dev_id: to pass the net device pointer.
2446  *  Description: this is the main driver interrupt service routine.
2447  *  It can call:
2448  *  o DMA service routine (to manage incoming frame reception and transmission
2449  *    status)
2450  *  o Core interrupts to manage: remote wake-up, management counter, LPI
2451  *    interrupts.
2452  */
2453 static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
2454 {
2455         struct net_device *dev = (struct net_device *)dev_id;
2456         struct stmmac_priv *priv = netdev_priv(dev);
2457
2458         if (priv->irq_wake)
2459                 pm_wakeup_event(priv->device, 0);
2460
2461         if (unlikely(!dev)) {
2462                 pr_err("%s: invalid dev pointer\n", __func__);
2463                 return IRQ_NONE;
2464         }
2465
2466         /* To handle GMAC own interrupts */
2467         if (priv->plat->has_gmac) {
2468                 int status = priv->hw->mac->host_irq_status(priv->hw,
2469                                                             &priv->xstats);
2470                 if (unlikely(status)) {
2471                         /* For LPI we need to save the tx status */
2472                         if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE)
2473                                 priv->tx_path_in_lpi_mode = true;
2474                         if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE)
2475                                 priv->tx_path_in_lpi_mode = false;
2476                 }
2477         }
2478
2479         /* To handle DMA interrupts */
2480         stmmac_dma_interrupt(priv);
2481
2482         return IRQ_HANDLED;
2483 }
2484
2485 #ifdef CONFIG_NET_POLL_CONTROLLER
2486 /* Polling receive - used by NETCONSOLE and other diagnostic tools
2487  * to allow network I/O with interrupts disabled.
2488  */
2489 static void stmmac_poll_controller(struct net_device *dev)
2490 {
2491         disable_irq(dev->irq);
2492         stmmac_interrupt(dev->irq, dev);
2493         enable_irq(dev->irq);
2494 }
2495 #endif
2496
2497 /**
2498  *  stmmac_ioctl - Entry point for the Ioctl
2499  *  @dev: Device pointer.
2500  *  @rq: An IOCTL specefic structure, that can contain a pointer to
2501  *  a proprietary structure used to pass information to the driver.
2502  *  @cmd: IOCTL command
2503  *  Description:
2504  *  Currently it supports the phy_mii_ioctl(...) and HW time stamping.
2505  */
2506 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2507 {
2508         struct stmmac_priv *priv = netdev_priv(dev);
2509         int ret = -EOPNOTSUPP;
2510
2511         if (!netif_running(dev))
2512                 return -EINVAL;
2513
2514         switch (cmd) {
2515         case SIOCGMIIPHY:
2516         case SIOCGMIIREG:
2517         case SIOCSMIIREG:
2518                 if (!priv->phydev)
2519                         return -EINVAL;
2520                 ret = phy_mii_ioctl(priv->phydev, rq, cmd);
2521                 break;
2522         case SIOCSHWTSTAMP:
2523                 ret = stmmac_hwtstamp_ioctl(dev, rq);
2524                 break;
2525         default:
2526                 break;
2527         }
2528
2529         return ret;
2530 }
2531
2532 #ifdef CONFIG_DEBUG_FS
2533 static struct dentry *stmmac_fs_dir;
2534
2535 static void sysfs_display_ring(void *head, int size, int extend_desc,
2536                                struct seq_file *seq)
2537 {
2538         int i;
2539         struct dma_extended_desc *ep = (struct dma_extended_desc *)head;
2540         struct dma_desc *p = (struct dma_desc *)head;
2541
2542         for (i = 0; i < size; i++) {
2543                 u64 x;
2544                 if (extend_desc) {
2545                         x = *(u64 *) ep;
2546                         seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
2547                                    i, (unsigned int)virt_to_phys(ep),
2548                                    (unsigned int)x, (unsigned int)(x >> 32),
2549                                    ep->basic.des2, ep->basic.des3);
2550                         ep++;
2551                 } else {
2552                         x = *(u64 *) p;
2553                         seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
2554                                    i, (unsigned int)virt_to_phys(ep),
2555                                    (unsigned int)x, (unsigned int)(x >> 32),
2556                                    p->des2, p->des3);
2557                         p++;
2558                 }
2559                 seq_printf(seq, "\n");
2560         }
2561 }
2562
2563 static int stmmac_sysfs_ring_read(struct seq_file *seq, void *v)
2564 {
2565         struct net_device *dev = seq->private;
2566         struct stmmac_priv *priv = netdev_priv(dev);
2567         unsigned int txsize = priv->dma_tx_size;
2568         unsigned int rxsize = priv->dma_rx_size;
2569
2570         if (priv->extend_desc) {
2571                 seq_printf(seq, "Extended RX descriptor ring:\n");
2572                 sysfs_display_ring((void *)priv->dma_erx, rxsize, 1, seq);
2573                 seq_printf(seq, "Extended TX descriptor ring:\n");
2574                 sysfs_display_ring((void *)priv->dma_etx, txsize, 1, seq);
2575         } else {
2576                 seq_printf(seq, "RX descriptor ring:\n");
2577                 sysfs_display_ring((void *)priv->dma_rx, rxsize, 0, seq);
2578                 seq_printf(seq, "TX descriptor ring:\n");
2579                 sysfs_display_ring((void *)priv->dma_tx, txsize, 0, seq);
2580         }
2581
2582         return 0;
2583 }
2584
2585 static int stmmac_sysfs_ring_open(struct inode *inode, struct file *file)
2586 {
2587         return single_open(file, stmmac_sysfs_ring_read, inode->i_private);
2588 }
2589
2590 static const struct file_operations stmmac_rings_status_fops = {
2591         .owner = THIS_MODULE,
2592         .open = stmmac_sysfs_ring_open,
2593         .read = seq_read,
2594         .llseek = seq_lseek,
2595         .release = single_release,
2596 };
2597
2598 static int stmmac_sysfs_dma_cap_read(struct seq_file *seq, void *v)
2599 {
2600         struct net_device *dev = seq->private;
2601         struct stmmac_priv *priv = netdev_priv(dev);
2602
2603         if (!priv->hw_cap_support) {
2604                 seq_printf(seq, "DMA HW features not supported\n");
2605                 return 0;
2606         }
2607
2608         seq_printf(seq, "==============================\n");
2609         seq_printf(seq, "\tDMA HW features\n");
2610         seq_printf(seq, "==============================\n");
2611
2612         seq_printf(seq, "\t10/100 Mbps %s\n",
2613                    (priv->dma_cap.mbps_10_100) ? "Y" : "N");
2614         seq_printf(seq, "\t1000 Mbps %s\n",
2615                    (priv->dma_cap.mbps_1000) ? "Y" : "N");
2616         seq_printf(seq, "\tHalf duple %s\n",
2617                    (priv->dma_cap.half_duplex) ? "Y" : "N");
2618         seq_printf(seq, "\tHash Filter: %s\n",
2619                    (priv->dma_cap.hash_filter) ? "Y" : "N");
2620         seq_printf(seq, "\tMultiple MAC address registers: %s\n",
2621                    (priv->dma_cap.multi_addr) ? "Y" : "N");
2622         seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfatces): %s\n",
2623                    (priv->dma_cap.pcs) ? "Y" : "N");
2624         seq_printf(seq, "\tSMA (MDIO) Interface: %s\n",
2625                    (priv->dma_cap.sma_mdio) ? "Y" : "N");
2626         seq_printf(seq, "\tPMT Remote wake up: %s\n",
2627                    (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N");
2628         seq_printf(seq, "\tPMT Magic Frame: %s\n",
2629                    (priv->dma_cap.pmt_magic_frame) ? "Y" : "N");
2630         seq_printf(seq, "\tRMON module: %s\n",
2631                    (priv->dma_cap.rmon) ? "Y" : "N");
2632         seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n",
2633                    (priv->dma_cap.time_stamp) ? "Y" : "N");
2634         seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp:%s\n",
2635                    (priv->dma_cap.atime_stamp) ? "Y" : "N");
2636         seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE) %s\n",
2637                    (priv->dma_cap.eee) ? "Y" : "N");
2638         seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N");
2639         seq_printf(seq, "\tChecksum Offload in TX: %s\n",
2640                    (priv->dma_cap.tx_coe) ? "Y" : "N");
2641         seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n",
2642                    (priv->dma_cap.rx_coe_type1) ? "Y" : "N");
2643         seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n",
2644                    (priv->dma_cap.rx_coe_type2) ? "Y" : "N");
2645         seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n",
2646                    (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N");
2647         seq_printf(seq, "\tNumber of Additional RX channel: %d\n",
2648                    priv->dma_cap.number_rx_channel);
2649         seq_printf(seq, "\tNumber of Additional TX channel: %d\n",
2650                    priv->dma_cap.number_tx_channel);
2651         seq_printf(seq, "\tEnhanced descriptors: %s\n",
2652                    (priv->dma_cap.enh_desc) ? "Y" : "N");
2653
2654         return 0;
2655 }
2656
2657 static int stmmac_sysfs_dma_cap_open(struct inode *inode, struct file *file)
2658 {
2659         return single_open(file, stmmac_sysfs_dma_cap_read, inode->i_private);
2660 }
2661
2662 static const struct file_operations stmmac_dma_cap_fops = {
2663         .owner = THIS_MODULE,
2664         .open = stmmac_sysfs_dma_cap_open,
2665         .read = seq_read,
2666         .llseek = seq_lseek,
2667         .release = single_release,
2668 };
2669
2670 static int stmmac_init_fs(struct net_device *dev)
2671 {
2672         struct stmmac_priv *priv = netdev_priv(dev);
2673
2674         /* Create per netdev entries */
2675         priv->dbgfs_dir = debugfs_create_dir(dev->name, stmmac_fs_dir);
2676
2677         if (!priv->dbgfs_dir || IS_ERR(priv->dbgfs_dir)) {
2678                 pr_err("ERROR %s/%s, debugfs create directory failed\n",
2679                        STMMAC_RESOURCE_NAME, dev->name);
2680
2681                 return -ENOMEM;
2682         }
2683
2684         /* Entry to report DMA RX/TX rings */
2685         priv->dbgfs_rings_status =
2686                 debugfs_create_file("descriptors_status", S_IRUGO,
2687                                     priv->dbgfs_dir, dev,
2688                                     &stmmac_rings_status_fops);
2689
2690         if (!priv->dbgfs_rings_status || IS_ERR(priv->dbgfs_rings_status)) {
2691                 pr_info("ERROR creating stmmac ring debugfs file\n");
2692                 debugfs_remove_recursive(priv->dbgfs_dir);
2693
2694                 return -ENOMEM;
2695         }
2696
2697         /* Entry to report the DMA HW features */
2698         priv->dbgfs_dma_cap = debugfs_create_file("dma_cap", S_IRUGO,
2699                                             priv->dbgfs_dir,
2700                                             dev, &stmmac_dma_cap_fops);
2701
2702         if (!priv->dbgfs_dma_cap || IS_ERR(priv->dbgfs_dma_cap)) {
2703                 pr_info("ERROR creating stmmac MMC debugfs file\n");
2704                 debugfs_remove_recursive(priv->dbgfs_dir);
2705
2706                 return -ENOMEM;
2707         }
2708
2709         return 0;
2710 }
2711
2712 static void stmmac_exit_fs(struct net_device *dev)
2713 {
2714         struct stmmac_priv *priv = netdev_priv(dev);
2715
2716         debugfs_remove_recursive(priv->dbgfs_dir);
2717 }
2718 #endif /* CONFIG_DEBUG_FS */
2719
2720 static const struct net_device_ops stmmac_netdev_ops = {
2721         .ndo_open = stmmac_open,
2722         .ndo_start_xmit = stmmac_xmit,
2723         .ndo_stop = stmmac_release,
2724         .ndo_change_mtu = stmmac_change_mtu,
2725         .ndo_fix_features = stmmac_fix_features,
2726         .ndo_set_features = stmmac_set_features,
2727         .ndo_set_rx_mode = stmmac_set_rx_mode,
2728         .ndo_tx_timeout = stmmac_tx_timeout,
2729         .ndo_do_ioctl = stmmac_ioctl,
2730 #ifdef CONFIG_NET_POLL_CONTROLLER
2731         .ndo_poll_controller = stmmac_poll_controller,
2732 #endif
2733         .ndo_set_mac_address = eth_mac_addr,
2734 };
2735
2736 /**
2737  *  stmmac_hw_init - Init the MAC device
2738  *  @priv: driver private structure
2739  *  Description: this function is to configure the MAC device according to
2740  *  some platform parameters or the HW capability register. It prepares the
2741  *  driver to use either ring or chain modes and to setup either enhanced or
2742  *  normal descriptors.
2743  */
2744 static int stmmac_hw_init(struct stmmac_priv *priv)
2745 {
2746         struct mac_device_info *mac;
2747
2748         /* Identify the MAC HW device */
2749         if (priv->plat->has_gmac) {
2750                 priv->dev->priv_flags |= IFF_UNICAST_FLT;
2751                 mac = dwmac1000_setup(priv->ioaddr,
2752                                       priv->plat->multicast_filter_bins,
2753                                       priv->plat->unicast_filter_entries);
2754         } else {
2755                 mac = dwmac100_setup(priv->ioaddr);
2756         }
2757         if (!mac)
2758                 return -ENOMEM;
2759
2760         priv->hw = mac;
2761
2762         /* Get and dump the chip ID */
2763         priv->synopsys_id = stmmac_get_synopsys_id(priv);
2764
2765         /* To use the chained or ring mode */
2766         if (chain_mode) {
2767                 priv->hw->mode = &chain_mode_ops;
2768                 pr_info(" Chain mode enabled\n");
2769                 priv->mode = STMMAC_CHAIN_MODE;
2770         } else {
2771                 priv->hw->mode = &ring_mode_ops;
2772                 pr_info(" Ring mode enabled\n");
2773                 priv->mode = STMMAC_RING_MODE;
2774         }
2775
2776         /* Get the HW capability (new GMAC newer than 3.50a) */
2777         priv->hw_cap_support = stmmac_get_hw_features(priv);
2778         if (priv->hw_cap_support) {
2779                 pr_info(" DMA HW capability register supported");
2780
2781                 /* We can override some gmac/dma configuration fields: e.g.
2782                  * enh_desc, tx_coe (e.g. that are passed through the
2783                  * platform) with the values from the HW capability
2784                  * register (if supported).
2785                  */
2786                 priv->plat->enh_desc = priv->dma_cap.enh_desc;
2787                 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up;
2788
2789                 /* TXCOE doesn't work in thresh DMA mode */
2790                 if (priv->plat->force_thresh_dma_mode)
2791                         priv->plat->tx_coe = 0;
2792                 else
2793                         priv->plat->tx_coe = priv->dma_cap.tx_coe;
2794
2795                 if (priv->dma_cap.rx_coe_type2)
2796                         priv->plat->rx_coe = STMMAC_RX_COE_TYPE2;
2797                 else if (priv->dma_cap.rx_coe_type1)
2798                         priv->plat->rx_coe = STMMAC_RX_COE_TYPE1;
2799
2800         } else
2801                 pr_info(" No HW DMA feature register supported");
2802
2803         /* To use alternate (extended) or normal descriptor structures */
2804         stmmac_selec_desc_mode(priv);
2805
2806         if (priv->plat->rx_coe) {
2807                 priv->hw->rx_csum = priv->plat->rx_coe;
2808                 pr_info(" RX Checksum Offload Engine supported (type %d)\n",
2809                         priv->plat->rx_coe);
2810         }
2811         if (priv->plat->tx_coe)
2812                 pr_info(" TX Checksum insertion supported\n");
2813
2814         if (priv->plat->pmt) {
2815                 pr_info(" Wake-Up On Lan supported\n");
2816                 device_set_wakeup_capable(priv->device, 1);
2817         }
2818
2819         return 0;
2820 }
2821
2822 /**
2823  * stmmac_dvr_probe
2824  * @device: device pointer
2825  * @plat_dat: platform data pointer
2826  * @res: stmmac resource pointer
2827  * Description: this is the main probe function used to
2828  * call the alloc_etherdev, allocate the priv structure.
2829  * Return:
2830  * returns 0 on success, otherwise errno.
2831  */
2832 int stmmac_dvr_probe(struct device *device,
2833                      struct plat_stmmacenet_data *plat_dat,
2834                      struct stmmac_resources *res)
2835 {
2836         int ret = 0;
2837         struct net_device *ndev = NULL;
2838         struct stmmac_priv *priv;
2839
2840         ndev = alloc_etherdev(sizeof(struct stmmac_priv));
2841         if (!ndev)
2842                 return -ENOMEM;
2843
2844         SET_NETDEV_DEV(ndev, device);
2845
2846         priv = netdev_priv(ndev);
2847         priv->device = device;
2848         priv->dev = ndev;
2849
2850         stmmac_set_ethtool_ops(ndev);
2851         priv->pause = pause;
2852         priv->plat = plat_dat;
2853         priv->ioaddr = res->addr;
2854         priv->dev->base_addr = (unsigned long)res->addr;
2855
2856         priv->dev->irq = res->irq;
2857         priv->wol_irq = res->wol_irq;
2858         priv->lpi_irq = res->lpi_irq;
2859
2860         if (res->mac)
2861                 memcpy(priv->dev->dev_addr, res->mac, ETH_ALEN);
2862
2863         dev_set_drvdata(device, priv->dev);
2864
2865         /* Verify driver arguments */
2866         stmmac_verify_args();
2867
2868         /* Override with kernel parameters if supplied XXX CRS XXX
2869          * this needs to have multiple instances
2870          */
2871         if ((phyaddr >= 0) && (phyaddr <= 31))
2872                 priv->plat->phy_addr = phyaddr;
2873
2874         priv->stmmac_clk = devm_clk_get(priv->device, STMMAC_RESOURCE_NAME);
2875         if (IS_ERR(priv->stmmac_clk)) {
2876                 dev_warn(priv->device, "%s: warning: cannot get CSR clock\n",
2877                          __func__);
2878                 /* If failed to obtain stmmac_clk and specific clk_csr value
2879                  * is NOT passed from the platform, probe fail.
2880                  */
2881                 if (!priv->plat->clk_csr) {
2882                         ret = PTR_ERR(priv->stmmac_clk);
2883                         goto error_clk_get;
2884                 } else {
2885                         priv->stmmac_clk = NULL;
2886                 }
2887         }
2888         clk_prepare_enable(priv->stmmac_clk);
2889
2890         //priv->pclk = devm_clk_get(priv->device, "pclk");
2891         priv->pclk = devm_clk_get(priv->device, "pclk_mac");
2892         if (IS_ERR(priv->pclk)) {
2893                 if (PTR_ERR(priv->pclk) == -EPROBE_DEFER) {
2894                         ret = -EPROBE_DEFER;
2895                         goto error_pclk_get;
2896                 }
2897                 priv->pclk = NULL;
2898         }
2899         clk_prepare_enable(priv->pclk);
2900
2901         priv->stmmac_rst = devm_reset_control_get(priv->device,
2902                                                   STMMAC_RESOURCE_NAME);
2903         if (IS_ERR(priv->stmmac_rst)) {
2904                 if (PTR_ERR(priv->stmmac_rst) == -EPROBE_DEFER) {
2905                         ret = -EPROBE_DEFER;
2906                         goto error_hw_init;
2907                 }
2908                 dev_info(priv->device, "no reset control found\n");
2909                 priv->stmmac_rst = NULL;
2910         }
2911         if (priv->stmmac_rst)
2912                 reset_control_deassert(priv->stmmac_rst);
2913
2914         /* Init MAC and get the capabilities */
2915         ret = stmmac_hw_init(priv);
2916         if (ret)
2917                 goto error_hw_init;
2918
2919         ndev->netdev_ops = &stmmac_netdev_ops;
2920
2921         ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2922                             NETIF_F_RXCSUM;
2923         ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA;
2924         ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
2925 #ifdef STMMAC_VLAN_TAG_USED
2926         /* Both mac100 and gmac support receive VLAN tag detection */
2927         ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
2928 #endif
2929         priv->msg_enable = netif_msg_init(debug, default_msg_level);
2930
2931         if (flow_ctrl)
2932                 priv->flow_ctrl = FLOW_AUTO;    /* RX/TX pause on */
2933
2934         /* Rx Watchdog is available in the COREs newer than the 3.40.
2935          * In some case, for example on bugged HW this feature
2936          * has to be disable and this can be done by passing the
2937          * riwt_off field from the platform.
2938          */
2939         if ((priv->synopsys_id >= DWMAC_CORE_3_50) && (!priv->plat->riwt_off)) {
2940                 priv->use_riwt = 1;
2941                 pr_info(" Enable RX Mitigation via HW Watchdog Timer\n");
2942         }
2943
2944         netif_napi_add(ndev, &priv->napi, stmmac_poll, 64);
2945
2946         spin_lock_init(&priv->lock);
2947         spin_lock_init(&priv->tx_lock);
2948
2949         /* If a specific clk_csr value is passed from the platform
2950          * this means that the CSR Clock Range selection cannot be
2951          * changed at run-time and it is fixed. Viceversa the driver'll try to
2952          * set the MDC clock dynamically according to the csr actual
2953          * clock input.
2954          */
2955         if (!priv->plat->clk_csr)
2956                 stmmac_clk_csr_set(priv);
2957         else
2958                 priv->clk_csr = priv->plat->clk_csr;
2959
2960         stmmac_check_pcs_mode(priv);
2961
2962         if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI &&
2963             priv->pcs != STMMAC_PCS_RTBI) {
2964                 /* MDIO bus Registration */
2965                 ret = stmmac_mdio_register(ndev);
2966                 if (ret < 0) {
2967                         pr_debug("%s: MDIO bus (id: %d) registration failed",
2968                                  __func__, priv->plat->bus_id);
2969                         goto error_mdio_register;
2970                 }
2971         }
2972
2973         ret = register_netdev(ndev);
2974         if (ret) {
2975                 netdev_err(priv->dev, "%s: ERROR %i registering the device\n",
2976                            __func__, ret);
2977                 goto error_netdev_register;
2978         }
2979
2980         return ret;
2981
2982 error_netdev_register:
2983         if (priv->pcs != STMMAC_PCS_RGMII &&
2984             priv->pcs != STMMAC_PCS_TBI &&
2985             priv->pcs != STMMAC_PCS_RTBI)
2986                 stmmac_mdio_unregister(ndev);
2987 error_mdio_register:
2988         netif_napi_del(&priv->napi);
2989 error_hw_init:
2990         clk_disable_unprepare(priv->pclk);
2991 error_pclk_get:
2992         clk_disable_unprepare(priv->stmmac_clk);
2993 error_clk_get:
2994         free_netdev(ndev);
2995
2996         return ret;
2997 }
2998 EXPORT_SYMBOL_GPL(stmmac_dvr_probe);
2999
3000 /**
3001  * stmmac_dvr_remove
3002  * @ndev: net device pointer
3003  * Description: this function resets the TX/RX processes, disables the MAC RX/TX
3004  * changes the link status, releases the DMA descriptor rings.
3005  */
3006 int stmmac_dvr_remove(struct net_device *ndev)
3007 {
3008         struct stmmac_priv *priv = netdev_priv(ndev);
3009
3010         pr_info("%s:\n\tremoving driver", __func__);
3011
3012         priv->hw->dma->stop_rx(priv->ioaddr);
3013         priv->hw->dma->stop_tx(priv->ioaddr);
3014
3015         stmmac_set_mac(priv->ioaddr, false);
3016         netif_carrier_off(ndev);
3017         unregister_netdev(ndev);
3018         if (priv->stmmac_rst)
3019                 reset_control_assert(priv->stmmac_rst);
3020         clk_disable_unprepare(priv->pclk);
3021         clk_disable_unprepare(priv->stmmac_clk);
3022         if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI &&
3023             priv->pcs != STMMAC_PCS_RTBI)
3024                 stmmac_mdio_unregister(ndev);
3025         free_netdev(ndev);
3026
3027         return 0;
3028 }
3029 EXPORT_SYMBOL_GPL(stmmac_dvr_remove);
3030
3031 /**
3032  * stmmac_suspend - suspend callback
3033  * @ndev: net device pointer
3034  * Description: this is the function to suspend the device and it is called
3035  * by the platform driver to stop the network queue, release the resources,
3036  * program the PMT register (for WoL), clean and release driver resources.
3037  */
3038 int stmmac_suspend(struct net_device *ndev)
3039 {
3040         struct stmmac_priv *priv = netdev_priv(ndev);
3041         unsigned long flags;
3042
3043         if (!ndev || !netif_running(ndev))
3044                 return 0;
3045
3046         if (priv->phydev)
3047                 phy_stop(priv->phydev);
3048
3049         netif_device_detach(ndev);
3050         netif_stop_queue(ndev);
3051
3052         napi_disable(&priv->napi);
3053
3054         spin_lock_irqsave(&priv->lock, flags);
3055
3056         /* Stop TX/RX DMA */
3057         priv->hw->dma->stop_tx(priv->ioaddr);
3058         priv->hw->dma->stop_rx(priv->ioaddr);
3059
3060         /* Enable Power down mode by programming the PMT regs */
3061         if (device_may_wakeup(priv->device)) {
3062                 priv->hw->mac->pmt(priv->hw, priv->wolopts);
3063                 priv->irq_wake = 1;
3064         } else {
3065                 stmmac_set_mac(priv->ioaddr, false);
3066                 pinctrl_pm_select_sleep_state(priv->device);
3067                 /* Disable clock in case of PWM is off */
3068                 clk_disable(priv->pclk);
3069                 clk_disable(priv->stmmac_clk);
3070         }
3071         spin_unlock_irqrestore(&priv->lock, flags);
3072
3073         priv->oldlink = 0;
3074         priv->speed = 0;
3075         priv->oldduplex = -1;
3076         return 0;
3077 }
3078 EXPORT_SYMBOL_GPL(stmmac_suspend);
3079
3080 /**
3081  * stmmac_resume - resume callback
3082  * @ndev: net device pointer
3083  * Description: when resume this function is invoked to setup the DMA and CORE
3084  * in a usable state.
3085  */
3086 int stmmac_resume(struct net_device *ndev)
3087 {
3088         struct stmmac_priv *priv = netdev_priv(ndev);
3089         unsigned long flags;
3090
3091         if (!netif_running(ndev))
3092                 return 0;
3093
3094         /* Power Down bit, into the PM register, is cleared
3095          * automatically as soon as a magic packet or a Wake-up frame
3096          * is received. Anyway, it's better to manually clear
3097          * this bit because it can generate problems while resuming
3098          * from another devices (e.g. serial console).
3099          */
3100         if (device_may_wakeup(priv->device)) {
3101                 spin_lock_irqsave(&priv->lock, flags);
3102                 priv->hw->mac->pmt(priv->hw, 0);
3103                 spin_unlock_irqrestore(&priv->lock, flags);
3104                 priv->irq_wake = 0;
3105         } else {
3106                 pinctrl_pm_select_default_state(priv->device);
3107                 /* enable the clk prevously disabled */
3108                 clk_enable(priv->stmmac_clk);
3109                 clk_enable(priv->pclk);
3110                 /* reset the phy so that it's ready */
3111                 if (priv->mii)
3112                         stmmac_mdio_reset(priv->mii);
3113         }
3114
3115         spin_lock_irqsave(&priv->lock, flags);
3116
3117         priv->cur_rx = 0;
3118         priv->dirty_rx = 0;
3119         priv->dirty_tx = 0;
3120         priv->cur_tx = 0;
3121         stmmac_clear_descriptors(priv);
3122
3123         stmmac_hw_setup(ndev, false);
3124         stmmac_init_tx_coalesce(priv);
3125         stmmac_set_rx_mode(ndev);
3126
3127         napi_enable(&priv->napi);
3128
3129         netif_start_queue(ndev);
3130
3131         netif_device_attach(ndev);
3132
3133         spin_unlock_irqrestore(&priv->lock, flags);
3134
3135         if (priv->phydev)
3136                 phy_start(priv->phydev);
3137
3138         return 0;
3139 }
3140 EXPORT_SYMBOL_GPL(stmmac_resume);
3141
3142 #ifndef MODULE
3143 static int __init stmmac_cmdline_opt(char *str)
3144 {
3145         char *opt;
3146
3147         if (!str || !*str)
3148                 return -EINVAL;
3149         while ((opt = strsep(&str, ",")) != NULL) {
3150                 if (!strncmp(opt, "debug:", 6)) {
3151                         if (kstrtoint(opt + 6, 0, &debug))
3152                                 goto err;
3153                 } else if (!strncmp(opt, "phyaddr:", 8)) {
3154                         if (kstrtoint(opt + 8, 0, &phyaddr))
3155                                 goto err;
3156                 } else if (!strncmp(opt, "dma_txsize:", 11)) {
3157                         if (kstrtoint(opt + 11, 0, &dma_txsize))
3158                                 goto err;
3159                 } else if (!strncmp(opt, "dma_rxsize:", 11)) {
3160                         if (kstrtoint(opt + 11, 0, &dma_rxsize))
3161                                 goto err;
3162                 } else if (!strncmp(opt, "buf_sz:", 7)) {
3163                         if (kstrtoint(opt + 7, 0, &buf_sz))
3164                                 goto err;
3165                 } else if (!strncmp(opt, "tc:", 3)) {
3166                         if (kstrtoint(opt + 3, 0, &tc))
3167                                 goto err;
3168                 } else if (!strncmp(opt, "watchdog:", 9)) {
3169                         if (kstrtoint(opt + 9, 0, &watchdog))
3170                                 goto err;
3171                 } else if (!strncmp(opt, "flow_ctrl:", 10)) {
3172                         if (kstrtoint(opt + 10, 0, &flow_ctrl))
3173                                 goto err;
3174                 } else if (!strncmp(opt, "pause:", 6)) {
3175                         if (kstrtoint(opt + 6, 0, &pause))
3176                                 goto err;
3177                 } else if (!strncmp(opt, "eee_timer:", 10)) {
3178                         if (kstrtoint(opt + 10, 0, &eee_timer))
3179                                 goto err;
3180                 } else if (!strncmp(opt, "chain_mode:", 11)) {
3181                         if (kstrtoint(opt + 11, 0, &chain_mode))
3182                                 goto err;
3183                 }
3184         }
3185         return 0;
3186
3187 err:
3188         pr_err("%s: ERROR broken module parameter conversion", __func__);
3189         return -EINVAL;
3190 }
3191
3192 __setup("stmmaceth=", stmmac_cmdline_opt);
3193 #endif /* MODULE */
3194
3195 static int __init stmmac_init(void)
3196 {
3197 #ifdef CONFIG_DEBUG_FS
3198         /* Create debugfs main directory if it doesn't exist yet */
3199         if (!stmmac_fs_dir) {
3200                 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL);
3201
3202                 if (!stmmac_fs_dir || IS_ERR(stmmac_fs_dir)) {
3203                         pr_err("ERROR %s, debugfs create directory failed\n",
3204                                STMMAC_RESOURCE_NAME);
3205
3206                         return -ENOMEM;
3207                 }
3208         }
3209 #endif
3210
3211         return 0;
3212 }
3213
3214 static void __exit stmmac_exit(void)
3215 {
3216 #ifdef CONFIG_DEBUG_FS
3217         debugfs_remove_recursive(stmmac_fs_dir);
3218 #endif
3219 }
3220
3221 module_init(stmmac_init)
3222 module_exit(stmmac_exit)
3223
3224 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver");
3225 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
3226 MODULE_LICENSE("GPL");