drivers/net/ethernet/stmicro/stmmac/stmmac_main.c

   1 /*******************************************************************************
   2   This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
   3   ST Ethernet IPs are built around a Synopsys IP Core.
   4
   5         Copyright(C) 2007-2011 STMicroelectronics Ltd
   6
   7   This program is free software; you can redistribute it and/or modify it
   8   under the terms and conditions of the GNU General Public License,
   9   version 2, as published by the Free Software Foundation.
  10
  11   This program is distributed in the hope it will be useful, but WITHOUT
  12   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14   more details.
  15
  16   You should have received a copy of the GNU General Public License along with
  17   this program; if not, write to the Free Software Foundation, Inc.,
  18   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  19
  20   The full GNU General Public License is included in this distribution in
  21   the file called "COPYING".
  22
  23   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
  24
  25   Documentation available at:
  26         http://www.stlinux.com
  27   Support available at:
  28         https://bugzilla.stlinux.com/
  29 *******************************************************************************/
  30
  31 #include <linux/clk.h>
  32 #include <linux/kernel.h>
  33 #include <linux/interrupt.h>
  34 #include <linux/ip.h>
  35 #include <linux/tcp.h>
  36 #include <linux/skbuff.h>
  37 #include <linux/ethtool.h>
  38 #include <linux/if_ether.h>
  39 #include <linux/crc32.h>
  40 #include <linux/mii.h>
  41 #include <linux/if.h>
  42 #include <linux/if_vlan.h>
  43 #include <linux/dma-mapping.h>
  44 #include <linux/slab.h>
  45 #include <linux/prefetch.h>
  46 #ifdef CONFIG_STMMAC_DEBUG_FS
  47 #include <linux/debugfs.h>
  48 #include <linux/seq_file.h>
  49 #endif
  50 #include "stmmac.h"
  51
  52 #undef STMMAC_DEBUG
  53 /*#define STMMAC_DEBUG*/
  54 #ifdef STMMAC_DEBUG
  55 #define DBG(nlevel, klevel, fmt, args...) \
  56                 ((void)(netif_msg_##nlevel(priv) && \
  57                 printk(KERN_##klevel fmt, ## args)))
  58 #else
  59 #define DBG(nlevel, klevel, fmt, args...) do { } while (0)
  60 #endif
  61
  62 #undef STMMAC_RX_DEBUG
  63 /*#define STMMAC_RX_DEBUG*/
  64 #ifdef STMMAC_RX_DEBUG
  65 #define RX_DBG(fmt, args...)  printk(fmt, ## args)
  66 #else
  67 #define RX_DBG(fmt, args...)  do { } while (0)
  68 #endif
  69
  70 #undef STMMAC_XMIT_DEBUG
  71 /*#define STMMAC_XMIT_DEBUG*/
  72 #ifdef STMMAC_XMIT_DEBUG
  73 #define TX_DBG(fmt, args...)  printk(fmt, ## args)
  74 #else
  75 #define TX_DBG(fmt, args...)  do { } while (0)
  76 #endif
  77
  78 #define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x)
  79 #define JUMBO_LEN       9000
  80
  81 /* Module parameters */
  82 #define TX_TIMEO 5000 /* default 5 seconds */
  83 static int watchdog = TX_TIMEO;
  84 module_param(watchdog, int, S_IRUGO | S_IWUSR);
  85 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds");
  86
  87 static int debug = -1;          /* -1: default, 0: no output, 16:  all */
  88 module_param(debug, int, S_IRUGO | S_IWUSR);
  89 MODULE_PARM_DESC(debug, "Message Level (0: no output, 16: all)");
  90
  91 int phyaddr = -1;
  92 module_param(phyaddr, int, S_IRUGO);
  93 MODULE_PARM_DESC(phyaddr, "Physical device address");
  94
  95 #define DMA_TX_SIZE 256
  96 static int dma_txsize = DMA_TX_SIZE;
  97 module_param(dma_txsize, int, S_IRUGO | S_IWUSR);
  98 MODULE_PARM_DESC(dma_txsize, "Number of descriptors in the TX list");
  99
 100 #define DMA_RX_SIZE 256
 101 static int dma_rxsize = DMA_RX_SIZE;
 102 module_param(dma_rxsize, int, S_IRUGO | S_IWUSR);
 103 MODULE_PARM_DESC(dma_rxsize, "Number of descriptors in the RX list");
 104
 105 static int flow_ctrl = FLOW_OFF;
 106 module_param(flow_ctrl, int, S_IRUGO | S_IWUSR);
 107 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]");
 108
 109 static int pause = PAUSE_TIME;
 110 module_param(pause, int, S_IRUGO | S_IWUSR);
 111 MODULE_PARM_DESC(pause, "Flow Control Pause Time");
 112
 113 #define TC_DEFAULT 64
 114 static int tc = TC_DEFAULT;
 115 module_param(tc, int, S_IRUGO | S_IWUSR);
 116 MODULE_PARM_DESC(tc, "DMA threshold control value");
 117
 118 #define DMA_BUFFER_SIZE BUF_SIZE_2KiB
 119 static int buf_sz = DMA_BUFFER_SIZE;
 120 module_param(buf_sz, int, S_IRUGO | S_IWUSR);
 121 MODULE_PARM_DESC(buf_sz, "DMA buffer size");
 122
 123 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
 124                                       NETIF_MSG_LINK | NETIF_MSG_IFUP |
 125                                       NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);
 126
 127 #define STMMAC_DEFAULT_LPI_TIMER        1000
 128 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER;
 129 module_param(eee_timer, int, S_IRUGO | S_IWUSR);
 130 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec");
 131 #define STMMAC_LPI_TIMER(x) (jiffies + msecs_to_jiffies(x))
 132
 133 /* By default the driver will use the ring mode to manage tx and rx descriptors
 134  * but passing this value so user can force to use the chain instead of the ring
 135  */
 136 static unsigned int chain_mode;
 137 module_param(chain_mode, int, S_IRUGO);
 138 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode");
 139
 140 static irqreturn_t stmmac_interrupt(int irq, void *dev_id);
 141
 142 #ifdef CONFIG_STMMAC_DEBUG_FS
 143 static int stmmac_init_fs(struct net_device *dev);
 144 static void stmmac_exit_fs(void);
 145 #endif
 146
 147 #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x))
 148
 149 /**
 150  * stmmac_verify_args - verify the driver parameters.
 151  * Description: it verifies if some wrong parameter is passed to the driver.
 152  * Note that wrong parameters are replaced with the default values.
 153  */
 154 static void stmmac_verify_args(void)
 155 {
 156         if (unlikely(watchdog < 0))
 157                 watchdog = TX_TIMEO;
 158         if (unlikely(dma_rxsize < 0))
 159                 dma_rxsize = DMA_RX_SIZE;
 160         if (unlikely(dma_txsize < 0))
 161                 dma_txsize = DMA_TX_SIZE;
 162         if (unlikely((buf_sz < DMA_BUFFER_SIZE) || (buf_sz > BUF_SIZE_16KiB)))
 163                 buf_sz = DMA_BUFFER_SIZE;
 164         if (unlikely(flow_ctrl > 1))
 165                 flow_ctrl = FLOW_AUTO;
 166         else if (likely(flow_ctrl < 0))
 167                 flow_ctrl = FLOW_OFF;
 168         if (unlikely((pause < 0) || (pause > 0xffff)))
 169                 pause = PAUSE_TIME;
 170         if (eee_timer < 0)
 171                 eee_timer = STMMAC_DEFAULT_LPI_TIMER;
 172 }
 173
 174 static void stmmac_clk_csr_set(struct stmmac_priv *priv)
 175 {
 176         u32 clk_rate;
 177
 178         clk_rate = clk_get_rate(priv->stmmac_clk);
 179
 180         /* Platform provided default clk_csr would be assumed valid
 181          * for all other cases except for the below mentioned ones. */
 182         if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) {
 183                 if (clk_rate < CSR_F_35M)
 184                         priv->clk_csr = STMMAC_CSR_20_35M;
 185                 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M))
 186                         priv->clk_csr = STMMAC_CSR_35_60M;
 187                 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M))
 188                         priv->clk_csr = STMMAC_CSR_60_100M;
 189                 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M))
 190                         priv->clk_csr = STMMAC_CSR_100_150M;
 191                 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M))
 192                         priv->clk_csr = STMMAC_CSR_150_250M;
 193                 else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M))
 194                         priv->clk_csr = STMMAC_CSR_250_300M;
 195         } /* For values higher than the IEEE 802.3 specified frequency
 196            * we can not estimate the proper divider as it is not known
 197            * the frequency of clk_csr_i. So we do not change the default
 198            * divider. */
 199 }
 200
 201 #if defined(STMMAC_XMIT_DEBUG) || defined(STMMAC_RX_DEBUG)
 202 static void print_pkt(unsigned char *buf, int len)
 203 {
 204         int j;
 205         pr_info("len = %d byte, buf addr: 0x%p", len, buf);
 206         for (j = 0; j < len; j++) {
 207                 if ((j % 16) == 0)
 208                         pr_info("\n %03x:", j);
 209                 pr_info(" %02x", buf[j]);
 210         }
 211         pr_info("\n");
 212 }
 213 #endif
 214
 215 /* minimum number of free TX descriptors required to wake up TX process */
 216 #define STMMAC_TX_THRESH(x)     (x->dma_tx_size/4)
 217
 218 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv)
 219 {
 220         return priv->dirty_tx + priv->dma_tx_size - priv->cur_tx - 1;
 221 }
 222
 223 /* On some ST platforms, some HW system configuraton registers have to be
 224  * set according to the link speed negotiated.
 225  */
 226 static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv *priv)
 227 {
 228         struct phy_device *phydev = priv->phydev;
 229
 230         if (likely(priv->plat->fix_mac_speed))
 231                 priv->plat->fix_mac_speed(priv->plat->bsp_priv,
 232                                           phydev->speed);
 233 }
 234
 235 static void stmmac_enable_eee_mode(struct stmmac_priv *priv)
 236 {
 237         /* Check and enter in LPI mode */
 238         if ((priv->dirty_tx == priv->cur_tx) &&
 239             (priv->tx_path_in_lpi_mode == false))
 240                 priv->hw->mac->set_eee_mode(priv->ioaddr);
 241 }
 242
 243 void stmmac_disable_eee_mode(struct stmmac_priv *priv)
 244 {
 245         /* Exit and disable EEE in case of we are are in LPI state. */
 246         priv->hw->mac->reset_eee_mode(priv->ioaddr);
 247         del_timer_sync(&priv->eee_ctrl_timer);
 248         priv->tx_path_in_lpi_mode = false;
 249 }
 250
 251 /**
 252  * stmmac_eee_ctrl_timer
 253  * @arg : data hook
 254  * Description:
 255  *  If there is no data transfer and if we are not in LPI state,
 256  *  then MAC Transmitter can be moved to LPI state.
 257  */
 258 static void stmmac_eee_ctrl_timer(unsigned long arg)
 259 {
 260         struct stmmac_priv *priv = (struct stmmac_priv *)arg;
 261
 262         stmmac_enable_eee_mode(priv);
 263         mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_TIMER(eee_timer));
 264 }
 265
 266 /**
 267  * stmmac_eee_init
 268  * @priv: private device pointer
 269  * Description:
 270  *  If the EEE support has been enabled while configuring the driver,
 271  *  if the GMAC actually supports the EEE (from the HW cap reg) and the
 272  *  phy can also manage EEE, so enable the LPI state and start the timer
 273  *  to verify if the tx path can enter in LPI state.
 274  */
 275 bool stmmac_eee_init(struct stmmac_priv *priv)
 276 {
 277         bool ret = false;
 278
 279         /* MAC core supports the EEE feature. */
 280         if (priv->dma_cap.eee) {
 281                 /* Check if the PHY supports EEE */
 282                 if (phy_init_eee(priv->phydev, 1))
 283                         goto out;
 284
 285                 priv->eee_active = 1;
 286                 init_timer(&priv->eee_ctrl_timer);
 287                 priv->eee_ctrl_timer.function = stmmac_eee_ctrl_timer;
 288                 priv->eee_ctrl_timer.data = (unsigned long)priv;
 289                 priv->eee_ctrl_timer.expires = STMMAC_LPI_TIMER(eee_timer);
 290                 add_timer(&priv->eee_ctrl_timer);
 291
 292                 priv->hw->mac->set_eee_timer(priv->ioaddr,
 293                                              STMMAC_DEFAULT_LIT_LS_TIMER,
 294                                              priv->tx_lpi_timer);
 295
 296                 pr_info("stmmac: Energy-Efficient Ethernet initialized\n");
 297
 298                 ret = true;
 299         }
 300 out:
 301         return ret;
 302 }
 303
 304 static void stmmac_eee_adjust(struct stmmac_priv *priv)
 305 {
 306         /* When the EEE has been already initialised we have to
 307          * modify the PLS bit in the LPI ctrl & status reg according
 308          * to the PHY link status. For this reason.
 309          */
 310         if (priv->eee_enabled)
 311                 priv->hw->mac->set_eee_pls(priv->ioaddr, priv->phydev->link);
 312 }
 313
 314 /**
 315  * stmmac_adjust_link
 316  * @dev: net device structure
 317  * Description: it adjusts the link parameters.
 318  */
 319 static void stmmac_adjust_link(struct net_device *dev)
 320 {
 321         struct stmmac_priv *priv = netdev_priv(dev);
 322         struct phy_device *phydev = priv->phydev;
 323         unsigned long flags;
 324         int new_state = 0;
 325         unsigned int fc = priv->flow_ctrl, pause_time = priv->pause;
 326
 327         if (phydev == NULL)
 328                 return;
 329
 330         DBG(probe, DEBUG, "stmmac_adjust_link: called.  address %d link %d\n",
 331             phydev->addr, phydev->link);
 332
 333         spin_lock_irqsave(&priv->lock, flags);
 334
 335         if (phydev->link) {
 336                 u32 ctrl = readl(priv->ioaddr + MAC_CTRL_REG);
 337
 338                 /* Now we make sure that we can be in full duplex mode.
 339                  * If not, we operate in half-duplex mode. */
 340                 if (phydev->duplex != priv->oldduplex) {
 341                         new_state = 1;
 342                         if (!(phydev->duplex))
 343                                 ctrl &= ~priv->hw->link.duplex;
 344                         else
 345                                 ctrl |= priv->hw->link.duplex;
 346                         priv->oldduplex = phydev->duplex;
 347                 }
 348                 /* Flow Control operation */
 349                 if (phydev->pause)
 350                         priv->hw->mac->flow_ctrl(priv->ioaddr, phydev->duplex,
 351                                                  fc, pause_time);
 352
 353                 if (phydev->speed != priv->speed) {
 354                         new_state = 1;
 355                         switch (phydev->speed) {
 356                         case 1000:
 357                                 if (likely(priv->plat->has_gmac))
 358                                         ctrl &= ~priv->hw->link.port;
 359                                         stmmac_hw_fix_mac_speed(priv);
 360                                 break;
 361                         case 100:
 362                         case 10:
 363                                 if (priv->plat->has_gmac) {
 364                                         ctrl |= priv->hw->link.port;
 365                                         if (phydev->speed == SPEED_100) {
 366                                                 ctrl |= priv->hw->link.speed;
 367                                         } else {
 368                                                 ctrl &= ~(priv->hw->link.speed);
 369                                         }
 370                                 } else {
 371                                         ctrl &= ~priv->hw->link.port;
 372                                 }
 373                                 stmmac_hw_fix_mac_speed(priv);
 374                                 break;
 375                         default:
 376                                 if (netif_msg_link(priv))
 377                                         pr_warning("%s: Speed (%d) is not 10"
 378                                        " or 100!\n", dev->name, phydev->speed);
 379                                 break;
 380                         }
 381
 382                         priv->speed = phydev->speed;
 383                 }
 384
 385                 writel(ctrl, priv->ioaddr + MAC_CTRL_REG);
 386
 387                 if (!priv->oldlink) {
 388                         new_state = 1;
 389                         priv->oldlink = 1;
 390                 }
 391         } else if (priv->oldlink) {
 392                 new_state = 1;
 393                 priv->oldlink = 0;
 394                 priv->speed = 0;
 395                 priv->oldduplex = -1;
 396         }
 397
 398         if (new_state && netif_msg_link(priv))
 399                 phy_print_status(phydev);
 400
 401         stmmac_eee_adjust(priv);
 402
 403         spin_unlock_irqrestore(&priv->lock, flags);
 404
 405         DBG(probe, DEBUG, "stmmac_adjust_link: exiting\n");
 406 }
 407
 408 /**
 409  * stmmac_init_phy - PHY initialization
 410  * @dev: net device structure
 411  * Description: it initializes the driver's PHY state, and attaches the PHY
 412  * to the mac driver.
 413  *  Return value:
 414  *  0 on success
 415  */
 416 static int stmmac_init_phy(struct net_device *dev)
 417 {
 418         struct stmmac_priv *priv = netdev_priv(dev);
 419         struct phy_device *phydev;
 420         char phy_id_fmt[MII_BUS_ID_SIZE + 3];
 421         char bus_id[MII_BUS_ID_SIZE];
 422         int interface = priv->plat->interface;
 423         priv->oldlink = 0;
 424         priv->speed = 0;
 425         priv->oldduplex = -1;
 426
 427         if (priv->plat->phy_bus_name)
 428                 snprintf(bus_id, MII_BUS_ID_SIZE, "%s-%x",
 429                                 priv->plat->phy_bus_name, priv->plat->bus_id);
 430         else
 431                 snprintf(bus_id, MII_BUS_ID_SIZE, "stmmac-%x",
 432                                 priv->plat->bus_id);
 433
 434         snprintf(phy_id_fmt, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id,
 435                  priv->plat->phy_addr);
 436         pr_debug("stmmac_init_phy:  trying to attach to %s\n", phy_id_fmt);
 437
 438         phydev = phy_connect(dev, phy_id_fmt, &stmmac_adjust_link, interface);
 439
 440         if (IS_ERR(phydev)) {
 441                 pr_err("%s: Could not attach to PHY\n", dev->name);
 442                 return PTR_ERR(phydev);
 443         }
 444
 445         /* Stop Advertising 1000BASE Capability if interface is not GMII */
 446         if ((interface == PHY_INTERFACE_MODE_MII) ||
 447             (interface == PHY_INTERFACE_MODE_RMII))
 448                 phydev->advertising &= ~(SUPPORTED_1000baseT_Half |
 449                                          SUPPORTED_1000baseT_Full);
 450
 451         /*
 452          * Broken HW is sometimes missing the pull-up resistor on the
 453          * MDIO line, which results in reads to non-existent devices returning
 454          * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent
 455          * device as well.
 456          * Note: phydev->phy_id is the result of reading the UID PHY registers.
 457          */
 458         if (phydev->phy_id == 0) {
 459                 phy_disconnect(phydev);
 460                 return -ENODEV;
 461         }
 462         pr_debug("stmmac_init_phy:  %s: attached to PHY (UID 0x%x)"
 463                  " Link = %d\n", dev->name, phydev->phy_id, phydev->link);
 464
 465         priv->phydev = phydev;
 466
 467         return 0;
 468 }
 469
 470 /**
 471  * display_ring
 472  * @p: pointer to the ring.
 473  * @size: size of the ring.
 474  * Description: display all the descriptors within the ring.
 475  */
 476 static void display_ring(struct dma_desc *p, int size)
 477 {
 478         struct tmp_s {
 479                 u64 a;
 480                 unsigned int b;
 481                 unsigned int c;
 482         };
 483         int i;
 484         for (i = 0; i < size; i++) {
 485                 struct tmp_s *x = (struct tmp_s *)(p + i);
 486                 pr_info("\t%d [0x%x]: DES0=0x%x DES1=0x%x BUF1=0x%x BUF2=0x%x",
 487                        i, (unsigned int)virt_to_phys(&p[i]),
 488                        (unsigned int)(x->a), (unsigned int)((x->a) >> 32),
 489                        x->b, x->c);
 490                 pr_info("\n");
 491         }
 492 }
 493
 494 static int stmmac_set_bfsize(int mtu, int bufsize)
 495 {
 496         int ret = bufsize;
 497
 498         if (mtu >= BUF_SIZE_4KiB)
 499                 ret = BUF_SIZE_8KiB;
 500         else if (mtu >= BUF_SIZE_2KiB)
 501                 ret = BUF_SIZE_4KiB;
 502         else if (mtu >= DMA_BUFFER_SIZE)
 503                 ret = BUF_SIZE_2KiB;
 504         else
 505                 ret = DMA_BUFFER_SIZE;
 506
 507         return ret;
 508 }
 509
 510 /**
 511  * init_dma_desc_rings - init the RX/TX descriptor rings
 512  * @dev: net device structure
 513  * Description:  this function initializes the DMA RX/TX descriptors
 514  * and allocates the socket buffers. It suppors the chained and ring
 515  * modes.
 516  */
 517 static void init_dma_desc_rings(struct net_device *dev)
 518 {
 519         int i;
 520         struct stmmac_priv *priv = netdev_priv(dev);
 521         struct sk_buff *skb;
 522         unsigned int txsize = priv->dma_tx_size;
 523         unsigned int rxsize = priv->dma_rx_size;
 524         unsigned int bfsize = 0;
 525         int dis_ic = 0;
 526
 527         /* Set the max buffer size according to the DESC mode
 528          * and the MTU. Note that RING mode allows 16KiB bsize. */
 529         if (priv->mode == STMMAC_RING_MODE)
 530                 bfsize = priv->hw->ring->set_16kib_bfsize(dev->mtu);
 531
 532         if (bfsize < BUF_SIZE_16KiB)
 533                 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz);
 534
 535         DBG(probe, INFO, "stmmac: txsize %d, rxsize %d, bfsize %d\n",
 536             txsize, rxsize, bfsize);
 537
 538         priv->rx_skbuff_dma = kmalloc_array(rxsize, sizeof(dma_addr_t),
 539                                             GFP_KERNEL);
 540         priv->rx_skbuff = kmalloc_array(rxsize, sizeof(struct sk_buff *),
 541                                         GFP_KERNEL);
 542         priv->dma_rx = dma_alloc_coherent(priv->device,
 543                                           rxsize * sizeof(struct dma_desc),
 544                                           &priv->dma_rx_phy, GFP_KERNEL);
 545         priv->tx_skbuff = kmalloc_array(txsize, sizeof(struct sk_buff *),
 546                                         GFP_KERNEL);
 547         priv->dma_tx = dma_alloc_coherent(priv->device,
 548                                           txsize * sizeof(struct dma_desc),
 549                                           &priv->dma_tx_phy, GFP_KERNEL);
 550
 551         if ((priv->dma_rx == NULL) || (priv->dma_tx == NULL))
 552                 return;
 553
 554         DBG(probe, INFO, "stmmac (%s) DMA desc: virt addr (Rx %p, "
 555             "Tx %p)\n\tDMA phy addr (Rx 0x%08x, Tx 0x%08x)\n",
 556             dev->name, priv->dma_rx, priv->dma_tx,
 557             (unsigned int)priv->dma_rx_phy, (unsigned int)priv->dma_tx_phy);
 558
 559         /* RX INITIALIZATION */
 560         DBG(probe, INFO, "stmmac: SKB addresses:\n"
 561                          "skb\t\tskb data\tdma data\n");
 562
 563         for (i = 0; i < rxsize; i++) {
 564                 struct dma_desc *p = priv->dma_rx + i;
 565
 566                 skb = __netdev_alloc_skb(dev, bfsize + NET_IP_ALIGN,
 567                                          GFP_KERNEL);
 568                 if (unlikely(skb == NULL)) {
 569                         pr_err("%s: Rx init fails; skb is NULL\n", __func__);
 570                         break;
 571                 }
 572                 skb_reserve(skb, NET_IP_ALIGN);
 573                 priv->rx_skbuff[i] = skb;
 574                 priv->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data,
 575                                                 bfsize, DMA_FROM_DEVICE);
 576
 577                 p->des2 = priv->rx_skbuff_dma[i];
 578
 579                 if ((priv->mode == STMMAC_RING_MODE) &&
 580                     (bfsize == BUF_SIZE_16KiB))
 581                         priv->hw->ring->init_desc3(p);
 582
 583                 DBG(probe, INFO, "[%p]\t[%p]\t[%x]\n", priv->rx_skbuff[i],
 584                         priv->rx_skbuff[i]->data, priv->rx_skbuff_dma[i]);
 585         }
 586         priv->cur_rx = 0;
 587         priv->dirty_rx = (unsigned int)(i - rxsize);
 588         priv->dma_buf_sz = bfsize;
 589         buf_sz = bfsize;
 590
 591         /* TX INITIALIZATION */
 592         for (i = 0; i < txsize; i++) {
 593                 priv->tx_skbuff[i] = NULL;
 594                 priv->dma_tx[i].des2 = 0;
 595         }
 596
 597         /* In case of Chained mode this sets the des3 to the next
 598          * element in the chain */
 599         if (priv->mode == STMMAC_CHAIN_MODE) {
 600                 priv->hw->chain->init_dma_chain(priv->dma_rx, priv->dma_rx_phy,
 601                                                 rxsize);
 602                 priv->hw->chain->init_dma_chain(priv->dma_tx, priv->dma_tx_phy,
 603                                                 txsize);
 604         }
 605         priv->dirty_tx = 0;
 606         priv->cur_tx = 0;
 607
 608         if (priv->use_riwt)
 609                 dis_ic = 1;
 610         /* Clear the Rx/Tx descriptors */
 611         priv->hw->desc->init_rx_desc(priv->dma_rx, rxsize, dis_ic, priv->mode);
 612         priv->hw->desc->init_tx_desc(priv->dma_tx, txsize, priv->mode);
 613
 614         if (netif_msg_hw(priv)) {
 615                 pr_info("RX descriptor ring:\n");
 616                 display_ring(priv->dma_rx, rxsize);
 617                 pr_info("TX descriptor ring:\n");
 618                 display_ring(priv->dma_tx, txsize);
 619         }
 620 }
 621
 622 static void dma_free_rx_skbufs(struct stmmac_priv *priv)
 623 {
 624         int i;
 625
 626         for (i = 0; i < priv->dma_rx_size; i++) {
 627                 if (priv->rx_skbuff[i]) {
 628                         dma_unmap_single(priv->device, priv->rx_skbuff_dma[i],
 629                                          priv->dma_buf_sz, DMA_FROM_DEVICE);
 630                         dev_kfree_skb_any(priv->rx_skbuff[i]);
 631                 }
 632                 priv->rx_skbuff[i] = NULL;
 633         }
 634 }
 635
 636 static void dma_free_tx_skbufs(struct stmmac_priv *priv)
 637 {
 638         int i;
 639
 640         for (i = 0; i < priv->dma_tx_size; i++) {
 641                 if (priv->tx_skbuff[i] != NULL) {
 642                         struct dma_desc *p = priv->dma_tx + i;
 643                         if (p->des2)
 644                                 dma_unmap_single(priv->device, p->des2,
 645                                                  priv->hw->desc->get_tx_len(p),
 646                                                  DMA_TO_DEVICE);
 647                         dev_kfree_skb_any(priv->tx_skbuff[i]);
 648                         priv->tx_skbuff[i] = NULL;
 649                 }
 650         }
 651 }
 652
 653 static void free_dma_desc_resources(struct stmmac_priv *priv)
 654 {
 655         /* Release the DMA TX/RX socket buffers */
 656         dma_free_rx_skbufs(priv);
 657         dma_free_tx_skbufs(priv);
 658
 659         /* Free the region of consistent memory previously allocated for
 660          * the DMA */
 661         dma_free_coherent(priv->device,
 662                           priv->dma_tx_size * sizeof(struct dma_desc),
 663                           priv->dma_tx, priv->dma_tx_phy);
 664         dma_free_coherent(priv->device,
 665                           priv->dma_rx_size * sizeof(struct dma_desc),
 666                           priv->dma_rx, priv->dma_rx_phy);
 667         kfree(priv->rx_skbuff_dma);
 668         kfree(priv->rx_skbuff);
 669         kfree(priv->tx_skbuff);
 670 }
 671
 672 /**
 673  *  stmmac_dma_operation_mode - HW DMA operation mode
 674  *  @priv : pointer to the private device structure.
 675  *  Description: it sets the DMA operation mode: tx/rx DMA thresholds
 676  *  or Store-And-Forward capability.
 677  */
 678 static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
 679 {
 680         if (likely(priv->plat->force_sf_dma_mode ||
 681                 ((priv->plat->tx_coe) && (!priv->no_csum_insertion)))) {
 682                 /*
 683                  * In case of GMAC, SF mode can be enabled
 684                  * to perform the TX COE in HW. This depends on:
 685                  * 1) TX COE if actually supported
 686                  * 2) There is no bugged Jumbo frame support
 687                  *    that needs to not insert csum in the TDES.
 688                  */
 689                 priv->hw->dma->dma_mode(priv->ioaddr,
 690                                         SF_DMA_MODE, SF_DMA_MODE);
 691                 tc = SF_DMA_MODE;
 692         } else
 693                 priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE);
 694 }
 695
 696 /**
 697  * stmmac_tx_clean:
 698  * @priv: private data pointer
 699  * Description: it reclaims resources after transmission completes.
 700  */
 701 static void stmmac_tx_clean(struct stmmac_priv *priv)
 702 {
 703         unsigned int txsize = priv->dma_tx_size;
 704
 705         spin_lock(&priv->tx_lock);
 706
 707         priv->xstats.tx_clean++;
 708
 709         while (priv->dirty_tx != priv->cur_tx) {
 710                 int last;
 711                 unsigned int entry = priv->dirty_tx % txsize;
 712                 struct sk_buff *skb = priv->tx_skbuff[entry];
 713                 struct dma_desc *p = priv->dma_tx + entry;
 714
 715                 /* Check if the descriptor is owned by the DMA. */
 716                 if (priv->hw->desc->get_tx_owner(p))
 717                         break;
 718
 719                 /* Verify tx error by looking at the last segment */
 720                 last = priv->hw->desc->get_tx_ls(p);
 721                 if (likely(last)) {
 722                         int tx_error =
 723                                 priv->hw->desc->tx_status(&priv->dev->stats,
 724                                                           &priv->xstats, p,
 725                                                           priv->ioaddr);
 726                         if (likely(tx_error == 0)) {
 727                                 priv->dev->stats.tx_packets++;
 728                                 priv->xstats.tx_pkt_n++;
 729                         } else
 730                                 priv->dev->stats.tx_errors++;
 731                 }
 732                 TX_DBG("%s: curr %d, dirty %d\n", __func__,
 733                         priv->cur_tx, priv->dirty_tx);
 734
 735                 if (likely(p->des2))
 736                         dma_unmap_single(priv->device, p->des2,
 737                                          priv->hw->desc->get_tx_len(p),
 738                                          DMA_TO_DEVICE);
 739                 if (priv->mode == STMMAC_RING_MODE)
 740                         priv->hw->ring->clean_desc3(p);
 741
 742                 if (likely(skb != NULL)) {
 743                         dev_kfree_skb(skb);
 744                         priv->tx_skbuff[entry] = NULL;
 745                 }
 746
 747                 priv->hw->desc->release_tx_desc(p, priv->mode);
 748
 749                 priv->dirty_tx++;
 750         }
 751         if (unlikely(netif_queue_stopped(priv->dev) &&
 752                      stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv))) {
 753                 netif_tx_lock(priv->dev);
 754                 if (netif_queue_stopped(priv->dev) &&
 755                      stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv)) {
 756                         TX_DBG("%s: restart transmit\n", __func__);
 757                         netif_wake_queue(priv->dev);
 758                 }
 759                 netif_tx_unlock(priv->dev);
 760         }
 761
 762         if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) {
 763                 stmmac_enable_eee_mode(priv);
 764                 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_TIMER(eee_timer));
 765         }
 766         spin_unlock(&priv->tx_lock);
 767 }
 768
 769 static inline void stmmac_enable_dma_irq(struct stmmac_priv *priv)
 770 {
 771         priv->hw->dma->enable_dma_irq(priv->ioaddr);
 772 }
 773
 774 static inline void stmmac_disable_dma_irq(struct stmmac_priv *priv)
 775 {
 776         priv->hw->dma->disable_dma_irq(priv->ioaddr);
 777 }
 778
 779
 780 /**
 781  * stmmac_tx_err:
 782  * @priv: pointer to the private device structure
 783  * Description: it cleans the descriptors and restarts the transmission
 784  * in case of errors.
 785  */
 786 static void stmmac_tx_err(struct stmmac_priv *priv)
 787 {
 788         netif_stop_queue(priv->dev);
 789
 790         priv->hw->dma->stop_tx(priv->ioaddr);
 791         dma_free_tx_skbufs(priv);
 792         priv->hw->desc->init_tx_desc(priv->dma_tx, priv->dma_tx_size,
 793                                      priv->mode);
 794         priv->dirty_tx = 0;
 795         priv->cur_tx = 0;
 796         priv->hw->dma->start_tx(priv->ioaddr);
 797
 798         priv->dev->stats.tx_errors++;
 799         netif_wake_queue(priv->dev);
 800 }
 801
 802 static void stmmac_dma_interrupt(struct stmmac_priv *priv)
 803 {
 804         int status;
 805
 806         status = priv->hw->dma->dma_interrupt(priv->ioaddr, &priv->xstats);
 807         if (likely((status & handle_rx)) || (status & handle_tx)) {
 808                 if (likely(napi_schedule_prep(&priv->napi))) {
 809                         stmmac_disable_dma_irq(priv);
 810                         __napi_schedule(&priv->napi);
 811                 }
 812         }
 813         if (unlikely(status & tx_hard_error_bump_tc)) {
 814                 /* Try to bump up the dma threshold on this failure */
 815                 if (unlikely(tc != SF_DMA_MODE) && (tc <= 256)) {
 816                         tc += 64;
 817                         priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE);
 818                         priv->xstats.threshold = tc;
 819                 }
 820         } else if (unlikely(status == tx_hard_error))
 821                 stmmac_tx_err(priv);
 822 }
 823
 824 static void stmmac_mmc_setup(struct stmmac_priv *priv)
 825 {
 826         unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET |
 827                             MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET;
 828
 829         /* Mask MMC irq, counters are managed in SW and registers
 830          * are cleared on each READ eventually. */
 831         dwmac_mmc_intr_all_mask(priv->ioaddr);
 832
 833         if (priv->dma_cap.rmon) {
 834                 dwmac_mmc_ctrl(priv->ioaddr, mode);
 835                 memset(&priv->mmc, 0, sizeof(struct stmmac_counters));
 836         } else
 837                 pr_info(" No MAC Management Counters available\n");
 838 }
 839
 840 static u32 stmmac_get_synopsys_id(struct stmmac_priv *priv)
 841 {
 842         u32 hwid = priv->hw->synopsys_uid;
 843
 844         /* Only check valid Synopsys Id because old MAC chips
 845          * have no HW registers where get the ID */
 846         if (likely(hwid)) {
 847                 u32 uid = ((hwid & 0x0000ff00) >> 8);
 848                 u32 synid = (hwid & 0x000000ff);
 849
 850                 pr_info("stmmac - user ID: 0x%x, Synopsys ID: 0x%x\n",
 851                         uid, synid);
 852
 853                 return synid;
 854         }
 855         return 0;
 856 }
 857
 858 /**
 859  * stmmac_selec_desc_mode
 860  * @priv : private structure
 861  * Description: select the Enhanced/Alternate or Normal descriptors
 862  */
 863 static void stmmac_selec_desc_mode(struct stmmac_priv *priv)
 864 {
 865         if (priv->plat->enh_desc) {
 866                 pr_info(" Enhanced/Alternate descriptors\n");
 867                 priv->hw->desc = &enh_desc_ops;
 868         } else {
 869                 pr_info(" Normal descriptors\n");
 870                 priv->hw->desc = &ndesc_ops;
 871         }
 872 }
 873
 874 /**
 875  * stmmac_get_hw_features
 876  * @priv : private device pointer
 877  * Description:
 878  *  new GMAC chip generations have a new register to indicate the
 879  *  presence of the optional feature/functions.
 880  *  This can be also used to override the value passed through the
 881  *  platform and necessary for old MAC10/100 and GMAC chips.
 882  */
 883 static int stmmac_get_hw_features(struct stmmac_priv *priv)
 884 {
 885         u32 hw_cap = 0;
 886
 887         if (priv->hw->dma->get_hw_feature) {
 888                 hw_cap = priv->hw->dma->get_hw_feature(priv->ioaddr);
 889
 890                 priv->dma_cap.mbps_10_100 = (hw_cap & DMA_HW_FEAT_MIISEL);
 891                 priv->dma_cap.mbps_1000 = (hw_cap & DMA_HW_FEAT_GMIISEL) >> 1;
 892                 priv->dma_cap.half_duplex = (hw_cap & DMA_HW_FEAT_HDSEL) >> 2;
 893                 priv->dma_cap.hash_filter = (hw_cap & DMA_HW_FEAT_HASHSEL) >> 4;
 894                 priv->dma_cap.multi_addr =
 895                         (hw_cap & DMA_HW_FEAT_ADDMACADRSEL) >> 5;
 896                 priv->dma_cap.pcs = (hw_cap & DMA_HW_FEAT_PCSSEL) >> 6;
 897                 priv->dma_cap.sma_mdio = (hw_cap & DMA_HW_FEAT_SMASEL) >> 8;
 898                 priv->dma_cap.pmt_remote_wake_up =
 899                         (hw_cap & DMA_HW_FEAT_RWKSEL) >> 9;
 900                 priv->dma_cap.pmt_magic_frame =
 901                         (hw_cap & DMA_HW_FEAT_MGKSEL) >> 10;
 902                 /* MMC */
 903                 priv->dma_cap.rmon = (hw_cap & DMA_HW_FEAT_MMCSEL) >> 11;
 904                 /* IEEE 1588-2002*/
 905                 priv->dma_cap.time_stamp =
 906                         (hw_cap & DMA_HW_FEAT_TSVER1SEL) >> 12;
 907                 /* IEEE 1588-2008*/
 908                 priv->dma_cap.atime_stamp =
 909                         (hw_cap & DMA_HW_FEAT_TSVER2SEL) >> 13;
 910                 /* 802.3az - Energy-Efficient Ethernet (EEE) */
 911                 priv->dma_cap.eee = (hw_cap & DMA_HW_FEAT_EEESEL) >> 14;
 912                 priv->dma_cap.av = (hw_cap & DMA_HW_FEAT_AVSEL) >> 15;
 913                 /* TX and RX csum */
 914                 priv->dma_cap.tx_coe = (hw_cap & DMA_HW_FEAT_TXCOESEL) >> 16;
 915                 priv->dma_cap.rx_coe_type1 =
 916                         (hw_cap & DMA_HW_FEAT_RXTYP1COE) >> 17;
 917                 priv->dma_cap.rx_coe_type2 =
 918                         (hw_cap & DMA_HW_FEAT_RXTYP2COE) >> 18;
 919                 priv->dma_cap.rxfifo_over_2048 =
 920                         (hw_cap & DMA_HW_FEAT_RXFIFOSIZE) >> 19;
 921                 /* TX and RX number of channels */
 922                 priv->dma_cap.number_rx_channel =
 923                         (hw_cap & DMA_HW_FEAT_RXCHCNT) >> 20;
 924                 priv->dma_cap.number_tx_channel =
 925                         (hw_cap & DMA_HW_FEAT_TXCHCNT) >> 22;
 926                 /* Alternate (enhanced) DESC mode*/
 927                 priv->dma_cap.enh_desc =
 928                         (hw_cap & DMA_HW_FEAT_ENHDESSEL) >> 24;
 929         }
 930
 931         return hw_cap;
 932 }
 933
 934 static void stmmac_check_ether_addr(struct stmmac_priv *priv)
 935 {
 936         /* verify if the MAC address is valid, in case of failures it
 937          * generates a random MAC address */
 938         if (!is_valid_ether_addr(priv->dev->dev_addr)) {
 939                 priv->hw->mac->get_umac_addr((void __iomem *)
 940                                              priv->dev->base_addr,
 941                                              priv->dev->dev_addr, 0);
 942                 if  (!is_valid_ether_addr(priv->dev->dev_addr))
 943                         eth_hw_addr_random(priv->dev);
 944         }
 945         pr_warning("%s: device MAC address %pM\n", priv->dev->name,
 946                                                    priv->dev->dev_addr);
 947 }
 948
 949 static int stmmac_init_dma_engine(struct stmmac_priv *priv)
 950 {
 951         int pbl = DEFAULT_DMA_PBL, fixed_burst = 0, burst_len = 0;
 952         int mixed_burst = 0;
 953
 954         /* Some DMA parameters can be passed from the platform;
 955          * in case of these are not passed we keep a default
 956          * (good for all the chips) and init the DMA! */
 957         if (priv->plat->dma_cfg) {
 958                 pbl = priv->plat->dma_cfg->pbl;
 959                 fixed_burst = priv->plat->dma_cfg->fixed_burst;
 960                 mixed_burst = priv->plat->dma_cfg->mixed_burst;
 961                 burst_len = priv->plat->dma_cfg->burst_len;
 962         }
 963
 964         return priv->hw->dma->init(priv->ioaddr, pbl, fixed_burst, mixed_burst,
 965                                    burst_len, priv->dma_tx_phy,
 966                                    priv->dma_rx_phy);
 967 }
 968
 969 /**
 970  * stmmac_tx_timer:
 971  * @data: data pointer
 972  * Description:
 973  * This is the timer handler to directly invoke the stmmac_tx_clean.
 974  */
 975 static void stmmac_tx_timer(unsigned long data)
 976 {
 977         struct stmmac_priv *priv = (struct stmmac_priv *)data;
 978
 979         stmmac_tx_clean(priv);
 980 }
 981
 982 /**
 983  * stmmac_tx_timer:
 984  * @priv: private data structure
 985  * Description:
 986  * This inits the transmit coalesce parameters: i.e. timer rate,
 987  * timer handler and default threshold used for enabling the
 988  * interrupt on completion bit.
 989  */
 990 static void stmmac_init_tx_coalesce(struct stmmac_priv *priv)
 991 {
 992         priv->tx_coal_frames = STMMAC_TX_FRAMES;
 993         priv->tx_coal_timer = STMMAC_COAL_TX_TIMER;
 994         init_timer(&priv->txtimer);
 995         priv->txtimer.expires = STMMAC_COAL_TIMER(priv->tx_coal_timer);
 996         priv->txtimer.data = (unsigned long)priv;
 997         priv->txtimer.function = stmmac_tx_timer;
 998         add_timer(&priv->txtimer);
 999 }
1000
1001 /**
1002  *  stmmac_open - open entry point of the driver
1003  *  @dev : pointer to the device structure.
1004  *  Description:
1005  *  This function is the open entry point of the driver.
1006  *  Return value:
1007  *  0 on success and an appropriate (-)ve integer as defined in errno.h
1008  *  file on failure.
1009  */
1010 static int stmmac_open(struct net_device *dev)
1011 {
1012         struct stmmac_priv *priv = netdev_priv(dev);
1013         int ret;
1014
1015         clk_prepare_enable(priv->stmmac_clk);
1016
1017         stmmac_check_ether_addr(priv);
1018
1019         ret = stmmac_init_phy(dev);
1020         if (unlikely(ret)) {
1021                 pr_err("%s: Cannot attach to PHY (error: %d)\n", __func__, ret);
1022                 goto open_error;
1023         }
1024
1025         /* Create and initialize the TX/RX descriptors chains. */
1026         priv->dma_tx_size = STMMAC_ALIGN(dma_txsize);
1027         priv->dma_rx_size = STMMAC_ALIGN(dma_rxsize);
1028         priv->dma_buf_sz = STMMAC_ALIGN(buf_sz);
1029         init_dma_desc_rings(dev);
1030
1031         /* DMA initialization and SW reset */
1032         ret = stmmac_init_dma_engine(priv);
1033         if (ret < 0) {
1034                 pr_err("%s: DMA initialization failed\n", __func__);
1035                 goto open_error;
1036         }
1037
1038         /* Copy the MAC addr into the HW  */
1039         priv->hw->mac->set_umac_addr(priv->ioaddr, dev->dev_addr, 0);
1040
1041         /* If required, perform hw setup of the bus. */
1042         if (priv->plat->bus_setup)
1043                 priv->plat->bus_setup(priv->ioaddr);
1044
1045         /* Initialize the MAC Core */
1046         priv->hw->mac->core_init(priv->ioaddr);
1047
1048         /* Request the IRQ lines */
1049         ret = request_irq(dev->irq, stmmac_interrupt,
1050                          IRQF_SHARED, dev->name, dev);
1051         if (unlikely(ret < 0)) {
1052                 pr_err("%s: ERROR: allocating the IRQ %d (error: %d)\n",
1053                        __func__, dev->irq, ret);
1054                 goto open_error;
1055         }
1056
1057         /* Request the Wake IRQ in case of another line is used for WoL */
1058         if (priv->wol_irq != dev->irq) {
1059                 ret = request_irq(priv->wol_irq, stmmac_interrupt,
1060                                   IRQF_SHARED, dev->name, dev);
1061                 if (unlikely(ret < 0)) {
1062                         pr_err("%s: ERROR: allocating the ext WoL IRQ %d "
1063                                "(error: %d)\n", __func__, priv->wol_irq, ret);
1064                         goto open_error_wolirq;
1065                 }
1066         }
1067
1068         /* Request the IRQ lines */
1069         if (priv->lpi_irq != -ENXIO) {
1070                 ret = request_irq(priv->lpi_irq, stmmac_interrupt, IRQF_SHARED,
1071                                   dev->name, dev);
1072                 if (unlikely(ret < 0)) {
1073                         pr_err("%s: ERROR: allocating the LPI IRQ %d (%d)\n",
1074                                __func__, priv->lpi_irq, ret);
1075                         goto open_error_lpiirq;
1076                 }
1077         }
1078
1079         /* Enable the MAC Rx/Tx */
1080         stmmac_set_mac(priv->ioaddr, true);
1081
1082         /* Set the HW DMA mode and the COE */
1083         stmmac_dma_operation_mode(priv);
1084
1085         /* Extra statistics */
1086         memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats));
1087         priv->xstats.threshold = tc;
1088
1089         stmmac_mmc_setup(priv);
1090
1091 #ifdef CONFIG_STMMAC_DEBUG_FS
1092         ret = stmmac_init_fs(dev);
1093         if (ret < 0)
1094                 pr_warning("%s: failed debugFS registration\n", __func__);
1095 #endif
1096         /* Start the ball rolling... */
1097         DBG(probe, DEBUG, "%s: DMA RX/TX processes started...\n", dev->name);
1098         priv->hw->dma->start_tx(priv->ioaddr);
1099         priv->hw->dma->start_rx(priv->ioaddr);
1100
1101         /* Dump DMA/MAC registers */
1102         if (netif_msg_hw(priv)) {
1103                 priv->hw->mac->dump_regs(priv->ioaddr);
1104                 priv->hw->dma->dump_regs(priv->ioaddr);
1105         }
1106
1107         if (priv->phydev)
1108                 phy_start(priv->phydev);
1109
1110         priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS_TIMER;
1111         priv->eee_enabled = stmmac_eee_init(priv);
1112
1113         stmmac_init_tx_coalesce(priv);
1114
1115         if ((priv->use_riwt) && (priv->hw->dma->rx_watchdog)) {
1116                 priv->rx_riwt = MAX_DMA_RIWT;
1117                 priv->hw->dma->rx_watchdog(priv->ioaddr, MAX_DMA_RIWT);
1118         }
1119
1120         napi_enable(&priv->napi);
1121         netif_start_queue(dev);
1122
1123         return 0;
1124
1125 open_error_lpiirq:
1126         if (priv->wol_irq != dev->irq)
1127                 free_irq(priv->wol_irq, dev);
1128
1129 open_error_wolirq:
1130         free_irq(dev->irq, dev);
1131
1132 open_error:
1133         if (priv->phydev)
1134                 phy_disconnect(priv->phydev);
1135
1136         clk_disable_unprepare(priv->stmmac_clk);
1137
1138         return ret;
1139 }
1140
1141 /**
1142  *  stmmac_release - close entry point of the driver
1143  *  @dev : device pointer.
1144  *  Description:
1145  *  This is the stop entry point of the driver.
1146  */
1147 static int stmmac_release(struct net_device *dev)
1148 {
1149         struct stmmac_priv *priv = netdev_priv(dev);
1150
1151         if (priv->eee_enabled)
1152                 del_timer_sync(&priv->eee_ctrl_timer);
1153
1154         /* Stop and disconnect the PHY */
1155         if (priv->phydev) {
1156                 phy_stop(priv->phydev);
1157                 phy_disconnect(priv->phydev);
1158                 priv->phydev = NULL;
1159         }
1160
1161         netif_stop_queue(dev);
1162
1163         napi_disable(&priv->napi);
1164
1165         del_timer_sync(&priv->txtimer);
1166
1167         /* Free the IRQ lines */
1168         free_irq(dev->irq, dev);
1169         if (priv->wol_irq != dev->irq)
1170                 free_irq(priv->wol_irq, dev);
1171         if (priv->lpi_irq != -ENXIO)
1172                 free_irq(priv->lpi_irq, dev);
1173
1174         /* Stop TX/RX DMA and clear the descriptors */
1175         priv->hw->dma->stop_tx(priv->ioaddr);
1176         priv->hw->dma->stop_rx(priv->ioaddr);
1177
1178         /* Release and free the Rx/Tx resources */
1179         free_dma_desc_resources(priv);
1180
1181         /* Disable the MAC Rx/Tx */
1182         stmmac_set_mac(priv->ioaddr, false);
1183
1184         netif_carrier_off(dev);
1185
1186 #ifdef CONFIG_STMMAC_DEBUG_FS
1187         stmmac_exit_fs();
1188 #endif
1189         clk_disable_unprepare(priv->stmmac_clk);
1190
1191         return 0;
1192 }
1193
1194 /**
1195  *  stmmac_xmit:
1196  *  @skb : the socket buffer
1197  *  @dev : device pointer
1198  *  Description : Tx entry point of the driver.
1199  */
1200 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
1201 {
1202         struct stmmac_priv *priv = netdev_priv(dev);
1203         unsigned int txsize = priv->dma_tx_size;
1204         unsigned int entry;
1205         int i, csum_insertion = 0, is_jumbo = 0;
1206         int nfrags = skb_shinfo(skb)->nr_frags;
1207         struct dma_desc *desc, *first;
1208         unsigned int nopaged_len = skb_headlen(skb);
1209
1210         if (unlikely(stmmac_tx_avail(priv) < nfrags + 1)) {
1211                 if (!netif_queue_stopped(dev)) {
1212                         netif_stop_queue(dev);
1213                         /* This is a hard error, log it. */
1214                         pr_err("%s: BUG! Tx Ring full when queue awake\n",
1215                                 __func__);
1216                 }
1217                 return NETDEV_TX_BUSY;
1218         }
1219
1220         spin_lock(&priv->tx_lock);
1221
1222         if (priv->tx_path_in_lpi_mode)
1223                 stmmac_disable_eee_mode(priv);
1224
1225         entry = priv->cur_tx % txsize;
1226
1227 #ifdef STMMAC_XMIT_DEBUG
1228         if ((skb->len > ETH_FRAME_LEN) || nfrags)
1229                 pr_debug("stmmac xmit: [entry %d]\n"
1230                          "\tskb addr %p - len: %d - nopaged_len: %d\n"
1231                          "\tn_frags: %d - ip_summed: %d - %s gso\n"
1232                          "\ttx_count_frames %d\n", entry,
1233                          skb, skb->len, nopaged_len, nfrags, skb->ip_summed,
1234                          !skb_is_gso(skb) ? "isn't" : "is",
1235                          priv->tx_count_frames);
1236 #endif
1237
1238         csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL);
1239
1240         desc = priv->dma_tx + entry;
1241         first = desc;
1242
1243 #ifdef STMMAC_XMIT_DEBUG
1244         if ((nfrags > 0) || (skb->len > ETH_FRAME_LEN))
1245                 pr_debug("\tskb len: %d, nopaged_len: %d,\n"
1246                          "\t\tn_frags: %d, ip_summed: %d\n",
1247                          skb->len, nopaged_len, nfrags, skb->ip_summed);
1248 #endif
1249         priv->tx_skbuff[entry] = skb;
1250
1251         /* To program the descriptors according to the size of the frame */
1252         if (priv->mode == STMMAC_RING_MODE) {
1253                 is_jumbo = priv->hw->ring->is_jumbo_frm(skb->len,
1254                                                         priv->plat->enh_desc);
1255                 if (unlikely(is_jumbo))
1256                         entry = priv->hw->ring->jumbo_frm(priv, skb,
1257                                                           csum_insertion);
1258         } else {
1259                 is_jumbo = priv->hw->chain->is_jumbo_frm(skb->len,
1260                                                         priv->plat->enh_desc);
1261                 if (unlikely(is_jumbo))
1262                         entry = priv->hw->chain->jumbo_frm(priv, skb,
1263                                                            csum_insertion);
1264         }
1265         if (likely(!is_jumbo)) {
1266                 desc->des2 = dma_map_single(priv->device, skb->data,
1267                                         nopaged_len, DMA_TO_DEVICE);
1268                 priv->hw->desc->prepare_tx_desc(desc, 1, nopaged_len,
1269                                                 csum_insertion, priv->mode);
1270         } else
1271                 desc = priv->dma_tx + entry;
1272
1273         for (i = 0; i < nfrags; i++) {
1274                 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1275                 int len = skb_frag_size(frag);
1276
1277                 entry = (++priv->cur_tx) % txsize;
1278                 desc = priv->dma_tx + entry;
1279
1280                 TX_DBG("\t[entry %d] segment len: %d\n", entry, len);
1281                 desc->des2 = skb_frag_dma_map(priv->device, frag, 0, len,
1282                                               DMA_TO_DEVICE);
1283                 priv->tx_skbuff[entry] = NULL;
1284                 priv->hw->desc->prepare_tx_desc(desc, 0, len, csum_insertion,
1285                                                 priv->mode);
1286                 wmb();
1287                 priv->hw->desc->set_tx_owner(desc);
1288                 wmb();
1289         }
1290
1291         /* Finalize the latest segment. */
1292         priv->hw->desc->close_tx_desc(desc);
1293
1294         wmb();
1295         /* According to the coalesce parameter the IC bit for the latest
1296          * segment could be reset and the timer re-started to invoke the
1297          * stmmac_tx function. This approach takes care about the fragments.
1298          */
1299         priv->tx_count_frames += nfrags + 1;
1300         if (priv->tx_coal_frames > priv->tx_count_frames) {
1301                 priv->hw->desc->clear_tx_ic(desc);
1302                 priv->xstats.tx_reset_ic_bit++;
1303                 TX_DBG("\t[entry %d]: tx_count_frames %d\n", entry,
1304                        priv->tx_count_frames);
1305                 mod_timer(&priv->txtimer,
1306                           STMMAC_COAL_TIMER(priv->tx_coal_timer));
1307         } else
1308                 priv->tx_count_frames = 0;
1309
1310         /* To avoid raise condition */
1311         priv->hw->desc->set_tx_owner(first);
1312         wmb();
1313
1314         priv->cur_tx++;
1315
1316 #ifdef STMMAC_XMIT_DEBUG
1317         if (netif_msg_pktdata(priv)) {
1318                 pr_info("stmmac xmit: current=%d, dirty=%d, entry=%d, "
1319                        "first=%p, nfrags=%d\n",
1320                        (priv->cur_tx % txsize), (priv->dirty_tx % txsize),
1321                        entry, first, nfrags);
1322                 display_ring(priv->dma_tx, txsize);
1323                 pr_info(">>> frame to be transmitted: ");
1324                 print_pkt(skb->data, skb->len);
1325         }
1326 #endif
1327         if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) {
1328                 TX_DBG("%s: stop transmitted packets\n", __func__);
1329                 netif_stop_queue(dev);
1330         }
1331
1332         dev->stats.tx_bytes += skb->len;
1333
1334         skb_tx_timestamp(skb);
1335
1336         priv->hw->dma->enable_dma_transmission(priv->ioaddr);
1337
1338         spin_unlock(&priv->tx_lock);
1339
1340         return NETDEV_TX_OK;
1341 }
1342
1343 static inline void stmmac_rx_refill(struct stmmac_priv *priv)
1344 {
1345         unsigned int rxsize = priv->dma_rx_size;
1346         int bfsize = priv->dma_buf_sz;
1347         struct dma_desc *p = priv->dma_rx;
1348
1349         for (; priv->cur_rx - priv->dirty_rx > 0; priv->dirty_rx++) {
1350                 unsigned int entry = priv->dirty_rx % rxsize;
1351                 if (likely(priv->rx_skbuff[entry] == NULL)) {
1352                         struct sk_buff *skb;
1353
1354                         skb = netdev_alloc_skb_ip_align(priv->dev, bfsize);
1355
1356                         if (unlikely(skb == NULL))
1357                                 break;
1358
1359                         priv->rx_skbuff[entry] = skb;
1360                         priv->rx_skbuff_dma[entry] =
1361                             dma_map_single(priv->device, skb->data, bfsize,
1362                                            DMA_FROM_DEVICE);
1363
1364                         (p + entry)->des2 = priv->rx_skbuff_dma[entry];
1365
1366                         if (unlikely((priv->mode == STMMAC_RING_MODE) &&
1367                                      (priv->plat->has_gmac)))
1368                                 priv->hw->ring->refill_desc3(bfsize, p + entry);
1369
1370                         RX_DBG(KERN_INFO "\trefill entry #%d\n", entry);
1371                 }
1372                 wmb();
1373                 priv->hw->desc->set_rx_owner(p + entry);
1374                 wmb();
1375         }
1376 }
1377
1378 static int stmmac_rx(struct stmmac_priv *priv, int limit)
1379 {
1380         unsigned int rxsize = priv->dma_rx_size;
1381         unsigned int entry = priv->cur_rx % rxsize;
1382         unsigned int next_entry;
1383         unsigned int count = 0;
1384         struct dma_desc *p = priv->dma_rx + entry;
1385         struct dma_desc *p_next;
1386
1387 #ifdef STMMAC_RX_DEBUG
1388         if (netif_msg_hw(priv)) {
1389                 pr_debug(">>> stmmac_rx: descriptor ring:\n");
1390                 display_ring(priv->dma_rx, rxsize);
1391         }
1392 #endif
1393         while (!priv->hw->desc->get_rx_owner(p)) {
1394                 int status;
1395
1396                 if (count >= limit)
1397                         break;
1398
1399                 count++;
1400
1401                 next_entry = (++priv->cur_rx) % rxsize;
1402                 p_next = priv->dma_rx + next_entry;
1403                 prefetch(p_next);
1404
1405                 /* read the status of the incoming frame */
1406                 status = (priv->hw->desc->rx_status(&priv->dev->stats,
1407                                                     &priv->xstats, p));
1408                 if (unlikely(status == discard_frame))
1409                         priv->dev->stats.rx_errors++;
1410                 else {
1411                         struct sk_buff *skb;
1412                         int frame_len;
1413
1414                         frame_len = priv->hw->desc->get_rx_frame_len(p,
1415                                         priv->plat->rx_coe);
1416                         /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
1417                          * Type frames (LLC/LLC-SNAP) */
1418                         if (unlikely(status != llc_snap))
1419                                 frame_len -= ETH_FCS_LEN;
1420 #ifdef STMMAC_RX_DEBUG
1421                         if (frame_len > ETH_FRAME_LEN)
1422                                 pr_debug("\tRX frame size %d, COE status: %d\n",
1423                                         frame_len, status);
1424
1425                         if (netif_msg_hw(priv))
1426                                 pr_debug("\tdesc: %p [entry %d] buff=0x%x\n",
1427                                         p, entry, p->des2);
1428 #endif
1429                         skb = priv->rx_skbuff[entry];
1430                         if (unlikely(!skb)) {
1431                                 pr_err("%s: Inconsistent Rx descriptor chain\n",
1432                                         priv->dev->name);
1433                                 priv->dev->stats.rx_dropped++;
1434                                 break;
1435                         }
1436                         prefetch(skb->data - NET_IP_ALIGN);
1437                         priv->rx_skbuff[entry] = NULL;
1438
1439                         skb_put(skb, frame_len);
1440                         dma_unmap_single(priv->device,
1441                                          priv->rx_skbuff_dma[entry],
1442                                          priv->dma_buf_sz, DMA_FROM_DEVICE);
1443 #ifdef STMMAC_RX_DEBUG
1444                         if (netif_msg_pktdata(priv)) {
1445                                 pr_info(" frame received (%dbytes)", frame_len);
1446                                 print_pkt(skb->data, frame_len);
1447                         }
1448 #endif
1449                         skb->protocol = eth_type_trans(skb, priv->dev);
1450
1451                         if (unlikely(!priv->plat->rx_coe))
1452                                 skb_checksum_none_assert(skb);
1453                         else
1454                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1455
1456                         napi_gro_receive(&priv->napi, skb);
1457
1458                         priv->dev->stats.rx_packets++;
1459                         priv->dev->stats.rx_bytes += frame_len;
1460                 }
1461                 entry = next_entry;
1462                 p = p_next;     /* use prefetched values */
1463         }
1464
1465         stmmac_rx_refill(priv);
1466
1467         priv->xstats.rx_pkt_n += count;
1468
1469         return count;
1470 }
1471
1472 /**
1473  *  stmmac_poll - stmmac poll method (NAPI)
1474  *  @napi : pointer to the napi structure.
1475  *  @budget : maximum number of packets that the current CPU can receive from
1476  *            all interfaces.
1477  *  Description :
1478  *  To look at the incoming frames and clear the tx resources.
1479  */
1480 static int stmmac_poll(struct napi_struct *napi, int budget)
1481 {
1482         struct stmmac_priv *priv = container_of(napi, struct stmmac_priv, napi);
1483         int work_done = 0;
1484
1485         priv->xstats.napi_poll++;
1486         stmmac_tx_clean(priv);
1487
1488         work_done = stmmac_rx(priv, budget);
1489         if (work_done < budget) {
1490                 napi_complete(napi);
1491                 stmmac_enable_dma_irq(priv);
1492         }
1493         return work_done;
1494 }
1495
1496 /**
1497  *  stmmac_tx_timeout
1498  *  @dev : Pointer to net device structure
1499  *  Description: this function is called when a packet transmission fails to
1500  *   complete within a reasonable time. The driver will mark the error in the
1501  *   netdev structure and arrange for the device to be reset to a sane state
1502  *   in order to transmit a new packet.
1503  */
1504 static void stmmac_tx_timeout(struct net_device *dev)
1505 {
1506         struct stmmac_priv *priv = netdev_priv(dev);
1507
1508         /* Clear Tx resources and restart transmitting again */
1509         stmmac_tx_err(priv);
1510 }
1511
1512 /* Configuration changes (passed on by ifconfig) */
1513 static int stmmac_config(struct net_device *dev, struct ifmap *map)
1514 {
1515         if (dev->flags & IFF_UP)        /* can't act on a running interface */
1516                 return -EBUSY;
1517
1518         /* Don't allow changing the I/O address */
1519         if (map->base_addr != dev->base_addr) {
1520                 pr_warning("%s: can't change I/O address\n", dev->name);
1521                 return -EOPNOTSUPP;
1522         }
1523
1524         /* Don't allow changing the IRQ */
1525         if (map->irq != dev->irq) {
1526                 pr_warning("%s: can't change IRQ number %d\n",
1527                        dev->name, dev->irq);
1528                 return -EOPNOTSUPP;
1529         }
1530
1531         /* ignore other fields */
1532         return 0;
1533 }
1534
1535 /**
1536  *  stmmac_set_rx_mode - entry point for multicast addressing
1537  *  @dev : pointer to the device structure
1538  *  Description:
1539  *  This function is a driver entry point which gets called by the kernel
1540  *  whenever multicast addresses must be enabled/disabled.
1541  *  Return value:
1542  *  void.
1543  */
1544 static void stmmac_set_rx_mode(struct net_device *dev)
1545 {
1546         struct stmmac_priv *priv = netdev_priv(dev);
1547
1548         spin_lock(&priv->lock);
1549         priv->hw->mac->set_filter(dev, priv->synopsys_id);
1550         spin_unlock(&priv->lock);
1551 }
1552
1553 /**
1554  *  stmmac_change_mtu - entry point to change MTU size for the device.
1555  *  @dev : device pointer.
1556  *  @new_mtu : the new MTU size for the device.
1557  *  Description: the Maximum Transfer Unit (MTU) is used by the network layer
1558  *  to drive packet transmission. Ethernet has an MTU of 1500 octets
1559  *  (ETH_DATA_LEN). This value can be changed with ifconfig.
1560  *  Return value:
1561  *  0 on success and an appropriate (-)ve integer as defined in errno.h
1562  *  file on failure.
1563  */
1564 static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
1565 {
1566         struct stmmac_priv *priv = netdev_priv(dev);
1567         int max_mtu;
1568
1569         if (netif_running(dev)) {
1570                 pr_err("%s: must be stopped to change its MTU\n", dev->name);
1571                 return -EBUSY;
1572         }
1573
1574         if (priv->plat->enh_desc)
1575                 max_mtu = JUMBO_LEN;
1576         else
1577                 max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN);
1578
1579         if ((new_mtu < 46) || (new_mtu > max_mtu)) {
1580                 pr_err("%s: invalid MTU, max MTU is: %d\n", dev->name, max_mtu);
1581                 return -EINVAL;
1582         }
1583
1584         dev->mtu = new_mtu;
1585         netdev_update_features(dev);
1586
1587         return 0;
1588 }
1589
1590 static netdev_features_t stmmac_fix_features(struct net_device *dev,
1591         netdev_features_t features)
1592 {
1593         struct stmmac_priv *priv = netdev_priv(dev);
1594
1595         if (priv->plat->rx_coe == STMMAC_RX_COE_NONE)
1596                 features &= ~NETIF_F_RXCSUM;
1597         else if (priv->plat->rx_coe == STMMAC_RX_COE_TYPE1)
1598                 features &= ~NETIF_F_IPV6_CSUM;
1599         if (!priv->plat->tx_coe)
1600                 features &= ~NETIF_F_ALL_CSUM;
1601
1602         /* Some GMAC devices have a bugged Jumbo frame support that
1603          * needs to have the Tx COE disabled for oversized frames
1604          * (due to limited buffer sizes). In this case we disable
1605          * the TX csum insertionin the TDES and not use SF. */
1606         if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN))
1607                 features &= ~NETIF_F_ALL_CSUM;
1608
1609         return features;
1610 }
1611
1612 static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
1613 {
1614         struct net_device *dev = (struct net_device *)dev_id;
1615         struct stmmac_priv *priv = netdev_priv(dev);
1616
1617         if (unlikely(!dev)) {
1618                 pr_err("%s: invalid dev pointer\n", __func__);
1619                 return IRQ_NONE;
1620         }
1621
1622         /* To handle GMAC own interrupts */
1623         if (priv->plat->has_gmac) {
1624                 int status = priv->hw->mac->host_irq_status((void __iomem *)
1625                                                             dev->base_addr);
1626                 if (unlikely(status)) {
1627                         if (status & core_mmc_tx_irq)
1628                                 priv->xstats.mmc_tx_irq_n++;
1629                         if (status & core_mmc_rx_irq)
1630                                 priv->xstats.mmc_rx_irq_n++;
1631                         if (status & core_mmc_rx_csum_offload_irq)
1632                                 priv->xstats.mmc_rx_csum_offload_irq_n++;
1633                         if (status & core_irq_receive_pmt_irq)
1634                                 priv->xstats.irq_receive_pmt_irq_n++;
1635
1636                         /* For LPI we need to save the tx status */
1637                         if (status & core_irq_tx_path_in_lpi_mode) {
1638                                 priv->xstats.irq_tx_path_in_lpi_mode_n++;
1639                                 priv->tx_path_in_lpi_mode = true;
1640                         }
1641                         if (status & core_irq_tx_path_exit_lpi_mode) {
1642                                 priv->xstats.irq_tx_path_exit_lpi_mode_n++;
1643                                 priv->tx_path_in_lpi_mode = false;
1644                         }
1645                         if (status & core_irq_rx_path_in_lpi_mode)
1646                                 priv->xstats.irq_rx_path_in_lpi_mode_n++;
1647                         if (status & core_irq_rx_path_exit_lpi_mode)
1648                                 priv->xstats.irq_rx_path_exit_lpi_mode_n++;
1649                 }
1650         }
1651
1652         /* To handle DMA interrupts */
1653         stmmac_dma_interrupt(priv);
1654
1655         return IRQ_HANDLED;
1656 }
1657
1658 #ifdef CONFIG_NET_POLL_CONTROLLER
1659 /* Polling receive - used by NETCONSOLE and other diagnostic tools
1660  * to allow network I/O with interrupts disabled. */
1661 static void stmmac_poll_controller(struct net_device *dev)
1662 {
1663         disable_irq(dev->irq);
1664         stmmac_interrupt(dev->irq, dev);
1665         enable_irq(dev->irq);
1666 }
1667 #endif
1668
1669 /**
1670  *  stmmac_ioctl - Entry point for the Ioctl
1671  *  @dev: Device pointer.
1672  *  @rq: An IOCTL specefic structure, that can contain a pointer to
1673  *  a proprietary structure used to pass information to the driver.
1674  *  @cmd: IOCTL command
1675  *  Description:
1676  *  Currently there are no special functionality supported in IOCTL, just the
1677  *  phy_mii_ioctl(...) can be invoked.
1678  */
1679 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1680 {
1681         struct stmmac_priv *priv = netdev_priv(dev);
1682         int ret;
1683
1684         if (!netif_running(dev))
1685                 return -EINVAL;
1686
1687         if (!priv->phydev)
1688                 return -EINVAL;
1689
1690         ret = phy_mii_ioctl(priv->phydev, rq, cmd);
1691
1692         return ret;
1693 }
1694
1695 #ifdef CONFIG_STMMAC_DEBUG_FS
1696 static struct dentry *stmmac_fs_dir;
1697 static struct dentry *stmmac_rings_status;
1698 static struct dentry *stmmac_dma_cap;
1699
1700 static int stmmac_sysfs_ring_read(struct seq_file *seq, void *v)
1701 {
1702         struct tmp_s {
1703                 u64 a;
1704                 unsigned int b;
1705                 unsigned int c;
1706         };
1707         int i;
1708         struct net_device *dev = seq->private;
1709         struct stmmac_priv *priv = netdev_priv(dev);
1710
1711         seq_printf(seq, "=======================\n");
1712         seq_printf(seq, " RX descriptor ring\n");
1713         seq_printf(seq, "=======================\n");
1714
1715         for (i = 0; i < priv->dma_rx_size; i++) {
1716                 struct tmp_s *x = (struct tmp_s *)(priv->dma_rx + i);
1717                 seq_printf(seq, "[%d] DES0=0x%x DES1=0x%x BUF1=0x%x BUF2=0x%x",
1718                            i, (unsigned int)(x->a),
1719                            (unsigned int)((x->a) >> 32), x->b, x->c);
1720                 seq_printf(seq, "\n");
1721         }
1722
1723         seq_printf(seq, "\n");
1724         seq_printf(seq, "=======================\n");
1725         seq_printf(seq, "  TX descriptor ring\n");
1726         seq_printf(seq, "=======================\n");
1727
1728         for (i = 0; i < priv->dma_tx_size; i++) {
1729                 struct tmp_s *x = (struct tmp_s *)(priv->dma_tx + i);
1730                 seq_printf(seq, "[%d] DES0=0x%x DES1=0x%x BUF1=0x%x BUF2=0x%x",
1731                            i, (unsigned int)(x->a),
1732                            (unsigned int)((x->a) >> 32), x->b, x->c);
1733                 seq_printf(seq, "\n");
1734         }
1735
1736         return 0;
1737 }
1738
1739 static int stmmac_sysfs_ring_open(struct inode *inode, struct file *file)
1740 {
1741         return single_open(file, stmmac_sysfs_ring_read, inode->i_private);
1742 }
1743
1744 static const struct file_operations stmmac_rings_status_fops = {
1745         .owner = THIS_MODULE,
1746         .open = stmmac_sysfs_ring_open,
1747         .read = seq_read,
1748         .llseek = seq_lseek,
1749         .release = single_release,
1750 };
1751
1752 static int stmmac_sysfs_dma_cap_read(struct seq_file *seq, void *v)
1753 {
1754         struct net_device *dev = seq->private;
1755         struct stmmac_priv *priv = netdev_priv(dev);
1756
1757         if (!priv->hw_cap_support) {
1758                 seq_printf(seq, "DMA HW features not supported\n");
1759                 return 0;
1760         }
1761
1762         seq_printf(seq, "==============================\n");
1763         seq_printf(seq, "\tDMA HW features\n");
1764         seq_printf(seq, "==============================\n");
1765
1766         seq_printf(seq, "\t10/100 Mbps %s\n",
1767                    (priv->dma_cap.mbps_10_100) ? "Y" : "N");
1768         seq_printf(seq, "\t1000 Mbps %s\n",
1769                    (priv->dma_cap.mbps_1000) ? "Y" : "N");
1770         seq_printf(seq, "\tHalf duple %s\n",
1771                    (priv->dma_cap.half_duplex) ? "Y" : "N");
1772         seq_printf(seq, "\tHash Filter: %s\n",
1773                    (priv->dma_cap.hash_filter) ? "Y" : "N");
1774         seq_printf(seq, "\tMultiple MAC address registers: %s\n",
1775                    (priv->dma_cap.multi_addr) ? "Y" : "N");
1776         seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfatces): %s\n",
1777                    (priv->dma_cap.pcs) ? "Y" : "N");
1778         seq_printf(seq, "\tSMA (MDIO) Interface: %s\n",
1779                    (priv->dma_cap.sma_mdio) ? "Y" : "N");
1780         seq_printf(seq, "\tPMT Remote wake up: %s\n",
1781                    (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N");
1782         seq_printf(seq, "\tPMT Magic Frame: %s\n",
1783                    (priv->dma_cap.pmt_magic_frame) ? "Y" : "N");
1784         seq_printf(seq, "\tRMON module: %s\n",
1785                    (priv->dma_cap.rmon) ? "Y" : "N");
1786         seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n",
1787                    (priv->dma_cap.time_stamp) ? "Y" : "N");
1788         seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp:%s\n",
1789                    (priv->dma_cap.atime_stamp) ? "Y" : "N");
1790         seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE) %s\n",
1791                    (priv->dma_cap.eee) ? "Y" : "N");
1792         seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N");
1793         seq_printf(seq, "\tChecksum Offload in TX: %s\n",
1794                    (priv->dma_cap.tx_coe) ? "Y" : "N");
1795         seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n",
1796                    (priv->dma_cap.rx_coe_type1) ? "Y" : "N");
1797         seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n",
1798                    (priv->dma_cap.rx_coe_type2) ? "Y" : "N");
1799         seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n",
1800                    (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N");
1801         seq_printf(seq, "\tNumber of Additional RX channel: %d\n",
1802                    priv->dma_cap.number_rx_channel);
1803         seq_printf(seq, "\tNumber of Additional TX channel: %d\n",
1804                    priv->dma_cap.number_tx_channel);
1805         seq_printf(seq, "\tEnhanced descriptors: %s\n",
1806                    (priv->dma_cap.enh_desc) ? "Y" : "N");
1807
1808         return 0;
1809 }
1810
1811 static int stmmac_sysfs_dma_cap_open(struct inode *inode, struct file *file)
1812 {
1813         return single_open(file, stmmac_sysfs_dma_cap_read, inode->i_private);
1814 }
1815
1816 static const struct file_operations stmmac_dma_cap_fops = {
1817         .owner = THIS_MODULE,
1818         .open = stmmac_sysfs_dma_cap_open,
1819         .read = seq_read,
1820         .llseek = seq_lseek,
1821         .release = single_release,
1822 };
1823
1824 static int stmmac_init_fs(struct net_device *dev)
1825 {
1826         /* Create debugfs entries */
1827         stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL);
1828
1829         if (!stmmac_fs_dir || IS_ERR(stmmac_fs_dir)) {
1830                 pr_err("ERROR %s, debugfs create directory failed\n",
1831                        STMMAC_RESOURCE_NAME);
1832
1833                 return -ENOMEM;
1834         }
1835
1836         /* Entry to report DMA RX/TX rings */
1837         stmmac_rings_status = debugfs_create_file("descriptors_status",
1838                                            S_IRUGO, stmmac_fs_dir, dev,
1839                                            &stmmac_rings_status_fops);
1840
1841         if (!stmmac_rings_status || IS_ERR(stmmac_rings_status)) {
1842                 pr_info("ERROR creating stmmac ring debugfs file\n");
1843                 debugfs_remove(stmmac_fs_dir);
1844
1845                 return -ENOMEM;
1846         }
1847
1848         /* Entry to report the DMA HW features */
1849         stmmac_dma_cap = debugfs_create_file("dma_cap", S_IRUGO, stmmac_fs_dir,
1850                                              dev, &stmmac_dma_cap_fops);
1851
1852         if (!stmmac_dma_cap || IS_ERR(stmmac_dma_cap)) {
1853                 pr_info("ERROR creating stmmac MMC debugfs file\n");
1854                 debugfs_remove(stmmac_rings_status);
1855                 debugfs_remove(stmmac_fs_dir);
1856
1857                 return -ENOMEM;
1858         }
1859
1860         return 0;
1861 }
1862
1863 static void stmmac_exit_fs(void)
1864 {
1865         debugfs_remove(stmmac_rings_status);
1866         debugfs_remove(stmmac_dma_cap);
1867         debugfs_remove(stmmac_fs_dir);
1868 }
1869 #endif /* CONFIG_STMMAC_DEBUG_FS */
1870
1871 static const struct net_device_ops stmmac_netdev_ops = {
1872         .ndo_open = stmmac_open,
1873         .ndo_start_xmit = stmmac_xmit,
1874         .ndo_stop = stmmac_release,
1875         .ndo_change_mtu = stmmac_change_mtu,
1876         .ndo_fix_features = stmmac_fix_features,
1877         .ndo_set_rx_mode = stmmac_set_rx_mode,
1878         .ndo_tx_timeout = stmmac_tx_timeout,
1879         .ndo_do_ioctl = stmmac_ioctl,
1880         .ndo_set_config = stmmac_config,
1881 #ifdef CONFIG_NET_POLL_CONTROLLER
1882         .ndo_poll_controller = stmmac_poll_controller,
1883 #endif
1884         .ndo_set_mac_address = eth_mac_addr,
1885 };
1886
1887 /**
1888  *  stmmac_hw_init - Init the MAC device
1889  *  @priv : pointer to the private device structure.
1890  *  Description: this function detects which MAC device
1891  *  (GMAC/MAC10-100) has to attached, checks the HW capability
1892  *  (if supported) and sets the driver's features (for example
1893  *  to use the ring or chaine mode or support the normal/enh
1894  *  descriptor structure).
1895  */
1896 static int stmmac_hw_init(struct stmmac_priv *priv)
1897 {
1898         int ret = 0;
1899         struct mac_device_info *mac;
1900
1901         /* Identify the MAC HW device */
1902         if (priv->plat->has_gmac) {
1903                 priv->dev->priv_flags |= IFF_UNICAST_FLT;
1904                 mac = dwmac1000_setup(priv->ioaddr);
1905         } else {
1906                 mac = dwmac100_setup(priv->ioaddr);
1907         }
1908         if (!mac)
1909                 return -ENOMEM;
1910
1911         priv->hw = mac;
1912
1913         /* Get and dump the chip ID */
1914         priv->synopsys_id = stmmac_get_synopsys_id(priv);
1915
1916         /* To use the chained or ring mode */
1917         if (chain_mode) {
1918                 priv->hw->chain = &chain_mode_ops;
1919                 pr_info(" Chain mode enabled\n");
1920                 priv->mode = STMMAC_CHAIN_MODE;
1921         } else {
1922                 priv->hw->ring = &ring_mode_ops;
1923                 pr_info(" Ring mode enabled\n");
1924                 priv->mode = STMMAC_RING_MODE;
1925         }
1926
1927         /* Get the HW capability (new GMAC newer than 3.50a) */
1928         priv->hw_cap_support = stmmac_get_hw_features(priv);
1929         if (priv->hw_cap_support) {
1930                 pr_info(" DMA HW capability register supported");
1931
1932                 /* We can override some gmac/dma configuration fields: e.g.
1933                  * enh_desc, tx_coe (e.g. that are passed through the
1934                  * platform) with the values from the HW capability
1935                  * register (if supported).
1936                  */
1937                 priv->plat->enh_desc = priv->dma_cap.enh_desc;
1938                 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up;
1939
1940                 priv->plat->tx_coe = priv->dma_cap.tx_coe;
1941
1942                 if (priv->dma_cap.rx_coe_type2)
1943                         priv->plat->rx_coe = STMMAC_RX_COE_TYPE2;
1944                 else if (priv->dma_cap.rx_coe_type1)
1945                         priv->plat->rx_coe = STMMAC_RX_COE_TYPE1;
1946
1947         } else
1948                 pr_info(" No HW DMA feature register supported");
1949
1950         /* Select the enhnaced/normal descriptor structures */
1951         stmmac_selec_desc_mode(priv);
1952
1953         /* Enable the IPC (Checksum Offload) and check if the feature has been
1954          * enabled during the core configuration. */
1955         ret = priv->hw->mac->rx_ipc(priv->ioaddr);
1956         if (!ret) {
1957                 pr_warning(" RX IPC Checksum Offload not configured.\n");
1958                 priv->plat->rx_coe = STMMAC_RX_COE_NONE;
1959         }
1960
1961         if (priv->plat->rx_coe)
1962                 pr_info(" RX Checksum Offload Engine supported (type %d)\n",
1963                         priv->plat->rx_coe);
1964         if (priv->plat->tx_coe)
1965                 pr_info(" TX Checksum insertion supported\n");
1966
1967         if (priv->plat->pmt) {
1968                 pr_info(" Wake-Up On Lan supported\n");
1969                 device_set_wakeup_capable(priv->device, 1);
1970         }
1971
1972         return ret;
1973 }
1974
1975 /**
1976  * stmmac_dvr_probe
1977  * @device: device pointer
1978  * @plat_dat: platform data pointer
1979  * @addr: iobase memory address
1980  * Description: this is the main probe function used to
1981  * call the alloc_etherdev, allocate the priv structure.
1982  */
1983 struct stmmac_priv *stmmac_dvr_probe(struct device *device,
1984                                      struct plat_stmmacenet_data *plat_dat,
1985                                      void __iomem *addr)
1986 {
1987         int ret = 0;
1988         struct net_device *ndev = NULL;
1989         struct stmmac_priv *priv;
1990
1991         ndev = alloc_etherdev(sizeof(struct stmmac_priv));
1992         if (!ndev)
1993                 return NULL;
1994
1995         SET_NETDEV_DEV(ndev, device);
1996
1997         priv = netdev_priv(ndev);
1998         priv->device = device;
1999         priv->dev = ndev;
2000
2001         ether_setup(ndev);
2002
2003         stmmac_set_ethtool_ops(ndev);
2004         priv->pause = pause;
2005         priv->plat = plat_dat;
2006         priv->ioaddr = addr;
2007         priv->dev->base_addr = (unsigned long)addr;
2008
2009         /* Verify driver arguments */
2010         stmmac_verify_args();
2011
2012         /* Override with kernel parameters if supplied XXX CRS XXX
2013          * this needs to have multiple instances */
2014         if ((phyaddr >= 0) && (phyaddr <= 31))
2015                 priv->plat->phy_addr = phyaddr;
2016
2017         /* Init MAC and get the capabilities */
2018         stmmac_hw_init(priv);
2019
2020         ndev->netdev_ops = &stmmac_netdev_ops;
2021
2022         ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2023                             NETIF_F_RXCSUM;
2024         ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA;
2025         ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
2026 #ifdef STMMAC_VLAN_TAG_USED
2027         /* Both mac100 and gmac support receive VLAN tag detection */
2028         ndev->features |= NETIF_F_HW_VLAN_RX;
2029 #endif
2030         priv->msg_enable = netif_msg_init(debug, default_msg_level);
2031
2032         if (flow_ctrl)
2033                 priv->flow_ctrl = FLOW_AUTO;    /* RX/TX pause on */
2034
2035         /* Rx Watchdog is available in the COREs newer than the 3.40.
2036          * In some case, for example on bugged HW this feature
2037          * has to be disable and this can be done by passing the
2038          * riwt_off field from the platform.
2039          */
2040         if ((priv->synopsys_id >= DWMAC_CORE_3_50) && (!priv->plat->riwt_off)) {
2041                 priv->use_riwt = 1;
2042                 pr_info(" Enable RX Mitigation via HW Watchdog Timer\n");
2043         }
2044
2045         netif_napi_add(ndev, &priv->napi, stmmac_poll, 64);
2046
2047         spin_lock_init(&priv->lock);
2048         spin_lock_init(&priv->tx_lock);
2049
2050         ret = register_netdev(ndev);
2051         if (ret) {
2052                 pr_err("%s: ERROR %i registering the device\n", __func__, ret);
2053                 goto error_netdev_register;
2054         }
2055
2056         priv->stmmac_clk = clk_get(priv->device, STMMAC_RESOURCE_NAME);
2057         if (IS_ERR(priv->stmmac_clk)) {
2058                 pr_warning("%s: warning: cannot get CSR clock\n", __func__);
2059                 goto error_clk_get;
2060         }
2061
2062         /* If a specific clk_csr value is passed from the platform
2063          * this means that the CSR Clock Range selection cannot be
2064          * changed at run-time and it is fixed. Viceversa the driver'll try to
2065          * set the MDC clock dynamically according to the csr actual
2066          * clock input.
2067          */
2068         if (!priv->plat->clk_csr)
2069                 stmmac_clk_csr_set(priv);
2070         else
2071                 priv->clk_csr = priv->plat->clk_csr;
2072
2073         /* MDIO bus Registration */
2074         ret = stmmac_mdio_register(ndev);
2075         if (ret < 0) {
2076                 pr_debug("%s: MDIO bus (id: %d) registration failed",
2077                          __func__, priv->plat->bus_id);
2078                 goto error_mdio_register;
2079         }
2080
2081         return priv;
2082
2083 error_mdio_register:
2084         clk_put(priv->stmmac_clk);
2085 error_clk_get:
2086         unregister_netdev(ndev);
2087 error_netdev_register:
2088         netif_napi_del(&priv->napi);
2089         free_netdev(ndev);
2090
2091         return NULL;
2092 }
2093
2094 /**
2095  * stmmac_dvr_remove
2096  * @ndev: net device pointer
2097  * Description: this function resets the TX/RX processes, disables the MAC RX/TX
2098  * changes the link status, releases the DMA descriptor rings.
2099  */
2100 int stmmac_dvr_remove(struct net_device *ndev)
2101 {
2102         struct stmmac_priv *priv = netdev_priv(ndev);
2103
2104         pr_info("%s:\n\tremoving driver", __func__);
2105
2106         priv->hw->dma->stop_rx(priv->ioaddr);
2107         priv->hw->dma->stop_tx(priv->ioaddr);
2108
2109         stmmac_set_mac(priv->ioaddr, false);
2110         stmmac_mdio_unregister(ndev);
2111         netif_carrier_off(ndev);
2112         unregister_netdev(ndev);
2113         free_netdev(ndev);
2114
2115         return 0;
2116 }
2117
2118 #ifdef CONFIG_PM
2119 int stmmac_suspend(struct net_device *ndev)
2120 {
2121         struct stmmac_priv *priv = netdev_priv(ndev);
2122         int dis_ic = 0;
2123         unsigned long flags;
2124
2125         if (!ndev || !netif_running(ndev))
2126                 return 0;
2127
2128         if (priv->phydev)
2129                 phy_stop(priv->phydev);
2130
2131         spin_lock_irqsave(&priv->lock, flags);
2132
2133         netif_device_detach(ndev);
2134         netif_stop_queue(ndev);
2135
2136         if (priv->use_riwt)
2137                 dis_ic = 1;
2138
2139         napi_disable(&priv->napi);
2140
2141         /* Stop TX/RX DMA */
2142         priv->hw->dma->stop_tx(priv->ioaddr);
2143         priv->hw->dma->stop_rx(priv->ioaddr);
2144         /* Clear the Rx/Tx descriptors */
2145         priv->hw->desc->init_rx_desc(priv->dma_rx, priv->dma_rx_size,
2146                                      dis_ic, priv->mode);
2147         priv->hw->desc->init_tx_desc(priv->dma_tx, priv->dma_tx_size,
2148                                      priv->mode);
2149
2150         /* Enable Power down mode by programming the PMT regs */
2151         if (device_may_wakeup(priv->device))
2152                 priv->hw->mac->pmt(priv->ioaddr, priv->wolopts);
2153         else {
2154                 stmmac_set_mac(priv->ioaddr, false);
2155                 /* Disable clock in case of PWM is off */
2156                 clk_disable_unprepare(priv->stmmac_clk);
2157         }
2158         spin_unlock_irqrestore(&priv->lock, flags);
2159         return 0;
2160 }
2161
2162 int stmmac_resume(struct net_device *ndev)
2163 {
2164         struct stmmac_priv *priv = netdev_priv(ndev);
2165         unsigned long flags;
2166
2167         if (!netif_running(ndev))
2168                 return 0;
2169
2170         spin_lock_irqsave(&priv->lock, flags);
2171
2172         /* Power Down bit, into the PM register, is cleared
2173          * automatically as soon as a magic packet or a Wake-up frame
2174          * is received. Anyway, it's better to manually clear
2175          * this bit because it can generate problems while resuming
2176          * from another devices (e.g. serial console). */
2177         if (device_may_wakeup(priv->device))
2178                 priv->hw->mac->pmt(priv->ioaddr, 0);
2179         else
2180                 /* enable the clk prevously disabled */
2181                 clk_prepare_enable(priv->stmmac_clk);
2182
2183         netif_device_attach(ndev);
2184
2185         /* Enable the MAC and DMA */
2186         stmmac_set_mac(priv->ioaddr, true);
2187         priv->hw->dma->start_tx(priv->ioaddr);
2188         priv->hw->dma->start_rx(priv->ioaddr);
2189
2190         napi_enable(&priv->napi);
2191
2192         netif_start_queue(ndev);
2193
2194         spin_unlock_irqrestore(&priv->lock, flags);
2195
2196         if (priv->phydev)
2197                 phy_start(priv->phydev);
2198
2199         return 0;
2200 }
2201
2202 int stmmac_freeze(struct net_device *ndev)
2203 {
2204         if (!ndev || !netif_running(ndev))
2205                 return 0;
2206
2207         return stmmac_release(ndev);
2208 }
2209
2210 int stmmac_restore(struct net_device *ndev)
2211 {
2212         if (!ndev || !netif_running(ndev))
2213                 return 0;
2214
2215         return stmmac_open(ndev);
2216 }
2217 #endif /* CONFIG_PM */
2218
2219 /* Driver can be configured w/ and w/ both PCI and Platf drivers
2220  * depending on the configuration selected.
2221  */
2222 static int __init stmmac_init(void)
2223 {
2224         int ret;
2225
2226         ret = stmmac_register_platform();
2227         if (ret)
2228                 goto err;
2229         ret = stmmac_register_pci();
2230         if (ret)
2231                 goto err_pci;
2232         return 0;
2233 err_pci:
2234         stmmac_unregister_platform();
2235 err:
2236         pr_err("stmmac: driver registration failed\n");
2237         return ret;
2238 }
2239
2240 static void __exit stmmac_exit(void)
2241 {
2242         stmmac_unregister_platform();
2243         stmmac_unregister_pci();
2244 }
2245
2246 module_init(stmmac_init);
2247 module_exit(stmmac_exit);
2248
2249 #ifndef MODULE
2250 static int __init stmmac_cmdline_opt(char *str)
2251 {
2252         char *opt;
2253
2254         if (!str || !*str)
2255                 return -EINVAL;
2256         while ((opt = strsep(&str, ",")) != NULL) {
2257                 if (!strncmp(opt, "debug:", 6)) {
2258                         if (kstrtoint(opt + 6, 0, &debug))
2259                                 goto err;
2260                 } else if (!strncmp(opt, "phyaddr:", 8)) {
2261                         if (kstrtoint(opt + 8, 0, &phyaddr))
2262                                 goto err;
2263                 } else if (!strncmp(opt, "dma_txsize:", 11)) {
2264                         if (kstrtoint(opt + 11, 0, &dma_txsize))
2265                                 goto err;
2266                 } else if (!strncmp(opt, "dma_rxsize:", 11)) {
2267                         if (kstrtoint(opt + 11, 0, &dma_rxsize))
2268                                 goto err;
2269                 } else if (!strncmp(opt, "buf_sz:", 7)) {
2270                         if (kstrtoint(opt + 7, 0, &buf_sz))
2271                                 goto err;
2272                 } else if (!strncmp(opt, "tc:", 3)) {
2273                         if (kstrtoint(opt + 3, 0, &tc))
2274                                 goto err;
2275                 } else if (!strncmp(opt, "watchdog:", 9)) {
2276                         if (kstrtoint(opt + 9, 0, &watchdog))
2277                                 goto err;
2278                 } else if (!strncmp(opt, "flow_ctrl:", 10)) {
2279                         if (kstrtoint(opt + 10, 0, &flow_ctrl))
2280                                 goto err;
2281                 } else if (!strncmp(opt, "pause:", 6)) {
2282                         if (kstrtoint(opt + 6, 0, &pause))
2283                                 goto err;
2284                 } else if (!strncmp(opt, "eee_timer:", 10)) {
2285                         if (kstrtoint(opt + 10, 0, &eee_timer))
2286                                 goto err;
2287                 } else if (!strncmp(opt, "chain_mode:", 11)) {
2288                         if (kstrtoint(opt + 11, 0, &chain_mode))
2289                                 goto err;
2290                 }
2291         }
2292         return 0;
2293
2294 err:
2295         pr_err("%s: ERROR broken module parameter conversion", __func__);
2296         return -EINVAL;
2297 }
2298
2299 __setup("stmmaceth=", stmmac_cmdline_opt);
2300 #endif
2301
2302 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver");
2303 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
2304 MODULE_LICENSE("GPL");