drivers/net/ethernet/stmicro/stmmac/stmmac_main.c

   1 /*******************************************************************************
   2   This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
   3   ST Ethernet IPs are built around a Synopsys IP Core.
   4
   5         Copyright(C) 2007-2011 STMicroelectronics Ltd
   6
   7   This program is free software; you can redistribute it and/or modify it
   8   under the terms and conditions of the GNU General Public License,
   9   version 2, as published by the Free Software Foundation.
  10
  11   This program is distributed in the hope it will be useful, but WITHOUT
  12   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14   more details.
  15
  16   You should have received a copy of the GNU General Public License along with
  17   this program; if not, write to the Free Software Foundation, Inc.,
  18   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  19
  20   The full GNU General Public License is included in this distribution in
  21   the file called "COPYING".
  22
  23   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
  24
  25   Documentation available at:
  26         http://www.stlinux.com
  27   Support available at:
  28         https://bugzilla.stlinux.com/
  29 *******************************************************************************/
  30
  31 #include <linux/clk.h>
  32 #include <linux/kernel.h>
  33 #include <linux/interrupt.h>
  34 #include <linux/ip.h>
  35 #include <linux/tcp.h>
  36 #include <linux/skbuff.h>
  37 #include <linux/ethtool.h>
  38 #include <linux/if_ether.h>
  39 #include <linux/crc32.h>
  40 #include <linux/mii.h>
  41 #include <linux/if.h>
  42 #include <linux/if_vlan.h>
  43 #include <linux/dma-mapping.h>
  44 #include <linux/slab.h>
  45 #include <linux/prefetch.h>
  46 #ifdef CONFIG_STMMAC_DEBUG_FS
  47 #include <linux/debugfs.h>
  48 #include <linux/seq_file.h>
  49 #endif
  50 #include <linux/net_tstamp.h>
  51 #include "stmmac_ptp.h"
  52 #include "stmmac.h"
  53
  54 #undef STMMAC_DEBUG
  55 /*#define STMMAC_DEBUG*/
  56 #ifdef STMMAC_DEBUG
  57 #define DBG(nlevel, klevel, fmt, args...) \
  58                 ((void)(netif_msg_##nlevel(priv) && \
  59                 printk(KERN_##klevel fmt, ## args)))
  60 #else
  61 #define DBG(nlevel, klevel, fmt, args...) do { } while (0)
  62 #endif
  63
  64 #undef STMMAC_RX_DEBUG
  65 /*#define STMMAC_RX_DEBUG*/
  66 #ifdef STMMAC_RX_DEBUG
  67 #define RX_DBG(fmt, args...)  printk(fmt, ## args)
  68 #else
  69 #define RX_DBG(fmt, args...)  do { } while (0)
  70 #endif
  71
  72 #undef STMMAC_XMIT_DEBUG
  73 /*#define STMMAC_XMIT_DEBUG*/
  74 #ifdef STMMAC_XMIT_DEBUG
  75 #define TX_DBG(fmt, args...)  printk(fmt, ## args)
  76 #else
  77 #define TX_DBG(fmt, args...)  do { } while (0)
  78 #endif
  79
  80 #define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x)
  81 #define JUMBO_LEN       9000
  82
  83 /* Module parameters */
  84 #define TX_TIMEO 5000 /* default 5 seconds */
  85 static int watchdog = TX_TIMEO;
  86 module_param(watchdog, int, S_IRUGO | S_IWUSR);
  87 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds");
  88
  89 static int debug = -1;          /* -1: default, 0: no output, 16:  all */
  90 module_param(debug, int, S_IRUGO | S_IWUSR);
  91 MODULE_PARM_DESC(debug, "Message Level (0: no output, 16: all)");
  92
  93 int phyaddr = -1;
  94 module_param(phyaddr, int, S_IRUGO);
  95 MODULE_PARM_DESC(phyaddr, "Physical device address");
  96
  97 #define DMA_TX_SIZE 256
  98 static int dma_txsize = DMA_TX_SIZE;
  99 module_param(dma_txsize, int, S_IRUGO | S_IWUSR);
 100 MODULE_PARM_DESC(dma_txsize, "Number of descriptors in the TX list");
 101
 102 #define DMA_RX_SIZE 256
 103 static int dma_rxsize = DMA_RX_SIZE;
 104 module_param(dma_rxsize, int, S_IRUGO | S_IWUSR);
 105 MODULE_PARM_DESC(dma_rxsize, "Number of descriptors in the RX list");
 106
 107 static int flow_ctrl = FLOW_OFF;
 108 module_param(flow_ctrl, int, S_IRUGO | S_IWUSR);
 109 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]");
 110
 111 static int pause = PAUSE_TIME;
 112 module_param(pause, int, S_IRUGO | S_IWUSR);
 113 MODULE_PARM_DESC(pause, "Flow Control Pause Time");
 114
 115 #define TC_DEFAULT 64
 116 static int tc = TC_DEFAULT;
 117 module_param(tc, int, S_IRUGO | S_IWUSR);
 118 MODULE_PARM_DESC(tc, "DMA threshold control value");
 119
 120 #define DMA_BUFFER_SIZE BUF_SIZE_2KiB
 121 static int buf_sz = DMA_BUFFER_SIZE;
 122 module_param(buf_sz, int, S_IRUGO | S_IWUSR);
 123 MODULE_PARM_DESC(buf_sz, "DMA buffer size");
 124
 125 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
 126                                       NETIF_MSG_LINK | NETIF_MSG_IFUP |
 127                                       NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);
 128
 129 #define STMMAC_DEFAULT_LPI_TIMER        1000
 130 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER;
 131 module_param(eee_timer, int, S_IRUGO | S_IWUSR);
 132 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec");
 133 #define STMMAC_LPI_TIMER(x) (jiffies + msecs_to_jiffies(x))
 134
 135 /* By default the driver will use the ring mode to manage tx and rx descriptors
 136  * but passing this value so user can force to use the chain instead of the ring
 137  */
 138 static unsigned int chain_mode;
 139 module_param(chain_mode, int, S_IRUGO);
 140 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode");
 141
 142 static irqreturn_t stmmac_interrupt(int irq, void *dev_id);
 143
 144 #ifdef CONFIG_STMMAC_DEBUG_FS
 145 static int stmmac_init_fs(struct net_device *dev);
 146 static void stmmac_exit_fs(void);
 147 #endif
 148
 149 #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x))
 150
 151 /**
 152  * stmmac_verify_args - verify the driver parameters.
 153  * Description: it verifies if some wrong parameter is passed to the driver.
 154  * Note that wrong parameters are replaced with the default values.
 155  */
 156 static void stmmac_verify_args(void)
 157 {
 158         if (unlikely(watchdog < 0))
 159                 watchdog = TX_TIMEO;
 160         if (unlikely(dma_rxsize < 0))
 161                 dma_rxsize = DMA_RX_SIZE;
 162         if (unlikely(dma_txsize < 0))
 163                 dma_txsize = DMA_TX_SIZE;
 164         if (unlikely((buf_sz < DMA_BUFFER_SIZE) || (buf_sz > BUF_SIZE_16KiB)))
 165                 buf_sz = DMA_BUFFER_SIZE;
 166         if (unlikely(flow_ctrl > 1))
 167                 flow_ctrl = FLOW_AUTO;
 168         else if (likely(flow_ctrl < 0))
 169                 flow_ctrl = FLOW_OFF;
 170         if (unlikely((pause < 0) || (pause > 0xffff)))
 171                 pause = PAUSE_TIME;
 172         if (eee_timer < 0)
 173                 eee_timer = STMMAC_DEFAULT_LPI_TIMER;
 174 }
 175
 176 static void stmmac_clk_csr_set(struct stmmac_priv *priv)
 177 {
 178         u32 clk_rate;
 179
 180         clk_rate = clk_get_rate(priv->stmmac_clk);
 181
 182         /* Platform provided default clk_csr would be assumed valid
 183          * for all other cases except for the below mentioned ones. */
 184         if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) {
 185                 if (clk_rate < CSR_F_35M)
 186                         priv->clk_csr = STMMAC_CSR_20_35M;
 187                 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M))
 188                         priv->clk_csr = STMMAC_CSR_35_60M;
 189                 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M))
 190                         priv->clk_csr = STMMAC_CSR_60_100M;
 191                 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M))
 192                         priv->clk_csr = STMMAC_CSR_100_150M;
 193                 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M))
 194                         priv->clk_csr = STMMAC_CSR_150_250M;
 195                 else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M))
 196                         priv->clk_csr = STMMAC_CSR_250_300M;
 197         } /* For values higher than the IEEE 802.3 specified frequency
 198            * we can not estimate the proper divider as it is not known
 199            * the frequency of clk_csr_i. So we do not change the default
 200            * divider. */
 201 }
 202
 203 #if defined(STMMAC_XMIT_DEBUG) || defined(STMMAC_RX_DEBUG)
 204 static void print_pkt(unsigned char *buf, int len)
 205 {
 206         int j;
 207         pr_info("len = %d byte, buf addr: 0x%p", len, buf);
 208         for (j = 0; j < len; j++) {
 209                 if ((j % 16) == 0)
 210                         pr_info("\n %03x:", j);
 211                 pr_info(" %02x", buf[j]);
 212         }
 213         pr_info("\n");
 214 }
 215 #endif
 216
 217 /* minimum number of free TX descriptors required to wake up TX process */
 218 #define STMMAC_TX_THRESH(x)     (x->dma_tx_size/4)
 219
 220 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv)
 221 {
 222         return priv->dirty_tx + priv->dma_tx_size - priv->cur_tx - 1;
 223 }
 224
 225 /* On some ST platforms, some HW system configuraton registers have to be
 226  * set according to the link speed negotiated.
 227  */
 228 static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv *priv)
 229 {
 230         struct phy_device *phydev = priv->phydev;
 231
 232         if (likely(priv->plat->fix_mac_speed))
 233                 priv->plat->fix_mac_speed(priv->plat->bsp_priv,
 234                                           phydev->speed);
 235 }
 236
 237 static void stmmac_enable_eee_mode(struct stmmac_priv *priv)
 238 {
 239         /* Check and enter in LPI mode */
 240         if ((priv->dirty_tx == priv->cur_tx) &&
 241             (priv->tx_path_in_lpi_mode == false))
 242                 priv->hw->mac->set_eee_mode(priv->ioaddr);
 243 }
 244
 245 void stmmac_disable_eee_mode(struct stmmac_priv *priv)
 246 {
 247         /* Exit and disable EEE in case of we are are in LPI state. */
 248         priv->hw->mac->reset_eee_mode(priv->ioaddr);
 249         del_timer_sync(&priv->eee_ctrl_timer);
 250         priv->tx_path_in_lpi_mode = false;
 251 }
 252
 253 /**
 254  * stmmac_eee_ctrl_timer
 255  * @arg : data hook
 256  * Description:
 257  *  If there is no data transfer and if we are not in LPI state,
 258  *  then MAC Transmitter can be moved to LPI state.
 259  */
 260 static void stmmac_eee_ctrl_timer(unsigned long arg)
 261 {
 262         struct stmmac_priv *priv = (struct stmmac_priv *)arg;
 263
 264         stmmac_enable_eee_mode(priv);
 265         mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_TIMER(eee_timer));
 266 }
 267
 268 /**
 269  * stmmac_eee_init
 270  * @priv: private device pointer
 271  * Description:
 272  *  If the EEE support has been enabled while configuring the driver,
 273  *  if the GMAC actually supports the EEE (from the HW cap reg) and the
 274  *  phy can also manage EEE, so enable the LPI state and start the timer
 275  *  to verify if the tx path can enter in LPI state.
 276  */
 277 bool stmmac_eee_init(struct stmmac_priv *priv)
 278 {
 279         bool ret = false;
 280
 281         /* MAC core supports the EEE feature. */
 282         if (priv->dma_cap.eee) {
 283                 /* Check if the PHY supports EEE */
 284                 if (phy_init_eee(priv->phydev, 1))
 285                         goto out;
 286
 287                 priv->eee_active = 1;
 288                 init_timer(&priv->eee_ctrl_timer);
 289                 priv->eee_ctrl_timer.function = stmmac_eee_ctrl_timer;
 290                 priv->eee_ctrl_timer.data = (unsigned long)priv;
 291                 priv->eee_ctrl_timer.expires = STMMAC_LPI_TIMER(eee_timer);
 292                 add_timer(&priv->eee_ctrl_timer);
 293
 294                 priv->hw->mac->set_eee_timer(priv->ioaddr,
 295                                              STMMAC_DEFAULT_LIT_LS_TIMER,
 296                                              priv->tx_lpi_timer);
 297
 298                 pr_info("stmmac: Energy-Efficient Ethernet initialized\n");
 299
 300                 ret = true;
 301         }
 302 out:
 303         return ret;
 304 }
 305
 306 static void stmmac_eee_adjust(struct stmmac_priv *priv)
 307 {
 308         /* When the EEE has been already initialised we have to
 309          * modify the PLS bit in the LPI ctrl & status reg according
 310          * to the PHY link status. For this reason.
 311          */
 312         if (priv->eee_enabled)
 313                 priv->hw->mac->set_eee_pls(priv->ioaddr, priv->phydev->link);
 314 }
 315
 316 /* stmmac_get_tx_hwtstamp:
 317  * @priv : pointer to private device structure.
 318  * @entry : descriptor index to be used.
 319  * @skb : the socket buffer
 320  * Description :
 321  * This function will read timestamp from the descriptor & pass it to stack.
 322  * and also perform some sanity checks.
 323  */
 324 static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv,
 325                                    unsigned int entry,
 326                                    struct sk_buff *skb)
 327 {
 328         struct skb_shared_hwtstamps shhwtstamp;
 329         u64 ns;
 330         void *desc = NULL;
 331
 332         if (!priv->hwts_tx_en)
 333                 return;
 334
 335         /* if skb doesn't support hw tstamp */
 336         if (likely(!(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)))
 337                 return;
 338
 339         if (priv->adv_ts)
 340                 desc = (priv->dma_etx + entry);
 341         else
 342                 desc = (priv->dma_tx + entry);
 343
 344         /* check tx tstamp status */
 345         if (!priv->hw->desc->get_tx_timestamp_status((struct dma_desc *)desc))
 346                 return;
 347
 348         /* get the valid tstamp */
 349         ns = priv->hw->desc->get_timestamp(desc, priv->adv_ts);
 350
 351         memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
 352         shhwtstamp.hwtstamp = ns_to_ktime(ns);
 353         /* pass tstamp to stack */
 354         skb_tstamp_tx(skb, &shhwtstamp);
 355
 356         return;
 357 }
 358
 359 /* stmmac_get_rx_hwtstamp:
 360  * @priv : pointer to private device structure.
 361  * @entry : descriptor index to be used.
 362  * @skb : the socket buffer
 363  * Description :
 364  * This function will read received packet's timestamp from the descriptor
 365  * and pass it to stack. It also perform some sanity checks.
 366  */
 367 static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv,
 368                                    unsigned int entry,
 369                                    struct sk_buff *skb)
 370 {
 371         struct skb_shared_hwtstamps *shhwtstamp = NULL;
 372         u64 ns;
 373         void *desc = NULL;
 374
 375         if (!priv->hwts_rx_en)
 376                 return;
 377
 378         if (priv->adv_ts)
 379                 desc = (priv->dma_erx + entry);
 380         else
 381                 desc = (priv->dma_rx + entry);
 382
 383         /* if rx tstamp is not valid */
 384         if (!priv->hw->desc->get_rx_timestamp_status(desc, priv->adv_ts))
 385                 return;
 386
 387         /* get valid tstamp */
 388         ns = priv->hw->desc->get_timestamp(desc, priv->adv_ts);
 389         shhwtstamp = skb_hwtstamps(skb);
 390         memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
 391         shhwtstamp->hwtstamp = ns_to_ktime(ns);
 392 }
 393
 394 /**
 395  *  stmmac_hwtstamp_ioctl - control hardware timestamping.
 396  *  @dev: device pointer.
 397  *  @ifr: An IOCTL specefic structure, that can contain a pointer to
 398  *  a proprietary structure used to pass information to the driver.
 399  *  Description:
 400  *  This function configures the MAC to enable/disable both outgoing(TX)
 401  *  and incoming(RX) packets time stamping based on user input.
 402  *  Return Value:
 403  *  0 on success and an appropriate -ve integer on failure.
 404  */
 405 static int stmmac_hwtstamp_ioctl(struct net_device *dev, struct ifreq *ifr)
 406 {
 407         struct stmmac_priv *priv = netdev_priv(dev);
 408         struct hwtstamp_config config;
 409         struct timespec now;
 410         u64 temp = 0;
 411         u32 ptp_v2 = 0;
 412         u32 tstamp_all = 0;
 413         u32 ptp_over_ipv4_udp = 0;
 414         u32 ptp_over_ipv6_udp = 0;
 415         u32 ptp_over_ethernet = 0;
 416         u32 snap_type_sel = 0;
 417         u32 ts_master_en = 0;
 418         u32 ts_event_en = 0;
 419         u32 value = 0;
 420
 421         if (!(priv->dma_cap.time_stamp || priv->adv_ts)) {
 422                 netdev_alert(priv->dev, "No support for HW time stamping\n");
 423                 priv->hwts_tx_en = 0;
 424                 priv->hwts_rx_en = 0;
 425
 426                 return -EOPNOTSUPP;
 427         }
 428
 429         if (copy_from_user(&config, ifr->ifr_data,
 430                 sizeof(struct hwtstamp_config)))
 431                 return -EFAULT;
 432
 433         pr_debug("%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n",
 434                  __func__, config.flags, config.tx_type, config.rx_filter);
 435
 436         /* reserved for future extensions */
 437         if (config.flags)
 438                 return -EINVAL;
 439
 440         switch (config.tx_type) {
 441         case HWTSTAMP_TX_OFF:
 442                 priv->hwts_tx_en = 0;
 443                 break;
 444         case HWTSTAMP_TX_ON:
 445                 priv->hwts_tx_en = 1;
 446                 break;
 447         default:
 448                 return -ERANGE;
 449         }
 450
 451         if (priv->adv_ts) {
 452                 switch (config.rx_filter) {
 453                 /* time stamp no incoming packet at all */
 454                 case HWTSTAMP_FILTER_NONE:
 455                         config.rx_filter = HWTSTAMP_FILTER_NONE;
 456                         break;
 457
 458                 /* PTP v1, UDP, any kind of event packet */
 459                 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
 460                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
 461                         /* take time stamp for all event messages */
 462                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
 463
 464                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 465                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 466                         break;
 467
 468                 /* PTP v1, UDP, Sync packet */
 469                 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
 470                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC;
 471                         /* take time stamp for SYNC messages only */
 472                         ts_event_en = PTP_TCR_TSEVNTENA;
 473
 474                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 475                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 476                         break;
 477
 478                 /* PTP v1, UDP, Delay_req packet */
 479                 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
 480                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ;
 481                         /* take time stamp for Delay_Req messages only */
 482                         ts_master_en = PTP_TCR_TSMSTRENA;
 483                         ts_event_en = PTP_TCR_TSEVNTENA;
 484
 485                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 486                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 487                         break;
 488
 489                 /* PTP v2, UDP, any kind of event packet */
 490                 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
 491                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
 492                         ptp_v2 = PTP_TCR_TSVER2ENA;
 493                         /* take time stamp for all event messages */
 494                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
 495
 496                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 497                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 498                         break;
 499
 500                 /* PTP v2, UDP, Sync packet */
 501                 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
 502                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC;
 503                         ptp_v2 = PTP_TCR_TSVER2ENA;
 504                         /* take time stamp for SYNC messages only */
 505                         ts_event_en = PTP_TCR_TSEVNTENA;
 506
 507                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 508                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 509                         break;
 510
 511                 /* PTP v2, UDP, Delay_req packet */
 512                 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
 513                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ;
 514                         ptp_v2 = PTP_TCR_TSVER2ENA;
 515                         /* take time stamp for Delay_Req messages only */
 516                         ts_master_en = PTP_TCR_TSMSTRENA;
 517                         ts_event_en = PTP_TCR_TSEVNTENA;
 518
 519                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 520                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 521                         break;
 522
 523                 /* PTP v2/802.AS1, any layer, any kind of event packet */
 524                 case HWTSTAMP_FILTER_PTP_V2_EVENT:
 525                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
 526                         ptp_v2 = PTP_TCR_TSVER2ENA;
 527                         /* take time stamp for all event messages */
 528                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
 529
 530                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 531                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 532                         ptp_over_ethernet = PTP_TCR_TSIPENA;
 533                         break;
 534
 535                 /* PTP v2/802.AS1, any layer, Sync packet */
 536                 case HWTSTAMP_FILTER_PTP_V2_SYNC:
 537                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC;
 538                         ptp_v2 = PTP_TCR_TSVER2ENA;
 539                         /* take time stamp for SYNC messages only */
 540                         ts_event_en = PTP_TCR_TSEVNTENA;
 541
 542                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 543                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 544                         ptp_over_ethernet = PTP_TCR_TSIPENA;
 545                         break;
 546
 547                 /* PTP v2/802.AS1, any layer, Delay_req packet */
 548                 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
 549                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ;
 550                         ptp_v2 = PTP_TCR_TSVER2ENA;
 551                         /* take time stamp for Delay_Req messages only */
 552                         ts_master_en = PTP_TCR_TSMSTRENA;
 553                         ts_event_en = PTP_TCR_TSEVNTENA;
 554
 555                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 556                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 557                         ptp_over_ethernet = PTP_TCR_TSIPENA;
 558                         break;
 559
 560                 /* time stamp any incoming packet */
 561                 case HWTSTAMP_FILTER_ALL:
 562                         config.rx_filter = HWTSTAMP_FILTER_ALL;
 563                         tstamp_all = PTP_TCR_TSENALL;
 564                         break;
 565
 566                 default:
 567                         return -ERANGE;
 568                 }
 569         } else {
 570                 switch (config.rx_filter) {
 571                 case HWTSTAMP_FILTER_NONE:
 572                         config.rx_filter = HWTSTAMP_FILTER_NONE;
 573                         break;
 574                 default:
 575                         /* PTP v1, UDP, any kind of event packet */
 576                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
 577                         break;
 578                 }
 579         }
 580         priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1);
 581
 582         if (!priv->hwts_tx_en && !priv->hwts_rx_en)
 583                 priv->hw->ptp->config_hw_tstamping(priv->ioaddr, 0);
 584         else {
 585                 value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSCTRLSSR |
 586                         tstamp_all | ptp_v2 | ptp_over_ethernet |
 587                         ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en |
 588                         ts_master_en | snap_type_sel);
 589
 590                 priv->hw->ptp->config_hw_tstamping(priv->ioaddr, value);
 591
 592                 /* program Sub Second Increment reg */
 593                 priv->hw->ptp->config_sub_second_increment(priv->ioaddr);
 594
 595                 /* calculate default added value:
 596                  * formula is :
 597                  * addend = (2^32)/freq_div_ratio;
 598                  * where, freq_div_ratio = STMMAC_SYSCLOCK/50MHz
 599                  * hence, addend = ((2^32) * 50MHz)/STMMAC_SYSCLOCK;
 600                  * NOTE: STMMAC_SYSCLOCK should be >= 50MHz to
 601                  *       achive 20ns accuracy.
 602                  *
 603                  * 2^x * y == (y << x), hence
 604                  * 2^32 * 50000000 ==> (50000000 << 32)
 605                  */
 606                 temp = (u64)(50000000ULL << 32);
 607                 priv->default_addend = div_u64(temp, STMMAC_SYSCLOCK);
 608                 priv->hw->ptp->config_addend(priv->ioaddr,
 609                                              priv->default_addend);
 610
 611                 /* initialize system time */
 612                 getnstimeofday(&now);
 613                 priv->hw->ptp->init_systime(priv->ioaddr, now.tv_sec,
 614                                             now.tv_nsec);
 615         }
 616
 617         return copy_to_user(ifr->ifr_data, &config,
 618                             sizeof(struct hwtstamp_config)) ? -EFAULT : 0;
 619 }
 620
 621 static void stmmac_init_ptp(struct stmmac_priv *priv)
 622 {
 623         if (priv->dma_cap.time_stamp) {
 624                 pr_debug("IEEE 1588-2002 Time Stamp supported\n");
 625                 priv->adv_ts = 0;
 626         }
 627         if (priv->dma_cap.atime_stamp && priv->extend_desc) {
 628                 pr_debug("IEEE 1588-2008 Advanced Time Stamp supported\n");
 629                 priv->adv_ts = 1;
 630         }
 631
 632         priv->hw->ptp = &stmmac_ptp;
 633         priv->hwts_tx_en = 0;
 634         priv->hwts_rx_en = 0;
 635 }
 636
 637 /**
 638  * stmmac_adjust_link
 639  * @dev: net device structure
 640  * Description: it adjusts the link parameters.
 641  */
 642 static void stmmac_adjust_link(struct net_device *dev)
 643 {
 644         struct stmmac_priv *priv = netdev_priv(dev);
 645         struct phy_device *phydev = priv->phydev;
 646         unsigned long flags;
 647         int new_state = 0;
 648         unsigned int fc = priv->flow_ctrl, pause_time = priv->pause;
 649
 650         if (phydev == NULL)
 651                 return;
 652
 653         DBG(probe, DEBUG, "stmmac_adjust_link: called.  address %d link %d\n",
 654             phydev->addr, phydev->link);
 655
 656         spin_lock_irqsave(&priv->lock, flags);
 657
 658         if (phydev->link) {
 659                 u32 ctrl = readl(priv->ioaddr + MAC_CTRL_REG);
 660
 661                 /* Now we make sure that we can be in full duplex mode.
 662                  * If not, we operate in half-duplex mode. */
 663                 if (phydev->duplex != priv->oldduplex) {
 664                         new_state = 1;
 665                         if (!(phydev->duplex))
 666                                 ctrl &= ~priv->hw->link.duplex;
 667                         else
 668                                 ctrl |= priv->hw->link.duplex;
 669                         priv->oldduplex = phydev->duplex;
 670                 }
 671                 /* Flow Control operation */
 672                 if (phydev->pause)
 673                         priv->hw->mac->flow_ctrl(priv->ioaddr, phydev->duplex,
 674                                                  fc, pause_time);
 675
 676                 if (phydev->speed != priv->speed) {
 677                         new_state = 1;
 678                         switch (phydev->speed) {
 679                         case 1000:
 680                                 if (likely(priv->plat->has_gmac))
 681                                         ctrl &= ~priv->hw->link.port;
 682                                         stmmac_hw_fix_mac_speed(priv);
 683                                 break;
 684                         case 100:
 685                         case 10:
 686                                 if (priv->plat->has_gmac) {
 687                                         ctrl |= priv->hw->link.port;
 688                                         if (phydev->speed == SPEED_100) {
 689                                                 ctrl |= priv->hw->link.speed;
 690                                         } else {
 691                                                 ctrl &= ~(priv->hw->link.speed);
 692                                         }
 693                                 } else {
 694                                         ctrl &= ~priv->hw->link.port;
 695                                 }
 696                                 stmmac_hw_fix_mac_speed(priv);
 697                                 break;
 698                         default:
 699                                 if (netif_msg_link(priv))
 700                                         pr_warning("%s: Speed (%d) is not 10"
 701                                        " or 100!\n", dev->name, phydev->speed);
 702                                 break;
 703                         }
 704
 705                         priv->speed = phydev->speed;
 706                 }
 707
 708                 writel(ctrl, priv->ioaddr + MAC_CTRL_REG);
 709
 710                 if (!priv->oldlink) {
 711                         new_state = 1;
 712                         priv->oldlink = 1;
 713                 }
 714         } else if (priv->oldlink) {
 715                 new_state = 1;
 716                 priv->oldlink = 0;
 717                 priv->speed = 0;
 718                 priv->oldduplex = -1;
 719         }
 720
 721         if (new_state && netif_msg_link(priv))
 722                 phy_print_status(phydev);
 723
 724         stmmac_eee_adjust(priv);
 725
 726         spin_unlock_irqrestore(&priv->lock, flags);
 727
 728         DBG(probe, DEBUG, "stmmac_adjust_link: exiting\n");
 729 }
 730
 731 static void stmmac_check_pcs_mode(struct stmmac_priv *priv)
 732 {
 733         int interface = priv->plat->interface;
 734
 735         if (priv->dma_cap.pcs) {
 736                 if ((interface & PHY_INTERFACE_MODE_RGMII) ||
 737                     (interface & PHY_INTERFACE_MODE_RGMII_ID) ||
 738                     (interface & PHY_INTERFACE_MODE_RGMII_RXID) ||
 739                     (interface & PHY_INTERFACE_MODE_RGMII_TXID)) {
 740                         pr_debug("STMMAC: PCS RGMII support enable\n");
 741                         priv->pcs = STMMAC_PCS_RGMII;
 742                 } else if (interface & PHY_INTERFACE_MODE_SGMII) {
 743                         pr_debug("STMMAC: PCS SGMII support enable\n");
 744                         priv->pcs = STMMAC_PCS_SGMII;
 745                 }
 746         }
 747 }
 748
 749 /**
 750  * stmmac_init_phy - PHY initialization
 751  * @dev: net device structure
 752  * Description: it initializes the driver's PHY state, and attaches the PHY
 753  * to the mac driver.
 754  *  Return value:
 755  *  0 on success
 756  */
 757 static int stmmac_init_phy(struct net_device *dev)
 758 {
 759         struct stmmac_priv *priv = netdev_priv(dev);
 760         struct phy_device *phydev;
 761         char phy_id_fmt[MII_BUS_ID_SIZE + 3];
 762         char bus_id[MII_BUS_ID_SIZE];
 763         int interface = priv->plat->interface;
 764         priv->oldlink = 0;
 765         priv->speed = 0;
 766         priv->oldduplex = -1;
 767
 768         if (priv->plat->phy_bus_name)
 769                 snprintf(bus_id, MII_BUS_ID_SIZE, "%s-%x",
 770                                 priv->plat->phy_bus_name, priv->plat->bus_id);
 771         else
 772                 snprintf(bus_id, MII_BUS_ID_SIZE, "stmmac-%x",
 773                                 priv->plat->bus_id);
 774
 775         snprintf(phy_id_fmt, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id,
 776                  priv->plat->phy_addr);
 777         pr_debug("stmmac_init_phy:  trying to attach to %s\n", phy_id_fmt);
 778
 779         phydev = phy_connect(dev, phy_id_fmt, &stmmac_adjust_link, interface);
 780
 781         if (IS_ERR(phydev)) {
 782                 pr_err("%s: Could not attach to PHY\n", dev->name);
 783                 return PTR_ERR(phydev);
 784         }
 785
 786         /* Stop Advertising 1000BASE Capability if interface is not GMII */
 787         if ((interface == PHY_INTERFACE_MODE_MII) ||
 788             (interface == PHY_INTERFACE_MODE_RMII))
 789                 phydev->advertising &= ~(SUPPORTED_1000baseT_Half |
 790                                          SUPPORTED_1000baseT_Full);
 791
 792         /*
 793          * Broken HW is sometimes missing the pull-up resistor on the
 794          * MDIO line, which results in reads to non-existent devices returning
 795          * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent
 796          * device as well.
 797          * Note: phydev->phy_id is the result of reading the UID PHY registers.
 798          */
 799         if (phydev->phy_id == 0) {
 800                 phy_disconnect(phydev);
 801                 return -ENODEV;
 802         }
 803         pr_debug("stmmac_init_phy:  %s: attached to PHY (UID 0x%x)"
 804                  " Link = %d\n", dev->name, phydev->phy_id, phydev->link);
 805
 806         priv->phydev = phydev;
 807
 808         return 0;
 809 }
 810
 811 /**
 812  * stmmac_display_ring
 813  * @p: pointer to the ring.
 814  * @size: size of the ring.
 815  * Description: display the control/status and buffer descriptors.
 816  */
 817 static void stmmac_display_ring(void *head, int size, int extend_desc)
 818 {
 819         int i;
 820         struct dma_extended_desc *ep = (struct dma_extended_desc *) head;
 821         struct dma_desc *p = (struct dma_desc *) head;
 822
 823         for (i = 0; i < size; i++) {
 824                 u64 x;
 825                 if (extend_desc) {
 826                         x = *(u64 *) ep;
 827                         pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
 828                                 i, (unsigned int) virt_to_phys(ep),
 829                                 (unsigned int) x, (unsigned int) (x >> 32),
 830                                 ep->basic.des2, ep->basic.des3);
 831                         ep++;
 832                 } else {
 833                         x = *(u64 *) p;
 834                         pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x",
 835                                 i, (unsigned int) virt_to_phys(p),
 836                                 (unsigned int) x, (unsigned int) (x >> 32),
 837                                 p->des2, p->des3);
 838                         p++;
 839                 }
 840                 pr_info("\n");
 841         }
 842 }
 843
 844 static void stmmac_display_rings(struct stmmac_priv *priv)
 845 {
 846         unsigned int txsize = priv->dma_tx_size;
 847         unsigned int rxsize = priv->dma_rx_size;
 848
 849         if (priv->extend_desc) {
 850                 pr_info("Extended RX descriptor ring:\n");
 851                 stmmac_display_ring((void *) priv->dma_erx, rxsize, 1);
 852                 pr_info("Extended TX descriptor ring:\n");
 853                 stmmac_display_ring((void *) priv->dma_etx, txsize, 1);
 854         } else {
 855                 pr_info("RX descriptor ring:\n");
 856                 stmmac_display_ring((void *)priv->dma_rx, rxsize, 0);
 857                 pr_info("TX descriptor ring:\n");
 858                 stmmac_display_ring((void *)priv->dma_tx, txsize, 0);
 859         }
 860 }
 861
 862 static int stmmac_set_bfsize(int mtu, int bufsize)
 863 {
 864         int ret = bufsize;
 865
 866         if (mtu >= BUF_SIZE_4KiB)
 867                 ret = BUF_SIZE_8KiB;
 868         else if (mtu >= BUF_SIZE_2KiB)
 869                 ret = BUF_SIZE_4KiB;
 870         else if (mtu >= DMA_BUFFER_SIZE)
 871                 ret = BUF_SIZE_2KiB;
 872         else
 873                 ret = DMA_BUFFER_SIZE;
 874
 875         return ret;
 876 }
 877
 878 static void stmmac_clear_descriptors(struct stmmac_priv *priv)
 879 {
 880         int i;
 881         unsigned int txsize = priv->dma_tx_size;
 882         unsigned int rxsize = priv->dma_rx_size;
 883
 884         /* Clear the Rx/Tx descriptors */
 885         for (i = 0; i < rxsize; i++)
 886                 if (priv->extend_desc)
 887                         priv->hw->desc->init_rx_desc(&priv->dma_erx[i].basic,
 888                                                      priv->use_riwt, priv->mode,
 889                                                      (i == rxsize - 1));
 890                 else
 891                         priv->hw->desc->init_rx_desc(&priv->dma_rx[i],
 892                                                      priv->use_riwt, priv->mode,
 893                                                      (i == rxsize - 1));
 894         for (i = 0; i < txsize; i++)
 895                 if (priv->extend_desc)
 896                         priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic,
 897                                                      priv->mode,
 898                                                      (i == txsize - 1));
 899                 else
 900                         priv->hw->desc->init_tx_desc(&priv->dma_tx[i],
 901                                                      priv->mode,
 902                                                      (i == txsize - 1));
 903 }
 904
 905 static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p,
 906                                   int i)
 907 {
 908         struct sk_buff *skb;
 909
 910         skb = __netdev_alloc_skb(priv->dev, priv->dma_buf_sz + NET_IP_ALIGN,
 911                                  GFP_KERNEL);
 912         if (unlikely(skb == NULL)) {
 913                 pr_err("%s: Rx init fails; skb is NULL\n", __func__);
 914                 return 1;
 915         }
 916         skb_reserve(skb, NET_IP_ALIGN);
 917         priv->rx_skbuff[i] = skb;
 918         priv->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data,
 919                                                 priv->dma_buf_sz,
 920                                                 DMA_FROM_DEVICE);
 921
 922         p->des2 = priv->rx_skbuff_dma[i];
 923
 924         if ((priv->mode == STMMAC_RING_MODE) &&
 925             (priv->dma_buf_sz == BUF_SIZE_16KiB))
 926                 priv->hw->ring->init_desc3(p);
 927
 928         return 0;
 929 }
 930
 931 /**
 932  * init_dma_desc_rings - init the RX/TX descriptor rings
 933  * @dev: net device structure
 934  * Description:  this function initializes the DMA RX/TX descriptors
 935  * and allocates the socket buffers. It suppors the chained and ring
 936  * modes.
 937  */
 938 static void init_dma_desc_rings(struct net_device *dev)
 939 {
 940         int i;
 941         struct stmmac_priv *priv = netdev_priv(dev);
 942         unsigned int txsize = priv->dma_tx_size;
 943         unsigned int rxsize = priv->dma_rx_size;
 944         unsigned int bfsize = 0;
 945
 946         /* Set the max buffer size according to the DESC mode
 947          * and the MTU. Note that RING mode allows 16KiB bsize. */
 948         if (priv->mode == STMMAC_RING_MODE)
 949                 bfsize = priv->hw->ring->set_16kib_bfsize(dev->mtu);
 950
 951         if (bfsize < BUF_SIZE_16KiB)
 952                 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz);
 953
 954         DBG(probe, INFO, "stmmac: txsize %d, rxsize %d, bfsize %d\n",
 955             txsize, rxsize, bfsize);
 956
 957         if (priv->extend_desc) {
 958                 priv->dma_erx = dma_alloc_coherent(priv->device, rxsize *
 959                                                    sizeof(struct
 960                                                           dma_extended_desc),
 961                                                    &priv->dma_rx_phy,
 962                                                    GFP_KERNEL);
 963                 priv->dma_etx = dma_alloc_coherent(priv->device, txsize *
 964                                                    sizeof(struct
 965                                                           dma_extended_desc),
 966                                                    &priv->dma_tx_phy,
 967                                                    GFP_KERNEL);
 968                 if ((!priv->dma_erx) || (!priv->dma_etx))
 969                         return;
 970         } else {
 971                 priv->dma_rx = dma_alloc_coherent(priv->device, rxsize *
 972                                                   sizeof(struct dma_desc),
 973                                                   &priv->dma_rx_phy,
 974                                                   GFP_KERNEL);
 975                 priv->dma_tx = dma_alloc_coherent(priv->device, txsize *
 976                                                   sizeof(struct dma_desc),
 977                                                   &priv->dma_tx_phy,
 978                                                   GFP_KERNEL);
 979                 if ((!priv->dma_rx) || (!priv->dma_tx))
 980                         return;
 981         }
 982
 983         priv->rx_skbuff_dma = kmalloc_array(rxsize, sizeof(dma_addr_t),
 984                                             GFP_KERNEL);
 985         priv->rx_skbuff = kmalloc_array(rxsize, sizeof(struct sk_buff *),
 986                                         GFP_KERNEL);
 987         priv->tx_skbuff_dma = kmalloc_array(txsize, sizeof(dma_addr_t),
 988                                         GFP_KERNEL);
 989         priv->tx_skbuff = kmalloc_array(txsize, sizeof(struct sk_buff *),
 990                                         GFP_KERNEL);
 991         if (netif_msg_drv(priv))
 992                 pr_debug("(%s) dma_rx_phy=0x%08x dma_tx_phy=0x%08x\n", __func__,
 993                          (u32) priv->dma_rx_phy, (u32) priv->dma_tx_phy);
 994
 995         /* RX INITIALIZATION */
 996         DBG(probe, INFO, "stmmac: SKB addresses:\nskb\t\tskb data\tdma data\n");
 997         for (i = 0; i < rxsize; i++) {
 998                 struct dma_desc *p;
 999                 if (priv->extend_desc)
1000                         p = &((priv->dma_erx + i)->basic);
1001                 else
1002                         p = priv->dma_rx + i;
1003
1004                 if (stmmac_init_rx_buffers(priv, p, i))
1005                         break;
1006
1007                 DBG(probe, INFO, "[%p]\t[%p]\t[%x]\n", priv->rx_skbuff[i],
1008                         priv->rx_skbuff[i]->data, priv->rx_skbuff_dma[i]);
1009         }
1010         priv->cur_rx = 0;
1011         priv->dirty_rx = (unsigned int)(i - rxsize);
1012         priv->dma_buf_sz = bfsize;
1013         buf_sz = bfsize;
1014
1015         /* Setup the chained descriptor addresses */
1016         if (priv->mode == STMMAC_CHAIN_MODE) {
1017                 if (priv->extend_desc) {
1018                         priv->hw->chain->init(priv->dma_erx, priv->dma_rx_phy,
1019                                               rxsize, 1);
1020                         priv->hw->chain->init(priv->dma_etx, priv->dma_tx_phy,
1021                                               txsize, 1);
1022                 } else {
1023                         priv->hw->chain->init(priv->dma_rx, priv->dma_rx_phy,
1024                                               rxsize, 0);
1025                         priv->hw->chain->init(priv->dma_tx, priv->dma_tx_phy,
1026                                               txsize, 0);
1027                 }
1028         }
1029
1030         /* TX INITIALIZATION */
1031         for (i = 0; i < txsize; i++) {
1032                 struct dma_desc *p;
1033                 if (priv->extend_desc)
1034                         p = &((priv->dma_etx + i)->basic);
1035                 else
1036                         p = priv->dma_tx + i;
1037                 p->des2 = 0;
1038                 priv->tx_skbuff_dma[i] = 0;
1039                 priv->tx_skbuff[i] = NULL;
1040         }
1041
1042         priv->dirty_tx = 0;
1043         priv->cur_tx = 0;
1044
1045         stmmac_clear_descriptors(priv);
1046
1047         if (netif_msg_hw(priv))
1048                 stmmac_display_rings(priv);
1049 }
1050
1051 static void dma_free_rx_skbufs(struct stmmac_priv *priv)
1052 {
1053         int i;
1054
1055         for (i = 0; i < priv->dma_rx_size; i++) {
1056                 if (priv->rx_skbuff[i]) {
1057                         dma_unmap_single(priv->device, priv->rx_skbuff_dma[i],
1058                                          priv->dma_buf_sz, DMA_FROM_DEVICE);
1059                         dev_kfree_skb_any(priv->rx_skbuff[i]);
1060                 }
1061                 priv->rx_skbuff[i] = NULL;
1062         }
1063 }
1064
1065 static void dma_free_tx_skbufs(struct stmmac_priv *priv)
1066 {
1067         int i;
1068
1069         for (i = 0; i < priv->dma_tx_size; i++) {
1070                 if (priv->tx_skbuff[i] != NULL) {
1071                         struct dma_desc *p;
1072                         if (priv->extend_desc)
1073                                 p = &((priv->dma_etx + i)->basic);
1074                         else
1075                                 p = priv->dma_tx + i;
1076
1077                         if (priv->tx_skbuff_dma[i])
1078                                 dma_unmap_single(priv->device,
1079                                                  priv->tx_skbuff_dma[i],
1080                                                  priv->hw->desc->get_tx_len(p),
1081                                                  DMA_TO_DEVICE);
1082                         dev_kfree_skb_any(priv->tx_skbuff[i]);
1083                         priv->tx_skbuff[i] = NULL;
1084                         priv->tx_skbuff_dma[i] = 0;
1085                 }
1086         }
1087 }
1088
1089 static void free_dma_desc_resources(struct stmmac_priv *priv)
1090 {
1091         /* Release the DMA TX/RX socket buffers */
1092         dma_free_rx_skbufs(priv);
1093         dma_free_tx_skbufs(priv);
1094
1095         /* Free the region of consistent memory previously allocated for
1096          * the DMA */
1097         if (!priv->extend_desc) {
1098                 dma_free_coherent(priv->device,
1099                                   priv->dma_tx_size * sizeof(struct dma_desc),
1100                                   priv->dma_tx, priv->dma_tx_phy);
1101                 dma_free_coherent(priv->device,
1102                                   priv->dma_rx_size * sizeof(struct dma_desc),
1103                                   priv->dma_rx, priv->dma_rx_phy);
1104         } else {
1105                 dma_free_coherent(priv->device, priv->dma_tx_size *
1106                                   sizeof(struct dma_extended_desc),
1107                                   priv->dma_etx, priv->dma_tx_phy);
1108                 dma_free_coherent(priv->device, priv->dma_rx_size *
1109                                   sizeof(struct dma_extended_desc),
1110                                   priv->dma_erx, priv->dma_rx_phy);
1111         }
1112         kfree(priv->rx_skbuff_dma);
1113         kfree(priv->rx_skbuff);
1114         kfree(priv->tx_skbuff_dma);
1115         kfree(priv->tx_skbuff);
1116 }
1117
1118 /**
1119  *  stmmac_dma_operation_mode - HW DMA operation mode
1120  *  @priv : pointer to the private device structure.
1121  *  Description: it sets the DMA operation mode: tx/rx DMA thresholds
1122  *  or Store-And-Forward capability.
1123  */
1124 static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
1125 {
1126         if (likely(priv->plat->force_sf_dma_mode ||
1127                 ((priv->plat->tx_coe) && (!priv->no_csum_insertion)))) {
1128                 /*
1129                  * In case of GMAC, SF mode can be enabled
1130                  * to perform the TX COE in HW. This depends on:
1131                  * 1) TX COE if actually supported
1132                  * 2) There is no bugged Jumbo frame support
1133                  *    that needs to not insert csum in the TDES.
1134                  */
1135                 priv->hw->dma->dma_mode(priv->ioaddr,
1136                                         SF_DMA_MODE, SF_DMA_MODE);
1137                 tc = SF_DMA_MODE;
1138         } else
1139                 priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE);
1140 }
1141
1142 /**
1143  * stmmac_tx_clean:
1144  * @priv: private data pointer
1145  * Description: it reclaims resources after transmission completes.
1146  */
1147 static void stmmac_tx_clean(struct stmmac_priv *priv)
1148 {
1149         unsigned int txsize = priv->dma_tx_size;
1150
1151         spin_lock(&priv->tx_lock);
1152
1153         priv->xstats.tx_clean++;
1154
1155         while (priv->dirty_tx != priv->cur_tx) {
1156                 int last;
1157                 unsigned int entry = priv->dirty_tx % txsize;
1158                 struct sk_buff *skb = priv->tx_skbuff[entry];
1159                 struct dma_desc *p;
1160
1161                 if (priv->extend_desc)
1162                         p = (struct dma_desc *) (priv->dma_etx + entry);
1163                 else
1164                         p = priv->dma_tx + entry;
1165
1166                 /* Check if the descriptor is owned by the DMA. */
1167                 if (priv->hw->desc->get_tx_owner(p))
1168                         break;
1169
1170                 /* Verify tx error by looking at the last segment. */
1171                 last = priv->hw->desc->get_tx_ls(p);
1172                 if (likely(last)) {
1173                         int tx_error =
1174                                 priv->hw->desc->tx_status(&priv->dev->stats,
1175                                                           &priv->xstats, p,
1176                                                           priv->ioaddr);
1177                         if (likely(tx_error == 0)) {
1178                                 priv->dev->stats.tx_packets++;
1179                                 priv->xstats.tx_pkt_n++;
1180                         } else
1181                                 priv->dev->stats.tx_errors++;
1182
1183                         stmmac_get_tx_hwtstamp(priv, entry, skb);
1184                 }
1185                 TX_DBG("%s: curr %d, dirty %d\n", __func__,
1186                         priv->cur_tx, priv->dirty_tx);
1187
1188                 if (likely(priv->tx_skbuff_dma[entry])) {
1189                         dma_unmap_single(priv->device,
1190                                          priv->tx_skbuff_dma[entry],
1191                                          priv->hw->desc->get_tx_len(p),
1192                                          DMA_TO_DEVICE);
1193                         priv->tx_skbuff_dma[entry] = 0;
1194                 }
1195                 priv->hw->ring->clean_desc3(priv, p);
1196
1197                 if (likely(skb != NULL)) {
1198                         dev_kfree_skb(skb);
1199                         priv->tx_skbuff[entry] = NULL;
1200                 }
1201
1202                 priv->hw->desc->release_tx_desc(p, priv->mode);
1203
1204                 priv->dirty_tx++;
1205         }
1206         if (unlikely(netif_queue_stopped(priv->dev) &&
1207                      stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv))) {
1208                 netif_tx_lock(priv->dev);
1209                 if (netif_queue_stopped(priv->dev) &&
1210                      stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv)) {
1211                         TX_DBG("%s: restart transmit\n", __func__);
1212                         netif_wake_queue(priv->dev);
1213                 }
1214                 netif_tx_unlock(priv->dev);
1215         }
1216
1217         if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) {
1218                 stmmac_enable_eee_mode(priv);
1219                 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_TIMER(eee_timer));
1220         }
1221         spin_unlock(&priv->tx_lock);
1222 }
1223
1224 static inline void stmmac_enable_dma_irq(struct stmmac_priv *priv)
1225 {
1226         priv->hw->dma->enable_dma_irq(priv->ioaddr);
1227 }
1228
1229 static inline void stmmac_disable_dma_irq(struct stmmac_priv *priv)
1230 {
1231         priv->hw->dma->disable_dma_irq(priv->ioaddr);
1232 }
1233
1234
1235 /**
1236  * stmmac_tx_err:
1237  * @priv: pointer to the private device structure
1238  * Description: it cleans the descriptors and restarts the transmission
1239  * in case of errors.
1240  */
1241 static void stmmac_tx_err(struct stmmac_priv *priv)
1242 {
1243         int i;
1244         int txsize = priv->dma_tx_size;
1245         netif_stop_queue(priv->dev);
1246
1247         priv->hw->dma->stop_tx(priv->ioaddr);
1248         dma_free_tx_skbufs(priv);
1249         for (i = 0; i < txsize; i++)
1250                 if (priv->extend_desc)
1251                         priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic,
1252                                                      priv->mode,
1253                                                      (i == txsize - 1));
1254                 else
1255                         priv->hw->desc->init_tx_desc(&priv->dma_tx[i],
1256                                                      priv->mode,
1257                                                      (i == txsize - 1));
1258         priv->dirty_tx = 0;
1259         priv->cur_tx = 0;
1260         priv->hw->dma->start_tx(priv->ioaddr);
1261
1262         priv->dev->stats.tx_errors++;
1263         netif_wake_queue(priv->dev);
1264 }
1265
1266 static void stmmac_dma_interrupt(struct stmmac_priv *priv)
1267 {
1268         int status;
1269
1270         status = priv->hw->dma->dma_interrupt(priv->ioaddr, &priv->xstats);
1271         if (likely((status & handle_rx)) || (status & handle_tx)) {
1272                 if (likely(napi_schedule_prep(&priv->napi))) {
1273                         stmmac_disable_dma_irq(priv);
1274                         __napi_schedule(&priv->napi);
1275                 }
1276         }
1277         if (unlikely(status & tx_hard_error_bump_tc)) {
1278                 /* Try to bump up the dma threshold on this failure */
1279                 if (unlikely(tc != SF_DMA_MODE) && (tc <= 256)) {
1280                         tc += 64;
1281                         priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE);
1282                         priv->xstats.threshold = tc;
1283                 }
1284         } else if (unlikely(status == tx_hard_error))
1285                 stmmac_tx_err(priv);
1286 }
1287
1288 static void stmmac_mmc_setup(struct stmmac_priv *priv)
1289 {
1290         unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET |
1291                             MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET;
1292
1293         /* Mask MMC irq, counters are managed in SW and registers
1294          * are cleared on each READ eventually. */
1295         dwmac_mmc_intr_all_mask(priv->ioaddr);
1296
1297         if (priv->dma_cap.rmon) {
1298                 dwmac_mmc_ctrl(priv->ioaddr, mode);
1299                 memset(&priv->mmc, 0, sizeof(struct stmmac_counters));
1300         } else
1301                 pr_info(" No MAC Management Counters available\n");
1302 }
1303
1304 static u32 stmmac_get_synopsys_id(struct stmmac_priv *priv)
1305 {
1306         u32 hwid = priv->hw->synopsys_uid;
1307
1308         /* Only check valid Synopsys Id because old MAC chips
1309          * have no HW registers where get the ID */
1310         if (likely(hwid)) {
1311                 u32 uid = ((hwid & 0x0000ff00) >> 8);
1312                 u32 synid = (hwid & 0x000000ff);
1313
1314                 pr_info("stmmac - user ID: 0x%x, Synopsys ID: 0x%x\n",
1315                         uid, synid);
1316
1317                 return synid;
1318         }
1319         return 0;
1320 }
1321
1322 /**
1323  * stmmac_selec_desc_mode
1324  * @priv : private structure
1325  * Description: select the Enhanced/Alternate or Normal descriptors
1326  */
1327 static void stmmac_selec_desc_mode(struct stmmac_priv *priv)
1328 {
1329         if (priv->plat->enh_desc) {
1330                 pr_info(" Enhanced/Alternate descriptors\n");
1331
1332                 /* GMAC older than 3.50 has no extended descriptors */
1333                 if (priv->synopsys_id >= DWMAC_CORE_3_50) {
1334                         pr_info("\tEnabled extended descriptors\n");
1335                         priv->extend_desc = 1;
1336                 } else
1337                         pr_warn("Extended descriptors not supported\n");
1338
1339                 priv->hw->desc = &enh_desc_ops;
1340         } else {
1341                 pr_info(" Normal descriptors\n");
1342                 priv->hw->desc = &ndesc_ops;
1343         }
1344 }
1345
1346 /**
1347  * stmmac_get_hw_features
1348  * @priv : private device pointer
1349  * Description:
1350  *  new GMAC chip generations have a new register to indicate the
1351  *  presence of the optional feature/functions.
1352  *  This can be also used to override the value passed through the
1353  *  platform and necessary for old MAC10/100 and GMAC chips.
1354  */
1355 static int stmmac_get_hw_features(struct stmmac_priv *priv)
1356 {
1357         u32 hw_cap = 0;
1358
1359         if (priv->hw->dma->get_hw_feature) {
1360                 hw_cap = priv->hw->dma->get_hw_feature(priv->ioaddr);
1361
1362                 priv->dma_cap.mbps_10_100 = (hw_cap & DMA_HW_FEAT_MIISEL);
1363                 priv->dma_cap.mbps_1000 = (hw_cap & DMA_HW_FEAT_GMIISEL) >> 1;
1364                 priv->dma_cap.half_duplex = (hw_cap & DMA_HW_FEAT_HDSEL) >> 2;
1365                 priv->dma_cap.hash_filter = (hw_cap & DMA_HW_FEAT_HASHSEL) >> 4;
1366                 priv->dma_cap.multi_addr =
1367                         (hw_cap & DMA_HW_FEAT_ADDMACADRSEL) >> 5;
1368                 priv->dma_cap.pcs = (hw_cap & DMA_HW_FEAT_PCSSEL) >> 6;
1369                 priv->dma_cap.sma_mdio = (hw_cap & DMA_HW_FEAT_SMASEL) >> 8;
1370                 priv->dma_cap.pmt_remote_wake_up =
1371                         (hw_cap & DMA_HW_FEAT_RWKSEL) >> 9;
1372                 priv->dma_cap.pmt_magic_frame =
1373                         (hw_cap & DMA_HW_FEAT_MGKSEL) >> 10;
1374                 /* MMC */
1375                 priv->dma_cap.rmon = (hw_cap & DMA_HW_FEAT_MMCSEL) >> 11;
1376                 /* IEEE 1588-2002*/
1377                 priv->dma_cap.time_stamp =
1378                         (hw_cap & DMA_HW_FEAT_TSVER1SEL) >> 12;
1379                 /* IEEE 1588-2008*/
1380                 priv->dma_cap.atime_stamp =
1381                         (hw_cap & DMA_HW_FEAT_TSVER2SEL) >> 13;
1382                 /* 802.3az - Energy-Efficient Ethernet (EEE) */
1383                 priv->dma_cap.eee = (hw_cap & DMA_HW_FEAT_EEESEL) >> 14;
1384                 priv->dma_cap.av = (hw_cap & DMA_HW_FEAT_AVSEL) >> 15;
1385                 /* TX and RX csum */
1386                 priv->dma_cap.tx_coe = (hw_cap & DMA_HW_FEAT_TXCOESEL) >> 16;
1387                 priv->dma_cap.rx_coe_type1 =
1388                         (hw_cap & DMA_HW_FEAT_RXTYP1COE) >> 17;
1389                 priv->dma_cap.rx_coe_type2 =
1390                         (hw_cap & DMA_HW_FEAT_RXTYP2COE) >> 18;
1391                 priv->dma_cap.rxfifo_over_2048 =
1392                         (hw_cap & DMA_HW_FEAT_RXFIFOSIZE) >> 19;
1393                 /* TX and RX number of channels */
1394                 priv->dma_cap.number_rx_channel =
1395                         (hw_cap & DMA_HW_FEAT_RXCHCNT) >> 20;
1396                 priv->dma_cap.number_tx_channel =
1397                         (hw_cap & DMA_HW_FEAT_TXCHCNT) >> 22;
1398                 /* Alternate (enhanced) DESC mode*/
1399                 priv->dma_cap.enh_desc =
1400                         (hw_cap & DMA_HW_FEAT_ENHDESSEL) >> 24;
1401         }
1402
1403         return hw_cap;
1404 }
1405
1406 static void stmmac_check_ether_addr(struct stmmac_priv *priv)
1407 {
1408         /* verify if the MAC address is valid, in case of failures it
1409          * generates a random MAC address */
1410         if (!is_valid_ether_addr(priv->dev->dev_addr)) {
1411                 priv->hw->mac->get_umac_addr((void __iomem *)
1412                                              priv->dev->base_addr,
1413                                              priv->dev->dev_addr, 0);
1414                 if  (!is_valid_ether_addr(priv->dev->dev_addr))
1415                         eth_hw_addr_random(priv->dev);
1416         }
1417         pr_warning("%s: device MAC address %pM\n", priv->dev->name,
1418                                                    priv->dev->dev_addr);
1419 }
1420
1421 static int stmmac_init_dma_engine(struct stmmac_priv *priv)
1422 {
1423         int pbl = DEFAULT_DMA_PBL, fixed_burst = 0, burst_len = 0;
1424         int mixed_burst = 0;
1425         int atds = 0;
1426
1427         /* Some DMA parameters can be passed from the platform;
1428          * in case of these are not passed we keep a default
1429          * (good for all the chips) and init the DMA! */
1430         if (priv->plat->dma_cfg) {
1431                 pbl = priv->plat->dma_cfg->pbl;
1432                 fixed_burst = priv->plat->dma_cfg->fixed_burst;
1433                 mixed_burst = priv->plat->dma_cfg->mixed_burst;
1434                 burst_len = priv->plat->dma_cfg->burst_len;
1435         }
1436
1437         if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE))
1438                 atds = 1;
1439
1440         return priv->hw->dma->init(priv->ioaddr, pbl, fixed_burst, mixed_burst,
1441                                    burst_len, priv->dma_tx_phy,
1442                                    priv->dma_rx_phy, atds);
1443 }
1444
1445 /**
1446  * stmmac_tx_timer:
1447  * @data: data pointer
1448  * Description:
1449  * This is the timer handler to directly invoke the stmmac_tx_clean.
1450  */
1451 static void stmmac_tx_timer(unsigned long data)
1452 {
1453         struct stmmac_priv *priv = (struct stmmac_priv *)data;
1454
1455         stmmac_tx_clean(priv);
1456 }
1457
1458 /**
1459  * stmmac_tx_timer:
1460  * @priv: private data structure
1461  * Description:
1462  * This inits the transmit coalesce parameters: i.e. timer rate,
1463  * timer handler and default threshold used for enabling the
1464  * interrupt on completion bit.
1465  */
1466 static void stmmac_init_tx_coalesce(struct stmmac_priv *priv)
1467 {
1468         priv->tx_coal_frames = STMMAC_TX_FRAMES;
1469         priv->tx_coal_timer = STMMAC_COAL_TX_TIMER;
1470         init_timer(&priv->txtimer);
1471         priv->txtimer.expires = STMMAC_COAL_TIMER(priv->tx_coal_timer);
1472         priv->txtimer.data = (unsigned long)priv;
1473         priv->txtimer.function = stmmac_tx_timer;
1474         add_timer(&priv->txtimer);
1475 }
1476
1477 /**
1478  *  stmmac_open - open entry point of the driver
1479  *  @dev : pointer to the device structure.
1480  *  Description:
1481  *  This function is the open entry point of the driver.
1482  *  Return value:
1483  *  0 on success and an appropriate (-)ve integer as defined in errno.h
1484  *  file on failure.
1485  */
1486 static int stmmac_open(struct net_device *dev)
1487 {
1488         struct stmmac_priv *priv = netdev_priv(dev);
1489         int ret;
1490
1491         clk_prepare_enable(priv->stmmac_clk);
1492
1493         stmmac_check_ether_addr(priv);
1494
1495         if (!priv->pcs) {
1496                 ret = stmmac_init_phy(dev);
1497                 if (ret) {
1498                         pr_err("%s: Cannot attach to PHY (error: %d)\n",
1499                                __func__, ret);
1500                         goto open_error;
1501                 }
1502         }
1503
1504         /* Create and initialize the TX/RX descriptors chains. */
1505         priv->dma_tx_size = STMMAC_ALIGN(dma_txsize);
1506         priv->dma_rx_size = STMMAC_ALIGN(dma_rxsize);
1507         priv->dma_buf_sz = STMMAC_ALIGN(buf_sz);
1508         init_dma_desc_rings(dev);
1509
1510         /* DMA initialization and SW reset */
1511         ret = stmmac_init_dma_engine(priv);
1512         if (ret < 0) {
1513                 pr_err("%s: DMA initialization failed\n", __func__);
1514                 goto open_error;
1515         }
1516
1517         /* Copy the MAC addr into the HW  */
1518         priv->hw->mac->set_umac_addr(priv->ioaddr, dev->dev_addr, 0);
1519
1520         /* If required, perform hw setup of the bus. */
1521         if (priv->plat->bus_setup)
1522                 priv->plat->bus_setup(priv->ioaddr);
1523
1524         /* Initialize the MAC Core */
1525         priv->hw->mac->core_init(priv->ioaddr);
1526
1527         /* Request the IRQ lines */
1528         ret = request_irq(dev->irq, stmmac_interrupt,
1529                          IRQF_SHARED, dev->name, dev);
1530         if (unlikely(ret < 0)) {
1531                 pr_err("%s: ERROR: allocating the IRQ %d (error: %d)\n",
1532                        __func__, dev->irq, ret);
1533                 goto open_error;
1534         }
1535
1536         /* Request the Wake IRQ in case of another line is used for WoL */
1537         if (priv->wol_irq != dev->irq) {
1538                 ret = request_irq(priv->wol_irq, stmmac_interrupt,
1539                                   IRQF_SHARED, dev->name, dev);
1540                 if (unlikely(ret < 0)) {
1541                         pr_err("%s: ERROR: allocating the ext WoL IRQ %d "
1542                                "(error: %d)\n", __func__, priv->wol_irq, ret);
1543                         goto open_error_wolirq;
1544                 }
1545         }
1546
1547         /* Request the IRQ lines */
1548         if (priv->lpi_irq != -ENXIO) {
1549                 ret = request_irq(priv->lpi_irq, stmmac_interrupt, IRQF_SHARED,
1550                                   dev->name, dev);
1551                 if (unlikely(ret < 0)) {
1552                         pr_err("%s: ERROR: allocating the LPI IRQ %d (%d)\n",
1553                                __func__, priv->lpi_irq, ret);
1554                         goto open_error_lpiirq;
1555                 }
1556         }
1557
1558         /* Enable the MAC Rx/Tx */
1559         stmmac_set_mac(priv->ioaddr, true);
1560
1561         /* Set the HW DMA mode and the COE */
1562         stmmac_dma_operation_mode(priv);
1563
1564         /* Extra statistics */
1565         memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats));
1566         priv->xstats.threshold = tc;
1567
1568         stmmac_mmc_setup(priv);
1569
1570         stmmac_init_ptp(priv);
1571
1572 #ifdef CONFIG_STMMAC_DEBUG_FS
1573         ret = stmmac_init_fs(dev);
1574         if (ret < 0)
1575                 pr_warning("%s: failed debugFS registration\n", __func__);
1576 #endif
1577         /* Start the ball rolling... */
1578         DBG(probe, DEBUG, "%s: DMA RX/TX processes started...\n", dev->name);
1579         priv->hw->dma->start_tx(priv->ioaddr);
1580         priv->hw->dma->start_rx(priv->ioaddr);
1581
1582         /* Dump DMA/MAC registers */
1583         if (netif_msg_hw(priv)) {
1584                 priv->hw->mac->dump_regs(priv->ioaddr);
1585                 priv->hw->dma->dump_regs(priv->ioaddr);
1586         }
1587
1588         if (priv->phydev)
1589                 phy_start(priv->phydev);
1590
1591         priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS_TIMER;
1592
1593         /* Using PCS we cannot dial with the phy registers at this stage
1594          * so we do not support extra feature like EEE.
1595          */
1596         if (!priv->pcs)
1597                 priv->eee_enabled = stmmac_eee_init(priv);
1598
1599         stmmac_init_tx_coalesce(priv);
1600
1601         if ((priv->use_riwt) && (priv->hw->dma->rx_watchdog)) {
1602                 priv->rx_riwt = MAX_DMA_RIWT;
1603                 priv->hw->dma->rx_watchdog(priv->ioaddr, MAX_DMA_RIWT);
1604         }
1605
1606         if (priv->pcs && priv->hw->mac->ctrl_ane)
1607                 priv->hw->mac->ctrl_ane(priv->ioaddr, 0);
1608
1609         napi_enable(&priv->napi);
1610         netif_start_queue(dev);
1611
1612         return 0;
1613
1614 open_error_lpiirq:
1615         if (priv->wol_irq != dev->irq)
1616                 free_irq(priv->wol_irq, dev);
1617
1618 open_error_wolirq:
1619         free_irq(dev->irq, dev);
1620
1621 open_error:
1622         if (priv->phydev)
1623                 phy_disconnect(priv->phydev);
1624
1625         clk_disable_unprepare(priv->stmmac_clk);
1626
1627         return ret;
1628 }
1629
1630 /**
1631  *  stmmac_release - close entry point of the driver
1632  *  @dev : device pointer.
1633  *  Description:
1634  *  This is the stop entry point of the driver.
1635  */
1636 static int stmmac_release(struct net_device *dev)
1637 {
1638         struct stmmac_priv *priv = netdev_priv(dev);
1639
1640         if (priv->eee_enabled)
1641                 del_timer_sync(&priv->eee_ctrl_timer);
1642
1643         /* Stop and disconnect the PHY */
1644         if (priv->phydev) {
1645                 phy_stop(priv->phydev);
1646                 phy_disconnect(priv->phydev);
1647                 priv->phydev = NULL;
1648         }
1649
1650         netif_stop_queue(dev);
1651
1652         napi_disable(&priv->napi);
1653
1654         del_timer_sync(&priv->txtimer);
1655
1656         /* Free the IRQ lines */
1657         free_irq(dev->irq, dev);
1658         if (priv->wol_irq != dev->irq)
1659                 free_irq(priv->wol_irq, dev);
1660         if (priv->lpi_irq != -ENXIO)
1661                 free_irq(priv->lpi_irq, dev);
1662
1663         /* Stop TX/RX DMA and clear the descriptors */
1664         priv->hw->dma->stop_tx(priv->ioaddr);
1665         priv->hw->dma->stop_rx(priv->ioaddr);
1666
1667         /* Release and free the Rx/Tx resources */
1668         free_dma_desc_resources(priv);
1669
1670         /* Disable the MAC Rx/Tx */
1671         stmmac_set_mac(priv->ioaddr, false);
1672
1673         netif_carrier_off(dev);
1674
1675 #ifdef CONFIG_STMMAC_DEBUG_FS
1676         stmmac_exit_fs();
1677 #endif
1678         clk_disable_unprepare(priv->stmmac_clk);
1679
1680         return 0;
1681 }
1682
1683 /**
1684  *  stmmac_xmit:
1685  *  @skb : the socket buffer
1686  *  @dev : device pointer
1687  *  Description : Tx entry point of the driver.
1688  */
1689 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
1690 {
1691         struct stmmac_priv *priv = netdev_priv(dev);
1692         unsigned int txsize = priv->dma_tx_size;
1693         unsigned int entry;
1694         int i, csum_insertion = 0, is_jumbo = 0;
1695         int nfrags = skb_shinfo(skb)->nr_frags;
1696         struct dma_desc *desc, *first;
1697         unsigned int nopaged_len = skb_headlen(skb);
1698
1699         if (unlikely(stmmac_tx_avail(priv) < nfrags + 1)) {
1700                 if (!netif_queue_stopped(dev)) {
1701                         netif_stop_queue(dev);
1702                         /* This is a hard error, log it. */
1703                         pr_err("%s: BUG! Tx Ring full when queue awake\n",
1704                                 __func__);
1705                 }
1706                 return NETDEV_TX_BUSY;
1707         }
1708
1709         spin_lock(&priv->tx_lock);
1710
1711         if (priv->tx_path_in_lpi_mode)
1712                 stmmac_disable_eee_mode(priv);
1713
1714         entry = priv->cur_tx % txsize;
1715
1716 #ifdef STMMAC_XMIT_DEBUG
1717         if ((skb->len > ETH_FRAME_LEN) || nfrags)
1718                 pr_debug("stmmac xmit: [entry %d]\n"
1719                          "\tskb addr %p - len: %d - nopaged_len: %d\n"
1720                          "\tn_frags: %d - ip_summed: %d - %s gso\n"
1721                          "\ttx_count_frames %d\n", entry,
1722                          skb, skb->len, nopaged_len, nfrags, skb->ip_summed,
1723                          !skb_is_gso(skb) ? "isn't" : "is",
1724                          priv->tx_count_frames);
1725 #endif
1726
1727         csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL);
1728
1729         if (priv->extend_desc)
1730                 desc = (struct dma_desc *) (priv->dma_etx + entry);
1731         else
1732                 desc = priv->dma_tx + entry;
1733
1734         first = desc;
1735
1736 #ifdef STMMAC_XMIT_DEBUG
1737         if ((nfrags > 0) || (skb->len > ETH_FRAME_LEN))
1738                 pr_debug("\tskb len: %d, nopaged_len: %d,\n"
1739                          "\t\tn_frags: %d, ip_summed: %d\n",
1740                          skb->len, nopaged_len, nfrags, skb->ip_summed);
1741 #endif
1742         priv->tx_skbuff[entry] = skb;
1743
1744         /* To program the descriptors according to the size of the frame */
1745         if (priv->mode == STMMAC_RING_MODE) {
1746                 is_jumbo = priv->hw->ring->is_jumbo_frm(skb->len,
1747                                                         priv->plat->enh_desc);
1748                 if (unlikely(is_jumbo))
1749                         entry = priv->hw->ring->jumbo_frm(priv, skb,
1750                                                           csum_insertion);
1751         } else {
1752                 is_jumbo = priv->hw->chain->is_jumbo_frm(skb->len,
1753                                                         priv->plat->enh_desc);
1754                 if (unlikely(is_jumbo))
1755                         entry = priv->hw->chain->jumbo_frm(priv, skb,
1756                                                            csum_insertion);
1757         }
1758         if (likely(!is_jumbo)) {
1759                 desc->des2 = dma_map_single(priv->device, skb->data,
1760                                         nopaged_len, DMA_TO_DEVICE);
1761                 priv->tx_skbuff_dma[entry] = desc->des2;
1762                 priv->hw->desc->prepare_tx_desc(desc, 1, nopaged_len,
1763                                                 csum_insertion, priv->mode);
1764         } else
1765                 desc = first;
1766
1767         for (i = 0; i < nfrags; i++) {
1768                 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1769                 int len = skb_frag_size(frag);
1770
1771                 entry = (++priv->cur_tx) % txsize;
1772                 if (priv->extend_desc)
1773                         desc = (struct dma_desc *) (priv->dma_etx + entry);
1774                 else
1775                         desc = priv->dma_tx + entry;
1776
1777                 TX_DBG("\t[entry %d] segment len: %d\n", entry, len);
1778                 desc->des2 = skb_frag_dma_map(priv->device, frag, 0, len,
1779                                               DMA_TO_DEVICE);
1780                 priv->tx_skbuff_dma[entry] = desc->des2;
1781                 priv->tx_skbuff[entry] = NULL;
1782                 priv->hw->desc->prepare_tx_desc(desc, 0, len, csum_insertion,
1783                                                 priv->mode);
1784                 wmb();
1785                 priv->hw->desc->set_tx_owner(desc);
1786                 wmb();
1787         }
1788
1789         /* Finalize the latest segment. */
1790         priv->hw->desc->close_tx_desc(desc);
1791
1792         wmb();
1793         /* According to the coalesce parameter the IC bit for the latest
1794          * segment could be reset and the timer re-started to invoke the
1795          * stmmac_tx function. This approach takes care about the fragments.
1796          */
1797         priv->tx_count_frames += nfrags + 1;
1798         if (priv->tx_coal_frames > priv->tx_count_frames) {
1799                 priv->hw->desc->clear_tx_ic(desc);
1800                 priv->xstats.tx_reset_ic_bit++;
1801                 TX_DBG("\t[entry %d]: tx_count_frames %d\n", entry,
1802                        priv->tx_count_frames);
1803                 mod_timer(&priv->txtimer,
1804                           STMMAC_COAL_TIMER(priv->tx_coal_timer));
1805         } else
1806                 priv->tx_count_frames = 0;
1807
1808         /* To avoid raise condition */
1809         priv->hw->desc->set_tx_owner(first);
1810         wmb();
1811
1812         priv->cur_tx++;
1813
1814 #ifdef STMMAC_XMIT_DEBUG
1815         if (netif_msg_pktdata(priv)) {
1816                 pr_info("stmmac xmit: current=%d, dirty=%d, entry=%d, "
1817                        "first=%p, nfrags=%d\n",
1818                        (priv->cur_tx % txsize), (priv->dirty_tx % txsize),
1819                        entry, first, nfrags);
1820                 if (priv->extend_desc)
1821                         stmmac_display_ring((void *)priv->dma_etx, txsize, 1);
1822                 else
1823                         stmmac_display_ring((void *)priv->dma_tx, txsize, 0);
1824
1825                 pr_info(">>> frame to be transmitted: ");
1826                 print_pkt(skb->data, skb->len);
1827         }
1828 #endif
1829         if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) {
1830                 TX_DBG("%s: stop transmitted packets\n", __func__);
1831                 netif_stop_queue(dev);
1832         }
1833
1834         dev->stats.tx_bytes += skb->len;
1835
1836         if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
1837                      priv->hwts_tx_en)) {
1838                 /* declare that device is doing timestamping */
1839                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1840                 priv->hw->desc->enable_tx_timestamp(first);
1841         }
1842
1843         if (!priv->hwts_tx_en)
1844                 skb_tx_timestamp(skb);
1845
1846         priv->hw->dma->enable_dma_transmission(priv->ioaddr);
1847
1848         spin_unlock(&priv->tx_lock);
1849
1850         return NETDEV_TX_OK;
1851 }
1852
1853 static inline void stmmac_rx_refill(struct stmmac_priv *priv)
1854 {
1855         unsigned int rxsize = priv->dma_rx_size;
1856         int bfsize = priv->dma_buf_sz;
1857
1858         for (; priv->cur_rx - priv->dirty_rx > 0; priv->dirty_rx++) {
1859                 unsigned int entry = priv->dirty_rx % rxsize;
1860                 struct dma_desc *p;
1861
1862                 if (priv->extend_desc)
1863                         p = (struct dma_desc *) (priv->dma_erx + entry);
1864                 else
1865                         p = priv->dma_rx + entry;
1866
1867                 if (likely(priv->rx_skbuff[entry] == NULL)) {
1868                         struct sk_buff *skb;
1869
1870                         skb = netdev_alloc_skb_ip_align(priv->dev, bfsize);
1871
1872                         if (unlikely(skb == NULL))
1873                                 break;
1874
1875                         priv->rx_skbuff[entry] = skb;
1876                         priv->rx_skbuff_dma[entry] =
1877                             dma_map_single(priv->device, skb->data, bfsize,
1878                                            DMA_FROM_DEVICE);
1879
1880                         p->des2 = priv->rx_skbuff_dma[entry];
1881
1882                         priv->hw->ring->refill_desc3(priv, p);
1883
1884                         RX_DBG(KERN_INFO "\trefill entry #%d\n", entry);
1885                 }
1886                 wmb();
1887                 priv->hw->desc->set_rx_owner(p);
1888                 wmb();
1889         }
1890 }
1891
1892 static int stmmac_rx(struct stmmac_priv *priv, int limit)
1893 {
1894         unsigned int rxsize = priv->dma_rx_size;
1895         unsigned int entry = priv->cur_rx % rxsize;
1896         unsigned int next_entry;
1897         unsigned int count = 0;
1898
1899 #ifdef STMMAC_RX_DEBUG
1900         if (netif_msg_hw(priv)) {
1901                 pr_debug(">>> stmmac_rx: descriptor ring:\n");
1902                 if (priv->extend_desc)
1903                         stmmac_display_ring((void *) priv->dma_erx, rxsize, 1);
1904                 else
1905                         stmmac_display_ring((void *)priv->dma_rx, rxsize, 0);
1906         }
1907 #endif
1908         while (count < limit) {
1909                 int status;
1910                 struct dma_desc *p, *p_next;
1911
1912                 if (priv->extend_desc)
1913                         p = (struct dma_desc *) (priv->dma_erx + entry);
1914                 else
1915                         p = priv->dma_rx + entry ;
1916
1917                 if (priv->hw->desc->get_rx_owner(p))
1918                         break;
1919
1920                 count++;
1921
1922                 next_entry = (++priv->cur_rx) % rxsize;
1923                 if (priv->extend_desc)
1924                         p_next = (struct dma_desc *) (priv->dma_erx +
1925                                                       next_entry);
1926                 else
1927                         p_next = priv->dma_rx + next_entry;
1928
1929                 prefetch(p_next);
1930
1931                 /* read the status of the incoming frame */
1932                 status = priv->hw->desc->rx_status(&priv->dev->stats,
1933                                                    &priv->xstats, p);
1934                 if ((priv->extend_desc) && (priv->hw->desc->rx_extended_status))
1935                         priv->hw->desc->rx_extended_status(&priv->dev->stats,
1936                                                            &priv->xstats,
1937                                                            priv->dma_erx +
1938                                                            entry);
1939                 if (unlikely(status == discard_frame)) {
1940                         priv->dev->stats.rx_errors++;
1941                         if (priv->hwts_rx_en && !priv->extend_desc) {
1942                                 /* DESC2 & DESC3 will be overwitten by device
1943                                  * with timestamp value, hence reinitialize
1944                                  * them in stmmac_rx_refill() function so that
1945                                  * device can reuse it.
1946                                  */
1947                                 priv->rx_skbuff[entry] = NULL;
1948                                 dma_unmap_single(priv->device,
1949                                         priv->rx_skbuff_dma[entry],
1950                                         priv->dma_buf_sz, DMA_FROM_DEVICE);
1951                         }
1952                 } else {
1953                         struct sk_buff *skb;
1954                         int frame_len;
1955
1956                         frame_len = priv->hw->desc->get_rx_frame_len(p,
1957                                         priv->plat->rx_coe);
1958                         /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
1959                          * Type frames (LLC/LLC-SNAP) */
1960                         if (unlikely(status != llc_snap))
1961                                 frame_len -= ETH_FCS_LEN;
1962 #ifdef STMMAC_RX_DEBUG
1963                         if (frame_len > ETH_FRAME_LEN)
1964                                 pr_debug("\tRX frame size %d, COE status: %d\n",
1965                                         frame_len, status);
1966
1967                         if (netif_msg_hw(priv))
1968                                 pr_debug("\tdesc: %p [entry %d] buff=0x%x\n",
1969                                         p, entry, p->des2);
1970 #endif
1971                         skb = priv->rx_skbuff[entry];
1972                         if (unlikely(!skb)) {
1973                                 pr_err("%s: Inconsistent Rx descriptor chain\n",
1974                                         priv->dev->name);
1975                                 priv->dev->stats.rx_dropped++;
1976                                 break;
1977                         }
1978                         prefetch(skb->data - NET_IP_ALIGN);
1979                         priv->rx_skbuff[entry] = NULL;
1980
1981                         stmmac_get_rx_hwtstamp(priv, entry, skb);
1982
1983                         skb_put(skb, frame_len);
1984                         dma_unmap_single(priv->device,
1985                                          priv->rx_skbuff_dma[entry],
1986                                          priv->dma_buf_sz, DMA_FROM_DEVICE);
1987 #ifdef STMMAC_RX_DEBUG
1988                         if (netif_msg_pktdata(priv)) {
1989                                 pr_info(" frame received (%dbytes)", frame_len);
1990                                 print_pkt(skb->data, frame_len);
1991                         }
1992 #endif
1993                         skb->protocol = eth_type_trans(skb, priv->dev);
1994
1995                         if (unlikely(!priv->plat->rx_coe))
1996                                 skb_checksum_none_assert(skb);
1997                         else
1998                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1999
2000                         napi_gro_receive(&priv->napi, skb);
2001
2002                         priv->dev->stats.rx_packets++;
2003                         priv->dev->stats.rx_bytes += frame_len;
2004                 }
2005                 entry = next_entry;
2006         }
2007
2008         stmmac_rx_refill(priv);
2009
2010         priv->xstats.rx_pkt_n += count;
2011
2012         return count;
2013 }
2014
2015 /**
2016  *  stmmac_poll - stmmac poll method (NAPI)
2017  *  @napi : pointer to the napi structure.
2018  *  @budget : maximum number of packets that the current CPU can receive from
2019  *            all interfaces.
2020  *  Description :
2021  *  To look at the incoming frames and clear the tx resources.
2022  */
2023 static int stmmac_poll(struct napi_struct *napi, int budget)
2024 {
2025         struct stmmac_priv *priv = container_of(napi, struct stmmac_priv, napi);
2026         int work_done = 0;
2027
2028         priv->xstats.napi_poll++;
2029         stmmac_tx_clean(priv);
2030
2031         work_done = stmmac_rx(priv, budget);
2032         if (work_done < budget) {
2033                 napi_complete(napi);
2034                 stmmac_enable_dma_irq(priv);
2035         }
2036         return work_done;
2037 }
2038
2039 /**
2040  *  stmmac_tx_timeout
2041  *  @dev : Pointer to net device structure
2042  *  Description: this function is called when a packet transmission fails to
2043  *   complete within a reasonable time. The driver will mark the error in the
2044  *   netdev structure and arrange for the device to be reset to a sane state
2045  *   in order to transmit a new packet.
2046  */
2047 static void stmmac_tx_timeout(struct net_device *dev)
2048 {
2049         struct stmmac_priv *priv = netdev_priv(dev);
2050
2051         /* Clear Tx resources and restart transmitting again */
2052         stmmac_tx_err(priv);
2053 }
2054
2055 /* Configuration changes (passed on by ifconfig) */
2056 static int stmmac_config(struct net_device *dev, struct ifmap *map)
2057 {
2058         if (dev->flags & IFF_UP)        /* can't act on a running interface */
2059                 return -EBUSY;
2060
2061         /* Don't allow changing the I/O address */
2062         if (map->base_addr != dev->base_addr) {
2063                 pr_warning("%s: can't change I/O address\n", dev->name);
2064                 return -EOPNOTSUPP;
2065         }
2066
2067         /* Don't allow changing the IRQ */
2068         if (map->irq != dev->irq) {
2069                 pr_warning("%s: can't change IRQ number %d\n",
2070                        dev->name, dev->irq);
2071                 return -EOPNOTSUPP;
2072         }
2073
2074         /* ignore other fields */
2075         return 0;
2076 }
2077
2078 /**
2079  *  stmmac_set_rx_mode - entry point for multicast addressing
2080  *  @dev : pointer to the device structure
2081  *  Description:
2082  *  This function is a driver entry point which gets called by the kernel
2083  *  whenever multicast addresses must be enabled/disabled.
2084  *  Return value:
2085  *  void.
2086  */
2087 static void stmmac_set_rx_mode(struct net_device *dev)
2088 {
2089         struct stmmac_priv *priv = netdev_priv(dev);
2090
2091         spin_lock(&priv->lock);
2092         priv->hw->mac->set_filter(dev, priv->synopsys_id);
2093         spin_unlock(&priv->lock);
2094 }
2095
2096 /**
2097  *  stmmac_change_mtu - entry point to change MTU size for the device.
2098  *  @dev : device pointer.
2099  *  @new_mtu : the new MTU size for the device.
2100  *  Description: the Maximum Transfer Unit (MTU) is used by the network layer
2101  *  to drive packet transmission. Ethernet has an MTU of 1500 octets
2102  *  (ETH_DATA_LEN). This value can be changed with ifconfig.
2103  *  Return value:
2104  *  0 on success and an appropriate (-)ve integer as defined in errno.h
2105  *  file on failure.
2106  */
2107 static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
2108 {
2109         struct stmmac_priv *priv = netdev_priv(dev);
2110         int max_mtu;
2111
2112         if (netif_running(dev)) {
2113                 pr_err("%s: must be stopped to change its MTU\n", dev->name);
2114                 return -EBUSY;
2115         }
2116
2117         if (priv->plat->enh_desc)
2118                 max_mtu = JUMBO_LEN;
2119         else
2120                 max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN);
2121
2122         if ((new_mtu < 46) || (new_mtu > max_mtu)) {
2123                 pr_err("%s: invalid MTU, max MTU is: %d\n", dev->name, max_mtu);
2124                 return -EINVAL;
2125         }
2126
2127         dev->mtu = new_mtu;
2128         netdev_update_features(dev);
2129
2130         return 0;
2131 }
2132
2133 static netdev_features_t stmmac_fix_features(struct net_device *dev,
2134         netdev_features_t features)
2135 {
2136         struct stmmac_priv *priv = netdev_priv(dev);
2137
2138         if (priv->plat->rx_coe == STMMAC_RX_COE_NONE)
2139                 features &= ~NETIF_F_RXCSUM;
2140         else if (priv->plat->rx_coe == STMMAC_RX_COE_TYPE1)
2141                 features &= ~NETIF_F_IPV6_CSUM;
2142         if (!priv->plat->tx_coe)
2143                 features &= ~NETIF_F_ALL_CSUM;
2144
2145         /* Some GMAC devices have a bugged Jumbo frame support that
2146          * needs to have the Tx COE disabled for oversized frames
2147          * (due to limited buffer sizes). In this case we disable
2148          * the TX csum insertionin the TDES and not use SF. */
2149         if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN))
2150                 features &= ~NETIF_F_ALL_CSUM;
2151
2152         return features;
2153 }
2154
2155 static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
2156 {
2157         struct net_device *dev = (struct net_device *)dev_id;
2158         struct stmmac_priv *priv = netdev_priv(dev);
2159
2160         if (unlikely(!dev)) {
2161                 pr_err("%s: invalid dev pointer\n", __func__);
2162                 return IRQ_NONE;
2163         }
2164
2165         /* To handle GMAC own interrupts */
2166         if (priv->plat->has_gmac) {
2167                 int status = priv->hw->mac->host_irq_status((void __iomem *)
2168                                                             dev->base_addr,
2169                                                             &priv->xstats);
2170                 if (unlikely(status)) {
2171                         /* For LPI we need to save the tx status */
2172                         if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE)
2173                                 priv->tx_path_in_lpi_mode = true;
2174                         if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE)
2175                                 priv->tx_path_in_lpi_mode = false;
2176                 }
2177         }
2178
2179         /* To handle DMA interrupts */
2180         stmmac_dma_interrupt(priv);
2181
2182         return IRQ_HANDLED;
2183 }
2184
2185 #ifdef CONFIG_NET_POLL_CONTROLLER
2186 /* Polling receive - used by NETCONSOLE and other diagnostic tools
2187  * to allow network I/O with interrupts disabled. */
2188 static void stmmac_poll_controller(struct net_device *dev)
2189 {
2190         disable_irq(dev->irq);
2191         stmmac_interrupt(dev->irq, dev);
2192         enable_irq(dev->irq);
2193 }
2194 #endif
2195
2196 /**
2197  *  stmmac_ioctl - Entry point for the Ioctl
2198  *  @dev: Device pointer.
2199  *  @rq: An IOCTL specefic structure, that can contain a pointer to
2200  *  a proprietary structure used to pass information to the driver.
2201  *  @cmd: IOCTL command
2202  *  Description:
2203  *  Currently it supports just the phy_mii_ioctl(...) and HW time stamping.
2204  */
2205 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2206 {
2207         struct stmmac_priv *priv = netdev_priv(dev);
2208         int ret = -EOPNOTSUPP;
2209
2210         if (!netif_running(dev))
2211                 return -EINVAL;
2212
2213         switch (cmd) {
2214         case SIOCGMIIPHY:
2215         case SIOCGMIIREG:
2216         case SIOCSMIIREG:
2217                 if (!priv->phydev)
2218                         return -EINVAL;
2219                 ret = phy_mii_ioctl(priv->phydev, rq, cmd);
2220                 break;
2221         case SIOCSHWTSTAMP:
2222                 ret = stmmac_hwtstamp_ioctl(dev, rq);
2223                 break;
2224         default:
2225                 break;
2226         }
2227
2228         return ret;
2229 }
2230
2231 #ifdef CONFIG_STMMAC_DEBUG_FS
2232 static struct dentry *stmmac_fs_dir;
2233 static struct dentry *stmmac_rings_status;
2234 static struct dentry *stmmac_dma_cap;
2235
2236 static void sysfs_display_ring(void *head, int size, int extend_desc,
2237                                 struct seq_file *seq)
2238 {
2239         int i;
2240         struct dma_extended_desc *ep = (struct dma_extended_desc *) head;
2241         struct dma_desc *p = (struct dma_desc *) head;
2242
2243         for (i = 0; i < size; i++) {
2244                 u64 x;
2245                 if (extend_desc) {
2246                         x = *(u64 *) ep;
2247                         seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
2248                                    i, (unsigned int) virt_to_phys(ep),
2249                                    (unsigned int) x, (unsigned int) (x >> 32),
2250                                    ep->basic.des2, ep->basic.des3);
2251                         ep++;
2252                 } else {
2253                         x = *(u64 *) p;
2254                         seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
2255                                    i, (unsigned int) virt_to_phys(ep),
2256                                    (unsigned int) x, (unsigned int) (x >> 32),
2257                                    p->des2, p->des3);
2258                         p++;
2259                 }
2260                 seq_printf(seq, "\n");
2261         }
2262 }
2263
2264 static int stmmac_sysfs_ring_read(struct seq_file *seq, void *v)
2265 {
2266         struct net_device *dev = seq->private;
2267         struct stmmac_priv *priv = netdev_priv(dev);
2268         unsigned int txsize = priv->dma_tx_size;
2269         unsigned int rxsize = priv->dma_rx_size;
2270
2271         if (priv->extend_desc) {
2272                 seq_printf(seq, "Extended RX descriptor ring:\n");
2273                 sysfs_display_ring((void *) priv->dma_erx, rxsize, 1, seq);
2274                 seq_printf(seq, "Extended TX descriptor ring:\n");
2275                 sysfs_display_ring((void *) priv->dma_etx, txsize, 1, seq);
2276         } else {
2277                 seq_printf(seq, "RX descriptor ring:\n");
2278                 sysfs_display_ring((void *)priv->dma_rx, rxsize, 0, seq);
2279                 seq_printf(seq, "TX descriptor ring:\n");
2280                 sysfs_display_ring((void *)priv->dma_tx, txsize, 0, seq);
2281         }
2282
2283         return 0;
2284 }
2285
2286 static int stmmac_sysfs_ring_open(struct inode *inode, struct file *file)
2287 {
2288         return single_open(file, stmmac_sysfs_ring_read, inode->i_private);
2289 }
2290
2291 static const struct file_operations stmmac_rings_status_fops = {
2292         .owner = THIS_MODULE,
2293         .open = stmmac_sysfs_ring_open,
2294         .read = seq_read,
2295         .llseek = seq_lseek,
2296         .release = single_release,
2297 };
2298
2299 static int stmmac_sysfs_dma_cap_read(struct seq_file *seq, void *v)
2300 {
2301         struct net_device *dev = seq->private;
2302         struct stmmac_priv *priv = netdev_priv(dev);
2303
2304         if (!priv->hw_cap_support) {
2305                 seq_printf(seq, "DMA HW features not supported\n");
2306                 return 0;
2307         }
2308
2309         seq_printf(seq, "==============================\n");
2310         seq_printf(seq, "\tDMA HW features\n");
2311         seq_printf(seq, "==============================\n");
2312
2313         seq_printf(seq, "\t10/100 Mbps %s\n",
2314                    (priv->dma_cap.mbps_10_100) ? "Y" : "N");
2315         seq_printf(seq, "\t1000 Mbps %s\n",
2316                    (priv->dma_cap.mbps_1000) ? "Y" : "N");
2317         seq_printf(seq, "\tHalf duple %s\n",
2318                    (priv->dma_cap.half_duplex) ? "Y" : "N");
2319         seq_printf(seq, "\tHash Filter: %s\n",
2320                    (priv->dma_cap.hash_filter) ? "Y" : "N");
2321         seq_printf(seq, "\tMultiple MAC address registers: %s\n",
2322                    (priv->dma_cap.multi_addr) ? "Y" : "N");
2323         seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfatces): %s\n",
2324                    (priv->dma_cap.pcs) ? "Y" : "N");
2325         seq_printf(seq, "\tSMA (MDIO) Interface: %s\n",
2326                    (priv->dma_cap.sma_mdio) ? "Y" : "N");
2327         seq_printf(seq, "\tPMT Remote wake up: %s\n",
2328                    (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N");
2329         seq_printf(seq, "\tPMT Magic Frame: %s\n",
2330                    (priv->dma_cap.pmt_magic_frame) ? "Y" : "N");
2331         seq_printf(seq, "\tRMON module: %s\n",
2332                    (priv->dma_cap.rmon) ? "Y" : "N");
2333         seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n",
2334                    (priv->dma_cap.time_stamp) ? "Y" : "N");
2335         seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp:%s\n",
2336                    (priv->dma_cap.atime_stamp) ? "Y" : "N");
2337         seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE) %s\n",
2338                    (priv->dma_cap.eee) ? "Y" : "N");
2339         seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N");
2340         seq_printf(seq, "\tChecksum Offload in TX: %s\n",
2341                    (priv->dma_cap.tx_coe) ? "Y" : "N");
2342         seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n",
2343                    (priv->dma_cap.rx_coe_type1) ? "Y" : "N");
2344         seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n",
2345                    (priv->dma_cap.rx_coe_type2) ? "Y" : "N");
2346         seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n",
2347                    (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N");
2348         seq_printf(seq, "\tNumber of Additional RX channel: %d\n",
2349                    priv->dma_cap.number_rx_channel);
2350         seq_printf(seq, "\tNumber of Additional TX channel: %d\n",
2351                    priv->dma_cap.number_tx_channel);
2352         seq_printf(seq, "\tEnhanced descriptors: %s\n",
2353                    (priv->dma_cap.enh_desc) ? "Y" : "N");
2354
2355         return 0;
2356 }
2357
2358 static int stmmac_sysfs_dma_cap_open(struct inode *inode, struct file *file)
2359 {
2360         return single_open(file, stmmac_sysfs_dma_cap_read, inode->i_private);
2361 }
2362
2363 static const struct file_operations stmmac_dma_cap_fops = {
2364         .owner = THIS_MODULE,
2365         .open = stmmac_sysfs_dma_cap_open,
2366         .read = seq_read,
2367         .llseek = seq_lseek,
2368         .release = single_release,
2369 };
2370
2371 static int stmmac_init_fs(struct net_device *dev)
2372 {
2373         /* Create debugfs entries */
2374         stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL);
2375
2376         if (!stmmac_fs_dir || IS_ERR(stmmac_fs_dir)) {
2377                 pr_err("ERROR %s, debugfs create directory failed\n",
2378                        STMMAC_RESOURCE_NAME);
2379
2380                 return -ENOMEM;
2381         }
2382
2383         /* Entry to report DMA RX/TX rings */
2384         stmmac_rings_status = debugfs_create_file("descriptors_status",
2385                                            S_IRUGO, stmmac_fs_dir, dev,
2386                                            &stmmac_rings_status_fops);
2387
2388         if (!stmmac_rings_status || IS_ERR(stmmac_rings_status)) {
2389                 pr_info("ERROR creating stmmac ring debugfs file\n");
2390                 debugfs_remove(stmmac_fs_dir);
2391
2392                 return -ENOMEM;
2393         }
2394
2395         /* Entry to report the DMA HW features */
2396         stmmac_dma_cap = debugfs_create_file("dma_cap", S_IRUGO, stmmac_fs_dir,
2397                                              dev, &stmmac_dma_cap_fops);
2398
2399         if (!stmmac_dma_cap || IS_ERR(stmmac_dma_cap)) {
2400                 pr_info("ERROR creating stmmac MMC debugfs file\n");
2401                 debugfs_remove(stmmac_rings_status);
2402                 debugfs_remove(stmmac_fs_dir);
2403
2404                 return -ENOMEM;
2405         }
2406
2407         return 0;
2408 }
2409
2410 static void stmmac_exit_fs(void)
2411 {
2412         debugfs_remove(stmmac_rings_status);
2413         debugfs_remove(stmmac_dma_cap);
2414         debugfs_remove(stmmac_fs_dir);
2415 }
2416 #endif /* CONFIG_STMMAC_DEBUG_FS */
2417
2418 static const struct net_device_ops stmmac_netdev_ops = {
2419         .ndo_open = stmmac_open,
2420         .ndo_start_xmit = stmmac_xmit,
2421         .ndo_stop = stmmac_release,
2422         .ndo_change_mtu = stmmac_change_mtu,
2423         .ndo_fix_features = stmmac_fix_features,
2424         .ndo_set_rx_mode = stmmac_set_rx_mode,
2425         .ndo_tx_timeout = stmmac_tx_timeout,
2426         .ndo_do_ioctl = stmmac_ioctl,
2427         .ndo_set_config = stmmac_config,
2428 #ifdef CONFIG_NET_POLL_CONTROLLER
2429         .ndo_poll_controller = stmmac_poll_controller,
2430 #endif
2431         .ndo_set_mac_address = eth_mac_addr,
2432 };
2433
2434 /**
2435  *  stmmac_hw_init - Init the MAC device
2436  *  @priv : pointer to the private device structure.
2437  *  Description: this function detects which MAC device
2438  *  (GMAC/MAC10-100) has to attached, checks the HW capability
2439  *  (if supported) and sets the driver's features (for example
2440  *  to use the ring or chaine mode or support the normal/enh
2441  *  descriptor structure).
2442  */
2443 static int stmmac_hw_init(struct stmmac_priv *priv)
2444 {
2445         int ret;
2446         struct mac_device_info *mac;
2447
2448         /* Identify the MAC HW device */
2449         if (priv->plat->has_gmac) {
2450                 priv->dev->priv_flags |= IFF_UNICAST_FLT;
2451                 mac = dwmac1000_setup(priv->ioaddr);
2452         } else {
2453                 mac = dwmac100_setup(priv->ioaddr);
2454         }
2455         if (!mac)
2456                 return -ENOMEM;
2457
2458         priv->hw = mac;
2459
2460         /* Get and dump the chip ID */
2461         priv->synopsys_id = stmmac_get_synopsys_id(priv);
2462
2463         /* To use alternate (extended) or normal descriptor structures */
2464         stmmac_selec_desc_mode(priv);
2465
2466         /* To use the chained or ring mode */
2467         if (chain_mode) {
2468                 priv->hw->chain = &chain_mode_ops;
2469                 pr_info(" Chain mode enabled\n");
2470                 priv->mode = STMMAC_CHAIN_MODE;
2471         } else {
2472                 priv->hw->ring = &ring_mode_ops;
2473                 pr_info(" Ring mode enabled\n");
2474                 priv->mode = STMMAC_RING_MODE;
2475         }
2476
2477         /* Get the HW capability (new GMAC newer than 3.50a) */
2478         priv->hw_cap_support = stmmac_get_hw_features(priv);
2479         if (priv->hw_cap_support) {
2480                 pr_info(" DMA HW capability register supported");
2481
2482                 /* We can override some gmac/dma configuration fields: e.g.
2483                  * enh_desc, tx_coe (e.g. that are passed through the
2484                  * platform) with the values from the HW capability
2485                  * register (if supported).
2486                  */
2487                 priv->plat->enh_desc = priv->dma_cap.enh_desc;
2488                 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up;
2489
2490                 priv->plat->tx_coe = priv->dma_cap.tx_coe;
2491
2492                 if (priv->dma_cap.rx_coe_type2)
2493                         priv->plat->rx_coe = STMMAC_RX_COE_TYPE2;
2494                 else if (priv->dma_cap.rx_coe_type1)
2495                         priv->plat->rx_coe = STMMAC_RX_COE_TYPE1;
2496
2497         } else
2498                 pr_info(" No HW DMA feature register supported");
2499
2500         /* Enable the IPC (Checksum Offload) and check if the feature has been
2501          * enabled during the core configuration. */
2502         ret = priv->hw->mac->rx_ipc(priv->ioaddr);
2503         if (!ret) {
2504                 pr_warning(" RX IPC Checksum Offload not configured.\n");
2505                 priv->plat->rx_coe = STMMAC_RX_COE_NONE;
2506         }
2507
2508         if (priv->plat->rx_coe)
2509                 pr_info(" RX Checksum Offload Engine supported (type %d)\n",
2510                         priv->plat->rx_coe);
2511         if (priv->plat->tx_coe)
2512                 pr_info(" TX Checksum insertion supported\n");
2513
2514         if (priv->plat->pmt) {
2515                 pr_info(" Wake-Up On Lan supported\n");
2516                 device_set_wakeup_capable(priv->device, 1);
2517         }
2518
2519         return 0;
2520 }
2521
2522 /**
2523  * stmmac_dvr_probe
2524  * @device: device pointer
2525  * @plat_dat: platform data pointer
2526  * @addr: iobase memory address
2527  * Description: this is the main probe function used to
2528  * call the alloc_etherdev, allocate the priv structure.
2529  */
2530 struct stmmac_priv *stmmac_dvr_probe(struct device *device,
2531                                      struct plat_stmmacenet_data *plat_dat,
2532                                      void __iomem *addr)
2533 {
2534         int ret = 0;
2535         struct net_device *ndev = NULL;
2536         struct stmmac_priv *priv;
2537
2538         ndev = alloc_etherdev(sizeof(struct stmmac_priv));
2539         if (!ndev)
2540                 return NULL;
2541
2542         SET_NETDEV_DEV(ndev, device);
2543
2544         priv = netdev_priv(ndev);
2545         priv->device = device;
2546         priv->dev = ndev;
2547
2548         ether_setup(ndev);
2549
2550         stmmac_set_ethtool_ops(ndev);
2551         priv->pause = pause;
2552         priv->plat = plat_dat;
2553         priv->ioaddr = addr;
2554         priv->dev->base_addr = (unsigned long)addr;
2555
2556         /* Verify driver arguments */
2557         stmmac_verify_args();
2558
2559         /* Override with kernel parameters if supplied XXX CRS XXX
2560          * this needs to have multiple instances */
2561         if ((phyaddr >= 0) && (phyaddr <= 31))
2562                 priv->plat->phy_addr = phyaddr;
2563
2564         /* Init MAC and get the capabilities */
2565         ret = stmmac_hw_init(priv);
2566         if (ret)
2567                 goto error_free_netdev;
2568
2569         ndev->netdev_ops = &stmmac_netdev_ops;
2570
2571         ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2572                             NETIF_F_RXCSUM;
2573         ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA;
2574         ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
2575 #ifdef STMMAC_VLAN_TAG_USED
2576         /* Both mac100 and gmac support receive VLAN tag detection */
2577         ndev->features |= NETIF_F_HW_VLAN_RX;
2578 #endif
2579         priv->msg_enable = netif_msg_init(debug, default_msg_level);
2580
2581         if (flow_ctrl)
2582                 priv->flow_ctrl = FLOW_AUTO;    /* RX/TX pause on */
2583
2584         /* Rx Watchdog is available in the COREs newer than the 3.40.
2585          * In some case, for example on bugged HW this feature
2586          * has to be disable and this can be done by passing the
2587          * riwt_off field from the platform.
2588          */
2589         if ((priv->synopsys_id >= DWMAC_CORE_3_50) && (!priv->plat->riwt_off)) {
2590                 priv->use_riwt = 1;
2591                 pr_info(" Enable RX Mitigation via HW Watchdog Timer\n");
2592         }
2593
2594         netif_napi_add(ndev, &priv->napi, stmmac_poll, 64);
2595
2596         spin_lock_init(&priv->lock);
2597         spin_lock_init(&priv->tx_lock);
2598
2599         ret = register_netdev(ndev);
2600         if (ret) {
2601                 pr_err("%s: ERROR %i registering the device\n", __func__, ret);
2602                 goto error_netdev_register;
2603         }
2604
2605         priv->stmmac_clk = clk_get(priv->device, STMMAC_RESOURCE_NAME);
2606         if (IS_ERR(priv->stmmac_clk)) {
2607                 pr_warning("%s: warning: cannot get CSR clock\n", __func__);
2608                 goto error_clk_get;
2609         }
2610
2611         /* If a specific clk_csr value is passed from the platform
2612          * this means that the CSR Clock Range selection cannot be
2613          * changed at run-time and it is fixed. Viceversa the driver'll try to
2614          * set the MDC clock dynamically according to the csr actual
2615          * clock input.
2616          */
2617         if (!priv->plat->clk_csr)
2618                 stmmac_clk_csr_set(priv);
2619         else
2620                 priv->clk_csr = priv->plat->clk_csr;
2621
2622         stmmac_check_pcs_mode(priv);
2623
2624         if (!priv->pcs) {
2625                 /* MDIO bus Registration */
2626                 ret = stmmac_mdio_register(ndev);
2627                 if (ret < 0) {
2628                         pr_debug("%s: MDIO bus (id: %d) registration failed",
2629                                  __func__, priv->plat->bus_id);
2630                         goto error_mdio_register;
2631                 }
2632         }
2633
2634         return priv;
2635
2636 error_mdio_register:
2637         clk_put(priv->stmmac_clk);
2638 error_clk_get:
2639         unregister_netdev(ndev);
2640 error_netdev_register:
2641         netif_napi_del(&priv->napi);
2642 error_free_netdev:
2643         free_netdev(ndev);
2644
2645         return NULL;
2646 }
2647
2648 /**
2649  * stmmac_dvr_remove
2650  * @ndev: net device pointer
2651  * Description: this function resets the TX/RX processes, disables the MAC RX/TX
2652  * changes the link status, releases the DMA descriptor rings.
2653  */
2654 int stmmac_dvr_remove(struct net_device *ndev)
2655 {
2656         struct stmmac_priv *priv = netdev_priv(ndev);
2657
2658         pr_info("%s:\n\tremoving driver", __func__);
2659
2660         priv->hw->dma->stop_rx(priv->ioaddr);
2661         priv->hw->dma->stop_tx(priv->ioaddr);
2662
2663         stmmac_set_mac(priv->ioaddr, false);
2664         if (!priv->pcs)
2665                 stmmac_mdio_unregister(ndev);
2666         netif_carrier_off(ndev);
2667         unregister_netdev(ndev);
2668         free_netdev(ndev);
2669
2670         return 0;
2671 }
2672
2673 #ifdef CONFIG_PM
2674 int stmmac_suspend(struct net_device *ndev)
2675 {
2676         struct stmmac_priv *priv = netdev_priv(ndev);
2677         unsigned long flags;
2678
2679         if (!ndev || !netif_running(ndev))
2680                 return 0;
2681
2682         if (priv->phydev)
2683                 phy_stop(priv->phydev);
2684
2685         spin_lock_irqsave(&priv->lock, flags);
2686
2687         netif_device_detach(ndev);
2688         netif_stop_queue(ndev);
2689
2690         napi_disable(&priv->napi);
2691
2692         /* Stop TX/RX DMA */
2693         priv->hw->dma->stop_tx(priv->ioaddr);
2694         priv->hw->dma->stop_rx(priv->ioaddr);
2695
2696         stmmac_clear_descriptors(priv);
2697
2698         /* Enable Power down mode by programming the PMT regs */
2699         if (device_may_wakeup(priv->device))
2700                 priv->hw->mac->pmt(priv->ioaddr, priv->wolopts);
2701         else {
2702                 stmmac_set_mac(priv->ioaddr, false);
2703                 /* Disable clock in case of PWM is off */
2704                 clk_disable_unprepare(priv->stmmac_clk);
2705         }
2706         spin_unlock_irqrestore(&priv->lock, flags);
2707         return 0;
2708 }
2709
2710 int stmmac_resume(struct net_device *ndev)
2711 {
2712         struct stmmac_priv *priv = netdev_priv(ndev);
2713         unsigned long flags;
2714
2715         if (!netif_running(ndev))
2716                 return 0;
2717
2718         spin_lock_irqsave(&priv->lock, flags);
2719
2720         /* Power Down bit, into the PM register, is cleared
2721          * automatically as soon as a magic packet or a Wake-up frame
2722          * is received. Anyway, it's better to manually clear
2723          * this bit because it can generate problems while resuming
2724          * from another devices (e.g. serial console). */
2725         if (device_may_wakeup(priv->device))
2726                 priv->hw->mac->pmt(priv->ioaddr, 0);
2727         else
2728                 /* enable the clk prevously disabled */
2729                 clk_prepare_enable(priv->stmmac_clk);
2730
2731         netif_device_attach(ndev);
2732
2733         /* Enable the MAC and DMA */
2734         stmmac_set_mac(priv->ioaddr, true);
2735         priv->hw->dma->start_tx(priv->ioaddr);
2736         priv->hw->dma->start_rx(priv->ioaddr);
2737
2738         napi_enable(&priv->napi);
2739
2740         netif_start_queue(ndev);
2741
2742         spin_unlock_irqrestore(&priv->lock, flags);
2743
2744         if (priv->phydev)
2745                 phy_start(priv->phydev);
2746
2747         return 0;
2748 }
2749
2750 int stmmac_freeze(struct net_device *ndev)
2751 {
2752         if (!ndev || !netif_running(ndev))
2753                 return 0;
2754
2755         return stmmac_release(ndev);
2756 }
2757
2758 int stmmac_restore(struct net_device *ndev)
2759 {
2760         if (!ndev || !netif_running(ndev))
2761                 return 0;
2762
2763         return stmmac_open(ndev);
2764 }
2765 #endif /* CONFIG_PM */
2766
2767 /* Driver can be configured w/ and w/ both PCI and Platf drivers
2768  * depending on the configuration selected.
2769  */
2770 static int __init stmmac_init(void)
2771 {
2772         int ret;
2773
2774         ret = stmmac_register_platform();
2775         if (ret)
2776                 goto err;
2777         ret = stmmac_register_pci();
2778         if (ret)
2779                 goto err_pci;
2780         return 0;
2781 err_pci:
2782         stmmac_unregister_platform();
2783 err:
2784         pr_err("stmmac: driver registration failed\n");
2785         return ret;
2786 }
2787
2788 static void __exit stmmac_exit(void)
2789 {
2790         stmmac_unregister_platform();
2791         stmmac_unregister_pci();
2792 }
2793
2794 module_init(stmmac_init);
2795 module_exit(stmmac_exit);
2796
2797 #ifndef MODULE
2798 static int __init stmmac_cmdline_opt(char *str)
2799 {
2800         char *opt;
2801
2802         if (!str || !*str)
2803                 return -EINVAL;
2804         while ((opt = strsep(&str, ",")) != NULL) {
2805                 if (!strncmp(opt, "debug:", 6)) {
2806                         if (kstrtoint(opt + 6, 0, &debug))
2807                                 goto err;
2808                 } else if (!strncmp(opt, "phyaddr:", 8)) {
2809                         if (kstrtoint(opt + 8, 0, &phyaddr))
2810                                 goto err;
2811                 } else if (!strncmp(opt, "dma_txsize:", 11)) {
2812                         if (kstrtoint(opt + 11, 0, &dma_txsize))
2813                                 goto err;
2814                 } else if (!strncmp(opt, "dma_rxsize:", 11)) {
2815                         if (kstrtoint(opt + 11, 0, &dma_rxsize))
2816                                 goto err;
2817                 } else if (!strncmp(opt, "buf_sz:", 7)) {
2818                         if (kstrtoint(opt + 7, 0, &buf_sz))
2819                                 goto err;
2820                 } else if (!strncmp(opt, "tc:", 3)) {
2821                         if (kstrtoint(opt + 3, 0, &tc))
2822                                 goto err;
2823                 } else if (!strncmp(opt, "watchdog:", 9)) {
2824                         if (kstrtoint(opt + 9, 0, &watchdog))
2825                                 goto err;
2826                 } else if (!strncmp(opt, "flow_ctrl:", 10)) {
2827                         if (kstrtoint(opt + 10, 0, &flow_ctrl))
2828                                 goto err;
2829                 } else if (!strncmp(opt, "pause:", 6)) {
2830                         if (kstrtoint(opt + 6, 0, &pause))
2831                                 goto err;
2832                 } else if (!strncmp(opt, "eee_timer:", 10)) {
2833                         if (kstrtoint(opt + 10, 0, &eee_timer))
2834                                 goto err;
2835                 } else if (!strncmp(opt, "chain_mode:", 11)) {
2836                         if (kstrtoint(opt + 11, 0, &chain_mode))
2837                                 goto err;
2838                 }
2839         }
2840         return 0;
2841
2842 err:
2843         pr_err("%s: ERROR broken module parameter conversion", __func__);
2844         return -EINVAL;
2845 }
2846
2847 __setup("stmmaceth=", stmmac_cmdline_opt);
2848 #endif
2849
2850 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver");
2851 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
2852 MODULE_LICENSE("GPL");