1 /* cassini.c: Sun Microsystems Cassini(+) ethernet driver.
3 * Copyright (C) 2004 Sun Microsystems Inc.
4 * Copyright (C) 2003 Adrian Sun (asun@darksunrising.com)
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of the
9 * License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
21 * This driver uses the sungem driver (c) David Miller
22 * (davem@redhat.com) as its basis.
24 * The cassini chip has a number of features that distinguish it from
26 * 4 transmit descriptor rings that are used for either QoS (VLAN) or
27 * load balancing (non-VLAN mode)
28 * batching of multiple packets
29 * multiple CPU dispatching
30 * page-based RX descriptor engine with separate completion rings
31 * Gigabit support (GMII and PCS interface)
32 * MIF link up/down detection works
34 * RX is handled by page sized buffers that are attached as fragments to
35 * the skb. here's what's done:
36 * -- driver allocates pages at a time and keeps reference counts
38 * -- the upper protocol layers assume that the header is in the skb
39 * itself. as a result, cassini will copy a small amount (64 bytes)
41 * -- driver appends the rest of the data pages as frags to skbuffs
42 * and increments the reference count
43 * -- on page reclamation, the driver swaps the page with a spare page.
44 * if that page is still in use, it frees its reference to that page,
45 * and allocates a new page for use. otherwise, it just recycles the
48 * NOTE: cassini can parse the header. however, it's not worth it
49 * as long as the network stack requires a header copy.
51 * TX has 4 queues. currently these queues are used in a round-robin
52 * fashion for load balancing. They can also be used for QoS. for that
53 * to work, however, QoS information needs to be exposed down to the driver
54 * level so that subqueues get targeted to particular transmit rings.
55 * alternatively, the queues can be configured via use of the all-purpose
58 * RX DATA: the rx completion ring has all the info, but the rx desc
59 * ring has all of the data. RX can conceivably come in under multiple
60 * interrupts, but the INT# assignment needs to be set up properly by
61 * the BIOS and conveyed to the driver. PCI BIOSes don't know how to do
62 * that. also, the two descriptor rings are designed to distinguish between
63 * encrypted and non-encrypted packets, but we use them for buffering
66 * by default, the selective clear mask is set up to process rx packets.
69 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
71 #include <linux/module.h>
72 #include <linux/kernel.h>
73 #include <linux/types.h>
74 #include <linux/compiler.h>
75 #include <linux/slab.h>
76 #include <linux/delay.h>
77 #include <linux/init.h>
78 #include <linux/interrupt.h>
79 #include <linux/vmalloc.h>
80 #include <linux/ioport.h>
81 #include <linux/pci.h>
83 #include <linux/highmem.h>
84 #include <linux/list.h>
85 #include <linux/dma-mapping.h>
87 #include <linux/netdevice.h>
88 #include <linux/etherdevice.h>
89 #include <linux/skbuff.h>
90 #include <linux/ethtool.h>
91 #include <linux/crc32.h>
92 #include <linux/random.h>
93 #include <linux/mii.h>
95 #include <linux/tcp.h>
96 #include <linux/mutex.h>
97 #include <linux/firmware.h>
99 #include <net/checksum.h>
101 #include <linux/atomic.h>
102 #include <asm/system.h>
104 #include <asm/byteorder.h>
105 #include <asm/uaccess.h>
107 #define cas_page_map(x) kmap_atomic((x), KM_SKB_DATA_SOFTIRQ)
108 #define cas_page_unmap(x) kunmap_atomic((x), KM_SKB_DATA_SOFTIRQ)
109 #define CAS_NCPUS num_online_cpus()
111 #define cas_skb_release(x) netif_rx(x)
113 /* select which firmware to use */
114 #define USE_HP_WORKAROUND
115 #define HP_WORKAROUND_DEFAULT /* select which firmware to use as default */
116 #define CAS_HP_ALT_FIRMWARE cas_prog_null /* alternate firmware */
120 #define USE_TX_COMPWB /* use completion writeback registers */
121 #define USE_CSMA_CD_PROTO /* standard CSMA/CD */
122 #define USE_RX_BLANK /* hw interrupt mitigation */
123 #undef USE_ENTROPY_DEV /* don't test for entropy device */
125 /* NOTE: these aren't useable unless PCI interrupts can be assigned.
126 * also, we need to make cp->lock finer-grained.
133 #undef USE_VPD_DEBUG /* debug vpd information if defined */
135 /* rx processing options */
136 #define USE_PAGE_ORDER /* specify to allocate large rx pages */
137 #define RX_DONT_BATCH 0 /* if 1, don't batch flows */
138 #define RX_COPY_ALWAYS 0 /* if 0, use frags */
139 #define RX_COPY_MIN 64 /* copy a little to make upper layers happy */
140 #undef RX_COUNT_BUFFERS /* define to calculate RX buffer stats */
142 #define DRV_MODULE_NAME "cassini"
143 #define DRV_MODULE_VERSION "1.6"
144 #define DRV_MODULE_RELDATE "21 May 2008"
146 #define CAS_DEF_MSG_ENABLE \
156 /* length of time before we decide the hardware is borked,
157 * and dev->tx_timeout() should be called to fix the problem
159 #define CAS_TX_TIMEOUT (HZ)
160 #define CAS_LINK_TIMEOUT (22*HZ/10)
161 #define CAS_LINK_FAST_TIMEOUT (1)
163 /* timeout values for state changing. these specify the number
164 * of 10us delays to be used before giving up.
166 #define STOP_TRIES_PHY 1000
167 #define STOP_TRIES 5000
169 /* specify a minimum frame size to deal with some fifo issues
170 * max mtu == 2 * page size - ethernet header - 64 - swivel =
171 * 2 * page_size - 0x50
173 #define CAS_MIN_FRAME 97
174 #define CAS_1000MB_MIN_FRAME 255
175 #define CAS_MIN_MTU 60
176 #define CAS_MAX_MTU min(((cp->page_size << 1) - 0x50), 9000)
180 * Eliminate these and use separate atomic counters for each, to
181 * avoid a race condition.
184 #define CAS_RESET_MTU 1
185 #define CAS_RESET_ALL 2
186 #define CAS_RESET_SPARE 3
189 static char version[] __devinitdata =
190 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
192 static int cassini_debug = -1; /* -1 == use CAS_DEF_MSG_ENABLE as value */
193 static int link_mode;
195 MODULE_AUTHOR("Adrian Sun (asun@darksunrising.com)");
196 MODULE_DESCRIPTION("Sun Cassini(+) ethernet driver");
197 MODULE_LICENSE("GPL");
198 MODULE_FIRMWARE("sun/cassini.bin");
199 module_param(cassini_debug, int, 0);
200 MODULE_PARM_DESC(cassini_debug, "Cassini bitmapped debugging message enable value");
201 module_param(link_mode, int, 0);
202 MODULE_PARM_DESC(link_mode, "default link mode");
205 * Work around for a PCS bug in which the link goes down due to the chip
206 * being confused and never showing a link status of "up."
208 #define DEFAULT_LINKDOWN_TIMEOUT 5
210 * Value in seconds, for user input.
212 static int linkdown_timeout = DEFAULT_LINKDOWN_TIMEOUT;
213 module_param(linkdown_timeout, int, 0);
214 MODULE_PARM_DESC(linkdown_timeout,
215 "min reset interval in sec. for PCS linkdown issue; disabled if not positive");
218 * value in 'ticks' (units used by jiffies). Set when we init the
219 * module because 'HZ' in actually a function call on some flavors of
220 * Linux. This will default to DEFAULT_LINKDOWN_TIMEOUT * HZ.
222 static int link_transition_timeout;
226 static u16 link_modes[] __devinitdata = {
227 BMCR_ANENABLE, /* 0 : autoneg */
228 0, /* 1 : 10bt half duplex */
229 BMCR_SPEED100, /* 2 : 100bt half duplex */
230 BMCR_FULLDPLX, /* 3 : 10bt full duplex */
231 BMCR_SPEED100|BMCR_FULLDPLX, /* 4 : 100bt full duplex */
232 CAS_BMCR_SPEED1000|BMCR_FULLDPLX /* 5 : 1000bt full duplex */
235 static DEFINE_PCI_DEVICE_TABLE(cas_pci_tbl) = {
236 { PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_CASSINI,
237 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
238 { PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_SATURN,
239 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
243 MODULE_DEVICE_TABLE(pci, cas_pci_tbl);
245 static void cas_set_link_modes(struct cas *cp);
247 static inline void cas_lock_tx(struct cas *cp)
251 for (i = 0; i < N_TX_RINGS; i++)
252 spin_lock(&cp->tx_lock[i]);
255 static inline void cas_lock_all(struct cas *cp)
257 spin_lock_irq(&cp->lock);
261 /* WTZ: QA was finding deadlock problems with the previous
262 * versions after long test runs with multiple cards per machine.
263 * See if replacing cas_lock_all with safer versions helps. The
264 * symptoms QA is reporting match those we'd expect if interrupts
265 * aren't being properly restored, and we fixed a previous deadlock
266 * with similar symptoms by using save/restore versions in other
269 #define cas_lock_all_save(cp, flags) \
271 struct cas *xxxcp = (cp); \
272 spin_lock_irqsave(&xxxcp->lock, flags); \
273 cas_lock_tx(xxxcp); \
276 static inline void cas_unlock_tx(struct cas *cp)
280 for (i = N_TX_RINGS; i > 0; i--)
281 spin_unlock(&cp->tx_lock[i - 1]);
284 static inline void cas_unlock_all(struct cas *cp)
287 spin_unlock_irq(&cp->lock);
290 #define cas_unlock_all_restore(cp, flags) \
292 struct cas *xxxcp = (cp); \
293 cas_unlock_tx(xxxcp); \
294 spin_unlock_irqrestore(&xxxcp->lock, flags); \
297 static void cas_disable_irq(struct cas *cp, const int ring)
299 /* Make sure we won't get any more interrupts */
301 writel(0xFFFFFFFF, cp->regs + REG_INTR_MASK);
305 /* disable completion interrupts and selectively mask */
306 if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
308 #if defined (USE_PCI_INTB) || defined(USE_PCI_INTC) || defined(USE_PCI_INTD)
318 writel(INTRN_MASK_CLEAR_ALL | INTRN_MASK_RX_EN,
319 cp->regs + REG_PLUS_INTRN_MASK(ring));
323 writel(INTRN_MASK_CLEAR_ALL, cp->regs +
324 REG_PLUS_INTRN_MASK(ring));
330 static inline void cas_mask_intr(struct cas *cp)
334 for (i = 0; i < N_RX_COMP_RINGS; i++)
335 cas_disable_irq(cp, i);
338 static void cas_enable_irq(struct cas *cp, const int ring)
340 if (ring == 0) { /* all but TX_DONE */
341 writel(INTR_TX_DONE, cp->regs + REG_INTR_MASK);
345 if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
347 #if defined (USE_PCI_INTB) || defined(USE_PCI_INTC) || defined(USE_PCI_INTD)
357 writel(INTRN_MASK_RX_EN, cp->regs +
358 REG_PLUS_INTRN_MASK(ring));
367 static inline void cas_unmask_intr(struct cas *cp)
371 for (i = 0; i < N_RX_COMP_RINGS; i++)
372 cas_enable_irq(cp, i);
375 static inline void cas_entropy_gather(struct cas *cp)
377 #ifdef USE_ENTROPY_DEV
378 if ((cp->cas_flags & CAS_FLAG_ENTROPY_DEV) == 0)
381 batch_entropy_store(readl(cp->regs + REG_ENTROPY_IV),
382 readl(cp->regs + REG_ENTROPY_IV),
387 static inline void cas_entropy_reset(struct cas *cp)
389 #ifdef USE_ENTROPY_DEV
390 if ((cp->cas_flags & CAS_FLAG_ENTROPY_DEV) == 0)
393 writel(BIM_LOCAL_DEV_PAD | BIM_LOCAL_DEV_PROM | BIM_LOCAL_DEV_EXT,
394 cp->regs + REG_BIM_LOCAL_DEV_EN);
395 writeb(ENTROPY_RESET_STC_MODE, cp->regs + REG_ENTROPY_RESET);
396 writeb(0x55, cp->regs + REG_ENTROPY_RAND_REG);
398 /* if we read back 0x0, we don't have an entropy device */
399 if (readb(cp->regs + REG_ENTROPY_RAND_REG) == 0)
400 cp->cas_flags &= ~CAS_FLAG_ENTROPY_DEV;
404 /* access to the phy. the following assumes that we've initialized the MIF to
405 * be in frame rather than bit-bang mode
407 static u16 cas_phy_read(struct cas *cp, int reg)
410 int limit = STOP_TRIES_PHY;
412 cmd = MIF_FRAME_ST | MIF_FRAME_OP_READ;
413 cmd |= CAS_BASE(MIF_FRAME_PHY_ADDR, cp->phy_addr);
414 cmd |= CAS_BASE(MIF_FRAME_REG_ADDR, reg);
415 cmd |= MIF_FRAME_TURN_AROUND_MSB;
416 writel(cmd, cp->regs + REG_MIF_FRAME);
418 /* poll for completion */
419 while (limit-- > 0) {
421 cmd = readl(cp->regs + REG_MIF_FRAME);
422 if (cmd & MIF_FRAME_TURN_AROUND_LSB)
423 return cmd & MIF_FRAME_DATA_MASK;
425 return 0xFFFF; /* -1 */
428 static int cas_phy_write(struct cas *cp, int reg, u16 val)
430 int limit = STOP_TRIES_PHY;
433 cmd = MIF_FRAME_ST | MIF_FRAME_OP_WRITE;
434 cmd |= CAS_BASE(MIF_FRAME_PHY_ADDR, cp->phy_addr);
435 cmd |= CAS_BASE(MIF_FRAME_REG_ADDR, reg);
436 cmd |= MIF_FRAME_TURN_AROUND_MSB;
437 cmd |= val & MIF_FRAME_DATA_MASK;
438 writel(cmd, cp->regs + REG_MIF_FRAME);
440 /* poll for completion */
441 while (limit-- > 0) {
443 cmd = readl(cp->regs + REG_MIF_FRAME);
444 if (cmd & MIF_FRAME_TURN_AROUND_LSB)
450 static void cas_phy_powerup(struct cas *cp)
452 u16 ctl = cas_phy_read(cp, MII_BMCR);
454 if ((ctl & BMCR_PDOWN) == 0)
457 cas_phy_write(cp, MII_BMCR, ctl);
460 static void cas_phy_powerdown(struct cas *cp)
462 u16 ctl = cas_phy_read(cp, MII_BMCR);
464 if (ctl & BMCR_PDOWN)
467 cas_phy_write(cp, MII_BMCR, ctl);
470 /* cp->lock held. note: the last put_page will free the buffer */
471 static int cas_page_free(struct cas *cp, cas_page_t *page)
473 pci_unmap_page(cp->pdev, page->dma_addr, cp->page_size,
475 __free_pages(page->buffer, cp->page_order);
480 #ifdef RX_COUNT_BUFFERS
481 #define RX_USED_ADD(x, y) ((x)->used += (y))
482 #define RX_USED_SET(x, y) ((x)->used = (y))
484 #define RX_USED_ADD(x, y)
485 #define RX_USED_SET(x, y)
488 /* local page allocation routines for the receive buffers. jumbo pages
489 * require at least 8K contiguous and 8K aligned buffers.
491 static cas_page_t *cas_page_alloc(struct cas *cp, const gfp_t flags)
495 page = kmalloc(sizeof(cas_page_t), flags);
499 INIT_LIST_HEAD(&page->list);
500 RX_USED_SET(page, 0);
501 page->buffer = alloc_pages(flags, cp->page_order);
504 page->dma_addr = pci_map_page(cp->pdev, page->buffer, 0,
505 cp->page_size, PCI_DMA_FROMDEVICE);
513 /* initialize spare pool of rx buffers, but allocate during the open */
514 static void cas_spare_init(struct cas *cp)
516 spin_lock(&cp->rx_inuse_lock);
517 INIT_LIST_HEAD(&cp->rx_inuse_list);
518 spin_unlock(&cp->rx_inuse_lock);
520 spin_lock(&cp->rx_spare_lock);
521 INIT_LIST_HEAD(&cp->rx_spare_list);
522 cp->rx_spares_needed = RX_SPARE_COUNT;
523 spin_unlock(&cp->rx_spare_lock);
526 /* used on close. free all the spare buffers. */
527 static void cas_spare_free(struct cas *cp)
529 struct list_head list, *elem, *tmp;
531 /* free spare buffers */
532 INIT_LIST_HEAD(&list);
533 spin_lock(&cp->rx_spare_lock);
534 list_splice_init(&cp->rx_spare_list, &list);
535 spin_unlock(&cp->rx_spare_lock);
536 list_for_each_safe(elem, tmp, &list) {
537 cas_page_free(cp, list_entry(elem, cas_page_t, list));
540 INIT_LIST_HEAD(&list);
543 * Looks like Adrian had protected this with a different
544 * lock than used everywhere else to manipulate this list.
546 spin_lock(&cp->rx_inuse_lock);
547 list_splice_init(&cp->rx_inuse_list, &list);
548 spin_unlock(&cp->rx_inuse_lock);
550 spin_lock(&cp->rx_spare_lock);
551 list_splice_init(&cp->rx_inuse_list, &list);
552 spin_unlock(&cp->rx_spare_lock);
554 list_for_each_safe(elem, tmp, &list) {
555 cas_page_free(cp, list_entry(elem, cas_page_t, list));
559 /* replenish spares if needed */
560 static void cas_spare_recover(struct cas *cp, const gfp_t flags)
562 struct list_head list, *elem, *tmp;
565 /* check inuse list. if we don't need any more free buffers,
569 /* make a local copy of the list */
570 INIT_LIST_HEAD(&list);
571 spin_lock(&cp->rx_inuse_lock);
572 list_splice_init(&cp->rx_inuse_list, &list);
573 spin_unlock(&cp->rx_inuse_lock);
575 list_for_each_safe(elem, tmp, &list) {
576 cas_page_t *page = list_entry(elem, cas_page_t, list);
579 * With the lockless pagecache, cassini buffering scheme gets
580 * slightly less accurate: we might find that a page has an
581 * elevated reference count here, due to a speculative ref,
582 * and skip it as in-use. Ideally we would be able to reclaim
583 * it. However this would be such a rare case, it doesn't
584 * matter too much as we should pick it up the next time round.
586 * Importantly, if we find that the page has a refcount of 1
587 * here (our refcount), then we know it is definitely not inuse
588 * so we can reuse it.
590 if (page_count(page->buffer) > 1)
594 spin_lock(&cp->rx_spare_lock);
595 if (cp->rx_spares_needed > 0) {
596 list_add(elem, &cp->rx_spare_list);
597 cp->rx_spares_needed--;
598 spin_unlock(&cp->rx_spare_lock);
600 spin_unlock(&cp->rx_spare_lock);
601 cas_page_free(cp, page);
605 /* put any inuse buffers back on the list */
606 if (!list_empty(&list)) {
607 spin_lock(&cp->rx_inuse_lock);
608 list_splice(&list, &cp->rx_inuse_list);
609 spin_unlock(&cp->rx_inuse_lock);
612 spin_lock(&cp->rx_spare_lock);
613 needed = cp->rx_spares_needed;
614 spin_unlock(&cp->rx_spare_lock);
618 /* we still need spares, so try to allocate some */
619 INIT_LIST_HEAD(&list);
622 cas_page_t *spare = cas_page_alloc(cp, flags);
625 list_add(&spare->list, &list);
629 spin_lock(&cp->rx_spare_lock);
630 list_splice(&list, &cp->rx_spare_list);
631 cp->rx_spares_needed -= i;
632 spin_unlock(&cp->rx_spare_lock);
635 /* pull a page from the list. */
636 static cas_page_t *cas_page_dequeue(struct cas *cp)
638 struct list_head *entry;
641 spin_lock(&cp->rx_spare_lock);
642 if (list_empty(&cp->rx_spare_list)) {
643 /* try to do a quick recovery */
644 spin_unlock(&cp->rx_spare_lock);
645 cas_spare_recover(cp, GFP_ATOMIC);
646 spin_lock(&cp->rx_spare_lock);
647 if (list_empty(&cp->rx_spare_list)) {
648 netif_err(cp, rx_err, cp->dev,
649 "no spare buffers available\n");
650 spin_unlock(&cp->rx_spare_lock);
655 entry = cp->rx_spare_list.next;
657 recover = ++cp->rx_spares_needed;
658 spin_unlock(&cp->rx_spare_lock);
660 /* trigger the timer to do the recovery */
661 if ((recover & (RX_SPARE_RECOVER_VAL - 1)) == 0) {
663 atomic_inc(&cp->reset_task_pending);
664 atomic_inc(&cp->reset_task_pending_spare);
665 schedule_work(&cp->reset_task);
667 atomic_set(&cp->reset_task_pending, CAS_RESET_SPARE);
668 schedule_work(&cp->reset_task);
671 return list_entry(entry, cas_page_t, list);
675 static void cas_mif_poll(struct cas *cp, const int enable)
679 cfg = readl(cp->regs + REG_MIF_CFG);
680 cfg &= (MIF_CFG_MDIO_0 | MIF_CFG_MDIO_1);
682 if (cp->phy_type & CAS_PHY_MII_MDIO1)
683 cfg |= MIF_CFG_PHY_SELECT;
685 /* poll and interrupt on link status change. */
687 cfg |= MIF_CFG_POLL_EN;
688 cfg |= CAS_BASE(MIF_CFG_POLL_REG, MII_BMSR);
689 cfg |= CAS_BASE(MIF_CFG_POLL_PHY, cp->phy_addr);
691 writel((enable) ? ~(BMSR_LSTATUS | BMSR_ANEGCOMPLETE) : 0xFFFF,
692 cp->regs + REG_MIF_MASK);
693 writel(cfg, cp->regs + REG_MIF_CFG);
696 /* Must be invoked under cp->lock */
697 static void cas_begin_auto_negotiation(struct cas *cp, struct ethtool_cmd *ep)
703 int oldstate = cp->lstate;
704 int link_was_not_down = !(oldstate == link_down);
706 /* Setup link parameters */
709 lcntl = cp->link_cntl;
710 if (ep->autoneg == AUTONEG_ENABLE)
711 cp->link_cntl = BMCR_ANENABLE;
713 u32 speed = ethtool_cmd_speed(ep);
715 if (speed == SPEED_100)
716 cp->link_cntl |= BMCR_SPEED100;
717 else if (speed == SPEED_1000)
718 cp->link_cntl |= CAS_BMCR_SPEED1000;
719 if (ep->duplex == DUPLEX_FULL)
720 cp->link_cntl |= BMCR_FULLDPLX;
723 changed = (lcntl != cp->link_cntl);
726 if (cp->lstate == link_up) {
727 netdev_info(cp->dev, "PCS link down\n");
730 netdev_info(cp->dev, "link configuration changed\n");
733 cp->lstate = link_down;
734 cp->link_transition = LINK_TRANSITION_LINK_DOWN;
739 * WTZ: If the old state was link_up, we turn off the carrier
740 * to replicate everything we do elsewhere on a link-down
741 * event when we were already in a link-up state..
743 if (oldstate == link_up)
744 netif_carrier_off(cp->dev);
745 if (changed && link_was_not_down) {
747 * WTZ: This branch will simply schedule a full reset after
748 * we explicitly changed link modes in an ioctl. See if this
749 * fixes the link-problems we were having for forced mode.
751 atomic_inc(&cp->reset_task_pending);
752 atomic_inc(&cp->reset_task_pending_all);
753 schedule_work(&cp->reset_task);
755 mod_timer(&cp->link_timer, jiffies + CAS_LINK_TIMEOUT);
759 if (cp->phy_type & CAS_PHY_SERDES) {
760 u32 val = readl(cp->regs + REG_PCS_MII_CTRL);
762 if (cp->link_cntl & BMCR_ANENABLE) {
763 val |= (PCS_MII_RESTART_AUTONEG | PCS_MII_AUTONEG_EN);
764 cp->lstate = link_aneg;
766 if (cp->link_cntl & BMCR_FULLDPLX)
767 val |= PCS_MII_CTRL_DUPLEX;
768 val &= ~PCS_MII_AUTONEG_EN;
769 cp->lstate = link_force_ok;
771 cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
772 writel(val, cp->regs + REG_PCS_MII_CTRL);
776 ctl = cas_phy_read(cp, MII_BMCR);
777 ctl &= ~(BMCR_FULLDPLX | BMCR_SPEED100 |
778 CAS_BMCR_SPEED1000 | BMCR_ANENABLE);
779 ctl |= cp->link_cntl;
780 if (ctl & BMCR_ANENABLE) {
781 ctl |= BMCR_ANRESTART;
782 cp->lstate = link_aneg;
784 cp->lstate = link_force_ok;
786 cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
787 cas_phy_write(cp, MII_BMCR, ctl);
792 mod_timer(&cp->link_timer, jiffies + CAS_LINK_TIMEOUT);
795 /* Must be invoked under cp->lock. */
796 static int cas_reset_mii_phy(struct cas *cp)
798 int limit = STOP_TRIES_PHY;
801 cas_phy_write(cp, MII_BMCR, BMCR_RESET);
804 val = cas_phy_read(cp, MII_BMCR);
805 if ((val & BMCR_RESET) == 0)
812 static int cas_saturn_firmware_init(struct cas *cp)
814 const struct firmware *fw;
815 const char fw_name[] = "sun/cassini.bin";
818 if (PHY_NS_DP83065 != cp->phy_id)
821 err = request_firmware(&fw, fw_name, &cp->pdev->dev);
823 pr_err("Failed to load firmware \"%s\"\n",
828 pr_err("bogus length %zu in \"%s\"\n",
833 cp->fw_load_addr= fw->data[1] << 8 | fw->data[0];
834 cp->fw_size = fw->size - 2;
835 cp->fw_data = vmalloc(cp->fw_size);
838 pr_err("\"%s\" Failed %d\n", fw_name, err);
841 memcpy(cp->fw_data, &fw->data[2], cp->fw_size);
843 release_firmware(fw);
847 static void cas_saturn_firmware_load(struct cas *cp)
851 cas_phy_powerdown(cp);
853 /* expanded memory access mode */
854 cas_phy_write(cp, DP83065_MII_MEM, 0x0);
856 /* pointer configuration for new firmware */
857 cas_phy_write(cp, DP83065_MII_REGE, 0x8ff9);
858 cas_phy_write(cp, DP83065_MII_REGD, 0xbd);
859 cas_phy_write(cp, DP83065_MII_REGE, 0x8ffa);
860 cas_phy_write(cp, DP83065_MII_REGD, 0x82);
861 cas_phy_write(cp, DP83065_MII_REGE, 0x8ffb);
862 cas_phy_write(cp, DP83065_MII_REGD, 0x0);
863 cas_phy_write(cp, DP83065_MII_REGE, 0x8ffc);
864 cas_phy_write(cp, DP83065_MII_REGD, 0x39);
866 /* download new firmware */
867 cas_phy_write(cp, DP83065_MII_MEM, 0x1);
868 cas_phy_write(cp, DP83065_MII_REGE, cp->fw_load_addr);
869 for (i = 0; i < cp->fw_size; i++)
870 cas_phy_write(cp, DP83065_MII_REGD, cp->fw_data[i]);
872 /* enable firmware */
873 cas_phy_write(cp, DP83065_MII_REGE, 0x8ff8);
874 cas_phy_write(cp, DP83065_MII_REGD, 0x1);
878 /* phy initialization */
879 static void cas_phy_init(struct cas *cp)
883 /* if we're in MII/GMII mode, set up phy */
884 if (CAS_PHY_MII(cp->phy_type)) {
885 writel(PCS_DATAPATH_MODE_MII,
886 cp->regs + REG_PCS_DATAPATH_MODE);
889 cas_reset_mii_phy(cp); /* take out of isolate mode */
891 if (PHY_LUCENT_B0 == cp->phy_id) {
892 /* workaround link up/down issue with lucent */
893 cas_phy_write(cp, LUCENT_MII_REG, 0x8000);
894 cas_phy_write(cp, MII_BMCR, 0x00f1);
895 cas_phy_write(cp, LUCENT_MII_REG, 0x0);
897 } else if (PHY_BROADCOM_B0 == (cp->phy_id & 0xFFFFFFFC)) {
898 /* workarounds for broadcom phy */
899 cas_phy_write(cp, BROADCOM_MII_REG8, 0x0C20);
900 cas_phy_write(cp, BROADCOM_MII_REG7, 0x0012);
901 cas_phy_write(cp, BROADCOM_MII_REG5, 0x1804);
902 cas_phy_write(cp, BROADCOM_MII_REG7, 0x0013);
903 cas_phy_write(cp, BROADCOM_MII_REG5, 0x1204);
904 cas_phy_write(cp, BROADCOM_MII_REG7, 0x8006);
905 cas_phy_write(cp, BROADCOM_MII_REG5, 0x0132);
906 cas_phy_write(cp, BROADCOM_MII_REG7, 0x8006);
907 cas_phy_write(cp, BROADCOM_MII_REG5, 0x0232);
908 cas_phy_write(cp, BROADCOM_MII_REG7, 0x201F);
909 cas_phy_write(cp, BROADCOM_MII_REG5, 0x0A20);
911 } else if (PHY_BROADCOM_5411 == cp->phy_id) {
912 val = cas_phy_read(cp, BROADCOM_MII_REG4);
913 val = cas_phy_read(cp, BROADCOM_MII_REG4);
915 /* link workaround */
916 cas_phy_write(cp, BROADCOM_MII_REG4,
920 } else if (cp->cas_flags & CAS_FLAG_SATURN) {
921 writel((cp->phy_type & CAS_PHY_MII_MDIO0) ?
922 SATURN_PCFG_FSI : 0x0,
923 cp->regs + REG_SATURN_PCFG);
925 /* load firmware to address 10Mbps auto-negotiation
926 * issue. NOTE: this will need to be changed if the
927 * default firmware gets fixed.
929 if (PHY_NS_DP83065 == cp->phy_id) {
930 cas_saturn_firmware_load(cp);
935 /* advertise capabilities */
936 val = cas_phy_read(cp, MII_BMCR);
937 val &= ~BMCR_ANENABLE;
938 cas_phy_write(cp, MII_BMCR, val);
941 cas_phy_write(cp, MII_ADVERTISE,
942 cas_phy_read(cp, MII_ADVERTISE) |
943 (ADVERTISE_10HALF | ADVERTISE_10FULL |
944 ADVERTISE_100HALF | ADVERTISE_100FULL |
945 CAS_ADVERTISE_PAUSE |
946 CAS_ADVERTISE_ASYM_PAUSE));
948 if (cp->cas_flags & CAS_FLAG_1000MB_CAP) {
949 /* make sure that we don't advertise half
950 * duplex to avoid a chip issue
952 val = cas_phy_read(cp, CAS_MII_1000_CTRL);
953 val &= ~CAS_ADVERTISE_1000HALF;
954 val |= CAS_ADVERTISE_1000FULL;
955 cas_phy_write(cp, CAS_MII_1000_CTRL, val);
959 /* reset pcs for serdes */
963 writel(PCS_DATAPATH_MODE_SERDES,
964 cp->regs + REG_PCS_DATAPATH_MODE);
966 /* enable serdes pins on saturn */
967 if (cp->cas_flags & CAS_FLAG_SATURN)
968 writel(0, cp->regs + REG_SATURN_PCFG);
970 /* Reset PCS unit. */
971 val = readl(cp->regs + REG_PCS_MII_CTRL);
972 val |= PCS_MII_RESET;
973 writel(val, cp->regs + REG_PCS_MII_CTRL);
976 while (--limit > 0) {
978 if ((readl(cp->regs + REG_PCS_MII_CTRL) &
983 netdev_warn(cp->dev, "PCS reset bit would not clear [%08x]\n",
984 readl(cp->regs + REG_PCS_STATE_MACHINE));
986 /* Make sure PCS is disabled while changing advertisement
989 writel(0x0, cp->regs + REG_PCS_CFG);
991 /* Advertise all capabilities except half-duplex. */
992 val = readl(cp->regs + REG_PCS_MII_ADVERT);
993 val &= ~PCS_MII_ADVERT_HD;
994 val |= (PCS_MII_ADVERT_FD | PCS_MII_ADVERT_SYM_PAUSE |
995 PCS_MII_ADVERT_ASYM_PAUSE);
996 writel(val, cp->regs + REG_PCS_MII_ADVERT);
999 writel(PCS_CFG_EN, cp->regs + REG_PCS_CFG);
1001 /* pcs workaround: enable sync detect */
1002 writel(PCS_SERDES_CTRL_SYNCD_EN,
1003 cp->regs + REG_PCS_SERDES_CTRL);
1008 static int cas_pcs_link_check(struct cas *cp)
1010 u32 stat, state_machine;
1013 /* The link status bit latches on zero, so you must
1014 * read it twice in such a case to see a transition
1015 * to the link being up.
1017 stat = readl(cp->regs + REG_PCS_MII_STATUS);
1018 if ((stat & PCS_MII_STATUS_LINK_STATUS) == 0)
1019 stat = readl(cp->regs + REG_PCS_MII_STATUS);
1021 /* The remote-fault indication is only valid
1022 * when autoneg has completed.
1024 if ((stat & (PCS_MII_STATUS_AUTONEG_COMP |
1025 PCS_MII_STATUS_REMOTE_FAULT)) ==
1026 (PCS_MII_STATUS_AUTONEG_COMP | PCS_MII_STATUS_REMOTE_FAULT))
1027 netif_info(cp, link, cp->dev, "PCS RemoteFault\n");
1029 /* work around link detection issue by querying the PCS state
1032 state_machine = readl(cp->regs + REG_PCS_STATE_MACHINE);
1033 if ((state_machine & PCS_SM_LINK_STATE_MASK) != SM_LINK_STATE_UP) {
1034 stat &= ~PCS_MII_STATUS_LINK_STATUS;
1035 } else if (state_machine & PCS_SM_WORD_SYNC_STATE_MASK) {
1036 stat |= PCS_MII_STATUS_LINK_STATUS;
1039 if (stat & PCS_MII_STATUS_LINK_STATUS) {
1040 if (cp->lstate != link_up) {
1042 cp->lstate = link_up;
1043 cp->link_transition = LINK_TRANSITION_LINK_UP;
1045 cas_set_link_modes(cp);
1046 netif_carrier_on(cp->dev);
1049 } else if (cp->lstate == link_up) {
1050 cp->lstate = link_down;
1051 if (link_transition_timeout != 0 &&
1052 cp->link_transition != LINK_TRANSITION_REQUESTED_RESET &&
1053 !cp->link_transition_jiffies_valid) {
1055 * force a reset, as a workaround for the
1056 * link-failure problem. May want to move this to a
1057 * point a bit earlier in the sequence. If we had
1058 * generated a reset a short time ago, we'll wait for
1059 * the link timer to check the status until a
1060 * timer expires (link_transistion_jiffies_valid is
1061 * true when the timer is running.) Instead of using
1062 * a system timer, we just do a check whenever the
1063 * link timer is running - this clears the flag after
1067 cp->link_transition = LINK_TRANSITION_REQUESTED_RESET;
1068 cp->link_transition_jiffies = jiffies;
1069 cp->link_transition_jiffies_valid = 1;
1071 cp->link_transition = LINK_TRANSITION_ON_FAILURE;
1073 netif_carrier_off(cp->dev);
1075 netif_info(cp, link, cp->dev, "PCS link down\n");
1077 /* Cassini only: if you force a mode, there can be
1078 * sync problems on link down. to fix that, the following
1079 * things need to be checked:
1080 * 1) read serialink state register
1081 * 2) read pcs status register to verify link down.
1082 * 3) if link down and serial link == 0x03, then you need
1083 * to global reset the chip.
1085 if ((cp->cas_flags & CAS_FLAG_REG_PLUS) == 0) {
1086 /* should check to see if we're in a forced mode */
1087 stat = readl(cp->regs + REG_PCS_SERDES_STATE);
1091 } else if (cp->lstate == link_down) {
1092 if (link_transition_timeout != 0 &&
1093 cp->link_transition != LINK_TRANSITION_REQUESTED_RESET &&
1094 !cp->link_transition_jiffies_valid) {
1095 /* force a reset, as a workaround for the
1096 * link-failure problem. May want to move
1097 * this to a point a bit earlier in the
1101 cp->link_transition = LINK_TRANSITION_REQUESTED_RESET;
1102 cp->link_transition_jiffies = jiffies;
1103 cp->link_transition_jiffies_valid = 1;
1105 cp->link_transition = LINK_TRANSITION_STILL_FAILED;
1112 static int cas_pcs_interrupt(struct net_device *dev,
1113 struct cas *cp, u32 status)
1115 u32 stat = readl(cp->regs + REG_PCS_INTR_STATUS);
1117 if ((stat & PCS_INTR_STATUS_LINK_CHANGE) == 0)
1119 return cas_pcs_link_check(cp);
1122 static int cas_txmac_interrupt(struct net_device *dev,
1123 struct cas *cp, u32 status)
1125 u32 txmac_stat = readl(cp->regs + REG_MAC_TX_STATUS);
1130 netif_printk(cp, intr, KERN_DEBUG, cp->dev,
1131 "txmac interrupt, txmac_stat: 0x%x\n", txmac_stat);
1133 /* Defer timer expiration is quite normal,
1134 * don't even log the event.
1136 if ((txmac_stat & MAC_TX_DEFER_TIMER) &&
1137 !(txmac_stat & ~MAC_TX_DEFER_TIMER))
1140 spin_lock(&cp->stat_lock[0]);
1141 if (txmac_stat & MAC_TX_UNDERRUN) {
1142 netdev_err(dev, "TX MAC xmit underrun\n");
1143 cp->net_stats[0].tx_fifo_errors++;
1146 if (txmac_stat & MAC_TX_MAX_PACKET_ERR) {
1147 netdev_err(dev, "TX MAC max packet size error\n");
1148 cp->net_stats[0].tx_errors++;
1151 /* The rest are all cases of one of the 16-bit TX
1152 * counters expiring.
1154 if (txmac_stat & MAC_TX_COLL_NORMAL)
1155 cp->net_stats[0].collisions += 0x10000;
1157 if (txmac_stat & MAC_TX_COLL_EXCESS) {
1158 cp->net_stats[0].tx_aborted_errors += 0x10000;
1159 cp->net_stats[0].collisions += 0x10000;
1162 if (txmac_stat & MAC_TX_COLL_LATE) {
1163 cp->net_stats[0].tx_aborted_errors += 0x10000;
1164 cp->net_stats[0].collisions += 0x10000;
1166 spin_unlock(&cp->stat_lock[0]);
1168 /* We do not keep track of MAC_TX_COLL_FIRST and
1169 * MAC_TX_PEAK_ATTEMPTS events.
1174 static void cas_load_firmware(struct cas *cp, cas_hp_inst_t *firmware)
1176 cas_hp_inst_t *inst;
1181 while ((inst = firmware) && inst->note) {
1182 writel(i, cp->regs + REG_HP_INSTR_RAM_ADDR);
1184 val = CAS_BASE(HP_INSTR_RAM_HI_VAL, inst->val);
1185 val |= CAS_BASE(HP_INSTR_RAM_HI_MASK, inst->mask);
1186 writel(val, cp->regs + REG_HP_INSTR_RAM_DATA_HI);
1188 val = CAS_BASE(HP_INSTR_RAM_MID_OUTARG, inst->outarg >> 10);
1189 val |= CAS_BASE(HP_INSTR_RAM_MID_OUTOP, inst->outop);
1190 val |= CAS_BASE(HP_INSTR_RAM_MID_FNEXT, inst->fnext);
1191 val |= CAS_BASE(HP_INSTR_RAM_MID_FOFF, inst->foff);
1192 val |= CAS_BASE(HP_INSTR_RAM_MID_SNEXT, inst->snext);
1193 val |= CAS_BASE(HP_INSTR_RAM_MID_SOFF, inst->soff);
1194 val |= CAS_BASE(HP_INSTR_RAM_MID_OP, inst->op);
1195 writel(val, cp->regs + REG_HP_INSTR_RAM_DATA_MID);
1197 val = CAS_BASE(HP_INSTR_RAM_LOW_OUTMASK, inst->outmask);
1198 val |= CAS_BASE(HP_INSTR_RAM_LOW_OUTSHIFT, inst->outshift);
1199 val |= CAS_BASE(HP_INSTR_RAM_LOW_OUTEN, inst->outenab);
1200 val |= CAS_BASE(HP_INSTR_RAM_LOW_OUTARG, inst->outarg);
1201 writel(val, cp->regs + REG_HP_INSTR_RAM_DATA_LOW);
1207 static void cas_init_rx_dma(struct cas *cp)
1209 u64 desc_dma = cp->block_dvma;
1213 /* rx free descriptors */
1214 val = CAS_BASE(RX_CFG_SWIVEL, RX_SWIVEL_OFF_VAL);
1215 val |= CAS_BASE(RX_CFG_DESC_RING, RX_DESC_RINGN_INDEX(0));
1216 val |= CAS_BASE(RX_CFG_COMP_RING, RX_COMP_RINGN_INDEX(0));
1217 if ((N_RX_DESC_RINGS > 1) &&
1218 (cp->cas_flags & CAS_FLAG_REG_PLUS)) /* do desc 2 */
1219 val |= CAS_BASE(RX_CFG_DESC_RING1, RX_DESC_RINGN_INDEX(1));
1220 writel(val, cp->regs + REG_RX_CFG);
1222 val = (unsigned long) cp->init_rxds[0] -
1223 (unsigned long) cp->init_block;
1224 writel((desc_dma + val) >> 32, cp->regs + REG_RX_DB_HI);
1225 writel((desc_dma + val) & 0xffffffff, cp->regs + REG_RX_DB_LOW);
1226 writel(RX_DESC_RINGN_SIZE(0) - 4, cp->regs + REG_RX_KICK);
1228 if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
1229 /* rx desc 2 is for IPSEC packets. however,
1230 * we don't it that for that purpose.
1232 val = (unsigned long) cp->init_rxds[1] -
1233 (unsigned long) cp->init_block;
1234 writel((desc_dma + val) >> 32, cp->regs + REG_PLUS_RX_DB1_HI);
1235 writel((desc_dma + val) & 0xffffffff, cp->regs +
1236 REG_PLUS_RX_DB1_LOW);
1237 writel(RX_DESC_RINGN_SIZE(1) - 4, cp->regs +
1241 /* rx completion registers */
1242 val = (unsigned long) cp->init_rxcs[0] -
1243 (unsigned long) cp->init_block;
1244 writel((desc_dma + val) >> 32, cp->regs + REG_RX_CB_HI);
1245 writel((desc_dma + val) & 0xffffffff, cp->regs + REG_RX_CB_LOW);
1247 if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
1249 for (i = 1; i < MAX_RX_COMP_RINGS; i++) {
1250 val = (unsigned long) cp->init_rxcs[i] -
1251 (unsigned long) cp->init_block;
1252 writel((desc_dma + val) >> 32, cp->regs +
1253 REG_PLUS_RX_CBN_HI(i));
1254 writel((desc_dma + val) & 0xffffffff, cp->regs +
1255 REG_PLUS_RX_CBN_LOW(i));
1259 /* read selective clear regs to prevent spurious interrupts
1260 * on reset because complete == kick.
1261 * selective clear set up to prevent interrupts on resets
1263 readl(cp->regs + REG_INTR_STATUS_ALIAS);
1264 writel(INTR_RX_DONE | INTR_RX_BUF_UNAVAIL, cp->regs + REG_ALIAS_CLEAR);
1265 if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
1266 for (i = 1; i < N_RX_COMP_RINGS; i++)
1267 readl(cp->regs + REG_PLUS_INTRN_STATUS_ALIAS(i));
1269 /* 2 is different from 3 and 4 */
1270 if (N_RX_COMP_RINGS > 1)
1271 writel(INTR_RX_DONE_ALT | INTR_RX_BUF_UNAVAIL_1,
1272 cp->regs + REG_PLUS_ALIASN_CLEAR(1));
1274 for (i = 2; i < N_RX_COMP_RINGS; i++)
1275 writel(INTR_RX_DONE_ALT,
1276 cp->regs + REG_PLUS_ALIASN_CLEAR(i));
1279 /* set up pause thresholds */
1280 val = CAS_BASE(RX_PAUSE_THRESH_OFF,
1281 cp->rx_pause_off / RX_PAUSE_THRESH_QUANTUM);
1282 val |= CAS_BASE(RX_PAUSE_THRESH_ON,
1283 cp->rx_pause_on / RX_PAUSE_THRESH_QUANTUM);
1284 writel(val, cp->regs + REG_RX_PAUSE_THRESH);
1286 /* zero out dma reassembly buffers */
1287 for (i = 0; i < 64; i++) {
1288 writel(i, cp->regs + REG_RX_TABLE_ADDR);
1289 writel(0x0, cp->regs + REG_RX_TABLE_DATA_LOW);
1290 writel(0x0, cp->regs + REG_RX_TABLE_DATA_MID);
1291 writel(0x0, cp->regs + REG_RX_TABLE_DATA_HI);
1294 /* make sure address register is 0 for normal operation */
1295 writel(0x0, cp->regs + REG_RX_CTRL_FIFO_ADDR);
1296 writel(0x0, cp->regs + REG_RX_IPP_FIFO_ADDR);
1298 /* interrupt mitigation */
1300 val = CAS_BASE(RX_BLANK_INTR_TIME, RX_BLANK_INTR_TIME_VAL);
1301 val |= CAS_BASE(RX_BLANK_INTR_PKT, RX_BLANK_INTR_PKT_VAL);
1302 writel(val, cp->regs + REG_RX_BLANK);
1304 writel(0x0, cp->regs + REG_RX_BLANK);
1307 /* interrupt generation as a function of low water marks for
1308 * free desc and completion entries. these are used to trigger
1309 * housekeeping for rx descs. we don't use the free interrupt
1310 * as it's not very useful
1312 /* val = CAS_BASE(RX_AE_THRESH_FREE, RX_AE_FREEN_VAL(0)); */
1313 val = CAS_BASE(RX_AE_THRESH_COMP, RX_AE_COMP_VAL);
1314 writel(val, cp->regs + REG_RX_AE_THRESH);
1315 if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
1316 val = CAS_BASE(RX_AE1_THRESH_FREE, RX_AE_FREEN_VAL(1));
1317 writel(val, cp->regs + REG_PLUS_RX_AE1_THRESH);
1320 /* Random early detect registers. useful for congestion avoidance.
1321 * this should be tunable.
1323 writel(0x0, cp->regs + REG_RX_RED);
1325 /* receive page sizes. default == 2K (0x800) */
1327 if (cp->page_size == 0x1000)
1329 else if (cp->page_size == 0x2000)
1331 else if (cp->page_size == 0x4000)
1334 /* round mtu + offset. constrain to page size. */
1335 size = cp->dev->mtu + 64;
1336 if (size > cp->page_size)
1337 size = cp->page_size;
1341 else if (size <= 0x800)
1343 else if (size <= 0x1000)
1348 cp->mtu_stride = 1 << (i + 10);
1349 val = CAS_BASE(RX_PAGE_SIZE, val);
1350 val |= CAS_BASE(RX_PAGE_SIZE_MTU_STRIDE, i);
1351 val |= CAS_BASE(RX_PAGE_SIZE_MTU_COUNT, cp->page_size >> (i + 10));
1352 val |= CAS_BASE(RX_PAGE_SIZE_MTU_OFF, 0x1);
1353 writel(val, cp->regs + REG_RX_PAGE_SIZE);
1355 /* enable the header parser if desired */
1356 if (CAS_HP_FIRMWARE == cas_prog_null)
1359 val = CAS_BASE(HP_CFG_NUM_CPU, CAS_NCPUS > 63 ? 0 : CAS_NCPUS);
1360 val |= HP_CFG_PARSE_EN | HP_CFG_SYN_INC_MASK;
1361 val |= CAS_BASE(HP_CFG_TCP_THRESH, HP_TCP_THRESH_VAL);
1362 writel(val, cp->regs + REG_HP_CFG);
1365 static inline void cas_rxc_init(struct cas_rx_comp *rxc)
1367 memset(rxc, 0, sizeof(*rxc));
1368 rxc->word4 = cpu_to_le64(RX_COMP4_ZERO);
1371 /* NOTE: we use the ENC RX DESC ring for spares. the rx_page[0,1]
1372 * flipping is protected by the fact that the chip will not
1373 * hand back the same page index while it's being processed.
1375 static inline cas_page_t *cas_page_spare(struct cas *cp, const int index)
1377 cas_page_t *page = cp->rx_pages[1][index];
1380 if (page_count(page->buffer) == 1)
1383 new = cas_page_dequeue(cp);
1385 spin_lock(&cp->rx_inuse_lock);
1386 list_add(&page->list, &cp->rx_inuse_list);
1387 spin_unlock(&cp->rx_inuse_lock);
1392 /* this needs to be changed if we actually use the ENC RX DESC ring */
1393 static cas_page_t *cas_page_swap(struct cas *cp, const int ring,
1396 cas_page_t **page0 = cp->rx_pages[0];
1397 cas_page_t **page1 = cp->rx_pages[1];
1399 /* swap if buffer is in use */
1400 if (page_count(page0[index]->buffer) > 1) {
1401 cas_page_t *new = cas_page_spare(cp, index);
1403 page1[index] = page0[index];
1407 RX_USED_SET(page0[index], 0);
1408 return page0[index];
1411 static void cas_clean_rxds(struct cas *cp)
1413 /* only clean ring 0 as ring 1 is used for spare buffers */
1414 struct cas_rx_desc *rxd = cp->init_rxds[0];
1417 /* release all rx flows */
1418 for (i = 0; i < N_RX_FLOWS; i++) {
1419 struct sk_buff *skb;
1420 while ((skb = __skb_dequeue(&cp->rx_flows[i]))) {
1421 cas_skb_release(skb);
1425 /* initialize descriptors */
1426 size = RX_DESC_RINGN_SIZE(0);
1427 for (i = 0; i < size; i++) {
1428 cas_page_t *page = cas_page_swap(cp, 0, i);
1429 rxd[i].buffer = cpu_to_le64(page->dma_addr);
1430 rxd[i].index = cpu_to_le64(CAS_BASE(RX_INDEX_NUM, i) |
1431 CAS_BASE(RX_INDEX_RING, 0));
1434 cp->rx_old[0] = RX_DESC_RINGN_SIZE(0) - 4;
1436 cp->cas_flags &= ~CAS_FLAG_RXD_POST(0);
1439 static void cas_clean_rxcs(struct cas *cp)
1443 /* take ownership of rx comp descriptors */
1444 memset(cp->rx_cur, 0, sizeof(*cp->rx_cur)*N_RX_COMP_RINGS);
1445 memset(cp->rx_new, 0, sizeof(*cp->rx_new)*N_RX_COMP_RINGS);
1446 for (i = 0; i < N_RX_COMP_RINGS; i++) {
1447 struct cas_rx_comp *rxc = cp->init_rxcs[i];
1448 for (j = 0; j < RX_COMP_RINGN_SIZE(i); j++) {
1449 cas_rxc_init(rxc + j);
1455 /* When we get a RX fifo overflow, the RX unit is probably hung
1456 * so we do the following.
1458 * If any part of the reset goes wrong, we return 1 and that causes the
1459 * whole chip to be reset.
1461 static int cas_rxmac_reset(struct cas *cp)
1463 struct net_device *dev = cp->dev;
1467 /* First, reset MAC RX. */
1468 writel(cp->mac_rx_cfg & ~MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG);
1469 for (limit = 0; limit < STOP_TRIES; limit++) {
1470 if (!(readl(cp->regs + REG_MAC_RX_CFG) & MAC_RX_CFG_EN))
1474 if (limit == STOP_TRIES) {
1475 netdev_err(dev, "RX MAC will not disable, resetting whole chip\n");
1479 /* Second, disable RX DMA. */
1480 writel(0, cp->regs + REG_RX_CFG);
1481 for (limit = 0; limit < STOP_TRIES; limit++) {
1482 if (!(readl(cp->regs + REG_RX_CFG) & RX_CFG_DMA_EN))
1486 if (limit == STOP_TRIES) {
1487 netdev_err(dev, "RX DMA will not disable, resetting whole chip\n");
1493 /* Execute RX reset command. */
1494 writel(SW_RESET_RX, cp->regs + REG_SW_RESET);
1495 for (limit = 0; limit < STOP_TRIES; limit++) {
1496 if (!(readl(cp->regs + REG_SW_RESET) & SW_RESET_RX))
1500 if (limit == STOP_TRIES) {
1501 netdev_err(dev, "RX reset command will not execute, resetting whole chip\n");
1505 /* reset driver rx state */
1509 /* Now, reprogram the rest of RX unit. */
1510 cas_init_rx_dma(cp);
1513 val = readl(cp->regs + REG_RX_CFG);
1514 writel(val | RX_CFG_DMA_EN, cp->regs + REG_RX_CFG);
1515 writel(MAC_RX_FRAME_RECV, cp->regs + REG_MAC_RX_MASK);
1516 val = readl(cp->regs + REG_MAC_RX_CFG);
1517 writel(val | MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG);
1522 static int cas_rxmac_interrupt(struct net_device *dev, struct cas *cp,
1525 u32 stat = readl(cp->regs + REG_MAC_RX_STATUS);
1530 netif_dbg(cp, intr, cp->dev, "rxmac interrupt, stat: 0x%x\n", stat);
1532 /* these are all rollovers */
1533 spin_lock(&cp->stat_lock[0]);
1534 if (stat & MAC_RX_ALIGN_ERR)
1535 cp->net_stats[0].rx_frame_errors += 0x10000;
1537 if (stat & MAC_RX_CRC_ERR)
1538 cp->net_stats[0].rx_crc_errors += 0x10000;
1540 if (stat & MAC_RX_LEN_ERR)
1541 cp->net_stats[0].rx_length_errors += 0x10000;
1543 if (stat & MAC_RX_OVERFLOW) {
1544 cp->net_stats[0].rx_over_errors++;
1545 cp->net_stats[0].rx_fifo_errors++;
1548 /* We do not track MAC_RX_FRAME_COUNT and MAC_RX_VIOL_ERR
1551 spin_unlock(&cp->stat_lock[0]);
1555 static int cas_mac_interrupt(struct net_device *dev, struct cas *cp,
1558 u32 stat = readl(cp->regs + REG_MAC_CTRL_STATUS);
1563 netif_printk(cp, intr, KERN_DEBUG, cp->dev,
1564 "mac interrupt, stat: 0x%x\n", stat);
1566 /* This interrupt is just for pause frame and pause
1567 * tracking. It is useful for diagnostics and debug
1568 * but probably by default we will mask these events.
1570 if (stat & MAC_CTRL_PAUSE_STATE)
1571 cp->pause_entered++;
1573 if (stat & MAC_CTRL_PAUSE_RECEIVED)
1574 cp->pause_last_time_recvd = (stat >> 16);
1580 /* Must be invoked under cp->lock. */
1581 static inline int cas_mdio_link_not_up(struct cas *cp)
1585 switch (cp->lstate) {
1586 case link_force_ret:
1587 netif_info(cp, link, cp->dev, "Autoneg failed again, keeping forced mode\n");
1588 cas_phy_write(cp, MII_BMCR, cp->link_fcntl);
1589 cp->timer_ticks = 5;
1590 cp->lstate = link_force_ok;
1591 cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
1595 val = cas_phy_read(cp, MII_BMCR);
1597 /* Try forced modes. we try things in the following order:
1598 * 1000 full -> 100 full/half -> 10 half
1600 val &= ~(BMCR_ANRESTART | BMCR_ANENABLE);
1601 val |= BMCR_FULLDPLX;
1602 val |= (cp->cas_flags & CAS_FLAG_1000MB_CAP) ?
1603 CAS_BMCR_SPEED1000 : BMCR_SPEED100;
1604 cas_phy_write(cp, MII_BMCR, val);
1605 cp->timer_ticks = 5;
1606 cp->lstate = link_force_try;
1607 cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
1610 case link_force_try:
1611 /* Downgrade from 1000 to 100 to 10 Mbps if necessary. */
1612 val = cas_phy_read(cp, MII_BMCR);
1613 cp->timer_ticks = 5;
1614 if (val & CAS_BMCR_SPEED1000) { /* gigabit */
1615 val &= ~CAS_BMCR_SPEED1000;
1616 val |= (BMCR_SPEED100 | BMCR_FULLDPLX);
1617 cas_phy_write(cp, MII_BMCR, val);
1621 if (val & BMCR_SPEED100) {
1622 if (val & BMCR_FULLDPLX) /* fd failed */
1623 val &= ~BMCR_FULLDPLX;
1624 else { /* 100Mbps failed */
1625 val &= ~BMCR_SPEED100;
1627 cas_phy_write(cp, MII_BMCR, val);
1637 /* must be invoked with cp->lock held */
1638 static int cas_mii_link_check(struct cas *cp, const u16 bmsr)
1642 if (bmsr & BMSR_LSTATUS) {
1643 /* Ok, here we got a link. If we had it due to a forced
1644 * fallback, and we were configured for autoneg, we
1645 * retry a short autoneg pass. If you know your hub is
1646 * broken, use ethtool ;)
1648 if ((cp->lstate == link_force_try) &&
1649 (cp->link_cntl & BMCR_ANENABLE)) {
1650 cp->lstate = link_force_ret;
1651 cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
1652 cas_mif_poll(cp, 0);
1653 cp->link_fcntl = cas_phy_read(cp, MII_BMCR);
1654 cp->timer_ticks = 5;
1656 netif_info(cp, link, cp->dev,
1657 "Got link after fallback, retrying autoneg once...\n");
1658 cas_phy_write(cp, MII_BMCR,
1659 cp->link_fcntl | BMCR_ANENABLE |
1661 cas_mif_poll(cp, 1);
1663 } else if (cp->lstate != link_up) {
1664 cp->lstate = link_up;
1665 cp->link_transition = LINK_TRANSITION_LINK_UP;
1668 cas_set_link_modes(cp);
1669 netif_carrier_on(cp->dev);
1675 /* link not up. if the link was previously up, we restart the
1679 if (cp->lstate == link_up) {
1680 cp->lstate = link_down;
1681 cp->link_transition = LINK_TRANSITION_LINK_DOWN;
1683 netif_carrier_off(cp->dev);
1685 netif_info(cp, link, cp->dev, "Link down\n");
1688 } else if (++cp->timer_ticks > 10)
1689 cas_mdio_link_not_up(cp);
1694 static int cas_mif_interrupt(struct net_device *dev, struct cas *cp,
1697 u32 stat = readl(cp->regs + REG_MIF_STATUS);
1700 /* check for a link change */
1701 if (CAS_VAL(MIF_STATUS_POLL_STATUS, stat) == 0)
1704 bmsr = CAS_VAL(MIF_STATUS_POLL_DATA, stat);
1705 return cas_mii_link_check(cp, bmsr);
1708 static int cas_pci_interrupt(struct net_device *dev, struct cas *cp,
1711 u32 stat = readl(cp->regs + REG_PCI_ERR_STATUS);
1716 netdev_err(dev, "PCI error [%04x:%04x]",
1717 stat, readl(cp->regs + REG_BIM_DIAG));
1719 /* cassini+ has this reserved */
1720 if ((stat & PCI_ERR_BADACK) &&
1721 ((cp->cas_flags & CAS_FLAG_REG_PLUS) == 0))
1722 pr_cont(" <No ACK64# during ABS64 cycle>");
1724 if (stat & PCI_ERR_DTRTO)
1725 pr_cont(" <Delayed transaction timeout>");
1726 if (stat & PCI_ERR_OTHER)
1727 pr_cont(" <other>");
1728 if (stat & PCI_ERR_BIM_DMA_WRITE)
1729 pr_cont(" <BIM DMA 0 write req>");
1730 if (stat & PCI_ERR_BIM_DMA_READ)
1731 pr_cont(" <BIM DMA 0 read req>");
1734 if (stat & PCI_ERR_OTHER) {
1737 /* Interrogate PCI config space for the
1740 pci_read_config_word(cp->pdev, PCI_STATUS, &cfg);
1741 netdev_err(dev, "Read PCI cfg space status [%04x]\n", cfg);
1742 if (cfg & PCI_STATUS_PARITY)
1743 netdev_err(dev, "PCI parity error detected\n");
1744 if (cfg & PCI_STATUS_SIG_TARGET_ABORT)
1745 netdev_err(dev, "PCI target abort\n");
1746 if (cfg & PCI_STATUS_REC_TARGET_ABORT)
1747 netdev_err(dev, "PCI master acks target abort\n");
1748 if (cfg & PCI_STATUS_REC_MASTER_ABORT)
1749 netdev_err(dev, "PCI master abort\n");
1750 if (cfg & PCI_STATUS_SIG_SYSTEM_ERROR)
1751 netdev_err(dev, "PCI system error SERR#\n");
1752 if (cfg & PCI_STATUS_DETECTED_PARITY)
1753 netdev_err(dev, "PCI parity error\n");
1755 /* Write the error bits back to clear them. */
1756 cfg &= (PCI_STATUS_PARITY |
1757 PCI_STATUS_SIG_TARGET_ABORT |
1758 PCI_STATUS_REC_TARGET_ABORT |
1759 PCI_STATUS_REC_MASTER_ABORT |
1760 PCI_STATUS_SIG_SYSTEM_ERROR |
1761 PCI_STATUS_DETECTED_PARITY);
1762 pci_write_config_word(cp->pdev, PCI_STATUS, cfg);
1765 /* For all PCI errors, we should reset the chip. */
1769 /* All non-normal interrupt conditions get serviced here.
1770 * Returns non-zero if we should just exit the interrupt
1771 * handler right now (ie. if we reset the card which invalidates
1772 * all of the other original irq status bits).
1774 static int cas_abnormal_irq(struct net_device *dev, struct cas *cp,
1777 if (status & INTR_RX_TAG_ERROR) {
1778 /* corrupt RX tag framing */
1779 netif_printk(cp, rx_err, KERN_DEBUG, cp->dev,
1780 "corrupt rx tag framing\n");
1781 spin_lock(&cp->stat_lock[0]);
1782 cp->net_stats[0].rx_errors++;
1783 spin_unlock(&cp->stat_lock[0]);
1787 if (status & INTR_RX_LEN_MISMATCH) {
1788 /* length mismatch. */
1789 netif_printk(cp, rx_err, KERN_DEBUG, cp->dev,
1790 "length mismatch for rx frame\n");
1791 spin_lock(&cp->stat_lock[0]);
1792 cp->net_stats[0].rx_errors++;
1793 spin_unlock(&cp->stat_lock[0]);
1797 if (status & INTR_PCS_STATUS) {
1798 if (cas_pcs_interrupt(dev, cp, status))
1802 if (status & INTR_TX_MAC_STATUS) {
1803 if (cas_txmac_interrupt(dev, cp, status))
1807 if (status & INTR_RX_MAC_STATUS) {
1808 if (cas_rxmac_interrupt(dev, cp, status))
1812 if (status & INTR_MAC_CTRL_STATUS) {
1813 if (cas_mac_interrupt(dev, cp, status))
1817 if (status & INTR_MIF_STATUS) {
1818 if (cas_mif_interrupt(dev, cp, status))
1822 if (status & INTR_PCI_ERROR_STATUS) {
1823 if (cas_pci_interrupt(dev, cp, status))
1830 atomic_inc(&cp->reset_task_pending);
1831 atomic_inc(&cp->reset_task_pending_all);
1832 netdev_err(dev, "reset called in cas_abnormal_irq [0x%x]\n", status);
1833 schedule_work(&cp->reset_task);
1835 atomic_set(&cp->reset_task_pending, CAS_RESET_ALL);
1836 netdev_err(dev, "reset called in cas_abnormal_irq\n");
1837 schedule_work(&cp->reset_task);
1842 /* NOTE: CAS_TABORT returns 1 or 2 so that it can be used when
1843 * determining whether to do a netif_stop/wakeup
1845 #define CAS_TABORT(x) (((x)->cas_flags & CAS_FLAG_TARGET_ABORT) ? 2 : 1)
1846 #define CAS_ROUND_PAGE(x) (((x) + PAGE_SIZE - 1) & PAGE_MASK)
1847 static inline int cas_calc_tabort(struct cas *cp, const unsigned long addr,
1850 unsigned long off = addr + len;
1852 if (CAS_TABORT(cp) == 1)
1854 if ((CAS_ROUND_PAGE(off) - off) > TX_TARGET_ABORT_LEN)
1856 return TX_TARGET_ABORT_LEN;
1859 static inline void cas_tx_ringN(struct cas *cp, int ring, int limit)
1861 struct cas_tx_desc *txds;
1862 struct sk_buff **skbs;
1863 struct net_device *dev = cp->dev;
1866 spin_lock(&cp->tx_lock[ring]);
1867 txds = cp->init_txds[ring];
1868 skbs = cp->tx_skbs[ring];
1869 entry = cp->tx_old[ring];
1871 count = TX_BUFF_COUNT(ring, entry, limit);
1872 while (entry != limit) {
1873 struct sk_buff *skb = skbs[entry];
1879 /* this should never occur */
1880 entry = TX_DESC_NEXT(ring, entry);
1884 /* however, we might get only a partial skb release. */
1885 count -= skb_shinfo(skb)->nr_frags +
1886 + cp->tx_tiny_use[ring][entry].nbufs + 1;
1890 netif_printk(cp, tx_done, KERN_DEBUG, cp->dev,
1891 "tx[%d] done, slot %d\n", ring, entry);
1894 cp->tx_tiny_use[ring][entry].nbufs = 0;
1896 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
1897 struct cas_tx_desc *txd = txds + entry;
1899 daddr = le64_to_cpu(txd->buffer);
1900 dlen = CAS_VAL(TX_DESC_BUFLEN,
1901 le64_to_cpu(txd->control));
1902 pci_unmap_page(cp->pdev, daddr, dlen,
1904 entry = TX_DESC_NEXT(ring, entry);
1906 /* tiny buffer may follow */
1907 if (cp->tx_tiny_use[ring][entry].used) {
1908 cp->tx_tiny_use[ring][entry].used = 0;
1909 entry = TX_DESC_NEXT(ring, entry);
1913 spin_lock(&cp->stat_lock[ring]);
1914 cp->net_stats[ring].tx_packets++;
1915 cp->net_stats[ring].tx_bytes += skb->len;
1916 spin_unlock(&cp->stat_lock[ring]);
1917 dev_kfree_skb_irq(skb);
1919 cp->tx_old[ring] = entry;
1921 /* this is wrong for multiple tx rings. the net device needs
1922 * multiple queues for this to do the right thing. we wait
1923 * for 2*packets to be available when using tiny buffers
1925 if (netif_queue_stopped(dev) &&
1926 (TX_BUFFS_AVAIL(cp, ring) > CAS_TABORT(cp)*(MAX_SKB_FRAGS + 1)))
1927 netif_wake_queue(dev);
1928 spin_unlock(&cp->tx_lock[ring]);
1931 static void cas_tx(struct net_device *dev, struct cas *cp,
1935 #ifdef USE_TX_COMPWB
1936 u64 compwb = le64_to_cpu(cp->init_block->tx_compwb);
1938 netif_printk(cp, intr, KERN_DEBUG, cp->dev,
1939 "tx interrupt, status: 0x%x, %llx\n",
1940 status, (unsigned long long)compwb);
1941 /* process all the rings */
1942 for (ring = 0; ring < N_TX_RINGS; ring++) {
1943 #ifdef USE_TX_COMPWB
1944 /* use the completion writeback registers */
1945 limit = (CAS_VAL(TX_COMPWB_MSB, compwb) << 8) |
1946 CAS_VAL(TX_COMPWB_LSB, compwb);
1947 compwb = TX_COMPWB_NEXT(compwb);
1949 limit = readl(cp->regs + REG_TX_COMPN(ring));
1951 if (cp->tx_old[ring] != limit)
1952 cas_tx_ringN(cp, ring, limit);
1957 static int cas_rx_process_pkt(struct cas *cp, struct cas_rx_comp *rxc,
1958 int entry, const u64 *words,
1959 struct sk_buff **skbref)
1961 int dlen, hlen, len, i, alloclen;
1962 int off, swivel = RX_SWIVEL_OFF_VAL;
1963 struct cas_page *page;
1964 struct sk_buff *skb;
1965 void *addr, *crcaddr;
1969 hlen = CAS_VAL(RX_COMP2_HDR_SIZE, words[1]);
1970 dlen = CAS_VAL(RX_COMP1_DATA_SIZE, words[0]);
1973 if (RX_COPY_ALWAYS || (words[2] & RX_COMP3_SMALL_PKT))
1976 alloclen = max(hlen, RX_COPY_MIN);
1978 skb = dev_alloc_skb(alloclen + swivel + cp->crc_size);
1983 skb_reserve(skb, swivel);
1986 addr = crcaddr = NULL;
1987 if (hlen) { /* always copy header pages */
1988 i = CAS_VAL(RX_COMP2_HDR_INDEX, words[1]);
1989 page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)];
1990 off = CAS_VAL(RX_COMP2_HDR_OFF, words[1]) * 0x100 +
1994 if (!dlen) /* attach FCS */
1996 pci_dma_sync_single_for_cpu(cp->pdev, page->dma_addr + off, i,
1997 PCI_DMA_FROMDEVICE);
1998 addr = cas_page_map(page->buffer);
1999 memcpy(p, addr + off, i);
2000 pci_dma_sync_single_for_device(cp->pdev, page->dma_addr + off, i,
2001 PCI_DMA_FROMDEVICE);
2002 cas_page_unmap(addr);
2003 RX_USED_ADD(page, 0x100);
2009 if (alloclen < (hlen + dlen)) {
2010 skb_frag_t *frag = skb_shinfo(skb)->frags;
2012 /* normal or jumbo packets. we use frags */
2013 i = CAS_VAL(RX_COMP1_DATA_INDEX, words[0]);
2014 page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)];
2015 off = CAS_VAL(RX_COMP1_DATA_OFF, words[0]) + swivel;
2017 hlen = min(cp->page_size - off, dlen);
2019 netif_printk(cp, rx_err, KERN_DEBUG, cp->dev,
2020 "rx page overflow: %d\n", hlen);
2021 dev_kfree_skb_irq(skb);
2025 if (i == dlen) /* attach FCS */
2027 pci_dma_sync_single_for_cpu(cp->pdev, page->dma_addr + off, i,
2028 PCI_DMA_FROMDEVICE);
2030 /* make sure we always copy a header */
2032 if (p == (char *) skb->data) { /* not split */
2033 addr = cas_page_map(page->buffer);
2034 memcpy(p, addr + off, RX_COPY_MIN);
2035 pci_dma_sync_single_for_device(cp->pdev, page->dma_addr + off, i,
2036 PCI_DMA_FROMDEVICE);
2037 cas_page_unmap(addr);
2039 swivel = RX_COPY_MIN;
2040 RX_USED_ADD(page, cp->mtu_stride);
2042 RX_USED_ADD(page, hlen);
2044 skb_put(skb, alloclen);
2046 skb_shinfo(skb)->nr_frags++;
2047 skb->data_len += hlen - swivel;
2048 skb->truesize += hlen - swivel;
2049 skb->len += hlen - swivel;
2051 __skb_frag_set_page(frag, page->buffer);
2052 __skb_frag_ref(frag);
2053 frag->page_offset = off;
2054 skb_frag_size_set(frag, hlen - swivel);
2056 /* any more data? */
2057 if ((words[0] & RX_COMP1_SPLIT_PKT) && ((dlen -= hlen) > 0)) {
2061 i = CAS_VAL(RX_COMP2_NEXT_INDEX, words[1]);
2062 page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)];
2063 pci_dma_sync_single_for_cpu(cp->pdev, page->dma_addr,
2064 hlen + cp->crc_size,
2065 PCI_DMA_FROMDEVICE);
2066 pci_dma_sync_single_for_device(cp->pdev, page->dma_addr,
2067 hlen + cp->crc_size,
2068 PCI_DMA_FROMDEVICE);
2070 skb_shinfo(skb)->nr_frags++;
2071 skb->data_len += hlen;
2075 __skb_frag_set_page(frag, page->buffer);
2076 __skb_frag_ref(frag);
2077 frag->page_offset = 0;
2078 skb_frag_size_set(frag, hlen);
2079 RX_USED_ADD(page, hlen + cp->crc_size);
2083 addr = cas_page_map(page->buffer);
2084 crcaddr = addr + off + hlen;
2088 /* copying packet */
2092 i = CAS_VAL(RX_COMP1_DATA_INDEX, words[0]);
2093 page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)];
2094 off = CAS_VAL(RX_COMP1_DATA_OFF, words[0]) + swivel;
2095 hlen = min(cp->page_size - off, dlen);
2097 netif_printk(cp, rx_err, KERN_DEBUG, cp->dev,
2098 "rx page overflow: %d\n", hlen);
2099 dev_kfree_skb_irq(skb);
2103 if (i == dlen) /* attach FCS */
2105 pci_dma_sync_single_for_cpu(cp->pdev, page->dma_addr + off, i,
2106 PCI_DMA_FROMDEVICE);
2107 addr = cas_page_map(page->buffer);
2108 memcpy(p, addr + off, i);
2109 pci_dma_sync_single_for_device(cp->pdev, page->dma_addr + off, i,
2110 PCI_DMA_FROMDEVICE);
2111 cas_page_unmap(addr);
2112 if (p == (char *) skb->data) /* not split */
2113 RX_USED_ADD(page, cp->mtu_stride);
2115 RX_USED_ADD(page, i);
2117 /* any more data? */
2118 if ((words[0] & RX_COMP1_SPLIT_PKT) && ((dlen -= hlen) > 0)) {
2120 i = CAS_VAL(RX_COMP2_NEXT_INDEX, words[1]);
2121 page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)];
2122 pci_dma_sync_single_for_cpu(cp->pdev, page->dma_addr,
2123 dlen + cp->crc_size,
2124 PCI_DMA_FROMDEVICE);
2125 addr = cas_page_map(page->buffer);
2126 memcpy(p, addr, dlen + cp->crc_size);
2127 pci_dma_sync_single_for_device(cp->pdev, page->dma_addr,
2128 dlen + cp->crc_size,
2129 PCI_DMA_FROMDEVICE);
2130 cas_page_unmap(addr);
2131 RX_USED_ADD(page, dlen + cp->crc_size);
2136 crcaddr = skb->data + alloclen;
2138 skb_put(skb, alloclen);
2141 csum = (__force __sum16)htons(CAS_VAL(RX_COMP4_TCP_CSUM, words[3]));
2143 /* checksum includes FCS. strip it out. */
2144 csum = csum_fold(csum_partial(crcaddr, cp->crc_size,
2145 csum_unfold(csum)));
2147 cas_page_unmap(addr);
2149 skb->protocol = eth_type_trans(skb, cp->dev);
2150 if (skb->protocol == htons(ETH_P_IP)) {
2151 skb->csum = csum_unfold(~csum);
2152 skb->ip_summed = CHECKSUM_COMPLETE;
2154 skb_checksum_none_assert(skb);
2159 /* we can handle up to 64 rx flows at a time. we do the same thing
2160 * as nonreassm except that we batch up the buffers.
2161 * NOTE: we currently just treat each flow as a bunch of packets that
2162 * we pass up. a better way would be to coalesce the packets
2163 * into a jumbo packet. to do that, we need to do the following:
2164 * 1) the first packet will have a clean split between header and
2166 * 2) each time the next flow packet comes in, extend the
2167 * data length and merge the checksums.
2168 * 3) on flow release, fix up the header.
2169 * 4) make sure the higher layer doesn't care.
2170 * because packets get coalesced, we shouldn't run into fragment count
2173 static inline void cas_rx_flow_pkt(struct cas *cp, const u64 *words,
2174 struct sk_buff *skb)
2176 int flowid = CAS_VAL(RX_COMP3_FLOWID, words[2]) & (N_RX_FLOWS - 1);
2177 struct sk_buff_head *flow = &cp->rx_flows[flowid];
2179 /* this is protected at a higher layer, so no need to
2180 * do any additional locking here. stick the buffer
2183 __skb_queue_tail(flow, skb);
2184 if (words[0] & RX_COMP1_RELEASE_FLOW) {
2185 while ((skb = __skb_dequeue(flow))) {
2186 cas_skb_release(skb);
2191 /* put rx descriptor back on ring. if a buffer is in use by a higher
2192 * layer, this will need to put in a replacement.
2194 static void cas_post_page(struct cas *cp, const int ring, const int index)
2199 entry = cp->rx_old[ring];
2201 new = cas_page_swap(cp, ring, index);
2202 cp->init_rxds[ring][entry].buffer = cpu_to_le64(new->dma_addr);
2203 cp->init_rxds[ring][entry].index =
2204 cpu_to_le64(CAS_BASE(RX_INDEX_NUM, index) |
2205 CAS_BASE(RX_INDEX_RING, ring));
2207 entry = RX_DESC_ENTRY(ring, entry + 1);
2208 cp->rx_old[ring] = entry;
2214 writel(entry, cp->regs + REG_RX_KICK);
2215 else if ((N_RX_DESC_RINGS > 1) &&
2216 (cp->cas_flags & CAS_FLAG_REG_PLUS))
2217 writel(entry, cp->regs + REG_PLUS_RX_KICK1);
2221 /* only when things are bad */
2222 static int cas_post_rxds_ringN(struct cas *cp, int ring, int num)
2224 unsigned int entry, last, count, released;
2226 cas_page_t **page = cp->rx_pages[ring];
2228 entry = cp->rx_old[ring];
2230 netif_printk(cp, intr, KERN_DEBUG, cp->dev,
2231 "rxd[%d] interrupt, done: %d\n", ring, entry);
2234 count = entry & 0x3;
2235 last = RX_DESC_ENTRY(ring, num ? entry + num - 4: entry - 4);
2237 while (entry != last) {
2238 /* make a new buffer if it's still in use */
2239 if (page_count(page[entry]->buffer) > 1) {
2240 cas_page_t *new = cas_page_dequeue(cp);
2242 /* let the timer know that we need to
2245 cp->cas_flags |= CAS_FLAG_RXD_POST(ring);
2246 if (!timer_pending(&cp->link_timer))
2247 mod_timer(&cp->link_timer, jiffies +
2248 CAS_LINK_FAST_TIMEOUT);
2249 cp->rx_old[ring] = entry;
2250 cp->rx_last[ring] = num ? num - released : 0;
2253 spin_lock(&cp->rx_inuse_lock);
2254 list_add(&page[entry]->list, &cp->rx_inuse_list);
2255 spin_unlock(&cp->rx_inuse_lock);
2256 cp->init_rxds[ring][entry].buffer =
2257 cpu_to_le64(new->dma_addr);
2267 entry = RX_DESC_ENTRY(ring, entry + 1);
2269 cp->rx_old[ring] = entry;
2275 writel(cluster, cp->regs + REG_RX_KICK);
2276 else if ((N_RX_DESC_RINGS > 1) &&
2277 (cp->cas_flags & CAS_FLAG_REG_PLUS))
2278 writel(cluster, cp->regs + REG_PLUS_RX_KICK1);
2283 /* process a completion ring. packets are set up in three basic ways:
2284 * small packets: should be copied header + data in single buffer.
2285 * large packets: header and data in a single buffer.
2286 * split packets: header in a separate buffer from data.
2287 * data may be in multiple pages. data may be > 256
2288 * bytes but in a single page.
2290 * NOTE: RX page posting is done in this routine as well. while there's
2291 * the capability of using multiple RX completion rings, it isn't
2292 * really worthwhile due to the fact that the page posting will
2293 * force serialization on the single descriptor ring.
2295 static int cas_rx_ringN(struct cas *cp, int ring, int budget)
2297 struct cas_rx_comp *rxcs = cp->init_rxcs[ring];
2301 netif_printk(cp, intr, KERN_DEBUG, cp->dev,
2302 "rx[%d] interrupt, done: %d/%d\n",
2304 readl(cp->regs + REG_RX_COMP_HEAD), cp->rx_new[ring]);
2306 entry = cp->rx_new[ring];
2309 struct cas_rx_comp *rxc = rxcs + entry;
2310 struct sk_buff *uninitialized_var(skb);
2315 words[0] = le64_to_cpu(rxc->word1);
2316 words[1] = le64_to_cpu(rxc->word2);
2317 words[2] = le64_to_cpu(rxc->word3);
2318 words[3] = le64_to_cpu(rxc->word4);
2320 /* don't touch if still owned by hw */
2321 type = CAS_VAL(RX_COMP1_TYPE, words[0]);
2325 /* hw hasn't cleared the zero bit yet */
2326 if (words[3] & RX_COMP4_ZERO) {
2330 /* get info on the packet */
2331 if (words[3] & (RX_COMP4_LEN_MISMATCH | RX_COMP4_BAD)) {
2332 spin_lock(&cp->stat_lock[ring]);
2333 cp->net_stats[ring].rx_errors++;
2334 if (words[3] & RX_COMP4_LEN_MISMATCH)
2335 cp->net_stats[ring].rx_length_errors++;
2336 if (words[3] & RX_COMP4_BAD)
2337 cp->net_stats[ring].rx_crc_errors++;
2338 spin_unlock(&cp->stat_lock[ring]);
2340 /* We'll just return it to Cassini. */
2342 spin_lock(&cp->stat_lock[ring]);
2343 ++cp->net_stats[ring].rx_dropped;
2344 spin_unlock(&cp->stat_lock[ring]);
2348 len = cas_rx_process_pkt(cp, rxc, entry, words, &skb);
2354 /* see if it's a flow re-assembly or not. the driver
2355 * itself handles release back up.
2357 if (RX_DONT_BATCH || (type == 0x2)) {
2358 /* non-reassm: these always get released */
2359 cas_skb_release(skb);
2361 cas_rx_flow_pkt(cp, words, skb);
2364 spin_lock(&cp->stat_lock[ring]);
2365 cp->net_stats[ring].rx_packets++;
2366 cp->net_stats[ring].rx_bytes += len;
2367 spin_unlock(&cp->stat_lock[ring]);
2372 /* should it be released? */
2373 if (words[0] & RX_COMP1_RELEASE_HDR) {
2374 i = CAS_VAL(RX_COMP2_HDR_INDEX, words[1]);
2375 dring = CAS_VAL(RX_INDEX_RING, i);
2376 i = CAS_VAL(RX_INDEX_NUM, i);
2377 cas_post_page(cp, dring, i);
2380 if (words[0] & RX_COMP1_RELEASE_DATA) {
2381 i = CAS_VAL(RX_COMP1_DATA_INDEX, words[0]);
2382 dring = CAS_VAL(RX_INDEX_RING, i);
2383 i = CAS_VAL(RX_INDEX_NUM, i);
2384 cas_post_page(cp, dring, i);
2387 if (words[0] & RX_COMP1_RELEASE_NEXT) {
2388 i = CAS_VAL(RX_COMP2_NEXT_INDEX, words[1]);
2389 dring = CAS_VAL(RX_INDEX_RING, i);
2390 i = CAS_VAL(RX_INDEX_NUM, i);
2391 cas_post_page(cp, dring, i);
2394 /* skip to the next entry */
2395 entry = RX_COMP_ENTRY(ring, entry + 1 +
2396 CAS_VAL(RX_COMP1_SKIP, words[0]));
2398 if (budget && (npackets >= budget))
2402 cp->rx_new[ring] = entry;
2405 netdev_info(cp->dev, "Memory squeeze, deferring packet\n");
2410 /* put completion entries back on the ring */
2411 static void cas_post_rxcs_ringN(struct net_device *dev,
2412 struct cas *cp, int ring)
2414 struct cas_rx_comp *rxc = cp->init_rxcs[ring];
2417 last = cp->rx_cur[ring];
2418 entry = cp->rx_new[ring];
2419 netif_printk(cp, intr, KERN_DEBUG, dev,
2420 "rxc[%d] interrupt, done: %d/%d\n",
2421 ring, readl(cp->regs + REG_RX_COMP_HEAD), entry);
2423 /* zero and re-mark descriptors */
2424 while (last != entry) {
2425 cas_rxc_init(rxc + last);
2426 last = RX_COMP_ENTRY(ring, last + 1);
2428 cp->rx_cur[ring] = last;
2431 writel(last, cp->regs + REG_RX_COMP_TAIL);
2432 else if (cp->cas_flags & CAS_FLAG_REG_PLUS)
2433 writel(last, cp->regs + REG_PLUS_RX_COMPN_TAIL(ring));
2438 /* cassini can use all four PCI interrupts for the completion ring.
2439 * rings 3 and 4 are identical
2441 #if defined(USE_PCI_INTC) || defined(USE_PCI_INTD)
2442 static inline void cas_handle_irqN(struct net_device *dev,
2443 struct cas *cp, const u32 status,
2446 if (status & (INTR_RX_COMP_FULL_ALT | INTR_RX_COMP_AF_ALT))
2447 cas_post_rxcs_ringN(dev, cp, ring);
2450 static irqreturn_t cas_interruptN(int irq, void *dev_id)
2452 struct net_device *dev = dev_id;
2453 struct cas *cp = netdev_priv(dev);
2454 unsigned long flags;
2455 int ring = (irq == cp->pci_irq_INTC) ? 2 : 3;
2456 u32 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(ring));
2458 /* check for shared irq */
2462 spin_lock_irqsave(&cp->lock, flags);
2463 if (status & INTR_RX_DONE_ALT) { /* handle rx separately */
2466 napi_schedule(&cp->napi);
2468 cas_rx_ringN(cp, ring, 0);
2470 status &= ~INTR_RX_DONE_ALT;
2474 cas_handle_irqN(dev, cp, status, ring);
2475 spin_unlock_irqrestore(&cp->lock, flags);
2481 /* everything but rx packets */
2482 static inline void cas_handle_irq1(struct cas *cp, const u32 status)
2484 if (status & INTR_RX_BUF_UNAVAIL_1) {
2485 /* Frame arrived, no free RX buffers available.
2486 * NOTE: we can get this on a link transition. */
2487 cas_post_rxds_ringN(cp, 1, 0);
2488 spin_lock(&cp->stat_lock[1]);
2489 cp->net_stats[1].rx_dropped++;
2490 spin_unlock(&cp->stat_lock[1]);
2493 if (status & INTR_RX_BUF_AE_1)
2494 cas_post_rxds_ringN(cp, 1, RX_DESC_RINGN_SIZE(1) -
2495 RX_AE_FREEN_VAL(1));
2497 if (status & (INTR_RX_COMP_AF | INTR_RX_COMP_FULL))
2498 cas_post_rxcs_ringN(cp, 1);
2501 /* ring 2 handles a few more events than 3 and 4 */
2502 static irqreturn_t cas_interrupt1(int irq, void *dev_id)
2504 struct net_device *dev = dev_id;
2505 struct cas *cp = netdev_priv(dev);
2506 unsigned long flags;
2507 u32 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(1));
2509 /* check for shared interrupt */
2513 spin_lock_irqsave(&cp->lock, flags);
2514 if (status & INTR_RX_DONE_ALT) { /* handle rx separately */
2517 napi_schedule(&cp->napi);
2519 cas_rx_ringN(cp, 1, 0);
2521 status &= ~INTR_RX_DONE_ALT;
2524 cas_handle_irq1(cp, status);
2525 spin_unlock_irqrestore(&cp->lock, flags);
2530 static inline void cas_handle_irq(struct net_device *dev,
2531 struct cas *cp, const u32 status)
2533 /* housekeeping interrupts */
2534 if (status & INTR_ERROR_MASK)
2535 cas_abnormal_irq(dev, cp, status);
2537 if (status & INTR_RX_BUF_UNAVAIL) {
2538 /* Frame arrived, no free RX buffers available.
2539 * NOTE: we can get this on a link transition.
2541 cas_post_rxds_ringN(cp, 0, 0);
2542 spin_lock(&cp->stat_lock[0]);
2543 cp->net_stats[0].rx_dropped++;
2544 spin_unlock(&cp->stat_lock[0]);
2545 } else if (status & INTR_RX_BUF_AE) {
2546 cas_post_rxds_ringN(cp, 0, RX_DESC_RINGN_SIZE(0) -
2547 RX_AE_FREEN_VAL(0));
2550 if (status & (INTR_RX_COMP_AF | INTR_RX_COMP_FULL))
2551 cas_post_rxcs_ringN(dev, cp, 0);
2554 static irqreturn_t cas_interrupt(int irq, void *dev_id)
2556 struct net_device *dev = dev_id;
2557 struct cas *cp = netdev_priv(dev);
2558 unsigned long flags;
2559 u32 status = readl(cp->regs + REG_INTR_STATUS);
2564 spin_lock_irqsave(&cp->lock, flags);
2565 if (status & (INTR_TX_ALL | INTR_TX_INTME)) {
2566 cas_tx(dev, cp, status);
2567 status &= ~(INTR_TX_ALL | INTR_TX_INTME);
2570 if (status & INTR_RX_DONE) {
2573 napi_schedule(&cp->napi);
2575 cas_rx_ringN(cp, 0, 0);
2577 status &= ~INTR_RX_DONE;
2581 cas_handle_irq(dev, cp, status);
2582 spin_unlock_irqrestore(&cp->lock, flags);
2588 static int cas_poll(struct napi_struct *napi, int budget)
2590 struct cas *cp = container_of(napi, struct cas, napi);
2591 struct net_device *dev = cp->dev;
2592 int i, enable_intr, credits;
2593 u32 status = readl(cp->regs + REG_INTR_STATUS);
2594 unsigned long flags;
2596 spin_lock_irqsave(&cp->lock, flags);
2597 cas_tx(dev, cp, status);
2598 spin_unlock_irqrestore(&cp->lock, flags);
2600 /* NAPI rx packets. we spread the credits across all of the
2603 * to make sure we're fair with the work we loop through each
2604 * ring N_RX_COMP_RING times with a request of
2605 * budget / N_RX_COMP_RINGS
2609 for (i = 0; i < N_RX_COMP_RINGS; i++) {
2611 for (j = 0; j < N_RX_COMP_RINGS; j++) {
2612 credits += cas_rx_ringN(cp, j, budget / N_RX_COMP_RINGS);
2613 if (credits >= budget) {
2621 /* final rx completion */
2622 spin_lock_irqsave(&cp->lock, flags);
2624 cas_handle_irq(dev, cp, status);
2627 if (N_RX_COMP_RINGS > 1) {
2628 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(1));
2630 cas_handle_irq1(dev, cp, status);
2635 if (N_RX_COMP_RINGS > 2) {
2636 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(2));
2638 cas_handle_irqN(dev, cp, status, 2);
2643 if (N_RX_COMP_RINGS > 3) {
2644 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(3));
2646 cas_handle_irqN(dev, cp, status, 3);
2649 spin_unlock_irqrestore(&cp->lock, flags);
2651 napi_complete(napi);
2652 cas_unmask_intr(cp);
2658 #ifdef CONFIG_NET_POLL_CONTROLLER
2659 static void cas_netpoll(struct net_device *dev)
2661 struct cas *cp = netdev_priv(dev);
2663 cas_disable_irq(cp, 0);
2664 cas_interrupt(cp->pdev->irq, dev);
2665 cas_enable_irq(cp, 0);
2668 if (N_RX_COMP_RINGS > 1) {
2669 /* cas_interrupt1(); */
2673 if (N_RX_COMP_RINGS > 2) {
2674 /* cas_interruptN(); */
2678 if (N_RX_COMP_RINGS > 3) {
2679 /* cas_interruptN(); */
2685 static void cas_tx_timeout(struct net_device *dev)
2687 struct cas *cp = netdev_priv(dev);
2689 netdev_err(dev, "transmit timed out, resetting\n");
2690 if (!cp->hw_running) {
2691 netdev_err(dev, "hrm.. hw not running!\n");
2695 netdev_err(dev, "MIF_STATE[%08x]\n",
2696 readl(cp->regs + REG_MIF_STATE_MACHINE));
2698 netdev_err(dev, "MAC_STATE[%08x]\n",
2699 readl(cp->regs + REG_MAC_STATE_MACHINE));
2701 netdev_err(dev, "TX_STATE[%08x:%08x:%08x] FIFO[%08x:%08x:%08x] SM1[%08x] SM2[%08x]\n",
2702 readl(cp->regs + REG_TX_CFG),
2703 readl(cp->regs + REG_MAC_TX_STATUS),
2704 readl(cp->regs + REG_MAC_TX_CFG),
2705 readl(cp->regs + REG_TX_FIFO_PKT_CNT),
2706 readl(cp->regs + REG_TX_FIFO_WRITE_PTR),
2707 readl(cp->regs + REG_TX_FIFO_READ_PTR),
2708 readl(cp->regs + REG_TX_SM_1),
2709 readl(cp->regs + REG_TX_SM_2));
2711 netdev_err(dev, "RX_STATE[%08x:%08x:%08x]\n",
2712 readl(cp->regs + REG_RX_CFG),
2713 readl(cp->regs + REG_MAC_RX_STATUS),
2714 readl(cp->regs + REG_MAC_RX_CFG));
2716 netdev_err(dev, "HP_STATE[%08x:%08x:%08x:%08x]\n",
2717 readl(cp->regs + REG_HP_STATE_MACHINE),
2718 readl(cp->regs + REG_HP_STATUS0),
2719 readl(cp->regs + REG_HP_STATUS1),
2720 readl(cp->regs + REG_HP_STATUS2));
2723 atomic_inc(&cp->reset_task_pending);
2724 atomic_inc(&cp->reset_task_pending_all);
2725 schedule_work(&cp->reset_task);
2727 atomic_set(&cp->reset_task_pending, CAS_RESET_ALL);
2728 schedule_work(&cp->reset_task);
2732 static inline int cas_intme(int ring, int entry)
2734 /* Algorithm: IRQ every 1/2 of descriptors. */
2735 if (!(entry & ((TX_DESC_RINGN_SIZE(ring) >> 1) - 1)))
2741 static void cas_write_txd(struct cas *cp, int ring, int entry,
2742 dma_addr_t mapping, int len, u64 ctrl, int last)
2744 struct cas_tx_desc *txd = cp->init_txds[ring] + entry;
2746 ctrl |= CAS_BASE(TX_DESC_BUFLEN, len);
2747 if (cas_intme(ring, entry))
2748 ctrl |= TX_DESC_INTME;
2750 ctrl |= TX_DESC_EOF;
2751 txd->control = cpu_to_le64(ctrl);
2752 txd->buffer = cpu_to_le64(mapping);
2755 static inline void *tx_tiny_buf(struct cas *cp, const int ring,
2758 return cp->tx_tiny_bufs[ring] + TX_TINY_BUF_LEN*entry;
2761 static inline dma_addr_t tx_tiny_map(struct cas *cp, const int ring,
2762 const int entry, const int tentry)
2764 cp->tx_tiny_use[ring][tentry].nbufs++;
2765 cp->tx_tiny_use[ring][entry].used = 1;
2766 return cp->tx_tiny_dvma[ring] + TX_TINY_BUF_LEN*entry;
2769 static inline int cas_xmit_tx_ringN(struct cas *cp, int ring,
2770 struct sk_buff *skb)
2772 struct net_device *dev = cp->dev;
2773 int entry, nr_frags, frag, tabort, tentry;
2775 unsigned long flags;
2779 spin_lock_irqsave(&cp->tx_lock[ring], flags);
2781 /* This is a hard error, log it. */
2782 if (TX_BUFFS_AVAIL(cp, ring) <=
2783 CAS_TABORT(cp)*(skb_shinfo(skb)->nr_frags + 1)) {
2784 netif_stop_queue(dev);
2785 spin_unlock_irqrestore(&cp->tx_lock[ring], flags);
2786 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n");
2791 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2792 const u64 csum_start_off = skb_checksum_start_offset(skb);
2793 const u64 csum_stuff_off = csum_start_off + skb->csum_offset;
2795 ctrl = TX_DESC_CSUM_EN |
2796 CAS_BASE(TX_DESC_CSUM_START, csum_start_off) |
2797 CAS_BASE(TX_DESC_CSUM_STUFF, csum_stuff_off);
2800 entry = cp->tx_new[ring];
2801 cp->tx_skbs[ring][entry] = skb;
2803 nr_frags = skb_shinfo(skb)->nr_frags;
2804 len = skb_headlen(skb);
2805 mapping = pci_map_page(cp->pdev, virt_to_page(skb->data),
2806 offset_in_page(skb->data), len,
2810 tabort = cas_calc_tabort(cp, (unsigned long) skb->data, len);
2811 if (unlikely(tabort)) {
2812 /* NOTE: len is always > tabort */
2813 cas_write_txd(cp, ring, entry, mapping, len - tabort,
2814 ctrl | TX_DESC_SOF, 0);
2815 entry = TX_DESC_NEXT(ring, entry);
2817 skb_copy_from_linear_data_offset(skb, len - tabort,
2818 tx_tiny_buf(cp, ring, entry), tabort);
2819 mapping = tx_tiny_map(cp, ring, entry, tentry);
2820 cas_write_txd(cp, ring, entry, mapping, tabort, ctrl,
2823 cas_write_txd(cp, ring, entry, mapping, len, ctrl |
2824 TX_DESC_SOF, (nr_frags == 0));
2826 entry = TX_DESC_NEXT(ring, entry);
2828 for (frag = 0; frag < nr_frags; frag++) {
2829 const skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
2831 len = skb_frag_size(fragp);
2832 mapping = skb_frag_dma_map(&cp->pdev->dev, fragp, 0, len,
2835 tabort = cas_calc_tabort(cp, fragp->page_offset, len);
2836 if (unlikely(tabort)) {
2839 /* NOTE: len is always > tabort */
2840 cas_write_txd(cp, ring, entry, mapping, len - tabort,
2842 entry = TX_DESC_NEXT(ring, entry);
2844 addr = cas_page_map(skb_frag_page(fragp));
2845 memcpy(tx_tiny_buf(cp, ring, entry),
2846 addr + fragp->page_offset + len - tabort,
2848 cas_page_unmap(addr);
2849 mapping = tx_tiny_map(cp, ring, entry, tentry);
2853 cas_write_txd(cp, ring, entry, mapping, len, ctrl,
2854 (frag + 1 == nr_frags));
2855 entry = TX_DESC_NEXT(ring, entry);
2858 cp->tx_new[ring] = entry;
2859 if (TX_BUFFS_AVAIL(cp, ring) <= CAS_TABORT(cp)*(MAX_SKB_FRAGS + 1))
2860 netif_stop_queue(dev);
2862 netif_printk(cp, tx_queued, KERN_DEBUG, dev,
2863 "tx[%d] queued, slot %d, skblen %d, avail %d\n",
2864 ring, entry, skb->len, TX_BUFFS_AVAIL(cp, ring));
2865 writel(entry, cp->regs + REG_TX_KICKN(ring));
2866 spin_unlock_irqrestore(&cp->tx_lock[ring], flags);
2870 static netdev_tx_t cas_start_xmit(struct sk_buff *skb, struct net_device *dev)
2872 struct cas *cp = netdev_priv(dev);
2874 /* this is only used as a load-balancing hint, so it doesn't
2875 * need to be SMP safe
2879 if (skb_padto(skb, cp->min_frame_size))
2880 return NETDEV_TX_OK;
2882 /* XXX: we need some higher-level QoS hooks to steer packets to
2883 * individual queues.
2885 if (cas_xmit_tx_ringN(cp, ring++ & N_TX_RINGS_MASK, skb))
2886 return NETDEV_TX_BUSY;
2887 return NETDEV_TX_OK;
2890 static void cas_init_tx_dma(struct cas *cp)
2892 u64 desc_dma = cp->block_dvma;
2897 /* set up tx completion writeback registers. must be 8-byte aligned */
2898 #ifdef USE_TX_COMPWB
2899 off = offsetof(struct cas_init_block, tx_compwb);
2900 writel((desc_dma + off) >> 32, cp->regs + REG_TX_COMPWB_DB_HI);
2901 writel((desc_dma + off) & 0xffffffff, cp->regs + REG_TX_COMPWB_DB_LOW);
2904 /* enable completion writebacks, enable paced mode,
2905 * disable read pipe, and disable pre-interrupt compwbs
2907 val = TX_CFG_COMPWB_Q1 | TX_CFG_COMPWB_Q2 |
2908 TX_CFG_COMPWB_Q3 | TX_CFG_COMPWB_Q4 |
2909 TX_CFG_DMA_RDPIPE_DIS | TX_CFG_PACED_MODE |
2910 TX_CFG_INTR_COMPWB_DIS;
2912 /* write out tx ring info and tx desc bases */
2913 for (i = 0; i < MAX_TX_RINGS; i++) {
2914 off = (unsigned long) cp->init_txds[i] -
2915 (unsigned long) cp->init_block;
2917 val |= CAS_TX_RINGN_BASE(i);
2918 writel((desc_dma + off) >> 32, cp->regs + REG_TX_DBN_HI(i));
2919 writel((desc_dma + off) & 0xffffffff, cp->regs +
2921 /* don't zero out the kick register here as the system
2925 writel(val, cp->regs + REG_TX_CFG);
2927 /* program max burst sizes. these numbers should be different
2931 writel(0x800, cp->regs + REG_TX_MAXBURST_0);
2932 writel(0x1600, cp->regs + REG_TX_MAXBURST_1);
2933 writel(0x2400, cp->regs + REG_TX_MAXBURST_2);
2934 writel(0x4800, cp->regs + REG_TX_MAXBURST_3);
2936 writel(0x800, cp->regs + REG_TX_MAXBURST_0);
2937 writel(0x800, cp->regs + REG_TX_MAXBURST_1);
2938 writel(0x800, cp->regs + REG_TX_MAXBURST_2);
2939 writel(0x800, cp->regs + REG_TX_MAXBURST_3);
2943 /* Must be invoked under cp->lock. */
2944 static inline void cas_init_dma(struct cas *cp)
2946 cas_init_tx_dma(cp);
2947 cas_init_rx_dma(cp);
2950 static void cas_process_mc_list(struct cas *cp)
2954 struct netdev_hw_addr *ha;
2957 memset(hash_table, 0, sizeof(hash_table));
2958 netdev_for_each_mc_addr(ha, cp->dev) {
2959 if (i <= CAS_MC_EXACT_MATCH_SIZE) {
2960 /* use the alternate mac address registers for the
2961 * first 15 multicast addresses
2963 writel((ha->addr[4] << 8) | ha->addr[5],
2964 cp->regs + REG_MAC_ADDRN(i*3 + 0));
2965 writel((ha->addr[2] << 8) | ha->addr[3],
2966 cp->regs + REG_MAC_ADDRN(i*3 + 1));
2967 writel((ha->addr[0] << 8) | ha->addr[1],
2968 cp->regs + REG_MAC_ADDRN(i*3 + 2));
2972 /* use hw hash table for the next series of
2973 * multicast addresses
2975 crc = ether_crc_le(ETH_ALEN, ha->addr);
2977 hash_table[crc >> 4] |= 1 << (15 - (crc & 0xf));
2980 for (i = 0; i < 16; i++)
2981 writel(hash_table[i], cp->regs + REG_MAC_HASH_TABLEN(i));
2984 /* Must be invoked under cp->lock. */
2985 static u32 cas_setup_multicast(struct cas *cp)
2990 if (cp->dev->flags & IFF_PROMISC) {
2991 rxcfg |= MAC_RX_CFG_PROMISC_EN;
2993 } else if (cp->dev->flags & IFF_ALLMULTI) {
2994 for (i=0; i < 16; i++)
2995 writel(0xFFFF, cp->regs + REG_MAC_HASH_TABLEN(i));
2996 rxcfg |= MAC_RX_CFG_HASH_FILTER_EN;
2999 cas_process_mc_list(cp);
3000 rxcfg |= MAC_RX_CFG_HASH_FILTER_EN;
3006 /* must be invoked under cp->stat_lock[N_TX_RINGS] */
3007 static void cas_clear_mac_err(struct cas *cp)
3009 writel(0, cp->regs + REG_MAC_COLL_NORMAL);
3010 writel(0, cp->regs + REG_MAC_COLL_FIRST);
3011 writel(0, cp->regs + REG_MAC_COLL_EXCESS);
3012 writel(0, cp->regs + REG_MAC_COLL_LATE);
3013 writel(0, cp->regs + REG_MAC_TIMER_DEFER);
3014 writel(0, cp->regs + REG_MAC_ATTEMPTS_PEAK);
3015 writel(0, cp->regs + REG_MAC_RECV_FRAME);
3016 writel(0, cp->regs + REG_MAC_LEN_ERR);
3017 writel(0, cp->regs + REG_MAC_ALIGN_ERR);
3018 writel(0, cp->regs + REG_MAC_FCS_ERR);
3019 writel(0, cp->regs + REG_MAC_RX_CODE_ERR);
3023 static void cas_mac_reset(struct cas *cp)
3027 /* do both TX and RX reset */
3028 writel(0x1, cp->regs + REG_MAC_TX_RESET);
3029 writel(0x1, cp->regs + REG_MAC_RX_RESET);
3034 if (readl(cp->regs + REG_MAC_TX_RESET) == 0)
3042 if (readl(cp->regs + REG_MAC_RX_RESET) == 0)
3047 if (readl(cp->regs + REG_MAC_TX_RESET) |
3048 readl(cp->regs + REG_MAC_RX_RESET))
3049 netdev_err(cp->dev, "mac tx[%d]/rx[%d] reset failed [%08x]\n",
3050 readl(cp->regs + REG_MAC_TX_RESET),
3051 readl(cp->regs + REG_MAC_RX_RESET),
3052 readl(cp->regs + REG_MAC_STATE_MACHINE));
3056 /* Must be invoked under cp->lock. */
3057 static void cas_init_mac(struct cas *cp)
3059 unsigned char *e = &cp->dev->dev_addr[0];
3063 /* setup core arbitration weight register */
3064 writel(CAWR_RR_DIS, cp->regs + REG_CAWR);
3066 /* XXX Use pci_dma_burst_advice() */
3067 #if !defined(CONFIG_SPARC64) && !defined(CONFIG_ALPHA)
3068 /* set the infinite burst register for chips that don't have
3071 if ((cp->cas_flags & CAS_FLAG_TARGET_ABORT) == 0)
3072 writel(INF_BURST_EN, cp->regs + REG_INF_BURST);
3075 writel(0x1BF0, cp->regs + REG_MAC_SEND_PAUSE);
3077 writel(0x00, cp->regs + REG_MAC_IPG0);
3078 writel(0x08, cp->regs + REG_MAC_IPG1);
3079 writel(0x04, cp->regs + REG_MAC_IPG2);
3081 /* change later for 802.3z */
3082 writel(0x40, cp->regs + REG_MAC_SLOT_TIME);
3084 /* min frame + FCS */
3085 writel(ETH_ZLEN + 4, cp->regs + REG_MAC_FRAMESIZE_MIN);
3087 /* Ethernet payload + header + FCS + optional VLAN tag. NOTE: we
3088 * specify the maximum frame size to prevent RX tag errors on
3091 writel(CAS_BASE(MAC_FRAMESIZE_MAX_BURST, 0x2000) |
3092 CAS_BASE(MAC_FRAMESIZE_MAX_FRAME,
3093 (CAS_MAX_MTU + ETH_HLEN + 4 + 4)),
3094 cp->regs + REG_MAC_FRAMESIZE_MAX);
3096 /* NOTE: crc_size is used as a surrogate for half-duplex.
3097 * workaround saturn half-duplex issue by increasing preamble
3100 if ((cp->cas_flags & CAS_FLAG_SATURN) && cp->crc_size)
3101 writel(0x41, cp->regs + REG_MAC_PA_SIZE);
3103 writel(0x07, cp->regs + REG_MAC_PA_SIZE);
3104 writel(0x04, cp->regs + REG_MAC_JAM_SIZE);
3105 writel(0x10, cp->regs + REG_MAC_ATTEMPT_LIMIT);
3106 writel(0x8808, cp->regs + REG_MAC_CTRL_TYPE);
3108 writel((e[5] | (e[4] << 8)) & 0x3ff, cp->regs + REG_MAC_RANDOM_SEED);
3110 writel(0, cp->regs + REG_MAC_ADDR_FILTER0);
3111 writel(0, cp->regs + REG_MAC_ADDR_FILTER1);
3112 writel(0, cp->regs + REG_MAC_ADDR_FILTER2);
3113 writel(0, cp->regs + REG_MAC_ADDR_FILTER2_1_MASK);
3114 writel(0, cp->regs + REG_MAC_ADDR_FILTER0_MASK);
3116 /* setup mac address in perfect filter array */
3117 for (i = 0; i < 45; i++)
3118 writel(0x0, cp->regs + REG_MAC_ADDRN(i));
3120 writel((e[4] << 8) | e[5], cp->regs + REG_MAC_ADDRN(0));
3121 writel((e[2] << 8) | e[3], cp->regs + REG_MAC_ADDRN(1));
3122 writel((e[0] << 8) | e[1], cp->regs + REG_MAC_ADDRN(2));
3124 writel(0x0001, cp->regs + REG_MAC_ADDRN(42));
3125 writel(0xc200, cp->regs + REG_MAC_ADDRN(43));
3126 writel(0x0180, cp->regs + REG_MAC_ADDRN(44));
3128 cp->mac_rx_cfg = cas_setup_multicast(cp);
3130 spin_lock(&cp->stat_lock[N_TX_RINGS]);
3131 cas_clear_mac_err(cp);
3132 spin_unlock(&cp->stat_lock[N_TX_RINGS]);
3134 /* Setup MAC interrupts. We want to get all of the interesting
3135 * counter expiration events, but we do not want to hear about
3136 * normal rx/tx as the DMA engine tells us that.
3138 writel(MAC_TX_FRAME_XMIT, cp->regs + REG_MAC_TX_MASK);
3139 writel(MAC_RX_FRAME_RECV, cp->regs + REG_MAC_RX_MASK);
3141 /* Don't enable even the PAUSE interrupts for now, we
3142 * make no use of those events other than to record them.
3144 writel(0xffffffff, cp->regs + REG_MAC_CTRL_MASK);
3147 /* Must be invoked under cp->lock. */
3148 static void cas_init_pause_thresholds(struct cas *cp)
3150 /* Calculate pause thresholds. Setting the OFF threshold to the
3151 * full RX fifo size effectively disables PAUSE generation
3153 if (cp->rx_fifo_size <= (2 * 1024)) {
3154 cp->rx_pause_off = cp->rx_pause_on = cp->rx_fifo_size;
3156 int max_frame = (cp->dev->mtu + ETH_HLEN + 4 + 4 + 64) & ~63;
3157 if (max_frame * 3 > cp->rx_fifo_size) {
3158 cp->rx_pause_off = 7104;
3159 cp->rx_pause_on = 960;
3161 int off = (cp->rx_fifo_size - (max_frame * 2));
3162 int on = off - max_frame;
3163 cp->rx_pause_off = off;
3164 cp->rx_pause_on = on;
3169 static int cas_vpd_match(const void __iomem *p, const char *str)
3171 int len = strlen(str) + 1;
3174 for (i = 0; i < len; i++) {
3175 if (readb(p + i) != str[i])
3182 /* get the mac address by reading the vpd information in the rom.
3183 * also get the phy type and determine if there's an entropy generator.
3184 * NOTE: this is a bit convoluted for the following reasons:
3185 * 1) vpd info has order-dependent mac addresses for multinic cards
3186 * 2) the only way to determine the nic order is to use the slot
3188 * 3) fiber cards don't have bridges, so their slot numbers don't
3190 * 4) we don't actually know we have a fiber card until after
3191 * the mac addresses are parsed.
3193 static int cas_get_vpd_info(struct cas *cp, unsigned char *dev_addr,
3196 void __iomem *p = cp->regs + REG_EXPANSION_ROM_RUN_START;
3197 void __iomem *base, *kstart;
3200 #define VPD_FOUND_MAC 0x01
3201 #define VPD_FOUND_PHY 0x02
3203 int phy_type = CAS_PHY_MII_MDIO0; /* default phy type */
3206 #if defined(CONFIG_SPARC)
3207 const unsigned char *addr;
3210 /* give us access to the PROM */
3211 writel(BIM_LOCAL_DEV_PROM | BIM_LOCAL_DEV_PAD,
3212 cp->regs + REG_BIM_LOCAL_DEV_EN);
3214 /* check for an expansion rom */
3215 if (readb(p) != 0x55 || readb(p + 1) != 0xaa)
3216 goto use_random_mac_addr;
3218 /* search for beginning of vpd */
3220 for (i = 2; i < EXPANSION_ROM_SIZE; i++) {
3221 /* check for PCIR */
3222 if ((readb(p + i + 0) == 0x50) &&
3223 (readb(p + i + 1) == 0x43) &&
3224 (readb(p + i + 2) == 0x49) &&
3225 (readb(p + i + 3) == 0x52)) {
3226 base = p + (readb(p + i + 8) |
3227 (readb(p + i + 9) << 8));
3232 if (!base || (readb(base) != 0x82))
3233 goto use_random_mac_addr;
3235 i = (readb(base + 1) | (readb(base + 2) << 8)) + 3;
3236 while (i < EXPANSION_ROM_SIZE) {
3237 if (readb(base + i) != 0x90) /* no vpd found */
3238 goto use_random_mac_addr;
3240 /* found a vpd field */
3241 len = readb(base + i + 1) | (readb(base + i + 2) << 8);
3243 /* extract keywords */
3244 kstart = base + i + 3;
3246 while ((p - kstart) < len) {
3247 int klen = readb(p + 2);
3253 /* look for the following things:
3254 * -- correct length == 29
3255 * 3 (type) + 2 (size) +
3256 * 18 (strlen("local-mac-address") + 1) +
3258 * -- VPD Instance 'I'
3259 * -- VPD Type Bytes 'B'
3260 * -- VPD data length == 6
3261 * -- property string == local-mac-address
3263 * -- correct length == 24
3264 * 3 (type) + 2 (size) +
3265 * 12 (strlen("entropy-dev") + 1) +
3266 * 7 (strlen("vms110") + 1)
3267 * -- VPD Instance 'I'
3268 * -- VPD Type String 'B'
3269 * -- VPD data length == 7
3270 * -- property string == entropy-dev
3272 * -- correct length == 18
3273 * 3 (type) + 2 (size) +
3274 * 9 (strlen("phy-type") + 1) +
3275 * 4 (strlen("pcs") + 1)
3276 * -- VPD Instance 'I'
3277 * -- VPD Type String 'S'
3278 * -- VPD data length == 4
3279 * -- property string == phy-type
3281 * -- correct length == 23
3282 * 3 (type) + 2 (size) +
3283 * 14 (strlen("phy-interface") + 1) +
3284 * 4 (strlen("pcs") + 1)
3285 * -- VPD Instance 'I'
3286 * -- VPD Type String 'S'
3287 * -- VPD data length == 4
3288 * -- property string == phy-interface
3290 if (readb(p) != 'I')
3293 /* finally, check string and length */
3294 type = readb(p + 3);
3296 if ((klen == 29) && readb(p + 4) == 6 &&
3297 cas_vpd_match(p + 5,
3298 "local-mac-address")) {
3299 if (mac_off++ > offset)
3302 /* set mac address */
3303 for (j = 0; j < 6; j++)
3313 #ifdef USE_ENTROPY_DEV
3315 cas_vpd_match(p + 5, "entropy-dev") &&
3316 cas_vpd_match(p + 17, "vms110")) {
3317 cp->cas_flags |= CAS_FLAG_ENTROPY_DEV;
3322 if (found & VPD_FOUND_PHY)
3325 if ((klen == 18) && readb(p + 4) == 4 &&
3326 cas_vpd_match(p + 5, "phy-type")) {
3327 if (cas_vpd_match(p + 14, "pcs")) {
3328 phy_type = CAS_PHY_SERDES;
3333 if ((klen == 23) && readb(p + 4) == 4 &&
3334 cas_vpd_match(p + 5, "phy-interface")) {
3335 if (cas_vpd_match(p + 19, "pcs")) {
3336 phy_type = CAS_PHY_SERDES;
3341 found |= VPD_FOUND_MAC;
3345 found |= VPD_FOUND_PHY;
3353 use_random_mac_addr:
3354 if (found & VPD_FOUND_MAC)
3357 #if defined(CONFIG_SPARC)
3358 addr = of_get_property(cp->of_node, "local-mac-address", NULL);
3360 memcpy(dev_addr, addr, 6);
3365 /* Sun MAC prefix then 3 random bytes. */
3366 pr_info("MAC address not found in ROM VPD\n");
3370 get_random_bytes(dev_addr + 3, 3);
3373 writel(0, cp->regs + REG_BIM_LOCAL_DEV_EN);
3377 /* check pci invariants */
3378 static void cas_check_pci_invariants(struct cas *cp)
3380 struct pci_dev *pdev = cp->pdev;
3383 if ((pdev->vendor == PCI_VENDOR_ID_SUN) &&
3384 (pdev->device == PCI_DEVICE_ID_SUN_CASSINI)) {
3385 if (pdev->revision >= CAS_ID_REVPLUS)
3386 cp->cas_flags |= CAS_FLAG_REG_PLUS;
3387 if (pdev->revision < CAS_ID_REVPLUS02u)
3388 cp->cas_flags |= CAS_FLAG_TARGET_ABORT;
3390 /* Original Cassini supports HW CSUM, but it's not
3391 * enabled by default as it can trigger TX hangs.
3393 if (pdev->revision < CAS_ID_REV2)
3394 cp->cas_flags |= CAS_FLAG_NO_HW_CSUM;
3396 /* Only sun has original cassini chips. */
3397 cp->cas_flags |= CAS_FLAG_REG_PLUS;
3399 /* We use a flag because the same phy might be externally
3402 if ((pdev->vendor == PCI_VENDOR_ID_NS) &&
3403 (pdev->device == PCI_DEVICE_ID_NS_SATURN))
3404 cp->cas_flags |= CAS_FLAG_SATURN;
3409 static int cas_check_invariants(struct cas *cp)
3411 struct pci_dev *pdev = cp->pdev;
3415 /* get page size for rx buffers. */
3417 #ifdef USE_PAGE_ORDER
3418 if (PAGE_SHIFT < CAS_JUMBO_PAGE_SHIFT) {
3419 /* see if we can allocate larger pages */
3420 struct page *page = alloc_pages(GFP_ATOMIC,
3421 CAS_JUMBO_PAGE_SHIFT -
3424 __free_pages(page, CAS_JUMBO_PAGE_SHIFT - PAGE_SHIFT);
3425 cp->page_order = CAS_JUMBO_PAGE_SHIFT - PAGE_SHIFT;
3427 printk("MTU limited to %d bytes\n", CAS_MAX_MTU);
3431 cp->page_size = (PAGE_SIZE << cp->page_order);
3433 /* Fetch the FIFO configurations. */
3434 cp->tx_fifo_size = readl(cp->regs + REG_TX_FIFO_SIZE) * 64;
3435 cp->rx_fifo_size = RX_FIFO_SIZE;
3437 /* finish phy determination. MDIO1 takes precedence over MDIO0 if
3438 * they're both connected.
3440 cp->phy_type = cas_get_vpd_info(cp, cp->dev->dev_addr,
3441 PCI_SLOT(pdev->devfn));
3442 if (cp->phy_type & CAS_PHY_SERDES) {
3443 cp->cas_flags |= CAS_FLAG_1000MB_CAP;
3444 return 0; /* no more checking needed */
3448 cfg = readl(cp->regs + REG_MIF_CFG);
3449 if (cfg & MIF_CFG_MDIO_1) {
3450 cp->phy_type = CAS_PHY_MII_MDIO1;
3451 } else if (cfg & MIF_CFG_MDIO_0) {
3452 cp->phy_type = CAS_PHY_MII_MDIO0;
3455 cas_mif_poll(cp, 0);
3456 writel(PCS_DATAPATH_MODE_MII, cp->regs + REG_PCS_DATAPATH_MODE);
3458 for (i = 0; i < 32; i++) {
3462 for (j = 0; j < 3; j++) {
3464 phy_id = cas_phy_read(cp, MII_PHYSID1) << 16;
3465 phy_id |= cas_phy_read(cp, MII_PHYSID2);
3466 if (phy_id && (phy_id != 0xFFFFFFFF)) {
3467 cp->phy_id = phy_id;
3472 pr_err("MII phy did not respond [%08x]\n",
3473 readl(cp->regs + REG_MIF_STATE_MACHINE));
3477 /* see if we can do gigabit */
3478 cfg = cas_phy_read(cp, MII_BMSR);
3479 if ((cfg & CAS_BMSR_1000_EXTEND) &&
3480 cas_phy_read(cp, CAS_MII_1000_EXTEND))
3481 cp->cas_flags |= CAS_FLAG_1000MB_CAP;
3485 /* Must be invoked under cp->lock. */
3486 static inline void cas_start_dma(struct cas *cp)
3493 val = readl(cp->regs + REG_TX_CFG) | TX_CFG_DMA_EN;
3494 writel(val, cp->regs + REG_TX_CFG);
3495 val = readl(cp->regs + REG_RX_CFG) | RX_CFG_DMA_EN;
3496 writel(val, cp->regs + REG_RX_CFG);
3498 /* enable the mac */
3499 val = readl(cp->regs + REG_MAC_TX_CFG) | MAC_TX_CFG_EN;
3500 writel(val, cp->regs + REG_MAC_TX_CFG);
3501 val = readl(cp->regs + REG_MAC_RX_CFG) | MAC_RX_CFG_EN;
3502 writel(val, cp->regs + REG_MAC_RX_CFG);
3506 val = readl(cp->regs + REG_MAC_TX_CFG);
3507 if ((val & MAC_TX_CFG_EN))
3511 if (i < 0) txfailed = 1;
3514 val = readl(cp->regs + REG_MAC_RX_CFG);
3515 if ((val & MAC_RX_CFG_EN)) {
3518 "enabling mac failed [tx:%08x:%08x]\n",
3519 readl(cp->regs + REG_MIF_STATE_MACHINE),
3520 readl(cp->regs + REG_MAC_STATE_MACHINE));
3522 goto enable_rx_done;
3526 netdev_err(cp->dev, "enabling mac failed [%s:%08x:%08x]\n",
3527 (txfailed ? "tx,rx" : "rx"),
3528 readl(cp->regs + REG_MIF_STATE_MACHINE),
3529 readl(cp->regs + REG_MAC_STATE_MACHINE));
3532 cas_unmask_intr(cp); /* enable interrupts */
3533 writel(RX_DESC_RINGN_SIZE(0) - 4, cp->regs + REG_RX_KICK);
3534 writel(0, cp->regs + REG_RX_COMP_TAIL);
3536 if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
3537 if (N_RX_DESC_RINGS > 1)
3538 writel(RX_DESC_RINGN_SIZE(1) - 4,
3539 cp->regs + REG_PLUS_RX_KICK1);
3541 for (i = 1; i < N_RX_COMP_RINGS; i++)
3542 writel(0, cp->regs + REG_PLUS_RX_COMPN_TAIL(i));
3546 /* Must be invoked under cp->lock. */
3547 static void cas_read_pcs_link_mode(struct cas *cp, int *fd, int *spd,
3550 u32 val = readl(cp->regs + REG_PCS_MII_LPA);
3551 *fd = (val & PCS_MII_LPA_FD) ? 1 : 0;
3552 *pause = (val & PCS_MII_LPA_SYM_PAUSE) ? 0x01 : 0x00;
3553 if (val & PCS_MII_LPA_ASYM_PAUSE)
3558 /* Must be invoked under cp->lock. */
3559 static void cas_read_mii_link_mode(struct cas *cp, int *fd, int *spd,
3568 /* use GMII registers */
3569 val = cas_phy_read(cp, MII_LPA);
3570 if (val & CAS_LPA_PAUSE)
3573 if (val & CAS_LPA_ASYM_PAUSE)
3576 if (val & LPA_DUPLEX)
3581 if (cp->cas_flags & CAS_FLAG_1000MB_CAP) {
3582 val = cas_phy_read(cp, CAS_MII_1000_STATUS);
3583 if (val & (CAS_LPA_1000FULL | CAS_LPA_1000HALF))
3585 if (val & CAS_LPA_1000FULL)
3590 /* A link-up condition has occurred, initialize and enable the
3593 * Must be invoked under cp->lock.
3595 static void cas_set_link_modes(struct cas *cp)
3598 int full_duplex, speed, pause;
3604 if (CAS_PHY_MII(cp->phy_type)) {
3605 cas_mif_poll(cp, 0);
3606 val = cas_phy_read(cp, MII_BMCR);
3607 if (val & BMCR_ANENABLE) {
3608 cas_read_mii_link_mode(cp, &full_duplex, &speed,
3611 if (val & BMCR_FULLDPLX)
3614 if (val & BMCR_SPEED100)
3616 else if (val & CAS_BMCR_SPEED1000)
3617 speed = (cp->cas_flags & CAS_FLAG_1000MB_CAP) ?
3620 cas_mif_poll(cp, 1);
3623 val = readl(cp->regs + REG_PCS_MII_CTRL);
3624 cas_read_pcs_link_mode(cp, &full_duplex, &speed, &pause);
3625 if ((val & PCS_MII_AUTONEG_EN) == 0) {
3626 if (val & PCS_MII_CTRL_DUPLEX)
3631 netif_info(cp, link, cp->dev, "Link up at %d Mbps, %s-duplex\n",
3632 speed, full_duplex ? "full" : "half");
3634 val = MAC_XIF_TX_MII_OUTPUT_EN | MAC_XIF_LINK_LED;
3635 if (CAS_PHY_MII(cp->phy_type)) {
3636 val |= MAC_XIF_MII_BUFFER_OUTPUT_EN;
3638 val |= MAC_XIF_DISABLE_ECHO;
3641 val |= MAC_XIF_FDPLX_LED;
3643 val |= MAC_XIF_GMII_MODE;
3644 writel(val, cp->regs + REG_MAC_XIF_CFG);
3646 /* deal with carrier and collision detect. */
3647 val = MAC_TX_CFG_IPG_EN;
3649 val |= MAC_TX_CFG_IGNORE_CARRIER;
3650 val |= MAC_TX_CFG_IGNORE_COLL;
3652 #ifndef USE_CSMA_CD_PROTO
3653 val |= MAC_TX_CFG_NEVER_GIVE_UP_EN;
3654 val |= MAC_TX_CFG_NEVER_GIVE_UP_LIM;
3657 /* val now set up for REG_MAC_TX_CFG */
3659 /* If gigabit and half-duplex, enable carrier extension
3660 * mode. increase slot time to 512 bytes as well.
3661 * else, disable it and make sure slot time is 64 bytes.
3662 * also activate checksum bug workaround
3664 if ((speed == 1000) && !full_duplex) {
3665 writel(val | MAC_TX_CFG_CARRIER_EXTEND,
3666 cp->regs + REG_MAC_TX_CFG);
3668 val = readl(cp->regs + REG_MAC_RX_CFG);
3669 val &= ~MAC_RX_CFG_STRIP_FCS; /* checksum workaround */
3670 writel(val | MAC_RX_CFG_CARRIER_EXTEND,
3671 cp->regs + REG_MAC_RX_CFG);
3673 writel(0x200, cp->regs + REG_MAC_SLOT_TIME);
3676 /* minimum size gigabit frame at half duplex */
3677 cp->min_frame_size = CAS_1000MB_MIN_FRAME;
3680 writel(val, cp->regs + REG_MAC_TX_CFG);
3682 /* checksum bug workaround. don't strip FCS when in
3685 val = readl(cp->regs + REG_MAC_RX_CFG);
3687 val |= MAC_RX_CFG_STRIP_FCS;
3689 cp->min_frame_size = CAS_MIN_MTU;
3691 val &= ~MAC_RX_CFG_STRIP_FCS;
3693 cp->min_frame_size = CAS_MIN_FRAME;
3695 writel(val & ~MAC_RX_CFG_CARRIER_EXTEND,
3696 cp->regs + REG_MAC_RX_CFG);
3697 writel(0x40, cp->regs + REG_MAC_SLOT_TIME);
3700 if (netif_msg_link(cp)) {
3702 netdev_info(cp->dev, "Pause is enabled (rxfifo: %d off: %d on: %d)\n",
3706 } else if (pause & 0x10) {
3707 netdev_info(cp->dev, "TX pause enabled\n");
3709 netdev_info(cp->dev, "Pause is disabled\n");
3713 val = readl(cp->regs + REG_MAC_CTRL_CFG);
3714 val &= ~(MAC_CTRL_CFG_SEND_PAUSE_EN | MAC_CTRL_CFG_RECV_PAUSE_EN);
3715 if (pause) { /* symmetric or asymmetric pause */
3716 val |= MAC_CTRL_CFG_SEND_PAUSE_EN;
3717 if (pause & 0x01) { /* symmetric pause */
3718 val |= MAC_CTRL_CFG_RECV_PAUSE_EN;
3721 writel(val, cp->regs + REG_MAC_CTRL_CFG);
3725 /* Must be invoked under cp->lock. */
3726 static void cas_init_hw(struct cas *cp, int restart_link)
3731 cas_init_pause_thresholds(cp);
3736 /* Default aneg parameters */
3737 cp->timer_ticks = 0;
3738 cas_begin_auto_negotiation(cp, NULL);
3739 } else if (cp->lstate == link_up) {
3740 cas_set_link_modes(cp);
3741 netif_carrier_on(cp->dev);
3745 /* Must be invoked under cp->lock. on earlier cassini boards,
3746 * SOFT_0 is tied to PCI reset. we use this to force a pci reset,
3747 * let it settle out, and then restore pci state.
3749 static void cas_hard_reset(struct cas *cp)
3751 writel(BIM_LOCAL_DEV_SOFT_0, cp->regs + REG_BIM_LOCAL_DEV_EN);
3753 pci_restore_state(cp->pdev);
3757 static void cas_global_reset(struct cas *cp, int blkflag)
3761 /* issue a global reset. don't use RSTOUT. */
3762 if (blkflag && !CAS_PHY_MII(cp->phy_type)) {
3763 /* For PCS, when the blkflag is set, we should set the
3764 * SW_REST_BLOCK_PCS_SLINK bit to prevent the results of
3765 * the last autonegotiation from being cleared. We'll
3766 * need some special handling if the chip is set into a
3769 writel((SW_RESET_TX | SW_RESET_RX | SW_RESET_BLOCK_PCS_SLINK),
3770 cp->regs + REG_SW_RESET);
3772 writel(SW_RESET_TX | SW_RESET_RX, cp->regs + REG_SW_RESET);
3775 /* need to wait at least 3ms before polling register */
3779 while (limit-- > 0) {
3780 u32 val = readl(cp->regs + REG_SW_RESET);
3781 if ((val & (SW_RESET_TX | SW_RESET_RX)) == 0)
3785 netdev_err(cp->dev, "sw reset failed\n");
3788 /* enable various BIM interrupts */
3789 writel(BIM_CFG_DPAR_INTR_ENABLE | BIM_CFG_RMA_INTR_ENABLE |
3790 BIM_CFG_RTA_INTR_ENABLE, cp->regs + REG_BIM_CFG);
3792 /* clear out pci error status mask for handled errors.
3793 * we don't deal with DMA counter overflows as they happen
3796 writel(0xFFFFFFFFU & ~(PCI_ERR_BADACK | PCI_ERR_DTRTO |
3797 PCI_ERR_OTHER | PCI_ERR_BIM_DMA_WRITE |
3798 PCI_ERR_BIM_DMA_READ), cp->regs +
3799 REG_PCI_ERR_STATUS_MASK);
3801 /* set up for MII by default to address mac rx reset timeout
3804 writel(PCS_DATAPATH_MODE_MII, cp->regs + REG_PCS_DATAPATH_MODE);
3807 static void cas_reset(struct cas *cp, int blkflag)
3812 cas_global_reset(cp, blkflag);
3814 cas_entropy_reset(cp);
3816 /* disable dma engines. */
3817 val = readl(cp->regs + REG_TX_CFG);
3818 val &= ~TX_CFG_DMA_EN;
3819 writel(val, cp->regs + REG_TX_CFG);
3821 val = readl(cp->regs + REG_RX_CFG);
3822 val &= ~RX_CFG_DMA_EN;
3823 writel(val, cp->regs + REG_RX_CFG);
3825 /* program header parser */
3826 if ((cp->cas_flags & CAS_FLAG_TARGET_ABORT) ||
3827 (CAS_HP_ALT_FIRMWARE == cas_prog_null)) {
3828 cas_load_firmware(cp, CAS_HP_FIRMWARE);
3830 cas_load_firmware(cp, CAS_HP_ALT_FIRMWARE);
3833 /* clear out error registers */
3834 spin_lock(&cp->stat_lock[N_TX_RINGS]);
3835 cas_clear_mac_err(cp);
3836 spin_unlock(&cp->stat_lock[N_TX_RINGS]);
3839 /* Shut down the chip, must be called with pm_mutex held. */
3840 static void cas_shutdown(struct cas *cp)
3842 unsigned long flags;
3844 /* Make us not-running to avoid timers respawning */
3847 del_timer_sync(&cp->link_timer);
3849 /* Stop the reset task */
3851 while (atomic_read(&cp->reset_task_pending_mtu) ||
3852 atomic_read(&cp->reset_task_pending_spare) ||
3853 atomic_read(&cp->reset_task_pending_all))
3857 while (atomic_read(&cp->reset_task_pending))
3860 /* Actually stop the chip */
3861 cas_lock_all_save(cp, flags);
3863 if (cp->cas_flags & CAS_FLAG_SATURN)
3864 cas_phy_powerdown(cp);
3865 cas_unlock_all_restore(cp, flags);
3868 static int cas_change_mtu(struct net_device *dev, int new_mtu)
3870 struct cas *cp = netdev_priv(dev);
3872 if (new_mtu < CAS_MIN_MTU || new_mtu > CAS_MAX_MTU)
3876 if (!netif_running(dev) || !netif_device_present(dev))
3879 /* let the reset task handle it */
3881 atomic_inc(&cp->reset_task_pending);
3882 if ((cp->phy_type & CAS_PHY_SERDES)) {
3883 atomic_inc(&cp->reset_task_pending_all);
3885 atomic_inc(&cp->reset_task_pending_mtu);
3887 schedule_work(&cp->reset_task);
3889 atomic_set(&cp->reset_task_pending, (cp->phy_type & CAS_PHY_SERDES) ?
3890 CAS_RESET_ALL : CAS_RESET_MTU);
3891 pr_err("reset called in cas_change_mtu\n");
3892 schedule_work(&cp->reset_task);
3895 flush_work_sync(&cp->reset_task);
3899 static void cas_clean_txd(struct cas *cp, int ring)
3901 struct cas_tx_desc *txd = cp->init_txds[ring];
3902 struct sk_buff *skb, **skbs = cp->tx_skbs[ring];
3906 size = TX_DESC_RINGN_SIZE(ring);
3907 for (i = 0; i < size; i++) {
3910 if (skbs[i] == NULL)
3916 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
3917 int ent = i & (size - 1);
3919 /* first buffer is never a tiny buffer and so
3920 * needs to be unmapped.
3922 daddr = le64_to_cpu(txd[ent].buffer);
3923 dlen = CAS_VAL(TX_DESC_BUFLEN,
3924 le64_to_cpu(txd[ent].control));
3925 pci_unmap_page(cp->pdev, daddr, dlen,
3928 if (frag != skb_shinfo(skb)->nr_frags) {
3931 /* next buffer might by a tiny buffer.
3934 ent = i & (size - 1);
3935 if (cp->tx_tiny_use[ring][ent].used)
3939 dev_kfree_skb_any(skb);
3942 /* zero out tiny buf usage */
3943 memset(cp->tx_tiny_use[ring], 0, size*sizeof(*cp->tx_tiny_use[ring]));
3946 /* freed on close */
3947 static inline void cas_free_rx_desc(struct cas *cp, int ring)
3949 cas_page_t **page = cp->rx_pages[ring];
3952 size = RX_DESC_RINGN_SIZE(ring);
3953 for (i = 0; i < size; i++) {
3955 cas_page_free(cp, page[i]);
3961 static void cas_free_rxds(struct cas *cp)
3965 for (i = 0; i < N_RX_DESC_RINGS; i++)
3966 cas_free_rx_desc(cp, i);
3969 /* Must be invoked under cp->lock. */
3970 static void cas_clean_rings(struct cas *cp)
3974 /* need to clean all tx rings */
3975 memset(cp->tx_old, 0, sizeof(*cp->tx_old)*N_TX_RINGS);
3976 memset(cp->tx_new, 0, sizeof(*cp->tx_new)*N_TX_RINGS);
3977 for (i = 0; i < N_TX_RINGS; i++)
3978 cas_clean_txd(cp, i);
3980 /* zero out init block */
3981 memset(cp->init_block, 0, sizeof(struct cas_init_block));
3986 /* allocated on open */
3987 static inline int cas_alloc_rx_desc(struct cas *cp, int ring)
3989 cas_page_t **page = cp->rx_pages[ring];
3992 size = RX_DESC_RINGN_SIZE(ring);
3993 for (i = 0; i < size; i++) {
3994 if ((page[i] = cas_page_alloc(cp, GFP_KERNEL)) == NULL)
4000 static int cas_alloc_rxds(struct cas *cp)
4004 for (i = 0; i < N_RX_DESC_RINGS; i++) {
4005 if (cas_alloc_rx_desc(cp, i) < 0) {
4013 static void cas_reset_task(struct work_struct *work)
4015 struct cas *cp = container_of(work, struct cas, reset_task);
4017 int pending = atomic_read(&cp->reset_task_pending);
4019 int pending_all = atomic_read(&cp->reset_task_pending_all);
4020 int pending_spare = atomic_read(&cp->reset_task_pending_spare);
4021 int pending_mtu = atomic_read(&cp->reset_task_pending_mtu);
4023 if (pending_all == 0 && pending_spare == 0 && pending_mtu == 0) {
4024 /* We can have more tasks scheduled than actually
4027 atomic_dec(&cp->reset_task_pending);
4031 /* The link went down, we reset the ring, but keep
4032 * DMA stopped. Use this function for reset
4035 if (cp->hw_running) {
4036 unsigned long flags;
4038 /* Make sure we don't get interrupts or tx packets */
4039 netif_device_detach(cp->dev);
4040 cas_lock_all_save(cp, flags);
4043 /* We call cas_spare_recover when we call cas_open.
4044 * but we do not initialize the lists cas_spare_recover
4045 * uses until cas_open is called.
4047 cas_spare_recover(cp, GFP_ATOMIC);
4050 /* test => only pending_spare set */
4051 if (!pending_all && !pending_mtu)
4054 if (pending == CAS_RESET_SPARE)
4057 /* when pending == CAS_RESET_ALL, the following
4058 * call to cas_init_hw will restart auto negotiation.
4059 * Setting the second argument of cas_reset to
4060 * !(pending == CAS_RESET_ALL) will set this argument
4061 * to 1 (avoiding reinitializing the PHY for the normal
4062 * PCS case) when auto negotiation is not restarted.
4065 cas_reset(cp, !(pending_all > 0));
4067 cas_clean_rings(cp);
4068 cas_init_hw(cp, (pending_all > 0));
4070 cas_reset(cp, !(pending == CAS_RESET_ALL));
4072 cas_clean_rings(cp);
4073 cas_init_hw(cp, pending == CAS_RESET_ALL);
4077 cas_unlock_all_restore(cp, flags);
4078 netif_device_attach(cp->dev);
4081 atomic_sub(pending_all, &cp->reset_task_pending_all);
4082 atomic_sub(pending_spare, &cp->reset_task_pending_spare);
4083 atomic_sub(pending_mtu, &cp->reset_task_pending_mtu);
4084 atomic_dec(&cp->reset_task_pending);
4086 atomic_set(&cp->reset_task_pending, 0);
4090 static void cas_link_timer(unsigned long data)
4092 struct cas *cp = (struct cas *) data;
4093 int mask, pending = 0, reset = 0;
4094 unsigned long flags;
4096 if (link_transition_timeout != 0 &&
4097 cp->link_transition_jiffies_valid &&
4098 ((jiffies - cp->link_transition_jiffies) >
4099 (link_transition_timeout))) {
4100 /* One-second counter so link-down workaround doesn't
4101 * cause resets to occur so fast as to fool the switch
4102 * into thinking the link is down.
4104 cp->link_transition_jiffies_valid = 0;
4107 if (!cp->hw_running)
4110 spin_lock_irqsave(&cp->lock, flags);
4112 cas_entropy_gather(cp);
4114 /* If the link task is still pending, we just
4115 * reschedule the link timer
4118 if (atomic_read(&cp->reset_task_pending_all) ||
4119 atomic_read(&cp->reset_task_pending_spare) ||
4120 atomic_read(&cp->reset_task_pending_mtu))
4123 if (atomic_read(&cp->reset_task_pending))
4127 /* check for rx cleaning */
4128 if ((mask = (cp->cas_flags & CAS_FLAG_RXD_POST_MASK))) {
4131 for (i = 0; i < MAX_RX_DESC_RINGS; i++) {
4132 rmask = CAS_FLAG_RXD_POST(i);
4133 if ((mask & rmask) == 0)
4136 /* post_rxds will do a mod_timer */
4137 if (cas_post_rxds_ringN(cp, i, cp->rx_last[i]) < 0) {
4141 cp->cas_flags &= ~rmask;
4145 if (CAS_PHY_MII(cp->phy_type)) {
4147 cas_mif_poll(cp, 0);
4148 bmsr = cas_phy_read(cp, MII_BMSR);
4149 /* WTZ: Solaris driver reads this twice, but that
4150 * may be due to the PCS case and the use of a
4151 * common implementation. Read it twice here to be
4154 bmsr = cas_phy_read(cp, MII_BMSR);
4155 cas_mif_poll(cp, 1);
4156 readl(cp->regs + REG_MIF_STATUS); /* avoid dups */
4157 reset = cas_mii_link_check(cp, bmsr);
4159 reset = cas_pcs_link_check(cp);
4165 /* check for tx state machine confusion */
4166 if ((readl(cp->regs + REG_MAC_TX_STATUS) & MAC_TX_FRAME_XMIT) == 0) {
4167 u32 val = readl(cp->regs + REG_MAC_STATE_MACHINE);
4169 int tlm = CAS_VAL(MAC_SM_TLM, val);
4171 if (((tlm == 0x5) || (tlm == 0x3)) &&
4172 (CAS_VAL(MAC_SM_ENCAP_SM, val) == 0)) {
4173 netif_printk(cp, tx_err, KERN_DEBUG, cp->dev,
4174 "tx err: MAC_STATE[%08x]\n", val);
4179 val = readl(cp->regs + REG_TX_FIFO_PKT_CNT);
4180 wptr = readl(cp->regs + REG_TX_FIFO_WRITE_PTR);
4181 rptr = readl(cp->regs + REG_TX_FIFO_READ_PTR);
4182 if ((val == 0) && (wptr != rptr)) {
4183 netif_printk(cp, tx_err, KERN_DEBUG, cp->dev,
4184 "tx err: TX_FIFO[%08x:%08x:%08x]\n",
4196 atomic_inc(&cp->reset_task_pending);
4197 atomic_inc(&cp->reset_task_pending_all);
4198 schedule_work(&cp->reset_task);
4200 atomic_set(&cp->reset_task_pending, CAS_RESET_ALL);
4201 pr_err("reset called in cas_link_timer\n");
4202 schedule_work(&cp->reset_task);
4207 mod_timer(&cp->link_timer, jiffies + CAS_LINK_TIMEOUT);
4209 spin_unlock_irqrestore(&cp->lock, flags);
4212 /* tiny buffers are used to avoid target abort issues with
4215 static void cas_tx_tiny_free(struct cas *cp)
4217 struct pci_dev *pdev = cp->pdev;
4220 for (i = 0; i < N_TX_RINGS; i++) {
4221 if (!cp->tx_tiny_bufs[i])
4224 pci_free_consistent(pdev, TX_TINY_BUF_BLOCK,
4225 cp->tx_tiny_bufs[i],
4226 cp->tx_tiny_dvma[i]);
4227 cp->tx_tiny_bufs[i] = NULL;
4231 static int cas_tx_tiny_alloc(struct cas *cp)
4233 struct pci_dev *pdev = cp->pdev;
4236 for (i = 0; i < N_TX_RINGS; i++) {
4237 cp->tx_tiny_bufs[i] =
4238 pci_alloc_consistent(pdev, TX_TINY_BUF_BLOCK,
4239 &cp->tx_tiny_dvma[i]);
4240 if (!cp->tx_tiny_bufs[i]) {
4241 cas_tx_tiny_free(cp);
4249 static int cas_open(struct net_device *dev)
4251 struct cas *cp = netdev_priv(dev);
4253 unsigned long flags;
4255 mutex_lock(&cp->pm_mutex);
4257 hw_was_up = cp->hw_running;
4259 /* The power-management mutex protects the hw_running
4260 * etc. state so it is safe to do this bit without cp->lock
4262 if (!cp->hw_running) {
4263 /* Reset the chip */
4264 cas_lock_all_save(cp, flags);
4265 /* We set the second arg to cas_reset to zero
4266 * because cas_init_hw below will have its second
4267 * argument set to non-zero, which will force
4268 * autonegotiation to start.
4272 cas_unlock_all_restore(cp, flags);
4276 if (cas_tx_tiny_alloc(cp) < 0)
4279 /* alloc rx descriptors */
4280 if (cas_alloc_rxds(cp) < 0)
4283 /* allocate spares */
4285 cas_spare_recover(cp, GFP_KERNEL);
4287 /* We can now request the interrupt as we know it's masked
4288 * on the controller. cassini+ has up to 4 interrupts
4289 * that can be used, but you need to do explicit pci interrupt
4290 * mapping to expose them
4292 if (request_irq(cp->pdev->irq, cas_interrupt,
4293 IRQF_SHARED, dev->name, (void *) dev)) {
4294 netdev_err(cp->dev, "failed to request irq !\n");
4300 napi_enable(&cp->napi);
4303 cas_lock_all_save(cp, flags);
4304 cas_clean_rings(cp);
4305 cas_init_hw(cp, !hw_was_up);
4307 cas_unlock_all_restore(cp, flags);
4309 netif_start_queue(dev);
4310 mutex_unlock(&cp->pm_mutex);
4317 cas_tx_tiny_free(cp);
4319 mutex_unlock(&cp->pm_mutex);
4323 static int cas_close(struct net_device *dev)
4325 unsigned long flags;
4326 struct cas *cp = netdev_priv(dev);
4329 napi_disable(&cp->napi);
4331 /* Make sure we don't get distracted by suspend/resume */
4332 mutex_lock(&cp->pm_mutex);
4334 netif_stop_queue(dev);
4336 /* Stop traffic, mark us closed */
4337 cas_lock_all_save(cp, flags);
4341 cas_begin_auto_negotiation(cp, NULL);
4342 cas_clean_rings(cp);
4343 cas_unlock_all_restore(cp, flags);
4345 free_irq(cp->pdev->irq, (void *) dev);
4348 cas_tx_tiny_free(cp);
4349 mutex_unlock(&cp->pm_mutex);
4354 const char name[ETH_GSTRING_LEN];
4355 } ethtool_cassini_statnames[] = {
4362 {"rx_frame_errors"},
4363 {"rx_length_errors"},
4366 {"tx_aborted_errors"},
4373 #define CAS_NUM_STAT_KEYS ARRAY_SIZE(ethtool_cassini_statnames)
4376 const int offsets; /* neg. values for 2nd arg to cas_read_phy */
4377 } ethtool_register_table[] = {
4392 {REG_PCS_MII_STATUS},
4393 {REG_PCS_STATE_MACHINE},
4394 {REG_MAC_COLL_EXCESS},
4397 #define CAS_REG_LEN ARRAY_SIZE(ethtool_register_table)
4398 #define CAS_MAX_REGS (sizeof (u32)*CAS_REG_LEN)
4400 static void cas_read_regs(struct cas *cp, u8 *ptr, int len)
4404 unsigned long flags;
4406 spin_lock_irqsave(&cp->lock, flags);
4407 for (i = 0, p = ptr; i < len ; i ++, p += sizeof(u32)) {
4410 if (ethtool_register_table[i].offsets < 0) {
4411 hval = cas_phy_read(cp,
4412 -ethtool_register_table[i].offsets);
4415 val= readl(cp->regs+ethtool_register_table[i].offsets);
4417 memcpy(p, (u8 *)&val, sizeof(u32));
4419 spin_unlock_irqrestore(&cp->lock, flags);
4422 static struct net_device_stats *cas_get_stats(struct net_device *dev)
4424 struct cas *cp = netdev_priv(dev);
4425 struct net_device_stats *stats = cp->net_stats;
4426 unsigned long flags;
4430 /* we collate all of the stats into net_stats[N_TX_RING] */
4431 if (!cp->hw_running)
4432 return stats + N_TX_RINGS;
4434 /* collect outstanding stats */
4435 /* WTZ: the Cassini spec gives these as 16 bit counters but
4436 * stored in 32-bit words. Added a mask of 0xffff to be safe,
4437 * in case the chip somehow puts any garbage in the other bits.
4438 * Also, counter usage didn't seem to mach what Adrian did
4439 * in the parts of the code that set these quantities. Made
4442 spin_lock_irqsave(&cp->stat_lock[N_TX_RINGS], flags);
4443 stats[N_TX_RINGS].rx_crc_errors +=
4444 readl(cp->regs + REG_MAC_FCS_ERR) & 0xffff;
4445 stats[N_TX_RINGS].rx_frame_errors +=
4446 readl(cp->regs + REG_MAC_ALIGN_ERR) &0xffff;
4447 stats[N_TX_RINGS].rx_length_errors +=
4448 readl(cp->regs + REG_MAC_LEN_ERR) & 0xffff;
4450 tmp = (readl(cp->regs + REG_MAC_COLL_EXCESS) & 0xffff) +
4451 (readl(cp->regs + REG_MAC_COLL_LATE) & 0xffff);
4452 stats[N_TX_RINGS].tx_aborted_errors += tmp;
4453 stats[N_TX_RINGS].collisions +=
4454 tmp + (readl(cp->regs + REG_MAC_COLL_NORMAL) & 0xffff);
4456 stats[N_TX_RINGS].tx_aborted_errors +=
4457 readl(cp->regs + REG_MAC_COLL_EXCESS);
4458 stats[N_TX_RINGS].collisions += readl(cp->regs + REG_MAC_COLL_EXCESS) +
4459 readl(cp->regs + REG_MAC_COLL_LATE);
4461 cas_clear_mac_err(cp);
4463 /* saved bits that are unique to ring 0 */
4464 spin_lock(&cp->stat_lock[0]);
4465 stats[N_TX_RINGS].collisions += stats[0].collisions;
4466 stats[N_TX_RINGS].rx_over_errors += stats[0].rx_over_errors;
4467 stats[N_TX_RINGS].rx_frame_errors += stats[0].rx_frame_errors;
4468 stats[N_TX_RINGS].rx_fifo_errors += stats[0].rx_fifo_errors;
4469 stats[N_TX_RINGS].tx_aborted_errors += stats[0].tx_aborted_errors;
4470 stats[N_TX_RINGS].tx_fifo_errors += stats[0].tx_fifo_errors;
4471 spin_unlock(&cp->stat_lock[0]);
4473 for (i = 0; i < N_TX_RINGS; i++) {
4474 spin_lock(&cp->stat_lock[i]);
4475 stats[N_TX_RINGS].rx_length_errors +=
4476 stats[i].rx_length_errors;
4477 stats[N_TX_RINGS].rx_crc_errors += stats[i].rx_crc_errors;
4478 stats[N_TX_RINGS].rx_packets += stats[i].rx_packets;
4479 stats[N_TX_RINGS].tx_packets += stats[i].tx_packets;
4480 stats[N_TX_RINGS].rx_bytes += stats[i].rx_bytes;
4481 stats[N_TX_RINGS].tx_bytes += stats[i].tx_bytes;
4482 stats[N_TX_RINGS].rx_errors += stats[i].rx_errors;
4483 stats[N_TX_RINGS].tx_errors += stats[i].tx_errors;
4484 stats[N_TX_RINGS].rx_dropped += stats[i].rx_dropped;
4485 stats[N_TX_RINGS].tx_dropped += stats[i].tx_dropped;
4486 memset(stats + i, 0, sizeof(struct net_device_stats));
4487 spin_unlock(&cp->stat_lock[i]);
4489 spin_unlock_irqrestore(&cp->stat_lock[N_TX_RINGS], flags);
4490 return stats + N_TX_RINGS;
4494 static void cas_set_multicast(struct net_device *dev)
4496 struct cas *cp = netdev_priv(dev);
4497 u32 rxcfg, rxcfg_new;
4498 unsigned long flags;
4499 int limit = STOP_TRIES;
4501 if (!cp->hw_running)
4504 spin_lock_irqsave(&cp->lock, flags);
4505 rxcfg = readl(cp->regs + REG_MAC_RX_CFG);
4507 /* disable RX MAC and wait for completion */
4508 writel(rxcfg & ~MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG);
4509 while (readl(cp->regs + REG_MAC_RX_CFG) & MAC_RX_CFG_EN) {
4515 /* disable hash filter and wait for completion */
4517 rxcfg &= ~(MAC_RX_CFG_PROMISC_EN | MAC_RX_CFG_HASH_FILTER_EN);
4518 writel(rxcfg & ~MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG);
4519 while (readl(cp->regs + REG_MAC_RX_CFG) & MAC_RX_CFG_HASH_FILTER_EN) {
4525 /* program hash filters */
4526 cp->mac_rx_cfg = rxcfg_new = cas_setup_multicast(cp);
4528 writel(rxcfg, cp->regs + REG_MAC_RX_CFG);
4529 spin_unlock_irqrestore(&cp->lock, flags);
4532 static void cas_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
4534 struct cas *cp = netdev_priv(dev);
4535 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
4536 strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
4537 strlcpy(info->bus_info, pci_name(cp->pdev), sizeof(info->bus_info));
4538 info->regdump_len = cp->casreg_len < CAS_MAX_REGS ?
4539 cp->casreg_len : CAS_MAX_REGS;
4540 info->n_stats = CAS_NUM_STAT_KEYS;
4543 static int cas_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
4545 struct cas *cp = netdev_priv(dev);
4547 int full_duplex, speed, pause;
4548 unsigned long flags;
4549 enum link_state linkstate = link_up;
4551 cmd->advertising = 0;
4552 cmd->supported = SUPPORTED_Autoneg;
4553 if (cp->cas_flags & CAS_FLAG_1000MB_CAP) {
4554 cmd->supported |= SUPPORTED_1000baseT_Full;
4555 cmd->advertising |= ADVERTISED_1000baseT_Full;
4558 /* Record PHY settings if HW is on. */
4559 spin_lock_irqsave(&cp->lock, flags);
4561 linkstate = cp->lstate;
4562 if (CAS_PHY_MII(cp->phy_type)) {
4563 cmd->port = PORT_MII;
4564 cmd->transceiver = (cp->cas_flags & CAS_FLAG_SATURN) ?
4565 XCVR_INTERNAL : XCVR_EXTERNAL;
4566 cmd->phy_address = cp->phy_addr;
4567 cmd->advertising |= ADVERTISED_TP | ADVERTISED_MII |
4568 ADVERTISED_10baseT_Half |
4569 ADVERTISED_10baseT_Full |
4570 ADVERTISED_100baseT_Half |
4571 ADVERTISED_100baseT_Full;
4574 (SUPPORTED_10baseT_Half |
4575 SUPPORTED_10baseT_Full |
4576 SUPPORTED_100baseT_Half |
4577 SUPPORTED_100baseT_Full |
4578 SUPPORTED_TP | SUPPORTED_MII);
4580 if (cp->hw_running) {
4581 cas_mif_poll(cp, 0);
4582 bmcr = cas_phy_read(cp, MII_BMCR);
4583 cas_read_mii_link_mode(cp, &full_duplex,
4585 cas_mif_poll(cp, 1);
4589 cmd->port = PORT_FIBRE;
4590 cmd->transceiver = XCVR_INTERNAL;
4591 cmd->phy_address = 0;
4592 cmd->supported |= SUPPORTED_FIBRE;
4593 cmd->advertising |= ADVERTISED_FIBRE;
4595 if (cp->hw_running) {
4596 /* pcs uses the same bits as mii */
4597 bmcr = readl(cp->regs + REG_PCS_MII_CTRL);
4598 cas_read_pcs_link_mode(cp, &full_duplex,
4602 spin_unlock_irqrestore(&cp->lock, flags);
4604 if (bmcr & BMCR_ANENABLE) {
4605 cmd->advertising |= ADVERTISED_Autoneg;
4606 cmd->autoneg = AUTONEG_ENABLE;
4607 ethtool_cmd_speed_set(cmd, ((speed == 10) ?
4610 SPEED_1000 : SPEED_100)));
4611 cmd->duplex = full_duplex ? DUPLEX_FULL : DUPLEX_HALF;
4613 cmd->autoneg = AUTONEG_DISABLE;
4614 ethtool_cmd_speed_set(cmd, ((bmcr & CAS_BMCR_SPEED1000) ?
4616 ((bmcr & BMCR_SPEED100) ?
4617 SPEED_100 : SPEED_10)));
4619 (bmcr & BMCR_FULLDPLX) ?
4620 DUPLEX_FULL : DUPLEX_HALF;
4622 if (linkstate != link_up) {
4623 /* Force these to "unknown" if the link is not up and
4624 * autonogotiation in enabled. We can set the link
4625 * speed to 0, but not cmd->duplex,
4626 * because its legal values are 0 and 1. Ethtool will
4627 * print the value reported in parentheses after the
4628 * word "Unknown" for unrecognized values.
4630 * If in forced mode, we report the speed and duplex
4631 * settings that we configured.
4633 if (cp->link_cntl & BMCR_ANENABLE) {
4634 ethtool_cmd_speed_set(cmd, 0);
4637 ethtool_cmd_speed_set(cmd, SPEED_10);
4638 if (cp->link_cntl & BMCR_SPEED100) {
4639 ethtool_cmd_speed_set(cmd, SPEED_100);
4640 } else if (cp->link_cntl & CAS_BMCR_SPEED1000) {
4641 ethtool_cmd_speed_set(cmd, SPEED_1000);
4643 cmd->duplex = (cp->link_cntl & BMCR_FULLDPLX)?
4644 DUPLEX_FULL : DUPLEX_HALF;
4650 static int cas_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
4652 struct cas *cp = netdev_priv(dev);
4653 unsigned long flags;
4654 u32 speed = ethtool_cmd_speed(cmd);
4656 /* Verify the settings we care about. */
4657 if (cmd->autoneg != AUTONEG_ENABLE &&
4658 cmd->autoneg != AUTONEG_DISABLE)
4661 if (cmd->autoneg == AUTONEG_DISABLE &&
4662 ((speed != SPEED_1000 &&
4663 speed != SPEED_100 &&
4664 speed != SPEED_10) ||
4665 (cmd->duplex != DUPLEX_HALF &&
4666 cmd->duplex != DUPLEX_FULL)))
4669 /* Apply settings and restart link process. */
4670 spin_lock_irqsave(&cp->lock, flags);
4671 cas_begin_auto_negotiation(cp, cmd);
4672 spin_unlock_irqrestore(&cp->lock, flags);
4676 static int cas_nway_reset(struct net_device *dev)
4678 struct cas *cp = netdev_priv(dev);
4679 unsigned long flags;
4681 if ((cp->link_cntl & BMCR_ANENABLE) == 0)
4684 /* Restart link process. */
4685 spin_lock_irqsave(&cp->lock, flags);
4686 cas_begin_auto_negotiation(cp, NULL);
4687 spin_unlock_irqrestore(&cp->lock, flags);
4692 static u32 cas_get_link(struct net_device *dev)
4694 struct cas *cp = netdev_priv(dev);
4695 return cp->lstate == link_up;
4698 static u32 cas_get_msglevel(struct net_device *dev)
4700 struct cas *cp = netdev_priv(dev);
4701 return cp->msg_enable;
4704 static void cas_set_msglevel(struct net_device *dev, u32 value)
4706 struct cas *cp = netdev_priv(dev);
4707 cp->msg_enable = value;
4710 static int cas_get_regs_len(struct net_device *dev)
4712 struct cas *cp = netdev_priv(dev);
4713 return cp->casreg_len < CAS_MAX_REGS ? cp->casreg_len: CAS_MAX_REGS;
4716 static void cas_get_regs(struct net_device *dev, struct ethtool_regs *regs,
4719 struct cas *cp = netdev_priv(dev);
4721 /* cas_read_regs handles locks (cp->lock). */
4722 cas_read_regs(cp, p, regs->len / sizeof(u32));
4725 static int cas_get_sset_count(struct net_device *dev, int sset)
4729 return CAS_NUM_STAT_KEYS;
4735 static void cas_get_strings(struct net_device *dev, u32 stringset, u8 *data)
4737 memcpy(data, ðtool_cassini_statnames,
4738 CAS_NUM_STAT_KEYS * ETH_GSTRING_LEN);
4741 static void cas_get_ethtool_stats(struct net_device *dev,
4742 struct ethtool_stats *estats, u64 *data)
4744 struct cas *cp = netdev_priv(dev);
4745 struct net_device_stats *stats = cas_get_stats(cp->dev);
4747 data[i++] = stats->collisions;
4748 data[i++] = stats->rx_bytes;
4749 data[i++] = stats->rx_crc_errors;
4750 data[i++] = stats->rx_dropped;
4751 data[i++] = stats->rx_errors;
4752 data[i++] = stats->rx_fifo_errors;
4753 data[i++] = stats->rx_frame_errors;
4754 data[i++] = stats->rx_length_errors;
4755 data[i++] = stats->rx_over_errors;
4756 data[i++] = stats->rx_packets;
4757 data[i++] = stats->tx_aborted_errors;
4758 data[i++] = stats->tx_bytes;
4759 data[i++] = stats->tx_dropped;
4760 data[i++] = stats->tx_errors;
4761 data[i++] = stats->tx_fifo_errors;
4762 data[i++] = stats->tx_packets;
4763 BUG_ON(i != CAS_NUM_STAT_KEYS);
4766 static const struct ethtool_ops cas_ethtool_ops = {
4767 .get_drvinfo = cas_get_drvinfo,
4768 .get_settings = cas_get_settings,
4769 .set_settings = cas_set_settings,
4770 .nway_reset = cas_nway_reset,
4771 .get_link = cas_get_link,
4772 .get_msglevel = cas_get_msglevel,
4773 .set_msglevel = cas_set_msglevel,
4774 .get_regs_len = cas_get_regs_len,
4775 .get_regs = cas_get_regs,
4776 .get_sset_count = cas_get_sset_count,
4777 .get_strings = cas_get_strings,
4778 .get_ethtool_stats = cas_get_ethtool_stats,
4781 static int cas_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4783 struct cas *cp = netdev_priv(dev);
4784 struct mii_ioctl_data *data = if_mii(ifr);
4785 unsigned long flags;
4786 int rc = -EOPNOTSUPP;
4788 /* Hold the PM mutex while doing ioctl's or we may collide
4789 * with open/close and power management and oops.
4791 mutex_lock(&cp->pm_mutex);
4793 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
4794 data->phy_id = cp->phy_addr;
4795 /* Fallthrough... */
4797 case SIOCGMIIREG: /* Read MII PHY register. */
4798 spin_lock_irqsave(&cp->lock, flags);
4799 cas_mif_poll(cp, 0);
4800 data->val_out = cas_phy_read(cp, data->reg_num & 0x1f);
4801 cas_mif_poll(cp, 1);
4802 spin_unlock_irqrestore(&cp->lock, flags);
4806 case SIOCSMIIREG: /* Write MII PHY register. */
4807 spin_lock_irqsave(&cp->lock, flags);
4808 cas_mif_poll(cp, 0);
4809 rc = cas_phy_write(cp, data->reg_num & 0x1f, data->val_in);
4810 cas_mif_poll(cp, 1);
4811 spin_unlock_irqrestore(&cp->lock, flags);
4817 mutex_unlock(&cp->pm_mutex);
4821 /* When this chip sits underneath an Intel 31154 bridge, it is the
4822 * only subordinate device and we can tweak the bridge settings to
4823 * reflect that fact.
4825 static void __devinit cas_program_bridge(struct pci_dev *cas_pdev)
4827 struct pci_dev *pdev = cas_pdev->bus->self;
4833 if (pdev->vendor != 0x8086 || pdev->device != 0x537c)
4836 /* Clear bit 10 (Bus Parking Control) in the Secondary
4837 * Arbiter Control/Status Register which lives at offset
4838 * 0x41. Using a 32-bit word read/modify/write at 0x40
4839 * is much simpler so that's how we do this.
4841 pci_read_config_dword(pdev, 0x40, &val);
4843 pci_write_config_dword(pdev, 0x40, val);
4845 /* Max out the Multi-Transaction Timer settings since
4846 * Cassini is the only device present.
4848 * The register is 16-bit and lives at 0x50. When the
4849 * settings are enabled, it extends the GRANT# signal
4850 * for a requestor after a transaction is complete. This
4851 * allows the next request to run without first needing
4852 * to negotiate the GRANT# signal back.
4854 * Bits 12:10 define the grant duration:
4862 * All other values are illegal.
4864 * Bits 09:00 define which REQ/GNT signal pairs get the
4865 * GRANT# signal treatment. We set them all.
4867 pci_write_config_word(pdev, 0x50, (5 << 10) | 0x3ff);
4869 /* The Read Prefecth Policy register is 16-bit and sits at
4870 * offset 0x52. It enables a "smart" pre-fetch policy. We
4871 * enable it and max out all of the settings since only one
4872 * device is sitting underneath and thus bandwidth sharing is
4875 * The register has several 3 bit fields, which indicates a
4876 * multiplier applied to the base amount of prefetching the
4877 * chip would do. These fields are at:
4879 * 15:13 --- ReRead Primary Bus
4880 * 12:10 --- FirstRead Primary Bus
4881 * 09:07 --- ReRead Secondary Bus
4882 * 06:04 --- FirstRead Secondary Bus
4884 * Bits 03:00 control which REQ/GNT pairs the prefetch settings
4885 * get enabled on. Bit 3 is a grouped enabler which controls
4886 * all of the REQ/GNT pairs from [8:3]. Bits 2 to 0 control
4887 * the individual REQ/GNT pairs [2:0].
4889 pci_write_config_word(pdev, 0x52,
4896 /* Force cacheline size to 0x8 */
4897 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
4899 /* Force latency timer to maximum setting so Cassini can
4900 * sit on the bus as long as it likes.
4902 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xff);
4905 static const struct net_device_ops cas_netdev_ops = {
4906 .ndo_open = cas_open,
4907 .ndo_stop = cas_close,
4908 .ndo_start_xmit = cas_start_xmit,
4909 .ndo_get_stats = cas_get_stats,
4910 .ndo_set_rx_mode = cas_set_multicast,
4911 .ndo_do_ioctl = cas_ioctl,
4912 .ndo_tx_timeout = cas_tx_timeout,
4913 .ndo_change_mtu = cas_change_mtu,
4914 .ndo_set_mac_address = eth_mac_addr,
4915 .ndo_validate_addr = eth_validate_addr,
4916 #ifdef CONFIG_NET_POLL_CONTROLLER
4917 .ndo_poll_controller = cas_netpoll,
4921 static int __devinit cas_init_one(struct pci_dev *pdev,
4922 const struct pci_device_id *ent)
4924 static int cas_version_printed = 0;
4925 unsigned long casreg_len;
4926 struct net_device *dev;
4928 int i, err, pci_using_dac;
4930 u8 orig_cacheline_size = 0, cas_cacheline_size = 0;
4932 if (cas_version_printed++ == 0)
4933 pr_info("%s", version);
4935 err = pci_enable_device(pdev);
4937 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
4941 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
4942 dev_err(&pdev->dev, "Cannot find proper PCI device "
4943 "base address, aborting\n");
4945 goto err_out_disable_pdev;
4948 dev = alloc_etherdev(sizeof(*cp));
4950 dev_err(&pdev->dev, "Etherdev alloc failed, aborting\n");
4952 goto err_out_disable_pdev;
4954 SET_NETDEV_DEV(dev, &pdev->dev);
4956 err = pci_request_regions(pdev, dev->name);
4958 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
4959 goto err_out_free_netdev;
4961 pci_set_master(pdev);
4963 /* we must always turn on parity response or else parity
4964 * doesn't get generated properly. disable SERR/PERR as well.
4965 * in addition, we want to turn MWI on.
4967 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4968 pci_cmd &= ~PCI_COMMAND_SERR;
4969 pci_cmd |= PCI_COMMAND_PARITY;
4970 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
4971 if (pci_try_set_mwi(pdev))
4972 pr_warning("Could not enable MWI for %s\n", pci_name(pdev));
4974 cas_program_bridge(pdev);
4977 * On some architectures, the default cache line size set
4978 * by pci_try_set_mwi reduces perforamnce. We have to increase
4979 * it for this case. To start, we'll print some configuration
4983 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE,
4984 &orig_cacheline_size);
4985 if (orig_cacheline_size < CAS_PREF_CACHELINE_SIZE) {
4986 cas_cacheline_size =
4987 (CAS_PREF_CACHELINE_SIZE < SMP_CACHE_BYTES) ?
4988 CAS_PREF_CACHELINE_SIZE : SMP_CACHE_BYTES;
4989 if (pci_write_config_byte(pdev,
4990 PCI_CACHE_LINE_SIZE,
4991 cas_cacheline_size)) {
4992 dev_err(&pdev->dev, "Could not set PCI cache "
4994 goto err_write_cacheline;
5000 /* Configure DMA attributes. */
5001 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
5003 err = pci_set_consistent_dma_mask(pdev,
5006 dev_err(&pdev->dev, "Unable to obtain 64-bit DMA "
5007 "for consistent allocations\n");
5008 goto err_out_free_res;
5012 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
5014 dev_err(&pdev->dev, "No usable DMA configuration, "
5016 goto err_out_free_res;
5021 casreg_len = pci_resource_len(pdev, 0);
5023 cp = netdev_priv(dev);
5026 /* A value of 0 indicates we never explicitly set it */
5027 cp->orig_cacheline_size = cas_cacheline_size ? orig_cacheline_size: 0;
5030 cp->msg_enable = (cassini_debug < 0) ? CAS_DEF_MSG_ENABLE :
5033 #if defined(CONFIG_SPARC)
5034 cp->of_node = pci_device_to_OF_node(pdev);
5037 cp->link_transition = LINK_TRANSITION_UNKNOWN;
5038 cp->link_transition_jiffies_valid = 0;
5040 spin_lock_init(&cp->lock);
5041 spin_lock_init(&cp->rx_inuse_lock);
5042 spin_lock_init(&cp->rx_spare_lock);
5043 for (i = 0; i < N_TX_RINGS; i++) {
5044 spin_lock_init(&cp->stat_lock[i]);
5045 spin_lock_init(&cp->tx_lock[i]);
5047 spin_lock_init(&cp->stat_lock[N_TX_RINGS]);
5048 mutex_init(&cp->pm_mutex);
5050 init_timer(&cp->link_timer);
5051 cp->link_timer.function = cas_link_timer;
5052 cp->link_timer.data = (unsigned long) cp;
5055 /* Just in case the implementation of atomic operations
5056 * change so that an explicit initialization is necessary.
5058 atomic_set(&cp->reset_task_pending, 0);
5059 atomic_set(&cp->reset_task_pending_all, 0);
5060 atomic_set(&cp->reset_task_pending_spare, 0);
5061 atomic_set(&cp->reset_task_pending_mtu, 0);
5063 INIT_WORK(&cp->reset_task, cas_reset_task);
5065 /* Default link parameters */
5066 if (link_mode >= 0 && link_mode < 6)
5067 cp->link_cntl = link_modes[link_mode];
5069 cp->link_cntl = BMCR_ANENABLE;
5070 cp->lstate = link_down;
5071 cp->link_transition = LINK_TRANSITION_LINK_DOWN;
5072 netif_carrier_off(cp->dev);
5073 cp->timer_ticks = 0;
5075 /* give us access to cassini registers */
5076 cp->regs = pci_iomap(pdev, 0, casreg_len);
5078 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
5079 goto err_out_free_res;
5081 cp->casreg_len = casreg_len;
5083 pci_save_state(pdev);
5084 cas_check_pci_invariants(cp);
5087 if (cas_check_invariants(cp))
5088 goto err_out_iounmap;
5089 if (cp->cas_flags & CAS_FLAG_SATURN)
5090 if (cas_saturn_firmware_init(cp))
5091 goto err_out_iounmap;
5093 cp->init_block = (struct cas_init_block *)
5094 pci_alloc_consistent(pdev, sizeof(struct cas_init_block),
5096 if (!cp->init_block) {
5097 dev_err(&pdev->dev, "Cannot allocate init block, aborting\n");
5098 goto err_out_iounmap;
5101 for (i = 0; i < N_TX_RINGS; i++)
5102 cp->init_txds[i] = cp->init_block->txds[i];
5104 for (i = 0; i < N_RX_DESC_RINGS; i++)
5105 cp->init_rxds[i] = cp->init_block->rxds[i];
5107 for (i = 0; i < N_RX_COMP_RINGS; i++)
5108 cp->init_rxcs[i] = cp->init_block->rxcs[i];
5110 for (i = 0; i < N_RX_FLOWS; i++)
5111 skb_queue_head_init(&cp->rx_flows[i]);
5113 dev->netdev_ops = &cas_netdev_ops;
5114 dev->ethtool_ops = &cas_ethtool_ops;
5115 dev->watchdog_timeo = CAS_TX_TIMEOUT;
5118 netif_napi_add(dev, &cp->napi, cas_poll, 64);
5120 dev->irq = pdev->irq;
5123 /* Cassini features. */
5124 if ((cp->cas_flags & CAS_FLAG_NO_HW_CSUM) == 0)
5125 dev->features |= NETIF_F_HW_CSUM | NETIF_F_SG;
5128 dev->features |= NETIF_F_HIGHDMA;
5130 if (register_netdev(dev)) {
5131 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
5132 goto err_out_free_consistent;
5135 i = readl(cp->regs + REG_BIM_CFG);
5136 netdev_info(dev, "Sun Cassini%s (%sbit/%sMHz PCI/%s) Ethernet[%d] %pM\n",
5137 (cp->cas_flags & CAS_FLAG_REG_PLUS) ? "+" : "",
5138 (i & BIM_CFG_32BIT) ? "32" : "64",
5139 (i & BIM_CFG_66MHZ) ? "66" : "33",
5140 (cp->phy_type == CAS_PHY_SERDES) ? "Fi" : "Cu", pdev->irq,
5143 pci_set_drvdata(pdev, dev);
5145 cas_entropy_reset(cp);
5147 cas_begin_auto_negotiation(cp, NULL);
5150 err_out_free_consistent:
5151 pci_free_consistent(pdev, sizeof(struct cas_init_block),
5152 cp->init_block, cp->block_dvma);
5155 mutex_lock(&cp->pm_mutex);
5158 mutex_unlock(&cp->pm_mutex);
5160 pci_iounmap(pdev, cp->regs);
5164 pci_release_regions(pdev);
5166 err_write_cacheline:
5167 /* Try to restore it in case the error occurred after we
5170 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, orig_cacheline_size);
5172 err_out_free_netdev:
5175 err_out_disable_pdev:
5176 pci_disable_device(pdev);
5177 pci_set_drvdata(pdev, NULL);
5181 static void __devexit cas_remove_one(struct pci_dev *pdev)
5183 struct net_device *dev = pci_get_drvdata(pdev);
5188 cp = netdev_priv(dev);
5189 unregister_netdev(dev);
5194 mutex_lock(&cp->pm_mutex);
5195 cancel_work_sync(&cp->reset_task);
5198 mutex_unlock(&cp->pm_mutex);
5201 if (cp->orig_cacheline_size) {
5202 /* Restore the cache line size if we had modified
5205 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE,
5206 cp->orig_cacheline_size);
5209 pci_free_consistent(pdev, sizeof(struct cas_init_block),
5210 cp->init_block, cp->block_dvma);
5211 pci_iounmap(pdev, cp->regs);
5213 pci_release_regions(pdev);
5214 pci_disable_device(pdev);
5215 pci_set_drvdata(pdev, NULL);
5219 static int cas_suspend(struct pci_dev *pdev, pm_message_t state)
5221 struct net_device *dev = pci_get_drvdata(pdev);
5222 struct cas *cp = netdev_priv(dev);
5223 unsigned long flags;
5225 mutex_lock(&cp->pm_mutex);
5227 /* If the driver is opened, we stop the DMA */
5229 netif_device_detach(dev);
5231 cas_lock_all_save(cp, flags);
5233 /* We can set the second arg of cas_reset to 0
5234 * because on resume, we'll call cas_init_hw with
5235 * its second arg set so that autonegotiation is
5239 cas_clean_rings(cp);
5240 cas_unlock_all_restore(cp, flags);
5245 mutex_unlock(&cp->pm_mutex);
5250 static int cas_resume(struct pci_dev *pdev)
5252 struct net_device *dev = pci_get_drvdata(pdev);
5253 struct cas *cp = netdev_priv(dev);
5255 netdev_info(dev, "resuming\n");
5257 mutex_lock(&cp->pm_mutex);
5260 unsigned long flags;
5261 cas_lock_all_save(cp, flags);
5264 cas_clean_rings(cp);
5266 cas_unlock_all_restore(cp, flags);
5268 netif_device_attach(dev);
5270 mutex_unlock(&cp->pm_mutex);
5273 #endif /* CONFIG_PM */
5275 static struct pci_driver cas_driver = {
5276 .name = DRV_MODULE_NAME,
5277 .id_table = cas_pci_tbl,
5278 .probe = cas_init_one,
5279 .remove = __devexit_p(cas_remove_one),
5281 .suspend = cas_suspend,
5282 .resume = cas_resume
5286 static int __init cas_init(void)
5288 if (linkdown_timeout > 0)
5289 link_transition_timeout = linkdown_timeout * HZ;
5291 link_transition_timeout = 0;
5293 return pci_register_driver(&cas_driver);
5296 static void __exit cas_cleanup(void)
5298 pci_unregister_driver(&cas_driver);
5301 module_init(cas_init);
5302 module_exit(cas_cleanup);