2 * Driver for Xilinx TEMAC Ethernet device
4 * Copyright (c) 2008 Nissin Systems Co., Ltd., Yoshio Kashiwagi
5 * Copyright (c) 2005-2008 DLA Systems, David H. Lynch Jr. <dhlii@dlasys.net>
6 * Copyright (c) 2008-2009 Secret Lab Technologies Ltd.
8 * This is a driver for the Xilinx ll_temac ipcore which is often used
9 * in the Virtex and Spartan series of chips.
12 * - The ll_temac hardware uses indirect access for many of the TEMAC
13 * registers, include the MDIO bus. However, indirect access to MDIO
14 * registers take considerably more clock cycles than to TEMAC registers.
15 * MDIO accesses are long, so threads doing them should probably sleep
16 * rather than busywait. However, since only one indirect access can be
17 * in progress at any given time, that means that *all* indirect accesses
18 * could end up sleeping (to wait for an MDIO access to complete).
19 * Fortunately none of the indirect accesses are on the 'hot' path for tx
20 * or rx, so this should be okay.
23 * - Factor out locallink DMA code into separate driver
24 * - Fix multicast assignment.
25 * - Fix support for hardware checksumming.
26 * - Testing. Lots and lots of testing.
30 #include <linux/delay.h>
31 #include <linux/etherdevice.h>
32 #include <linux/mii.h>
33 #include <linux/module.h>
34 #include <linux/mutex.h>
35 #include <linux/netdevice.h>
37 #include <linux/of_device.h>
38 #include <linux/of_irq.h>
39 #include <linux/of_mdio.h>
40 #include <linux/of_platform.h>
41 #include <linux/of_address.h>
42 #include <linux/skbuff.h>
43 #include <linux/spinlock.h>
44 #include <linux/tcp.h> /* needed for sizeof(tcphdr) */
45 #include <linux/udp.h> /* needed for sizeof(udphdr) */
46 #include <linux/phy.h>
50 #include <linux/slab.h>
51 #include <linux/interrupt.h>
52 #include <linux/dma-mapping.h>
59 /* ---------------------------------------------------------------------
60 * Low level register access functions
63 u32 temac_ior(struct temac_local *lp, int offset)
65 return in_be32(lp->regs + offset);
68 void temac_iow(struct temac_local *lp, int offset, u32 value)
70 out_be32(lp->regs + offset, value);
73 int temac_indirect_busywait(struct temac_local *lp)
75 unsigned long end = jiffies + 2;
77 while (!(temac_ior(lp, XTE_RDY0_OFFSET) & XTE_RDY0_HARD_ACS_RDY_MASK)) {
78 if (time_before_eq(end, jiffies)) {
90 * lp->indirect_mutex must be held when calling this function
92 u32 temac_indirect_in32(struct temac_local *lp, int reg)
96 if (temac_indirect_busywait(lp))
98 temac_iow(lp, XTE_CTL0_OFFSET, reg);
99 if (temac_indirect_busywait(lp))
101 val = temac_ior(lp, XTE_LSW0_OFFSET);
107 * temac_indirect_out32
109 * lp->indirect_mutex must be held when calling this function
111 void temac_indirect_out32(struct temac_local *lp, int reg, u32 value)
113 if (temac_indirect_busywait(lp))
115 temac_iow(lp, XTE_LSW0_OFFSET, value);
116 temac_iow(lp, XTE_CTL0_OFFSET, CNTLREG_WRITE_ENABLE_MASK | reg);
117 temac_indirect_busywait(lp);
121 * temac_dma_in32 - Memory mapped DMA read, this function expects a
122 * register input that is based on DCR word addresses which
123 * are then converted to memory mapped byte addresses
125 static u32 temac_dma_in32(struct temac_local *lp, int reg)
127 return in_be32(lp->sdma_regs + (reg << 2));
131 * temac_dma_out32 - Memory mapped DMA read, this function expects a
132 * register input that is based on DCR word addresses which
133 * are then converted to memory mapped byte addresses
135 static void temac_dma_out32(struct temac_local *lp, int reg, u32 value)
137 out_be32(lp->sdma_regs + (reg << 2), value);
140 /* DMA register access functions can be DCR based or memory mapped.
141 * The PowerPC 440 is DCR based, the PowerPC 405 and MicroBlaze are both
144 #ifdef CONFIG_PPC_DCR
147 * temac_dma_dcr_in32 - DCR based DMA read
149 static u32 temac_dma_dcr_in(struct temac_local *lp, int reg)
151 return dcr_read(lp->sdma_dcrs, reg);
155 * temac_dma_dcr_out32 - DCR based DMA write
157 static void temac_dma_dcr_out(struct temac_local *lp, int reg, u32 value)
159 dcr_write(lp->sdma_dcrs, reg, value);
163 * temac_dcr_setup - If the DMA is DCR based, then setup the address and
166 static int temac_dcr_setup(struct temac_local *lp, struct platform_device *op,
167 struct device_node *np)
171 /* setup the dcr address mapping if it's in the device tree */
173 dcrs = dcr_resource_start(np, 0);
175 lp->sdma_dcrs = dcr_map(np, dcrs, dcr_resource_len(np, 0));
176 lp->dma_in = temac_dma_dcr_in;
177 lp->dma_out = temac_dma_dcr_out;
178 dev_dbg(&op->dev, "DCR base: %x\n", dcrs);
181 /* no DCR in the device tree, indicate a failure */
188 * temac_dcr_setup - This is a stub for when DCR is not supported,
189 * such as with MicroBlaze
191 static int temac_dcr_setup(struct temac_local *lp, struct platform_device *op,
192 struct device_node *np)
200 * temac_dma_bd_release - Release buffer descriptor rings
202 static void temac_dma_bd_release(struct net_device *ndev)
204 struct temac_local *lp = netdev_priv(ndev);
207 /* Reset Local Link (DMA) */
208 lp->dma_out(lp, DMA_CONTROL_REG, DMA_CONTROL_RST);
210 for (i = 0; i < RX_BD_NUM; i++) {
214 dma_unmap_single(ndev->dev.parent, lp->rx_bd_v[i].phys,
215 XTE_MAX_JUMBO_FRAME_SIZE, DMA_FROM_DEVICE);
216 dev_kfree_skb(lp->rx_skb[i]);
220 dma_free_coherent(ndev->dev.parent,
221 sizeof(*lp->rx_bd_v) * RX_BD_NUM,
222 lp->rx_bd_v, lp->rx_bd_p);
224 dma_free_coherent(ndev->dev.parent,
225 sizeof(*lp->tx_bd_v) * TX_BD_NUM,
226 lp->tx_bd_v, lp->tx_bd_p);
231 * temac_dma_bd_init - Setup buffer descriptor rings
233 static int temac_dma_bd_init(struct net_device *ndev)
235 struct temac_local *lp = netdev_priv(ndev);
239 lp->rx_skb = kcalloc(RX_BD_NUM, sizeof(*lp->rx_skb), GFP_KERNEL);
243 /* allocate the tx and rx ring buffer descriptors. */
244 /* returns a virtual address and a physical address. */
245 lp->tx_bd_v = dma_zalloc_coherent(ndev->dev.parent,
246 sizeof(*lp->tx_bd_v) * TX_BD_NUM,
247 &lp->tx_bd_p, GFP_KERNEL);
251 lp->rx_bd_v = dma_zalloc_coherent(ndev->dev.parent,
252 sizeof(*lp->rx_bd_v) * RX_BD_NUM,
253 &lp->rx_bd_p, GFP_KERNEL);
257 for (i = 0; i < TX_BD_NUM; i++) {
258 lp->tx_bd_v[i].next = lp->tx_bd_p +
259 sizeof(*lp->tx_bd_v) * ((i + 1) % TX_BD_NUM);
262 for (i = 0; i < RX_BD_NUM; i++) {
263 lp->rx_bd_v[i].next = lp->rx_bd_p +
264 sizeof(*lp->rx_bd_v) * ((i + 1) % RX_BD_NUM);
266 skb = netdev_alloc_skb_ip_align(ndev,
267 XTE_MAX_JUMBO_FRAME_SIZE);
272 /* returns physical address of skb->data */
273 lp->rx_bd_v[i].phys = dma_map_single(ndev->dev.parent,
275 XTE_MAX_JUMBO_FRAME_SIZE,
277 lp->rx_bd_v[i].len = XTE_MAX_JUMBO_FRAME_SIZE;
278 lp->rx_bd_v[i].app0 = STS_CTRL_APP0_IRQONEND;
281 lp->dma_out(lp, TX_CHNL_CTRL, 0x10220400 |
283 CHNL_CTRL_IRQ_DLY_EN |
284 CHNL_CTRL_IRQ_COAL_EN);
287 lp->dma_out(lp, RX_CHNL_CTRL, 0xff070000 |
289 CHNL_CTRL_IRQ_DLY_EN |
290 CHNL_CTRL_IRQ_COAL_EN |
294 lp->dma_out(lp, RX_CURDESC_PTR, lp->rx_bd_p);
295 lp->dma_out(lp, RX_TAILDESC_PTR,
296 lp->rx_bd_p + (sizeof(*lp->rx_bd_v) * (RX_BD_NUM - 1)));
297 lp->dma_out(lp, TX_CURDESC_PTR, lp->tx_bd_p);
299 /* Init descriptor indexes */
308 temac_dma_bd_release(ndev);
312 /* ---------------------------------------------------------------------
316 static void temac_do_set_mac_address(struct net_device *ndev)
318 struct temac_local *lp = netdev_priv(ndev);
320 /* set up unicast MAC address filter set its mac address */
321 mutex_lock(&lp->indirect_mutex);
322 temac_indirect_out32(lp, XTE_UAW0_OFFSET,
323 (ndev->dev_addr[0]) |
324 (ndev->dev_addr[1] << 8) |
325 (ndev->dev_addr[2] << 16) |
326 (ndev->dev_addr[3] << 24));
327 /* There are reserved bits in EUAW1
328 * so don't affect them Set MAC bits [47:32] in EUAW1 */
329 temac_indirect_out32(lp, XTE_UAW1_OFFSET,
330 (ndev->dev_addr[4] & 0x000000ff) |
331 (ndev->dev_addr[5] << 8));
332 mutex_unlock(&lp->indirect_mutex);
335 static int temac_init_mac_address(struct net_device *ndev, void *address)
337 memcpy(ndev->dev_addr, address, ETH_ALEN);
338 if (!is_valid_ether_addr(ndev->dev_addr))
339 eth_hw_addr_random(ndev);
340 temac_do_set_mac_address(ndev);
344 static int temac_set_mac_address(struct net_device *ndev, void *p)
346 struct sockaddr *addr = p;
348 if (!is_valid_ether_addr(addr->sa_data))
349 return -EADDRNOTAVAIL;
350 memcpy(ndev->dev_addr, addr->sa_data, ETH_ALEN);
351 temac_do_set_mac_address(ndev);
355 static void temac_set_multicast_list(struct net_device *ndev)
357 struct temac_local *lp = netdev_priv(ndev);
358 u32 multi_addr_msw, multi_addr_lsw, val;
361 mutex_lock(&lp->indirect_mutex);
362 if (ndev->flags & (IFF_ALLMULTI | IFF_PROMISC) ||
363 netdev_mc_count(ndev) > MULTICAST_CAM_TABLE_NUM) {
365 * We must make the kernel realise we had to move
366 * into promisc mode or we start all out war on
367 * the cable. If it was a promisc request the
368 * flag is already set. If not we assert it.
370 ndev->flags |= IFF_PROMISC;
371 temac_indirect_out32(lp, XTE_AFM_OFFSET, XTE_AFM_EPPRM_MASK);
372 dev_info(&ndev->dev, "Promiscuous mode enabled.\n");
373 } else if (!netdev_mc_empty(ndev)) {
374 struct netdev_hw_addr *ha;
377 netdev_for_each_mc_addr(ha, ndev) {
378 if (i >= MULTICAST_CAM_TABLE_NUM)
380 multi_addr_msw = ((ha->addr[3] << 24) |
381 (ha->addr[2] << 16) |
384 temac_indirect_out32(lp, XTE_MAW0_OFFSET,
386 multi_addr_lsw = ((ha->addr[5] << 8) |
387 (ha->addr[4]) | (i << 16));
388 temac_indirect_out32(lp, XTE_MAW1_OFFSET,
393 val = temac_indirect_in32(lp, XTE_AFM_OFFSET);
394 temac_indirect_out32(lp, XTE_AFM_OFFSET,
395 val & ~XTE_AFM_EPPRM_MASK);
396 temac_indirect_out32(lp, XTE_MAW0_OFFSET, 0);
397 temac_indirect_out32(lp, XTE_MAW1_OFFSET, 0);
398 dev_info(&ndev->dev, "Promiscuous mode disabled.\n");
400 mutex_unlock(&lp->indirect_mutex);
403 static struct temac_option {
409 } temac_options[] = {
410 /* Turn on jumbo packet support for both Rx and Tx */
412 .opt = XTE_OPTION_JUMBO,
413 .reg = XTE_TXC_OFFSET,
414 .m_or = XTE_TXC_TXJMBO_MASK,
417 .opt = XTE_OPTION_JUMBO,
418 .reg = XTE_RXC1_OFFSET,
419 .m_or =XTE_RXC1_RXJMBO_MASK,
421 /* Turn on VLAN packet support for both Rx and Tx */
423 .opt = XTE_OPTION_VLAN,
424 .reg = XTE_TXC_OFFSET,
425 .m_or =XTE_TXC_TXVLAN_MASK,
428 .opt = XTE_OPTION_VLAN,
429 .reg = XTE_RXC1_OFFSET,
430 .m_or =XTE_RXC1_RXVLAN_MASK,
432 /* Turn on FCS stripping on receive packets */
434 .opt = XTE_OPTION_FCS_STRIP,
435 .reg = XTE_RXC1_OFFSET,
436 .m_or =XTE_RXC1_RXFCS_MASK,
438 /* Turn on FCS insertion on transmit packets */
440 .opt = XTE_OPTION_FCS_INSERT,
441 .reg = XTE_TXC_OFFSET,
442 .m_or =XTE_TXC_TXFCS_MASK,
444 /* Turn on length/type field checking on receive packets */
446 .opt = XTE_OPTION_LENTYPE_ERR,
447 .reg = XTE_RXC1_OFFSET,
448 .m_or =XTE_RXC1_RXLT_MASK,
450 /* Turn on flow control */
452 .opt = XTE_OPTION_FLOW_CONTROL,
453 .reg = XTE_FCC_OFFSET,
454 .m_or =XTE_FCC_RXFLO_MASK,
456 /* Turn on flow control */
458 .opt = XTE_OPTION_FLOW_CONTROL,
459 .reg = XTE_FCC_OFFSET,
460 .m_or =XTE_FCC_TXFLO_MASK,
462 /* Turn on promiscuous frame filtering (all frames are received ) */
464 .opt = XTE_OPTION_PROMISC,
465 .reg = XTE_AFM_OFFSET,
466 .m_or =XTE_AFM_EPPRM_MASK,
468 /* Enable transmitter if not already enabled */
470 .opt = XTE_OPTION_TXEN,
471 .reg = XTE_TXC_OFFSET,
472 .m_or =XTE_TXC_TXEN_MASK,
474 /* Enable receiver? */
476 .opt = XTE_OPTION_RXEN,
477 .reg = XTE_RXC1_OFFSET,
478 .m_or =XTE_RXC1_RXEN_MASK,
486 static u32 temac_setoptions(struct net_device *ndev, u32 options)
488 struct temac_local *lp = netdev_priv(ndev);
489 struct temac_option *tp = &temac_options[0];
492 mutex_lock(&lp->indirect_mutex);
494 reg = temac_indirect_in32(lp, tp->reg) & ~tp->m_or;
495 if (options & tp->opt)
497 temac_indirect_out32(lp, tp->reg, reg);
500 lp->options |= options;
501 mutex_unlock(&lp->indirect_mutex);
506 /* Initialize temac */
507 static void temac_device_reset(struct net_device *ndev)
509 struct temac_local *lp = netdev_priv(ndev);
513 /* Perform a software reset */
515 /* 0x300 host enable bit ? */
516 /* reset PHY through control register ?:1 */
518 dev_dbg(&ndev->dev, "%s()\n", __func__);
520 mutex_lock(&lp->indirect_mutex);
521 /* Reset the receiver and wait for it to finish reset */
522 temac_indirect_out32(lp, XTE_RXC1_OFFSET, XTE_RXC1_RXRST_MASK);
524 while (temac_indirect_in32(lp, XTE_RXC1_OFFSET) & XTE_RXC1_RXRST_MASK) {
526 if (--timeout == 0) {
528 "temac_device_reset RX reset timeout!!\n");
533 /* Reset the transmitter and wait for it to finish reset */
534 temac_indirect_out32(lp, XTE_TXC_OFFSET, XTE_TXC_TXRST_MASK);
536 while (temac_indirect_in32(lp, XTE_TXC_OFFSET) & XTE_TXC_TXRST_MASK) {
538 if (--timeout == 0) {
540 "temac_device_reset TX reset timeout!!\n");
545 /* Disable the receiver */
546 val = temac_indirect_in32(lp, XTE_RXC1_OFFSET);
547 temac_indirect_out32(lp, XTE_RXC1_OFFSET, val & ~XTE_RXC1_RXEN_MASK);
549 /* Reset Local Link (DMA) */
550 lp->dma_out(lp, DMA_CONTROL_REG, DMA_CONTROL_RST);
552 while (lp->dma_in(lp, DMA_CONTROL_REG) & DMA_CONTROL_RST) {
554 if (--timeout == 0) {
556 "temac_device_reset DMA reset timeout!!\n");
560 lp->dma_out(lp, DMA_CONTROL_REG, DMA_TAIL_ENABLE);
562 if (temac_dma_bd_init(ndev)) {
564 "temac_device_reset descriptor allocation failed\n");
567 temac_indirect_out32(lp, XTE_RXC0_OFFSET, 0);
568 temac_indirect_out32(lp, XTE_RXC1_OFFSET, 0);
569 temac_indirect_out32(lp, XTE_TXC_OFFSET, 0);
570 temac_indirect_out32(lp, XTE_FCC_OFFSET, XTE_FCC_RXFLO_MASK);
572 mutex_unlock(&lp->indirect_mutex);
574 /* Sync default options with HW
575 * but leave receiver and transmitter disabled. */
576 temac_setoptions(ndev,
577 lp->options & ~(XTE_OPTION_TXEN | XTE_OPTION_RXEN));
579 temac_do_set_mac_address(ndev);
581 /* Set address filter table */
582 temac_set_multicast_list(ndev);
583 if (temac_setoptions(ndev, lp->options))
584 dev_err(&ndev->dev, "Error setting TEMAC options\n");
586 /* Init Driver variable */
587 ndev->trans_start = jiffies; /* prevent tx timeout */
590 static void temac_adjust_link(struct net_device *ndev)
592 struct temac_local *lp = netdev_priv(ndev);
593 struct phy_device *phy = lp->phy_dev;
597 /* hash together the state values to decide if something has changed */
598 link_state = phy->speed | (phy->duplex << 1) | phy->link;
600 mutex_lock(&lp->indirect_mutex);
601 if (lp->last_link != link_state) {
602 mii_speed = temac_indirect_in32(lp, XTE_EMCFG_OFFSET);
603 mii_speed &= ~XTE_EMCFG_LINKSPD_MASK;
605 switch (phy->speed) {
606 case SPEED_1000: mii_speed |= XTE_EMCFG_LINKSPD_1000; break;
607 case SPEED_100: mii_speed |= XTE_EMCFG_LINKSPD_100; break;
608 case SPEED_10: mii_speed |= XTE_EMCFG_LINKSPD_10; break;
611 /* Write new speed setting out to TEMAC */
612 temac_indirect_out32(lp, XTE_EMCFG_OFFSET, mii_speed);
613 lp->last_link = link_state;
614 phy_print_status(phy);
616 mutex_unlock(&lp->indirect_mutex);
619 static void temac_start_xmit_done(struct net_device *ndev)
621 struct temac_local *lp = netdev_priv(ndev);
622 struct cdmac_bd *cur_p;
623 unsigned int stat = 0;
625 cur_p = &lp->tx_bd_v[lp->tx_bd_ci];
628 while (stat & STS_CTRL_APP0_CMPLT) {
629 dma_unmap_single(ndev->dev.parent, cur_p->phys, cur_p->len,
632 dev_kfree_skb_irq((struct sk_buff *)cur_p->app4);
639 ndev->stats.tx_packets++;
640 ndev->stats.tx_bytes += cur_p->len;
643 if (lp->tx_bd_ci >= TX_BD_NUM)
646 cur_p = &lp->tx_bd_v[lp->tx_bd_ci];
650 netif_wake_queue(ndev);
653 static inline int temac_check_tx_bd_space(struct temac_local *lp, int num_frag)
655 struct cdmac_bd *cur_p;
658 tail = lp->tx_bd_tail;
659 cur_p = &lp->tx_bd_v[tail];
663 return NETDEV_TX_BUSY;
666 if (tail >= TX_BD_NUM)
669 cur_p = &lp->tx_bd_v[tail];
671 } while (num_frag >= 0);
676 static int temac_start_xmit(struct sk_buff *skb, struct net_device *ndev)
678 struct temac_local *lp = netdev_priv(ndev);
679 struct cdmac_bd *cur_p;
680 dma_addr_t start_p, tail_p;
682 unsigned long num_frag;
685 num_frag = skb_shinfo(skb)->nr_frags;
686 frag = &skb_shinfo(skb)->frags[0];
687 start_p = lp->tx_bd_p + sizeof(*lp->tx_bd_v) * lp->tx_bd_tail;
688 cur_p = &lp->tx_bd_v[lp->tx_bd_tail];
690 if (temac_check_tx_bd_space(lp, num_frag)) {
691 if (!netif_queue_stopped(ndev))
692 netif_stop_queue(ndev);
693 return NETDEV_TX_BUSY;
697 if (skb->ip_summed == CHECKSUM_PARTIAL) {
698 unsigned int csum_start_off = skb_checksum_start_offset(skb);
699 unsigned int csum_index_off = csum_start_off + skb->csum_offset;
701 cur_p->app0 |= 1; /* TX Checksum Enabled */
702 cur_p->app1 = (csum_start_off << 16) | csum_index_off;
703 cur_p->app2 = 0; /* initial checksum seed */
706 cur_p->app0 |= STS_CTRL_APP0_SOP;
707 cur_p->len = skb_headlen(skb);
708 cur_p->phys = dma_map_single(ndev->dev.parent, skb->data,
709 skb_headlen(skb), DMA_TO_DEVICE);
710 cur_p->app4 = (unsigned long)skb;
712 for (ii = 0; ii < num_frag; ii++) {
714 if (lp->tx_bd_tail >= TX_BD_NUM)
717 cur_p = &lp->tx_bd_v[lp->tx_bd_tail];
718 cur_p->phys = dma_map_single(ndev->dev.parent,
719 skb_frag_address(frag),
720 skb_frag_size(frag), DMA_TO_DEVICE);
721 cur_p->len = skb_frag_size(frag);
725 cur_p->app0 |= STS_CTRL_APP0_EOP;
727 tail_p = lp->tx_bd_p + sizeof(*lp->tx_bd_v) * lp->tx_bd_tail;
729 if (lp->tx_bd_tail >= TX_BD_NUM)
732 skb_tx_timestamp(skb);
734 /* Kick off the transfer */
735 lp->dma_out(lp, TX_TAILDESC_PTR, tail_p); /* DMA start */
741 static void ll_temac_recv(struct net_device *ndev)
743 struct temac_local *lp = netdev_priv(ndev);
744 struct sk_buff *skb, *new_skb;
746 struct cdmac_bd *cur_p;
751 spin_lock_irqsave(&lp->rx_lock, flags);
753 tail_p = lp->rx_bd_p + sizeof(*lp->rx_bd_v) * lp->rx_bd_ci;
754 cur_p = &lp->rx_bd_v[lp->rx_bd_ci];
756 bdstat = cur_p->app0;
757 while ((bdstat & STS_CTRL_APP0_CMPLT)) {
759 skb = lp->rx_skb[lp->rx_bd_ci];
760 length = cur_p->app4 & 0x3FFF;
762 dma_unmap_single(ndev->dev.parent, cur_p->phys, length,
765 skb_put(skb, length);
766 skb->protocol = eth_type_trans(skb, ndev);
767 skb_checksum_none_assert(skb);
769 /* if we're doing rx csum offload, set it up */
770 if (((lp->temac_features & TEMAC_FEATURE_RX_CSUM) != 0) &&
771 (skb->protocol == htons(ETH_P_IP)) &&
774 skb->csum = cur_p->app3 & 0xFFFF;
775 skb->ip_summed = CHECKSUM_COMPLETE;
778 if (!skb_defer_rx_timestamp(skb))
781 ndev->stats.rx_packets++;
782 ndev->stats.rx_bytes += length;
784 new_skb = netdev_alloc_skb_ip_align(ndev,
785 XTE_MAX_JUMBO_FRAME_SIZE);
787 spin_unlock_irqrestore(&lp->rx_lock, flags);
791 cur_p->app0 = STS_CTRL_APP0_IRQONEND;
792 cur_p->phys = dma_map_single(ndev->dev.parent, new_skb->data,
793 XTE_MAX_JUMBO_FRAME_SIZE,
795 cur_p->len = XTE_MAX_JUMBO_FRAME_SIZE;
796 lp->rx_skb[lp->rx_bd_ci] = new_skb;
799 if (lp->rx_bd_ci >= RX_BD_NUM)
802 cur_p = &lp->rx_bd_v[lp->rx_bd_ci];
803 bdstat = cur_p->app0;
805 lp->dma_out(lp, RX_TAILDESC_PTR, tail_p);
807 spin_unlock_irqrestore(&lp->rx_lock, flags);
810 static irqreturn_t ll_temac_tx_irq(int irq, void *_ndev)
812 struct net_device *ndev = _ndev;
813 struct temac_local *lp = netdev_priv(ndev);
816 status = lp->dma_in(lp, TX_IRQ_REG);
817 lp->dma_out(lp, TX_IRQ_REG, status);
819 if (status & (IRQ_COAL | IRQ_DLY))
820 temac_start_xmit_done(lp->ndev);
822 dev_err(&ndev->dev, "DMA error 0x%x\n", status);
827 static irqreturn_t ll_temac_rx_irq(int irq, void *_ndev)
829 struct net_device *ndev = _ndev;
830 struct temac_local *lp = netdev_priv(ndev);
833 /* Read and clear the status registers */
834 status = lp->dma_in(lp, RX_IRQ_REG);
835 lp->dma_out(lp, RX_IRQ_REG, status);
837 if (status & (IRQ_COAL | IRQ_DLY))
838 ll_temac_recv(lp->ndev);
843 static int temac_open(struct net_device *ndev)
845 struct temac_local *lp = netdev_priv(ndev);
848 dev_dbg(&ndev->dev, "temac_open()\n");
851 lp->phy_dev = of_phy_connect(lp->ndev, lp->phy_node,
852 temac_adjust_link, 0, 0);
854 dev_err(lp->dev, "of_phy_connect() failed\n");
858 phy_start(lp->phy_dev);
861 temac_device_reset(ndev);
863 rc = request_irq(lp->tx_irq, ll_temac_tx_irq, 0, ndev->name, ndev);
866 rc = request_irq(lp->rx_irq, ll_temac_rx_irq, 0, ndev->name, ndev);
873 free_irq(lp->tx_irq, ndev);
876 phy_disconnect(lp->phy_dev);
878 dev_err(lp->dev, "request_irq() failed\n");
882 static int temac_stop(struct net_device *ndev)
884 struct temac_local *lp = netdev_priv(ndev);
886 dev_dbg(&ndev->dev, "temac_close()\n");
888 free_irq(lp->tx_irq, ndev);
889 free_irq(lp->rx_irq, ndev);
892 phy_disconnect(lp->phy_dev);
895 temac_dma_bd_release(ndev);
900 #ifdef CONFIG_NET_POLL_CONTROLLER
902 temac_poll_controller(struct net_device *ndev)
904 struct temac_local *lp = netdev_priv(ndev);
906 disable_irq(lp->tx_irq);
907 disable_irq(lp->rx_irq);
909 ll_temac_rx_irq(lp->tx_irq, ndev);
910 ll_temac_tx_irq(lp->rx_irq, ndev);
912 enable_irq(lp->tx_irq);
913 enable_irq(lp->rx_irq);
917 static int temac_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
919 struct temac_local *lp = netdev_priv(ndev);
921 if (!netif_running(ndev))
927 return phy_mii_ioctl(lp->phy_dev, rq, cmd);
930 static const struct net_device_ops temac_netdev_ops = {
931 .ndo_open = temac_open,
932 .ndo_stop = temac_stop,
933 .ndo_start_xmit = temac_start_xmit,
934 .ndo_set_mac_address = temac_set_mac_address,
935 .ndo_validate_addr = eth_validate_addr,
936 .ndo_do_ioctl = temac_ioctl,
937 #ifdef CONFIG_NET_POLL_CONTROLLER
938 .ndo_poll_controller = temac_poll_controller,
942 /* ---------------------------------------------------------------------
943 * SYSFS device attributes
945 static ssize_t temac_show_llink_regs(struct device *dev,
946 struct device_attribute *attr, char *buf)
948 struct net_device *ndev = dev_get_drvdata(dev);
949 struct temac_local *lp = netdev_priv(ndev);
952 for (i = 0; i < 0x11; i++)
953 len += sprintf(buf + len, "%.8x%s", lp->dma_in(lp, i),
954 (i % 8) == 7 ? "\n" : " ");
955 len += sprintf(buf + len, "\n");
960 static DEVICE_ATTR(llink_regs, 0440, temac_show_llink_regs, NULL);
962 static struct attribute *temac_device_attrs[] = {
963 &dev_attr_llink_regs.attr,
967 static const struct attribute_group temac_attr_group = {
968 .attrs = temac_device_attrs,
971 /* ethtool support */
972 static int temac_get_settings(struct net_device *ndev, struct ethtool_cmd *cmd)
974 struct temac_local *lp = netdev_priv(ndev);
975 return phy_ethtool_gset(lp->phy_dev, cmd);
978 static int temac_set_settings(struct net_device *ndev, struct ethtool_cmd *cmd)
980 struct temac_local *lp = netdev_priv(ndev);
981 return phy_ethtool_sset(lp->phy_dev, cmd);
984 static int temac_nway_reset(struct net_device *ndev)
986 struct temac_local *lp = netdev_priv(ndev);
987 return phy_start_aneg(lp->phy_dev);
990 static const struct ethtool_ops temac_ethtool_ops = {
991 .get_settings = temac_get_settings,
992 .set_settings = temac_set_settings,
993 .nway_reset = temac_nway_reset,
994 .get_link = ethtool_op_get_link,
995 .get_ts_info = ethtool_op_get_ts_info,
998 static int temac_of_probe(struct platform_device *op)
1000 struct device_node *np;
1001 struct temac_local *lp;
1002 struct net_device *ndev;
1007 /* Init network device structure */
1008 ndev = alloc_etherdev(sizeof(*lp));
1012 platform_set_drvdata(op, ndev);
1013 SET_NETDEV_DEV(ndev, &op->dev);
1014 ndev->flags &= ~IFF_MULTICAST; /* clear multicast */
1015 ndev->features = NETIF_F_SG;
1016 ndev->netdev_ops = &temac_netdev_ops;
1017 ndev->ethtool_ops = &temac_ethtool_ops;
1019 ndev->features |= NETIF_F_IP_CSUM; /* Can checksum TCP/UDP over IPv4. */
1020 ndev->features |= NETIF_F_HW_CSUM; /* Can checksum all the packets. */
1021 ndev->features |= NETIF_F_IPV6_CSUM; /* Can checksum IPV6 TCP/UDP */
1022 ndev->features |= NETIF_F_HIGHDMA; /* Can DMA to high memory. */
1023 ndev->features |= NETIF_F_HW_VLAN_CTAG_TX; /* Transmit VLAN hw accel */
1024 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX; /* Receive VLAN hw acceleration */
1025 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; /* Receive VLAN filtering */
1026 ndev->features |= NETIF_F_VLAN_CHALLENGED; /* cannot handle VLAN pkts */
1027 ndev->features |= NETIF_F_GSO; /* Enable software GSO. */
1028 ndev->features |= NETIF_F_MULTI_QUEUE; /* Has multiple TX/RX queues */
1029 ndev->features |= NETIF_F_LRO; /* large receive offload */
1032 /* setup temac private info structure */
1033 lp = netdev_priv(ndev);
1036 lp->options = XTE_OPTION_DEFAULTS;
1037 spin_lock_init(&lp->rx_lock);
1038 mutex_init(&lp->indirect_mutex);
1040 /* map device registers */
1041 lp->regs = of_iomap(op->dev.of_node, 0);
1043 dev_err(&op->dev, "could not map temac regs.\n");
1048 /* Setup checksum offload, but default to off if not specified */
1049 lp->temac_features = 0;
1050 p = (__be32 *)of_get_property(op->dev.of_node, "xlnx,txcsum", NULL);
1051 if (p && be32_to_cpu(*p)) {
1052 lp->temac_features |= TEMAC_FEATURE_TX_CSUM;
1053 /* Can checksum TCP/UDP over IPv4. */
1054 ndev->features |= NETIF_F_IP_CSUM;
1056 p = (__be32 *)of_get_property(op->dev.of_node, "xlnx,rxcsum", NULL);
1057 if (p && be32_to_cpu(*p))
1058 lp->temac_features |= TEMAC_FEATURE_RX_CSUM;
1060 /* Find the DMA node, map the DMA registers, and decode the DMA IRQs */
1061 np = of_parse_phandle(op->dev.of_node, "llink-connected", 0);
1063 dev_err(&op->dev, "could not find DMA node\n");
1068 /* Setup the DMA register accesses, could be DCR or memory mapped */
1069 if (temac_dcr_setup(lp, op, np)) {
1071 /* no DCR in the device tree, try non-DCR */
1072 lp->sdma_regs = of_iomap(np, 0);
1073 if (lp->sdma_regs) {
1074 lp->dma_in = temac_dma_in32;
1075 lp->dma_out = temac_dma_out32;
1076 dev_dbg(&op->dev, "MEM base: %p\n", lp->sdma_regs);
1078 dev_err(&op->dev, "unable to map DMA registers\n");
1084 lp->rx_irq = irq_of_parse_and_map(np, 0);
1085 lp->tx_irq = irq_of_parse_and_map(np, 1);
1087 of_node_put(np); /* Finished with the DMA node; drop the reference */
1089 if (!lp->rx_irq || !lp->tx_irq) {
1090 dev_err(&op->dev, "could not determine irqs\n");
1096 /* Retrieve the MAC address */
1097 addr = of_get_property(op->dev.of_node, "local-mac-address", &size);
1098 if ((!addr) || (size != 6)) {
1099 dev_err(&op->dev, "could not find MAC address\n");
1103 temac_init_mac_address(ndev, (void *)addr);
1105 rc = temac_mdio_setup(lp, op->dev.of_node);
1107 dev_warn(&op->dev, "error registering MDIO bus\n");
1109 lp->phy_node = of_parse_phandle(op->dev.of_node, "phy-handle", 0);
1111 dev_dbg(lp->dev, "using PHY node %s (%p)\n", np->full_name, np);
1113 /* Add the device attributes */
1114 rc = sysfs_create_group(&lp->dev->kobj, &temac_attr_group);
1116 dev_err(lp->dev, "Error creating sysfs files\n");
1120 rc = register_netdev(lp->ndev);
1122 dev_err(lp->dev, "register_netdev() error (%i)\n", rc);
1123 goto err_register_ndev;
1129 sysfs_remove_group(&lp->dev->kobj, &temac_attr_group);
1132 iounmap(lp->sdma_regs);
1141 static int temac_of_remove(struct platform_device *op)
1143 struct net_device *ndev = platform_get_drvdata(op);
1144 struct temac_local *lp = netdev_priv(ndev);
1146 temac_mdio_teardown(lp);
1147 unregister_netdev(ndev);
1148 sysfs_remove_group(&lp->dev->kobj, &temac_attr_group);
1149 of_node_put(lp->phy_node);
1150 lp->phy_node = NULL;
1153 iounmap(lp->sdma_regs);
1158 static const struct of_device_id temac_of_match[] = {
1159 { .compatible = "xlnx,xps-ll-temac-1.01.b", },
1160 { .compatible = "xlnx,xps-ll-temac-2.00.a", },
1161 { .compatible = "xlnx,xps-ll-temac-2.02.a", },
1162 { .compatible = "xlnx,xps-ll-temac-2.03.a", },
1165 MODULE_DEVICE_TABLE(of, temac_of_match);
1167 static struct platform_driver temac_of_driver = {
1168 .probe = temac_of_probe,
1169 .remove = temac_of_remove,
1171 .name = "xilinx_temac",
1172 .of_match_table = temac_of_match,
1176 module_platform_driver(temac_of_driver);
1178 MODULE_DESCRIPTION("Xilinx LL_TEMAC Ethernet driver");
1179 MODULE_AUTHOR("Yoshio Kashiwagi");
1180 MODULE_LICENSE("GPL");