2 * Driver for Xilinx TEMAC Ethernet device
4 * Copyright (c) 2008 Nissin Systems Co., Ltd., Yoshio Kashiwagi
5 * Copyright (c) 2005-2008 DLA Systems, David H. Lynch Jr. <dhlii@dlasys.net>
6 * Copyright (c) 2008-2009 Secret Lab Technologies Ltd.
8 * This is a driver for the Xilinx ll_temac ipcore which is often used
9 * in the Virtex and Spartan series of chips.
12 * - The ll_temac hardware uses indirect access for many of the TEMAC
13 * registers, include the MDIO bus. However, indirect access to MDIO
14 * registers take considerably more clock cycles than to TEMAC registers.
15 * MDIO accesses are long, so threads doing them should probably sleep
16 * rather than busywait. However, since only one indirect access can be
17 * in progress at any given time, that means that *all* indirect accesses
18 * could end up sleeping (to wait for an MDIO access to complete).
19 * Fortunately none of the indirect accesses are on the 'hot' path for tx
20 * or rx, so this should be okay.
23 * - Factor out locallink DMA code into separate driver
24 * - Fix multicast assignment.
25 * - Fix support for hardware checksumming.
26 * - Testing. Lots and lots of testing.
30 #include <linux/delay.h>
31 #include <linux/etherdevice.h>
32 #include <linux/init.h>
33 #include <linux/mii.h>
34 #include <linux/module.h>
35 #include <linux/mutex.h>
36 #include <linux/netdevice.h>
38 #include <linux/of_device.h>
39 #include <linux/of_mdio.h>
40 #include <linux/of_platform.h>
41 #include <linux/of_address.h>
42 #include <linux/skbuff.h>
43 #include <linux/spinlock.h>
44 #include <linux/tcp.h> /* needed for sizeof(tcphdr) */
45 #include <linux/udp.h> /* needed for sizeof(udphdr) */
46 #include <linux/phy.h>
50 #include <linux/slab.h>
51 #include <linux/interrupt.h>
52 #include <linux/dma-mapping.h>
59 /* ---------------------------------------------------------------------
60 * Low level register access functions
63 u32 temac_ior(struct temac_local *lp, int offset)
65 return in_be32((u32 *)(lp->regs + offset));
68 void temac_iow(struct temac_local *lp, int offset, u32 value)
70 out_be32((u32 *) (lp->regs + offset), value);
73 int temac_indirect_busywait(struct temac_local *lp)
75 long end = jiffies + 2;
77 while (!(temac_ior(lp, XTE_RDY0_OFFSET) & XTE_RDY0_HARD_ACS_RDY_MASK)) {
78 if (end - jiffies <= 0) {
90 * lp->indirect_mutex must be held when calling this function
92 u32 temac_indirect_in32(struct temac_local *lp, int reg)
96 if (temac_indirect_busywait(lp))
98 temac_iow(lp, XTE_CTL0_OFFSET, reg);
99 if (temac_indirect_busywait(lp))
101 val = temac_ior(lp, XTE_LSW0_OFFSET);
107 * temac_indirect_out32
109 * lp->indirect_mutex must be held when calling this function
111 void temac_indirect_out32(struct temac_local *lp, int reg, u32 value)
113 if (temac_indirect_busywait(lp))
115 temac_iow(lp, XTE_LSW0_OFFSET, value);
116 temac_iow(lp, XTE_CTL0_OFFSET, CNTLREG_WRITE_ENABLE_MASK | reg);
117 temac_indirect_busywait(lp);
121 * temac_dma_in32 - Memory mapped DMA read, this function expects a
122 * register input that is based on DCR word addresses which
123 * are then converted to memory mapped byte addresses
125 static u32 temac_dma_in32(struct temac_local *lp, int reg)
127 return in_be32((u32 *)(lp->sdma_regs + (reg << 2)));
131 * temac_dma_out32 - Memory mapped DMA read, this function expects a
132 * register input that is based on DCR word addresses which
133 * are then converted to memory mapped byte addresses
135 static void temac_dma_out32(struct temac_local *lp, int reg, u32 value)
137 out_be32((u32 *)(lp->sdma_regs + (reg << 2)), value);
140 /* DMA register access functions can be DCR based or memory mapped.
141 * The PowerPC 440 is DCR based, the PowerPC 405 and MicroBlaze are both
144 #ifdef CONFIG_PPC_DCR
147 * temac_dma_dcr_in32 - DCR based DMA read
149 static u32 temac_dma_dcr_in(struct temac_local *lp, int reg)
151 return dcr_read(lp->sdma_dcrs, reg);
155 * temac_dma_dcr_out32 - DCR based DMA write
157 static void temac_dma_dcr_out(struct temac_local *lp, int reg, u32 value)
159 dcr_write(lp->sdma_dcrs, reg, value);
163 * temac_dcr_setup - If the DMA is DCR based, then setup the address and
166 static int temac_dcr_setup(struct temac_local *lp, struct platform_device *op,
167 struct device_node *np)
171 /* setup the dcr address mapping if it's in the device tree */
173 dcrs = dcr_resource_start(np, 0);
175 lp->sdma_dcrs = dcr_map(np, dcrs, dcr_resource_len(np, 0));
176 lp->dma_in = temac_dma_dcr_in;
177 lp->dma_out = temac_dma_dcr_out;
178 dev_dbg(&op->dev, "DCR base: %x\n", dcrs);
181 /* no DCR in the device tree, indicate a failure */
188 * temac_dcr_setup - This is a stub for when DCR is not supported,
189 * such as with MicroBlaze
191 static int temac_dcr_setup(struct temac_local *lp, struct platform_device *op,
192 struct device_node *np)
200 * temac_dma_bd_release - Release buffer descriptor rings
202 static void temac_dma_bd_release(struct net_device *ndev)
204 struct temac_local *lp = netdev_priv(ndev);
207 /* Reset Local Link (DMA) */
208 lp->dma_out(lp, DMA_CONTROL_REG, DMA_CONTROL_RST);
210 for (i = 0; i < RX_BD_NUM; i++) {
214 dma_unmap_single(ndev->dev.parent, lp->rx_bd_v[i].phys,
215 XTE_MAX_JUMBO_FRAME_SIZE, DMA_FROM_DEVICE);
216 dev_kfree_skb(lp->rx_skb[i]);
220 dma_free_coherent(ndev->dev.parent,
221 sizeof(*lp->rx_bd_v) * RX_BD_NUM,
222 lp->rx_bd_v, lp->rx_bd_p);
224 dma_free_coherent(ndev->dev.parent,
225 sizeof(*lp->tx_bd_v) * TX_BD_NUM,
226 lp->tx_bd_v, lp->tx_bd_p);
232 * temac_dma_bd_init - Setup buffer descriptor rings
234 static int temac_dma_bd_init(struct net_device *ndev)
236 struct temac_local *lp = netdev_priv(ndev);
240 lp->rx_skb = kcalloc(RX_BD_NUM, sizeof(*lp->rx_skb), GFP_KERNEL);
244 /* allocate the tx and rx ring buffer descriptors. */
245 /* returns a virtual address and a physical address. */
246 lp->tx_bd_v = dma_alloc_coherent(ndev->dev.parent,
247 sizeof(*lp->tx_bd_v) * TX_BD_NUM,
248 &lp->tx_bd_p, GFP_KERNEL);
251 "unable to allocate DMA TX buffer descriptors");
254 lp->rx_bd_v = dma_alloc_coherent(ndev->dev.parent,
255 sizeof(*lp->rx_bd_v) * RX_BD_NUM,
256 &lp->rx_bd_p, GFP_KERNEL);
259 "unable to allocate DMA RX buffer descriptors");
263 memset(lp->tx_bd_v, 0, sizeof(*lp->tx_bd_v) * TX_BD_NUM);
264 for (i = 0; i < TX_BD_NUM; i++) {
265 lp->tx_bd_v[i].next = lp->tx_bd_p +
266 sizeof(*lp->tx_bd_v) * ((i + 1) % TX_BD_NUM);
269 memset(lp->rx_bd_v, 0, sizeof(*lp->rx_bd_v) * RX_BD_NUM);
270 for (i = 0; i < RX_BD_NUM; i++) {
271 lp->rx_bd_v[i].next = lp->rx_bd_p +
272 sizeof(*lp->rx_bd_v) * ((i + 1) % RX_BD_NUM);
274 skb = netdev_alloc_skb_ip_align(ndev,
275 XTE_MAX_JUMBO_FRAME_SIZE);
278 dev_err(&ndev->dev, "alloc_skb error %d\n", i);
282 /* returns physical address of skb->data */
283 lp->rx_bd_v[i].phys = dma_map_single(ndev->dev.parent,
285 XTE_MAX_JUMBO_FRAME_SIZE,
287 lp->rx_bd_v[i].len = XTE_MAX_JUMBO_FRAME_SIZE;
288 lp->rx_bd_v[i].app0 = STS_CTRL_APP0_IRQONEND;
291 lp->dma_out(lp, TX_CHNL_CTRL, 0x10220400 |
293 CHNL_CTRL_IRQ_DLY_EN |
294 CHNL_CTRL_IRQ_COAL_EN);
297 lp->dma_out(lp, RX_CHNL_CTRL, 0xff070000 |
299 CHNL_CTRL_IRQ_DLY_EN |
300 CHNL_CTRL_IRQ_COAL_EN |
304 lp->dma_out(lp, RX_CURDESC_PTR, lp->rx_bd_p);
305 lp->dma_out(lp, RX_TAILDESC_PTR,
306 lp->rx_bd_p + (sizeof(*lp->rx_bd_v) * (RX_BD_NUM - 1)));
307 lp->dma_out(lp, TX_CURDESC_PTR, lp->tx_bd_p);
312 temac_dma_bd_release(ndev);
316 /* ---------------------------------------------------------------------
320 static void temac_do_set_mac_address(struct net_device *ndev)
322 struct temac_local *lp = netdev_priv(ndev);
324 /* set up unicast MAC address filter set its mac address */
325 mutex_lock(&lp->indirect_mutex);
326 temac_indirect_out32(lp, XTE_UAW0_OFFSET,
327 (ndev->dev_addr[0]) |
328 (ndev->dev_addr[1] << 8) |
329 (ndev->dev_addr[2] << 16) |
330 (ndev->dev_addr[3] << 24));
331 /* There are reserved bits in EUAW1
332 * so don't affect them Set MAC bits [47:32] in EUAW1 */
333 temac_indirect_out32(lp, XTE_UAW1_OFFSET,
334 (ndev->dev_addr[4] & 0x000000ff) |
335 (ndev->dev_addr[5] << 8));
336 mutex_unlock(&lp->indirect_mutex);
339 static int temac_init_mac_address(struct net_device *ndev, void *address)
341 memcpy(ndev->dev_addr, address, ETH_ALEN);
342 if (!is_valid_ether_addr(ndev->dev_addr))
343 eth_hw_addr_random(ndev);
344 temac_do_set_mac_address(ndev);
348 static int temac_set_mac_address(struct net_device *ndev, void *p)
350 struct sockaddr *addr = p;
352 if (!is_valid_ether_addr(addr->sa_data))
353 return -EADDRNOTAVAIL;
354 memcpy(ndev->dev_addr, addr->sa_data, ETH_ALEN);
355 temac_do_set_mac_address(ndev);
359 static void temac_set_multicast_list(struct net_device *ndev)
361 struct temac_local *lp = netdev_priv(ndev);
362 u32 multi_addr_msw, multi_addr_lsw, val;
365 mutex_lock(&lp->indirect_mutex);
366 if (ndev->flags & (IFF_ALLMULTI | IFF_PROMISC) ||
367 netdev_mc_count(ndev) > MULTICAST_CAM_TABLE_NUM) {
369 * We must make the kernel realise we had to move
370 * into promisc mode or we start all out war on
371 * the cable. If it was a promisc request the
372 * flag is already set. If not we assert it.
374 ndev->flags |= IFF_PROMISC;
375 temac_indirect_out32(lp, XTE_AFM_OFFSET, XTE_AFM_EPPRM_MASK);
376 dev_info(&ndev->dev, "Promiscuous mode enabled.\n");
377 } else if (!netdev_mc_empty(ndev)) {
378 struct netdev_hw_addr *ha;
381 netdev_for_each_mc_addr(ha, ndev) {
382 if (i >= MULTICAST_CAM_TABLE_NUM)
384 multi_addr_msw = ((ha->addr[3] << 24) |
385 (ha->addr[2] << 16) |
388 temac_indirect_out32(lp, XTE_MAW0_OFFSET,
390 multi_addr_lsw = ((ha->addr[5] << 8) |
391 (ha->addr[4]) | (i << 16));
392 temac_indirect_out32(lp, XTE_MAW1_OFFSET,
397 val = temac_indirect_in32(lp, XTE_AFM_OFFSET);
398 temac_indirect_out32(lp, XTE_AFM_OFFSET,
399 val & ~XTE_AFM_EPPRM_MASK);
400 temac_indirect_out32(lp, XTE_MAW0_OFFSET, 0);
401 temac_indirect_out32(lp, XTE_MAW1_OFFSET, 0);
402 dev_info(&ndev->dev, "Promiscuous mode disabled.\n");
404 mutex_unlock(&lp->indirect_mutex);
407 struct temac_option {
413 } temac_options[] = {
414 /* Turn on jumbo packet support for both Rx and Tx */
416 .opt = XTE_OPTION_JUMBO,
417 .reg = XTE_TXC_OFFSET,
418 .m_or = XTE_TXC_TXJMBO_MASK,
421 .opt = XTE_OPTION_JUMBO,
422 .reg = XTE_RXC1_OFFSET,
423 .m_or =XTE_RXC1_RXJMBO_MASK,
425 /* Turn on VLAN packet support for both Rx and Tx */
427 .opt = XTE_OPTION_VLAN,
428 .reg = XTE_TXC_OFFSET,
429 .m_or =XTE_TXC_TXVLAN_MASK,
432 .opt = XTE_OPTION_VLAN,
433 .reg = XTE_RXC1_OFFSET,
434 .m_or =XTE_RXC1_RXVLAN_MASK,
436 /* Turn on FCS stripping on receive packets */
438 .opt = XTE_OPTION_FCS_STRIP,
439 .reg = XTE_RXC1_OFFSET,
440 .m_or =XTE_RXC1_RXFCS_MASK,
442 /* Turn on FCS insertion on transmit packets */
444 .opt = XTE_OPTION_FCS_INSERT,
445 .reg = XTE_TXC_OFFSET,
446 .m_or =XTE_TXC_TXFCS_MASK,
448 /* Turn on length/type field checking on receive packets */
450 .opt = XTE_OPTION_LENTYPE_ERR,
451 .reg = XTE_RXC1_OFFSET,
452 .m_or =XTE_RXC1_RXLT_MASK,
454 /* Turn on flow control */
456 .opt = XTE_OPTION_FLOW_CONTROL,
457 .reg = XTE_FCC_OFFSET,
458 .m_or =XTE_FCC_RXFLO_MASK,
460 /* Turn on flow control */
462 .opt = XTE_OPTION_FLOW_CONTROL,
463 .reg = XTE_FCC_OFFSET,
464 .m_or =XTE_FCC_TXFLO_MASK,
466 /* Turn on promiscuous frame filtering (all frames are received ) */
468 .opt = XTE_OPTION_PROMISC,
469 .reg = XTE_AFM_OFFSET,
470 .m_or =XTE_AFM_EPPRM_MASK,
472 /* Enable transmitter if not already enabled */
474 .opt = XTE_OPTION_TXEN,
475 .reg = XTE_TXC_OFFSET,
476 .m_or =XTE_TXC_TXEN_MASK,
478 /* Enable receiver? */
480 .opt = XTE_OPTION_RXEN,
481 .reg = XTE_RXC1_OFFSET,
482 .m_or =XTE_RXC1_RXEN_MASK,
490 static u32 temac_setoptions(struct net_device *ndev, u32 options)
492 struct temac_local *lp = netdev_priv(ndev);
493 struct temac_option *tp = &temac_options[0];
496 mutex_lock(&lp->indirect_mutex);
498 reg = temac_indirect_in32(lp, tp->reg) & ~tp->m_or;
499 if (options & tp->opt)
501 temac_indirect_out32(lp, tp->reg, reg);
504 lp->options |= options;
505 mutex_unlock(&lp->indirect_mutex);
510 /* Initialize temac */
511 static void temac_device_reset(struct net_device *ndev)
513 struct temac_local *lp = netdev_priv(ndev);
517 /* Perform a software reset */
519 /* 0x300 host enable bit ? */
520 /* reset PHY through control register ?:1 */
522 dev_dbg(&ndev->dev, "%s()\n", __func__);
524 mutex_lock(&lp->indirect_mutex);
525 /* Reset the receiver and wait for it to finish reset */
526 temac_indirect_out32(lp, XTE_RXC1_OFFSET, XTE_RXC1_RXRST_MASK);
528 while (temac_indirect_in32(lp, XTE_RXC1_OFFSET) & XTE_RXC1_RXRST_MASK) {
530 if (--timeout == 0) {
532 "temac_device_reset RX reset timeout!!\n");
537 /* Reset the transmitter and wait for it to finish reset */
538 temac_indirect_out32(lp, XTE_TXC_OFFSET, XTE_TXC_TXRST_MASK);
540 while (temac_indirect_in32(lp, XTE_TXC_OFFSET) & XTE_TXC_TXRST_MASK) {
542 if (--timeout == 0) {
544 "temac_device_reset TX reset timeout!!\n");
549 /* Disable the receiver */
550 val = temac_indirect_in32(lp, XTE_RXC1_OFFSET);
551 temac_indirect_out32(lp, XTE_RXC1_OFFSET, val & ~XTE_RXC1_RXEN_MASK);
553 /* Reset Local Link (DMA) */
554 lp->dma_out(lp, DMA_CONTROL_REG, DMA_CONTROL_RST);
556 while (lp->dma_in(lp, DMA_CONTROL_REG) & DMA_CONTROL_RST) {
558 if (--timeout == 0) {
560 "temac_device_reset DMA reset timeout!!\n");
564 lp->dma_out(lp, DMA_CONTROL_REG, DMA_TAIL_ENABLE);
566 if (temac_dma_bd_init(ndev)) {
568 "temac_device_reset descriptor allocation failed\n");
571 temac_indirect_out32(lp, XTE_RXC0_OFFSET, 0);
572 temac_indirect_out32(lp, XTE_RXC1_OFFSET, 0);
573 temac_indirect_out32(lp, XTE_TXC_OFFSET, 0);
574 temac_indirect_out32(lp, XTE_FCC_OFFSET, XTE_FCC_RXFLO_MASK);
576 mutex_unlock(&lp->indirect_mutex);
578 /* Sync default options with HW
579 * but leave receiver and transmitter disabled. */
580 temac_setoptions(ndev,
581 lp->options & ~(XTE_OPTION_TXEN | XTE_OPTION_RXEN));
583 temac_do_set_mac_address(ndev);
585 /* Set address filter table */
586 temac_set_multicast_list(ndev);
587 if (temac_setoptions(ndev, lp->options))
588 dev_err(&ndev->dev, "Error setting TEMAC options\n");
590 /* Init Driver variable */
591 ndev->trans_start = jiffies; /* prevent tx timeout */
594 void temac_adjust_link(struct net_device *ndev)
596 struct temac_local *lp = netdev_priv(ndev);
597 struct phy_device *phy = lp->phy_dev;
601 /* hash together the state values to decide if something has changed */
602 link_state = phy->speed | (phy->duplex << 1) | phy->link;
604 mutex_lock(&lp->indirect_mutex);
605 if (lp->last_link != link_state) {
606 mii_speed = temac_indirect_in32(lp, XTE_EMCFG_OFFSET);
607 mii_speed &= ~XTE_EMCFG_LINKSPD_MASK;
609 switch (phy->speed) {
610 case SPEED_1000: mii_speed |= XTE_EMCFG_LINKSPD_1000; break;
611 case SPEED_100: mii_speed |= XTE_EMCFG_LINKSPD_100; break;
612 case SPEED_10: mii_speed |= XTE_EMCFG_LINKSPD_10; break;
615 /* Write new speed setting out to TEMAC */
616 temac_indirect_out32(lp, XTE_EMCFG_OFFSET, mii_speed);
617 lp->last_link = link_state;
618 phy_print_status(phy);
620 mutex_unlock(&lp->indirect_mutex);
623 static void temac_start_xmit_done(struct net_device *ndev)
625 struct temac_local *lp = netdev_priv(ndev);
626 struct cdmac_bd *cur_p;
627 unsigned int stat = 0;
629 cur_p = &lp->tx_bd_v[lp->tx_bd_ci];
632 while (stat & STS_CTRL_APP0_CMPLT) {
633 dma_unmap_single(ndev->dev.parent, cur_p->phys, cur_p->len,
636 dev_kfree_skb_irq((struct sk_buff *)cur_p->app4);
643 ndev->stats.tx_packets++;
644 ndev->stats.tx_bytes += cur_p->len;
647 if (lp->tx_bd_ci >= TX_BD_NUM)
650 cur_p = &lp->tx_bd_v[lp->tx_bd_ci];
654 netif_wake_queue(ndev);
657 static inline int temac_check_tx_bd_space(struct temac_local *lp, int num_frag)
659 struct cdmac_bd *cur_p;
662 tail = lp->tx_bd_tail;
663 cur_p = &lp->tx_bd_v[tail];
667 return NETDEV_TX_BUSY;
670 if (tail >= TX_BD_NUM)
673 cur_p = &lp->tx_bd_v[tail];
675 } while (num_frag >= 0);
680 static int temac_start_xmit(struct sk_buff *skb, struct net_device *ndev)
682 struct temac_local *lp = netdev_priv(ndev);
683 struct cdmac_bd *cur_p;
684 dma_addr_t start_p, tail_p;
686 unsigned long num_frag;
689 num_frag = skb_shinfo(skb)->nr_frags;
690 frag = &skb_shinfo(skb)->frags[0];
691 start_p = lp->tx_bd_p + sizeof(*lp->tx_bd_v) * lp->tx_bd_tail;
692 cur_p = &lp->tx_bd_v[lp->tx_bd_tail];
694 if (temac_check_tx_bd_space(lp, num_frag)) {
695 if (!netif_queue_stopped(ndev)) {
696 netif_stop_queue(ndev);
697 return NETDEV_TX_BUSY;
699 return NETDEV_TX_BUSY;
703 if (skb->ip_summed == CHECKSUM_PARTIAL) {
704 unsigned int csum_start_off = skb_checksum_start_offset(skb);
705 unsigned int csum_index_off = csum_start_off + skb->csum_offset;
707 cur_p->app0 |= 1; /* TX Checksum Enabled */
708 cur_p->app1 = (csum_start_off << 16) | csum_index_off;
709 cur_p->app2 = 0; /* initial checksum seed */
712 cur_p->app0 |= STS_CTRL_APP0_SOP;
713 cur_p->len = skb_headlen(skb);
714 cur_p->phys = dma_map_single(ndev->dev.parent, skb->data, skb->len,
716 cur_p->app4 = (unsigned long)skb;
718 for (ii = 0; ii < num_frag; ii++) {
720 if (lp->tx_bd_tail >= TX_BD_NUM)
723 cur_p = &lp->tx_bd_v[lp->tx_bd_tail];
724 cur_p->phys = dma_map_single(ndev->dev.parent,
725 skb_frag_address(frag),
726 skb_frag_size(frag), DMA_TO_DEVICE);
727 cur_p->len = skb_frag_size(frag);
731 cur_p->app0 |= STS_CTRL_APP0_EOP;
733 tail_p = lp->tx_bd_p + sizeof(*lp->tx_bd_v) * lp->tx_bd_tail;
735 if (lp->tx_bd_tail >= TX_BD_NUM)
738 skb_tx_timestamp(skb);
740 /* Kick off the transfer */
741 lp->dma_out(lp, TX_TAILDESC_PTR, tail_p); /* DMA start */
747 static void ll_temac_recv(struct net_device *ndev)
749 struct temac_local *lp = netdev_priv(ndev);
750 struct sk_buff *skb, *new_skb;
752 struct cdmac_bd *cur_p;
757 spin_lock_irqsave(&lp->rx_lock, flags);
759 tail_p = lp->rx_bd_p + sizeof(*lp->rx_bd_v) * lp->rx_bd_ci;
760 cur_p = &lp->rx_bd_v[lp->rx_bd_ci];
762 bdstat = cur_p->app0;
763 while ((bdstat & STS_CTRL_APP0_CMPLT)) {
765 skb = lp->rx_skb[lp->rx_bd_ci];
766 length = cur_p->app4 & 0x3FFF;
768 dma_unmap_single(ndev->dev.parent, cur_p->phys, length,
771 skb_put(skb, length);
772 skb->protocol = eth_type_trans(skb, ndev);
773 skb_checksum_none_assert(skb);
775 /* if we're doing rx csum offload, set it up */
776 if (((lp->temac_features & TEMAC_FEATURE_RX_CSUM) != 0) &&
777 (skb->protocol == __constant_htons(ETH_P_IP)) &&
780 skb->csum = cur_p->app3 & 0xFFFF;
781 skb->ip_summed = CHECKSUM_COMPLETE;
784 if (!skb_defer_rx_timestamp(skb))
787 ndev->stats.rx_packets++;
788 ndev->stats.rx_bytes += length;
790 new_skb = netdev_alloc_skb_ip_align(ndev,
791 XTE_MAX_JUMBO_FRAME_SIZE);
794 dev_err(&ndev->dev, "no memory for new sk_buff\n");
795 spin_unlock_irqrestore(&lp->rx_lock, flags);
799 cur_p->app0 = STS_CTRL_APP0_IRQONEND;
800 cur_p->phys = dma_map_single(ndev->dev.parent, new_skb->data,
801 XTE_MAX_JUMBO_FRAME_SIZE,
803 cur_p->len = XTE_MAX_JUMBO_FRAME_SIZE;
804 lp->rx_skb[lp->rx_bd_ci] = new_skb;
807 if (lp->rx_bd_ci >= RX_BD_NUM)
810 cur_p = &lp->rx_bd_v[lp->rx_bd_ci];
811 bdstat = cur_p->app0;
813 lp->dma_out(lp, RX_TAILDESC_PTR, tail_p);
815 spin_unlock_irqrestore(&lp->rx_lock, flags);
818 static irqreturn_t ll_temac_tx_irq(int irq, void *_ndev)
820 struct net_device *ndev = _ndev;
821 struct temac_local *lp = netdev_priv(ndev);
824 status = lp->dma_in(lp, TX_IRQ_REG);
825 lp->dma_out(lp, TX_IRQ_REG, status);
827 if (status & (IRQ_COAL | IRQ_DLY))
828 temac_start_xmit_done(lp->ndev);
830 dev_err(&ndev->dev, "DMA error 0x%x\n", status);
835 static irqreturn_t ll_temac_rx_irq(int irq, void *_ndev)
837 struct net_device *ndev = _ndev;
838 struct temac_local *lp = netdev_priv(ndev);
841 /* Read and clear the status registers */
842 status = lp->dma_in(lp, RX_IRQ_REG);
843 lp->dma_out(lp, RX_IRQ_REG, status);
845 if (status & (IRQ_COAL | IRQ_DLY))
846 ll_temac_recv(lp->ndev);
851 static int temac_open(struct net_device *ndev)
853 struct temac_local *lp = netdev_priv(ndev);
856 dev_dbg(&ndev->dev, "temac_open()\n");
859 lp->phy_dev = of_phy_connect(lp->ndev, lp->phy_node,
860 temac_adjust_link, 0, 0);
862 dev_err(lp->dev, "of_phy_connect() failed\n");
866 phy_start(lp->phy_dev);
869 temac_device_reset(ndev);
871 rc = request_irq(lp->tx_irq, ll_temac_tx_irq, 0, ndev->name, ndev);
874 rc = request_irq(lp->rx_irq, ll_temac_rx_irq, 0, ndev->name, ndev);
881 free_irq(lp->tx_irq, ndev);
884 phy_disconnect(lp->phy_dev);
886 dev_err(lp->dev, "request_irq() failed\n");
890 static int temac_stop(struct net_device *ndev)
892 struct temac_local *lp = netdev_priv(ndev);
894 dev_dbg(&ndev->dev, "temac_close()\n");
896 free_irq(lp->tx_irq, ndev);
897 free_irq(lp->rx_irq, ndev);
900 phy_disconnect(lp->phy_dev);
903 temac_dma_bd_release(ndev);
908 #ifdef CONFIG_NET_POLL_CONTROLLER
910 temac_poll_controller(struct net_device *ndev)
912 struct temac_local *lp = netdev_priv(ndev);
914 disable_irq(lp->tx_irq);
915 disable_irq(lp->rx_irq);
917 ll_temac_rx_irq(lp->tx_irq, ndev);
918 ll_temac_tx_irq(lp->rx_irq, ndev);
920 enable_irq(lp->tx_irq);
921 enable_irq(lp->rx_irq);
925 static int temac_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
927 struct temac_local *lp = netdev_priv(ndev);
929 if (!netif_running(ndev))
935 return phy_mii_ioctl(lp->phy_dev, rq, cmd);
938 static const struct net_device_ops temac_netdev_ops = {
939 .ndo_open = temac_open,
940 .ndo_stop = temac_stop,
941 .ndo_start_xmit = temac_start_xmit,
942 .ndo_set_mac_address = temac_set_mac_address,
943 .ndo_validate_addr = eth_validate_addr,
944 .ndo_do_ioctl = temac_ioctl,
945 #ifdef CONFIG_NET_POLL_CONTROLLER
946 .ndo_poll_controller = temac_poll_controller,
950 /* ---------------------------------------------------------------------
951 * SYSFS device attributes
953 static ssize_t temac_show_llink_regs(struct device *dev,
954 struct device_attribute *attr, char *buf)
956 struct net_device *ndev = dev_get_drvdata(dev);
957 struct temac_local *lp = netdev_priv(ndev);
960 for (i = 0; i < 0x11; i++)
961 len += sprintf(buf + len, "%.8x%s", lp->dma_in(lp, i),
962 (i % 8) == 7 ? "\n" : " ");
963 len += sprintf(buf + len, "\n");
968 static DEVICE_ATTR(llink_regs, 0440, temac_show_llink_regs, NULL);
970 static struct attribute *temac_device_attrs[] = {
971 &dev_attr_llink_regs.attr,
975 static const struct attribute_group temac_attr_group = {
976 .attrs = temac_device_attrs,
979 /* ethtool support */
980 static int temac_get_settings(struct net_device *ndev, struct ethtool_cmd *cmd)
982 struct temac_local *lp = netdev_priv(ndev);
983 return phy_ethtool_gset(lp->phy_dev, cmd);
986 static int temac_set_settings(struct net_device *ndev, struct ethtool_cmd *cmd)
988 struct temac_local *lp = netdev_priv(ndev);
989 return phy_ethtool_sset(lp->phy_dev, cmd);
992 static int temac_nway_reset(struct net_device *ndev)
994 struct temac_local *lp = netdev_priv(ndev);
995 return phy_start_aneg(lp->phy_dev);
998 static const struct ethtool_ops temac_ethtool_ops = {
999 .get_settings = temac_get_settings,
1000 .set_settings = temac_set_settings,
1001 .nway_reset = temac_nway_reset,
1002 .get_link = ethtool_op_get_link,
1003 .get_ts_info = ethtool_op_get_ts_info,
1006 static int temac_of_probe(struct platform_device *op)
1008 struct device_node *np;
1009 struct temac_local *lp;
1010 struct net_device *ndev;
1015 /* Init network device structure */
1016 ndev = alloc_etherdev(sizeof(*lp));
1021 dev_set_drvdata(&op->dev, ndev);
1022 SET_NETDEV_DEV(ndev, &op->dev);
1023 ndev->flags &= ~IFF_MULTICAST; /* clear multicast */
1024 ndev->features = NETIF_F_SG | NETIF_F_FRAGLIST;
1025 ndev->netdev_ops = &temac_netdev_ops;
1026 ndev->ethtool_ops = &temac_ethtool_ops;
1028 ndev->features |= NETIF_F_IP_CSUM; /* Can checksum TCP/UDP over IPv4. */
1029 ndev->features |= NETIF_F_HW_CSUM; /* Can checksum all the packets. */
1030 ndev->features |= NETIF_F_IPV6_CSUM; /* Can checksum IPV6 TCP/UDP */
1031 ndev->features |= NETIF_F_HIGHDMA; /* Can DMA to high memory. */
1032 ndev->features |= NETIF_F_HW_VLAN_TX; /* Transmit VLAN hw accel */
1033 ndev->features |= NETIF_F_HW_VLAN_RX; /* Receive VLAN hw acceleration */
1034 ndev->features |= NETIF_F_HW_VLAN_FILTER; /* Receive VLAN filtering */
1035 ndev->features |= NETIF_F_VLAN_CHALLENGED; /* cannot handle VLAN pkts */
1036 ndev->features |= NETIF_F_GSO; /* Enable software GSO. */
1037 ndev->features |= NETIF_F_MULTI_QUEUE; /* Has multiple TX/RX queues */
1038 ndev->features |= NETIF_F_LRO; /* large receive offload */
1041 /* setup temac private info structure */
1042 lp = netdev_priv(ndev);
1045 lp->options = XTE_OPTION_DEFAULTS;
1046 spin_lock_init(&lp->rx_lock);
1047 mutex_init(&lp->indirect_mutex);
1049 /* map device registers */
1050 lp->regs = of_iomap(op->dev.of_node, 0);
1052 dev_err(&op->dev, "could not map temac regs.\n");
1056 /* Setup checksum offload, but default to off if not specified */
1057 lp->temac_features = 0;
1058 p = (__be32 *)of_get_property(op->dev.of_node, "xlnx,txcsum", NULL);
1059 if (p && be32_to_cpu(*p)) {
1060 lp->temac_features |= TEMAC_FEATURE_TX_CSUM;
1061 /* Can checksum TCP/UDP over IPv4. */
1062 ndev->features |= NETIF_F_IP_CSUM;
1064 p = (__be32 *)of_get_property(op->dev.of_node, "xlnx,rxcsum", NULL);
1065 if (p && be32_to_cpu(*p))
1066 lp->temac_features |= TEMAC_FEATURE_RX_CSUM;
1068 /* Find the DMA node, map the DMA registers, and decode the DMA IRQs */
1069 np = of_parse_phandle(op->dev.of_node, "llink-connected", 0);
1071 dev_err(&op->dev, "could not find DMA node\n");
1075 /* Setup the DMA register accesses, could be DCR or memory mapped */
1076 if (temac_dcr_setup(lp, op, np)) {
1078 /* no DCR in the device tree, try non-DCR */
1079 lp->sdma_regs = of_iomap(np, 0);
1080 if (lp->sdma_regs) {
1081 lp->dma_in = temac_dma_in32;
1082 lp->dma_out = temac_dma_out32;
1083 dev_dbg(&op->dev, "MEM base: %p\n", lp->sdma_regs);
1085 dev_err(&op->dev, "unable to map DMA registers\n");
1091 lp->rx_irq = irq_of_parse_and_map(np, 0);
1092 lp->tx_irq = irq_of_parse_and_map(np, 1);
1094 of_node_put(np); /* Finished with the DMA node; drop the reference */
1096 if (!lp->rx_irq || !lp->tx_irq) {
1097 dev_err(&op->dev, "could not determine irqs\n");
1103 /* Retrieve the MAC address */
1104 addr = of_get_property(op->dev.of_node, "local-mac-address", &size);
1105 if ((!addr) || (size != 6)) {
1106 dev_err(&op->dev, "could not find MAC address\n");
1110 temac_init_mac_address(ndev, (void *)addr);
1112 rc = temac_mdio_setup(lp, op->dev.of_node);
1114 dev_warn(&op->dev, "error registering MDIO bus\n");
1116 lp->phy_node = of_parse_phandle(op->dev.of_node, "phy-handle", 0);
1118 dev_dbg(lp->dev, "using PHY node %s (%p)\n", np->full_name, np);
1120 /* Add the device attributes */
1121 rc = sysfs_create_group(&lp->dev->kobj, &temac_attr_group);
1123 dev_err(lp->dev, "Error creating sysfs files\n");
1127 rc = register_netdev(lp->ndev);
1129 dev_err(lp->dev, "register_netdev() error (%i)\n", rc);
1130 goto err_register_ndev;
1136 sysfs_remove_group(&lp->dev->kobj, &temac_attr_group);
1139 iounmap(lp->sdma_regs);
1148 static int temac_of_remove(struct platform_device *op)
1150 struct net_device *ndev = dev_get_drvdata(&op->dev);
1151 struct temac_local *lp = netdev_priv(ndev);
1153 temac_mdio_teardown(lp);
1154 unregister_netdev(ndev);
1155 sysfs_remove_group(&lp->dev->kobj, &temac_attr_group);
1157 of_node_put(lp->phy_node);
1158 lp->phy_node = NULL;
1159 dev_set_drvdata(&op->dev, NULL);
1162 iounmap(lp->sdma_regs);
1167 static struct of_device_id temac_of_match[] = {
1168 { .compatible = "xlnx,xps-ll-temac-1.01.b", },
1169 { .compatible = "xlnx,xps-ll-temac-2.00.a", },
1170 { .compatible = "xlnx,xps-ll-temac-2.02.a", },
1171 { .compatible = "xlnx,xps-ll-temac-2.03.a", },
1174 MODULE_DEVICE_TABLE(of, temac_of_match);
1176 static struct platform_driver temac_of_driver = {
1177 .probe = temac_of_probe,
1178 .remove = temac_of_remove,
1180 .owner = THIS_MODULE,
1181 .name = "xilinx_temac",
1182 .of_match_table = temac_of_match,
1186 module_platform_driver(temac_of_driver);
1188 MODULE_DESCRIPTION("Xilinx LL_TEMAC Ethernet driver");
1189 MODULE_AUTHOR("Yoshio Kashiwagi");
1190 MODULE_LICENSE("GPL");