2 * MDIO bus driver for the Xilinx Axi Ethernet device
4 * Copyright (c) 2009 Secret Lab Technologies, Ltd.
5 * Copyright (c) 2010 - 2011 Michal Simek <monstr@monstr.eu>
6 * Copyright (c) 2010 - 2011 PetaLogix
7 * Copyright (c) 2010 - 2012 Xilinx, Inc. All rights reserved.
10 #include <linux/of_address.h>
11 #include <linux/of_mdio.h>
12 #include <linux/jiffies.h>
14 #include "xilinx_axienet.h"
16 #define MAX_MDIO_FREQ 2500000 /* 2.5 MHz */
17 #define DEFAULT_CLOCK_DIVISOR XAE_MDIO_DIV_DFT
19 /* Wait till MDIO interface is ready to accept a new transaction.*/
20 int axienet_mdio_wait_until_ready(struct axienet_local *lp)
22 unsigned long end = jiffies + 2;
23 while (!(axienet_ior(lp, XAE_MDIO_MCR_OFFSET) &
24 XAE_MDIO_MCR_READY_MASK)) {
25 if (time_before_eq(end, jiffies)) {
35 * axienet_mdio_read - MDIO interface read function
36 * @bus: Pointer to mii bus structure
37 * @phy_id: Address of the PHY device
38 * @reg: PHY register to read
40 * Return: The register contents on success, -ETIMEDOUT on a timeout
42 * Reads the contents of the requested register from the requested PHY
43 * address by first writing the details into MCR register. After a while
44 * the register MRD is read to obtain the PHY register content.
46 static int axienet_mdio_read(struct mii_bus *bus, int phy_id, int reg)
50 struct axienet_local *lp = bus->priv;
52 ret = axienet_mdio_wait_until_ready(lp);
56 axienet_iow(lp, XAE_MDIO_MCR_OFFSET,
57 (((phy_id << XAE_MDIO_MCR_PHYAD_SHIFT) &
58 XAE_MDIO_MCR_PHYAD_MASK) |
59 ((reg << XAE_MDIO_MCR_REGAD_SHIFT) &
60 XAE_MDIO_MCR_REGAD_MASK) |
61 XAE_MDIO_MCR_INITIATE_MASK |
62 XAE_MDIO_MCR_OP_READ_MASK));
64 ret = axienet_mdio_wait_until_ready(lp);
68 rc = axienet_ior(lp, XAE_MDIO_MRD_OFFSET) & 0x0000FFFF;
70 dev_dbg(lp->dev, "axienet_mdio_read(phy_id=%i, reg=%x) == %x\n",
77 * axienet_mdio_write - MDIO interface write function
78 * @bus: Pointer to mii bus structure
79 * @phy_id: Address of the PHY device
80 * @reg: PHY register to write to
81 * @val: Value to be written into the register
83 * Return: 0 on success, -ETIMEDOUT on a timeout
85 * Writes the value to the requested register by first writing the value
86 * into MWD register. The the MCR register is then appropriately setup
87 * to finish the write operation.
89 static int axienet_mdio_write(struct mii_bus *bus, int phy_id, int reg,
93 struct axienet_local *lp = bus->priv;
95 dev_dbg(lp->dev, "axienet_mdio_write(phy_id=%i, reg=%x, val=%x)\n",
98 ret = axienet_mdio_wait_until_ready(lp);
102 axienet_iow(lp, XAE_MDIO_MWD_OFFSET, (u32) val);
103 axienet_iow(lp, XAE_MDIO_MCR_OFFSET,
104 (((phy_id << XAE_MDIO_MCR_PHYAD_SHIFT) &
105 XAE_MDIO_MCR_PHYAD_MASK) |
106 ((reg << XAE_MDIO_MCR_REGAD_SHIFT) &
107 XAE_MDIO_MCR_REGAD_MASK) |
108 XAE_MDIO_MCR_INITIATE_MASK |
109 XAE_MDIO_MCR_OP_WRITE_MASK));
111 ret = axienet_mdio_wait_until_ready(lp);
118 * axienet_mdio_setup - MDIO setup function
119 * @lp: Pointer to axienet local data structure.
120 * @np: Pointer to device node
122 * Return: 0 on success, -ETIMEDOUT on a timeout, -ENOMEM when
123 * mdiobus_alloc (to allocate memory for mii bus structure) fails.
125 * Sets up the MDIO interface by initializing the MDIO clock and enabling the
126 * MDIO interface in hardware. Register the MDIO interface.
128 int axienet_mdio_setup(struct axienet_local *lp, struct device_node *np)
131 u32 clk_div, host_clock;
135 struct device_node *np1;
137 /* clk_div can be calculated by deriving it from the equation:
138 * fMDIO = fHOST / ((1 + clk_div) * 2)
140 * Where fMDIO <= 2500000, so we get:
141 * fHOST / ((1 + clk_div) * 2) <= 2500000
144 * 1 / ((1 + clk_div) * 2) <= (2500000 / fHOST)
147 * 1 / (1 + clk_div) <= ((2500000 * 2) / fHOST)
150 * 1 / (1 + clk_div) <= (5000000 / fHOST)
153 * (1 + clk_div) >= (fHOST / 5000000)
156 * clk_div >= (fHOST / 5000000) - 1
158 * fHOST can be read from the flattened device tree as property
159 * "clock-frequency" from the CPU
162 np1 = of_find_node_by_name(NULL, "cpu");
164 netdev_warn(lp->ndev, "Could not find CPU device node.\n");
165 netdev_warn(lp->ndev,
166 "Setting MDIO clock divisor to default %d\n",
167 DEFAULT_CLOCK_DIVISOR);
168 clk_div = DEFAULT_CLOCK_DIVISOR;
171 property_p = (u32 *) of_get_property(np1, "clock-frequency", NULL);
173 netdev_warn(lp->ndev, "clock-frequency property not found.\n");
174 netdev_warn(lp->ndev,
175 "Setting MDIO clock divisor to default %d\n",
176 DEFAULT_CLOCK_DIVISOR);
177 clk_div = DEFAULT_CLOCK_DIVISOR;
182 host_clock = be32_to_cpup(property_p);
183 clk_div = (host_clock / (MAX_MDIO_FREQ * 2)) - 1;
184 /* If there is any remainder from the division of
185 * fHOST / (MAX_MDIO_FREQ * 2), then we need to add
186 * 1 to the clock divisor or we will surely be above 2.5 MHz
188 if (host_clock % (MAX_MDIO_FREQ * 2))
192 "Setting MDIO clock divisor to %u/%u Hz host clock.\n",
193 clk_div, host_clock);
197 axienet_iow(lp, XAE_MDIO_MC_OFFSET,
198 (((u32) clk_div) | XAE_MDIO_MC_MDIOEN_MASK));
200 ret = axienet_mdio_wait_until_ready(lp);
204 bus = mdiobus_alloc();
208 np1 = of_get_parent(lp->phy_node);
209 of_address_to_resource(np1, 0, &res);
210 snprintf(bus->id, MII_BUS_ID_SIZE, "%.8llx",
211 (unsigned long long) res.start);
214 bus->name = "Xilinx Axi Ethernet MDIO";
215 bus->read = axienet_mdio_read;
216 bus->write = axienet_mdio_write;
217 bus->parent = lp->dev;
218 bus->irq = lp->mdio_irqs; /* preallocated IRQ table */
221 ret = of_mdiobus_register(bus, np1);
230 * axienet_mdio_teardown - MDIO remove function
231 * @lp: Pointer to axienet local data structure.
233 * Unregisters the MDIO and frees any associate memory for mii bus.
235 void axienet_mdio_teardown(struct axienet_local *lp)
237 mdiobus_unregister(lp->mii_bus);
238 kfree(lp->mii_bus->irq);
239 mdiobus_free(lp->mii_bus);