2 * linux/drivers/net/ethoc.c
4 * Copyright (C) 2007-2008 Avionic Design Development GmbH
5 * Copyright (C) 2008-2009 Avionic Design GmbH
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * Written by Thierry Reding <thierry.reding@avionic-design.de>
14 #include <linux/etherdevice.h>
15 #include <linux/crc32.h>
17 #include <linux/mii.h>
18 #include <linux/phy.h>
19 #include <linux/platform_device.h>
20 #include <linux/sched.h>
21 #include <linux/slab.h>
22 #include <net/ethoc.h>
24 static int buffer_size = 0x8000; /* 32 KBytes */
25 module_param(buffer_size, int, 0);
26 MODULE_PARM_DESC(buffer_size, "DMA buffer allocation size");
28 /* register offsets */
30 #define INT_SOURCE 0x04
35 #define PACKETLEN 0x18
37 #define TX_BD_NUM 0x20
38 #define CTRLMODER 0x24
40 #define MIICOMMAND 0x2c
41 #define MIIADDRESS 0x30
42 #define MIITX_DATA 0x34
43 #define MIIRX_DATA 0x38
44 #define MIISTATUS 0x3c
45 #define MAC_ADDR0 0x40
46 #define MAC_ADDR1 0x44
47 #define ETH_HASH0 0x48
48 #define ETH_HASH1 0x4c
49 #define ETH_TXCTRL 0x50
52 #define MODER_RXEN (1 << 0) /* receive enable */
53 #define MODER_TXEN (1 << 1) /* transmit enable */
54 #define MODER_NOPRE (1 << 2) /* no preamble */
55 #define MODER_BRO (1 << 3) /* broadcast address */
56 #define MODER_IAM (1 << 4) /* individual address mode */
57 #define MODER_PRO (1 << 5) /* promiscuous mode */
58 #define MODER_IFG (1 << 6) /* interframe gap for incoming frames */
59 #define MODER_LOOP (1 << 7) /* loopback */
60 #define MODER_NBO (1 << 8) /* no back-off */
61 #define MODER_EDE (1 << 9) /* excess defer enable */
62 #define MODER_FULLD (1 << 10) /* full duplex */
63 #define MODER_RESET (1 << 11) /* FIXME: reset (undocumented) */
64 #define MODER_DCRC (1 << 12) /* delayed CRC enable */
65 #define MODER_CRC (1 << 13) /* CRC enable */
66 #define MODER_HUGE (1 << 14) /* huge packets enable */
67 #define MODER_PAD (1 << 15) /* padding enabled */
68 #define MODER_RSM (1 << 16) /* receive small packets */
70 /* interrupt source and mask registers */
71 #define INT_MASK_TXF (1 << 0) /* transmit frame */
72 #define INT_MASK_TXE (1 << 1) /* transmit error */
73 #define INT_MASK_RXF (1 << 2) /* receive frame */
74 #define INT_MASK_RXE (1 << 3) /* receive error */
75 #define INT_MASK_BUSY (1 << 4)
76 #define INT_MASK_TXC (1 << 5) /* transmit control frame */
77 #define INT_MASK_RXC (1 << 6) /* receive control frame */
79 #define INT_MASK_TX (INT_MASK_TXF | INT_MASK_TXE)
80 #define INT_MASK_RX (INT_MASK_RXF | INT_MASK_RXE)
82 #define INT_MASK_ALL ( \
83 INT_MASK_TXF | INT_MASK_TXE | \
84 INT_MASK_RXF | INT_MASK_RXE | \
85 INT_MASK_TXC | INT_MASK_RXC | \
89 /* packet length register */
90 #define PACKETLEN_MIN(min) (((min) & 0xffff) << 16)
91 #define PACKETLEN_MAX(max) (((max) & 0xffff) << 0)
92 #define PACKETLEN_MIN_MAX(min, max) (PACKETLEN_MIN(min) | \
95 /* transmit buffer number register */
96 #define TX_BD_NUM_VAL(x) (((x) <= 0x80) ? (x) : 0x80)
98 /* control module mode register */
99 #define CTRLMODER_PASSALL (1 << 0) /* pass all receive frames */
100 #define CTRLMODER_RXFLOW (1 << 1) /* receive control flow */
101 #define CTRLMODER_TXFLOW (1 << 2) /* transmit control flow */
103 /* MII mode register */
104 #define MIIMODER_CLKDIV(x) ((x) & 0xfe) /* needs to be an even number */
105 #define MIIMODER_NOPRE (1 << 8) /* no preamble */
107 /* MII command register */
108 #define MIICOMMAND_SCAN (1 << 0) /* scan status */
109 #define MIICOMMAND_READ (1 << 1) /* read status */
110 #define MIICOMMAND_WRITE (1 << 2) /* write control data */
112 /* MII address register */
113 #define MIIADDRESS_FIAD(x) (((x) & 0x1f) << 0)
114 #define MIIADDRESS_RGAD(x) (((x) & 0x1f) << 8)
115 #define MIIADDRESS_ADDR(phy, reg) (MIIADDRESS_FIAD(phy) | \
116 MIIADDRESS_RGAD(reg))
118 /* MII transmit data register */
119 #define MIITX_DATA_VAL(x) ((x) & 0xffff)
121 /* MII receive data register */
122 #define MIIRX_DATA_VAL(x) ((x) & 0xffff)
124 /* MII status register */
125 #define MIISTATUS_LINKFAIL (1 << 0)
126 #define MIISTATUS_BUSY (1 << 1)
127 #define MIISTATUS_INVALID (1 << 2)
129 /* TX buffer descriptor */
130 #define TX_BD_CS (1 << 0) /* carrier sense lost */
131 #define TX_BD_DF (1 << 1) /* defer indication */
132 #define TX_BD_LC (1 << 2) /* late collision */
133 #define TX_BD_RL (1 << 3) /* retransmission limit */
134 #define TX_BD_RETRY_MASK (0x00f0)
135 #define TX_BD_RETRY(x) (((x) & 0x00f0) >> 4)
136 #define TX_BD_UR (1 << 8) /* transmitter underrun */
137 #define TX_BD_CRC (1 << 11) /* TX CRC enable */
138 #define TX_BD_PAD (1 << 12) /* pad enable for short packets */
139 #define TX_BD_WRAP (1 << 13)
140 #define TX_BD_IRQ (1 << 14) /* interrupt request enable */
141 #define TX_BD_READY (1 << 15) /* TX buffer ready */
142 #define TX_BD_LEN(x) (((x) & 0xffff) << 16)
143 #define TX_BD_LEN_MASK (0xffff << 16)
145 #define TX_BD_STATS (TX_BD_CS | TX_BD_DF | TX_BD_LC | \
146 TX_BD_RL | TX_BD_RETRY_MASK | TX_BD_UR)
148 /* RX buffer descriptor */
149 #define RX_BD_LC (1 << 0) /* late collision */
150 #define RX_BD_CRC (1 << 1) /* RX CRC error */
151 #define RX_BD_SF (1 << 2) /* short frame */
152 #define RX_BD_TL (1 << 3) /* too long */
153 #define RX_BD_DN (1 << 4) /* dribble nibble */
154 #define RX_BD_IS (1 << 5) /* invalid symbol */
155 #define RX_BD_OR (1 << 6) /* receiver overrun */
156 #define RX_BD_MISS (1 << 7)
157 #define RX_BD_CF (1 << 8) /* control frame */
158 #define RX_BD_WRAP (1 << 13)
159 #define RX_BD_IRQ (1 << 14) /* interrupt request enable */
160 #define RX_BD_EMPTY (1 << 15)
161 #define RX_BD_LEN(x) (((x) & 0xffff) << 16)
163 #define RX_BD_STATS (RX_BD_LC | RX_BD_CRC | RX_BD_SF | RX_BD_TL | \
164 RX_BD_DN | RX_BD_IS | RX_BD_OR | RX_BD_MISS)
166 #define ETHOC_BUFSIZ 1536
167 #define ETHOC_ZLEN 64
168 #define ETHOC_BD_BASE 0x400
169 #define ETHOC_TIMEOUT (HZ / 2)
170 #define ETHOC_MII_TIMEOUT (1 + (HZ / 5))
173 * struct ethoc - driver-private device structure
174 * @iobase: pointer to I/O memory region
175 * @membase: pointer to buffer memory region
176 * @dma_alloc: dma allocated buffer size
177 * @io_region_size: I/O memory region size
178 * @num_tx: number of send buffers
179 * @cur_tx: last send buffer written
180 * @dty_tx: last buffer actually sent
181 * @num_rx: number of receive buffers
182 * @cur_rx: current receive buffer
183 * @vma: pointer to array of virtual memory addresses for buffers
184 * @netdev: pointer to network device structure
185 * @napi: NAPI structure
186 * @msg_enable: device state flags
187 * @rx_lock: receive lock
190 * @mdio: MDIO bus for PHY access
191 * @phy_id: address of attached PHY
194 void __iomem *iobase;
195 void __iomem *membase;
197 resource_size_t io_region_size;
208 struct net_device *netdev;
209 struct napi_struct napi;
215 struct phy_device *phy;
216 struct mii_bus *mdio;
221 * struct ethoc_bd - buffer descriptor
222 * @stat: buffer statistics
223 * @addr: physical memory address
230 static inline u32 ethoc_read(struct ethoc *dev, loff_t offset)
232 return ioread32(dev->iobase + offset);
235 static inline void ethoc_write(struct ethoc *dev, loff_t offset, u32 data)
237 iowrite32(data, dev->iobase + offset);
240 static inline void ethoc_read_bd(struct ethoc *dev, int index,
243 loff_t offset = ETHOC_BD_BASE + (index * sizeof(struct ethoc_bd));
244 bd->stat = ethoc_read(dev, offset + 0);
245 bd->addr = ethoc_read(dev, offset + 4);
248 static inline void ethoc_write_bd(struct ethoc *dev, int index,
249 const struct ethoc_bd *bd)
251 loff_t offset = ETHOC_BD_BASE + (index * sizeof(struct ethoc_bd));
252 ethoc_write(dev, offset + 0, bd->stat);
253 ethoc_write(dev, offset + 4, bd->addr);
256 static inline void ethoc_enable_irq(struct ethoc *dev, u32 mask)
258 u32 imask = ethoc_read(dev, INT_MASK);
260 ethoc_write(dev, INT_MASK, imask);
263 static inline void ethoc_disable_irq(struct ethoc *dev, u32 mask)
265 u32 imask = ethoc_read(dev, INT_MASK);
267 ethoc_write(dev, INT_MASK, imask);
270 static inline void ethoc_ack_irq(struct ethoc *dev, u32 mask)
272 ethoc_write(dev, INT_SOURCE, mask);
275 static inline void ethoc_enable_rx_and_tx(struct ethoc *dev)
277 u32 mode = ethoc_read(dev, MODER);
278 mode |= MODER_RXEN | MODER_TXEN;
279 ethoc_write(dev, MODER, mode);
282 static inline void ethoc_disable_rx_and_tx(struct ethoc *dev)
284 u32 mode = ethoc_read(dev, MODER);
285 mode &= ~(MODER_RXEN | MODER_TXEN);
286 ethoc_write(dev, MODER, mode);
289 static int ethoc_init_ring(struct ethoc *dev, unsigned long mem_start)
299 ethoc_write(dev, TX_BD_NUM, dev->num_tx);
301 /* setup transmission buffers */
303 bd.stat = TX_BD_IRQ | TX_BD_CRC;
306 for (i = 0; i < dev->num_tx; i++) {
307 if (i == dev->num_tx - 1)
308 bd.stat |= TX_BD_WRAP;
310 ethoc_write_bd(dev, i, &bd);
311 bd.addr += ETHOC_BUFSIZ;
317 bd.stat = RX_BD_EMPTY | RX_BD_IRQ;
319 for (i = 0; i < dev->num_rx; i++) {
320 if (i == dev->num_rx - 1)
321 bd.stat |= RX_BD_WRAP;
323 ethoc_write_bd(dev, dev->num_tx + i, &bd);
324 bd.addr += ETHOC_BUFSIZ;
326 dev->vma[dev->num_tx + i] = vma;
333 static int ethoc_reset(struct ethoc *dev)
337 /* TODO: reset controller? */
339 ethoc_disable_rx_and_tx(dev);
341 /* TODO: setup registers */
343 /* enable FCS generation and automatic padding */
344 mode = ethoc_read(dev, MODER);
345 mode |= MODER_CRC | MODER_PAD;
346 ethoc_write(dev, MODER, mode);
348 /* set full-duplex mode */
349 mode = ethoc_read(dev, MODER);
351 ethoc_write(dev, MODER, mode);
352 ethoc_write(dev, IPGT, 0x15);
354 ethoc_ack_irq(dev, INT_MASK_ALL);
355 ethoc_enable_irq(dev, INT_MASK_ALL);
356 ethoc_enable_rx_and_tx(dev);
360 static unsigned int ethoc_update_rx_stats(struct ethoc *dev,
363 struct net_device *netdev = dev->netdev;
364 unsigned int ret = 0;
366 if (bd->stat & RX_BD_TL) {
367 dev_err(&netdev->dev, "RX: frame too long\n");
368 netdev->stats.rx_length_errors++;
372 if (bd->stat & RX_BD_SF) {
373 dev_err(&netdev->dev, "RX: frame too short\n");
374 netdev->stats.rx_length_errors++;
378 if (bd->stat & RX_BD_DN) {
379 dev_err(&netdev->dev, "RX: dribble nibble\n");
380 netdev->stats.rx_frame_errors++;
383 if (bd->stat & RX_BD_CRC) {
384 dev_err(&netdev->dev, "RX: wrong CRC\n");
385 netdev->stats.rx_crc_errors++;
389 if (bd->stat & RX_BD_OR) {
390 dev_err(&netdev->dev, "RX: overrun\n");
391 netdev->stats.rx_over_errors++;
395 if (bd->stat & RX_BD_MISS)
396 netdev->stats.rx_missed_errors++;
398 if (bd->stat & RX_BD_LC) {
399 dev_err(&netdev->dev, "RX: late collision\n");
400 netdev->stats.collisions++;
407 static int ethoc_rx(struct net_device *dev, int limit)
409 struct ethoc *priv = netdev_priv(dev);
412 for (count = 0; count < limit; ++count) {
416 entry = priv->num_tx + (priv->cur_rx % priv->num_rx);
417 ethoc_read_bd(priv, entry, &bd);
418 if (bd.stat & RX_BD_EMPTY)
421 if (ethoc_update_rx_stats(priv, &bd) == 0) {
422 int size = bd.stat >> 16;
425 size -= 4; /* strip the CRC */
426 skb = netdev_alloc_skb_ip_align(dev, size);
429 void *src = priv->vma[entry];
430 memcpy_fromio(skb_put(skb, size), src, size);
431 skb->protocol = eth_type_trans(skb, dev);
432 dev->stats.rx_packets++;
433 dev->stats.rx_bytes += size;
434 netif_receive_skb(skb);
437 dev_warn(&dev->dev, "low on memory - "
440 dev->stats.rx_dropped++;
445 /* clear the buffer descriptor so it can be reused */
446 bd.stat &= ~RX_BD_STATS;
447 bd.stat |= RX_BD_EMPTY;
448 ethoc_write_bd(priv, entry, &bd);
455 static int ethoc_update_tx_stats(struct ethoc *dev, struct ethoc_bd *bd)
457 struct net_device *netdev = dev->netdev;
459 if (bd->stat & TX_BD_LC) {
460 dev_err(&netdev->dev, "TX: late collision\n");
461 netdev->stats.tx_window_errors++;
464 if (bd->stat & TX_BD_RL) {
465 dev_err(&netdev->dev, "TX: retransmit limit\n");
466 netdev->stats.tx_aborted_errors++;
469 if (bd->stat & TX_BD_UR) {
470 dev_err(&netdev->dev, "TX: underrun\n");
471 netdev->stats.tx_fifo_errors++;
474 if (bd->stat & TX_BD_CS) {
475 dev_err(&netdev->dev, "TX: carrier sense lost\n");
476 netdev->stats.tx_carrier_errors++;
479 if (bd->stat & TX_BD_STATS)
480 netdev->stats.tx_errors++;
482 netdev->stats.collisions += (bd->stat >> 4) & 0xf;
483 netdev->stats.tx_bytes += bd->stat >> 16;
484 netdev->stats.tx_packets++;
488 static void ethoc_tx(struct net_device *dev)
490 struct ethoc *priv = netdev_priv(dev);
492 spin_lock(&priv->lock);
494 while (priv->dty_tx != priv->cur_tx) {
495 unsigned int entry = priv->dty_tx % priv->num_tx;
498 ethoc_read_bd(priv, entry, &bd);
499 if (bd.stat & TX_BD_READY)
502 entry = (++priv->dty_tx) % priv->num_tx;
503 (void)ethoc_update_tx_stats(priv, &bd);
506 if ((priv->cur_tx - priv->dty_tx) <= (priv->num_tx / 2))
507 netif_wake_queue(dev);
509 ethoc_ack_irq(priv, INT_MASK_TX);
510 spin_unlock(&priv->lock);
513 static irqreturn_t ethoc_interrupt(int irq, void *dev_id)
515 struct net_device *dev = dev_id;
516 struct ethoc *priv = netdev_priv(dev);
519 ethoc_disable_irq(priv, INT_MASK_ALL);
520 pending = ethoc_read(priv, INT_SOURCE);
521 if (unlikely(pending == 0)) {
522 ethoc_enable_irq(priv, INT_MASK_ALL);
526 ethoc_ack_irq(priv, pending);
528 if (pending & INT_MASK_BUSY) {
529 dev_err(&dev->dev, "packet dropped\n");
530 dev->stats.rx_dropped++;
533 if (pending & INT_MASK_RX) {
534 if (napi_schedule_prep(&priv->napi))
535 __napi_schedule(&priv->napi);
537 ethoc_enable_irq(priv, INT_MASK_RX);
540 if (pending & INT_MASK_TX)
543 ethoc_enable_irq(priv, INT_MASK_ALL & ~INT_MASK_RX);
547 static int ethoc_get_mac_address(struct net_device *dev, void *addr)
549 struct ethoc *priv = netdev_priv(dev);
550 u8 *mac = (u8 *)addr;
553 reg = ethoc_read(priv, MAC_ADDR0);
554 mac[2] = (reg >> 24) & 0xff;
555 mac[3] = (reg >> 16) & 0xff;
556 mac[4] = (reg >> 8) & 0xff;
557 mac[5] = (reg >> 0) & 0xff;
559 reg = ethoc_read(priv, MAC_ADDR1);
560 mac[0] = (reg >> 8) & 0xff;
561 mac[1] = (reg >> 0) & 0xff;
566 static int ethoc_poll(struct napi_struct *napi, int budget)
568 struct ethoc *priv = container_of(napi, struct ethoc, napi);
571 work_done = ethoc_rx(priv->netdev, budget);
572 if (work_done < budget) {
573 ethoc_enable_irq(priv, INT_MASK_RX);
580 static int ethoc_mdio_read(struct mii_bus *bus, int phy, int reg)
582 unsigned long timeout = jiffies + ETHOC_MII_TIMEOUT;
583 struct ethoc *priv = bus->priv;
585 ethoc_write(priv, MIIADDRESS, MIIADDRESS_ADDR(phy, reg));
586 ethoc_write(priv, MIICOMMAND, MIICOMMAND_READ);
588 while (time_before(jiffies, timeout)) {
589 u32 status = ethoc_read(priv, MIISTATUS);
590 if (!(status & MIISTATUS_BUSY)) {
591 u32 data = ethoc_read(priv, MIIRX_DATA);
592 /* reset MII command register */
593 ethoc_write(priv, MIICOMMAND, 0);
603 static int ethoc_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
605 unsigned long timeout = jiffies + ETHOC_MII_TIMEOUT;
606 struct ethoc *priv = bus->priv;
608 ethoc_write(priv, MIIADDRESS, MIIADDRESS_ADDR(phy, reg));
609 ethoc_write(priv, MIITX_DATA, val);
610 ethoc_write(priv, MIICOMMAND, MIICOMMAND_WRITE);
612 while (time_before(jiffies, timeout)) {
613 u32 stat = ethoc_read(priv, MIISTATUS);
614 if (!(stat & MIISTATUS_BUSY)) {
615 /* reset MII command register */
616 ethoc_write(priv, MIICOMMAND, 0);
626 static int ethoc_mdio_reset(struct mii_bus *bus)
631 static void ethoc_mdio_poll(struct net_device *dev)
635 static int __devinit ethoc_mdio_probe(struct net_device *dev)
637 struct ethoc *priv = netdev_priv(dev);
638 struct phy_device *phy;
641 if (priv->phy_id != -1) {
642 phy = priv->mdio->phy_map[priv->phy_id];
644 phy = phy_find_first(priv->mdio);
648 dev_err(&dev->dev, "no PHY found\n");
652 err = phy_connect_direct(dev, phy, ethoc_mdio_poll, 0,
653 PHY_INTERFACE_MODE_GMII);
655 dev_err(&dev->dev, "could not attach to PHY\n");
663 static int ethoc_open(struct net_device *dev)
665 struct ethoc *priv = netdev_priv(dev);
668 ret = request_irq(dev->irq, ethoc_interrupt, IRQF_SHARED,
673 ethoc_init_ring(priv, dev->mem_start);
676 if (netif_queue_stopped(dev)) {
677 dev_dbg(&dev->dev, " resuming queue\n");
678 netif_wake_queue(dev);
680 dev_dbg(&dev->dev, " starting queue\n");
681 netif_start_queue(dev);
684 phy_start(priv->phy);
685 napi_enable(&priv->napi);
687 if (netif_msg_ifup(priv)) {
688 dev_info(&dev->dev, "I/O: %08lx Memory: %08lx-%08lx\n",
689 dev->base_addr, dev->mem_start, dev->mem_end);
695 static int ethoc_stop(struct net_device *dev)
697 struct ethoc *priv = netdev_priv(dev);
699 napi_disable(&priv->napi);
704 ethoc_disable_rx_and_tx(priv);
705 free_irq(dev->irq, dev);
707 if (!netif_queue_stopped(dev))
708 netif_stop_queue(dev);
713 static int ethoc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
715 struct ethoc *priv = netdev_priv(dev);
716 struct mii_ioctl_data *mdio = if_mii(ifr);
717 struct phy_device *phy = NULL;
719 if (!netif_running(dev))
722 if (cmd != SIOCGMIIPHY) {
723 if (mdio->phy_id >= PHY_MAX_ADDR)
726 phy = priv->mdio->phy_map[mdio->phy_id];
733 return phy_mii_ioctl(phy, ifr, cmd);
736 static int ethoc_config(struct net_device *dev, struct ifmap *map)
741 static int ethoc_set_mac_address(struct net_device *dev, void *addr)
743 struct ethoc *priv = netdev_priv(dev);
744 u8 *mac = (u8 *)addr;
746 ethoc_write(priv, MAC_ADDR0, (mac[2] << 24) | (mac[3] << 16) |
747 (mac[4] << 8) | (mac[5] << 0));
748 ethoc_write(priv, MAC_ADDR1, (mac[0] << 8) | (mac[1] << 0));
753 static void ethoc_set_multicast_list(struct net_device *dev)
755 struct ethoc *priv = netdev_priv(dev);
756 u32 mode = ethoc_read(priv, MODER);
757 struct netdev_hw_addr *ha;
758 u32 hash[2] = { 0, 0 };
760 /* set loopback mode if requested */
761 if (dev->flags & IFF_LOOPBACK)
766 /* receive broadcast frames if requested */
767 if (dev->flags & IFF_BROADCAST)
772 /* enable promiscuous mode if requested */
773 if (dev->flags & IFF_PROMISC)
778 ethoc_write(priv, MODER, mode);
780 /* receive multicast frames */
781 if (dev->flags & IFF_ALLMULTI) {
782 hash[0] = 0xffffffff;
783 hash[1] = 0xffffffff;
785 netdev_for_each_mc_addr(ha, dev) {
786 u32 crc = ether_crc(ETH_ALEN, ha->addr);
787 int bit = (crc >> 26) & 0x3f;
788 hash[bit >> 5] |= 1 << (bit & 0x1f);
792 ethoc_write(priv, ETH_HASH0, hash[0]);
793 ethoc_write(priv, ETH_HASH1, hash[1]);
796 static int ethoc_change_mtu(struct net_device *dev, int new_mtu)
801 static void ethoc_tx_timeout(struct net_device *dev)
803 struct ethoc *priv = netdev_priv(dev);
804 u32 pending = ethoc_read(priv, INT_SOURCE);
806 ethoc_interrupt(dev->irq, dev);
809 static struct net_device_stats *ethoc_stats(struct net_device *dev)
814 static netdev_tx_t ethoc_start_xmit(struct sk_buff *skb, struct net_device *dev)
816 struct ethoc *priv = netdev_priv(dev);
821 if (unlikely(skb->len > ETHOC_BUFSIZ)) {
822 dev->stats.tx_errors++;
826 entry = priv->cur_tx % priv->num_tx;
827 spin_lock_irq(&priv->lock);
830 ethoc_read_bd(priv, entry, &bd);
831 if (unlikely(skb->len < ETHOC_ZLEN))
832 bd.stat |= TX_BD_PAD;
834 bd.stat &= ~TX_BD_PAD;
836 dest = priv->vma[entry];
837 memcpy_toio(dest, skb->data, skb->len);
839 bd.stat &= ~(TX_BD_STATS | TX_BD_LEN_MASK);
840 bd.stat |= TX_BD_LEN(skb->len);
841 ethoc_write_bd(priv, entry, &bd);
843 bd.stat |= TX_BD_READY;
844 ethoc_write_bd(priv, entry, &bd);
846 if (priv->cur_tx == (priv->dty_tx + priv->num_tx)) {
847 dev_dbg(&dev->dev, "stopping queue\n");
848 netif_stop_queue(dev);
851 spin_unlock_irq(&priv->lock);
857 static const struct net_device_ops ethoc_netdev_ops = {
858 .ndo_open = ethoc_open,
859 .ndo_stop = ethoc_stop,
860 .ndo_do_ioctl = ethoc_ioctl,
861 .ndo_set_config = ethoc_config,
862 .ndo_set_mac_address = ethoc_set_mac_address,
863 .ndo_set_multicast_list = ethoc_set_multicast_list,
864 .ndo_change_mtu = ethoc_change_mtu,
865 .ndo_tx_timeout = ethoc_tx_timeout,
866 .ndo_get_stats = ethoc_stats,
867 .ndo_start_xmit = ethoc_start_xmit,
871 * ethoc_probe() - initialize OpenCores ethernet MAC
872 * pdev: platform device
874 static int __devinit ethoc_probe(struct platform_device *pdev)
876 struct net_device *netdev = NULL;
877 struct resource *res = NULL;
878 struct resource *mmio = NULL;
879 struct resource *mem = NULL;
880 struct ethoc *priv = NULL;
885 /* allocate networking device */
886 netdev = alloc_etherdev(sizeof(struct ethoc));
888 dev_err(&pdev->dev, "cannot allocate network device\n");
893 SET_NETDEV_DEV(netdev, &pdev->dev);
894 platform_set_drvdata(pdev, netdev);
896 /* obtain I/O memory space */
897 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
899 dev_err(&pdev->dev, "cannot obtain I/O memory space\n");
904 mmio = devm_request_mem_region(&pdev->dev, res->start,
905 resource_size(res), res->name);
907 dev_err(&pdev->dev, "cannot request I/O memory space\n");
912 netdev->base_addr = mmio->start;
914 /* obtain buffer memory space */
915 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
917 mem = devm_request_mem_region(&pdev->dev, res->start,
918 resource_size(res), res->name);
920 dev_err(&pdev->dev, "cannot request memory space\n");
925 netdev->mem_start = mem->start;
926 netdev->mem_end = mem->end;
930 /* obtain device IRQ number */
931 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
933 dev_err(&pdev->dev, "cannot obtain IRQ\n");
938 netdev->irq = res->start;
940 /* setup driver-private data */
941 priv = netdev_priv(netdev);
942 priv->netdev = netdev;
944 priv->io_region_size = mmio->end - mmio->start + 1;
946 priv->iobase = devm_ioremap_nocache(&pdev->dev, netdev->base_addr,
947 resource_size(mmio));
949 dev_err(&pdev->dev, "cannot remap I/O memory space\n");
954 if (netdev->mem_end) {
955 priv->membase = devm_ioremap_nocache(&pdev->dev,
956 netdev->mem_start, resource_size(mem));
957 if (!priv->membase) {
958 dev_err(&pdev->dev, "cannot remap memory space\n");
963 /* Allocate buffer memory */
964 priv->membase = dmam_alloc_coherent(&pdev->dev,
965 buffer_size, (void *)&netdev->mem_start,
967 if (!priv->membase) {
968 dev_err(&pdev->dev, "cannot allocate %dB buffer\n",
973 netdev->mem_end = netdev->mem_start + buffer_size;
974 priv->dma_alloc = buffer_size;
977 /* calculate the number of TX/RX buffers, maximum 128 supported */
978 num_bd = min_t(unsigned int,
979 128, (netdev->mem_end - netdev->mem_start + 1) / ETHOC_BUFSIZ);
980 priv->num_tx = max(2, num_bd / 4);
981 priv->num_rx = num_bd - priv->num_tx;
983 priv->vma = devm_kzalloc(&pdev->dev, num_bd*sizeof(void*), GFP_KERNEL);
989 /* Allow the platform setup code to pass in a MAC address. */
990 if (pdev->dev.platform_data) {
991 struct ethoc_platform_data *pdata =
992 (struct ethoc_platform_data *)pdev->dev.platform_data;
993 memcpy(netdev->dev_addr, pdata->hwaddr, IFHWADDRLEN);
994 priv->phy_id = pdata->phy_id;
997 /* Check that the given MAC address is valid. If it isn't, read the
998 * current MAC from the controller. */
999 if (!is_valid_ether_addr(netdev->dev_addr))
1000 ethoc_get_mac_address(netdev, netdev->dev_addr);
1002 /* Check the MAC again for validity, if it still isn't choose and
1003 * program a random one. */
1004 if (!is_valid_ether_addr(netdev->dev_addr))
1005 random_ether_addr(netdev->dev_addr);
1007 ethoc_set_mac_address(netdev, netdev->dev_addr);
1009 /* register MII bus */
1010 priv->mdio = mdiobus_alloc();
1016 priv->mdio->name = "ethoc-mdio";
1017 snprintf(priv->mdio->id, MII_BUS_ID_SIZE, "%s-%d",
1018 priv->mdio->name, pdev->id);
1019 priv->mdio->read = ethoc_mdio_read;
1020 priv->mdio->write = ethoc_mdio_write;
1021 priv->mdio->reset = ethoc_mdio_reset;
1022 priv->mdio->priv = priv;
1024 priv->mdio->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
1025 if (!priv->mdio->irq) {
1030 for (phy = 0; phy < PHY_MAX_ADDR; phy++)
1031 priv->mdio->irq[phy] = PHY_POLL;
1033 ret = mdiobus_register(priv->mdio);
1035 dev_err(&netdev->dev, "failed to register MDIO bus\n");
1039 ret = ethoc_mdio_probe(netdev);
1041 dev_err(&netdev->dev, "failed to probe MDIO bus\n");
1045 ether_setup(netdev);
1047 /* setup the net_device structure */
1048 netdev->netdev_ops = ðoc_netdev_ops;
1049 netdev->watchdog_timeo = ETHOC_TIMEOUT;
1050 netdev->features |= 0;
1053 netif_napi_add(netdev, &priv->napi, ethoc_poll, 64);
1055 spin_lock_init(&priv->rx_lock);
1056 spin_lock_init(&priv->lock);
1058 ret = register_netdev(netdev);
1060 dev_err(&netdev->dev, "failed to register interface\n");
1067 netif_napi_del(&priv->napi);
1069 mdiobus_unregister(priv->mdio);
1071 kfree(priv->mdio->irq);
1072 mdiobus_free(priv->mdio);
1074 free_netdev(netdev);
1080 * ethoc_remove() - shutdown OpenCores ethernet MAC
1081 * @pdev: platform device
1083 static int __devexit ethoc_remove(struct platform_device *pdev)
1085 struct net_device *netdev = platform_get_drvdata(pdev);
1086 struct ethoc *priv = netdev_priv(netdev);
1088 platform_set_drvdata(pdev, NULL);
1091 netif_napi_del(&priv->napi);
1092 phy_disconnect(priv->phy);
1096 mdiobus_unregister(priv->mdio);
1097 kfree(priv->mdio->irq);
1098 mdiobus_free(priv->mdio);
1100 unregister_netdev(netdev);
1101 free_netdev(netdev);
1108 static int ethoc_suspend(struct platform_device *pdev, pm_message_t state)
1113 static int ethoc_resume(struct platform_device *pdev)
1118 # define ethoc_suspend NULL
1119 # define ethoc_resume NULL
1122 static struct platform_driver ethoc_driver = {
1123 .probe = ethoc_probe,
1124 .remove = __devexit_p(ethoc_remove),
1125 .suspend = ethoc_suspend,
1126 .resume = ethoc_resume,
1132 static int __init ethoc_init(void)
1134 return platform_driver_register(ðoc_driver);
1137 static void __exit ethoc_exit(void)
1139 platform_driver_unregister(ðoc_driver);
1142 module_init(ethoc_init);
1143 module_exit(ethoc_exit);
1145 MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>");
1146 MODULE_DESCRIPTION("OpenCores Ethernet MAC driver");
1147 MODULE_LICENSE("GPL v2");