2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
5 * Right now, I am very wasteful with the buffers. I allocate memory
6 * pages and then divide them into 2K frame buffers. This way I know I
7 * have buffers large enough to hold one frame within one buffer descriptor.
8 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
9 * will be much more memory efficient and will easily handle lots of
12 * Much better multiple PHY support by Magnus Damm.
13 * Copyright (c) 2000 Ericsson Radio Systems AB.
15 * Support for FEC controller of ColdFire processors.
16 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
18 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
19 * Copyright (c) 2004-2006 Macq Electronique SA.
21 * Copyright (C) 2010 Freescale Semiconductor, Inc.
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/string.h>
27 #include <linux/ptrace.h>
28 #include <linux/errno.h>
29 #include <linux/ioport.h>
30 #include <linux/slab.h>
31 #include <linux/interrupt.h>
32 #include <linux/pci.h>
33 #include <linux/init.h>
34 #include <linux/delay.h>
35 #include <linux/netdevice.h>
36 #include <linux/etherdevice.h>
37 #include <linux/skbuff.h>
38 #include <linux/spinlock.h>
39 #include <linux/workqueue.h>
40 #include <linux/bitops.h>
42 #include <linux/irq.h>
43 #include <linux/clk.h>
44 #include <linux/platform_device.h>
45 #include <linux/phy.h>
46 #include <linux/fec.h>
48 #include <asm/cacheflush.h>
51 #include <asm/coldfire.h>
52 #include <asm/mcfsim.h>
57 #if defined(CONFIG_ARM)
58 #define FEC_ALIGNMENT 0xf
60 #define FEC_ALIGNMENT 0x3
63 #define DRIVER_NAME "fec"
65 /* Controller is ENET-MAC */
66 #define FEC_QUIRK_ENET_MAC (1 << 0)
67 /* Controller needs driver to swap frame */
68 #define FEC_QUIRK_SWAP_FRAME (1 << 1)
70 static struct platform_device_id fec_devtype[] = {
76 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME,
81 static unsigned char macaddr[ETH_ALEN];
82 module_param_array(macaddr, byte, NULL, 0);
83 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
85 #if defined(CONFIG_M5272)
87 * Some hardware gets it MAC address out of local flash memory.
88 * if this is non-zero then assume it is the address to get MAC from.
90 #if defined(CONFIG_NETtel)
91 #define FEC_FLASHMAC 0xf0006006
92 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
93 #define FEC_FLASHMAC 0xf0006000
94 #elif defined(CONFIG_CANCam)
95 #define FEC_FLASHMAC 0xf0020000
96 #elif defined (CONFIG_M5272C3)
97 #define FEC_FLASHMAC (0xffe04000 + 4)
98 #elif defined(CONFIG_MOD5272)
99 #define FEC_FLASHMAC 0xffc0406b
101 #define FEC_FLASHMAC 0
103 #endif /* CONFIG_M5272 */
105 /* The number of Tx and Rx buffers. These are allocated from the page
106 * pool. The code may assume these are power of two, so it it best
107 * to keep them that size.
108 * We don't need to allocate pages for the transmitter. We just use
109 * the skbuffer directly.
111 #define FEC_ENET_RX_PAGES 8
112 #define FEC_ENET_RX_FRSIZE 2048
113 #define FEC_ENET_RX_FRPPG (PAGE_SIZE / FEC_ENET_RX_FRSIZE)
114 #define RX_RING_SIZE (FEC_ENET_RX_FRPPG * FEC_ENET_RX_PAGES)
115 #define FEC_ENET_TX_FRSIZE 2048
116 #define FEC_ENET_TX_FRPPG (PAGE_SIZE / FEC_ENET_TX_FRSIZE)
117 #define TX_RING_SIZE 16 /* Must be power of two */
118 #define TX_RING_MOD_MASK 15 /* for this to work */
120 #if (((RX_RING_SIZE + TX_RING_SIZE) * 8) > PAGE_SIZE)
121 #error "FEC: descriptor ring size constants too large"
124 /* Interrupt events/masks. */
125 #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
126 #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
127 #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
128 #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
129 #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
130 #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
131 #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
132 #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
133 #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
134 #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
136 #define FEC_DEFAULT_IMASK (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII)
138 /* The FEC stores dest/src/type, data, and checksum for receive packets.
140 #define PKT_MAXBUF_SIZE 1518
141 #define PKT_MINBUF_SIZE 64
142 #define PKT_MAXBLR_SIZE 1520
146 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
147 * size bits. Other FEC hardware does not, so we need to take that into
148 * account when setting it.
150 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
151 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM)
152 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
154 #define OPT_FRAME_SIZE 0
157 /* The FEC buffer descriptors track the ring buffers. The rx_bd_base and
158 * tx_bd_base always point to the base of the buffer descriptors. The
159 * cur_rx and cur_tx point to the currently available buffer.
160 * The dirty_tx tracks the current buffer that is being sent by the
161 * controller. The cur_tx and dirty_tx are equal under both completely
162 * empty and completely full conditions. The empty/ready indicator in
163 * the buffer descriptor determines the actual condition.
165 struct fec_enet_private {
166 /* Hardware registers of the FEC device */
169 struct net_device *netdev;
173 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
174 unsigned char *tx_bounce[TX_RING_SIZE];
175 struct sk_buff* tx_skbuff[TX_RING_SIZE];
176 struct sk_buff* rx_skbuff[RX_RING_SIZE];
180 /* CPM dual port RAM relative addresses */
182 /* Address of Rx and Tx buffers */
183 struct bufdesc *rx_bd_base;
184 struct bufdesc *tx_bd_base;
185 /* The next free ring entry */
186 struct bufdesc *cur_rx, *cur_tx;
187 /* The ring entries to be free()ed */
188 struct bufdesc *dirty_tx;
191 /* hold while accessing the HW like ringbuffer for tx/rx but not MAC */
194 struct platform_device *pdev;
198 /* Phylib and MDIO interface */
199 struct mii_bus *mii_bus;
200 struct phy_device *phy_dev;
203 phy_interface_t phy_interface;
206 struct completion mdio_done;
209 /* FEC MII MMFR bits definition */
210 #define FEC_MMFR_ST (1 << 30)
211 #define FEC_MMFR_OP_READ (2 << 28)
212 #define FEC_MMFR_OP_WRITE (1 << 28)
213 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23)
214 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18)
215 #define FEC_MMFR_TA (2 << 16)
216 #define FEC_MMFR_DATA(v) (v & 0xffff)
218 #define FEC_MII_TIMEOUT 1000 /* us */
220 /* Transmitter timeout */
221 #define TX_TIMEOUT (2 * HZ)
223 static void *swap_buffer(void *bufaddr, int len)
226 unsigned int *buf = bufaddr;
228 for (i = 0; i < (len + 3) / 4; i++, buf++)
229 *buf = cpu_to_be32(*buf);
235 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
237 struct fec_enet_private *fep = netdev_priv(ndev);
238 const struct platform_device_id *id_entry =
239 platform_get_device_id(fep->pdev);
242 unsigned short status;
246 /* Link is down or autonegotiation is in progress. */
247 return NETDEV_TX_BUSY;
250 spin_lock_irqsave(&fep->hw_lock, flags);
251 /* Fill in a Tx ring entry */
254 status = bdp->cbd_sc;
256 if (status & BD_ENET_TX_READY) {
257 /* Ooops. All transmit buffers are full. Bail out.
258 * This should not happen, since ndev->tbusy should be set.
260 printk("%s: tx queue full!.\n", ndev->name);
261 spin_unlock_irqrestore(&fep->hw_lock, flags);
262 return NETDEV_TX_BUSY;
265 /* Clear all of the status flags */
266 status &= ~BD_ENET_TX_STATS;
268 /* Set buffer length and buffer pointer */
270 bdp->cbd_datlen = skb->len;
273 * On some FEC implementations data must be aligned on
274 * 4-byte boundaries. Use bounce buffers to copy data
275 * and get it aligned. Ugh.
277 if (((unsigned long) bufaddr) & FEC_ALIGNMENT) {
279 index = bdp - fep->tx_bd_base;
280 memcpy(fep->tx_bounce[index], skb->data, skb->len);
281 bufaddr = fep->tx_bounce[index];
285 * Some design made an incorrect assumption on endian mode of
286 * the system that it's running on. As the result, driver has to
287 * swap every frame going to and coming from the controller.
289 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
290 swap_buffer(bufaddr, skb->len);
292 /* Save skb pointer */
293 fep->tx_skbuff[fep->skb_cur] = skb;
295 ndev->stats.tx_bytes += skb->len;
296 fep->skb_cur = (fep->skb_cur+1) & TX_RING_MOD_MASK;
298 /* Push the data cache so the CPM does not get stale memory
301 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, bufaddr,
302 FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE);
304 /* Send it on its way. Tell FEC it's ready, interrupt when done,
305 * it's the last BD of the frame, and to put the CRC on the end.
307 status |= (BD_ENET_TX_READY | BD_ENET_TX_INTR
308 | BD_ENET_TX_LAST | BD_ENET_TX_TC);
309 bdp->cbd_sc = status;
311 /* Trigger transmission start */
312 writel(0, fep->hwp + FEC_X_DES_ACTIVE);
314 /* If this was the last BD in the ring, start at the beginning again. */
315 if (status & BD_ENET_TX_WRAP)
316 bdp = fep->tx_bd_base;
320 if (bdp == fep->dirty_tx) {
322 netif_stop_queue(ndev);
327 skb_tx_timestamp(skb);
329 spin_unlock_irqrestore(&fep->hw_lock, flags);
334 /* This function is called to start or restart the FEC during a link
335 * change. This only happens when switching between half and full
339 fec_restart(struct net_device *ndev, int duplex)
341 struct fec_enet_private *fep = netdev_priv(ndev);
342 const struct platform_device_id *id_entry =
343 platform_get_device_id(fep->pdev);
346 u32 rcntl = OPT_FRAME_SIZE | 0x04;
348 /* Whack a reset. We should wait for this. */
349 writel(1, fep->hwp + FEC_ECNTRL);
353 * enet-mac reset will reset mac address registers too,
354 * so need to reconfigure it.
356 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
357 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN);
358 writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW);
359 writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH);
362 /* Clear any outstanding interrupt. */
363 writel(0xffc00000, fep->hwp + FEC_IEVENT);
365 /* Reset all multicast. */
366 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
367 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
369 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
370 writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
373 /* Set maximum receive buffer size. */
374 writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE);
376 /* Set receive and transmit descriptor base. */
377 writel(fep->bd_dma, fep->hwp + FEC_R_DES_START);
378 writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc) * RX_RING_SIZE,
379 fep->hwp + FEC_X_DES_START);
381 fep->dirty_tx = fep->cur_tx = fep->tx_bd_base;
382 fep->cur_rx = fep->rx_bd_base;
384 /* Reset SKB transmit buffers. */
385 fep->skb_cur = fep->skb_dirty = 0;
386 for (i = 0; i <= TX_RING_MOD_MASK; i++) {
387 if (fep->tx_skbuff[i]) {
388 dev_kfree_skb_any(fep->tx_skbuff[i]);
389 fep->tx_skbuff[i] = NULL;
393 /* Enable MII mode */
396 writel(0x04, fep->hwp + FEC_X_CNTRL);
400 writel(0x0, fep->hwp + FEC_X_CNTRL);
403 fep->full_duplex = duplex;
406 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
409 * The phy interface and speed need to get configured
410 * differently on enet-mac.
412 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
413 /* Enable flow control and length check */
414 rcntl |= 0x40000000 | 0x00000020;
417 if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
423 if (fep->phy_dev && fep->phy_dev->speed == SPEED_100)
429 #ifdef FEC_MIIGSK_ENR
430 if (fep->phy_interface == PHY_INTERFACE_MODE_RMII) {
431 /* disable the gasket and wait */
432 writel(0, fep->hwp + FEC_MIIGSK_ENR);
433 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
437 * configure the gasket:
438 * RMII, 50 MHz, no loopback, no echo
440 writel(1, fep->hwp + FEC_MIIGSK_CFGR);
442 /* re-enable the gasket */
443 writel(2, fep->hwp + FEC_MIIGSK_ENR);
447 writel(rcntl, fep->hwp + FEC_R_CNTRL);
449 /* And last, enable the transmit and receive processing */
450 writel(2, fep->hwp + FEC_ECNTRL);
451 writel(0, fep->hwp + FEC_R_DES_ACTIVE);
453 /* Enable interrupts we wish to service */
454 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
458 fec_stop(struct net_device *ndev)
460 struct fec_enet_private *fep = netdev_priv(ndev);
462 /* We cannot expect a graceful transmit stop without link !!! */
464 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */
466 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA))
467 printk("fec_stop : Graceful transmit stop did not complete !\n");
470 /* Whack a reset. We should wait for this. */
471 writel(1, fep->hwp + FEC_ECNTRL);
473 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
474 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
479 fec_timeout(struct net_device *ndev)
481 struct fec_enet_private *fep = netdev_priv(ndev);
483 ndev->stats.tx_errors++;
485 fec_restart(ndev, fep->full_duplex);
486 netif_wake_queue(ndev);
490 fec_enet_tx(struct net_device *ndev)
492 struct fec_enet_private *fep;
494 unsigned short status;
497 fep = netdev_priv(ndev);
498 spin_lock(&fep->hw_lock);
501 while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) {
502 if (bdp == fep->cur_tx && fep->tx_full == 0)
505 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
506 FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE);
507 bdp->cbd_bufaddr = 0;
509 skb = fep->tx_skbuff[fep->skb_dirty];
510 /* Check for errors. */
511 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
512 BD_ENET_TX_RL | BD_ENET_TX_UN |
514 ndev->stats.tx_errors++;
515 if (status & BD_ENET_TX_HB) /* No heartbeat */
516 ndev->stats.tx_heartbeat_errors++;
517 if (status & BD_ENET_TX_LC) /* Late collision */
518 ndev->stats.tx_window_errors++;
519 if (status & BD_ENET_TX_RL) /* Retrans limit */
520 ndev->stats.tx_aborted_errors++;
521 if (status & BD_ENET_TX_UN) /* Underrun */
522 ndev->stats.tx_fifo_errors++;
523 if (status & BD_ENET_TX_CSL) /* Carrier lost */
524 ndev->stats.tx_carrier_errors++;
526 ndev->stats.tx_packets++;
529 if (status & BD_ENET_TX_READY)
530 printk("HEY! Enet xmit interrupt and TX_READY.\n");
532 /* Deferred means some collisions occurred during transmit,
533 * but we eventually sent the packet OK.
535 if (status & BD_ENET_TX_DEF)
536 ndev->stats.collisions++;
538 /* Free the sk buffer associated with this last transmit */
539 dev_kfree_skb_any(skb);
540 fep->tx_skbuff[fep->skb_dirty] = NULL;
541 fep->skb_dirty = (fep->skb_dirty + 1) & TX_RING_MOD_MASK;
543 /* Update pointer to next buffer descriptor to be transmitted */
544 if (status & BD_ENET_TX_WRAP)
545 bdp = fep->tx_bd_base;
549 /* Since we have freed up a buffer, the ring is no longer full
553 if (netif_queue_stopped(ndev))
554 netif_wake_queue(ndev);
558 spin_unlock(&fep->hw_lock);
562 /* During a receive, the cur_rx points to the current incoming buffer.
563 * When we update through the ring, if the next incoming buffer has
564 * not been given to the system, we just set the empty indicator,
565 * effectively tossing the packet.
568 fec_enet_rx(struct net_device *ndev)
570 struct fec_enet_private *fep = netdev_priv(ndev);
571 const struct platform_device_id *id_entry =
572 platform_get_device_id(fep->pdev);
574 unsigned short status;
583 spin_lock(&fep->hw_lock);
585 /* First, grab all of the stats for the incoming packet.
586 * These get messed up if we get called due to a busy condition.
590 while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) {
592 /* Since we have allocated space to hold a complete frame,
593 * the last indicator should be set.
595 if ((status & BD_ENET_RX_LAST) == 0)
596 printk("FEC ENET: rcv is not +last\n");
599 goto rx_processing_done;
601 /* Check for errors. */
602 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
603 BD_ENET_RX_CR | BD_ENET_RX_OV)) {
604 ndev->stats.rx_errors++;
605 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) {
606 /* Frame too long or too short. */
607 ndev->stats.rx_length_errors++;
609 if (status & BD_ENET_RX_NO) /* Frame alignment */
610 ndev->stats.rx_frame_errors++;
611 if (status & BD_ENET_RX_CR) /* CRC Error */
612 ndev->stats.rx_crc_errors++;
613 if (status & BD_ENET_RX_OV) /* FIFO overrun */
614 ndev->stats.rx_fifo_errors++;
617 /* Report late collisions as a frame error.
618 * On this error, the BD is closed, but we don't know what we
619 * have in the buffer. So, just drop this frame on the floor.
621 if (status & BD_ENET_RX_CL) {
622 ndev->stats.rx_errors++;
623 ndev->stats.rx_frame_errors++;
624 goto rx_processing_done;
627 /* Process the incoming frame. */
628 ndev->stats.rx_packets++;
629 pkt_len = bdp->cbd_datlen;
630 ndev->stats.rx_bytes += pkt_len;
631 data = (__u8*)__va(bdp->cbd_bufaddr);
633 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
634 FEC_ENET_TX_FRSIZE, DMA_FROM_DEVICE);
636 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
637 swap_buffer(data, pkt_len);
639 /* This does 16 byte alignment, exactly what we need.
640 * The packet length includes FCS, but we don't want to
641 * include that when passing upstream as it messes up
642 * bridging applications.
644 skb = dev_alloc_skb(pkt_len - 4 + NET_IP_ALIGN);
646 if (unlikely(!skb)) {
647 printk("%s: Memory squeeze, dropping packet.\n",
649 ndev->stats.rx_dropped++;
651 skb_reserve(skb, NET_IP_ALIGN);
652 skb_put(skb, pkt_len - 4); /* Make room */
653 skb_copy_to_linear_data(skb, data, pkt_len - 4);
654 skb->protocol = eth_type_trans(skb, ndev);
655 if (!skb_defer_rx_timestamp(skb))
659 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, data,
660 FEC_ENET_TX_FRSIZE, DMA_FROM_DEVICE);
662 /* Clear the status flags for this buffer */
663 status &= ~BD_ENET_RX_STATS;
665 /* Mark the buffer empty */
666 status |= BD_ENET_RX_EMPTY;
667 bdp->cbd_sc = status;
669 /* Update BD pointer to next entry */
670 if (status & BD_ENET_RX_WRAP)
671 bdp = fep->rx_bd_base;
674 /* Doing this here will keep the FEC running while we process
675 * incoming frames. On a heavily loaded network, we should be
676 * able to keep up at the expense of system resources.
678 writel(0, fep->hwp + FEC_R_DES_ACTIVE);
682 spin_unlock(&fep->hw_lock);
686 fec_enet_interrupt(int irq, void *dev_id)
688 struct net_device *ndev = dev_id;
689 struct fec_enet_private *fep = netdev_priv(ndev);
691 irqreturn_t ret = IRQ_NONE;
694 int_events = readl(fep->hwp + FEC_IEVENT);
695 writel(int_events, fep->hwp + FEC_IEVENT);
697 if (int_events & FEC_ENET_RXF) {
702 /* Transmit OK, or non-fatal error. Update the buffer
703 * descriptors. FEC handles all errors, we just discover
704 * them as part of the transmit process.
706 if (int_events & FEC_ENET_TXF) {
711 if (int_events & FEC_ENET_MII) {
713 complete(&fep->mdio_done);
715 } while (int_events);
722 /* ------------------------------------------------------------------------- */
723 static void __inline__ fec_get_mac(struct net_device *ndev)
725 struct fec_enet_private *fep = netdev_priv(ndev);
726 struct fec_platform_data *pdata = fep->pdev->dev.platform_data;
727 unsigned char *iap, tmpaddr[ETH_ALEN];
730 * try to get mac address in following order:
732 * 1) module parameter via kernel command line in form
733 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0
738 * 2) from flash or fuse (via platform data)
740 if (!is_valid_ether_addr(iap)) {
743 iap = (unsigned char *)FEC_FLASHMAC;
746 memcpy(iap, pdata->mac, ETH_ALEN);
751 * 3) FEC mac registers set by bootloader
753 if (!is_valid_ether_addr(iap)) {
754 *((unsigned long *) &tmpaddr[0]) =
755 be32_to_cpu(readl(fep->hwp + FEC_ADDR_LOW));
756 *((unsigned short *) &tmpaddr[4]) =
757 be16_to_cpu(readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
761 memcpy(ndev->dev_addr, iap, ETH_ALEN);
763 /* Adjust MAC if using macaddr */
765 ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->pdev->id;
768 /* ------------------------------------------------------------------------- */
773 static void fec_enet_adjust_link(struct net_device *ndev)
775 struct fec_enet_private *fep = netdev_priv(ndev);
776 struct phy_device *phy_dev = fep->phy_dev;
779 int status_change = 0;
781 spin_lock_irqsave(&fep->hw_lock, flags);
783 /* Prevent a state halted on mii error */
784 if (fep->mii_timeout && phy_dev->state == PHY_HALTED) {
785 phy_dev->state = PHY_RESUMING;
789 /* Duplex link change */
791 if (fep->full_duplex != phy_dev->duplex) {
792 fec_restart(ndev, phy_dev->duplex);
797 /* Link on or off change */
798 if (phy_dev->link != fep->link) {
799 fep->link = phy_dev->link;
801 fec_restart(ndev, phy_dev->duplex);
808 spin_unlock_irqrestore(&fep->hw_lock, flags);
811 phy_print_status(phy_dev);
814 static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
816 struct fec_enet_private *fep = bus->priv;
817 unsigned long time_left;
819 fep->mii_timeout = 0;
820 init_completion(&fep->mdio_done);
822 /* start a read op */
823 writel(FEC_MMFR_ST | FEC_MMFR_OP_READ |
824 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
825 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
827 /* wait for end of transfer */
828 time_left = wait_for_completion_timeout(&fep->mdio_done,
829 usecs_to_jiffies(FEC_MII_TIMEOUT));
830 if (time_left == 0) {
831 fep->mii_timeout = 1;
832 printk(KERN_ERR "FEC: MDIO read timeout\n");
837 return FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA));
840 static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
843 struct fec_enet_private *fep = bus->priv;
844 unsigned long time_left;
846 fep->mii_timeout = 0;
847 init_completion(&fep->mdio_done);
849 /* start a write op */
850 writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE |
851 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
852 FEC_MMFR_TA | FEC_MMFR_DATA(value),
853 fep->hwp + FEC_MII_DATA);
855 /* wait for end of transfer */
856 time_left = wait_for_completion_timeout(&fep->mdio_done,
857 usecs_to_jiffies(FEC_MII_TIMEOUT));
858 if (time_left == 0) {
859 fep->mii_timeout = 1;
860 printk(KERN_ERR "FEC: MDIO write timeout\n");
867 static int fec_enet_mdio_reset(struct mii_bus *bus)
872 static int fec_enet_mii_probe(struct net_device *ndev)
874 struct fec_enet_private *fep = netdev_priv(ndev);
875 struct phy_device *phy_dev = NULL;
876 char mdio_bus_id[MII_BUS_ID_SIZE];
877 char phy_name[MII_BUS_ID_SIZE + 3];
879 int dev_id = fep->pdev->id;
883 /* check for attached phy */
884 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) {
885 if ((fep->mii_bus->phy_mask & (1 << phy_id)))
887 if (fep->mii_bus->phy_map[phy_id] == NULL)
889 if (fep->mii_bus->phy_map[phy_id]->phy_id == 0)
893 strncpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE);
897 if (phy_id >= PHY_MAX_ADDR) {
898 printk(KERN_INFO "%s: no PHY, assuming direct connection "
899 "to switch\n", ndev->name);
900 strncpy(mdio_bus_id, "0", MII_BUS_ID_SIZE);
904 snprintf(phy_name, MII_BUS_ID_SIZE, PHY_ID_FMT, mdio_bus_id, phy_id);
905 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link, 0,
906 PHY_INTERFACE_MODE_MII);
907 if (IS_ERR(phy_dev)) {
908 printk(KERN_ERR "%s: could not attach to PHY\n", ndev->name);
909 return PTR_ERR(phy_dev);
912 /* mask with MAC supported features */
913 phy_dev->supported &= PHY_BASIC_FEATURES;
914 phy_dev->advertising = phy_dev->supported;
916 fep->phy_dev = phy_dev;
918 fep->full_duplex = 0;
920 printk(KERN_INFO "%s: Freescale FEC PHY driver [%s] "
921 "(mii_bus:phy_addr=%s, irq=%d)\n", ndev->name,
922 fep->phy_dev->drv->name, dev_name(&fep->phy_dev->dev),
928 static int fec_enet_mii_init(struct platform_device *pdev)
930 static struct mii_bus *fec0_mii_bus;
931 struct net_device *ndev = platform_get_drvdata(pdev);
932 struct fec_enet_private *fep = netdev_priv(ndev);
933 const struct platform_device_id *id_entry =
934 platform_get_device_id(fep->pdev);
938 * The dual fec interfaces are not equivalent with enet-mac.
939 * Here are the differences:
941 * - fec0 supports MII & RMII modes while fec1 only supports RMII
942 * - fec0 acts as the 1588 time master while fec1 is slave
943 * - external phys can only be configured by fec0
945 * That is to say fec1 can not work independently. It only works
946 * when fec0 is working. The reason behind this design is that the
947 * second interface is added primarily for Switch mode.
949 * Because of the last point above, both phys are attached on fec0
950 * mdio interface in board design, and need to be configured by
953 if ((id_entry->driver_data & FEC_QUIRK_ENET_MAC) && pdev->id) {
954 /* fec1 uses fec0 mii_bus */
955 fep->mii_bus = fec0_mii_bus;
959 fep->mii_timeout = 0;
962 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed)
964 fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk), 5000000) << 1;
965 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
967 fep->mii_bus = mdiobus_alloc();
968 if (fep->mii_bus == NULL) {
973 fep->mii_bus->name = "fec_enet_mii_bus";
974 fep->mii_bus->read = fec_enet_mdio_read;
975 fep->mii_bus->write = fec_enet_mdio_write;
976 fep->mii_bus->reset = fec_enet_mdio_reset;
977 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%x", pdev->id + 1);
978 fep->mii_bus->priv = fep;
979 fep->mii_bus->parent = &pdev->dev;
981 fep->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
982 if (!fep->mii_bus->irq) {
984 goto err_out_free_mdiobus;
987 for (i = 0; i < PHY_MAX_ADDR; i++)
988 fep->mii_bus->irq[i] = PHY_POLL;
990 if (mdiobus_register(fep->mii_bus))
991 goto err_out_free_mdio_irq;
993 /* save fec0 mii_bus */
994 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC)
995 fec0_mii_bus = fep->mii_bus;
999 err_out_free_mdio_irq:
1000 kfree(fep->mii_bus->irq);
1001 err_out_free_mdiobus:
1002 mdiobus_free(fep->mii_bus);
1007 static void fec_enet_mii_remove(struct fec_enet_private *fep)
1010 phy_disconnect(fep->phy_dev);
1011 mdiobus_unregister(fep->mii_bus);
1012 kfree(fep->mii_bus->irq);
1013 mdiobus_free(fep->mii_bus);
1016 static int fec_enet_get_settings(struct net_device *ndev,
1017 struct ethtool_cmd *cmd)
1019 struct fec_enet_private *fep = netdev_priv(ndev);
1020 struct phy_device *phydev = fep->phy_dev;
1025 return phy_ethtool_gset(phydev, cmd);
1028 static int fec_enet_set_settings(struct net_device *ndev,
1029 struct ethtool_cmd *cmd)
1031 struct fec_enet_private *fep = netdev_priv(ndev);
1032 struct phy_device *phydev = fep->phy_dev;
1037 return phy_ethtool_sset(phydev, cmd);
1040 static void fec_enet_get_drvinfo(struct net_device *ndev,
1041 struct ethtool_drvinfo *info)
1043 struct fec_enet_private *fep = netdev_priv(ndev);
1045 strcpy(info->driver, fep->pdev->dev.driver->name);
1046 strcpy(info->version, "Revision: 1.0");
1047 strcpy(info->bus_info, dev_name(&ndev->dev));
1050 static struct ethtool_ops fec_enet_ethtool_ops = {
1051 .get_settings = fec_enet_get_settings,
1052 .set_settings = fec_enet_set_settings,
1053 .get_drvinfo = fec_enet_get_drvinfo,
1054 .get_link = ethtool_op_get_link,
1057 static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
1059 struct fec_enet_private *fep = netdev_priv(ndev);
1060 struct phy_device *phydev = fep->phy_dev;
1062 if (!netif_running(ndev))
1068 return phy_mii_ioctl(phydev, rq, cmd);
1071 static void fec_enet_free_buffers(struct net_device *ndev)
1073 struct fec_enet_private *fep = netdev_priv(ndev);
1075 struct sk_buff *skb;
1076 struct bufdesc *bdp;
1078 bdp = fep->rx_bd_base;
1079 for (i = 0; i < RX_RING_SIZE; i++) {
1080 skb = fep->rx_skbuff[i];
1082 if (bdp->cbd_bufaddr)
1083 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
1084 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
1090 bdp = fep->tx_bd_base;
1091 for (i = 0; i < TX_RING_SIZE; i++)
1092 kfree(fep->tx_bounce[i]);
1095 static int fec_enet_alloc_buffers(struct net_device *ndev)
1097 struct fec_enet_private *fep = netdev_priv(ndev);
1099 struct sk_buff *skb;
1100 struct bufdesc *bdp;
1102 bdp = fep->rx_bd_base;
1103 for (i = 0; i < RX_RING_SIZE; i++) {
1104 skb = dev_alloc_skb(FEC_ENET_RX_FRSIZE);
1106 fec_enet_free_buffers(ndev);
1109 fep->rx_skbuff[i] = skb;
1111 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, skb->data,
1112 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
1113 bdp->cbd_sc = BD_ENET_RX_EMPTY;
1117 /* Set the last buffer to wrap. */
1119 bdp->cbd_sc |= BD_SC_WRAP;
1121 bdp = fep->tx_bd_base;
1122 for (i = 0; i < TX_RING_SIZE; i++) {
1123 fep->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL);
1126 bdp->cbd_bufaddr = 0;
1130 /* Set the last buffer to wrap. */
1132 bdp->cbd_sc |= BD_SC_WRAP;
1138 fec_enet_open(struct net_device *ndev)
1140 struct fec_enet_private *fep = netdev_priv(ndev);
1143 /* I should reset the ring buffers here, but I don't yet know
1144 * a simple way to do that.
1147 ret = fec_enet_alloc_buffers(ndev);
1151 /* Probe and connect to PHY when open the interface */
1152 ret = fec_enet_mii_probe(ndev);
1154 fec_enet_free_buffers(ndev);
1157 phy_start(fep->phy_dev);
1158 netif_start_queue(ndev);
1164 fec_enet_close(struct net_device *ndev)
1166 struct fec_enet_private *fep = netdev_priv(ndev);
1168 /* Don't know what to do yet. */
1170 netif_stop_queue(ndev);
1174 phy_stop(fep->phy_dev);
1175 phy_disconnect(fep->phy_dev);
1178 fec_enet_free_buffers(ndev);
1183 /* Set or clear the multicast filter for this adaptor.
1184 * Skeleton taken from sunlance driver.
1185 * The CPM Ethernet implementation allows Multicast as well as individual
1186 * MAC address filtering. Some of the drivers check to make sure it is
1187 * a group multicast address, and discard those that are not. I guess I
1188 * will do the same for now, but just remove the test if you want
1189 * individual filtering as well (do the upper net layers want or support
1190 * this kind of feature?).
1193 #define HASH_BITS 6 /* #bits in hash */
1194 #define CRC32_POLY 0xEDB88320
1196 static void set_multicast_list(struct net_device *ndev)
1198 struct fec_enet_private *fep = netdev_priv(ndev);
1199 struct netdev_hw_addr *ha;
1200 unsigned int i, bit, data, crc, tmp;
1203 if (ndev->flags & IFF_PROMISC) {
1204 tmp = readl(fep->hwp + FEC_R_CNTRL);
1206 writel(tmp, fep->hwp + FEC_R_CNTRL);
1210 tmp = readl(fep->hwp + FEC_R_CNTRL);
1212 writel(tmp, fep->hwp + FEC_R_CNTRL);
1214 if (ndev->flags & IFF_ALLMULTI) {
1215 /* Catch all multicast addresses, so set the
1218 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1219 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1224 /* Clear filter and add the addresses in hash register
1226 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1227 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1229 netdev_for_each_mc_addr(ha, ndev) {
1230 /* Only support group multicast for now */
1231 if (!(ha->addr[0] & 1))
1234 /* calculate crc32 value of mac address */
1237 for (i = 0; i < ndev->addr_len; i++) {
1239 for (bit = 0; bit < 8; bit++, data >>= 1) {
1241 (((crc ^ data) & 1) ? CRC32_POLY : 0);
1245 /* only upper 6 bits (HASH_BITS) are used
1246 * which point to specific bit in he hash registers
1248 hash = (crc >> (32 - HASH_BITS)) & 0x3f;
1251 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1252 tmp |= 1 << (hash - 32);
1253 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1255 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1257 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1262 /* Set a MAC change in hardware. */
1264 fec_set_mac_address(struct net_device *ndev, void *p)
1266 struct fec_enet_private *fep = netdev_priv(ndev);
1267 struct sockaddr *addr = p;
1269 if (!is_valid_ether_addr(addr->sa_data))
1270 return -EADDRNOTAVAIL;
1272 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
1274 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) |
1275 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24),
1276 fep->hwp + FEC_ADDR_LOW);
1277 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24),
1278 fep->hwp + FEC_ADDR_HIGH);
1282 static const struct net_device_ops fec_netdev_ops = {
1283 .ndo_open = fec_enet_open,
1284 .ndo_stop = fec_enet_close,
1285 .ndo_start_xmit = fec_enet_start_xmit,
1286 .ndo_set_multicast_list = set_multicast_list,
1287 .ndo_change_mtu = eth_change_mtu,
1288 .ndo_validate_addr = eth_validate_addr,
1289 .ndo_tx_timeout = fec_timeout,
1290 .ndo_set_mac_address = fec_set_mac_address,
1291 .ndo_do_ioctl = fec_enet_ioctl,
1295 * XXX: We need to clean up on failure exits here.
1298 static int fec_enet_init(struct net_device *ndev)
1300 struct fec_enet_private *fep = netdev_priv(ndev);
1301 struct bufdesc *cbd_base;
1302 struct bufdesc *bdp;
1305 /* Allocate memory for buffer descriptors. */
1306 cbd_base = dma_alloc_coherent(NULL, PAGE_SIZE, &fep->bd_dma,
1309 printk("FEC: allocate descriptor memory failed?\n");
1313 spin_lock_init(&fep->hw_lock);
1317 /* Get the Ethernet address */
1320 /* Set receive and transmit descriptor base. */
1321 fep->rx_bd_base = cbd_base;
1322 fep->tx_bd_base = cbd_base + RX_RING_SIZE;
1324 /* The FEC Ethernet specific entries in the device structure */
1325 ndev->watchdog_timeo = TX_TIMEOUT;
1326 ndev->netdev_ops = &fec_netdev_ops;
1327 ndev->ethtool_ops = &fec_enet_ethtool_ops;
1329 /* Initialize the receive buffer descriptors. */
1330 bdp = fep->rx_bd_base;
1331 for (i = 0; i < RX_RING_SIZE; i++) {
1333 /* Initialize the BD for every fragment in the page. */
1338 /* Set the last buffer to wrap */
1340 bdp->cbd_sc |= BD_SC_WRAP;
1342 /* ...and the same for transmit */
1343 bdp = fep->tx_bd_base;
1344 for (i = 0; i < TX_RING_SIZE; i++) {
1346 /* Initialize the BD for every fragment in the page. */
1348 bdp->cbd_bufaddr = 0;
1352 /* Set the last buffer to wrap */
1354 bdp->cbd_sc |= BD_SC_WRAP;
1356 fec_restart(ndev, 0);
1361 static int __devinit
1362 fec_probe(struct platform_device *pdev)
1364 struct fec_enet_private *fep;
1365 struct fec_platform_data *pdata;
1366 struct net_device *ndev;
1367 int i, irq, ret = 0;
1370 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1374 r = request_mem_region(r->start, resource_size(r), pdev->name);
1378 /* Init network device */
1379 ndev = alloc_etherdev(sizeof(struct fec_enet_private));
1382 goto failed_alloc_etherdev;
1385 SET_NETDEV_DEV(ndev, &pdev->dev);
1387 /* setup board info structure */
1388 fep = netdev_priv(ndev);
1390 fep->hwp = ioremap(r->start, resource_size(r));
1395 goto failed_ioremap;
1398 platform_set_drvdata(pdev, ndev);
1400 pdata = pdev->dev.platform_data;
1402 fep->phy_interface = pdata->phy;
1404 /* This device has up to three irqs on some platforms */
1405 for (i = 0; i < 3; i++) {
1406 irq = platform_get_irq(pdev, i);
1409 ret = request_irq(irq, fec_enet_interrupt, IRQF_DISABLED, pdev->name, ndev);
1412 irq = platform_get_irq(pdev, i);
1413 free_irq(irq, ndev);
1419 fep->clk = clk_get(&pdev->dev, "fec_clk");
1420 if (IS_ERR(fep->clk)) {
1421 ret = PTR_ERR(fep->clk);
1424 clk_enable(fep->clk);
1426 ret = fec_enet_init(ndev);
1430 ret = fec_enet_mii_init(pdev);
1432 goto failed_mii_init;
1434 /* Carrier starts down, phylib will bring it up */
1435 netif_carrier_off(ndev);
1437 ret = register_netdev(ndev);
1439 goto failed_register;
1444 fec_enet_mii_remove(fep);
1447 clk_disable(fep->clk);
1450 for (i = 0; i < 3; i++) {
1451 irq = platform_get_irq(pdev, i);
1453 free_irq(irq, ndev);
1459 failed_alloc_etherdev:
1460 release_mem_region(r->start, resource_size(r));
1465 static int __devexit
1466 fec_drv_remove(struct platform_device *pdev)
1468 struct net_device *ndev = platform_get_drvdata(pdev);
1469 struct fec_enet_private *fep = netdev_priv(ndev);
1473 fec_enet_mii_remove(fep);
1474 clk_disable(fep->clk);
1477 unregister_netdev(ndev);
1480 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1482 release_mem_region(r->start, resource_size(r));
1484 platform_set_drvdata(pdev, NULL);
1491 fec_suspend(struct device *dev)
1493 struct net_device *ndev = dev_get_drvdata(dev);
1494 struct fec_enet_private *fep = netdev_priv(ndev);
1496 if (netif_running(ndev)) {
1498 netif_device_detach(ndev);
1500 clk_disable(fep->clk);
1506 fec_resume(struct device *dev)
1508 struct net_device *ndev = dev_get_drvdata(dev);
1509 struct fec_enet_private *fep = netdev_priv(ndev);
1511 clk_enable(fep->clk);
1512 if (netif_running(ndev)) {
1513 fec_restart(ndev, fep->full_duplex);
1514 netif_device_attach(ndev);
1520 static const struct dev_pm_ops fec_pm_ops = {
1521 .suspend = fec_suspend,
1522 .resume = fec_resume,
1523 .freeze = fec_suspend,
1525 .poweroff = fec_suspend,
1526 .restore = fec_resume,
1530 static struct platform_driver fec_driver = {
1532 .name = DRIVER_NAME,
1533 .owner = THIS_MODULE,
1538 .id_table = fec_devtype,
1540 .remove = __devexit_p(fec_drv_remove),
1544 fec_enet_module_init(void)
1546 printk(KERN_INFO "FEC Ethernet Driver\n");
1548 return platform_driver_register(&fec_driver);
1552 fec_enet_cleanup(void)
1554 platform_driver_unregister(&fec_driver);
1557 module_exit(fec_enet_cleanup);
1558 module_init(fec_enet_module_init);
1560 MODULE_LICENSE("GPL");