drivers/net/gianfar.c

   1 /*
   2  * drivers/net/gianfar.c
   3  *
   4  * Gianfar Ethernet Driver
   5  * This driver is designed for the non-CPM ethernet controllers
   6  * on the 85xx and 83xx family of integrated processors
   7  * Based on 8260_io/fcc_enet.c
   8  *
   9  * Author: Andy Fleming
  10  * Maintainer: Kumar Gala
  11  * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
  12  *
  13  * Copyright 2002-2009 Freescale Semiconductor, Inc.
  14  * Copyright 2007 MontaVista Software, Inc.
  15  *
  16  * This program is free software; you can redistribute  it and/or modify it
  17  * under  the terms of  the GNU General  Public License as published by the
  18  * Free Software Foundation;  either version 2 of the  License, or (at your
  19  * option) any later version.
  20  *
  21  *  Gianfar:  AKA Lambda Draconis, "Dragon"
  22  *  RA 11 31 24.2
  23  *  Dec +69 19 52
  24  *  V 3.84
  25  *  B-V +1.62
  26  *
  27  *  Theory of operation
  28  *
  29  *  The driver is initialized through of_device. Configuration information
  30  *  is therefore conveyed through an OF-style device tree.
  31  *
  32  *  The Gianfar Ethernet Controller uses a ring of buffer
  33  *  descriptors.  The beginning is indicated by a register
  34  *  pointing to the physical address of the start of the ring.
  35  *  The end is determined by a "wrap" bit being set in the
  36  *  last descriptor of the ring.
  37  *
  38  *  When a packet is received, the RXF bit in the
  39  *  IEVENT register is set, triggering an interrupt when the
  40  *  corresponding bit in the IMASK register is also set (if
  41  *  interrupt coalescing is active, then the interrupt may not
  42  *  happen immediately, but will wait until either a set number
  43  *  of frames or amount of time have passed).  In NAPI, the
  44  *  interrupt handler will signal there is work to be done, and
  45  *  exit. This method will start at the last known empty
  46  *  descriptor, and process every subsequent descriptor until there
  47  *  are none left with data (NAPI will stop after a set number of
  48  *  packets to give time to other tasks, but will eventually
  49  *  process all the packets).  The data arrives inside a
  50  *  pre-allocated skb, and so after the skb is passed up to the
  51  *  stack, a new skb must be allocated, and the address field in
  52  *  the buffer descriptor must be updated to indicate this new
  53  *  skb.
  54  *
  55  *  When the kernel requests that a packet be transmitted, the
  56  *  driver starts where it left off last time, and points the
  57  *  descriptor at the buffer which was passed in.  The driver
  58  *  then informs the DMA engine that there are packets ready to
  59  *  be transmitted.  Once the controller is finished transmitting
  60  *  the packet, an interrupt may be triggered (under the same
  61  *  conditions as for reception, but depending on the TXF bit).
  62  *  The driver then cleans up the buffer.
  63  */
  64
  65 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  66 #define DEBUG
  67
  68 #include <linux/kernel.h>
  69 #include <linux/string.h>
  70 #include <linux/errno.h>
  71 #include <linux/unistd.h>
  72 #include <linux/slab.h>
  73 #include <linux/interrupt.h>
  74 #include <linux/init.h>
  75 #include <linux/delay.h>
  76 #include <linux/netdevice.h>
  77 #include <linux/etherdevice.h>
  78 #include <linux/skbuff.h>
  79 #include <linux/if_vlan.h>
  80 #include <linux/spinlock.h>
  81 #include <linux/mm.h>
  82 #include <linux/of_mdio.h>
  83 #include <linux/of_platform.h>
  84 #include <linux/ip.h>
  85 #include <linux/tcp.h>
  86 #include <linux/udp.h>
  87 #include <linux/in.h>
  88 #include <linux/net_tstamp.h>
  89
  90 #include <asm/io.h>
  91 #include <asm/reg.h>
  92 #include <asm/irq.h>
  93 #include <asm/uaccess.h>
  94 #include <linux/module.h>
  95 #include <linux/dma-mapping.h>
  96 #include <linux/crc32.h>
  97 #include <linux/mii.h>
  98 #include <linux/phy.h>
  99 #include <linux/phy_fixed.h>
 100 #include <linux/of.h>
 101 #include <linux/of_net.h>
 102
 103 #include "gianfar.h"
 104 #include "fsl_pq_mdio.h"
 105
 106 #define TX_TIMEOUT      (1*HZ)
 107 #undef BRIEF_GFAR_ERRORS
 108 #undef VERBOSE_GFAR_ERRORS
 109
 110 const char gfar_driver_name[] = "Gianfar Ethernet";
 111 const char gfar_driver_version[] = "1.3";
 112
 113 static int gfar_enet_open(struct net_device *dev);
 114 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
 115 static void gfar_reset_task(struct work_struct *work);
 116 static void gfar_timeout(struct net_device *dev);
 117 static int gfar_close(struct net_device *dev);
 118 struct sk_buff *gfar_new_skb(struct net_device *dev);
 119 static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
 120                 struct sk_buff *skb);
 121 static int gfar_set_mac_address(struct net_device *dev);
 122 static int gfar_change_mtu(struct net_device *dev, int new_mtu);
 123 static irqreturn_t gfar_error(int irq, void *dev_id);
 124 static irqreturn_t gfar_transmit(int irq, void *dev_id);
 125 static irqreturn_t gfar_interrupt(int irq, void *dev_id);
 126 static void adjust_link(struct net_device *dev);
 127 static void init_registers(struct net_device *dev);
 128 static int init_phy(struct net_device *dev);
 129 static int gfar_probe(struct platform_device *ofdev);
 130 static int gfar_remove(struct platform_device *ofdev);
 131 static void free_skb_resources(struct gfar_private *priv);
 132 static void gfar_set_multi(struct net_device *dev);
 133 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
 134 static void gfar_configure_serdes(struct net_device *dev);
 135 static int gfar_poll(struct napi_struct *napi, int budget);
 136 #ifdef CONFIG_NET_POLL_CONTROLLER
 137 static void gfar_netpoll(struct net_device *dev);
 138 #endif
 139 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit);
 140 static int gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue);
 141 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
 142                               int amount_pull);
 143 static void gfar_vlan_rx_register(struct net_device *netdev,
 144                                 struct vlan_group *grp);
 145 void gfar_halt(struct net_device *dev);
 146 static void gfar_halt_nodisable(struct net_device *dev);
 147 void gfar_start(struct net_device *dev);
 148 static void gfar_clear_exact_match(struct net_device *dev);
 149 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
 150                                   const u8 *addr);
 151 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
 152
 153 MODULE_AUTHOR("Freescale Semiconductor, Inc");
 154 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
 155 MODULE_LICENSE("GPL");
 156
 157 static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
 158                             dma_addr_t buf)
 159 {
 160         u32 lstatus;
 161
 162         bdp->bufPtr = buf;
 163
 164         lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
 165         if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1)
 166                 lstatus |= BD_LFLAG(RXBD_WRAP);
 167
 168         eieio();
 169
 170         bdp->lstatus = lstatus;
 171 }
 172
 173 static int gfar_init_bds(struct net_device *ndev)
 174 {
 175         struct gfar_private *priv = netdev_priv(ndev);
 176         struct gfar_priv_tx_q *tx_queue = NULL;
 177         struct gfar_priv_rx_q *rx_queue = NULL;
 178         struct txbd8 *txbdp;
 179         struct rxbd8 *rxbdp;
 180         int i, j;
 181
 182         for (i = 0; i < priv->num_tx_queues; i++) {
 183                 tx_queue = priv->tx_queue[i];
 184                 /* Initialize some variables in our dev structure */
 185                 tx_queue->num_txbdfree = tx_queue->tx_ring_size;
 186                 tx_queue->dirty_tx = tx_queue->tx_bd_base;
 187                 tx_queue->cur_tx = tx_queue->tx_bd_base;
 188                 tx_queue->skb_curtx = 0;
 189                 tx_queue->skb_dirtytx = 0;
 190
 191                 /* Initialize Transmit Descriptor Ring */
 192                 txbdp = tx_queue->tx_bd_base;
 193                 for (j = 0; j < tx_queue->tx_ring_size; j++) {
 194                         txbdp->lstatus = 0;
 195                         txbdp->bufPtr = 0;
 196                         txbdp++;
 197                 }
 198
 199                 /* Set the last descriptor in the ring to indicate wrap */
 200                 txbdp--;
 201                 txbdp->status |= TXBD_WRAP;
 202         }
 203
 204         for (i = 0; i < priv->num_rx_queues; i++) {
 205                 rx_queue = priv->rx_queue[i];
 206                 rx_queue->cur_rx = rx_queue->rx_bd_base;
 207                 rx_queue->skb_currx = 0;
 208                 rxbdp = rx_queue->rx_bd_base;
 209
 210                 for (j = 0; j < rx_queue->rx_ring_size; j++) {
 211                         struct sk_buff *skb = rx_queue->rx_skbuff[j];
 212
 213                         if (skb) {
 214                                 gfar_init_rxbdp(rx_queue, rxbdp,
 215                                                 rxbdp->bufPtr);
 216                         } else {
 217                                 skb = gfar_new_skb(ndev);
 218                                 if (!skb) {
 219                                         netdev_err(ndev, "Can't allocate RX buffers\n");
 220                                         goto err_rxalloc_fail;
 221                                 }
 222                                 rx_queue->rx_skbuff[j] = skb;
 223
 224                                 gfar_new_rxbdp(rx_queue, rxbdp, skb);
 225                         }
 226
 227                         rxbdp++;
 228                 }
 229
 230         }
 231
 232         return 0;
 233
 234 err_rxalloc_fail:
 235         free_skb_resources(priv);
 236         return -ENOMEM;
 237 }
 238
 239 static int gfar_alloc_skb_resources(struct net_device *ndev)
 240 {
 241         void *vaddr;
 242         dma_addr_t addr;
 243         int i, j, k;
 244         struct gfar_private *priv = netdev_priv(ndev);
 245         struct device *dev = &priv->ofdev->dev;
 246         struct gfar_priv_tx_q *tx_queue = NULL;
 247         struct gfar_priv_rx_q *rx_queue = NULL;
 248
 249         priv->total_tx_ring_size = 0;
 250         for (i = 0; i < priv->num_tx_queues; i++)
 251                 priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size;
 252
 253         priv->total_rx_ring_size = 0;
 254         for (i = 0; i < priv->num_rx_queues; i++)
 255                 priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size;
 256
 257         /* Allocate memory for the buffer descriptors */
 258         vaddr = dma_alloc_coherent(dev,
 259                         sizeof(struct txbd8) * priv->total_tx_ring_size +
 260                         sizeof(struct rxbd8) * priv->total_rx_ring_size,
 261                         &addr, GFP_KERNEL);
 262         if (!vaddr) {
 263                 netif_err(priv, ifup, ndev,
 264                           "Could not allocate buffer descriptors!\n");
 265                 return -ENOMEM;
 266         }
 267
 268         for (i = 0; i < priv->num_tx_queues; i++) {
 269                 tx_queue = priv->tx_queue[i];
 270                 tx_queue->tx_bd_base = (struct txbd8 *) vaddr;
 271                 tx_queue->tx_bd_dma_base = addr;
 272                 tx_queue->dev = ndev;
 273                 /* enet DMA only understands physical addresses */
 274                 addr    += sizeof(struct txbd8) *tx_queue->tx_ring_size;
 275                 vaddr   += sizeof(struct txbd8) *tx_queue->tx_ring_size;
 276         }
 277
 278         /* Start the rx descriptor ring where the tx ring leaves off */
 279         for (i = 0; i < priv->num_rx_queues; i++) {
 280                 rx_queue = priv->rx_queue[i];
 281                 rx_queue->rx_bd_base = (struct rxbd8 *) vaddr;
 282                 rx_queue->rx_bd_dma_base = addr;
 283                 rx_queue->dev = ndev;
 284                 addr    += sizeof (struct rxbd8) * rx_queue->rx_ring_size;
 285                 vaddr   += sizeof (struct rxbd8) * rx_queue->rx_ring_size;
 286         }
 287
 288         /* Setup the skbuff rings */
 289         for (i = 0; i < priv->num_tx_queues; i++) {
 290                 tx_queue = priv->tx_queue[i];
 291                 tx_queue->tx_skbuff = kmalloc(sizeof(*tx_queue->tx_skbuff) *
 292                                   tx_queue->tx_ring_size, GFP_KERNEL);
 293                 if (!tx_queue->tx_skbuff) {
 294                         netif_err(priv, ifup, ndev,
 295                                   "Could not allocate tx_skbuff\n");
 296                         goto cleanup;
 297                 }
 298
 299                 for (k = 0; k < tx_queue->tx_ring_size; k++)
 300                         tx_queue->tx_skbuff[k] = NULL;
 301         }
 302
 303         for (i = 0; i < priv->num_rx_queues; i++) {
 304                 rx_queue = priv->rx_queue[i];
 305                 rx_queue->rx_skbuff = kmalloc(sizeof(*rx_queue->rx_skbuff) *
 306                                   rx_queue->rx_ring_size, GFP_KERNEL);
 307
 308                 if (!rx_queue->rx_skbuff) {
 309                         netif_err(priv, ifup, ndev,
 310                                   "Could not allocate rx_skbuff\n");
 311                         goto cleanup;
 312                 }
 313
 314                 for (j = 0; j < rx_queue->rx_ring_size; j++)
 315                         rx_queue->rx_skbuff[j] = NULL;
 316         }
 317
 318         if (gfar_init_bds(ndev))
 319                 goto cleanup;
 320
 321         return 0;
 322
 323 cleanup:
 324         free_skb_resources(priv);
 325         return -ENOMEM;
 326 }
 327
 328 static void gfar_init_tx_rx_base(struct gfar_private *priv)
 329 {
 330         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 331         u32 __iomem *baddr;
 332         int i;
 333
 334         baddr = &regs->tbase0;
 335         for(i = 0; i < priv->num_tx_queues; i++) {
 336                 gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base);
 337                 baddr   += 2;
 338         }
 339
 340         baddr = &regs->rbase0;
 341         for(i = 0; i < priv->num_rx_queues; i++) {
 342                 gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base);
 343                 baddr   += 2;
 344         }
 345 }
 346
 347 static void gfar_init_mac(struct net_device *ndev)
 348 {
 349         struct gfar_private *priv = netdev_priv(ndev);
 350         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 351         u32 rctrl = 0;
 352         u32 tctrl = 0;
 353         u32 attrs = 0;
 354
 355         /* write the tx/rx base registers */
 356         gfar_init_tx_rx_base(priv);
 357
 358         /* Configure the coalescing support */
 359         gfar_configure_coalescing(priv, 0xFF, 0xFF);
 360
 361         if (priv->rx_filer_enable) {
 362                 rctrl |= RCTRL_FILREN;
 363                 /* Program the RIR0 reg with the required distribution */
 364                 gfar_write(&regs->rir0, DEFAULT_RIR0);
 365         }
 366
 367         if (ndev->features & NETIF_F_RXCSUM)
 368                 rctrl |= RCTRL_CHECKSUMMING;
 369
 370         if (priv->extended_hash) {
 371                 rctrl |= RCTRL_EXTHASH;
 372
 373                 gfar_clear_exact_match(ndev);
 374                 rctrl |= RCTRL_EMEN;
 375         }
 376
 377         if (priv->padding) {
 378                 rctrl &= ~RCTRL_PAL_MASK;
 379                 rctrl |= RCTRL_PADDING(priv->padding);
 380         }
 381
 382         /* Insert receive time stamps into padding alignment bytes */
 383         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER) {
 384                 rctrl &= ~RCTRL_PAL_MASK;
 385                 rctrl |= RCTRL_PADDING(8);
 386                 priv->padding = 8;
 387         }
 388
 389         /* Enable HW time stamping if requested from user space */
 390         if (priv->hwts_rx_en)
 391                 rctrl |= RCTRL_PRSDEP_INIT | RCTRL_TS_ENABLE;
 392
 393         /* keep vlan related bits if it's enabled */
 394         if (priv->vlgrp) {
 395                 rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT;
 396                 tctrl |= TCTRL_VLINS;
 397         }
 398
 399         /* Init rctrl based on our settings */
 400         gfar_write(&regs->rctrl, rctrl);
 401
 402         if (ndev->features & NETIF_F_IP_CSUM)
 403                 tctrl |= TCTRL_INIT_CSUM;
 404
 405         tctrl |= TCTRL_TXSCHED_PRIO;
 406
 407         gfar_write(&regs->tctrl, tctrl);
 408
 409         /* Set the extraction length and index */
 410         attrs = ATTRELI_EL(priv->rx_stash_size) |
 411                 ATTRELI_EI(priv->rx_stash_index);
 412
 413         gfar_write(&regs->attreli, attrs);
 414
 415         /* Start with defaults, and add stashing or locking
 416          * depending on the approprate variables */
 417         attrs = ATTR_INIT_SETTINGS;
 418
 419         if (priv->bd_stash_en)
 420                 attrs |= ATTR_BDSTASH;
 421
 422         if (priv->rx_stash_size != 0)
 423                 attrs |= ATTR_BUFSTASH;
 424
 425         gfar_write(&regs->attr, attrs);
 426
 427         gfar_write(&regs->fifo_tx_thr, priv->fifo_threshold);
 428         gfar_write(&regs->fifo_tx_starve, priv->fifo_starve);
 429         gfar_write(&regs->fifo_tx_starve_shutoff, priv->fifo_starve_off);
 430 }
 431
 432 static struct net_device_stats *gfar_get_stats(struct net_device *dev)
 433 {
 434         struct gfar_private *priv = netdev_priv(dev);
 435         unsigned long rx_packets = 0, rx_bytes = 0, rx_dropped = 0;
 436         unsigned long tx_packets = 0, tx_bytes = 0;
 437         int i = 0;
 438
 439         for (i = 0; i < priv->num_rx_queues; i++) {
 440                 rx_packets += priv->rx_queue[i]->stats.rx_packets;
 441                 rx_bytes += priv->rx_queue[i]->stats.rx_bytes;
 442                 rx_dropped += priv->rx_queue[i]->stats.rx_dropped;
 443         }
 444
 445         dev->stats.rx_packets = rx_packets;
 446         dev->stats.rx_bytes = rx_bytes;
 447         dev->stats.rx_dropped = rx_dropped;
 448
 449         for (i = 0; i < priv->num_tx_queues; i++) {
 450                 tx_bytes += priv->tx_queue[i]->stats.tx_bytes;
 451                 tx_packets += priv->tx_queue[i]->stats.tx_packets;
 452         }
 453
 454         dev->stats.tx_bytes = tx_bytes;
 455         dev->stats.tx_packets = tx_packets;
 456
 457         return &dev->stats;
 458 }
 459
 460 static const struct net_device_ops gfar_netdev_ops = {
 461         .ndo_open = gfar_enet_open,
 462         .ndo_start_xmit = gfar_start_xmit,
 463         .ndo_stop = gfar_close,
 464         .ndo_change_mtu = gfar_change_mtu,
 465         .ndo_set_features = gfar_set_features,
 466         .ndo_set_multicast_list = gfar_set_multi,
 467         .ndo_tx_timeout = gfar_timeout,
 468         .ndo_do_ioctl = gfar_ioctl,
 469         .ndo_get_stats = gfar_get_stats,
 470         .ndo_vlan_rx_register = gfar_vlan_rx_register,
 471         .ndo_set_mac_address = eth_mac_addr,
 472         .ndo_validate_addr = eth_validate_addr,
 473 #ifdef CONFIG_NET_POLL_CONTROLLER
 474         .ndo_poll_controller = gfar_netpoll,
 475 #endif
 476 };
 477
 478 unsigned int ftp_rqfpr[MAX_FILER_IDX + 1];
 479 unsigned int ftp_rqfcr[MAX_FILER_IDX + 1];
 480
 481 void lock_rx_qs(struct gfar_private *priv)
 482 {
 483         int i = 0x0;
 484
 485         for (i = 0; i < priv->num_rx_queues; i++)
 486                 spin_lock(&priv->rx_queue[i]->rxlock);
 487 }
 488
 489 void lock_tx_qs(struct gfar_private *priv)
 490 {
 491         int i = 0x0;
 492
 493         for (i = 0; i < priv->num_tx_queues; i++)
 494                 spin_lock(&priv->tx_queue[i]->txlock);
 495 }
 496
 497 void unlock_rx_qs(struct gfar_private *priv)
 498 {
 499         int i = 0x0;
 500
 501         for (i = 0; i < priv->num_rx_queues; i++)
 502                 spin_unlock(&priv->rx_queue[i]->rxlock);
 503 }
 504
 505 void unlock_tx_qs(struct gfar_private *priv)
 506 {
 507         int i = 0x0;
 508
 509         for (i = 0; i < priv->num_tx_queues; i++)
 510                 spin_unlock(&priv->tx_queue[i]->txlock);
 511 }
 512
 513 /* Returns 1 if incoming frames use an FCB */
 514 static inline int gfar_uses_fcb(struct gfar_private *priv)
 515 {
 516         return priv->vlgrp || (priv->ndev->features & NETIF_F_RXCSUM) ||
 517                 (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER);
 518 }
 519
 520 static void free_tx_pointers(struct gfar_private *priv)
 521 {
 522         int i = 0;
 523
 524         for (i = 0; i < priv->num_tx_queues; i++)
 525                 kfree(priv->tx_queue[i]);
 526 }
 527
 528 static void free_rx_pointers(struct gfar_private *priv)
 529 {
 530         int i = 0;
 531
 532         for (i = 0; i < priv->num_rx_queues; i++)
 533                 kfree(priv->rx_queue[i]);
 534 }
 535
 536 static void unmap_group_regs(struct gfar_private *priv)
 537 {
 538         int i = 0;
 539
 540         for (i = 0; i < MAXGROUPS; i++)
 541                 if (priv->gfargrp[i].regs)
 542                         iounmap(priv->gfargrp[i].regs);
 543 }
 544
 545 static void disable_napi(struct gfar_private *priv)
 546 {
 547         int i = 0;
 548
 549         for (i = 0; i < priv->num_grps; i++)
 550                 napi_disable(&priv->gfargrp[i].napi);
 551 }
 552
 553 static void enable_napi(struct gfar_private *priv)
 554 {
 555         int i = 0;
 556
 557         for (i = 0; i < priv->num_grps; i++)
 558                 napi_enable(&priv->gfargrp[i].napi);
 559 }
 560
 561 static int gfar_parse_group(struct device_node *np,
 562                 struct gfar_private *priv, const char *model)
 563 {
 564         u32 *queue_mask;
 565
 566         priv->gfargrp[priv->num_grps].regs = of_iomap(np, 0);
 567         if (!priv->gfargrp[priv->num_grps].regs)
 568                 return -ENOMEM;
 569
 570         priv->gfargrp[priv->num_grps].interruptTransmit =
 571                         irq_of_parse_and_map(np, 0);
 572
 573         /* If we aren't the FEC we have multiple interrupts */
 574         if (model && strcasecmp(model, "FEC")) {
 575                 priv->gfargrp[priv->num_grps].interruptReceive =
 576                         irq_of_parse_and_map(np, 1);
 577                 priv->gfargrp[priv->num_grps].interruptError =
 578                         irq_of_parse_and_map(np,2);
 579                 if (priv->gfargrp[priv->num_grps].interruptTransmit == NO_IRQ ||
 580                     priv->gfargrp[priv->num_grps].interruptReceive  == NO_IRQ ||
 581                     priv->gfargrp[priv->num_grps].interruptError    == NO_IRQ)
 582                         return -EINVAL;
 583         }
 584
 585         priv->gfargrp[priv->num_grps].grp_id = priv->num_grps;
 586         priv->gfargrp[priv->num_grps].priv = priv;
 587         spin_lock_init(&priv->gfargrp[priv->num_grps].grplock);
 588         if(priv->mode == MQ_MG_MODE) {
 589                 queue_mask = (u32 *)of_get_property(np,
 590                                         "fsl,rx-bit-map", NULL);
 591                 priv->gfargrp[priv->num_grps].rx_bit_map =
 592                         queue_mask ?  *queue_mask :(DEFAULT_MAPPING >> priv->num_grps);
 593                 queue_mask = (u32 *)of_get_property(np,
 594                                         "fsl,tx-bit-map", NULL);
 595                 priv->gfargrp[priv->num_grps].tx_bit_map =
 596                         queue_mask ? *queue_mask : (DEFAULT_MAPPING >> priv->num_grps);
 597         } else {
 598                 priv->gfargrp[priv->num_grps].rx_bit_map = 0xFF;
 599                 priv->gfargrp[priv->num_grps].tx_bit_map = 0xFF;
 600         }
 601         priv->num_grps++;
 602
 603         return 0;
 604 }
 605
 606 static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev)
 607 {
 608         const char *model;
 609         const char *ctype;
 610         const void *mac_addr;
 611         int err = 0, i;
 612         struct net_device *dev = NULL;
 613         struct gfar_private *priv = NULL;
 614         struct device_node *np = ofdev->dev.of_node;
 615         struct device_node *child = NULL;
 616         const u32 *stash;
 617         const u32 *stash_len;
 618         const u32 *stash_idx;
 619         unsigned int num_tx_qs, num_rx_qs;
 620         u32 *tx_queues, *rx_queues;
 621
 622         if (!np || !of_device_is_available(np))
 623                 return -ENODEV;
 624
 625         /* parse the num of tx and rx queues */
 626         tx_queues = (u32 *)of_get_property(np, "fsl,num_tx_queues", NULL);
 627         num_tx_qs = tx_queues ? *tx_queues : 1;
 628
 629         if (num_tx_qs > MAX_TX_QS) {
 630                 pr_err("num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n",
 631                        num_tx_qs, MAX_TX_QS);
 632                 pr_err("Cannot do alloc_etherdev, aborting\n");
 633                 return -EINVAL;
 634         }
 635
 636         rx_queues = (u32 *)of_get_property(np, "fsl,num_rx_queues", NULL);
 637         num_rx_qs = rx_queues ? *rx_queues : 1;
 638
 639         if (num_rx_qs > MAX_RX_QS) {
 640                 pr_err("num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n",
 641                        num_rx_qs, MAX_RX_QS);
 642                 pr_err("Cannot do alloc_etherdev, aborting\n");
 643                 return -EINVAL;
 644         }
 645
 646         *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs);
 647         dev = *pdev;
 648         if (NULL == dev)
 649                 return -ENOMEM;
 650
 651         priv = netdev_priv(dev);
 652         priv->node = ofdev->dev.of_node;
 653         priv->ndev = dev;
 654
 655         priv->num_tx_queues = num_tx_qs;
 656         netif_set_real_num_rx_queues(dev, num_rx_qs);
 657         priv->num_rx_queues = num_rx_qs;
 658         priv->num_grps = 0x0;
 659
 660         /* Init Rx queue filer rule set linked list*/
 661         INIT_LIST_HEAD(&priv->rx_list.list);
 662         priv->rx_list.count = 0;
 663         mutex_init(&priv->rx_queue_access);
 664
 665         model = of_get_property(np, "model", NULL);
 666
 667         for (i = 0; i < MAXGROUPS; i++)
 668                 priv->gfargrp[i].regs = NULL;
 669
 670         /* Parse and initialize group specific information */
 671         if (of_device_is_compatible(np, "fsl,etsec2")) {
 672                 priv->mode = MQ_MG_MODE;
 673                 for_each_child_of_node(np, child) {
 674                         err = gfar_parse_group(child, priv, model);
 675                         if (err)
 676                                 goto err_grp_init;
 677                 }
 678         } else {
 679                 priv->mode = SQ_SG_MODE;
 680                 err = gfar_parse_group(np, priv, model);
 681                 if(err)
 682                         goto err_grp_init;
 683         }
 684
 685         for (i = 0; i < priv->num_tx_queues; i++)
 686                priv->tx_queue[i] = NULL;
 687         for (i = 0; i < priv->num_rx_queues; i++)
 688                 priv->rx_queue[i] = NULL;
 689
 690         for (i = 0; i < priv->num_tx_queues; i++) {
 691                 priv->tx_queue[i] = kzalloc(sizeof(struct gfar_priv_tx_q),
 692                                             GFP_KERNEL);
 693                 if (!priv->tx_queue[i]) {
 694                         err = -ENOMEM;
 695                         goto tx_alloc_failed;
 696                 }
 697                 priv->tx_queue[i]->tx_skbuff = NULL;
 698                 priv->tx_queue[i]->qindex = i;
 699                 priv->tx_queue[i]->dev = dev;
 700                 spin_lock_init(&(priv->tx_queue[i]->txlock));
 701         }
 702
 703         for (i = 0; i < priv->num_rx_queues; i++) {
 704                 priv->rx_queue[i] = kzalloc(sizeof(struct gfar_priv_rx_q),
 705                                             GFP_KERNEL);
 706                 if (!priv->rx_queue[i]) {
 707                         err = -ENOMEM;
 708                         goto rx_alloc_failed;
 709                 }
 710                 priv->rx_queue[i]->rx_skbuff = NULL;
 711                 priv->rx_queue[i]->qindex = i;
 712                 priv->rx_queue[i]->dev = dev;
 713                 spin_lock_init(&(priv->rx_queue[i]->rxlock));
 714         }
 715
 716
 717         stash = of_get_property(np, "bd-stash", NULL);
 718
 719         if (stash) {
 720                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;
 721                 priv->bd_stash_en = 1;
 722         }
 723
 724         stash_len = of_get_property(np, "rx-stash-len", NULL);
 725
 726         if (stash_len)
 727                 priv->rx_stash_size = *stash_len;
 728
 729         stash_idx = of_get_property(np, "rx-stash-idx", NULL);
 730
 731         if (stash_idx)
 732                 priv->rx_stash_index = *stash_idx;
 733
 734         if (stash_len || stash_idx)
 735                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;
 736
 737         mac_addr = of_get_mac_address(np);
 738         if (mac_addr)
 739                 memcpy(dev->dev_addr, mac_addr, MAC_ADDR_LEN);
 740
 741         if (model && !strcasecmp(model, "TSEC"))
 742                 priv->device_flags =
 743                         FSL_GIANFAR_DEV_HAS_GIGABIT |
 744                         FSL_GIANFAR_DEV_HAS_COALESCE |
 745                         FSL_GIANFAR_DEV_HAS_RMON |
 746                         FSL_GIANFAR_DEV_HAS_MULTI_INTR;
 747         if (model && !strcasecmp(model, "eTSEC"))
 748                 priv->device_flags =
 749                         FSL_GIANFAR_DEV_HAS_GIGABIT |
 750                         FSL_GIANFAR_DEV_HAS_COALESCE |
 751                         FSL_GIANFAR_DEV_HAS_RMON |
 752                         FSL_GIANFAR_DEV_HAS_MULTI_INTR |
 753                         FSL_GIANFAR_DEV_HAS_PADDING |
 754                         FSL_GIANFAR_DEV_HAS_CSUM |
 755                         FSL_GIANFAR_DEV_HAS_VLAN |
 756                         FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
 757                         FSL_GIANFAR_DEV_HAS_EXTENDED_HASH |
 758                         FSL_GIANFAR_DEV_HAS_TIMER;
 759
 760         ctype = of_get_property(np, "phy-connection-type", NULL);
 761
 762         /* We only care about rgmii-id.  The rest are autodetected */
 763         if (ctype && !strcmp(ctype, "rgmii-id"))
 764                 priv->interface = PHY_INTERFACE_MODE_RGMII_ID;
 765         else
 766                 priv->interface = PHY_INTERFACE_MODE_MII;
 767
 768         if (of_get_property(np, "fsl,magic-packet", NULL))
 769                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
 770
 771         priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
 772
 773         /* Find the TBI PHY.  If it's not there, we don't support SGMII */
 774         priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
 775
 776         return 0;
 777
 778 rx_alloc_failed:
 779         free_rx_pointers(priv);
 780 tx_alloc_failed:
 781         free_tx_pointers(priv);
 782 err_grp_init:
 783         unmap_group_regs(priv);
 784         free_netdev(dev);
 785         return err;
 786 }
 787
 788 static int gfar_hwtstamp_ioctl(struct net_device *netdev,
 789                         struct ifreq *ifr, int cmd)
 790 {
 791         struct hwtstamp_config config;
 792         struct gfar_private *priv = netdev_priv(netdev);
 793
 794         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
 795                 return -EFAULT;
 796
 797         /* reserved for future extensions */
 798         if (config.flags)
 799                 return -EINVAL;
 800
 801         switch (config.tx_type) {
 802         case HWTSTAMP_TX_OFF:
 803                 priv->hwts_tx_en = 0;
 804                 break;
 805         case HWTSTAMP_TX_ON:
 806                 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
 807                         return -ERANGE;
 808                 priv->hwts_tx_en = 1;
 809                 break;
 810         default:
 811                 return -ERANGE;
 812         }
 813
 814         switch (config.rx_filter) {
 815         case HWTSTAMP_FILTER_NONE:
 816                 if (priv->hwts_rx_en) {
 817                         stop_gfar(netdev);
 818                         priv->hwts_rx_en = 0;
 819                         startup_gfar(netdev);
 820                 }
 821                 break;
 822         default:
 823                 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
 824                         return -ERANGE;
 825                 if (!priv->hwts_rx_en) {
 826                         stop_gfar(netdev);
 827                         priv->hwts_rx_en = 1;
 828                         startup_gfar(netdev);
 829                 }
 830                 config.rx_filter = HWTSTAMP_FILTER_ALL;
 831                 break;
 832         }
 833
 834         return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
 835                 -EFAULT : 0;
 836 }
 837
 838 /* Ioctl MII Interface */
 839 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
 840 {
 841         struct gfar_private *priv = netdev_priv(dev);
 842
 843         if (!netif_running(dev))
 844                 return -EINVAL;
 845
 846         if (cmd == SIOCSHWTSTAMP)
 847                 return gfar_hwtstamp_ioctl(dev, rq, cmd);
 848
 849         if (!priv->phydev)
 850                 return -ENODEV;
 851
 852         return phy_mii_ioctl(priv->phydev, rq, cmd);
 853 }
 854
 855 static unsigned int reverse_bitmap(unsigned int bit_map, unsigned int max_qs)
 856 {
 857         unsigned int new_bit_map = 0x0;
 858         int mask = 0x1 << (max_qs - 1), i;
 859         for (i = 0; i < max_qs; i++) {
 860                 if (bit_map & mask)
 861                         new_bit_map = new_bit_map + (1 << i);
 862                 mask = mask >> 0x1;
 863         }
 864         return new_bit_map;
 865 }
 866
 867 static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar,
 868                                    u32 class)
 869 {
 870         u32 rqfpr = FPR_FILER_MASK;
 871         u32 rqfcr = 0x0;
 872
 873         rqfar--;
 874         rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT;
 875         ftp_rqfpr[rqfar] = rqfpr;
 876         ftp_rqfcr[rqfar] = rqfcr;
 877         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 878
 879         rqfar--;
 880         rqfcr = RQFCR_CMP_NOMATCH;
 881         ftp_rqfpr[rqfar] = rqfpr;
 882         ftp_rqfcr[rqfar] = rqfcr;
 883         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 884
 885         rqfar--;
 886         rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND;
 887         rqfpr = class;
 888         ftp_rqfcr[rqfar] = rqfcr;
 889         ftp_rqfpr[rqfar] = rqfpr;
 890         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 891
 892         rqfar--;
 893         rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND;
 894         rqfpr = class;
 895         ftp_rqfcr[rqfar] = rqfcr;
 896         ftp_rqfpr[rqfar] = rqfpr;
 897         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 898
 899         return rqfar;
 900 }
 901
 902 static void gfar_init_filer_table(struct gfar_private *priv)
 903 {
 904         int i = 0x0;
 905         u32 rqfar = MAX_FILER_IDX;
 906         u32 rqfcr = 0x0;
 907         u32 rqfpr = FPR_FILER_MASK;
 908
 909         /* Default rule */
 910         rqfcr = RQFCR_CMP_MATCH;
 911         ftp_rqfcr[rqfar] = rqfcr;
 912         ftp_rqfpr[rqfar] = rqfpr;
 913         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 914
 915         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6);
 916         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP);
 917         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP);
 918         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4);
 919         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP);
 920         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP);
 921
 922         /* cur_filer_idx indicated the first non-masked rule */
 923         priv->cur_filer_idx = rqfar;
 924
 925         /* Rest are masked rules */
 926         rqfcr = RQFCR_CMP_NOMATCH;
 927         for (i = 0; i < rqfar; i++) {
 928                 ftp_rqfcr[i] = rqfcr;
 929                 ftp_rqfpr[i] = rqfpr;
 930                 gfar_write_filer(priv, i, rqfcr, rqfpr);
 931         }
 932 }
 933
 934 static void gfar_detect_errata(struct gfar_private *priv)
 935 {
 936         struct device *dev = &priv->ofdev->dev;
 937         unsigned int pvr = mfspr(SPRN_PVR);
 938         unsigned int svr = mfspr(SPRN_SVR);
 939         unsigned int mod = (svr >> 16) & 0xfff6; /* w/o E suffix */
 940         unsigned int rev = svr & 0xffff;
 941
 942         /* MPC8313 Rev 2.0 and higher; All MPC837x */
 943         if ((pvr == 0x80850010 && mod == 0x80b0 && rev >= 0x0020) ||
 944                         (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
 945                 priv->errata |= GFAR_ERRATA_74;
 946
 947         /* MPC8313 and MPC837x all rev */
 948         if ((pvr == 0x80850010 && mod == 0x80b0) ||
 949                         (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
 950                 priv->errata |= GFAR_ERRATA_76;
 951
 952         /* MPC8313 and MPC837x all rev */
 953         if ((pvr == 0x80850010 && mod == 0x80b0) ||
 954                         (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
 955                 priv->errata |= GFAR_ERRATA_A002;
 956
 957         /* MPC8313 Rev < 2.0, MPC8548 rev 2.0 */
 958         if ((pvr == 0x80850010 && mod == 0x80b0 && rev < 0x0020) ||
 959                         (pvr == 0x80210020 && mod == 0x8030 && rev == 0x0020))
 960                 priv->errata |= GFAR_ERRATA_12;
 961
 962         if (priv->errata)
 963                 dev_info(dev, "enabled errata workarounds, flags: 0x%x\n",
 964                          priv->errata);
 965 }
 966
 967 /* Set up the ethernet device structure, private data,
 968  * and anything else we need before we start */
 969 static int gfar_probe(struct platform_device *ofdev)
 970 {
 971         u32 tempval;
 972         struct net_device *dev = NULL;
 973         struct gfar_private *priv = NULL;
 974         struct gfar __iomem *regs = NULL;
 975         int err = 0, i, grp_idx = 0;
 976         int len_devname;
 977         u32 rstat = 0, tstat = 0, rqueue = 0, tqueue = 0;
 978         u32 isrg = 0;
 979         u32 __iomem *baddr;
 980
 981         err = gfar_of_init(ofdev, &dev);
 982
 983         if (err)
 984                 return err;
 985
 986         priv = netdev_priv(dev);
 987         priv->ndev = dev;
 988         priv->ofdev = ofdev;
 989         priv->node = ofdev->dev.of_node;
 990         SET_NETDEV_DEV(dev, &ofdev->dev);
 991
 992         spin_lock_init(&priv->bflock);
 993         INIT_WORK(&priv->reset_task, gfar_reset_task);
 994
 995         dev_set_drvdata(&ofdev->dev, priv);
 996         regs = priv->gfargrp[0].regs;
 997
 998         gfar_detect_errata(priv);
 999
1000         /* Stop the DMA engine now, in case it was running before */
1001         /* (The firmware could have used it, and left it running). */
1002         gfar_halt(dev);
1003
1004         /* Reset MAC layer */
1005         gfar_write(&regs->maccfg1, MACCFG1_SOFT_RESET);
1006
1007         /* We need to delay at least 3 TX clocks */
1008         udelay(2);
1009
1010         tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
1011         gfar_write(&regs->maccfg1, tempval);
1012
1013         /* Initialize MACCFG2. */
1014         tempval = MACCFG2_INIT_SETTINGS;
1015         if (gfar_has_errata(priv, GFAR_ERRATA_74))
1016                 tempval |= MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK;
1017         gfar_write(&regs->maccfg2, tempval);
1018
1019         /* Initialize ECNTRL */
1020         gfar_write(&regs->ecntrl, ECNTRL_INIT_SETTINGS);
1021
1022         /* Set the dev->base_addr to the gfar reg region */
1023         dev->base_addr = (unsigned long) regs;
1024
1025         SET_NETDEV_DEV(dev, &ofdev->dev);
1026
1027         /* Fill in the dev structure */
1028         dev->watchdog_timeo = TX_TIMEOUT;
1029         dev->mtu = 1500;
1030         dev->netdev_ops = &gfar_netdev_ops;
1031         dev->ethtool_ops = &gfar_ethtool_ops;
1032
1033         /* Register for napi ...We are registering NAPI for each grp */
1034         for (i = 0; i < priv->num_grps; i++)
1035                 netif_napi_add(dev, &priv->gfargrp[i].napi, gfar_poll, GFAR_DEV_WEIGHT);
1036
1037         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
1038                 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
1039                         NETIF_F_RXCSUM;
1040                 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG |
1041                         NETIF_F_RXCSUM | NETIF_F_HIGHDMA;
1042         }
1043
1044         priv->vlgrp = NULL;
1045
1046         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN)
1047                 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1048
1049         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
1050                 priv->extended_hash = 1;
1051                 priv->hash_width = 9;
1052
1053                 priv->hash_regs[0] = &regs->igaddr0;
1054                 priv->hash_regs[1] = &regs->igaddr1;
1055                 priv->hash_regs[2] = &regs->igaddr2;
1056                 priv->hash_regs[3] = &regs->igaddr3;
1057                 priv->hash_regs[4] = &regs->igaddr4;
1058                 priv->hash_regs[5] = &regs->igaddr5;
1059                 priv->hash_regs[6] = &regs->igaddr6;
1060                 priv->hash_regs[7] = &regs->igaddr7;
1061                 priv->hash_regs[8] = &regs->gaddr0;
1062                 priv->hash_regs[9] = &regs->gaddr1;
1063                 priv->hash_regs[10] = &regs->gaddr2;
1064                 priv->hash_regs[11] = &regs->gaddr3;
1065                 priv->hash_regs[12] = &regs->gaddr4;
1066                 priv->hash_regs[13] = &regs->gaddr5;
1067                 priv->hash_regs[14] = &regs->gaddr6;
1068                 priv->hash_regs[15] = &regs->gaddr7;
1069
1070         } else {
1071                 priv->extended_hash = 0;
1072                 priv->hash_width = 8;
1073
1074                 priv->hash_regs[0] = &regs->gaddr0;
1075                 priv->hash_regs[1] = &regs->gaddr1;
1076                 priv->hash_regs[2] = &regs->gaddr2;
1077                 priv->hash_regs[3] = &regs->gaddr3;
1078                 priv->hash_regs[4] = &regs->gaddr4;
1079                 priv->hash_regs[5] = &regs->gaddr5;
1080                 priv->hash_regs[6] = &regs->gaddr6;
1081                 priv->hash_regs[7] = &regs->gaddr7;
1082         }
1083
1084         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)
1085                 priv->padding = DEFAULT_PADDING;
1086         else
1087                 priv->padding = 0;
1088
1089         if (dev->features & NETIF_F_IP_CSUM ||
1090                         priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
1091                 dev->hard_header_len += GMAC_FCB_LEN;
1092
1093         /* Program the isrg regs only if number of grps > 1 */
1094         if (priv->num_grps > 1) {
1095                 baddr = &regs->isrg0;
1096                 for (i = 0; i < priv->num_grps; i++) {
1097                         isrg |= (priv->gfargrp[i].rx_bit_map << ISRG_SHIFT_RX);
1098                         isrg |= (priv->gfargrp[i].tx_bit_map << ISRG_SHIFT_TX);
1099                         gfar_write(baddr, isrg);
1100                         baddr++;
1101                         isrg = 0x0;
1102                 }
1103         }
1104
1105         /* Need to reverse the bit maps as  bit_map's MSB is q0
1106          * but, for_each_set_bit parses from right to left, which
1107          * basically reverses the queue numbers */
1108         for (i = 0; i< priv->num_grps; i++) {
1109                 priv->gfargrp[i].tx_bit_map = reverse_bitmap(
1110                                 priv->gfargrp[i].tx_bit_map, MAX_TX_QS);
1111                 priv->gfargrp[i].rx_bit_map = reverse_bitmap(
1112                                 priv->gfargrp[i].rx_bit_map, MAX_RX_QS);
1113         }
1114
1115         /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values,
1116          * also assign queues to groups */
1117         for (grp_idx = 0; grp_idx < priv->num_grps; grp_idx++) {
1118                 priv->gfargrp[grp_idx].num_rx_queues = 0x0;
1119                 for_each_set_bit(i, &priv->gfargrp[grp_idx].rx_bit_map,
1120                                 priv->num_rx_queues) {
1121                         priv->gfargrp[grp_idx].num_rx_queues++;
1122                         priv->rx_queue[i]->grp = &priv->gfargrp[grp_idx];
1123                         rstat = rstat | (RSTAT_CLEAR_RHALT >> i);
1124                         rqueue = rqueue | ((RQUEUE_EN0 | RQUEUE_EX0) >> i);
1125                 }
1126                 priv->gfargrp[grp_idx].num_tx_queues = 0x0;
1127                 for_each_set_bit(i, &priv->gfargrp[grp_idx].tx_bit_map,
1128                                 priv->num_tx_queues) {
1129                         priv->gfargrp[grp_idx].num_tx_queues++;
1130                         priv->tx_queue[i]->grp = &priv->gfargrp[grp_idx];
1131                         tstat = tstat | (TSTAT_CLEAR_THALT >> i);
1132                         tqueue = tqueue | (TQUEUE_EN0 >> i);
1133                 }
1134                 priv->gfargrp[grp_idx].rstat = rstat;
1135                 priv->gfargrp[grp_idx].tstat = tstat;
1136                 rstat = tstat =0;
1137         }
1138
1139         gfar_write(&regs->rqueue, rqueue);
1140         gfar_write(&regs->tqueue, tqueue);
1141
1142         priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
1143
1144         /* Initializing some of the rx/tx queue level parameters */
1145         for (i = 0; i < priv->num_tx_queues; i++) {
1146                 priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE;
1147                 priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE;
1148                 priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE;
1149                 priv->tx_queue[i]->txic = DEFAULT_TXIC;
1150         }
1151
1152         for (i = 0; i < priv->num_rx_queues; i++) {
1153                 priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE;
1154                 priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE;
1155                 priv->rx_queue[i]->rxic = DEFAULT_RXIC;
1156         }
1157
1158         /* always enable rx filer*/
1159         priv->rx_filer_enable = 1;
1160         /* Enable most messages by default */
1161         priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
1162
1163         /* Carrier starts down, phylib will bring it up */
1164         netif_carrier_off(dev);
1165
1166         err = register_netdev(dev);
1167
1168         if (err) {
1169                 pr_err("%s: Cannot register net device, aborting\n", dev->name);
1170                 goto register_fail;
1171         }
1172
1173         device_init_wakeup(&dev->dev,
1174                 priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1175
1176         /* fill out IRQ number and name fields */
1177         len_devname = strlen(dev->name);
1178         for (i = 0; i < priv->num_grps; i++) {
1179                 strncpy(&priv->gfargrp[i].int_name_tx[0], dev->name,
1180                                 len_devname);
1181                 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1182                         strncpy(&priv->gfargrp[i].int_name_tx[len_devname],
1183                                 "_g", sizeof("_g"));
1184                         priv->gfargrp[i].int_name_tx[
1185                                 strlen(priv->gfargrp[i].int_name_tx)] = i+48;
1186                         strncpy(&priv->gfargrp[i].int_name_tx[strlen(
1187                                 priv->gfargrp[i].int_name_tx)],
1188                                 "_tx", sizeof("_tx") + 1);
1189
1190                         strncpy(&priv->gfargrp[i].int_name_rx[0], dev->name,
1191                                         len_devname);
1192                         strncpy(&priv->gfargrp[i].int_name_rx[len_devname],
1193                                         "_g", sizeof("_g"));
1194                         priv->gfargrp[i].int_name_rx[
1195                                 strlen(priv->gfargrp[i].int_name_rx)] = i+48;
1196                         strncpy(&priv->gfargrp[i].int_name_rx[strlen(
1197                                 priv->gfargrp[i].int_name_rx)],
1198                                 "_rx", sizeof("_rx") + 1);
1199
1200                         strncpy(&priv->gfargrp[i].int_name_er[0], dev->name,
1201                                         len_devname);
1202                         strncpy(&priv->gfargrp[i].int_name_er[len_devname],
1203                                 "_g", sizeof("_g"));
1204                         priv->gfargrp[i].int_name_er[strlen(
1205                                         priv->gfargrp[i].int_name_er)] = i+48;
1206                         strncpy(&priv->gfargrp[i].int_name_er[strlen(\
1207                                 priv->gfargrp[i].int_name_er)],
1208                                 "_er", sizeof("_er") + 1);
1209                 } else
1210                         priv->gfargrp[i].int_name_tx[len_devname] = '\0';
1211         }
1212
1213         /* Initialize the filer table */
1214         gfar_init_filer_table(priv);
1215
1216         /* Create all the sysfs files */
1217         gfar_init_sysfs(dev);
1218
1219         /* Print out the device info */
1220         netdev_info(dev, "mac: %pM\n", dev->dev_addr);
1221
1222         /* Even more device info helps when determining which kernel */
1223         /* provided which set of benchmarks. */
1224         netdev_info(dev, "Running with NAPI enabled\n");
1225         for (i = 0; i < priv->num_rx_queues; i++)
1226                 netdev_info(dev, "RX BD ring size for Q[%d]: %d\n",
1227                             i, priv->rx_queue[i]->rx_ring_size);
1228         for(i = 0; i < priv->num_tx_queues; i++)
1229                 netdev_info(dev, "TX BD ring size for Q[%d]: %d\n",
1230                             i, priv->tx_queue[i]->tx_ring_size);
1231
1232         return 0;
1233
1234 register_fail:
1235         unmap_group_regs(priv);
1236         free_tx_pointers(priv);
1237         free_rx_pointers(priv);
1238         if (priv->phy_node)
1239                 of_node_put(priv->phy_node);
1240         if (priv->tbi_node)
1241                 of_node_put(priv->tbi_node);
1242         free_netdev(dev);
1243         return err;
1244 }
1245
1246 static int gfar_remove(struct platform_device *ofdev)
1247 {
1248         struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
1249
1250         if (priv->phy_node)
1251                 of_node_put(priv->phy_node);
1252         if (priv->tbi_node)
1253                 of_node_put(priv->tbi_node);
1254
1255         dev_set_drvdata(&ofdev->dev, NULL);
1256
1257         unregister_netdev(priv->ndev);
1258         unmap_group_regs(priv);
1259         free_netdev(priv->ndev);
1260
1261         return 0;
1262 }
1263
1264 #ifdef CONFIG_PM
1265
1266 static int gfar_suspend(struct device *dev)
1267 {
1268         struct gfar_private *priv = dev_get_drvdata(dev);
1269         struct net_device *ndev = priv->ndev;
1270         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1271         unsigned long flags;
1272         u32 tempval;
1273
1274         int magic_packet = priv->wol_en &&
1275                 (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1276
1277         netif_device_detach(ndev);
1278
1279         if (netif_running(ndev)) {
1280
1281                 local_irq_save(flags);
1282                 lock_tx_qs(priv);
1283                 lock_rx_qs(priv);
1284
1285                 gfar_halt_nodisable(ndev);
1286
1287                 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
1288                 tempval = gfar_read(&regs->maccfg1);
1289
1290                 tempval &= ~MACCFG1_TX_EN;
1291
1292                 if (!magic_packet)
1293                         tempval &= ~MACCFG1_RX_EN;
1294
1295                 gfar_write(&regs->maccfg1, tempval);
1296
1297                 unlock_rx_qs(priv);
1298                 unlock_tx_qs(priv);
1299                 local_irq_restore(flags);
1300
1301                 disable_napi(priv);
1302
1303                 if (magic_packet) {
1304                         /* Enable interrupt on Magic Packet */
1305                         gfar_write(&regs->imask, IMASK_MAG);
1306
1307                         /* Enable Magic Packet mode */
1308                         tempval = gfar_read(&regs->maccfg2);
1309                         tempval |= MACCFG2_MPEN;
1310                         gfar_write(&regs->maccfg2, tempval);
1311                 } else {
1312                         phy_stop(priv->phydev);
1313                 }
1314         }
1315
1316         return 0;
1317 }
1318
1319 static int gfar_resume(struct device *dev)
1320 {
1321         struct gfar_private *priv = dev_get_drvdata(dev);
1322         struct net_device *ndev = priv->ndev;
1323         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1324         unsigned long flags;
1325         u32 tempval;
1326         int magic_packet = priv->wol_en &&
1327                 (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1328
1329         if (!netif_running(ndev)) {
1330                 netif_device_attach(ndev);
1331                 return 0;
1332         }
1333
1334         if (!magic_packet && priv->phydev)
1335                 phy_start(priv->phydev);
1336
1337         /* Disable Magic Packet mode, in case something
1338          * else woke us up.
1339          */
1340         local_irq_save(flags);
1341         lock_tx_qs(priv);
1342         lock_rx_qs(priv);
1343
1344         tempval = gfar_read(&regs->maccfg2);
1345         tempval &= ~MACCFG2_MPEN;
1346         gfar_write(&regs->maccfg2, tempval);
1347
1348         gfar_start(ndev);
1349
1350         unlock_rx_qs(priv);
1351         unlock_tx_qs(priv);
1352         local_irq_restore(flags);
1353
1354         netif_device_attach(ndev);
1355
1356         enable_napi(priv);
1357
1358         return 0;
1359 }
1360
1361 static int gfar_restore(struct device *dev)
1362 {
1363         struct gfar_private *priv = dev_get_drvdata(dev);
1364         struct net_device *ndev = priv->ndev;
1365
1366         if (!netif_running(ndev))
1367                 return 0;
1368
1369         gfar_init_bds(ndev);
1370         init_registers(ndev);
1371         gfar_set_mac_address(ndev);
1372         gfar_init_mac(ndev);
1373         gfar_start(ndev);
1374
1375         priv->oldlink = 0;
1376         priv->oldspeed = 0;
1377         priv->oldduplex = -1;
1378
1379         if (priv->phydev)
1380                 phy_start(priv->phydev);
1381
1382         netif_device_attach(ndev);
1383         enable_napi(priv);
1384
1385         return 0;
1386 }
1387
1388 static struct dev_pm_ops gfar_pm_ops = {
1389         .suspend = gfar_suspend,
1390         .resume = gfar_resume,
1391         .freeze = gfar_suspend,
1392         .thaw = gfar_resume,
1393         .restore = gfar_restore,
1394 };
1395
1396 #define GFAR_PM_OPS (&gfar_pm_ops)
1397
1398 #else
1399
1400 #define GFAR_PM_OPS NULL
1401
1402 #endif
1403
1404 /* Reads the controller's registers to determine what interface
1405  * connects it to the PHY.
1406  */
1407 static phy_interface_t gfar_get_interface(struct net_device *dev)
1408 {
1409         struct gfar_private *priv = netdev_priv(dev);
1410         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1411         u32 ecntrl;
1412
1413         ecntrl = gfar_read(&regs->ecntrl);
1414
1415         if (ecntrl & ECNTRL_SGMII_MODE)
1416                 return PHY_INTERFACE_MODE_SGMII;
1417
1418         if (ecntrl & ECNTRL_TBI_MODE) {
1419                 if (ecntrl & ECNTRL_REDUCED_MODE)
1420                         return PHY_INTERFACE_MODE_RTBI;
1421                 else
1422                         return PHY_INTERFACE_MODE_TBI;
1423         }
1424
1425         if (ecntrl & ECNTRL_REDUCED_MODE) {
1426                 if (ecntrl & ECNTRL_REDUCED_MII_MODE)
1427                         return PHY_INTERFACE_MODE_RMII;
1428                 else {
1429                         phy_interface_t interface = priv->interface;
1430
1431                         /*
1432                          * This isn't autodetected right now, so it must
1433                          * be set by the device tree or platform code.
1434                          */
1435                         if (interface == PHY_INTERFACE_MODE_RGMII_ID)
1436                                 return PHY_INTERFACE_MODE_RGMII_ID;
1437
1438                         return PHY_INTERFACE_MODE_RGMII;
1439                 }
1440         }
1441
1442         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
1443                 return PHY_INTERFACE_MODE_GMII;
1444
1445         return PHY_INTERFACE_MODE_MII;
1446 }
1447
1448
1449 /* Initializes driver's PHY state, and attaches to the PHY.
1450  * Returns 0 on success.
1451  */
1452 static int init_phy(struct net_device *dev)
1453 {
1454         struct gfar_private *priv = netdev_priv(dev);
1455         uint gigabit_support =
1456                 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
1457                 SUPPORTED_1000baseT_Full : 0;
1458         phy_interface_t interface;
1459
1460         priv->oldlink = 0;
1461         priv->oldspeed = 0;
1462         priv->oldduplex = -1;
1463
1464         interface = gfar_get_interface(dev);
1465
1466         priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0,
1467                                       interface);
1468         if (!priv->phydev)
1469                 priv->phydev = of_phy_connect_fixed_link(dev, &adjust_link,
1470                                                          interface);
1471         if (!priv->phydev) {
1472                 dev_err(&dev->dev, "could not attach to PHY\n");
1473                 return -ENODEV;
1474         }
1475
1476         if (interface == PHY_INTERFACE_MODE_SGMII)
1477                 gfar_configure_serdes(dev);
1478
1479         /* Remove any features not supported by the controller */
1480         priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
1481         priv->phydev->advertising = priv->phydev->supported;
1482
1483         return 0;
1484 }
1485
1486 /*
1487  * Initialize TBI PHY interface for communicating with the
1488  * SERDES lynx PHY on the chip.  We communicate with this PHY
1489  * through the MDIO bus on each controller, treating it as a
1490  * "normal" PHY at the address found in the TBIPA register.  We assume
1491  * that the TBIPA register is valid.  Either the MDIO bus code will set
1492  * it to a value that doesn't conflict with other PHYs on the bus, or the
1493  * value doesn't matter, as there are no other PHYs on the bus.
1494  */
1495 static void gfar_configure_serdes(struct net_device *dev)
1496 {
1497         struct gfar_private *priv = netdev_priv(dev);
1498         struct phy_device *tbiphy;
1499
1500         if (!priv->tbi_node) {
1501                 dev_warn(&dev->dev, "error: SGMII mode requires that the "
1502                                     "device tree specify a tbi-handle\n");
1503                 return;
1504         }
1505
1506         tbiphy = of_phy_find_device(priv->tbi_node);
1507         if (!tbiphy) {
1508                 dev_err(&dev->dev, "error: Could not get TBI device\n");
1509                 return;
1510         }
1511
1512         /*
1513          * If the link is already up, we must already be ok, and don't need to
1514          * configure and reset the TBI<->SerDes link.  Maybe U-Boot configured
1515          * everything for us?  Resetting it takes the link down and requires
1516          * several seconds for it to come back.
1517          */
1518         if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS)
1519                 return;
1520
1521         /* Single clk mode, mii mode off(for serdes communication) */
1522         phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT);
1523
1524         phy_write(tbiphy, MII_ADVERTISE,
1525                         ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
1526                         ADVERTISE_1000XPSE_ASYM);
1527
1528         phy_write(tbiphy, MII_BMCR, BMCR_ANENABLE |
1529                         BMCR_ANRESTART | BMCR_FULLDPLX | BMCR_SPEED1000);
1530 }
1531
1532 static void init_registers(struct net_device *dev)
1533 {
1534         struct gfar_private *priv = netdev_priv(dev);
1535         struct gfar __iomem *regs = NULL;
1536         int i = 0;
1537
1538         for (i = 0; i < priv->num_grps; i++) {
1539                 regs = priv->gfargrp[i].regs;
1540                 /* Clear IEVENT */
1541                 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
1542
1543                 /* Initialize IMASK */
1544                 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1545         }
1546
1547         regs = priv->gfargrp[0].regs;
1548         /* Init hash registers to zero */
1549         gfar_write(&regs->igaddr0, 0);
1550         gfar_write(&regs->igaddr1, 0);
1551         gfar_write(&regs->igaddr2, 0);
1552         gfar_write(&regs->igaddr3, 0);
1553         gfar_write(&regs->igaddr4, 0);
1554         gfar_write(&regs->igaddr5, 0);
1555         gfar_write(&regs->igaddr6, 0);
1556         gfar_write(&regs->igaddr7, 0);
1557
1558         gfar_write(&regs->gaddr0, 0);
1559         gfar_write(&regs->gaddr1, 0);
1560         gfar_write(&regs->gaddr2, 0);
1561         gfar_write(&regs->gaddr3, 0);
1562         gfar_write(&regs->gaddr4, 0);
1563         gfar_write(&regs->gaddr5, 0);
1564         gfar_write(&regs->gaddr6, 0);
1565         gfar_write(&regs->gaddr7, 0);
1566
1567         /* Zero out the rmon mib registers if it has them */
1568         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
1569                 memset_io(&(regs->rmon), 0, sizeof (struct rmon_mib));
1570
1571                 /* Mask off the CAM interrupts */
1572                 gfar_write(&regs->rmon.cam1, 0xffffffff);
1573                 gfar_write(&regs->rmon.cam2, 0xffffffff);
1574         }
1575
1576         /* Initialize the max receive buffer length */
1577         gfar_write(&regs->mrblr, priv->rx_buffer_size);
1578
1579         /* Initialize the Minimum Frame Length Register */
1580         gfar_write(&regs->minflr, MINFLR_INIT_SETTINGS);
1581 }
1582
1583 static int __gfar_is_rx_idle(struct gfar_private *priv)
1584 {
1585         u32 res;
1586
1587         /*
1588          * Normaly TSEC should not hang on GRS commands, so we should
1589          * actually wait for IEVENT_GRSC flag.
1590          */
1591         if (likely(!gfar_has_errata(priv, GFAR_ERRATA_A002)))
1592                 return 0;
1593
1594         /*
1595          * Read the eTSEC register at offset 0xD1C. If bits 7-14 are
1596          * the same as bits 23-30, the eTSEC Rx is assumed to be idle
1597          * and the Rx can be safely reset.
1598          */
1599         res = gfar_read((void __iomem *)priv->gfargrp[0].regs + 0xd1c);
1600         res &= 0x7f807f80;
1601         if ((res & 0xffff) == (res >> 16))
1602                 return 1;
1603
1604         return 0;
1605 }
1606
1607 /* Halt the receive and transmit queues */
1608 static void gfar_halt_nodisable(struct net_device *dev)
1609 {
1610         struct gfar_private *priv = netdev_priv(dev);
1611         struct gfar __iomem *regs = NULL;
1612         u32 tempval;
1613         int i = 0;
1614
1615         for (i = 0; i < priv->num_grps; i++) {
1616                 regs = priv->gfargrp[i].regs;
1617                 /* Mask all interrupts */
1618                 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1619
1620                 /* Clear all interrupts */
1621                 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
1622         }
1623
1624         regs = priv->gfargrp[0].regs;
1625         /* Stop the DMA, and wait for it to stop */
1626         tempval = gfar_read(&regs->dmactrl);
1627         if ((tempval & (DMACTRL_GRS | DMACTRL_GTS))
1628             != (DMACTRL_GRS | DMACTRL_GTS)) {
1629                 int ret;
1630
1631                 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
1632                 gfar_write(&regs->dmactrl, tempval);
1633
1634                 do {
1635                         ret = spin_event_timeout(((gfar_read(&regs->ievent) &
1636                                  (IEVENT_GRSC | IEVENT_GTSC)) ==
1637                                  (IEVENT_GRSC | IEVENT_GTSC)), 1000000, 0);
1638                         if (!ret && !(gfar_read(&regs->ievent) & IEVENT_GRSC))
1639                                 ret = __gfar_is_rx_idle(priv);
1640                 } while (!ret);
1641         }
1642 }
1643
1644 /* Halt the receive and transmit queues */
1645 void gfar_halt(struct net_device *dev)
1646 {
1647         struct gfar_private *priv = netdev_priv(dev);
1648         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1649         u32 tempval;
1650
1651         gfar_halt_nodisable(dev);
1652
1653         /* Disable Rx and Tx */
1654         tempval = gfar_read(&regs->maccfg1);
1655         tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
1656         gfar_write(&regs->maccfg1, tempval);
1657 }
1658
1659 static void free_grp_irqs(struct gfar_priv_grp *grp)
1660 {
1661         free_irq(grp->interruptError, grp);
1662         free_irq(grp->interruptTransmit, grp);
1663         free_irq(grp->interruptReceive, grp);
1664 }
1665
1666 void stop_gfar(struct net_device *dev)
1667 {
1668         struct gfar_private *priv = netdev_priv(dev);
1669         unsigned long flags;
1670         int i;
1671
1672         phy_stop(priv->phydev);
1673
1674
1675         /* Lock it down */
1676         local_irq_save(flags);
1677         lock_tx_qs(priv);
1678         lock_rx_qs(priv);
1679
1680         gfar_halt(dev);
1681
1682         unlock_rx_qs(priv);
1683         unlock_tx_qs(priv);
1684         local_irq_restore(flags);
1685
1686         /* Free the IRQs */
1687         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1688                 for (i = 0; i < priv->num_grps; i++)
1689                         free_grp_irqs(&priv->gfargrp[i]);
1690         } else {
1691                 for (i = 0; i < priv->num_grps; i++)
1692                         free_irq(priv->gfargrp[i].interruptTransmit,
1693                                         &priv->gfargrp[i]);
1694         }
1695
1696         free_skb_resources(priv);
1697 }
1698
1699 static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue)
1700 {
1701         struct txbd8 *txbdp;
1702         struct gfar_private *priv = netdev_priv(tx_queue->dev);
1703         int i, j;
1704
1705         txbdp = tx_queue->tx_bd_base;
1706
1707         for (i = 0; i < tx_queue->tx_ring_size; i++) {
1708                 if (!tx_queue->tx_skbuff[i])
1709                         continue;
1710
1711                 dma_unmap_single(&priv->ofdev->dev, txbdp->bufPtr,
1712                                 txbdp->length, DMA_TO_DEVICE);
1713                 txbdp->lstatus = 0;
1714                 for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags;
1715                                 j++) {
1716                         txbdp++;
1717                         dma_unmap_page(&priv->ofdev->dev, txbdp->bufPtr,
1718                                         txbdp->length, DMA_TO_DEVICE);
1719                 }
1720                 txbdp++;
1721                 dev_kfree_skb_any(tx_queue->tx_skbuff[i]);
1722                 tx_queue->tx_skbuff[i] = NULL;
1723         }
1724         kfree(tx_queue->tx_skbuff);
1725 }
1726
1727 static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue)
1728 {
1729         struct rxbd8 *rxbdp;
1730         struct gfar_private *priv = netdev_priv(rx_queue->dev);
1731         int i;
1732
1733         rxbdp = rx_queue->rx_bd_base;
1734
1735         for (i = 0; i < rx_queue->rx_ring_size; i++) {
1736                 if (rx_queue->rx_skbuff[i]) {
1737                         dma_unmap_single(&priv->ofdev->dev,
1738                                         rxbdp->bufPtr, priv->rx_buffer_size,
1739                                         DMA_FROM_DEVICE);
1740                         dev_kfree_skb_any(rx_queue->rx_skbuff[i]);
1741                         rx_queue->rx_skbuff[i] = NULL;
1742                 }
1743                 rxbdp->lstatus = 0;
1744                 rxbdp->bufPtr = 0;
1745                 rxbdp++;
1746         }
1747         kfree(rx_queue->rx_skbuff);
1748 }
1749
1750 /* If there are any tx skbs or rx skbs still around, free them.
1751  * Then free tx_skbuff and rx_skbuff */
1752 static void free_skb_resources(struct gfar_private *priv)
1753 {
1754         struct gfar_priv_tx_q *tx_queue = NULL;
1755         struct gfar_priv_rx_q *rx_queue = NULL;
1756         int i;
1757
1758         /* Go through all the buffer descriptors and free their data buffers */
1759         for (i = 0; i < priv->num_tx_queues; i++) {
1760                 tx_queue = priv->tx_queue[i];
1761                 if(tx_queue->tx_skbuff)
1762                         free_skb_tx_queue(tx_queue);
1763         }
1764
1765         for (i = 0; i < priv->num_rx_queues; i++) {
1766                 rx_queue = priv->rx_queue[i];
1767                 if(rx_queue->rx_skbuff)
1768                         free_skb_rx_queue(rx_queue);
1769         }
1770
1771         dma_free_coherent(&priv->ofdev->dev,
1772                         sizeof(struct txbd8) * priv->total_tx_ring_size +
1773                         sizeof(struct rxbd8) * priv->total_rx_ring_size,
1774                         priv->tx_queue[0]->tx_bd_base,
1775                         priv->tx_queue[0]->tx_bd_dma_base);
1776         skb_queue_purge(&priv->rx_recycle);
1777 }
1778
1779 void gfar_start(struct net_device *dev)
1780 {
1781         struct gfar_private *priv = netdev_priv(dev);
1782         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1783         u32 tempval;
1784         int i = 0;
1785
1786         /* Enable Rx and Tx in MACCFG1 */
1787         tempval = gfar_read(&regs->maccfg1);
1788         tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
1789         gfar_write(&regs->maccfg1, tempval);
1790
1791         /* Initialize DMACTRL to have WWR and WOP */
1792         tempval = gfar_read(&regs->dmactrl);
1793         tempval |= DMACTRL_INIT_SETTINGS;
1794         gfar_write(&regs->dmactrl, tempval);
1795
1796         /* Make sure we aren't stopped */
1797         tempval = gfar_read(&regs->dmactrl);
1798         tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
1799         gfar_write(&regs->dmactrl, tempval);
1800
1801         for (i = 0; i < priv->num_grps; i++) {
1802                 regs = priv->gfargrp[i].regs;
1803                 /* Clear THLT/RHLT, so that the DMA starts polling now */
1804                 gfar_write(&regs->tstat, priv->gfargrp[i].tstat);
1805                 gfar_write(&regs->rstat, priv->gfargrp[i].rstat);
1806                 /* Unmask the interrupts we look for */
1807                 gfar_write(&regs->imask, IMASK_DEFAULT);
1808         }
1809
1810         dev->trans_start = jiffies; /* prevent tx timeout */
1811 }
1812
1813 void gfar_configure_coalescing(struct gfar_private *priv,
1814         unsigned long tx_mask, unsigned long rx_mask)
1815 {
1816         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1817         u32 __iomem *baddr;
1818         int i = 0;
1819
1820         /* Backward compatible case ---- even if we enable
1821          * multiple queues, there's only single reg to program
1822          */
1823         gfar_write(&regs->txic, 0);
1824         if(likely(priv->tx_queue[0]->txcoalescing))
1825                 gfar_write(&regs->txic, priv->tx_queue[0]->txic);
1826
1827         gfar_write(&regs->rxic, 0);
1828         if(unlikely(priv->rx_queue[0]->rxcoalescing))
1829                 gfar_write(&regs->rxic, priv->rx_queue[0]->rxic);
1830
1831         if (priv->mode == MQ_MG_MODE) {
1832                 baddr = &regs->txic0;
1833                 for_each_set_bit(i, &tx_mask, priv->num_tx_queues) {
1834                         if (likely(priv->tx_queue[i]->txcoalescing)) {
1835                                 gfar_write(baddr + i, 0);
1836                                 gfar_write(baddr + i, priv->tx_queue[i]->txic);
1837                         }
1838                 }
1839
1840                 baddr = &regs->rxic0;
1841                 for_each_set_bit(i, &rx_mask, priv->num_rx_queues) {
1842                         if (likely(priv->rx_queue[i]->rxcoalescing)) {
1843                                 gfar_write(baddr + i, 0);
1844                                 gfar_write(baddr + i, priv->rx_queue[i]->rxic);
1845                         }
1846                 }
1847         }
1848 }
1849
1850 static int register_grp_irqs(struct gfar_priv_grp *grp)
1851 {
1852         struct gfar_private *priv = grp->priv;
1853         struct net_device *dev = priv->ndev;
1854         int err;
1855
1856         /* If the device has multiple interrupts, register for
1857          * them.  Otherwise, only register for the one */
1858         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1859                 /* Install our interrupt handlers for Error,
1860                  * Transmit, and Receive */
1861                 if ((err = request_irq(grp->interruptError, gfar_error, 0,
1862                                 grp->int_name_er,grp)) < 0) {
1863                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1864                                   grp->interruptError);
1865
1866                         goto err_irq_fail;
1867                 }
1868
1869                 if ((err = request_irq(grp->interruptTransmit, gfar_transmit,
1870                                 0, grp->int_name_tx, grp)) < 0) {
1871                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1872                                   grp->interruptTransmit);
1873                         goto tx_irq_fail;
1874                 }
1875
1876                 if ((err = request_irq(grp->interruptReceive, gfar_receive, 0,
1877                                 grp->int_name_rx, grp)) < 0) {
1878                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1879                                   grp->interruptReceive);
1880                         goto rx_irq_fail;
1881                 }
1882         } else {
1883                 if ((err = request_irq(grp->interruptTransmit, gfar_interrupt, 0,
1884                                 grp->int_name_tx, grp)) < 0) {
1885                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1886                                   grp->interruptTransmit);
1887                         goto err_irq_fail;
1888                 }
1889         }
1890
1891         return 0;
1892
1893 rx_irq_fail:
1894         free_irq(grp->interruptTransmit, grp);
1895 tx_irq_fail:
1896         free_irq(grp->interruptError, grp);
1897 err_irq_fail:
1898         return err;
1899
1900 }
1901
1902 /* Bring the controller up and running */
1903 int startup_gfar(struct net_device *ndev)
1904 {
1905         struct gfar_private *priv = netdev_priv(ndev);
1906         struct gfar __iomem *regs = NULL;
1907         int err, i, j;
1908
1909         for (i = 0; i < priv->num_grps; i++) {
1910                 regs= priv->gfargrp[i].regs;
1911                 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1912         }
1913
1914         regs= priv->gfargrp[0].regs;
1915         err = gfar_alloc_skb_resources(ndev);
1916         if (err)
1917                 return err;
1918
1919         gfar_init_mac(ndev);
1920
1921         for (i = 0; i < priv->num_grps; i++) {
1922                 err = register_grp_irqs(&priv->gfargrp[i]);
1923                 if (err) {
1924                         for (j = 0; j < i; j++)
1925                                 free_grp_irqs(&priv->gfargrp[j]);
1926                         goto irq_fail;
1927                 }
1928         }
1929
1930         /* Start the controller */
1931         gfar_start(ndev);
1932
1933         phy_start(priv->phydev);
1934
1935         gfar_configure_coalescing(priv, 0xFF, 0xFF);
1936
1937         return 0;
1938
1939 irq_fail:
1940         free_skb_resources(priv);
1941         return err;
1942 }
1943
1944 /* Called when something needs to use the ethernet device */
1945 /* Returns 0 for success. */
1946 static int gfar_enet_open(struct net_device *dev)
1947 {
1948         struct gfar_private *priv = netdev_priv(dev);
1949         int err;
1950
1951         enable_napi(priv);
1952
1953         skb_queue_head_init(&priv->rx_recycle);
1954
1955         /* Initialize a bunch of registers */
1956         init_registers(dev);
1957
1958         gfar_set_mac_address(dev);
1959
1960         err = init_phy(dev);
1961
1962         if (err) {
1963                 disable_napi(priv);
1964                 return err;
1965         }
1966
1967         err = startup_gfar(dev);
1968         if (err) {
1969                 disable_napi(priv);
1970                 return err;
1971         }
1972
1973         netif_tx_start_all_queues(dev);
1974
1975         device_set_wakeup_enable(&dev->dev, priv->wol_en);
1976
1977         return err;
1978 }
1979
1980 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
1981 {
1982         struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN);
1983
1984         memset(fcb, 0, GMAC_FCB_LEN);
1985
1986         return fcb;
1987 }
1988
1989 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb)
1990 {
1991         u8 flags = 0;
1992
1993         /* If we're here, it's a IP packet with a TCP or UDP
1994          * payload.  We set it to checksum, using a pseudo-header
1995          * we provide
1996          */
1997         flags = TXFCB_DEFAULT;
1998
1999         /* Tell the controller what the protocol is */
2000         /* And provide the already calculated phcs */
2001         if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
2002                 flags |= TXFCB_UDP;
2003                 fcb->phcs = udp_hdr(skb)->check;
2004         } else
2005                 fcb->phcs = tcp_hdr(skb)->check;
2006
2007         /* l3os is the distance between the start of the
2008          * frame (skb->data) and the start of the IP hdr.
2009          * l4os is the distance between the start of the
2010          * l3 hdr and the l4 hdr */
2011         fcb->l3os = (u16)(skb_network_offset(skb) - GMAC_FCB_LEN);
2012         fcb->l4os = skb_network_header_len(skb);
2013
2014         fcb->flags = flags;
2015 }
2016
2017 void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
2018 {
2019         fcb->flags |= TXFCB_VLN;
2020         fcb->vlctl = vlan_tx_tag_get(skb);
2021 }
2022
2023 static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
2024                                struct txbd8 *base, int ring_size)
2025 {
2026         struct txbd8 *new_bd = bdp + stride;
2027
2028         return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
2029 }
2030
2031 static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
2032                 int ring_size)
2033 {
2034         return skip_txbd(bdp, 1, base, ring_size);
2035 }
2036
2037 /* This is called by the kernel when a frame is ready for transmission. */
2038 /* It is pointed to by the dev->hard_start_xmit function pointer */
2039 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
2040 {
2041         struct gfar_private *priv = netdev_priv(dev);
2042         struct gfar_priv_tx_q *tx_queue = NULL;
2043         struct netdev_queue *txq;
2044         struct gfar __iomem *regs = NULL;
2045         struct txfcb *fcb = NULL;
2046         struct txbd8 *txbdp, *txbdp_start, *base, *txbdp_tstamp = NULL;
2047         u32 lstatus;
2048         int i, rq = 0, do_tstamp = 0;
2049         u32 bufaddr;
2050         unsigned long flags;
2051         unsigned int nr_frags, nr_txbds, length;
2052
2053         /*
2054          * TOE=1 frames larger than 2500 bytes may see excess delays
2055          * before start of transmission.
2056          */
2057         if (unlikely(gfar_has_errata(priv, GFAR_ERRATA_76) &&
2058                         skb->ip_summed == CHECKSUM_PARTIAL &&
2059                         skb->len > 2500)) {
2060                 int ret;
2061
2062                 ret = skb_checksum_help(skb);
2063                 if (ret)
2064                         return ret;
2065         }
2066
2067         rq = skb->queue_mapping;
2068         tx_queue = priv->tx_queue[rq];
2069         txq = netdev_get_tx_queue(dev, rq);
2070         base = tx_queue->tx_bd_base;
2071         regs = tx_queue->grp->regs;
2072
2073         /* check if time stamp should be generated */
2074         if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
2075                      priv->hwts_tx_en))
2076                 do_tstamp = 1;
2077
2078         /* make space for additional header when fcb is needed */
2079         if (((skb->ip_summed == CHECKSUM_PARTIAL) ||
2080                         vlan_tx_tag_present(skb) ||
2081                         unlikely(do_tstamp)) &&
2082                         (skb_headroom(skb) < GMAC_FCB_LEN)) {
2083                 struct sk_buff *skb_new;
2084
2085                 skb_new = skb_realloc_headroom(skb, GMAC_FCB_LEN);
2086                 if (!skb_new) {
2087                         dev->stats.tx_errors++;
2088                         kfree_skb(skb);
2089                         return NETDEV_TX_OK;
2090                 }
2091                 kfree_skb(skb);
2092                 skb = skb_new;
2093         }
2094
2095         /* total number of fragments in the SKB */
2096         nr_frags = skb_shinfo(skb)->nr_frags;
2097
2098         /* calculate the required number of TxBDs for this skb */
2099         if (unlikely(do_tstamp))
2100                 nr_txbds = nr_frags + 2;
2101         else
2102                 nr_txbds = nr_frags + 1;
2103
2104         /* check if there is space to queue this packet */
2105         if (nr_txbds > tx_queue->num_txbdfree) {
2106                 /* no space, stop the queue */
2107                 netif_tx_stop_queue(txq);
2108                 dev->stats.tx_fifo_errors++;
2109                 return NETDEV_TX_BUSY;
2110         }
2111
2112         /* Update transmit stats */
2113         tx_queue->stats.tx_bytes += skb->len;
2114         tx_queue->stats.tx_packets++;
2115
2116         txbdp = txbdp_start = tx_queue->cur_tx;
2117         lstatus = txbdp->lstatus;
2118
2119         /* Time stamp insertion requires one additional TxBD */
2120         if (unlikely(do_tstamp))
2121                 txbdp_tstamp = txbdp = next_txbd(txbdp, base,
2122                                 tx_queue->tx_ring_size);
2123
2124         if (nr_frags == 0) {
2125                 if (unlikely(do_tstamp))
2126                         txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_LAST |
2127                                         TXBD_INTERRUPT);
2128                 else
2129                         lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2130         } else {
2131                 /* Place the fragment addresses and lengths into the TxBDs */
2132                 for (i = 0; i < nr_frags; i++) {
2133                         /* Point at the next BD, wrapping as needed */
2134                         txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2135
2136                         length = skb_shinfo(skb)->frags[i].size;
2137
2138                         lstatus = txbdp->lstatus | length |
2139                                 BD_LFLAG(TXBD_READY);
2140
2141                         /* Handle the last BD specially */
2142                         if (i == nr_frags - 1)
2143                                 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2144
2145                         bufaddr = dma_map_page(&priv->ofdev->dev,
2146                                         skb_shinfo(skb)->frags[i].page,
2147                                         skb_shinfo(skb)->frags[i].page_offset,
2148                                         length,
2149                                         DMA_TO_DEVICE);
2150
2151                         /* set the TxBD length and buffer pointer */
2152                         txbdp->bufPtr = bufaddr;
2153                         txbdp->lstatus = lstatus;
2154                 }
2155
2156                 lstatus = txbdp_start->lstatus;
2157         }
2158
2159         /* Set up checksumming */
2160         if (CHECKSUM_PARTIAL == skb->ip_summed) {
2161                 fcb = gfar_add_fcb(skb);
2162                 /* as specified by errata */
2163                 if (unlikely(gfar_has_errata(priv, GFAR_ERRATA_12)
2164                              && ((unsigned long)fcb % 0x20) > 0x18)) {
2165                         __skb_pull(skb, GMAC_FCB_LEN);
2166                         skb_checksum_help(skb);
2167                 } else {
2168                         lstatus |= BD_LFLAG(TXBD_TOE);
2169                         gfar_tx_checksum(skb, fcb);
2170                 }
2171         }
2172
2173         if (vlan_tx_tag_present(skb)) {
2174                 if (unlikely(NULL == fcb)) {
2175                         fcb = gfar_add_fcb(skb);
2176                         lstatus |= BD_LFLAG(TXBD_TOE);
2177                 }
2178
2179                 gfar_tx_vlan(skb, fcb);
2180         }
2181
2182         /* Setup tx hardware time stamping if requested */
2183         if (unlikely(do_tstamp)) {
2184                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2185                 if (fcb == NULL)
2186                         fcb = gfar_add_fcb(skb);
2187                 fcb->ptp = 1;
2188                 lstatus |= BD_LFLAG(TXBD_TOE);
2189         }
2190
2191         txbdp_start->bufPtr = dma_map_single(&priv->ofdev->dev, skb->data,
2192                         skb_headlen(skb), DMA_TO_DEVICE);
2193
2194         /*
2195          * If time stamping is requested one additional TxBD must be set up. The
2196          * first TxBD points to the FCB and must have a data length of
2197          * GMAC_FCB_LEN. The second TxBD points to the actual frame data with
2198          * the full frame length.
2199          */
2200         if (unlikely(do_tstamp)) {
2201                 txbdp_tstamp->bufPtr = txbdp_start->bufPtr + GMAC_FCB_LEN;
2202                 txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_READY) |
2203                                 (skb_headlen(skb) - GMAC_FCB_LEN);
2204                 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | GMAC_FCB_LEN;
2205         } else {
2206                 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
2207         }
2208
2209         /*
2210          * We can work in parallel with gfar_clean_tx_ring(), except
2211          * when modifying num_txbdfree. Note that we didn't grab the lock
2212          * when we were reading the num_txbdfree and checking for available
2213          * space, that's because outside of this function it can only grow,
2214          * and once we've got needed space, it cannot suddenly disappear.
2215          *
2216          * The lock also protects us from gfar_error(), which can modify
2217          * regs->tstat and thus retrigger the transfers, which is why we
2218          * also must grab the lock before setting ready bit for the first
2219          * to be transmitted BD.
2220          */
2221         spin_lock_irqsave(&tx_queue->txlock, flags);
2222
2223         /*
2224          * The powerpc-specific eieio() is used, as wmb() has too strong
2225          * semantics (it requires synchronization between cacheable and
2226          * uncacheable mappings, which eieio doesn't provide and which we
2227          * don't need), thus requiring a more expensive sync instruction.  At
2228          * some point, the set of architecture-independent barrier functions
2229          * should be expanded to include weaker barriers.
2230          */
2231         eieio();
2232
2233         txbdp_start->lstatus = lstatus;
2234
2235         eieio(); /* force lstatus write before tx_skbuff */
2236
2237         tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb;
2238
2239         /* Update the current skb pointer to the next entry we will use
2240          * (wrapping if necessary) */
2241         tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) &
2242                 TX_RING_MOD_MASK(tx_queue->tx_ring_size);
2243
2244         tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2245
2246         /* reduce TxBD free count */
2247         tx_queue->num_txbdfree -= (nr_txbds);
2248
2249         /* If the next BD still needs to be cleaned up, then the bds
2250            are full.  We need to tell the kernel to stop sending us stuff. */
2251         if (!tx_queue->num_txbdfree) {
2252                 netif_tx_stop_queue(txq);
2253
2254                 dev->stats.tx_fifo_errors++;
2255         }
2256
2257         /* Tell the DMA to go go go */
2258         gfar_write(&regs->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex);
2259
2260         /* Unlock priv */
2261         spin_unlock_irqrestore(&tx_queue->txlock, flags);
2262
2263         return NETDEV_TX_OK;
2264 }
2265
2266 /* Stops the kernel queue, and halts the controller */
2267 static int gfar_close(struct net_device *dev)
2268 {
2269         struct gfar_private *priv = netdev_priv(dev);
2270
2271         disable_napi(priv);
2272
2273         cancel_work_sync(&priv->reset_task);
2274         stop_gfar(dev);
2275
2276         /* Disconnect from the PHY */
2277         phy_disconnect(priv->phydev);
2278         priv->phydev = NULL;
2279
2280         netif_tx_stop_all_queues(dev);
2281
2282         return 0;
2283 }
2284
2285 /* Changes the mac address if the controller is not running. */
2286 static int gfar_set_mac_address(struct net_device *dev)
2287 {
2288         gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
2289
2290         return 0;
2291 }
2292
2293
2294 /* Enables and disables VLAN insertion/extraction */
2295 static void gfar_vlan_rx_register(struct net_device *dev,
2296                 struct vlan_group *grp)
2297 {
2298         struct gfar_private *priv = netdev_priv(dev);
2299         struct gfar __iomem *regs = NULL;
2300         unsigned long flags;
2301         u32 tempval;
2302
2303         regs = priv->gfargrp[0].regs;
2304         local_irq_save(flags);
2305         lock_rx_qs(priv);
2306
2307         priv->vlgrp = grp;
2308
2309         if (grp) {
2310                 /* Enable VLAN tag insertion */
2311                 tempval = gfar_read(&regs->tctrl);
2312                 tempval |= TCTRL_VLINS;
2313
2314                 gfar_write(&regs->tctrl, tempval);
2315
2316                 /* Enable VLAN tag extraction */
2317                 tempval = gfar_read(&regs->rctrl);
2318                 tempval |= (RCTRL_VLEX | RCTRL_PRSDEP_INIT);
2319                 gfar_write(&regs->rctrl, tempval);
2320         } else {
2321                 /* Disable VLAN tag insertion */
2322                 tempval = gfar_read(&regs->tctrl);
2323                 tempval &= ~TCTRL_VLINS;
2324                 gfar_write(&regs->tctrl, tempval);
2325
2326                 /* Disable VLAN tag extraction */
2327                 tempval = gfar_read(&regs->rctrl);
2328                 tempval &= ~RCTRL_VLEX;
2329                 /* If parse is no longer required, then disable parser */
2330                 if (tempval & RCTRL_REQ_PARSER)
2331                         tempval |= RCTRL_PRSDEP_INIT;
2332                 else
2333                         tempval &= ~RCTRL_PRSDEP_INIT;
2334                 gfar_write(&regs->rctrl, tempval);
2335         }
2336
2337         gfar_change_mtu(dev, dev->mtu);
2338
2339         unlock_rx_qs(priv);
2340         local_irq_restore(flags);
2341 }
2342
2343 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
2344 {
2345         int tempsize, tempval;
2346         struct gfar_private *priv = netdev_priv(dev);
2347         struct gfar __iomem *regs = priv->gfargrp[0].regs;
2348         int oldsize = priv->rx_buffer_size;
2349         int frame_size = new_mtu + ETH_HLEN;
2350
2351         if (priv->vlgrp)
2352                 frame_size += VLAN_HLEN;
2353
2354         if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
2355                 netif_err(priv, drv, dev, "Invalid MTU setting\n");
2356                 return -EINVAL;
2357         }
2358
2359         if (gfar_uses_fcb(priv))
2360                 frame_size += GMAC_FCB_LEN;
2361
2362         frame_size += priv->padding;
2363
2364         tempsize =
2365             (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
2366             INCREMENTAL_BUFFER_SIZE;
2367
2368         /* Only stop and start the controller if it isn't already
2369          * stopped, and we changed something */
2370         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
2371                 stop_gfar(dev);
2372
2373         priv->rx_buffer_size = tempsize;
2374
2375         dev->mtu = new_mtu;
2376
2377         gfar_write(&regs->mrblr, priv->rx_buffer_size);
2378         gfar_write(&regs->maxfrm, priv->rx_buffer_size);
2379
2380         /* If the mtu is larger than the max size for standard
2381          * ethernet frames (ie, a jumbo frame), then set maccfg2
2382          * to allow huge frames, and to check the length */
2383         tempval = gfar_read(&regs->maccfg2);
2384
2385         if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE ||
2386                         gfar_has_errata(priv, GFAR_ERRATA_74))
2387                 tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
2388         else
2389                 tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
2390
2391         gfar_write(&regs->maccfg2, tempval);
2392
2393         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
2394                 startup_gfar(dev);
2395
2396         return 0;
2397 }
2398
2399 /* gfar_reset_task gets scheduled when a packet has not been
2400  * transmitted after a set amount of time.
2401  * For now, assume that clearing out all the structures, and
2402  * starting over will fix the problem.
2403  */
2404 static void gfar_reset_task(struct work_struct *work)
2405 {
2406         struct gfar_private *priv = container_of(work, struct gfar_private,
2407                         reset_task);
2408         struct net_device *dev = priv->ndev;
2409
2410         if (dev->flags & IFF_UP) {
2411                 netif_tx_stop_all_queues(dev);
2412                 stop_gfar(dev);
2413                 startup_gfar(dev);
2414                 netif_tx_start_all_queues(dev);
2415         }
2416
2417         netif_tx_schedule_all(dev);
2418 }
2419
2420 static void gfar_timeout(struct net_device *dev)
2421 {
2422         struct gfar_private *priv = netdev_priv(dev);
2423
2424         dev->stats.tx_errors++;
2425         schedule_work(&priv->reset_task);
2426 }
2427
2428 static void gfar_align_skb(struct sk_buff *skb)
2429 {
2430         /* We need the data buffer to be aligned properly.  We will reserve
2431          * as many bytes as needed to align the data properly
2432          */
2433         skb_reserve(skb, RXBUF_ALIGNMENT -
2434                 (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1)));
2435 }
2436
2437 /* Interrupt Handler for Transmit complete */
2438 static int gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue)
2439 {
2440         struct net_device *dev = tx_queue->dev;
2441         struct gfar_private *priv = netdev_priv(dev);
2442         struct gfar_priv_rx_q *rx_queue = NULL;
2443         struct txbd8 *bdp, *next = NULL;
2444         struct txbd8 *lbdp = NULL;
2445         struct txbd8 *base = tx_queue->tx_bd_base;
2446         struct sk_buff *skb;
2447         int skb_dirtytx;
2448         int tx_ring_size = tx_queue->tx_ring_size;
2449         int frags = 0, nr_txbds = 0;
2450         int i;
2451         int howmany = 0;
2452         u32 lstatus;
2453         size_t buflen;
2454
2455         rx_queue = priv->rx_queue[tx_queue->qindex];
2456         bdp = tx_queue->dirty_tx;
2457         skb_dirtytx = tx_queue->skb_dirtytx;
2458
2459         while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) {
2460                 unsigned long flags;
2461
2462                 frags = skb_shinfo(skb)->nr_frags;
2463
2464                 /*
2465                  * When time stamping, one additional TxBD must be freed.
2466                  * Also, we need to dma_unmap_single() the TxPAL.
2467                  */
2468                 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))
2469                         nr_txbds = frags + 2;
2470                 else
2471                         nr_txbds = frags + 1;
2472
2473                 lbdp = skip_txbd(bdp, nr_txbds - 1, base, tx_ring_size);
2474
2475                 lstatus = lbdp->lstatus;
2476
2477                 /* Only clean completed frames */
2478                 if ((lstatus & BD_LFLAG(TXBD_READY)) &&
2479                                 (lstatus & BD_LENGTH_MASK))
2480                         break;
2481
2482                 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
2483                         next = next_txbd(bdp, base, tx_ring_size);
2484                         buflen = next->length + GMAC_FCB_LEN;
2485                 } else
2486                         buflen = bdp->length;
2487
2488                 dma_unmap_single(&priv->ofdev->dev, bdp->bufPtr,
2489                                 buflen, DMA_TO_DEVICE);
2490
2491                 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
2492                         struct skb_shared_hwtstamps shhwtstamps;
2493                         u64 *ns = (u64*) (((u32)skb->data + 0x10) & ~0x7);
2494                         memset(&shhwtstamps, 0, sizeof(shhwtstamps));
2495                         shhwtstamps.hwtstamp = ns_to_ktime(*ns);
2496                         skb_tstamp_tx(skb, &shhwtstamps);
2497                         bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2498                         bdp = next;
2499                 }
2500
2501                 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2502                 bdp = next_txbd(bdp, base, tx_ring_size);
2503
2504                 for (i = 0; i < frags; i++) {
2505                         dma_unmap_page(&priv->ofdev->dev,
2506                                         bdp->bufPtr,
2507                                         bdp->length,
2508                                         DMA_TO_DEVICE);
2509                         bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2510                         bdp = next_txbd(bdp, base, tx_ring_size);
2511                 }
2512
2513                 /*
2514                  * If there's room in the queue (limit it to rx_buffer_size)
2515                  * we add this skb back into the pool, if it's the right size
2516                  */
2517                 if (skb_queue_len(&priv->rx_recycle) < rx_queue->rx_ring_size &&
2518                                 skb_recycle_check(skb, priv->rx_buffer_size +
2519                                         RXBUF_ALIGNMENT)) {
2520                         gfar_align_skb(skb);
2521                         skb_queue_head(&priv->rx_recycle, skb);
2522                 } else
2523                         dev_kfree_skb_any(skb);
2524
2525                 tx_queue->tx_skbuff[skb_dirtytx] = NULL;
2526
2527                 skb_dirtytx = (skb_dirtytx + 1) &
2528                         TX_RING_MOD_MASK(tx_ring_size);
2529
2530                 howmany++;
2531                 spin_lock_irqsave(&tx_queue->txlock, flags);
2532                 tx_queue->num_txbdfree += nr_txbds;
2533                 spin_unlock_irqrestore(&tx_queue->txlock, flags);
2534         }
2535
2536         /* If we freed a buffer, we can restart transmission, if necessary */
2537         if (__netif_subqueue_stopped(dev, tx_queue->qindex) && tx_queue->num_txbdfree)
2538                 netif_wake_subqueue(dev, tx_queue->qindex);
2539
2540         /* Update dirty indicators */
2541         tx_queue->skb_dirtytx = skb_dirtytx;
2542         tx_queue->dirty_tx = bdp;
2543
2544         return howmany;
2545 }
2546
2547 static void gfar_schedule_cleanup(struct gfar_priv_grp *gfargrp)
2548 {
2549         unsigned long flags;
2550
2551         spin_lock_irqsave(&gfargrp->grplock, flags);
2552         if (napi_schedule_prep(&gfargrp->napi)) {
2553                 gfar_write(&gfargrp->regs->imask, IMASK_RTX_DISABLED);
2554                 __napi_schedule(&gfargrp->napi);
2555         } else {
2556                 /*
2557                  * Clear IEVENT, so interrupts aren't called again
2558                  * because of the packets that have already arrived.
2559                  */
2560                 gfar_write(&gfargrp->regs->ievent, IEVENT_RTX_MASK);
2561         }
2562         spin_unlock_irqrestore(&gfargrp->grplock, flags);
2563
2564 }
2565
2566 /* Interrupt Handler for Transmit complete */
2567 static irqreturn_t gfar_transmit(int irq, void *grp_id)
2568 {
2569         gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
2570         return IRQ_HANDLED;
2571 }
2572
2573 static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
2574                 struct sk_buff *skb)
2575 {
2576         struct net_device *dev = rx_queue->dev;
2577         struct gfar_private *priv = netdev_priv(dev);
2578         dma_addr_t buf;
2579
2580         buf = dma_map_single(&priv->ofdev->dev, skb->data,
2581                              priv->rx_buffer_size, DMA_FROM_DEVICE);
2582         gfar_init_rxbdp(rx_queue, bdp, buf);
2583 }
2584
2585 static struct sk_buff * gfar_alloc_skb(struct net_device *dev)
2586 {
2587         struct gfar_private *priv = netdev_priv(dev);
2588         struct sk_buff *skb = NULL;
2589
2590         skb = netdev_alloc_skb(dev, priv->rx_buffer_size + RXBUF_ALIGNMENT);
2591         if (!skb)
2592                 return NULL;
2593
2594         gfar_align_skb(skb);
2595
2596         return skb;
2597 }
2598
2599 struct sk_buff * gfar_new_skb(struct net_device *dev)
2600 {
2601         struct gfar_private *priv = netdev_priv(dev);
2602         struct sk_buff *skb = NULL;
2603
2604         skb = skb_dequeue(&priv->rx_recycle);
2605         if (!skb)
2606                 skb = gfar_alloc_skb(dev);
2607
2608         return skb;
2609 }
2610
2611 static inline void count_errors(unsigned short status, struct net_device *dev)
2612 {
2613         struct gfar_private *priv = netdev_priv(dev);
2614         struct net_device_stats *stats = &dev->stats;
2615         struct gfar_extra_stats *estats = &priv->extra_stats;
2616
2617         /* If the packet was truncated, none of the other errors
2618          * matter */
2619         if (status & RXBD_TRUNCATED) {
2620                 stats->rx_length_errors++;
2621
2622                 estats->rx_trunc++;
2623
2624                 return;
2625         }
2626         /* Count the errors, if there were any */
2627         if (status & (RXBD_LARGE | RXBD_SHORT)) {
2628                 stats->rx_length_errors++;
2629
2630                 if (status & RXBD_LARGE)
2631                         estats->rx_large++;
2632                 else
2633                         estats->rx_short++;
2634         }
2635         if (status & RXBD_NONOCTET) {
2636                 stats->rx_frame_errors++;
2637                 estats->rx_nonoctet++;
2638         }
2639         if (status & RXBD_CRCERR) {
2640                 estats->rx_crcerr++;
2641                 stats->rx_crc_errors++;
2642         }
2643         if (status & RXBD_OVERRUN) {
2644                 estats->rx_overrun++;
2645                 stats->rx_crc_errors++;
2646         }
2647 }
2648
2649 irqreturn_t gfar_receive(int irq, void *grp_id)
2650 {
2651         gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
2652         return IRQ_HANDLED;
2653 }
2654
2655 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
2656 {
2657         /* If valid headers were found, and valid sums
2658          * were verified, then we tell the kernel that no
2659          * checksumming is necessary.  Otherwise, it is */
2660         if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
2661                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2662         else
2663                 skb_checksum_none_assert(skb);
2664 }
2665
2666
2667 /* gfar_process_frame() -- handle one incoming packet if skb
2668  * isn't NULL.  */
2669 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
2670                               int amount_pull)
2671 {
2672         struct gfar_private *priv = netdev_priv(dev);
2673         struct rxfcb *fcb = NULL;
2674
2675         int ret;
2676
2677         /* fcb is at the beginning if exists */
2678         fcb = (struct rxfcb *)skb->data;
2679
2680         /* Remove the FCB from the skb */
2681         /* Remove the padded bytes, if there are any */
2682         if (amount_pull) {
2683                 skb_record_rx_queue(skb, fcb->rq);
2684                 skb_pull(skb, amount_pull);
2685         }
2686
2687         /* Get receive timestamp from the skb */
2688         if (priv->hwts_rx_en) {
2689                 struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb);
2690                 u64 *ns = (u64 *) skb->data;
2691                 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
2692                 shhwtstamps->hwtstamp = ns_to_ktime(*ns);
2693         }
2694
2695         if (priv->padding)
2696                 skb_pull(skb, priv->padding);
2697
2698         if (dev->features & NETIF_F_RXCSUM)
2699                 gfar_rx_checksum(skb, fcb);
2700
2701         /* Tell the skb what kind of packet this is */
2702         skb->protocol = eth_type_trans(skb, dev);
2703
2704         /* Send the packet up the stack */
2705         if (unlikely(priv->vlgrp && (fcb->flags & RXFCB_VLN)))
2706                 ret = vlan_hwaccel_receive_skb(skb, priv->vlgrp, fcb->vlctl);
2707         else
2708                 ret = netif_receive_skb(skb);
2709
2710         if (NET_RX_DROP == ret)
2711                 priv->extra_stats.kernel_dropped++;
2712
2713         return 0;
2714 }
2715
2716 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
2717  *   until the budget/quota has been reached. Returns the number
2718  *   of frames handled
2719  */
2720 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit)
2721 {
2722         struct net_device *dev = rx_queue->dev;
2723         struct rxbd8 *bdp, *base;
2724         struct sk_buff *skb;
2725         int pkt_len;
2726         int amount_pull;
2727         int howmany = 0;
2728         struct gfar_private *priv = netdev_priv(dev);
2729
2730         /* Get the first full descriptor */
2731         bdp = rx_queue->cur_rx;
2732         base = rx_queue->rx_bd_base;
2733
2734         amount_pull = (gfar_uses_fcb(priv) ? GMAC_FCB_LEN : 0);
2735
2736         while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
2737                 struct sk_buff *newskb;
2738                 rmb();
2739
2740                 /* Add another skb for the future */
2741                 newskb = gfar_new_skb(dev);
2742
2743                 skb = rx_queue->rx_skbuff[rx_queue->skb_currx];
2744
2745                 dma_unmap_single(&priv->ofdev->dev, bdp->bufPtr,
2746                                 priv->rx_buffer_size, DMA_FROM_DEVICE);
2747
2748                 if (unlikely(!(bdp->status & RXBD_ERR) &&
2749                                 bdp->length > priv->rx_buffer_size))
2750                         bdp->status = RXBD_LARGE;
2751
2752                 /* We drop the frame if we failed to allocate a new buffer */
2753                 if (unlikely(!newskb || !(bdp->status & RXBD_LAST) ||
2754                                  bdp->status & RXBD_ERR)) {
2755                         count_errors(bdp->status, dev);
2756
2757                         if (unlikely(!newskb))
2758                                 newskb = skb;
2759                         else if (skb)
2760                                 skb_queue_head(&priv->rx_recycle, skb);
2761                 } else {
2762                         /* Increment the number of packets */
2763                         rx_queue->stats.rx_packets++;
2764                         howmany++;
2765
2766                         if (likely(skb)) {
2767                                 pkt_len = bdp->length - ETH_FCS_LEN;
2768                                 /* Remove the FCS from the packet length */
2769                                 skb_put(skb, pkt_len);
2770                                 rx_queue->stats.rx_bytes += pkt_len;
2771                                 skb_record_rx_queue(skb, rx_queue->qindex);
2772                                 gfar_process_frame(dev, skb, amount_pull);
2773
2774                         } else {
2775                                 netif_warn(priv, rx_err, dev, "Missing skb!\n");
2776                                 rx_queue->stats.rx_dropped++;
2777                                 priv->extra_stats.rx_skbmissing++;
2778                         }
2779
2780                 }
2781
2782                 rx_queue->rx_skbuff[rx_queue->skb_currx] = newskb;
2783
2784                 /* Setup the new bdp */
2785                 gfar_new_rxbdp(rx_queue, bdp, newskb);
2786
2787                 /* Update to the next pointer */
2788                 bdp = next_bd(bdp, base, rx_queue->rx_ring_size);
2789
2790                 /* update to point at the next skb */
2791                 rx_queue->skb_currx =
2792                     (rx_queue->skb_currx + 1) &
2793                     RX_RING_MOD_MASK(rx_queue->rx_ring_size);
2794         }
2795
2796         /* Update the current rxbd pointer to be the next one */
2797         rx_queue->cur_rx = bdp;
2798
2799         return howmany;
2800 }
2801
2802 static int gfar_poll(struct napi_struct *napi, int budget)
2803 {
2804         struct gfar_priv_grp *gfargrp = container_of(napi,
2805                         struct gfar_priv_grp, napi);
2806         struct gfar_private *priv = gfargrp->priv;
2807         struct gfar __iomem *regs = gfargrp->regs;
2808         struct gfar_priv_tx_q *tx_queue = NULL;
2809         struct gfar_priv_rx_q *rx_queue = NULL;
2810         int rx_cleaned = 0, budget_per_queue = 0, rx_cleaned_per_queue = 0;
2811         int tx_cleaned = 0, i, left_over_budget = budget;
2812         unsigned long serviced_queues = 0;
2813         int num_queues = 0;
2814
2815         num_queues = gfargrp->num_rx_queues;
2816         budget_per_queue = budget/num_queues;
2817
2818         /* Clear IEVENT, so interrupts aren't called again
2819          * because of the packets that have already arrived */
2820         gfar_write(&regs->ievent, IEVENT_RTX_MASK);
2821
2822         while (num_queues && left_over_budget) {
2823
2824                 budget_per_queue = left_over_budget/num_queues;
2825                 left_over_budget = 0;
2826
2827                 for_each_set_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) {
2828                         if (test_bit(i, &serviced_queues))
2829                                 continue;
2830                         rx_queue = priv->rx_queue[i];
2831                         tx_queue = priv->tx_queue[rx_queue->qindex];
2832
2833                         tx_cleaned += gfar_clean_tx_ring(tx_queue);
2834                         rx_cleaned_per_queue = gfar_clean_rx_ring(rx_queue,
2835                                                         budget_per_queue);
2836                         rx_cleaned += rx_cleaned_per_queue;
2837                         if(rx_cleaned_per_queue < budget_per_queue) {
2838                                 left_over_budget = left_over_budget +
2839                                         (budget_per_queue - rx_cleaned_per_queue);
2840                                 set_bit(i, &serviced_queues);
2841                                 num_queues--;
2842                         }
2843                 }
2844         }
2845
2846         if (tx_cleaned)
2847                 return budget;
2848
2849         if (rx_cleaned < budget) {
2850                 napi_complete(napi);
2851
2852                 /* Clear the halt bit in RSTAT */
2853                 gfar_write(&regs->rstat, gfargrp->rstat);
2854
2855                 gfar_write(&regs->imask, IMASK_DEFAULT);
2856
2857                 /* If we are coalescing interrupts, update the timer */
2858                 /* Otherwise, clear it */
2859                 gfar_configure_coalescing(priv,
2860                                 gfargrp->rx_bit_map, gfargrp->tx_bit_map);
2861         }
2862
2863         return rx_cleaned;
2864 }
2865
2866 #ifdef CONFIG_NET_POLL_CONTROLLER
2867 /*
2868  * Polling 'interrupt' - used by things like netconsole to send skbs
2869  * without having to re-enable interrupts. It's not called while
2870  * the interrupt routine is executing.
2871  */
2872 static void gfar_netpoll(struct net_device *dev)
2873 {
2874         struct gfar_private *priv = netdev_priv(dev);
2875         int i = 0;
2876
2877         /* If the device has multiple interrupts, run tx/rx */
2878         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
2879                 for (i = 0; i < priv->num_grps; i++) {
2880                         disable_irq(priv->gfargrp[i].interruptTransmit);
2881                         disable_irq(priv->gfargrp[i].interruptReceive);
2882                         disable_irq(priv->gfargrp[i].interruptError);
2883                         gfar_interrupt(priv->gfargrp[i].interruptTransmit,
2884                                                 &priv->gfargrp[i]);
2885                         enable_irq(priv->gfargrp[i].interruptError);
2886                         enable_irq(priv->gfargrp[i].interruptReceive);
2887                         enable_irq(priv->gfargrp[i].interruptTransmit);
2888                 }
2889         } else {
2890                 for (i = 0; i < priv->num_grps; i++) {
2891                         disable_irq(priv->gfargrp[i].interruptTransmit);
2892                         gfar_interrupt(priv->gfargrp[i].interruptTransmit,
2893                                                 &priv->gfargrp[i]);
2894                         enable_irq(priv->gfargrp[i].interruptTransmit);
2895                 }
2896         }
2897 }
2898 #endif
2899
2900 /* The interrupt handler for devices with one interrupt */
2901 static irqreturn_t gfar_interrupt(int irq, void *grp_id)
2902 {
2903         struct gfar_priv_grp *gfargrp = grp_id;
2904
2905         /* Save ievent for future reference */
2906         u32 events = gfar_read(&gfargrp->regs->ievent);
2907
2908         /* Check for reception */
2909         if (events & IEVENT_RX_MASK)
2910                 gfar_receive(irq, grp_id);
2911
2912         /* Check for transmit completion */
2913         if (events & IEVENT_TX_MASK)
2914                 gfar_transmit(irq, grp_id);
2915
2916         /* Check for errors */
2917         if (events & IEVENT_ERR_MASK)
2918                 gfar_error(irq, grp_id);
2919
2920         return IRQ_HANDLED;
2921 }
2922
2923 /* Called every time the controller might need to be made
2924  * aware of new link state.  The PHY code conveys this
2925  * information through variables in the phydev structure, and this
2926  * function converts those variables into the appropriate
2927  * register values, and can bring down the device if needed.
2928  */
2929 static void adjust_link(struct net_device *dev)
2930 {
2931         struct gfar_private *priv = netdev_priv(dev);
2932         struct gfar __iomem *regs = priv->gfargrp[0].regs;
2933         unsigned long flags;
2934         struct phy_device *phydev = priv->phydev;
2935         int new_state = 0;
2936
2937         local_irq_save(flags);
2938         lock_tx_qs(priv);
2939
2940         if (phydev->link) {
2941                 u32 tempval = gfar_read(&regs->maccfg2);
2942                 u32 ecntrl = gfar_read(&regs->ecntrl);
2943
2944                 /* Now we make sure that we can be in full duplex mode.
2945                  * If not, we operate in half-duplex mode. */
2946                 if (phydev->duplex != priv->oldduplex) {
2947                         new_state = 1;
2948                         if (!(phydev->duplex))
2949                                 tempval &= ~(MACCFG2_FULL_DUPLEX);
2950                         else
2951                                 tempval |= MACCFG2_FULL_DUPLEX;
2952
2953                         priv->oldduplex = phydev->duplex;
2954                 }
2955
2956                 if (phydev->speed != priv->oldspeed) {
2957                         new_state = 1;
2958                         switch (phydev->speed) {
2959                         case 1000:
2960                                 tempval =
2961                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
2962
2963                                 ecntrl &= ~(ECNTRL_R100);
2964                                 break;
2965                         case 100:
2966                         case 10:
2967                                 tempval =
2968                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
2969
2970                                 /* Reduced mode distinguishes
2971                                  * between 10 and 100 */
2972                                 if (phydev->speed == SPEED_100)
2973                                         ecntrl |= ECNTRL_R100;
2974                                 else
2975                                         ecntrl &= ~(ECNTRL_R100);
2976                                 break;
2977                         default:
2978                                 netif_warn(priv, link, dev,
2979                                            "Ack!  Speed (%d) is not 10/100/1000!\n",
2980                                            phydev->speed);
2981                                 break;
2982                         }
2983
2984                         priv->oldspeed = phydev->speed;
2985                 }
2986
2987                 gfar_write(&regs->maccfg2, tempval);
2988                 gfar_write(&regs->ecntrl, ecntrl);
2989
2990                 if (!priv->oldlink) {
2991                         new_state = 1;
2992                         priv->oldlink = 1;
2993                 }
2994         } else if (priv->oldlink) {
2995                 new_state = 1;
2996                 priv->oldlink = 0;
2997                 priv->oldspeed = 0;
2998                 priv->oldduplex = -1;
2999         }
3000
3001         if (new_state && netif_msg_link(priv))
3002                 phy_print_status(phydev);
3003         unlock_tx_qs(priv);
3004         local_irq_restore(flags);
3005 }
3006
3007 /* Update the hash table based on the current list of multicast
3008  * addresses we subscribe to.  Also, change the promiscuity of
3009  * the device based on the flags (this function is called
3010  * whenever dev->flags is changed */
3011 static void gfar_set_multi(struct net_device *dev)
3012 {
3013         struct netdev_hw_addr *ha;
3014         struct gfar_private *priv = netdev_priv(dev);
3015         struct gfar __iomem *regs = priv->gfargrp[0].regs;
3016         u32 tempval;
3017
3018         if (dev->flags & IFF_PROMISC) {
3019                 /* Set RCTRL to PROM */
3020                 tempval = gfar_read(&regs->rctrl);
3021                 tempval |= RCTRL_PROM;
3022                 gfar_write(&regs->rctrl, tempval);
3023         } else {
3024                 /* Set RCTRL to not PROM */
3025                 tempval = gfar_read(&regs->rctrl);
3026                 tempval &= ~(RCTRL_PROM);
3027                 gfar_write(&regs->rctrl, tempval);
3028         }
3029
3030         if (dev->flags & IFF_ALLMULTI) {
3031                 /* Set the hash to rx all multicast frames */
3032                 gfar_write(&regs->igaddr0, 0xffffffff);
3033                 gfar_write(&regs->igaddr1, 0xffffffff);
3034                 gfar_write(&regs->igaddr2, 0xffffffff);
3035                 gfar_write(&regs->igaddr3, 0xffffffff);
3036                 gfar_write(&regs->igaddr4, 0xffffffff);
3037                 gfar_write(&regs->igaddr5, 0xffffffff);
3038                 gfar_write(&regs->igaddr6, 0xffffffff);
3039                 gfar_write(&regs->igaddr7, 0xffffffff);
3040                 gfar_write(&regs->gaddr0, 0xffffffff);
3041                 gfar_write(&regs->gaddr1, 0xffffffff);
3042                 gfar_write(&regs->gaddr2, 0xffffffff);
3043                 gfar_write(&regs->gaddr3, 0xffffffff);
3044                 gfar_write(&regs->gaddr4, 0xffffffff);
3045                 gfar_write(&regs->gaddr5, 0xffffffff);
3046                 gfar_write(&regs->gaddr6, 0xffffffff);
3047                 gfar_write(&regs->gaddr7, 0xffffffff);
3048         } else {
3049                 int em_num;
3050                 int idx;
3051
3052                 /* zero out the hash */
3053                 gfar_write(&regs->igaddr0, 0x0);
3054                 gfar_write(&regs->igaddr1, 0x0);
3055                 gfar_write(&regs->igaddr2, 0x0);
3056                 gfar_write(&regs->igaddr3, 0x0);
3057                 gfar_write(&regs->igaddr4, 0x0);
3058                 gfar_write(&regs->igaddr5, 0x0);
3059                 gfar_write(&regs->igaddr6, 0x0);
3060                 gfar_write(&regs->igaddr7, 0x0);
3061                 gfar_write(&regs->gaddr0, 0x0);
3062                 gfar_write(&regs->gaddr1, 0x0);
3063                 gfar_write(&regs->gaddr2, 0x0);
3064                 gfar_write(&regs->gaddr3, 0x0);
3065                 gfar_write(&regs->gaddr4, 0x0);
3066                 gfar_write(&regs->gaddr5, 0x0);
3067                 gfar_write(&regs->gaddr6, 0x0);
3068                 gfar_write(&regs->gaddr7, 0x0);
3069
3070                 /* If we have extended hash tables, we need to
3071                  * clear the exact match registers to prepare for
3072                  * setting them */
3073                 if (priv->extended_hash) {
3074                         em_num = GFAR_EM_NUM + 1;
3075                         gfar_clear_exact_match(dev);
3076                         idx = 1;
3077                 } else {
3078                         idx = 0;
3079                         em_num = 0;
3080                 }
3081
3082                 if (netdev_mc_empty(dev))
3083                         return;
3084
3085                 /* Parse the list, and set the appropriate bits */
3086                 netdev_for_each_mc_addr(ha, dev) {
3087                         if (idx < em_num) {
3088                                 gfar_set_mac_for_addr(dev, idx, ha->addr);
3089                                 idx++;
3090                         } else
3091                                 gfar_set_hash_for_addr(dev, ha->addr);
3092                 }
3093         }
3094 }
3095
3096
3097 /* Clears each of the exact match registers to zero, so they
3098  * don't interfere with normal reception */
3099 static void gfar_clear_exact_match(struct net_device *dev)
3100 {
3101         int idx;
3102         static const u8 zero_arr[MAC_ADDR_LEN] = {0, 0, 0, 0, 0, 0};
3103
3104         for(idx = 1;idx < GFAR_EM_NUM + 1;idx++)
3105                 gfar_set_mac_for_addr(dev, idx, zero_arr);
3106 }
3107
3108 /* Set the appropriate hash bit for the given addr */
3109 /* The algorithm works like so:
3110  * 1) Take the Destination Address (ie the multicast address), and
3111  * do a CRC on it (little endian), and reverse the bits of the
3112  * result.
3113  * 2) Use the 8 most significant bits as a hash into a 256-entry
3114  * table.  The table is controlled through 8 32-bit registers:
3115  * gaddr0-7.  gaddr0's MSB is entry 0, and gaddr7's LSB is
3116  * gaddr7.  This means that the 3 most significant bits in the
3117  * hash index which gaddr register to use, and the 5 other bits
3118  * indicate which bit (assuming an IBM numbering scheme, which
3119  * for PowerPC (tm) is usually the case) in the register holds
3120  * the entry. */
3121 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
3122 {
3123         u32 tempval;
3124         struct gfar_private *priv = netdev_priv(dev);
3125         u32 result = ether_crc(MAC_ADDR_LEN, addr);
3126         int width = priv->hash_width;
3127         u8 whichbit = (result >> (32 - width)) & 0x1f;
3128         u8 whichreg = result >> (32 - width + 5);
3129         u32 value = (1 << (31-whichbit));
3130
3131         tempval = gfar_read(priv->hash_regs[whichreg]);
3132         tempval |= value;
3133         gfar_write(priv->hash_regs[whichreg], tempval);
3134 }
3135
3136
3137 /* There are multiple MAC Address register pairs on some controllers
3138  * This function sets the numth pair to a given address
3139  */
3140 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
3141                                   const u8 *addr)
3142 {
3143         struct gfar_private *priv = netdev_priv(dev);
3144         struct gfar __iomem *regs = priv->gfargrp[0].regs;
3145         int idx;
3146         char tmpbuf[MAC_ADDR_LEN];
3147         u32 tempval;
3148         u32 __iomem *macptr = &regs->macstnaddr1;
3149
3150         macptr += num*2;
3151
3152         /* Now copy it into the mac registers backwards, cuz */
3153         /* little endian is silly */
3154         for (idx = 0; idx < MAC_ADDR_LEN; idx++)
3155                 tmpbuf[MAC_ADDR_LEN - 1 - idx] = addr[idx];
3156
3157         gfar_write(macptr, *((u32 *) (tmpbuf)));
3158
3159         tempval = *((u32 *) (tmpbuf + 4));
3160
3161         gfar_write(macptr+1, tempval);
3162 }
3163
3164 /* GFAR error interrupt handler */
3165 static irqreturn_t gfar_error(int irq, void *grp_id)
3166 {
3167         struct gfar_priv_grp *gfargrp = grp_id;
3168         struct gfar __iomem *regs = gfargrp->regs;
3169         struct gfar_private *priv= gfargrp->priv;
3170         struct net_device *dev = priv->ndev;
3171
3172         /* Save ievent for future reference */
3173         u32 events = gfar_read(&regs->ievent);
3174
3175         /* Clear IEVENT */
3176         gfar_write(&regs->ievent, events & IEVENT_ERR_MASK);
3177
3178         /* Magic Packet is not an error. */
3179         if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
3180             (events & IEVENT_MAG))
3181                 events &= ~IEVENT_MAG;
3182
3183         /* Hmm... */
3184         if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
3185                 netdev_dbg(dev, "error interrupt (ievent=0x%08x imask=0x%08x)\n",
3186                            events, gfar_read(&regs->imask));
3187
3188         /* Update the error counters */
3189         if (events & IEVENT_TXE) {
3190                 dev->stats.tx_errors++;
3191
3192                 if (events & IEVENT_LC)
3193                         dev->stats.tx_window_errors++;
3194                 if (events & IEVENT_CRL)
3195                         dev->stats.tx_aborted_errors++;
3196                 if (events & IEVENT_XFUN) {
3197                         unsigned long flags;
3198
3199                         netif_dbg(priv, tx_err, dev,
3200                                   "TX FIFO underrun, packet dropped\n");
3201                         dev->stats.tx_dropped++;
3202                         priv->extra_stats.tx_underrun++;
3203
3204                         local_irq_save(flags);
3205                         lock_tx_qs(priv);
3206
3207                         /* Reactivate the Tx Queues */
3208                         gfar_write(&regs->tstat, gfargrp->tstat);
3209
3210                         unlock_tx_qs(priv);
3211                         local_irq_restore(flags);
3212                 }
3213                 netif_dbg(priv, tx_err, dev, "Transmit Error\n");
3214         }
3215         if (events & IEVENT_BSY) {
3216                 dev->stats.rx_errors++;
3217                 priv->extra_stats.rx_bsy++;
3218
3219                 gfar_receive(irq, grp_id);
3220
3221                 netif_dbg(priv, rx_err, dev, "busy error (rstat: %x)\n",
3222                           gfar_read(&regs->rstat));
3223         }
3224         if (events & IEVENT_BABR) {
3225                 dev->stats.rx_errors++;
3226                 priv->extra_stats.rx_babr++;
3227
3228                 netif_dbg(priv, rx_err, dev, "babbling RX error\n");
3229         }
3230         if (events & IEVENT_EBERR) {
3231                 priv->extra_stats.eberr++;
3232                 netif_dbg(priv, rx_err, dev, "bus error\n");
3233         }
3234         if (events & IEVENT_RXC)
3235                 netif_dbg(priv, rx_status, dev, "control frame\n");
3236
3237         if (events & IEVENT_BABT) {
3238                 priv->extra_stats.tx_babt++;
3239                 netif_dbg(priv, tx_err, dev, "babbling TX error\n");
3240         }
3241         return IRQ_HANDLED;
3242 }
3243
3244 static struct of_device_id gfar_match[] =
3245 {
3246         {
3247                 .type = "network",
3248                 .compatible = "gianfar",
3249         },
3250         {
3251                 .compatible = "fsl,etsec2",
3252         },
3253         {},
3254 };
3255 MODULE_DEVICE_TABLE(of, gfar_match);
3256
3257 /* Structure for a device driver */
3258 static struct platform_driver gfar_driver = {
3259         .driver = {
3260                 .name = "fsl-gianfar",
3261                 .owner = THIS_MODULE,
3262                 .pm = GFAR_PM_OPS,
3263                 .of_match_table = gfar_match,
3264         },
3265         .probe = gfar_probe,
3266         .remove = gfar_remove,
3267 };
3268
3269 static int __init gfar_init(void)
3270 {
3271         return platform_driver_register(&gfar_driver);
3272 }
3273
3274 static void __exit gfar_exit(void)
3275 {
3276         platform_driver_unregister(&gfar_driver);
3277 }
3278
3279 module_init(gfar_init);
3280 module_exit(gfar_exit);
3281