1 /*******************************************************************************
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007-2009 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
29 /* Linux PRO/1000 Ethernet Driver main header file */
34 #include "e1000_mac.h"
35 #include "e1000_82575.h"
37 #include <linux/clocksource.h>
38 #include <linux/timecompare.h>
39 #include <linux/net_tstamp.h>
43 /* ((1000000000ns / (6000ints/s * 1024ns)) << 2 = 648 */
44 #define IGB_START_ITR 648
46 /* TX/RX descriptor defines */
47 #define IGB_DEFAULT_TXD 256
48 #define IGB_MIN_TXD 80
49 #define IGB_MAX_TXD 4096
51 #define IGB_DEFAULT_RXD 256
52 #define IGB_MIN_RXD 80
53 #define IGB_MAX_RXD 4096
55 #define IGB_DEFAULT_ITR 3 /* dynamic */
56 #define IGB_MAX_ITR_USECS 10000
57 #define IGB_MIN_ITR_USECS 10
58 #define NON_Q_VECTORS 1
59 #define MAX_Q_VECTORS 8
61 /* Transmit and receive queues */
62 #define IGB_MAX_RX_QUEUES (adapter->vfs_allocated_count ? 2 : \
63 (hw->mac.type > e1000_82575 ? 8 : 4))
64 #define IGB_ABS_MAX_TX_QUEUES 8
65 #define IGB_MAX_TX_QUEUES IGB_MAX_RX_QUEUES
67 #define IGB_MAX_VF_MC_ENTRIES 30
68 #define IGB_MAX_VF_FUNCTIONS 8
69 #define IGB_MAX_VFTA_ENTRIES 128
71 struct vf_data_storage {
72 unsigned char vf_mac_addresses[ETH_ALEN];
73 u16 vf_mc_hashes[IGB_MAX_VF_MC_ENTRIES];
77 unsigned long last_nack;
78 u16 pf_vlan; /* When set, guest VLAN config not allowed. */
82 #define IGB_VF_FLAG_CTS 0x00000001 /* VF is clear to send data */
83 #define IGB_VF_FLAG_UNI_PROMISC 0x00000002 /* VF has unicast promisc */
84 #define IGB_VF_FLAG_MULTI_PROMISC 0x00000004 /* VF has multicast promisc */
85 #define IGB_VF_FLAG_PF_SET_MAC 0x00000008 /* PF has set MAC address */
87 /* RX descriptor control thresholds.
88 * PTHRESH - MAC will consider prefetch if it has fewer than this number of
89 * descriptors available in its onboard memory.
90 * Setting this to 0 disables RX descriptor prefetch.
91 * HTHRESH - MAC will only prefetch if there are at least this many descriptors
92 * available in host memory.
93 * If PTHRESH is 0, this should also be 0.
94 * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back
95 * descriptors until either it has this many to write back, or the
98 #define IGB_RX_PTHRESH 8
99 #define IGB_RX_HTHRESH 8
100 #define IGB_RX_WTHRESH 1
101 #define IGB_TX_PTHRESH 8
102 #define IGB_TX_HTHRESH 1
103 #define IGB_TX_WTHRESH ((hw->mac.type == e1000_82576 && \
104 adapter->msix_entries) ? 1 : 16)
106 /* this is the size past which hardware will drop packets when setting LPE=0 */
107 #define MAXIMUM_ETHERNET_VLAN_SIZE 1522
109 /* Supported Rx Buffer Sizes */
110 #define IGB_RXBUFFER_64 64 /* Used for packet split */
111 #define IGB_RXBUFFER_128 128 /* Used for packet split */
112 #define IGB_RXBUFFER_1024 1024
113 #define IGB_RXBUFFER_2048 2048
114 #define IGB_RXBUFFER_16384 16384
116 #define MAX_STD_JUMBO_FRAME_SIZE 9234
118 /* How many Tx Descriptors do we need to call netif_wake_queue ? */
119 #define IGB_TX_QUEUE_WAKE 16
120 /* How many Rx Buffers do we bundle into one write to the hardware ? */
121 #define IGB_RX_BUFFER_WRITE 16 /* Must be power of 2 */
123 #define AUTO_ALL_MODES 0
124 #define IGB_EEPROM_APME 0x0400
126 #ifndef IGB_MASTER_SLAVE
127 /* Switch to override PHY master/slave setting */
128 #define IGB_MASTER_SLAVE e1000_ms_hw_default
131 #define IGB_MNG_VLAN_NONE -1
133 /* wrapper around a pointer to a socket buffer,
134 * so a DMA handle can be stored along with the buffer */
141 unsigned long time_stamp;
144 unsigned int bytecount;
158 struct igb_tx_queue_stats {
165 struct igb_rx_queue_stats {
173 struct igb_q_vector {
174 struct igb_adapter *adapter; /* backlink */
175 struct igb_ring *rx_ring;
176 struct igb_ring *tx_ring;
177 struct napi_struct napi;
184 void __iomem *itr_register;
186 char name[IFNAMSIZ + 9];
190 struct igb_q_vector *q_vector; /* backlink to q_vector */
191 struct net_device *netdev; /* back pointer to net_device */
192 struct device *dev; /* device pointer for dma mapping */
193 dma_addr_t dma; /* phys address of the ring */
194 void *desc; /* descriptor ring memory */
195 unsigned int size; /* length of desc. ring in bytes */
196 u16 count; /* number of desc. in the ring */
203 struct igb_buffer *buffer_info; /* array of buffer info structs */
205 unsigned int total_bytes;
206 unsigned int total_packets;
213 struct igb_tx_queue_stats tx_stats;
214 struct u64_stats_sync tx_syncp;
215 struct u64_stats_sync tx_syncp2;
220 struct igb_rx_queue_stats rx_stats;
221 struct u64_stats_sync rx_syncp;
227 #define IGB_RING_FLAG_RX_CSUM 0x00000001 /* RX CSUM enabled */
228 #define IGB_RING_FLAG_RX_SCTP_CSUM 0x00000002 /* SCTP CSUM offload enabled */
230 #define IGB_RING_FLAG_TX_CTX_IDX 0x00000001 /* HW requires context index */
232 #define IGB_ADVTXD_DCMD (E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS)
234 #define E1000_RX_DESC_ADV(R, i) \
235 (&(((union e1000_adv_rx_desc *)((R).desc))[i]))
236 #define E1000_TX_DESC_ADV(R, i) \
237 (&(((union e1000_adv_tx_desc *)((R).desc))[i]))
238 #define E1000_TX_CTXTDESC_ADV(R, i) \
239 (&(((struct e1000_adv_tx_context_desc *)((R).desc))[i]))
241 /* igb_desc_unused - calculate if we have unused descriptors */
242 static inline int igb_desc_unused(struct igb_ring *ring)
244 if (ring->next_to_clean > ring->next_to_use)
245 return ring->next_to_clean - ring->next_to_use - 1;
247 return ring->count + ring->next_to_clean - ring->next_to_use - 1;
250 /* board specific private data structure */
252 struct timer_list watchdog_timer;
253 struct timer_list phy_info_timer;
254 struct vlan_group *vlgrp;
262 /* Interrupt Throttle Rate */
268 struct work_struct reset_task;
269 struct work_struct watchdog_task;
271 u8 tx_timeout_factor;
272 struct timer_list blink_timer;
273 unsigned long led_status;
276 struct igb_ring *tx_ring[16];
277 u32 tx_timeout_count;
280 struct igb_ring *rx_ring[16];
287 /* OS defined structs */
288 struct net_device *netdev;
289 struct pci_dev *pdev;
290 struct cyclecounter cycles;
291 struct timecounter clock;
292 struct timecompare compare;
293 struct hwtstamp_config hwtstamp_config;
295 spinlock_t stats64_lock;
296 struct rtnl_link_stats64 stats64;
298 /* structs defined in e1000_hw.h */
300 struct e1000_hw_stats stats;
301 struct e1000_phy_info phy_info;
302 struct e1000_phy_stats phy_stats;
305 struct igb_ring test_tx_ring;
306 struct igb_ring test_rx_ring;
310 unsigned int num_q_vectors;
311 struct igb_q_vector *q_vector[MAX_Q_VECTORS];
312 struct msix_entry *msix_entries;
313 u32 eims_enable_mask;
316 /* to not mess up cache alignment, always add to the bottom */
321 struct igb_ring *multi_tx_table[IGB_ABS_MAX_TX_QUEUES];
324 unsigned int vfs_allocated_count;
325 struct vf_data_storage *vf_data;
329 #define IGB_FLAG_HAS_MSI (1 << 0)
330 #define IGB_FLAG_DCA_ENABLED (1 << 1)
331 #define IGB_FLAG_QUAD_PORT_A (1 << 2)
332 #define IGB_FLAG_QUEUE_PAIRS (1 << 3)
334 #define IGB_82576_TSYNC_SHIFT 19
335 #define IGB_82580_TSYNC_SHIFT 24
336 #define IGB_TS_HDR_LEN 16
347 extern char igb_driver_name[];
348 extern char igb_driver_version[];
350 extern int igb_up(struct igb_adapter *);
351 extern void igb_down(struct igb_adapter *);
352 extern void igb_reinit_locked(struct igb_adapter *);
353 extern void igb_reset(struct igb_adapter *);
354 extern int igb_set_spd_dplx(struct igb_adapter *, u16);
355 extern int igb_setup_tx_resources(struct igb_ring *);
356 extern int igb_setup_rx_resources(struct igb_ring *);
357 extern void igb_free_tx_resources(struct igb_ring *);
358 extern void igb_free_rx_resources(struct igb_ring *);
359 extern void igb_configure_tx_ring(struct igb_adapter *, struct igb_ring *);
360 extern void igb_configure_rx_ring(struct igb_adapter *, struct igb_ring *);
361 extern void igb_setup_tctl(struct igb_adapter *);
362 extern void igb_setup_rctl(struct igb_adapter *);
363 extern netdev_tx_t igb_xmit_frame_ring_adv(struct sk_buff *, struct igb_ring *);
364 extern void igb_unmap_and_free_tx_resource(struct igb_ring *,
365 struct igb_buffer *);
366 extern void igb_alloc_rx_buffers_adv(struct igb_ring *, int);
367 extern void igb_update_stats(struct igb_adapter *, struct rtnl_link_stats64 *);
368 extern bool igb_has_link(struct igb_adapter *adapter);
369 extern void igb_set_ethtool_ops(struct net_device *);
370 extern void igb_power_up_link(struct igb_adapter *);
372 static inline s32 igb_reset_phy(struct e1000_hw *hw)
374 if (hw->phy.ops.reset)
375 return hw->phy.ops.reset(hw);
380 static inline s32 igb_read_phy_reg(struct e1000_hw *hw, u32 offset, u16 *data)
382 if (hw->phy.ops.read_reg)
383 return hw->phy.ops.read_reg(hw, offset, data);
388 static inline s32 igb_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data)
390 if (hw->phy.ops.write_reg)
391 return hw->phy.ops.write_reg(hw, offset, data);
396 static inline s32 igb_get_phy_info(struct e1000_hw *hw)
398 if (hw->phy.ops.get_phy_info)
399 return hw->phy.ops.get_phy_info(hw);