1 /*******************************************************************************
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007-2009 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include <linux/module.h>
29 #include <linux/types.h>
30 #include <linux/init.h>
31 #include <linux/vmalloc.h>
32 #include <linux/pagemap.h>
33 #include <linux/netdevice.h>
34 #include <linux/ipv6.h>
35 #include <net/checksum.h>
36 #include <net/ip6_checksum.h>
37 #include <linux/net_tstamp.h>
38 #include <linux/mii.h>
39 #include <linux/ethtool.h>
40 #include <linux/if_vlan.h>
41 #include <linux/pci.h>
42 #include <linux/pci-aspm.h>
43 #include <linux/delay.h>
44 #include <linux/interrupt.h>
45 #include <linux/if_ether.h>
46 #include <linux/aer.h>
48 #include <linux/dca.h>
52 #define DRV_VERSION "1.3.16-k2"
53 char igb_driver_name[] = "igb";
54 char igb_driver_version[] = DRV_VERSION;
55 static const char igb_driver_string[] =
56 "Intel(R) Gigabit Ethernet Network Driver";
57 static const char igb_copyright[] = "Copyright (c) 2007-2009 Intel Corporation.";
59 static const struct e1000_info *igb_info_tbl[] = {
60 [board_82575] = &e1000_82575_info,
63 static struct pci_device_id igb_pci_tbl[] = {
64 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
65 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
66 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
67 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
68 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
69 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
70 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
71 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
72 /* required last entry */
76 MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
78 void igb_reset(struct igb_adapter *);
79 static int igb_setup_all_tx_resources(struct igb_adapter *);
80 static int igb_setup_all_rx_resources(struct igb_adapter *);
81 static void igb_free_all_tx_resources(struct igb_adapter *);
82 static void igb_free_all_rx_resources(struct igb_adapter *);
83 void igb_update_stats(struct igb_adapter *);
84 static int igb_probe(struct pci_dev *, const struct pci_device_id *);
85 static void __devexit igb_remove(struct pci_dev *pdev);
86 static int igb_sw_init(struct igb_adapter *);
87 static int igb_open(struct net_device *);
88 static int igb_close(struct net_device *);
89 static void igb_configure_tx(struct igb_adapter *);
90 static void igb_configure_rx(struct igb_adapter *);
91 static void igb_setup_rctl(struct igb_adapter *);
92 static void igb_clean_all_tx_rings(struct igb_adapter *);
93 static void igb_clean_all_rx_rings(struct igb_adapter *);
94 static void igb_clean_tx_ring(struct igb_ring *);
95 static void igb_clean_rx_ring(struct igb_ring *);
96 static void igb_set_multi(struct net_device *);
97 static void igb_update_phy_info(unsigned long);
98 static void igb_watchdog(unsigned long);
99 static void igb_watchdog_task(struct work_struct *);
100 static int igb_xmit_frame_ring_adv(struct sk_buff *, struct net_device *,
102 static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *);
103 static struct net_device_stats *igb_get_stats(struct net_device *);
104 static int igb_change_mtu(struct net_device *, int);
105 static int igb_set_mac(struct net_device *, void *);
106 static irqreturn_t igb_intr(int irq, void *);
107 static irqreturn_t igb_intr_msi(int irq, void *);
108 static irqreturn_t igb_msix_other(int irq, void *);
109 static irqreturn_t igb_msix_rx(int irq, void *);
110 static irqreturn_t igb_msix_tx(int irq, void *);
111 #ifdef CONFIG_IGB_DCA
112 static void igb_update_rx_dca(struct igb_ring *);
113 static void igb_update_tx_dca(struct igb_ring *);
114 static void igb_setup_dca(struct igb_adapter *);
115 #endif /* CONFIG_IGB_DCA */
116 static bool igb_clean_tx_irq(struct igb_ring *);
117 static int igb_poll(struct napi_struct *, int);
118 static bool igb_clean_rx_irq_adv(struct igb_ring *, int *, int);
119 static void igb_alloc_rx_buffers_adv(struct igb_ring *, int);
120 static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
121 static void igb_tx_timeout(struct net_device *);
122 static void igb_reset_task(struct work_struct *);
123 static void igb_vlan_rx_register(struct net_device *, struct vlan_group *);
124 static void igb_vlan_rx_add_vid(struct net_device *, u16);
125 static void igb_vlan_rx_kill_vid(struct net_device *, u16);
126 static void igb_restore_vlan(struct igb_adapter *);
127 static void igb_ping_all_vfs(struct igb_adapter *);
128 static void igb_msg_task(struct igb_adapter *);
129 static int igb_rcv_msg_from_vf(struct igb_adapter *, u32);
130 static inline void igb_set_rah_pool(struct e1000_hw *, int , int);
131 static void igb_set_mc_list_pools(struct igb_adapter *, int, u16);
132 static void igb_vmm_control(struct igb_adapter *);
133 static inline void igb_set_vmolr(struct e1000_hw *, int);
134 static inline int igb_set_vf_rlpml(struct igb_adapter *, int, int);
135 static int igb_set_vf_mac(struct igb_adapter *adapter, int, unsigned char *);
136 static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
139 static int igb_suspend(struct pci_dev *, pm_message_t);
140 static int igb_resume(struct pci_dev *);
142 static void igb_shutdown(struct pci_dev *);
143 #ifdef CONFIG_IGB_DCA
144 static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
145 static struct notifier_block dca_notifier = {
146 .notifier_call = igb_notify_dca,
151 #ifdef CONFIG_NET_POLL_CONTROLLER
152 /* for netdump / net console */
153 static void igb_netpoll(struct net_device *);
155 #ifdef CONFIG_PCI_IOV
156 static unsigned int max_vfs = 0;
157 module_param(max_vfs, uint, 0);
158 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
159 "per physical function");
160 #endif /* CONFIG_PCI_IOV */
162 static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
163 pci_channel_state_t);
164 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
165 static void igb_io_resume(struct pci_dev *);
167 static struct pci_error_handlers igb_err_handler = {
168 .error_detected = igb_io_error_detected,
169 .slot_reset = igb_io_slot_reset,
170 .resume = igb_io_resume,
174 static struct pci_driver igb_driver = {
175 .name = igb_driver_name,
176 .id_table = igb_pci_tbl,
178 .remove = __devexit_p(igb_remove),
180 /* Power Managment Hooks */
181 .suspend = igb_suspend,
182 .resume = igb_resume,
184 .shutdown = igb_shutdown,
185 .err_handler = &igb_err_handler
188 static int global_quad_port_a; /* global quad port a indication */
190 MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
191 MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
192 MODULE_LICENSE("GPL");
193 MODULE_VERSION(DRV_VERSION);
196 * Scale the NIC clock cycle by a large factor so that
197 * relatively small clock corrections can be added or
198 * substracted at each clock tick. The drawbacks of a
199 * large factor are a) that the clock register overflows
200 * more quickly (not such a big deal) and b) that the
201 * increment per tick has to fit into 24 bits.
204 * TIMINCA = IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS *
206 * TIMINCA += TIMINCA * adjustment [ppm] / 1e9
208 * The base scale factor is intentionally a power of two
209 * so that the division in %struct timecounter can be done with
212 #define IGB_TSYNC_SHIFT (19)
213 #define IGB_TSYNC_SCALE (1<<IGB_TSYNC_SHIFT)
216 * The duration of one clock cycle of the NIC.
218 * @todo This hard-coded value is part of the specification and might change
219 * in future hardware revisions. Add revision check.
221 #define IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS 16
223 #if (IGB_TSYNC_SCALE * IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS) >= (1<<24)
224 # error IGB_TSYNC_SCALE and/or IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS are too large to fit into TIMINCA
228 * igb_read_clock - read raw cycle counter (to be used by time counter)
230 static cycle_t igb_read_clock(const struct cyclecounter *tc)
232 struct igb_adapter *adapter =
233 container_of(tc, struct igb_adapter, cycles);
234 struct e1000_hw *hw = &adapter->hw;
237 stamp = rd32(E1000_SYSTIML);
238 stamp |= (u64)rd32(E1000_SYSTIMH) << 32ULL;
245 * igb_get_hw_dev_name - return device name string
246 * used by hardware layer to print debugging information
248 char *igb_get_hw_dev_name(struct e1000_hw *hw)
250 struct igb_adapter *adapter = hw->back;
251 return adapter->netdev->name;
255 * igb_get_time_str - format current NIC and system time as string
257 static char *igb_get_time_str(struct igb_adapter *adapter,
260 cycle_t hw = adapter->cycles.read(&adapter->cycles);
261 struct timespec nic = ns_to_timespec(timecounter_read(&adapter->clock));
263 struct timespec delta;
264 getnstimeofday(&sys);
266 delta = timespec_sub(nic, sys);
269 "HW %llu, NIC %ld.%09lus, SYS %ld.%09lus, NIC-SYS %lds + %09luns",
271 (long)nic.tv_sec, nic.tv_nsec,
272 (long)sys.tv_sec, sys.tv_nsec,
273 (long)delta.tv_sec, delta.tv_nsec);
280 * igb_desc_unused - calculate if we have unused descriptors
282 static int igb_desc_unused(struct igb_ring *ring)
284 if (ring->next_to_clean > ring->next_to_use)
285 return ring->next_to_clean - ring->next_to_use - 1;
287 return ring->count + ring->next_to_clean - ring->next_to_use - 1;
291 * igb_init_module - Driver Registration Routine
293 * igb_init_module is the first routine called when the driver is
294 * loaded. All it does is register with the PCI subsystem.
296 static int __init igb_init_module(void)
299 printk(KERN_INFO "%s - version %s\n",
300 igb_driver_string, igb_driver_version);
302 printk(KERN_INFO "%s\n", igb_copyright);
304 global_quad_port_a = 0;
306 #ifdef CONFIG_IGB_DCA
307 dca_register_notify(&dca_notifier);
310 ret = pci_register_driver(&igb_driver);
314 module_init(igb_init_module);
317 * igb_exit_module - Driver Exit Cleanup Routine
319 * igb_exit_module is called just before the driver is removed
322 static void __exit igb_exit_module(void)
324 #ifdef CONFIG_IGB_DCA
325 dca_unregister_notify(&dca_notifier);
327 pci_unregister_driver(&igb_driver);
330 module_exit(igb_exit_module);
332 #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
334 * igb_cache_ring_register - Descriptor ring to register mapping
335 * @adapter: board private structure to initialize
337 * Once we know the feature-set enabled for the device, we'll cache
338 * the register offset the descriptor ring is assigned to.
340 static void igb_cache_ring_register(struct igb_adapter *adapter)
343 unsigned int rbase_offset = adapter->vfs_allocated_count;
345 switch (adapter->hw.mac.type) {
347 /* The queues are allocated for virtualization such that VF 0
348 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
349 * In order to avoid collision we start at the first free queue
350 * and continue consuming queues in the same sequence
352 for (i = 0; i < adapter->num_rx_queues; i++)
353 adapter->rx_ring[i].reg_idx = rbase_offset +
355 for (i = 0; i < adapter->num_tx_queues; i++)
356 adapter->tx_ring[i].reg_idx = rbase_offset +
361 for (i = 0; i < adapter->num_rx_queues; i++)
362 adapter->rx_ring[i].reg_idx = i;
363 for (i = 0; i < adapter->num_tx_queues; i++)
364 adapter->tx_ring[i].reg_idx = i;
370 * igb_alloc_queues - Allocate memory for all rings
371 * @adapter: board private structure to initialize
373 * We allocate one ring per queue at run-time since we don't know the
374 * number of queues at compile-time.
376 static int igb_alloc_queues(struct igb_adapter *adapter)
380 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
381 sizeof(struct igb_ring), GFP_KERNEL);
382 if (!adapter->tx_ring)
385 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
386 sizeof(struct igb_ring), GFP_KERNEL);
387 if (!adapter->rx_ring) {
388 kfree(adapter->tx_ring);
392 adapter->rx_ring->buddy = adapter->tx_ring;
394 for (i = 0; i < adapter->num_tx_queues; i++) {
395 struct igb_ring *ring = &(adapter->tx_ring[i]);
396 ring->count = adapter->tx_ring_count;
397 ring->adapter = adapter;
398 ring->queue_index = i;
400 for (i = 0; i < adapter->num_rx_queues; i++) {
401 struct igb_ring *ring = &(adapter->rx_ring[i]);
402 ring->count = adapter->rx_ring_count;
403 ring->adapter = adapter;
404 ring->queue_index = i;
405 ring->itr_register = E1000_ITR;
407 /* set a default napi handler for each rx_ring */
408 netif_napi_add(adapter->netdev, &ring->napi, igb_poll, 64);
411 igb_cache_ring_register(adapter);
415 static void igb_free_queues(struct igb_adapter *adapter)
419 for (i = 0; i < adapter->num_rx_queues; i++)
420 netif_napi_del(&adapter->rx_ring[i].napi);
422 adapter->num_rx_queues = 0;
423 adapter->num_tx_queues = 0;
425 kfree(adapter->tx_ring);
426 kfree(adapter->rx_ring);
429 #define IGB_N0_QUEUE -1
430 static void igb_assign_vector(struct igb_adapter *adapter, int rx_queue,
431 int tx_queue, int msix_vector)
434 struct e1000_hw *hw = &adapter->hw;
437 switch (hw->mac.type) {
439 /* The 82575 assigns vectors using a bitmask, which matches the
440 bitmask for the EICR/EIMS/EIMC registers. To assign one
441 or more queues to a vector, we write the appropriate bits
442 into the MSIXBM register for that vector. */
443 if (rx_queue > IGB_N0_QUEUE) {
444 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
445 adapter->rx_ring[rx_queue].eims_value = msixbm;
447 if (tx_queue > IGB_N0_QUEUE) {
448 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
449 adapter->tx_ring[tx_queue].eims_value =
450 E1000_EICR_TX_QUEUE0 << tx_queue;
452 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
455 /* 82576 uses a table-based method for assigning vectors.
456 Each queue has a single entry in the table to which we write
457 a vector number along with a "valid" bit. Sadly, the layout
458 of the table is somewhat counterintuitive. */
459 if (rx_queue > IGB_N0_QUEUE) {
460 index = (rx_queue >> 1) + adapter->vfs_allocated_count;
461 ivar = array_rd32(E1000_IVAR0, index);
462 if (rx_queue & 0x1) {
463 /* vector goes into third byte of register */
464 ivar = ivar & 0xFF00FFFF;
465 ivar |= (msix_vector | E1000_IVAR_VALID) << 16;
467 /* vector goes into low byte of register */
468 ivar = ivar & 0xFFFFFF00;
469 ivar |= msix_vector | E1000_IVAR_VALID;
471 adapter->rx_ring[rx_queue].eims_value= 1 << msix_vector;
472 array_wr32(E1000_IVAR0, index, ivar);
474 if (tx_queue > IGB_N0_QUEUE) {
475 index = (tx_queue >> 1) + adapter->vfs_allocated_count;
476 ivar = array_rd32(E1000_IVAR0, index);
477 if (tx_queue & 0x1) {
478 /* vector goes into high byte of register */
479 ivar = ivar & 0x00FFFFFF;
480 ivar |= (msix_vector | E1000_IVAR_VALID) << 24;
482 /* vector goes into second byte of register */
483 ivar = ivar & 0xFFFF00FF;
484 ivar |= (msix_vector | E1000_IVAR_VALID) << 8;
486 adapter->tx_ring[tx_queue].eims_value= 1 << msix_vector;
487 array_wr32(E1000_IVAR0, index, ivar);
497 * igb_configure_msix - Configure MSI-X hardware
499 * igb_configure_msix sets up the hardware to properly
500 * generate MSI-X interrupts.
502 static void igb_configure_msix(struct igb_adapter *adapter)
506 struct e1000_hw *hw = &adapter->hw;
508 adapter->eims_enable_mask = 0;
509 if (hw->mac.type == e1000_82576)
510 /* Turn on MSI-X capability first, or our settings
511 * won't stick. And it will take days to debug. */
512 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
513 E1000_GPIE_PBA | E1000_GPIE_EIAME |
516 for (i = 0; i < adapter->num_tx_queues; i++) {
517 struct igb_ring *tx_ring = &adapter->tx_ring[i];
518 igb_assign_vector(adapter, IGB_N0_QUEUE, i, vector++);
519 adapter->eims_enable_mask |= tx_ring->eims_value;
520 if (tx_ring->itr_val)
521 writel(tx_ring->itr_val,
522 hw->hw_addr + tx_ring->itr_register);
524 writel(1, hw->hw_addr + tx_ring->itr_register);
527 for (i = 0; i < adapter->num_rx_queues; i++) {
528 struct igb_ring *rx_ring = &adapter->rx_ring[i];
529 rx_ring->buddy = NULL;
530 igb_assign_vector(adapter, i, IGB_N0_QUEUE, vector++);
531 adapter->eims_enable_mask |= rx_ring->eims_value;
532 if (rx_ring->itr_val)
533 writel(rx_ring->itr_val,
534 hw->hw_addr + rx_ring->itr_register);
536 writel(1, hw->hw_addr + rx_ring->itr_register);
540 /* set vector for other causes, i.e. link changes */
541 switch (hw->mac.type) {
543 array_wr32(E1000_MSIXBM(0), vector++,
546 tmp = rd32(E1000_CTRL_EXT);
547 /* enable MSI-X PBA support*/
548 tmp |= E1000_CTRL_EXT_PBA_CLR;
550 /* Auto-Mask interrupts upon ICR read. */
551 tmp |= E1000_CTRL_EXT_EIAME;
552 tmp |= E1000_CTRL_EXT_IRCA;
554 wr32(E1000_CTRL_EXT, tmp);
555 adapter->eims_enable_mask |= E1000_EIMS_OTHER;
556 adapter->eims_other = E1000_EIMS_OTHER;
561 tmp = (vector++ | E1000_IVAR_VALID) << 8;
562 wr32(E1000_IVAR_MISC, tmp);
564 adapter->eims_enable_mask = (1 << (vector)) - 1;
565 adapter->eims_other = 1 << (vector - 1);
568 /* do nothing, since nothing else supports MSI-X */
570 } /* switch (hw->mac.type) */
575 * igb_request_msix - Initialize MSI-X interrupts
577 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
580 static int igb_request_msix(struct igb_adapter *adapter)
582 struct net_device *netdev = adapter->netdev;
583 int i, err = 0, vector = 0;
587 for (i = 0; i < adapter->num_tx_queues; i++) {
588 struct igb_ring *ring = &(adapter->tx_ring[i]);
589 sprintf(ring->name, "%s-tx-%d", netdev->name, i);
590 err = request_irq(adapter->msix_entries[vector].vector,
591 &igb_msix_tx, 0, ring->name,
592 &(adapter->tx_ring[i]));
595 ring->itr_register = E1000_EITR(0) + (vector << 2);
596 ring->itr_val = 976; /* ~4000 ints/sec */
599 for (i = 0; i < adapter->num_rx_queues; i++) {
600 struct igb_ring *ring = &(adapter->rx_ring[i]);
601 if (strlen(netdev->name) < (IFNAMSIZ - 5))
602 sprintf(ring->name, "%s-rx-%d", netdev->name, i);
604 memcpy(ring->name, netdev->name, IFNAMSIZ);
605 err = request_irq(adapter->msix_entries[vector].vector,
606 &igb_msix_rx, 0, ring->name,
607 &(adapter->rx_ring[i]));
610 ring->itr_register = E1000_EITR(0) + (vector << 2);
611 ring->itr_val = adapter->itr;
615 err = request_irq(adapter->msix_entries[vector].vector,
616 &igb_msix_other, 0, netdev->name, netdev);
620 igb_configure_msix(adapter);
626 static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
628 if (adapter->msix_entries) {
629 pci_disable_msix(adapter->pdev);
630 kfree(adapter->msix_entries);
631 adapter->msix_entries = NULL;
632 } else if (adapter->flags & IGB_FLAG_HAS_MSI)
633 pci_disable_msi(adapter->pdev);
639 * igb_set_interrupt_capability - set MSI or MSI-X if supported
641 * Attempt to configure interrupts using the best available
642 * capabilities of the hardware and kernel.
644 static void igb_set_interrupt_capability(struct igb_adapter *adapter)
649 /* Number of supported queues. */
650 /* Having more queues than CPUs doesn't make sense. */
651 adapter->num_rx_queues = min_t(u32, IGB_MAX_RX_QUEUES, num_online_cpus());
652 adapter->num_tx_queues = min_t(u32, IGB_MAX_TX_QUEUES, num_online_cpus());
654 numvecs = adapter->num_tx_queues + adapter->num_rx_queues + 1;
655 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
657 if (!adapter->msix_entries)
660 for (i = 0; i < numvecs; i++)
661 adapter->msix_entries[i].entry = i;
663 err = pci_enable_msix(adapter->pdev,
664 adapter->msix_entries,
669 igb_reset_interrupt_capability(adapter);
671 /* If we can't do MSI-X, try MSI */
673 #ifdef CONFIG_PCI_IOV
674 /* disable SR-IOV for non MSI-X configurations */
675 if (adapter->vf_data) {
676 struct e1000_hw *hw = &adapter->hw;
677 /* disable iov and allow time for transactions to clear */
678 pci_disable_sriov(adapter->pdev);
681 kfree(adapter->vf_data);
682 adapter->vf_data = NULL;
683 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
685 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
688 adapter->num_rx_queues = 1;
689 adapter->num_tx_queues = 1;
690 if (!pci_enable_msi(adapter->pdev))
691 adapter->flags |= IGB_FLAG_HAS_MSI;
693 /* Notify the stack of the (possibly) reduced Tx Queue count. */
694 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
699 * igb_request_irq - initialize interrupts
701 * Attempts to configure interrupts using the best available
702 * capabilities of the hardware and kernel.
704 static int igb_request_irq(struct igb_adapter *adapter)
706 struct net_device *netdev = adapter->netdev;
707 struct e1000_hw *hw = &adapter->hw;
710 if (adapter->msix_entries) {
711 err = igb_request_msix(adapter);
714 /* fall back to MSI */
715 igb_reset_interrupt_capability(adapter);
716 if (!pci_enable_msi(adapter->pdev))
717 adapter->flags |= IGB_FLAG_HAS_MSI;
718 igb_free_all_tx_resources(adapter);
719 igb_free_all_rx_resources(adapter);
720 adapter->num_rx_queues = 1;
721 igb_alloc_queues(adapter);
723 switch (hw->mac.type) {
725 wr32(E1000_MSIXBM(0),
726 (E1000_EICR_RX_QUEUE0 | E1000_EIMS_OTHER));
729 wr32(E1000_IVAR0, E1000_IVAR_VALID);
736 if (adapter->flags & IGB_FLAG_HAS_MSI) {
737 err = request_irq(adapter->pdev->irq, &igb_intr_msi, 0,
738 netdev->name, netdev);
741 /* fall back to legacy interrupts */
742 igb_reset_interrupt_capability(adapter);
743 adapter->flags &= ~IGB_FLAG_HAS_MSI;
746 err = request_irq(adapter->pdev->irq, &igb_intr, IRQF_SHARED,
747 netdev->name, netdev);
750 dev_err(&adapter->pdev->dev, "Error %d getting interrupt\n",
757 static void igb_free_irq(struct igb_adapter *adapter)
759 struct net_device *netdev = adapter->netdev;
761 if (adapter->msix_entries) {
764 for (i = 0; i < adapter->num_tx_queues; i++)
765 free_irq(adapter->msix_entries[vector++].vector,
766 &(adapter->tx_ring[i]));
767 for (i = 0; i < adapter->num_rx_queues; i++)
768 free_irq(adapter->msix_entries[vector++].vector,
769 &(adapter->rx_ring[i]));
771 free_irq(adapter->msix_entries[vector++].vector, netdev);
775 free_irq(adapter->pdev->irq, netdev);
779 * igb_irq_disable - Mask off interrupt generation on the NIC
780 * @adapter: board private structure
782 static void igb_irq_disable(struct igb_adapter *adapter)
784 struct e1000_hw *hw = &adapter->hw;
786 if (adapter->msix_entries) {
788 wr32(E1000_EIMC, ~0);
795 synchronize_irq(adapter->pdev->irq);
799 * igb_irq_enable - Enable default interrupt generation settings
800 * @adapter: board private structure
802 static void igb_irq_enable(struct igb_adapter *adapter)
804 struct e1000_hw *hw = &adapter->hw;
806 if (adapter->msix_entries) {
807 wr32(E1000_EIAC, adapter->eims_enable_mask);
808 wr32(E1000_EIAM, adapter->eims_enable_mask);
809 wr32(E1000_EIMS, adapter->eims_enable_mask);
810 if (adapter->vfs_allocated_count)
811 wr32(E1000_MBVFIMR, 0xFF);
812 wr32(E1000_IMS, (E1000_IMS_LSC | E1000_IMS_VMMB |
813 E1000_IMS_DOUTSYNC));
815 wr32(E1000_IMS, IMS_ENABLE_MASK);
816 wr32(E1000_IAM, IMS_ENABLE_MASK);
820 static void igb_update_mng_vlan(struct igb_adapter *adapter)
822 struct net_device *netdev = adapter->netdev;
823 u16 vid = adapter->hw.mng_cookie.vlan_id;
824 u16 old_vid = adapter->mng_vlan_id;
825 if (adapter->vlgrp) {
826 if (!vlan_group_get_device(adapter->vlgrp, vid)) {
827 if (adapter->hw.mng_cookie.status &
828 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
829 igb_vlan_rx_add_vid(netdev, vid);
830 adapter->mng_vlan_id = vid;
832 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
834 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
836 !vlan_group_get_device(adapter->vlgrp, old_vid))
837 igb_vlan_rx_kill_vid(netdev, old_vid);
839 adapter->mng_vlan_id = vid;
844 * igb_release_hw_control - release control of the h/w to f/w
845 * @adapter: address of board private structure
847 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
848 * For ASF and Pass Through versions of f/w this means that the
849 * driver is no longer loaded.
852 static void igb_release_hw_control(struct igb_adapter *adapter)
854 struct e1000_hw *hw = &adapter->hw;
857 /* Let firmware take over control of h/w */
858 ctrl_ext = rd32(E1000_CTRL_EXT);
860 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
865 * igb_get_hw_control - get control of the h/w from f/w
866 * @adapter: address of board private structure
868 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
869 * For ASF and Pass Through versions of f/w this means that
870 * the driver is loaded.
873 static void igb_get_hw_control(struct igb_adapter *adapter)
875 struct e1000_hw *hw = &adapter->hw;
878 /* Let firmware know the driver has taken over */
879 ctrl_ext = rd32(E1000_CTRL_EXT);
881 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
885 * igb_configure - configure the hardware for RX and TX
886 * @adapter: private board structure
888 static void igb_configure(struct igb_adapter *adapter)
890 struct net_device *netdev = adapter->netdev;
893 igb_get_hw_control(adapter);
894 igb_set_multi(netdev);
896 igb_restore_vlan(adapter);
898 igb_configure_tx(adapter);
899 igb_setup_rctl(adapter);
900 igb_configure_rx(adapter);
902 igb_rx_fifo_flush_82575(&adapter->hw);
904 /* call igb_desc_unused which always leaves
905 * at least 1 descriptor unused to make sure
906 * next_to_use != next_to_clean */
907 for (i = 0; i < adapter->num_rx_queues; i++) {
908 struct igb_ring *ring = &adapter->rx_ring[i];
909 igb_alloc_rx_buffers_adv(ring, igb_desc_unused(ring));
913 adapter->tx_queue_len = netdev->tx_queue_len;
918 * igb_up - Open the interface and prepare it to handle traffic
919 * @adapter: board private structure
922 int igb_up(struct igb_adapter *adapter)
924 struct e1000_hw *hw = &adapter->hw;
927 /* hardware has been reset, we need to reload some things */
928 igb_configure(adapter);
930 clear_bit(__IGB_DOWN, &adapter->state);
932 for (i = 0; i < adapter->num_rx_queues; i++)
933 napi_enable(&adapter->rx_ring[i].napi);
934 if (adapter->msix_entries)
935 igb_configure_msix(adapter);
937 igb_vmm_control(adapter);
938 igb_set_rah_pool(hw, adapter->vfs_allocated_count, 0);
939 igb_set_vmolr(hw, adapter->vfs_allocated_count);
941 /* Clear any pending interrupts. */
943 igb_irq_enable(adapter);
945 netif_tx_start_all_queues(adapter->netdev);
947 /* Fire a link change interrupt to start the watchdog. */
948 wr32(E1000_ICS, E1000_ICS_LSC);
952 void igb_down(struct igb_adapter *adapter)
954 struct e1000_hw *hw = &adapter->hw;
955 struct net_device *netdev = adapter->netdev;
959 /* signal that we're down so the interrupt handler does not
960 * reschedule our watchdog timer */
961 set_bit(__IGB_DOWN, &adapter->state);
963 /* disable receives in the hardware */
964 rctl = rd32(E1000_RCTL);
965 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
966 /* flush and sleep below */
968 netif_tx_stop_all_queues(netdev);
970 /* disable transmits in the hardware */
971 tctl = rd32(E1000_TCTL);
972 tctl &= ~E1000_TCTL_EN;
973 wr32(E1000_TCTL, tctl);
974 /* flush both disables and wait for them to finish */
978 for (i = 0; i < adapter->num_rx_queues; i++)
979 napi_disable(&adapter->rx_ring[i].napi);
981 igb_irq_disable(adapter);
983 del_timer_sync(&adapter->watchdog_timer);
984 del_timer_sync(&adapter->phy_info_timer);
986 netdev->tx_queue_len = adapter->tx_queue_len;
987 netif_carrier_off(netdev);
989 /* record the stats before reset*/
990 igb_update_stats(adapter);
992 adapter->link_speed = 0;
993 adapter->link_duplex = 0;
995 if (!pci_channel_offline(adapter->pdev))
997 igb_clean_all_tx_rings(adapter);
998 igb_clean_all_rx_rings(adapter);
999 #ifdef CONFIG_IGB_DCA
1001 /* since we reset the hardware DCA settings were cleared */
1002 igb_setup_dca(adapter);
1006 void igb_reinit_locked(struct igb_adapter *adapter)
1008 WARN_ON(in_interrupt());
1009 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
1013 clear_bit(__IGB_RESETTING, &adapter->state);
1016 void igb_reset(struct igb_adapter *adapter)
1018 struct e1000_hw *hw = &adapter->hw;
1019 struct e1000_mac_info *mac = &hw->mac;
1020 struct e1000_fc_info *fc = &hw->fc;
1021 u32 pba = 0, tx_space, min_tx_space, min_rx_space;
1024 /* Repartition Pba for greater than 9k mtu
1025 * To take effect CTRL.RST is required.
1027 switch (mac->type) {
1029 pba = E1000_PBA_64K;
1033 pba = E1000_PBA_34K;
1037 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
1038 (mac->type < e1000_82576)) {
1039 /* adjust PBA for jumbo frames */
1040 wr32(E1000_PBA, pba);
1042 /* To maintain wire speed transmits, the Tx FIFO should be
1043 * large enough to accommodate two full transmit packets,
1044 * rounded up to the next 1KB and expressed in KB. Likewise,
1045 * the Rx FIFO should be large enough to accommodate at least
1046 * one full receive packet and is similarly rounded up and
1047 * expressed in KB. */
1048 pba = rd32(E1000_PBA);
1049 /* upper 16 bits has Tx packet buffer allocation size in KB */
1050 tx_space = pba >> 16;
1051 /* lower 16 bits has Rx packet buffer allocation size in KB */
1053 /* the tx fifo also stores 16 bytes of information about the tx
1054 * but don't include ethernet FCS because hardware appends it */
1055 min_tx_space = (adapter->max_frame_size +
1056 sizeof(union e1000_adv_tx_desc) -
1058 min_tx_space = ALIGN(min_tx_space, 1024);
1059 min_tx_space >>= 10;
1060 /* software strips receive CRC, so leave room for it */
1061 min_rx_space = adapter->max_frame_size;
1062 min_rx_space = ALIGN(min_rx_space, 1024);
1063 min_rx_space >>= 10;
1065 /* If current Tx allocation is less than the min Tx FIFO size,
1066 * and the min Tx FIFO size is less than the current Rx FIFO
1067 * allocation, take space away from current Rx allocation */
1068 if (tx_space < min_tx_space &&
1069 ((min_tx_space - tx_space) < pba)) {
1070 pba = pba - (min_tx_space - tx_space);
1072 /* if short on rx space, rx wins and must trump tx
1074 if (pba < min_rx_space)
1077 wr32(E1000_PBA, pba);
1080 /* flow control settings */
1081 /* The high water mark must be low enough to fit one full frame
1082 * (or the size used for early receive) above it in the Rx FIFO.
1083 * Set it to the lower of:
1084 * - 90% of the Rx FIFO size, or
1085 * - the full Rx FIFO size minus one full frame */
1086 hwm = min(((pba << 10) * 9 / 10),
1087 ((pba << 10) - 2 * adapter->max_frame_size));
1089 if (mac->type < e1000_82576) {
1090 fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */
1091 fc->low_water = fc->high_water - 8;
1093 fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */
1094 fc->low_water = fc->high_water - 16;
1096 fc->pause_time = 0xFFFF;
1098 fc->type = fc->original_type;
1100 /* disable receive for all VFs and wait one second */
1101 if (adapter->vfs_allocated_count) {
1103 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
1104 adapter->vf_data[i].clear_to_send = false;
1106 /* ping all the active vfs to let them know we are going down */
1107 igb_ping_all_vfs(adapter);
1109 /* disable transmits and receives */
1110 wr32(E1000_VFRE, 0);
1111 wr32(E1000_VFTE, 0);
1114 /* Allow time for pending master requests to run */
1115 adapter->hw.mac.ops.reset_hw(&adapter->hw);
1118 if (adapter->hw.mac.ops.init_hw(&adapter->hw))
1119 dev_err(&adapter->pdev->dev, "Hardware Error\n");
1121 igb_update_mng_vlan(adapter);
1123 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
1124 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
1126 igb_reset_adaptive(&adapter->hw);
1127 igb_get_phy_info(&adapter->hw);
1130 static const struct net_device_ops igb_netdev_ops = {
1131 .ndo_open = igb_open,
1132 .ndo_stop = igb_close,
1133 .ndo_start_xmit = igb_xmit_frame_adv,
1134 .ndo_get_stats = igb_get_stats,
1135 .ndo_set_multicast_list = igb_set_multi,
1136 .ndo_set_mac_address = igb_set_mac,
1137 .ndo_change_mtu = igb_change_mtu,
1138 .ndo_do_ioctl = igb_ioctl,
1139 .ndo_tx_timeout = igb_tx_timeout,
1140 .ndo_validate_addr = eth_validate_addr,
1141 .ndo_vlan_rx_register = igb_vlan_rx_register,
1142 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
1143 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
1144 #ifdef CONFIG_NET_POLL_CONTROLLER
1145 .ndo_poll_controller = igb_netpoll,
1150 * igb_probe - Device Initialization Routine
1151 * @pdev: PCI device information struct
1152 * @ent: entry in igb_pci_tbl
1154 * Returns 0 on success, negative on failure
1156 * igb_probe initializes an adapter identified by a pci_dev structure.
1157 * The OS initialization, configuring of the adapter private structure,
1158 * and a hardware reset occur.
1160 static int __devinit igb_probe(struct pci_dev *pdev,
1161 const struct pci_device_id *ent)
1163 struct net_device *netdev;
1164 struct igb_adapter *adapter;
1165 struct e1000_hw *hw;
1166 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
1167 unsigned long mmio_start, mmio_len;
1168 int err, pci_using_dac;
1169 u16 eeprom_data = 0;
1170 u16 eeprom_apme_mask = IGB_EEPROM_APME;
1173 err = pci_enable_device_mem(pdev);
1178 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
1180 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
1184 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1186 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1188 dev_err(&pdev->dev, "No usable DMA "
1189 "configuration, aborting\n");
1195 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
1201 err = pci_enable_pcie_error_reporting(pdev);
1203 dev_err(&pdev->dev, "pci_enable_pcie_error_reporting failed "
1205 /* non-fatal, continue */
1208 pci_set_master(pdev);
1209 pci_save_state(pdev);
1212 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
1213 IGB_ABS_MAX_TX_QUEUES);
1215 goto err_alloc_etherdev;
1217 SET_NETDEV_DEV(netdev, &pdev->dev);
1219 pci_set_drvdata(pdev, netdev);
1220 adapter = netdev_priv(netdev);
1221 adapter->netdev = netdev;
1222 adapter->pdev = pdev;
1225 adapter->msg_enable = NETIF_MSG_DRV | NETIF_MSG_PROBE;
1227 mmio_start = pci_resource_start(pdev, 0);
1228 mmio_len = pci_resource_len(pdev, 0);
1231 hw->hw_addr = ioremap(mmio_start, mmio_len);
1235 netdev->netdev_ops = &igb_netdev_ops;
1236 igb_set_ethtool_ops(netdev);
1237 netdev->watchdog_timeo = 5 * HZ;
1239 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1241 netdev->mem_start = mmio_start;
1242 netdev->mem_end = mmio_start + mmio_len;
1244 /* PCI config space info */
1245 hw->vendor_id = pdev->vendor;
1246 hw->device_id = pdev->device;
1247 hw->revision_id = pdev->revision;
1248 hw->subsystem_vendor_id = pdev->subsystem_vendor;
1249 hw->subsystem_device_id = pdev->subsystem_device;
1251 /* setup the private structure */
1253 /* Copy the default MAC, PHY and NVM function pointers */
1254 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
1255 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
1256 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
1257 /* Initialize skew-specific constants */
1258 err = ei->get_invariants(hw);
1262 #ifdef CONFIG_PCI_IOV
1263 /* since iov functionality isn't critical to base device function we
1264 * can accept failure. If it fails we don't allow iov to be enabled */
1265 if (hw->mac.type == e1000_82576) {
1266 /* 82576 supports a maximum of 7 VFs in addition to the PF */
1267 unsigned int num_vfs = (max_vfs > 7) ? 7 : max_vfs;
1269 unsigned char mac_addr[ETH_ALEN];
1272 adapter->vf_data = kcalloc(num_vfs,
1273 sizeof(struct vf_data_storage),
1275 if (!adapter->vf_data) {
1277 "Could not allocate VF private data - "
1278 "IOV enable failed\n");
1280 err = pci_enable_sriov(pdev, num_vfs);
1282 adapter->vfs_allocated_count = num_vfs;
1283 dev_info(&pdev->dev,
1284 "%d vfs allocated\n",
1287 i < adapter->vfs_allocated_count;
1289 random_ether_addr(mac_addr);
1290 igb_set_vf_mac(adapter, i,
1294 kfree(adapter->vf_data);
1295 adapter->vf_data = NULL;
1302 /* setup the private structure */
1303 err = igb_sw_init(adapter);
1307 igb_get_bus_info_pcie(hw);
1310 switch (hw->mac.type) {
1312 adapter->flags |= IGB_FLAG_NEED_CTX_IDX;
1319 hw->phy.autoneg_wait_to_complete = false;
1320 hw->mac.adaptive_ifs = true;
1322 /* Copper options */
1323 if (hw->phy.media_type == e1000_media_type_copper) {
1324 hw->phy.mdix = AUTO_ALL_MODES;
1325 hw->phy.disable_polarity_correction = false;
1326 hw->phy.ms_type = e1000_ms_hw_default;
1329 if (igb_check_reset_block(hw))
1330 dev_info(&pdev->dev,
1331 "PHY reset is blocked due to SOL/IDER session.\n");
1333 netdev->features = NETIF_F_SG |
1335 NETIF_F_HW_VLAN_TX |
1336 NETIF_F_HW_VLAN_RX |
1337 NETIF_F_HW_VLAN_FILTER;
1339 netdev->features |= NETIF_F_IPV6_CSUM;
1340 netdev->features |= NETIF_F_TSO;
1341 netdev->features |= NETIF_F_TSO6;
1343 netdev->features |= NETIF_F_GRO;
1345 netdev->vlan_features |= NETIF_F_TSO;
1346 netdev->vlan_features |= NETIF_F_TSO6;
1347 netdev->vlan_features |= NETIF_F_IP_CSUM;
1348 netdev->vlan_features |= NETIF_F_SG;
1351 netdev->features |= NETIF_F_HIGHDMA;
1353 if (adapter->hw.mac.type == e1000_82576)
1354 netdev->features |= NETIF_F_SCTP_CSUM;
1356 adapter->en_mng_pt = igb_enable_mng_pass_thru(&adapter->hw);
1358 /* before reading the NVM, reset the controller to put the device in a
1359 * known good starting state */
1360 hw->mac.ops.reset_hw(hw);
1362 /* make sure the NVM is good */
1363 if (igb_validate_nvm_checksum(hw) < 0) {
1364 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
1369 /* copy the MAC address out of the NVM */
1370 if (hw->mac.ops.read_mac_addr(hw))
1371 dev_err(&pdev->dev, "NVM Read Error\n");
1373 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
1374 memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len);
1376 if (!is_valid_ether_addr(netdev->perm_addr)) {
1377 dev_err(&pdev->dev, "Invalid MAC Address\n");
1382 setup_timer(&adapter->watchdog_timer, &igb_watchdog,
1383 (unsigned long) adapter);
1384 setup_timer(&adapter->phy_info_timer, &igb_update_phy_info,
1385 (unsigned long) adapter);
1387 INIT_WORK(&adapter->reset_task, igb_reset_task);
1388 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
1390 /* Initialize link properties that are user-changeable */
1391 adapter->fc_autoneg = true;
1392 hw->mac.autoneg = true;
1393 hw->phy.autoneg_advertised = 0x2f;
1395 hw->fc.original_type = e1000_fc_default;
1396 hw->fc.type = e1000_fc_default;
1398 adapter->itr_setting = IGB_DEFAULT_ITR;
1399 adapter->itr = IGB_START_ITR;
1401 igb_validate_mdi_setting(hw);
1403 /* Initial Wake on LAN setting If APM wake is enabled in the EEPROM,
1404 * enable the ACPI Magic Packet filter
1407 if (hw->bus.func == 0)
1408 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
1409 else if (hw->bus.func == 1)
1410 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
1412 if (eeprom_data & eeprom_apme_mask)
1413 adapter->eeprom_wol |= E1000_WUFC_MAG;
1415 /* now that we have the eeprom settings, apply the special cases where
1416 * the eeprom may be wrong or the board simply won't support wake on
1417 * lan on a particular port */
1418 switch (pdev->device) {
1419 case E1000_DEV_ID_82575GB_QUAD_COPPER:
1420 adapter->eeprom_wol = 0;
1422 case E1000_DEV_ID_82575EB_FIBER_SERDES:
1423 case E1000_DEV_ID_82576_FIBER:
1424 case E1000_DEV_ID_82576_SERDES:
1425 /* Wake events only supported on port A for dual fiber
1426 * regardless of eeprom setting */
1427 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
1428 adapter->eeprom_wol = 0;
1430 case E1000_DEV_ID_82576_QUAD_COPPER:
1431 /* if quad port adapter, disable WoL on all but port A */
1432 if (global_quad_port_a != 0)
1433 adapter->eeprom_wol = 0;
1435 adapter->flags |= IGB_FLAG_QUAD_PORT_A;
1436 /* Reset for multiple quad port adapters */
1437 if (++global_quad_port_a == 4)
1438 global_quad_port_a = 0;
1442 /* initialize the wol settings based on the eeprom settings */
1443 adapter->wol = adapter->eeprom_wol;
1444 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
1446 /* reset the hardware with the new settings */
1449 /* let the f/w know that the h/w is now under the control of the
1451 igb_get_hw_control(adapter);
1453 strcpy(netdev->name, "eth%d");
1454 err = register_netdev(netdev);
1458 /* carrier off reporting is important to ethtool even BEFORE open */
1459 netif_carrier_off(netdev);
1461 #ifdef CONFIG_IGB_DCA
1462 if (dca_add_requester(&pdev->dev) == 0) {
1463 adapter->flags |= IGB_FLAG_DCA_ENABLED;
1464 dev_info(&pdev->dev, "DCA enabled\n");
1465 igb_setup_dca(adapter);
1470 * Initialize hardware timer: we keep it running just in case
1471 * that some program needs it later on.
1473 memset(&adapter->cycles, 0, sizeof(adapter->cycles));
1474 adapter->cycles.read = igb_read_clock;
1475 adapter->cycles.mask = CLOCKSOURCE_MASK(64);
1476 adapter->cycles.mult = 1;
1477 adapter->cycles.shift = IGB_TSYNC_SHIFT;
1480 IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS * IGB_TSYNC_SCALE);
1483 * Avoid rollover while we initialize by resetting the time counter.
1485 wr32(E1000_SYSTIML, 0x00000000);
1486 wr32(E1000_SYSTIMH, 0x00000000);
1489 * Set registers so that rollover occurs soon to test this.
1491 wr32(E1000_SYSTIML, 0x00000000);
1492 wr32(E1000_SYSTIMH, 0xFF800000);
1495 timecounter_init(&adapter->clock,
1497 ktime_to_ns(ktime_get_real()));
1500 * Synchronize our NIC clock against system wall clock. NIC
1501 * time stamp reading requires ~3us per sample, each sample
1502 * was pretty stable even under load => only require 10
1503 * samples for each offset comparison.
1505 memset(&adapter->compare, 0, sizeof(adapter->compare));
1506 adapter->compare.source = &adapter->clock;
1507 adapter->compare.target = ktime_get_real;
1508 adapter->compare.num_samples = 10;
1509 timecompare_update(&adapter->compare, 0);
1515 "igb: %s: hw %p initialized timer\n",
1516 igb_get_time_str(adapter, buffer),
1521 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
1522 /* print bus type/speed/width info */
1523 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
1525 ((hw->bus.speed == e1000_bus_speed_2500)
1526 ? "2.5Gb/s" : "unknown"),
1527 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
1528 (hw->bus.width == e1000_bus_width_pcie_x2) ? "Width x2" :
1529 (hw->bus.width == e1000_bus_width_pcie_x1) ? "Width x1" :
1533 igb_read_part_num(hw, &part_num);
1534 dev_info(&pdev->dev, "%s: PBA No: %06x-%03x\n", netdev->name,
1535 (part_num >> 8), (part_num & 0xff));
1537 dev_info(&pdev->dev,
1538 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
1539 adapter->msix_entries ? "MSI-X" :
1540 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
1541 adapter->num_rx_queues, adapter->num_tx_queues);
1546 igb_release_hw_control(adapter);
1548 if (!igb_check_reset_block(hw))
1551 if (hw->flash_address)
1552 iounmap(hw->flash_address);
1554 igb_free_queues(adapter);
1556 iounmap(hw->hw_addr);
1558 free_netdev(netdev);
1560 pci_release_selected_regions(pdev, pci_select_bars(pdev,
1564 pci_disable_device(pdev);
1569 * igb_remove - Device Removal Routine
1570 * @pdev: PCI device information struct
1572 * igb_remove is called by the PCI subsystem to alert the driver
1573 * that it should release a PCI device. The could be caused by a
1574 * Hot-Plug event, or because the driver is going to be removed from
1577 static void __devexit igb_remove(struct pci_dev *pdev)
1579 struct net_device *netdev = pci_get_drvdata(pdev);
1580 struct igb_adapter *adapter = netdev_priv(netdev);
1581 struct e1000_hw *hw = &adapter->hw;
1584 /* flush_scheduled work may reschedule our watchdog task, so
1585 * explicitly disable watchdog tasks from being rescheduled */
1586 set_bit(__IGB_DOWN, &adapter->state);
1587 del_timer_sync(&adapter->watchdog_timer);
1588 del_timer_sync(&adapter->phy_info_timer);
1590 flush_scheduled_work();
1592 #ifdef CONFIG_IGB_DCA
1593 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
1594 dev_info(&pdev->dev, "DCA disabled\n");
1595 dca_remove_requester(&pdev->dev);
1596 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
1597 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
1601 /* Release control of h/w to f/w. If f/w is AMT enabled, this
1602 * would have already happened in close and is redundant. */
1603 igb_release_hw_control(adapter);
1605 unregister_netdev(netdev);
1607 if (!igb_check_reset_block(&adapter->hw))
1608 igb_reset_phy(&adapter->hw);
1610 igb_reset_interrupt_capability(adapter);
1612 igb_free_queues(adapter);
1614 #ifdef CONFIG_PCI_IOV
1615 /* reclaim resources allocated to VFs */
1616 if (adapter->vf_data) {
1617 /* disable iov and allow time for transactions to clear */
1618 pci_disable_sriov(pdev);
1621 kfree(adapter->vf_data);
1622 adapter->vf_data = NULL;
1623 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
1625 dev_info(&pdev->dev, "IOV Disabled\n");
1628 iounmap(hw->hw_addr);
1629 if (hw->flash_address)
1630 iounmap(hw->flash_address);
1631 pci_release_selected_regions(pdev, pci_select_bars(pdev,
1634 free_netdev(netdev);
1636 err = pci_disable_pcie_error_reporting(pdev);
1639 "pci_disable_pcie_error_reporting failed 0x%x\n", err);
1641 pci_disable_device(pdev);
1645 * igb_sw_init - Initialize general software structures (struct igb_adapter)
1646 * @adapter: board private structure to initialize
1648 * igb_sw_init initializes the Adapter private data structure.
1649 * Fields are initialized based on PCI device information and
1650 * OS network device settings (MTU size).
1652 static int __devinit igb_sw_init(struct igb_adapter *adapter)
1654 struct e1000_hw *hw = &adapter->hw;
1655 struct net_device *netdev = adapter->netdev;
1656 struct pci_dev *pdev = adapter->pdev;
1658 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
1660 adapter->tx_ring_count = IGB_DEFAULT_TXD;
1661 adapter->rx_ring_count = IGB_DEFAULT_RXD;
1662 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
1663 adapter->rx_ps_hdr_size = 0; /* disable packet split */
1664 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1665 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
1667 /* This call may decrease the number of queues depending on
1668 * interrupt mode. */
1669 igb_set_interrupt_capability(adapter);
1671 if (igb_alloc_queues(adapter)) {
1672 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
1676 /* Explicitly disable IRQ since the NIC can be in any state. */
1677 igb_irq_disable(adapter);
1679 set_bit(__IGB_DOWN, &adapter->state);
1684 * igb_open - Called when a network interface is made active
1685 * @netdev: network interface device structure
1687 * Returns 0 on success, negative value on failure
1689 * The open entry point is called when a network interface is made
1690 * active by the system (IFF_UP). At this point all resources needed
1691 * for transmit and receive operations are allocated, the interrupt
1692 * handler is registered with the OS, the watchdog timer is started,
1693 * and the stack is notified that the interface is ready.
1695 static int igb_open(struct net_device *netdev)
1697 struct igb_adapter *adapter = netdev_priv(netdev);
1698 struct e1000_hw *hw = &adapter->hw;
1702 /* disallow open during test */
1703 if (test_bit(__IGB_TESTING, &adapter->state))
1706 netif_carrier_off(netdev);
1708 /* allocate transmit descriptors */
1709 err = igb_setup_all_tx_resources(adapter);
1713 /* allocate receive descriptors */
1714 err = igb_setup_all_rx_resources(adapter);
1718 /* e1000_power_up_phy(adapter); */
1720 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1721 if ((adapter->hw.mng_cookie.status &
1722 E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
1723 igb_update_mng_vlan(adapter);
1725 /* before we allocate an interrupt, we must be ready to handle it.
1726 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
1727 * as soon as we call pci_request_irq, so we have to setup our
1728 * clean_rx handler before we do so. */
1729 igb_configure(adapter);
1731 igb_vmm_control(adapter);
1732 igb_set_rah_pool(hw, adapter->vfs_allocated_count, 0);
1733 igb_set_vmolr(hw, adapter->vfs_allocated_count);
1735 err = igb_request_irq(adapter);
1739 /* From here on the code is the same as igb_up() */
1740 clear_bit(__IGB_DOWN, &adapter->state);
1742 for (i = 0; i < adapter->num_rx_queues; i++)
1743 napi_enable(&adapter->rx_ring[i].napi);
1745 /* Clear any pending interrupts. */
1748 igb_irq_enable(adapter);
1750 netif_tx_start_all_queues(netdev);
1752 /* Fire a link status change interrupt to start the watchdog. */
1753 wr32(E1000_ICS, E1000_ICS_LSC);
1758 igb_release_hw_control(adapter);
1759 /* e1000_power_down_phy(adapter); */
1760 igb_free_all_rx_resources(adapter);
1762 igb_free_all_tx_resources(adapter);
1770 * igb_close - Disables a network interface
1771 * @netdev: network interface device structure
1773 * Returns 0, this is not allowed to fail
1775 * The close entry point is called when an interface is de-activated
1776 * by the OS. The hardware is still under the driver's control, but
1777 * needs to be disabled. A global MAC reset is issued to stop the
1778 * hardware, and all transmit and receive resources are freed.
1780 static int igb_close(struct net_device *netdev)
1782 struct igb_adapter *adapter = netdev_priv(netdev);
1784 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
1787 igb_free_irq(adapter);
1789 igb_free_all_tx_resources(adapter);
1790 igb_free_all_rx_resources(adapter);
1792 /* kill manageability vlan ID if supported, but not if a vlan with
1793 * the same ID is registered on the host OS (let 8021q kill it) */
1794 if ((adapter->hw.mng_cookie.status &
1795 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
1797 vlan_group_get_device(adapter->vlgrp, adapter->mng_vlan_id)))
1798 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
1804 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
1805 * @adapter: board private structure
1806 * @tx_ring: tx descriptor ring (for a specific queue) to setup
1808 * Return 0 on success, negative on failure
1810 int igb_setup_tx_resources(struct igb_adapter *adapter,
1811 struct igb_ring *tx_ring)
1813 struct pci_dev *pdev = adapter->pdev;
1816 size = sizeof(struct igb_buffer) * tx_ring->count;
1817 tx_ring->buffer_info = vmalloc(size);
1818 if (!tx_ring->buffer_info)
1820 memset(tx_ring->buffer_info, 0, size);
1822 /* round up to nearest 4K */
1823 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
1824 tx_ring->size = ALIGN(tx_ring->size, 4096);
1826 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
1832 tx_ring->adapter = adapter;
1833 tx_ring->next_to_use = 0;
1834 tx_ring->next_to_clean = 0;
1838 vfree(tx_ring->buffer_info);
1839 dev_err(&adapter->pdev->dev,
1840 "Unable to allocate memory for the transmit descriptor ring\n");
1845 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
1846 * (Descriptors) for all queues
1847 * @adapter: board private structure
1849 * Return 0 on success, negative on failure
1851 static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
1856 for (i = 0; i < adapter->num_tx_queues; i++) {
1857 err = igb_setup_tx_resources(adapter, &adapter->tx_ring[i]);
1859 dev_err(&adapter->pdev->dev,
1860 "Allocation for Tx Queue %u failed\n", i);
1861 for (i--; i >= 0; i--)
1862 igb_free_tx_resources(&adapter->tx_ring[i]);
1867 for (i = 0; i < IGB_MAX_TX_QUEUES; i++) {
1868 r_idx = i % adapter->num_tx_queues;
1869 adapter->multi_tx_table[i] = &adapter->tx_ring[r_idx];
1875 * igb_configure_tx - Configure transmit Unit after Reset
1876 * @adapter: board private structure
1878 * Configure the Tx unit of the MAC after a reset.
1880 static void igb_configure_tx(struct igb_adapter *adapter)
1883 struct e1000_hw *hw = &adapter->hw;
1888 for (i = 0; i < adapter->num_tx_queues; i++) {
1889 struct igb_ring *ring = &adapter->tx_ring[i];
1891 wr32(E1000_TDLEN(j),
1892 ring->count * sizeof(union e1000_adv_tx_desc));
1894 wr32(E1000_TDBAL(j),
1895 tdba & 0x00000000ffffffffULL);
1896 wr32(E1000_TDBAH(j), tdba >> 32);
1898 ring->head = E1000_TDH(j);
1899 ring->tail = E1000_TDT(j);
1900 writel(0, hw->hw_addr + ring->tail);
1901 writel(0, hw->hw_addr + ring->head);
1902 txdctl = rd32(E1000_TXDCTL(j));
1903 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
1904 wr32(E1000_TXDCTL(j), txdctl);
1906 /* Turn off Relaxed Ordering on head write-backs. The
1907 * writebacks MUST be delivered in order or it will
1908 * completely screw up our bookeeping.
1910 txctrl = rd32(E1000_DCA_TXCTRL(j));
1911 txctrl &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN;
1912 wr32(E1000_DCA_TXCTRL(j), txctrl);
1915 /* disable queue 0 to prevent tail bump w/o re-configuration */
1916 if (adapter->vfs_allocated_count)
1917 wr32(E1000_TXDCTL(0), 0);
1919 /* Program the Transmit Control Register */
1920 tctl = rd32(E1000_TCTL);
1921 tctl &= ~E1000_TCTL_CT;
1922 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
1923 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
1925 igb_config_collision_dist(hw);
1927 /* Setup Transmit Descriptor Settings for eop descriptor */
1928 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS;
1930 /* Enable transmits */
1931 tctl |= E1000_TCTL_EN;
1933 wr32(E1000_TCTL, tctl);
1937 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
1938 * @adapter: board private structure
1939 * @rx_ring: rx descriptor ring (for a specific queue) to setup
1941 * Returns 0 on success, negative on failure
1943 int igb_setup_rx_resources(struct igb_adapter *adapter,
1944 struct igb_ring *rx_ring)
1946 struct pci_dev *pdev = adapter->pdev;
1949 size = sizeof(struct igb_buffer) * rx_ring->count;
1950 rx_ring->buffer_info = vmalloc(size);
1951 if (!rx_ring->buffer_info)
1953 memset(rx_ring->buffer_info, 0, size);
1955 desc_len = sizeof(union e1000_adv_rx_desc);
1957 /* Round up to nearest 4K */
1958 rx_ring->size = rx_ring->count * desc_len;
1959 rx_ring->size = ALIGN(rx_ring->size, 4096);
1961 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size,
1967 rx_ring->next_to_clean = 0;
1968 rx_ring->next_to_use = 0;
1970 rx_ring->adapter = adapter;
1975 vfree(rx_ring->buffer_info);
1976 dev_err(&adapter->pdev->dev, "Unable to allocate memory for "
1977 "the receive descriptor ring\n");
1982 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
1983 * (Descriptors) for all queues
1984 * @adapter: board private structure
1986 * Return 0 on success, negative on failure
1988 static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
1992 for (i = 0; i < adapter->num_rx_queues; i++) {
1993 err = igb_setup_rx_resources(adapter, &adapter->rx_ring[i]);
1995 dev_err(&adapter->pdev->dev,
1996 "Allocation for Rx Queue %u failed\n", i);
1997 for (i--; i >= 0; i--)
1998 igb_free_rx_resources(&adapter->rx_ring[i]);
2007 * igb_setup_rctl - configure the receive control registers
2008 * @adapter: Board private structure
2010 static void igb_setup_rctl(struct igb_adapter *adapter)
2012 struct e1000_hw *hw = &adapter->hw;
2017 rctl = rd32(E1000_RCTL);
2019 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2020 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
2022 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
2023 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
2026 * enable stripping of CRC. It's unlikely this will break BMC
2027 * redirection as it did with e1000. Newer features require
2028 * that the HW strips the CRC.
2030 rctl |= E1000_RCTL_SECRC;
2033 * disable store bad packets and clear size bits.
2035 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
2037 /* enable LPE when to prevent packets larger than max_frame_size */
2038 rctl |= E1000_RCTL_LPE;
2040 /* Setup buffer sizes */
2041 switch (adapter->rx_buffer_len) {
2042 case IGB_RXBUFFER_256:
2043 rctl |= E1000_RCTL_SZ_256;
2045 case IGB_RXBUFFER_512:
2046 rctl |= E1000_RCTL_SZ_512;
2049 srrctl = ALIGN(adapter->rx_buffer_len, 1024)
2050 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2054 /* 82575 and greater support packet-split where the protocol
2055 * header is placed in skb->data and the packet data is
2056 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
2057 * In the case of a non-split, skb->data is linearly filled,
2058 * followed by the page buffers. Therefore, skb->data is
2059 * sized to hold the largest protocol header.
2061 /* allocations using alloc_page take too long for regular MTU
2062 * so only enable packet split for jumbo frames */
2063 if (adapter->netdev->mtu > ETH_DATA_LEN) {
2064 adapter->rx_ps_hdr_size = IGB_RXBUFFER_128;
2065 srrctl |= adapter->rx_ps_hdr_size <<
2066 E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
2067 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2069 adapter->rx_ps_hdr_size = 0;
2070 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
2073 /* Attention!!! For SR-IOV PF driver operations you must enable
2074 * queue drop for all VF and PF queues to prevent head of line blocking
2075 * if an un-trusted VF does not provide descriptors to hardware.
2077 if (adapter->vfs_allocated_count) {
2080 /* set all queue drop enable bits */
2081 wr32(E1000_QDE, ALL_QUEUES);
2082 srrctl |= E1000_SRRCTL_DROP_EN;
2084 /* disable queue 0 to prevent tail write w/o re-config */
2085 wr32(E1000_RXDCTL(0), 0);
2087 vmolr = rd32(E1000_VMOLR(adapter->vfs_allocated_count));
2088 if (rctl & E1000_RCTL_LPE)
2089 vmolr |= E1000_VMOLR_LPE;
2090 if (adapter->num_rx_queues > 1)
2091 vmolr |= E1000_VMOLR_RSSE;
2092 wr32(E1000_VMOLR(adapter->vfs_allocated_count), vmolr);
2095 for (i = 0; i < adapter->num_rx_queues; i++) {
2096 int j = adapter->rx_ring[i].reg_idx;
2097 wr32(E1000_SRRCTL(j), srrctl);
2100 wr32(E1000_RCTL, rctl);
2104 * igb_rlpml_set - set maximum receive packet size
2105 * @adapter: board private structure
2107 * Configure maximum receivable packet size.
2109 static void igb_rlpml_set(struct igb_adapter *adapter)
2111 u32 max_frame_size = adapter->max_frame_size;
2112 struct e1000_hw *hw = &adapter->hw;
2113 u16 pf_id = adapter->vfs_allocated_count;
2116 max_frame_size += VLAN_TAG_SIZE;
2118 /* if vfs are enabled we set RLPML to the largest possible request
2119 * size and set the VMOLR RLPML to the size we need */
2121 igb_set_vf_rlpml(adapter, max_frame_size, pf_id);
2122 max_frame_size = MAX_STD_JUMBO_FRAME_SIZE + VLAN_TAG_SIZE;
2125 wr32(E1000_RLPML, max_frame_size);
2129 * igb_configure_vt_default_pool - Configure VT default pool
2130 * @adapter: board private structure
2132 * Configure the default pool
2134 static void igb_configure_vt_default_pool(struct igb_adapter *adapter)
2136 struct e1000_hw *hw = &adapter->hw;
2137 u16 pf_id = adapter->vfs_allocated_count;
2140 /* not in sr-iov mode - do nothing */
2144 vtctl = rd32(E1000_VT_CTL);
2145 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
2146 E1000_VT_CTL_DISABLE_DEF_POOL);
2147 vtctl |= pf_id << E1000_VT_CTL_DEFAULT_POOL_SHIFT;
2148 wr32(E1000_VT_CTL, vtctl);
2152 * igb_configure_rx - Configure receive Unit after Reset
2153 * @adapter: board private structure
2155 * Configure the Rx unit of the MAC after a reset.
2157 static void igb_configure_rx(struct igb_adapter *adapter)
2160 struct e1000_hw *hw = &adapter->hw;
2165 /* disable receives while setting up the descriptors */
2166 rctl = rd32(E1000_RCTL);
2167 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
2171 if (adapter->itr_setting > 3)
2172 wr32(E1000_ITR, adapter->itr);
2174 /* Setup the HW Rx Head and Tail Descriptor Pointers and
2175 * the Base and Length of the Rx Descriptor Ring */
2176 for (i = 0; i < adapter->num_rx_queues; i++) {
2177 struct igb_ring *ring = &adapter->rx_ring[i];
2178 int j = ring->reg_idx;
2180 wr32(E1000_RDBAL(j),
2181 rdba & 0x00000000ffffffffULL);
2182 wr32(E1000_RDBAH(j), rdba >> 32);
2183 wr32(E1000_RDLEN(j),
2184 ring->count * sizeof(union e1000_adv_rx_desc));
2186 ring->head = E1000_RDH(j);
2187 ring->tail = E1000_RDT(j);
2188 writel(0, hw->hw_addr + ring->tail);
2189 writel(0, hw->hw_addr + ring->head);
2191 rxdctl = rd32(E1000_RXDCTL(j));
2192 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
2193 rxdctl &= 0xFFF00000;
2194 rxdctl |= IGB_RX_PTHRESH;
2195 rxdctl |= IGB_RX_HTHRESH << 8;
2196 rxdctl |= IGB_RX_WTHRESH << 16;
2197 wr32(E1000_RXDCTL(j), rxdctl);
2200 if (adapter->num_rx_queues > 1) {
2209 get_random_bytes(&random[0], 40);
2211 if (hw->mac.type >= e1000_82576)
2215 for (j = 0; j < (32 * 4); j++) {
2217 adapter->rx_ring[(j % adapter->num_rx_queues)].reg_idx << shift;
2220 hw->hw_addr + E1000_RETA(0) + (j & ~3));
2222 if (adapter->vfs_allocated_count)
2223 mrqc = E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
2225 mrqc = E1000_MRQC_ENABLE_RSS_4Q;
2227 /* Fill out hash function seeds */
2228 for (j = 0; j < 10; j++)
2229 array_wr32(E1000_RSSRK(0), j, random[j]);
2231 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
2232 E1000_MRQC_RSS_FIELD_IPV4_TCP);
2233 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 |
2234 E1000_MRQC_RSS_FIELD_IPV6_TCP);
2235 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4_UDP |
2236 E1000_MRQC_RSS_FIELD_IPV6_UDP);
2237 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
2238 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
2240 wr32(E1000_MRQC, mrqc);
2241 } else if (adapter->vfs_allocated_count) {
2242 /* Enable multi-queue for sr-iov */
2243 wr32(E1000_MRQC, E1000_MRQC_ENABLE_VMDQ);
2246 /* Enable Receive Checksum Offload for TCP and UDP */
2247 rxcsum = rd32(E1000_RXCSUM);
2248 /* Disable raw packet checksumming */
2249 rxcsum |= E1000_RXCSUM_PCSD;
2251 if (adapter->hw.mac.type == e1000_82576)
2252 /* Enable Receive Checksum Offload for SCTP */
2253 rxcsum |= E1000_RXCSUM_CRCOFL;
2255 /* Don't need to set TUOFL or IPOFL, they default to 1 */
2256 wr32(E1000_RXCSUM, rxcsum);
2258 /* Set the default pool for the PF's first queue */
2259 igb_configure_vt_default_pool(adapter);
2261 igb_rlpml_set(adapter);
2263 /* Enable Receives */
2264 wr32(E1000_RCTL, rctl);
2268 * igb_free_tx_resources - Free Tx Resources per Queue
2269 * @tx_ring: Tx descriptor ring for a specific queue
2271 * Free all transmit software resources
2273 void igb_free_tx_resources(struct igb_ring *tx_ring)
2275 struct pci_dev *pdev = tx_ring->adapter->pdev;
2277 igb_clean_tx_ring(tx_ring);
2279 vfree(tx_ring->buffer_info);
2280 tx_ring->buffer_info = NULL;
2282 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
2284 tx_ring->desc = NULL;
2288 * igb_free_all_tx_resources - Free Tx Resources for All Queues
2289 * @adapter: board private structure
2291 * Free all transmit software resources
2293 static void igb_free_all_tx_resources(struct igb_adapter *adapter)
2297 for (i = 0; i < adapter->num_tx_queues; i++)
2298 igb_free_tx_resources(&adapter->tx_ring[i]);
2301 static void igb_unmap_and_free_tx_resource(struct igb_adapter *adapter,
2302 struct igb_buffer *buffer_info)
2304 buffer_info->dma = 0;
2305 if (buffer_info->skb) {
2306 skb_dma_unmap(&adapter->pdev->dev, buffer_info->skb,
2308 dev_kfree_skb_any(buffer_info->skb);
2309 buffer_info->skb = NULL;
2311 buffer_info->time_stamp = 0;
2312 /* buffer_info must be completely set up in the transmit path */
2316 * igb_clean_tx_ring - Free Tx Buffers
2317 * @tx_ring: ring to be cleaned
2319 static void igb_clean_tx_ring(struct igb_ring *tx_ring)
2321 struct igb_adapter *adapter = tx_ring->adapter;
2322 struct igb_buffer *buffer_info;
2326 if (!tx_ring->buffer_info)
2328 /* Free all the Tx ring sk_buffs */
2330 for (i = 0; i < tx_ring->count; i++) {
2331 buffer_info = &tx_ring->buffer_info[i];
2332 igb_unmap_and_free_tx_resource(adapter, buffer_info);
2335 size = sizeof(struct igb_buffer) * tx_ring->count;
2336 memset(tx_ring->buffer_info, 0, size);
2338 /* Zero out the descriptor ring */
2340 memset(tx_ring->desc, 0, tx_ring->size);
2342 tx_ring->next_to_use = 0;
2343 tx_ring->next_to_clean = 0;
2345 writel(0, adapter->hw.hw_addr + tx_ring->head);
2346 writel(0, adapter->hw.hw_addr + tx_ring->tail);
2350 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
2351 * @adapter: board private structure
2353 static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
2357 for (i = 0; i < adapter->num_tx_queues; i++)
2358 igb_clean_tx_ring(&adapter->tx_ring[i]);
2362 * igb_free_rx_resources - Free Rx Resources
2363 * @rx_ring: ring to clean the resources from
2365 * Free all receive software resources
2367 void igb_free_rx_resources(struct igb_ring *rx_ring)
2369 struct pci_dev *pdev = rx_ring->adapter->pdev;
2371 igb_clean_rx_ring(rx_ring);
2373 vfree(rx_ring->buffer_info);
2374 rx_ring->buffer_info = NULL;
2376 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
2378 rx_ring->desc = NULL;
2382 * igb_free_all_rx_resources - Free Rx Resources for All Queues
2383 * @adapter: board private structure
2385 * Free all receive software resources
2387 static void igb_free_all_rx_resources(struct igb_adapter *adapter)
2391 for (i = 0; i < adapter->num_rx_queues; i++)
2392 igb_free_rx_resources(&adapter->rx_ring[i]);
2396 * igb_clean_rx_ring - Free Rx Buffers per Queue
2397 * @rx_ring: ring to free buffers from
2399 static void igb_clean_rx_ring(struct igb_ring *rx_ring)
2401 struct igb_adapter *adapter = rx_ring->adapter;
2402 struct igb_buffer *buffer_info;
2403 struct pci_dev *pdev = adapter->pdev;
2407 if (!rx_ring->buffer_info)
2409 /* Free all the Rx ring sk_buffs */
2410 for (i = 0; i < rx_ring->count; i++) {
2411 buffer_info = &rx_ring->buffer_info[i];
2412 if (buffer_info->dma) {
2413 if (adapter->rx_ps_hdr_size)
2414 pci_unmap_single(pdev, buffer_info->dma,
2415 adapter->rx_ps_hdr_size,
2416 PCI_DMA_FROMDEVICE);
2418 pci_unmap_single(pdev, buffer_info->dma,
2419 adapter->rx_buffer_len,
2420 PCI_DMA_FROMDEVICE);
2421 buffer_info->dma = 0;
2424 if (buffer_info->skb) {
2425 dev_kfree_skb(buffer_info->skb);
2426 buffer_info->skb = NULL;
2428 if (buffer_info->page) {
2429 if (buffer_info->page_dma)
2430 pci_unmap_page(pdev, buffer_info->page_dma,
2432 PCI_DMA_FROMDEVICE);
2433 put_page(buffer_info->page);
2434 buffer_info->page = NULL;
2435 buffer_info->page_dma = 0;
2436 buffer_info->page_offset = 0;
2440 size = sizeof(struct igb_buffer) * rx_ring->count;
2441 memset(rx_ring->buffer_info, 0, size);
2443 /* Zero out the descriptor ring */
2444 memset(rx_ring->desc, 0, rx_ring->size);
2446 rx_ring->next_to_clean = 0;
2447 rx_ring->next_to_use = 0;
2449 writel(0, adapter->hw.hw_addr + rx_ring->head);
2450 writel(0, adapter->hw.hw_addr + rx_ring->tail);
2454 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
2455 * @adapter: board private structure
2457 static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
2461 for (i = 0; i < adapter->num_rx_queues; i++)
2462 igb_clean_rx_ring(&adapter->rx_ring[i]);
2466 * igb_set_mac - Change the Ethernet Address of the NIC
2467 * @netdev: network interface device structure
2468 * @p: pointer to an address structure
2470 * Returns 0 on success, negative on failure
2472 static int igb_set_mac(struct net_device *netdev, void *p)
2474 struct igb_adapter *adapter = netdev_priv(netdev);
2475 struct e1000_hw *hw = &adapter->hw;
2476 struct sockaddr *addr = p;
2478 if (!is_valid_ether_addr(addr->sa_data))
2479 return -EADDRNOTAVAIL;
2481 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2482 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
2484 hw->mac.ops.rar_set(hw, hw->mac.addr, 0);
2486 igb_set_rah_pool(hw, adapter->vfs_allocated_count, 0);
2492 * igb_set_multi - Multicast and Promiscuous mode set
2493 * @netdev: network interface device structure
2495 * The set_multi entry point is called whenever the multicast address
2496 * list or the network interface flags are updated. This routine is
2497 * responsible for configuring the hardware for proper multicast,
2498 * promiscuous mode, and all-multi behavior.
2500 static void igb_set_multi(struct net_device *netdev)
2502 struct igb_adapter *adapter = netdev_priv(netdev);
2503 struct e1000_hw *hw = &adapter->hw;
2504 struct e1000_mac_info *mac = &hw->mac;
2505 struct dev_mc_list *mc_ptr;
2506 u8 *mta_list = NULL;
2510 /* Check for Promiscuous and All Multicast modes */
2512 rctl = rd32(E1000_RCTL);
2514 if (netdev->flags & IFF_PROMISC) {
2515 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2516 rctl &= ~E1000_RCTL_VFE;
2518 if (netdev->flags & IFF_ALLMULTI) {
2519 rctl |= E1000_RCTL_MPE;
2520 rctl &= ~E1000_RCTL_UPE;
2522 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
2523 rctl |= E1000_RCTL_VFE;
2525 wr32(E1000_RCTL, rctl);
2527 if (netdev->mc_count) {
2528 mta_list = kzalloc(netdev->mc_count * 6, GFP_ATOMIC);
2530 dev_err(&adapter->pdev->dev,
2531 "failed to allocate multicast filter list\n");
2536 /* The shared function expects a packed array of only addresses. */
2537 mc_ptr = netdev->mc_list;
2539 for (i = 0; i < netdev->mc_count; i++) {
2542 memcpy(mta_list + (i*ETH_ALEN), mc_ptr->dmi_addr, ETH_ALEN);
2543 mc_ptr = mc_ptr->next;
2545 igb_update_mc_addr_list(hw, mta_list, i,
2546 adapter->vfs_allocated_count + 1,
2547 mac->rar_entry_count);
2549 igb_set_mc_list_pools(adapter, i, mac->rar_entry_count);
2550 igb_restore_vf_multicasts(adapter);
2555 /* Need to wait a few seconds after link up to get diagnostic information from
2557 static void igb_update_phy_info(unsigned long data)
2559 struct igb_adapter *adapter = (struct igb_adapter *) data;
2560 igb_get_phy_info(&adapter->hw);
2564 * igb_has_link - check shared code for link and determine up/down
2565 * @adapter: pointer to driver private info
2567 static bool igb_has_link(struct igb_adapter *adapter)
2569 struct e1000_hw *hw = &adapter->hw;
2570 bool link_active = false;
2573 /* get_link_status is set on LSC (link status) interrupt or
2574 * rx sequence error interrupt. get_link_status will stay
2575 * false until the e1000_check_for_link establishes link
2576 * for copper adapters ONLY
2578 switch (hw->phy.media_type) {
2579 case e1000_media_type_copper:
2580 if (hw->mac.get_link_status) {
2581 ret_val = hw->mac.ops.check_for_link(hw);
2582 link_active = !hw->mac.get_link_status;
2587 case e1000_media_type_fiber:
2588 ret_val = hw->mac.ops.check_for_link(hw);
2589 link_active = !!(rd32(E1000_STATUS) & E1000_STATUS_LU);
2591 case e1000_media_type_internal_serdes:
2592 ret_val = hw->mac.ops.check_for_link(hw);
2593 link_active = hw->mac.serdes_has_link;
2596 case e1000_media_type_unknown:
2604 * igb_watchdog - Timer Call-back
2605 * @data: pointer to adapter cast into an unsigned long
2607 static void igb_watchdog(unsigned long data)
2609 struct igb_adapter *adapter = (struct igb_adapter *)data;
2610 /* Do the rest outside of interrupt context */
2611 schedule_work(&adapter->watchdog_task);
2614 static void igb_watchdog_task(struct work_struct *work)
2616 struct igb_adapter *adapter = container_of(work,
2617 struct igb_adapter, watchdog_task);
2618 struct e1000_hw *hw = &adapter->hw;
2619 struct net_device *netdev = adapter->netdev;
2620 struct igb_ring *tx_ring = adapter->tx_ring;
2625 link = igb_has_link(adapter);
2626 if ((netif_carrier_ok(netdev)) && link)
2630 if (!netif_carrier_ok(netdev)) {
2632 hw->mac.ops.get_speed_and_duplex(&adapter->hw,
2633 &adapter->link_speed,
2634 &adapter->link_duplex);
2636 ctrl = rd32(E1000_CTRL);
2637 /* Links status message must follow this format */
2638 printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s, "
2639 "Flow Control: %s\n",
2641 adapter->link_speed,
2642 adapter->link_duplex == FULL_DUPLEX ?
2643 "Full Duplex" : "Half Duplex",
2644 ((ctrl & E1000_CTRL_TFCE) && (ctrl &
2645 E1000_CTRL_RFCE)) ? "RX/TX" : ((ctrl &
2646 E1000_CTRL_RFCE) ? "RX" : ((ctrl &
2647 E1000_CTRL_TFCE) ? "TX" : "None")));
2649 /* tweak tx_queue_len according to speed/duplex and
2650 * adjust the timeout factor */
2651 netdev->tx_queue_len = adapter->tx_queue_len;
2652 adapter->tx_timeout_factor = 1;
2653 switch (adapter->link_speed) {
2655 netdev->tx_queue_len = 10;
2656 adapter->tx_timeout_factor = 14;
2659 netdev->tx_queue_len = 100;
2660 /* maybe add some timeout factor ? */
2664 netif_carrier_on(netdev);
2666 igb_ping_all_vfs(adapter);
2668 /* link state has changed, schedule phy info update */
2669 if (!test_bit(__IGB_DOWN, &adapter->state))
2670 mod_timer(&adapter->phy_info_timer,
2671 round_jiffies(jiffies + 2 * HZ));
2674 if (netif_carrier_ok(netdev)) {
2675 adapter->link_speed = 0;
2676 adapter->link_duplex = 0;
2677 /* Links status message must follow this format */
2678 printk(KERN_INFO "igb: %s NIC Link is Down\n",
2680 netif_carrier_off(netdev);
2682 igb_ping_all_vfs(adapter);
2684 /* link state has changed, schedule phy info update */
2685 if (!test_bit(__IGB_DOWN, &adapter->state))
2686 mod_timer(&adapter->phy_info_timer,
2687 round_jiffies(jiffies + 2 * HZ));
2692 igb_update_stats(adapter);
2694 hw->mac.tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
2695 adapter->tpt_old = adapter->stats.tpt;
2696 hw->mac.collision_delta = adapter->stats.colc - adapter->colc_old;
2697 adapter->colc_old = adapter->stats.colc;
2699 adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
2700 adapter->gorc_old = adapter->stats.gorc;
2701 adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
2702 adapter->gotc_old = adapter->stats.gotc;
2704 igb_update_adaptive(&adapter->hw);
2706 if (!netif_carrier_ok(netdev)) {
2707 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
2708 /* We've lost link, so the controller stops DMA,
2709 * but we've got queued Tx work that's never going
2710 * to get done, so reset controller to flush Tx.
2711 * (Do the reset outside of interrupt context). */
2712 adapter->tx_timeout_count++;
2713 schedule_work(&adapter->reset_task);
2714 /* return immediately since reset is imminent */
2719 /* Cause software interrupt to ensure rx ring is cleaned */
2720 if (adapter->msix_entries) {
2721 for (i = 0; i < adapter->num_rx_queues; i++)
2722 eics |= adapter->rx_ring[i].eims_value;
2723 wr32(E1000_EICS, eics);
2725 wr32(E1000_ICS, E1000_ICS_RXDMT0);
2728 /* Force detection of hung controller every watchdog period */
2729 tx_ring->detect_tx_hung = true;
2731 /* Reset the timer */
2732 if (!test_bit(__IGB_DOWN, &adapter->state))
2733 mod_timer(&adapter->watchdog_timer,
2734 round_jiffies(jiffies + 2 * HZ));
2737 enum latency_range {
2741 latency_invalid = 255
2746 * igb_update_ring_itr - update the dynamic ITR value based on packet size
2748 * Stores a new ITR value based on strictly on packet size. This
2749 * algorithm is less sophisticated than that used in igb_update_itr,
2750 * due to the difficulty of synchronizing statistics across multiple
2751 * receive rings. The divisors and thresholds used by this fuction
2752 * were determined based on theoretical maximum wire speed and testing
2753 * data, in order to minimize response time while increasing bulk
2755 * This functionality is controlled by the InterruptThrottleRate module
2756 * parameter (see igb_param.c)
2757 * NOTE: This function is called only when operating in a multiqueue
2758 * receive environment.
2759 * @rx_ring: pointer to ring
2761 static void igb_update_ring_itr(struct igb_ring *rx_ring)
2763 int new_val = rx_ring->itr_val;
2764 int avg_wire_size = 0;
2765 struct igb_adapter *adapter = rx_ring->adapter;
2767 if (!rx_ring->total_packets)
2768 goto clear_counts; /* no packets, so don't do anything */
2770 /* For non-gigabit speeds, just fix the interrupt rate at 4000
2771 * ints/sec - ITR timer value of 120 ticks.
2773 if (adapter->link_speed != SPEED_1000) {
2777 avg_wire_size = rx_ring->total_bytes / rx_ring->total_packets;
2779 /* Add 24 bytes to size to account for CRC, preamble, and gap */
2780 avg_wire_size += 24;
2782 /* Don't starve jumbo frames */
2783 avg_wire_size = min(avg_wire_size, 3000);
2785 /* Give a little boost to mid-size frames */
2786 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
2787 new_val = avg_wire_size / 3;
2789 new_val = avg_wire_size / 2;
2792 if (new_val != rx_ring->itr_val) {
2793 rx_ring->itr_val = new_val;
2794 rx_ring->set_itr = 1;
2797 rx_ring->total_bytes = 0;
2798 rx_ring->total_packets = 0;
2802 * igb_update_itr - update the dynamic ITR value based on statistics
2803 * Stores a new ITR value based on packets and byte
2804 * counts during the last interrupt. The advantage of per interrupt
2805 * computation is faster updates and more accurate ITR for the current
2806 * traffic pattern. Constants in this function were computed
2807 * based on theoretical maximum wire speed and thresholds were set based
2808 * on testing data as well as attempting to minimize response time
2809 * while increasing bulk throughput.
2810 * this functionality is controlled by the InterruptThrottleRate module
2811 * parameter (see igb_param.c)
2812 * NOTE: These calculations are only valid when operating in a single-
2813 * queue environment.
2814 * @adapter: pointer to adapter
2815 * @itr_setting: current adapter->itr
2816 * @packets: the number of packets during this measurement interval
2817 * @bytes: the number of bytes during this measurement interval
2819 static unsigned int igb_update_itr(struct igb_adapter *adapter, u16 itr_setting,
2820 int packets, int bytes)
2822 unsigned int retval = itr_setting;
2825 goto update_itr_done;
2827 switch (itr_setting) {
2828 case lowest_latency:
2829 /* handle TSO and jumbo frames */
2830 if (bytes/packets > 8000)
2831 retval = bulk_latency;
2832 else if ((packets < 5) && (bytes > 512))
2833 retval = low_latency;
2835 case low_latency: /* 50 usec aka 20000 ints/s */
2836 if (bytes > 10000) {
2837 /* this if handles the TSO accounting */
2838 if (bytes/packets > 8000) {
2839 retval = bulk_latency;
2840 } else if ((packets < 10) || ((bytes/packets) > 1200)) {
2841 retval = bulk_latency;
2842 } else if ((packets > 35)) {
2843 retval = lowest_latency;
2845 } else if (bytes/packets > 2000) {
2846 retval = bulk_latency;
2847 } else if (packets <= 2 && bytes < 512) {
2848 retval = lowest_latency;
2851 case bulk_latency: /* 250 usec aka 4000 ints/s */
2852 if (bytes > 25000) {
2854 retval = low_latency;
2855 } else if (bytes < 1500) {
2856 retval = low_latency;
2865 static void igb_set_itr(struct igb_adapter *adapter)
2868 u32 new_itr = adapter->itr;
2870 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2871 if (adapter->link_speed != SPEED_1000) {
2877 adapter->rx_itr = igb_update_itr(adapter,
2879 adapter->rx_ring->total_packets,
2880 adapter->rx_ring->total_bytes);
2882 if (adapter->rx_ring->buddy) {
2883 adapter->tx_itr = igb_update_itr(adapter,
2885 adapter->tx_ring->total_packets,
2886 adapter->tx_ring->total_bytes);
2887 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2889 current_itr = adapter->rx_itr;
2892 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2893 if (adapter->itr_setting == 3 && current_itr == lowest_latency)
2894 current_itr = low_latency;
2896 switch (current_itr) {
2897 /* counts and packets in update_itr are dependent on these numbers */
2898 case lowest_latency:
2899 new_itr = 56; /* aka 70,000 ints/sec */
2902 new_itr = 196; /* aka 20,000 ints/sec */
2905 new_itr = 980; /* aka 4,000 ints/sec */
2912 adapter->rx_ring->total_bytes = 0;
2913 adapter->rx_ring->total_packets = 0;
2914 if (adapter->rx_ring->buddy) {
2915 adapter->rx_ring->buddy->total_bytes = 0;
2916 adapter->rx_ring->buddy->total_packets = 0;
2919 if (new_itr != adapter->itr) {
2920 /* this attempts to bias the interrupt rate towards Bulk
2921 * by adding intermediate steps when interrupt rate is
2923 new_itr = new_itr > adapter->itr ?
2924 max((new_itr * adapter->itr) /
2925 (new_itr + (adapter->itr >> 2)), new_itr) :
2927 /* Don't write the value here; it resets the adapter's
2928 * internal timer, and causes us to delay far longer than
2929 * we should between interrupts. Instead, we write the ITR
2930 * value at the beginning of the next interrupt so the timing
2931 * ends up being correct.
2933 adapter->itr = new_itr;
2934 adapter->rx_ring->itr_val = new_itr;
2935 adapter->rx_ring->set_itr = 1;
2942 #define IGB_TX_FLAGS_CSUM 0x00000001
2943 #define IGB_TX_FLAGS_VLAN 0x00000002
2944 #define IGB_TX_FLAGS_TSO 0x00000004
2945 #define IGB_TX_FLAGS_IPV4 0x00000008
2946 #define IGB_TX_FLAGS_TSTAMP 0x00000010
2947 #define IGB_TX_FLAGS_VLAN_MASK 0xffff0000
2948 #define IGB_TX_FLAGS_VLAN_SHIFT 16
2950 static inline int igb_tso_adv(struct igb_adapter *adapter,
2951 struct igb_ring *tx_ring,
2952 struct sk_buff *skb, u32 tx_flags, u8 *hdr_len)
2954 struct e1000_adv_tx_context_desc *context_desc;
2957 struct igb_buffer *buffer_info;
2958 u32 info = 0, tu_cmd = 0;
2959 u32 mss_l4len_idx, l4len;
2962 if (skb_header_cloned(skb)) {
2963 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2968 l4len = tcp_hdrlen(skb);
2971 if (skb->protocol == htons(ETH_P_IP)) {
2972 struct iphdr *iph = ip_hdr(skb);
2975 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2979 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
2980 ipv6_hdr(skb)->payload_len = 0;
2981 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
2982 &ipv6_hdr(skb)->daddr,
2986 i = tx_ring->next_to_use;
2988 buffer_info = &tx_ring->buffer_info[i];
2989 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
2990 /* VLAN MACLEN IPLEN */
2991 if (tx_flags & IGB_TX_FLAGS_VLAN)
2992 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
2993 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
2994 *hdr_len += skb_network_offset(skb);
2995 info |= skb_network_header_len(skb);
2996 *hdr_len += skb_network_header_len(skb);
2997 context_desc->vlan_macip_lens = cpu_to_le32(info);
2999 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
3000 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
3002 if (skb->protocol == htons(ETH_P_IP))
3003 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
3004 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
3006 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
3009 mss_l4len_idx = (skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT);
3010 mss_l4len_idx |= (l4len << E1000_ADVTXD_L4LEN_SHIFT);
3012 /* For 82575, context index must be unique per ring. */
3013 if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
3014 mss_l4len_idx |= tx_ring->queue_index << 4;
3016 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
3017 context_desc->seqnum_seed = 0;
3019 buffer_info->time_stamp = jiffies;
3020 buffer_info->next_to_watch = i;
3021 buffer_info->dma = 0;
3023 if (i == tx_ring->count)
3026 tx_ring->next_to_use = i;
3031 static inline bool igb_tx_csum_adv(struct igb_adapter *adapter,
3032 struct igb_ring *tx_ring,
3033 struct sk_buff *skb, u32 tx_flags)
3035 struct e1000_adv_tx_context_desc *context_desc;
3037 struct igb_buffer *buffer_info;
3038 u32 info = 0, tu_cmd = 0;
3040 if ((skb->ip_summed == CHECKSUM_PARTIAL) ||
3041 (tx_flags & IGB_TX_FLAGS_VLAN)) {
3042 i = tx_ring->next_to_use;
3043 buffer_info = &tx_ring->buffer_info[i];
3044 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
3046 if (tx_flags & IGB_TX_FLAGS_VLAN)
3047 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
3048 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
3049 if (skb->ip_summed == CHECKSUM_PARTIAL)
3050 info |= skb_network_header_len(skb);
3052 context_desc->vlan_macip_lens = cpu_to_le32(info);
3054 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
3056 if (skb->ip_summed == CHECKSUM_PARTIAL) {
3059 if (skb->protocol == cpu_to_be16(ETH_P_8021Q)) {
3060 const struct vlan_ethhdr *vhdr =
3061 (const struct vlan_ethhdr*)skb->data;
3063 protocol = vhdr->h_vlan_encapsulated_proto;
3065 protocol = skb->protocol;
3069 case cpu_to_be16(ETH_P_IP):
3070 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
3071 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
3072 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
3073 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
3074 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
3076 case cpu_to_be16(ETH_P_IPV6):
3077 /* XXX what about other V6 headers?? */
3078 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
3079 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
3080 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
3081 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
3084 if (unlikely(net_ratelimit()))
3085 dev_warn(&adapter->pdev->dev,
3086 "partial checksum but proto=%x!\n",
3092 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
3093 context_desc->seqnum_seed = 0;
3094 if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
3095 context_desc->mss_l4len_idx =
3096 cpu_to_le32(tx_ring->queue_index << 4);
3098 context_desc->mss_l4len_idx = 0;
3100 buffer_info->time_stamp = jiffies;
3101 buffer_info->next_to_watch = i;
3102 buffer_info->dma = 0;
3105 if (i == tx_ring->count)
3107 tx_ring->next_to_use = i;
3114 #define IGB_MAX_TXD_PWR 16
3115 #define IGB_MAX_DATA_PER_TXD (1<<IGB_MAX_TXD_PWR)
3117 static inline int igb_tx_map_adv(struct igb_adapter *adapter,
3118 struct igb_ring *tx_ring, struct sk_buff *skb,
3121 struct igb_buffer *buffer_info;
3122 unsigned int len = skb_headlen(skb);
3123 unsigned int count = 0, i;
3127 i = tx_ring->next_to_use;
3129 if (skb_dma_map(&adapter->pdev->dev, skb, DMA_TO_DEVICE)) {
3130 dev_err(&adapter->pdev->dev, "TX DMA map failed\n");
3134 map = skb_shinfo(skb)->dma_maps;
3136 buffer_info = &tx_ring->buffer_info[i];
3137 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
3138 buffer_info->length = len;
3139 /* set time_stamp *before* dma to help avoid a possible race */
3140 buffer_info->time_stamp = jiffies;
3141 buffer_info->next_to_watch = i;
3142 buffer_info->dma = map[count];
3145 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) {
3146 struct skb_frag_struct *frag;
3149 if (i == tx_ring->count)
3152 frag = &skb_shinfo(skb)->frags[f];
3155 buffer_info = &tx_ring->buffer_info[i];
3156 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
3157 buffer_info->length = len;
3158 buffer_info->time_stamp = jiffies;
3159 buffer_info->next_to_watch = i;
3160 buffer_info->dma = map[count];
3164 tx_ring->buffer_info[i].skb = skb;
3165 tx_ring->buffer_info[first].next_to_watch = i;
3170 static inline void igb_tx_queue_adv(struct igb_adapter *adapter,
3171 struct igb_ring *tx_ring,
3172 int tx_flags, int count, u32 paylen,
3175 union e1000_adv_tx_desc *tx_desc = NULL;
3176 struct igb_buffer *buffer_info;
3177 u32 olinfo_status = 0, cmd_type_len;
3180 cmd_type_len = (E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_IFCS |
3181 E1000_ADVTXD_DCMD_DEXT);
3183 if (tx_flags & IGB_TX_FLAGS_VLAN)
3184 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
3186 if (tx_flags & IGB_TX_FLAGS_TSTAMP)
3187 cmd_type_len |= E1000_ADVTXD_MAC_TSTAMP;
3189 if (tx_flags & IGB_TX_FLAGS_TSO) {
3190 cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
3192 /* insert tcp checksum */
3193 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3195 /* insert ip checksum */
3196 if (tx_flags & IGB_TX_FLAGS_IPV4)
3197 olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
3199 } else if (tx_flags & IGB_TX_FLAGS_CSUM) {
3200 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3203 if ((adapter->flags & IGB_FLAG_NEED_CTX_IDX) &&
3204 (tx_flags & (IGB_TX_FLAGS_CSUM | IGB_TX_FLAGS_TSO |
3205 IGB_TX_FLAGS_VLAN)))
3206 olinfo_status |= tx_ring->queue_index << 4;
3208 olinfo_status |= ((paylen - hdr_len) << E1000_ADVTXD_PAYLEN_SHIFT);
3210 i = tx_ring->next_to_use;
3212 buffer_info = &tx_ring->buffer_info[i];
3213 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
3214 tx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
3215 tx_desc->read.cmd_type_len =
3216 cpu_to_le32(cmd_type_len | buffer_info->length);
3217 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
3219 if (i == tx_ring->count)
3223 tx_desc->read.cmd_type_len |= cpu_to_le32(adapter->txd_cmd);
3224 /* Force memory writes to complete before letting h/w
3225 * know there are new descriptors to fetch. (Only
3226 * applicable for weak-ordered memory model archs,
3227 * such as IA-64). */
3230 tx_ring->next_to_use = i;
3231 writel(i, adapter->hw.hw_addr + tx_ring->tail);
3232 /* we need this if more than one processor can write to our tail
3233 * at a time, it syncronizes IO on IA64/Altix systems */
3237 static int __igb_maybe_stop_tx(struct net_device *netdev,
3238 struct igb_ring *tx_ring, int size)
3240 struct igb_adapter *adapter = netdev_priv(netdev);
3242 netif_stop_subqueue(netdev, tx_ring->queue_index);
3244 /* Herbert's original patch had:
3245 * smp_mb__after_netif_stop_queue();
3246 * but since that doesn't exist yet, just open code it. */
3249 /* We need to check again in a case another CPU has just
3250 * made room available. */
3251 if (igb_desc_unused(tx_ring) < size)
3255 netif_wake_subqueue(netdev, tx_ring->queue_index);
3256 ++adapter->restart_queue;
3260 static int igb_maybe_stop_tx(struct net_device *netdev,
3261 struct igb_ring *tx_ring, int size)
3263 if (igb_desc_unused(tx_ring) >= size)
3265 return __igb_maybe_stop_tx(netdev, tx_ring, size);
3268 static int igb_xmit_frame_ring_adv(struct sk_buff *skb,
3269 struct net_device *netdev,
3270 struct igb_ring *tx_ring)
3272 struct igb_adapter *adapter = netdev_priv(netdev);
3274 unsigned int tx_flags = 0;
3278 union skb_shared_tx *shtx;
3280 if (test_bit(__IGB_DOWN, &adapter->state)) {
3281 dev_kfree_skb_any(skb);
3282 return NETDEV_TX_OK;
3285 if (skb->len <= 0) {
3286 dev_kfree_skb_any(skb);
3287 return NETDEV_TX_OK;
3290 /* need: 1 descriptor per page,
3291 * + 2 desc gap to keep tail from touching head,
3292 * + 1 desc for skb->data,
3293 * + 1 desc for context descriptor,
3294 * otherwise try next time */
3295 if (igb_maybe_stop_tx(netdev, tx_ring, skb_shinfo(skb)->nr_frags + 4)) {
3296 /* this is a hard error */
3297 return NETDEV_TX_BUSY;
3301 * TODO: check that there currently is no other packet with
3302 * time stamping in the queue
3304 * When doing time stamping, keep the connection to the socket
3305 * a while longer: it is still needed by skb_hwtstamp_tx(),
3306 * called either in igb_tx_hwtstamp() or by our caller when
3307 * doing software time stamping.
3310 if (unlikely(shtx->hardware)) {
3311 shtx->in_progress = 1;
3312 tx_flags |= IGB_TX_FLAGS_TSTAMP;
3315 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
3316 tx_flags |= IGB_TX_FLAGS_VLAN;
3317 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
3320 if (skb->protocol == htons(ETH_P_IP))
3321 tx_flags |= IGB_TX_FLAGS_IPV4;
3323 first = tx_ring->next_to_use;
3324 tso = skb_is_gso(skb) ? igb_tso_adv(adapter, tx_ring, skb, tx_flags,
3328 dev_kfree_skb_any(skb);
3329 return NETDEV_TX_OK;
3333 tx_flags |= IGB_TX_FLAGS_TSO;
3334 else if (igb_tx_csum_adv(adapter, tx_ring, skb, tx_flags) &&
3335 (skb->ip_summed == CHECKSUM_PARTIAL))
3336 tx_flags |= IGB_TX_FLAGS_CSUM;
3339 * count reflects descriptors mapped, if 0 then mapping error
3340 * has occured and we need to rewind the descriptor queue
3342 count = igb_tx_map_adv(adapter, tx_ring, skb, first);
3345 igb_tx_queue_adv(adapter, tx_ring, tx_flags, count,
3347 netdev->trans_start = jiffies;
3348 /* Make sure there is space in the ring for the next send. */
3349 igb_maybe_stop_tx(netdev, tx_ring, MAX_SKB_FRAGS + 4);
3351 dev_kfree_skb_any(skb);
3352 tx_ring->buffer_info[first].time_stamp = 0;
3353 tx_ring->next_to_use = first;
3356 return NETDEV_TX_OK;
3359 static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *netdev)
3361 struct igb_adapter *adapter = netdev_priv(netdev);
3362 struct igb_ring *tx_ring;
3365 r_idx = skb->queue_mapping & (IGB_ABS_MAX_TX_QUEUES - 1);
3366 tx_ring = adapter->multi_tx_table[r_idx];
3368 /* This goes back to the question of how to logically map a tx queue
3369 * to a flow. Right now, performance is impacted slightly negatively
3370 * if using multiple tx queues. If the stack breaks away from a
3371 * single qdisc implementation, we can look at this again. */
3372 return (igb_xmit_frame_ring_adv(skb, netdev, tx_ring));
3376 * igb_tx_timeout - Respond to a Tx Hang
3377 * @netdev: network interface device structure
3379 static void igb_tx_timeout(struct net_device *netdev)
3381 struct igb_adapter *adapter = netdev_priv(netdev);
3382 struct e1000_hw *hw = &adapter->hw;
3384 /* Do the reset outside of interrupt context */
3385 adapter->tx_timeout_count++;
3386 schedule_work(&adapter->reset_task);
3388 (adapter->eims_enable_mask & ~adapter->eims_other));
3391 static void igb_reset_task(struct work_struct *work)
3393 struct igb_adapter *adapter;
3394 adapter = container_of(work, struct igb_adapter, reset_task);
3396 igb_reinit_locked(adapter);
3400 * igb_get_stats - Get System Network Statistics
3401 * @netdev: network interface device structure
3403 * Returns the address of the device statistics structure.
3404 * The statistics are actually updated from the timer callback.
3406 static struct net_device_stats *igb_get_stats(struct net_device *netdev)
3408 struct igb_adapter *adapter = netdev_priv(netdev);
3410 /* only return the current stats */
3411 return &adapter->net_stats;
3415 * igb_change_mtu - Change the Maximum Transfer Unit
3416 * @netdev: network interface device structure
3417 * @new_mtu: new value for maximum frame size
3419 * Returns 0 on success, negative on failure
3421 static int igb_change_mtu(struct net_device *netdev, int new_mtu)
3423 struct igb_adapter *adapter = netdev_priv(netdev);
3424 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
3426 if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
3427 (max_frame > MAX_JUMBO_FRAME_SIZE)) {
3428 dev_err(&adapter->pdev->dev, "Invalid MTU setting\n");
3432 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
3433 dev_err(&adapter->pdev->dev, "MTU > 9216 not supported.\n");
3437 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
3440 /* igb_down has a dependency on max_frame_size */
3441 adapter->max_frame_size = max_frame;
3442 if (netif_running(netdev))
3445 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
3446 * means we reserve 2 more, this pushes us to allocate from the next
3448 * i.e. RXBUFFER_2048 --> size-4096 slab
3451 if (max_frame <= IGB_RXBUFFER_256)
3452 adapter->rx_buffer_len = IGB_RXBUFFER_256;
3453 else if (max_frame <= IGB_RXBUFFER_512)
3454 adapter->rx_buffer_len = IGB_RXBUFFER_512;
3455 else if (max_frame <= IGB_RXBUFFER_1024)
3456 adapter->rx_buffer_len = IGB_RXBUFFER_1024;
3457 else if (max_frame <= IGB_RXBUFFER_2048)
3458 adapter->rx_buffer_len = IGB_RXBUFFER_2048;
3460 #if (PAGE_SIZE / 2) > IGB_RXBUFFER_16384
3461 adapter->rx_buffer_len = IGB_RXBUFFER_16384;
3463 adapter->rx_buffer_len = PAGE_SIZE / 2;
3466 /* if sr-iov is enabled we need to force buffer size to 1K or larger */
3467 if (adapter->vfs_allocated_count &&
3468 (adapter->rx_buffer_len < IGB_RXBUFFER_1024))
3469 adapter->rx_buffer_len = IGB_RXBUFFER_1024;
3471 /* adjust allocation if LPE protects us, and we aren't using SBP */
3472 if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) ||
3473 (max_frame == MAXIMUM_ETHERNET_VLAN_SIZE))
3474 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
3476 dev_info(&adapter->pdev->dev, "changing MTU from %d to %d\n",
3477 netdev->mtu, new_mtu);
3478 netdev->mtu = new_mtu;
3480 if (netif_running(netdev))
3485 clear_bit(__IGB_RESETTING, &adapter->state);
3491 * igb_update_stats - Update the board statistics counters
3492 * @adapter: board private structure
3495 void igb_update_stats(struct igb_adapter *adapter)
3497 struct e1000_hw *hw = &adapter->hw;
3498 struct pci_dev *pdev = adapter->pdev;
3501 #define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
3504 * Prevent stats update while adapter is being reset, or if the pci
3505 * connection is down.
3507 if (adapter->link_speed == 0)
3509 if (pci_channel_offline(pdev))
3512 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
3513 adapter->stats.gprc += rd32(E1000_GPRC);
3514 adapter->stats.gorc += rd32(E1000_GORCL);
3515 rd32(E1000_GORCH); /* clear GORCL */
3516 adapter->stats.bprc += rd32(E1000_BPRC);
3517 adapter->stats.mprc += rd32(E1000_MPRC);
3518 adapter->stats.roc += rd32(E1000_ROC);
3520 adapter->stats.prc64 += rd32(E1000_PRC64);
3521 adapter->stats.prc127 += rd32(E1000_PRC127);
3522 adapter->stats.prc255 += rd32(E1000_PRC255);
3523 adapter->stats.prc511 += rd32(E1000_PRC511);
3524 adapter->stats.prc1023 += rd32(E1000_PRC1023);
3525 adapter->stats.prc1522 += rd32(E1000_PRC1522);
3526 adapter->stats.symerrs += rd32(E1000_SYMERRS);
3527 adapter->stats.sec += rd32(E1000_SEC);
3529 adapter->stats.mpc += rd32(E1000_MPC);
3530 adapter->stats.scc += rd32(E1000_SCC);
3531 adapter->stats.ecol += rd32(E1000_ECOL);
3532 adapter->stats.mcc += rd32(E1000_MCC);
3533 adapter->stats.latecol += rd32(E1000_LATECOL);
3534 adapter->stats.dc += rd32(E1000_DC);
3535 adapter->stats.rlec += rd32(E1000_RLEC);
3536 adapter->stats.xonrxc += rd32(E1000_XONRXC);
3537 adapter->stats.xontxc += rd32(E1000_XONTXC);
3538 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
3539 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
3540 adapter->stats.fcruc += rd32(E1000_FCRUC);
3541 adapter->stats.gptc += rd32(E1000_GPTC);
3542 adapter->stats.gotc += rd32(E1000_GOTCL);
3543 rd32(E1000_GOTCH); /* clear GOTCL */
3544 adapter->stats.rnbc += rd32(E1000_RNBC);
3545 adapter->stats.ruc += rd32(E1000_RUC);
3546 adapter->stats.rfc += rd32(E1000_RFC);
3547 adapter->stats.rjc += rd32(E1000_RJC);
3548 adapter->stats.tor += rd32(E1000_TORH);
3549 adapter->stats.tot += rd32(E1000_TOTH);
3550 adapter->stats.tpr += rd32(E1000_TPR);
3552 adapter->stats.ptc64 += rd32(E1000_PTC64);
3553 adapter->stats.ptc127 += rd32(E1000_PTC127);
3554 adapter->stats.ptc255 += rd32(E1000_PTC255);
3555 adapter->stats.ptc511 += rd32(E1000_PTC511);
3556 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
3557 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
3559 adapter->stats.mptc += rd32(E1000_MPTC);
3560 adapter->stats.bptc += rd32(E1000_BPTC);
3562 /* used for adaptive IFS */
3564 hw->mac.tx_packet_delta = rd32(E1000_TPT);
3565 adapter->stats.tpt += hw->mac.tx_packet_delta;
3566 hw->mac.collision_delta = rd32(E1000_COLC);
3567 adapter->stats.colc += hw->mac.collision_delta;
3569 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
3570 adapter->stats.rxerrc += rd32(E1000_RXERRC);
3571 adapter->stats.tncrs += rd32(E1000_TNCRS);
3572 adapter->stats.tsctc += rd32(E1000_TSCTC);
3573 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
3575 adapter->stats.iac += rd32(E1000_IAC);
3576 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
3577 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
3578 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
3579 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
3580 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
3581 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
3582 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
3583 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
3585 /* Fill out the OS statistics structure */
3586 adapter->net_stats.multicast = adapter->stats.mprc;
3587 adapter->net_stats.collisions = adapter->stats.colc;
3591 if (hw->mac.type != e1000_82575) {
3593 u64 rqdpc_total = 0;
3595 /* Read out drops stats per RX queue. Notice RQDPC (Receive
3596 * Queue Drop Packet Count) stats only gets incremented, if
3597 * the DROP_EN but it set (in the SRRCTL register for that
3598 * queue). If DROP_EN bit is NOT set, then the some what
3599 * equivalent count is stored in RNBC (not per queue basis).
3600 * Also note the drop count is due to lack of available
3603 for (i = 0; i < adapter->num_rx_queues; i++) {
3604 rqdpc_tmp = rd32(E1000_RQDPC(i)) & 0xFFF;
3605 adapter->rx_ring[i].rx_stats.drops += rqdpc_tmp;
3606 rqdpc_total += adapter->rx_ring[i].rx_stats.drops;
3608 adapter->net_stats.rx_fifo_errors = rqdpc_total;
3611 /* Note RNBC (Receive No Buffers Count) is an not an exact
3612 * drop count as the hardware FIFO might save the day. Thats
3613 * one of the reason for saving it in rx_fifo_errors, as its
3614 * potentially not a true drop.
3616 adapter->net_stats.rx_fifo_errors += adapter->stats.rnbc;
3618 /* RLEC on some newer hardware can be incorrect so build
3619 * our own version based on RUC and ROC */
3620 adapter->net_stats.rx_errors = adapter->stats.rxerrc +
3621 adapter->stats.crcerrs + adapter->stats.algnerrc +
3622 adapter->stats.ruc + adapter->stats.roc +
3623 adapter->stats.cexterr;
3624 adapter->net_stats.rx_length_errors = adapter->stats.ruc +
3626 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
3627 adapter->net_stats.rx_frame_errors = adapter->stats.algnerrc;
3628 adapter->net_stats.rx_missed_errors = adapter->stats.mpc;
3631 adapter->net_stats.tx_errors = adapter->stats.ecol +
3632 adapter->stats.latecol;
3633 adapter->net_stats.tx_aborted_errors = adapter->stats.ecol;
3634 adapter->net_stats.tx_window_errors = adapter->stats.latecol;
3635 adapter->net_stats.tx_carrier_errors = adapter->stats.tncrs;
3637 /* Tx Dropped needs to be maintained elsewhere */
3640 if (hw->phy.media_type == e1000_media_type_copper) {
3641 if ((adapter->link_speed == SPEED_1000) &&
3642 (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
3643 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
3644 adapter->phy_stats.idle_errors += phy_tmp;
3648 /* Management Stats */
3649 adapter->stats.mgptc += rd32(E1000_MGTPTC);
3650 adapter->stats.mgprc += rd32(E1000_MGTPRC);
3651 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
3654 static irqreturn_t igb_msix_other(int irq, void *data)
3656 struct net_device *netdev = data;
3657 struct igb_adapter *adapter = netdev_priv(netdev);
3658 struct e1000_hw *hw = &adapter->hw;
3659 u32 icr = rd32(E1000_ICR);
3661 /* reading ICR causes bit 31 of EICR to be cleared */
3663 if(icr & E1000_ICR_DOUTSYNC) {
3664 /* HW is reporting DMA is out of sync */
3665 adapter->stats.doosync++;
3668 /* Check for a mailbox event */
3669 if (icr & E1000_ICR_VMMB)
3670 igb_msg_task(adapter);
3672 if (icr & E1000_ICR_LSC) {
3673 hw->mac.get_link_status = 1;
3674 /* guard against interrupt when we're going down */
3675 if (!test_bit(__IGB_DOWN, &adapter->state))
3676 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3679 wr32(E1000_IMS, E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_VMMB);
3680 wr32(E1000_EIMS, adapter->eims_other);
3685 static irqreturn_t igb_msix_tx(int irq, void *data)
3687 struct igb_ring *tx_ring = data;
3688 struct igb_adapter *adapter = tx_ring->adapter;
3689 struct e1000_hw *hw = &adapter->hw;
3691 #ifdef CONFIG_IGB_DCA
3692 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
3693 igb_update_tx_dca(tx_ring);
3696 tx_ring->total_bytes = 0;
3697 tx_ring->total_packets = 0;
3699 /* auto mask will automatically reenable the interrupt when we write
3701 if (!igb_clean_tx_irq(tx_ring))
3702 /* Ring was not completely cleaned, so fire another interrupt */
3703 wr32(E1000_EICS, tx_ring->eims_value);
3705 wr32(E1000_EIMS, tx_ring->eims_value);
3710 static void igb_write_itr(struct igb_ring *ring)
3712 struct e1000_hw *hw = &ring->adapter->hw;
3713 if ((ring->adapter->itr_setting & 3) && ring->set_itr) {
3714 switch (hw->mac.type) {
3716 wr32(ring->itr_register, ring->itr_val |
3720 wr32(ring->itr_register, ring->itr_val |
3721 (ring->itr_val << 16));
3728 static irqreturn_t igb_msix_rx(int irq, void *data)
3730 struct igb_ring *rx_ring = data;
3732 /* Write the ITR value calculated at the end of the
3733 * previous interrupt.
3736 igb_write_itr(rx_ring);
3738 if (napi_schedule_prep(&rx_ring->napi))
3739 __napi_schedule(&rx_ring->napi);
3741 #ifdef CONFIG_IGB_DCA
3742 if (rx_ring->adapter->flags & IGB_FLAG_DCA_ENABLED)
3743 igb_update_rx_dca(rx_ring);
3748 #ifdef CONFIG_IGB_DCA
3749 static void igb_update_rx_dca(struct igb_ring *rx_ring)
3752 struct igb_adapter *adapter = rx_ring->adapter;
3753 struct e1000_hw *hw = &adapter->hw;
3754 int cpu = get_cpu();
3755 int q = rx_ring->reg_idx;
3757 if (rx_ring->cpu != cpu) {
3758 dca_rxctrl = rd32(E1000_DCA_RXCTRL(q));
3759 if (hw->mac.type == e1000_82576) {
3760 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK_82576;
3761 dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) <<
3762 E1000_DCA_RXCTRL_CPUID_SHIFT;
3764 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK;
3765 dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
3767 dca_rxctrl |= E1000_DCA_RXCTRL_DESC_DCA_EN;
3768 dca_rxctrl |= E1000_DCA_RXCTRL_HEAD_DCA_EN;
3769 dca_rxctrl |= E1000_DCA_RXCTRL_DATA_DCA_EN;
3770 wr32(E1000_DCA_RXCTRL(q), dca_rxctrl);
3776 static void igb_update_tx_dca(struct igb_ring *tx_ring)
3779 struct igb_adapter *adapter = tx_ring->adapter;
3780 struct e1000_hw *hw = &adapter->hw;
3781 int cpu = get_cpu();
3782 int q = tx_ring->reg_idx;
3784 if (tx_ring->cpu != cpu) {
3785 dca_txctrl = rd32(E1000_DCA_TXCTRL(q));
3786 if (hw->mac.type == e1000_82576) {
3787 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK_82576;
3788 dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) <<
3789 E1000_DCA_TXCTRL_CPUID_SHIFT;
3791 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK;
3792 dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
3794 dca_txctrl |= E1000_DCA_TXCTRL_DESC_DCA_EN;
3795 wr32(E1000_DCA_TXCTRL(q), dca_txctrl);
3801 static void igb_setup_dca(struct igb_adapter *adapter)
3803 struct e1000_hw *hw = &adapter->hw;
3806 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
3809 /* Always use CB2 mode, difference is masked in the CB driver. */
3810 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
3812 for (i = 0; i < adapter->num_tx_queues; i++) {
3813 adapter->tx_ring[i].cpu = -1;
3814 igb_update_tx_dca(&adapter->tx_ring[i]);
3816 for (i = 0; i < adapter->num_rx_queues; i++) {
3817 adapter->rx_ring[i].cpu = -1;
3818 igb_update_rx_dca(&adapter->rx_ring[i]);
3822 static int __igb_notify_dca(struct device *dev, void *data)
3824 struct net_device *netdev = dev_get_drvdata(dev);
3825 struct igb_adapter *adapter = netdev_priv(netdev);
3826 struct e1000_hw *hw = &adapter->hw;
3827 unsigned long event = *(unsigned long *)data;
3830 case DCA_PROVIDER_ADD:
3831 /* if already enabled, don't do it again */
3832 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
3834 /* Always use CB2 mode, difference is masked
3835 * in the CB driver. */
3836 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
3837 if (dca_add_requester(dev) == 0) {
3838 adapter->flags |= IGB_FLAG_DCA_ENABLED;
3839 dev_info(&adapter->pdev->dev, "DCA enabled\n");
3840 igb_setup_dca(adapter);
3843 /* Fall Through since DCA is disabled. */
3844 case DCA_PROVIDER_REMOVE:
3845 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
3846 /* without this a class_device is left
3847 * hanging around in the sysfs model */
3848 dca_remove_requester(dev);
3849 dev_info(&adapter->pdev->dev, "DCA disabled\n");
3850 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
3851 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
3859 static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
3864 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
3867 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
3869 #endif /* CONFIG_IGB_DCA */
3871 static void igb_ping_all_vfs(struct igb_adapter *adapter)
3873 struct e1000_hw *hw = &adapter->hw;
3877 for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
3878 ping = E1000_PF_CONTROL_MSG;
3879 if (adapter->vf_data[i].clear_to_send)
3880 ping |= E1000_VT_MSGTYPE_CTS;
3881 igb_write_mbx(hw, &ping, 1, i);
3885 static int igb_set_vf_multicasts(struct igb_adapter *adapter,
3886 u32 *msgbuf, u32 vf)
3888 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
3889 u16 *hash_list = (u16 *)&msgbuf[1];
3890 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
3893 /* only up to 30 hash values supported */
3897 /* salt away the number of multi cast addresses assigned
3898 * to this VF for later use to restore when the PF multi cast
3901 vf_data->num_vf_mc_hashes = n;
3903 /* VFs are limited to using the MTA hash table for their multicast
3905 for (i = 0; i < n; i++)
3906 vf_data->vf_mc_hashes[i] = hash_list[i];;
3908 /* Flush and reset the mta with the new values */
3909 igb_set_multi(adapter->netdev);
3914 static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
3916 struct e1000_hw *hw = &adapter->hw;
3917 struct vf_data_storage *vf_data;
3920 for (i = 0; i < adapter->vfs_allocated_count; i++) {
3921 vf_data = &adapter->vf_data[i];
3922 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
3923 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
3927 static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
3929 struct e1000_hw *hw = &adapter->hw;
3930 u32 pool_mask, reg, vid;
3933 pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
3935 /* Find the vlan filter for this id */
3936 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
3937 reg = rd32(E1000_VLVF(i));
3939 /* remove the vf from the pool */
3942 /* if pool is empty then remove entry from vfta */
3943 if (!(reg & E1000_VLVF_POOLSEL_MASK) &&
3944 (reg & E1000_VLVF_VLANID_ENABLE)) {
3946 vid = reg & E1000_VLVF_VLANID_MASK;
3947 igb_vfta_set(hw, vid, false);
3950 wr32(E1000_VLVF(i), reg);
3954 static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf)
3956 struct e1000_hw *hw = &adapter->hw;
3959 /* It is an error to call this function when VFs are not enabled */
3960 if (!adapter->vfs_allocated_count)
3963 /* Find the vlan filter for this id */
3964 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
3965 reg = rd32(E1000_VLVF(i));
3966 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
3967 vid == (reg & E1000_VLVF_VLANID_MASK))
3972 if (i == E1000_VLVF_ARRAY_SIZE) {
3973 /* Did not find a matching VLAN ID entry that was
3974 * enabled. Search for a free filter entry, i.e.
3975 * one without the enable bit set
3977 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
3978 reg = rd32(E1000_VLVF(i));
3979 if (!(reg & E1000_VLVF_VLANID_ENABLE))
3983 if (i < E1000_VLVF_ARRAY_SIZE) {
3984 /* Found an enabled/available entry */
3985 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
3987 /* if !enabled we need to set this up in vfta */
3988 if (!(reg & E1000_VLVF_VLANID_ENABLE)) {
3989 /* add VID to filter table, if bit already set
3990 * PF must have added it outside of table */
3991 if (igb_vfta_set(hw, vid, true))
3992 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT +
3993 adapter->vfs_allocated_count);
3994 reg |= E1000_VLVF_VLANID_ENABLE;
3996 reg &= ~E1000_VLVF_VLANID_MASK;
3999 wr32(E1000_VLVF(i), reg);
4003 if (i < E1000_VLVF_ARRAY_SIZE) {
4004 /* remove vf from the pool */
4005 reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf));
4006 /* if pool is empty then remove entry from vfta */
4007 if (!(reg & E1000_VLVF_POOLSEL_MASK)) {
4009 igb_vfta_set(hw, vid, false);
4011 wr32(E1000_VLVF(i), reg);
4018 static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
4020 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
4021 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
4023 return igb_vlvf_set(adapter, vid, add, vf);
4026 static inline void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
4028 struct e1000_hw *hw = &adapter->hw;
4030 /* disable mailbox functionality for vf */
4031 adapter->vf_data[vf].clear_to_send = false;
4033 /* reset offloads to defaults */
4034 igb_set_vmolr(hw, vf);
4036 /* reset vlans for device */
4037 igb_clear_vf_vfta(adapter, vf);
4039 /* reset multicast table array for vf */
4040 adapter->vf_data[vf].num_vf_mc_hashes = 0;
4042 /* Flush and reset the mta with the new values */
4043 igb_set_multi(adapter->netdev);
4046 static inline void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
4048 struct e1000_hw *hw = &adapter->hw;
4049 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
4051 u8 *addr = (u8 *)(&msgbuf[1]);
4053 /* process all the same items cleared in a function level reset */
4054 igb_vf_reset_event(adapter, vf);
4056 /* set vf mac address */
4057 igb_rar_set(hw, vf_mac, vf + 1);
4058 igb_set_rah_pool(hw, vf, vf + 1);
4060 /* enable transmit and receive for vf */
4061 reg = rd32(E1000_VFTE);
4062 wr32(E1000_VFTE, reg | (1 << vf));
4063 reg = rd32(E1000_VFRE);
4064 wr32(E1000_VFRE, reg | (1 << vf));
4066 /* enable mailbox functionality for vf */
4067 adapter->vf_data[vf].clear_to_send = true;
4069 /* reply to reset with ack and vf mac address */
4070 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
4071 memcpy(addr, vf_mac, 6);
4072 igb_write_mbx(hw, msgbuf, 3, vf);
4075 static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
4077 unsigned char *addr = (char *)&msg[1];
4080 if (is_valid_ether_addr(addr))
4081 err = igb_set_vf_mac(adapter, vf, addr);
4087 static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
4089 struct e1000_hw *hw = &adapter->hw;
4090 u32 msg = E1000_VT_MSGTYPE_NACK;
4092 /* if device isn't clear to send it shouldn't be reading either */
4093 if (!adapter->vf_data[vf].clear_to_send)
4094 igb_write_mbx(hw, &msg, 1, vf);
4098 static void igb_msg_task(struct igb_adapter *adapter)
4100 struct e1000_hw *hw = &adapter->hw;
4103 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
4104 /* process any reset requests */
4105 if (!igb_check_for_rst(hw, vf)) {
4106 adapter->vf_data[vf].clear_to_send = false;
4107 igb_vf_reset_event(adapter, vf);
4110 /* process any messages pending */
4111 if (!igb_check_for_msg(hw, vf))
4112 igb_rcv_msg_from_vf(adapter, vf);
4114 /* process any acks */
4115 if (!igb_check_for_ack(hw, vf))
4116 igb_rcv_ack_from_vf(adapter, vf);
4121 static int igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
4123 u32 mbx_size = E1000_VFMAILBOX_SIZE;
4124 u32 msgbuf[mbx_size];
4125 struct e1000_hw *hw = &adapter->hw;
4128 retval = igb_read_mbx(hw, msgbuf, mbx_size, vf);
4131 dev_err(&adapter->pdev->dev,
4132 "Error receiving message from VF\n");
4134 /* this is a message we already processed, do nothing */
4135 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
4139 * until the vf completes a reset it should not be
4140 * allowed to start any configuration.
4143 if (msgbuf[0] == E1000_VF_RESET) {
4144 igb_vf_reset_msg(adapter, vf);
4149 if (!adapter->vf_data[vf].clear_to_send) {
4150 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
4151 igb_write_mbx(hw, msgbuf, 1, vf);
4155 switch ((msgbuf[0] & 0xFFFF)) {
4156 case E1000_VF_SET_MAC_ADDR:
4157 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
4159 case E1000_VF_SET_MULTICAST:
4160 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
4162 case E1000_VF_SET_LPE:
4163 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
4165 case E1000_VF_SET_VLAN:
4166 retval = igb_set_vf_vlan(adapter, msgbuf, vf);
4169 dev_err(&adapter->pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
4174 /* notify the VF of the results of what it sent us */
4176 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
4178 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
4180 msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
4182 igb_write_mbx(hw, msgbuf, 1, vf);
4188 * igb_intr_msi - Interrupt Handler
4189 * @irq: interrupt number
4190 * @data: pointer to a network interface device structure
4192 static irqreturn_t igb_intr_msi(int irq, void *data)
4194 struct net_device *netdev = data;
4195 struct igb_adapter *adapter = netdev_priv(netdev);
4196 struct e1000_hw *hw = &adapter->hw;
4197 /* read ICR disables interrupts using IAM */
4198 u32 icr = rd32(E1000_ICR);
4200 igb_write_itr(adapter->rx_ring);
4202 if(icr & E1000_ICR_DOUTSYNC) {
4203 /* HW is reporting DMA is out of sync */
4204 adapter->stats.doosync++;
4207 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
4208 hw->mac.get_link_status = 1;
4209 if (!test_bit(__IGB_DOWN, &adapter->state))
4210 mod_timer(&adapter->watchdog_timer, jiffies + 1);
4213 napi_schedule(&adapter->rx_ring[0].napi);
4219 * igb_intr - Legacy Interrupt Handler
4220 * @irq: interrupt number
4221 * @data: pointer to a network interface device structure
4223 static irqreturn_t igb_intr(int irq, void *data)
4225 struct net_device *netdev = data;
4226 struct igb_adapter *adapter = netdev_priv(netdev);
4227 struct e1000_hw *hw = &adapter->hw;
4228 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
4229 * need for the IMC write */
4230 u32 icr = rd32(E1000_ICR);
4232 return IRQ_NONE; /* Not our interrupt */
4234 igb_write_itr(adapter->rx_ring);
4236 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
4237 * not set, then the adapter didn't send an interrupt */
4238 if (!(icr & E1000_ICR_INT_ASSERTED))
4241 if(icr & E1000_ICR_DOUTSYNC) {
4242 /* HW is reporting DMA is out of sync */
4243 adapter->stats.doosync++;
4246 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
4247 hw->mac.get_link_status = 1;
4248 /* guard against interrupt when we're going down */
4249 if (!test_bit(__IGB_DOWN, &adapter->state))
4250 mod_timer(&adapter->watchdog_timer, jiffies + 1);
4253 napi_schedule(&adapter->rx_ring[0].napi);
4258 static inline void igb_rx_irq_enable(struct igb_ring *rx_ring)
4260 struct igb_adapter *adapter = rx_ring->adapter;
4261 struct e1000_hw *hw = &adapter->hw;
4263 if (adapter->itr_setting & 3) {
4264 if (adapter->num_rx_queues == 1)
4265 igb_set_itr(adapter);
4267 igb_update_ring_itr(rx_ring);
4270 if (!test_bit(__IGB_DOWN, &adapter->state)) {
4271 if (adapter->msix_entries)
4272 wr32(E1000_EIMS, rx_ring->eims_value);
4274 igb_irq_enable(adapter);
4279 * igb_poll - NAPI Rx polling callback
4280 * @napi: napi polling structure
4281 * @budget: count of how many packets we should handle
4283 static int igb_poll(struct napi_struct *napi, int budget)
4285 struct igb_ring *rx_ring = container_of(napi, struct igb_ring, napi);
4288 #ifdef CONFIG_IGB_DCA
4289 if (rx_ring->adapter->flags & IGB_FLAG_DCA_ENABLED)
4290 igb_update_rx_dca(rx_ring);
4292 igb_clean_rx_irq_adv(rx_ring, &work_done, budget);
4294 if (rx_ring->buddy) {
4295 #ifdef CONFIG_IGB_DCA
4296 if (rx_ring->adapter->flags & IGB_FLAG_DCA_ENABLED)
4297 igb_update_tx_dca(rx_ring->buddy);
4299 if (!igb_clean_tx_irq(rx_ring->buddy))
4303 /* If not enough Rx work done, exit the polling mode */
4304 if (work_done < budget) {
4305 napi_complete(napi);
4306 igb_rx_irq_enable(rx_ring);
4313 * igb_hwtstamp - utility function which checks for TX time stamp
4314 * @adapter: board private structure
4315 * @skb: packet that was just sent
4317 * If we were asked to do hardware stamping and such a time stamp is
4318 * available, then it must have been for this skb here because we only
4319 * allow only one such packet into the queue.
4321 static void igb_tx_hwtstamp(struct igb_adapter *adapter, struct sk_buff *skb)
4323 union skb_shared_tx *shtx = skb_tx(skb);
4324 struct e1000_hw *hw = &adapter->hw;
4326 if (unlikely(shtx->hardware)) {
4327 u32 valid = rd32(E1000_TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID;
4329 u64 regval = rd32(E1000_TXSTMPL);
4331 struct skb_shared_hwtstamps shhwtstamps;
4333 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
4334 regval |= (u64)rd32(E1000_TXSTMPH) << 32;
4335 ns = timecounter_cyc2time(&adapter->clock,
4337 timecompare_update(&adapter->compare, ns);
4338 shhwtstamps.hwtstamp = ns_to_ktime(ns);
4339 shhwtstamps.syststamp =
4340 timecompare_transform(&adapter->compare, ns);
4341 skb_tstamp_tx(skb, &shhwtstamps);
4347 * igb_clean_tx_irq - Reclaim resources after transmit completes
4348 * @adapter: board private structure
4349 * returns true if ring is completely cleaned
4351 static bool igb_clean_tx_irq(struct igb_ring *tx_ring)
4353 struct igb_adapter *adapter = tx_ring->adapter;
4354 struct net_device *netdev = adapter->netdev;
4355 struct e1000_hw *hw = &adapter->hw;
4356 struct igb_buffer *buffer_info;
4357 struct sk_buff *skb;
4358 union e1000_adv_tx_desc *tx_desc, *eop_desc;
4359 unsigned int total_bytes = 0, total_packets = 0;
4360 unsigned int i, eop, count = 0;
4361 bool cleaned = false;
4363 i = tx_ring->next_to_clean;
4364 eop = tx_ring->buffer_info[i].next_to_watch;
4365 eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
4367 while ((eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)) &&
4368 (count < tx_ring->count)) {
4369 for (cleaned = false; !cleaned; count++) {
4370 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
4371 buffer_info = &tx_ring->buffer_info[i];
4372 cleaned = (i == eop);
4373 skb = buffer_info->skb;
4376 unsigned int segs, bytecount;
4377 /* gso_segs is currently only valid for tcp */
4378 segs = skb_shinfo(skb)->gso_segs ?: 1;
4379 /* multiply data chunks by size of headers */
4380 bytecount = ((segs - 1) * skb_headlen(skb)) +
4382 total_packets += segs;
4383 total_bytes += bytecount;
4385 igb_tx_hwtstamp(adapter, skb);
4388 igb_unmap_and_free_tx_resource(adapter, buffer_info);
4389 tx_desc->wb.status = 0;
4392 if (i == tx_ring->count)
4395 eop = tx_ring->buffer_info[i].next_to_watch;
4396 eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
4399 tx_ring->next_to_clean = i;
4401 if (unlikely(count &&
4402 netif_carrier_ok(netdev) &&
4403 igb_desc_unused(tx_ring) >= IGB_TX_QUEUE_WAKE)) {
4404 /* Make sure that anybody stopping the queue after this
4405 * sees the new next_to_clean.
4408 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
4409 !(test_bit(__IGB_DOWN, &adapter->state))) {
4410 netif_wake_subqueue(netdev, tx_ring->queue_index);
4411 ++adapter->restart_queue;
4415 if (tx_ring->detect_tx_hung) {
4416 /* Detect a transmit hang in hardware, this serializes the
4417 * check with the clearing of time_stamp and movement of i */
4418 tx_ring->detect_tx_hung = false;
4419 if (tx_ring->buffer_info[i].time_stamp &&
4420 time_after(jiffies, tx_ring->buffer_info[i].time_stamp +
4421 (adapter->tx_timeout_factor * HZ))
4422 && !(rd32(E1000_STATUS) &
4423 E1000_STATUS_TXOFF)) {
4425 /* detected Tx unit hang */
4426 dev_err(&adapter->pdev->dev,
4427 "Detected Tx Unit Hang\n"
4431 " next_to_use <%x>\n"
4432 " next_to_clean <%x>\n"
4433 "buffer_info[next_to_clean]\n"
4434 " time_stamp <%lx>\n"
4435 " next_to_watch <%x>\n"
4437 " desc.status <%x>\n",
4438 tx_ring->queue_index,
4439 readl(adapter->hw.hw_addr + tx_ring->head),
4440 readl(adapter->hw.hw_addr + tx_ring->tail),
4441 tx_ring->next_to_use,
4442 tx_ring->next_to_clean,
4443 tx_ring->buffer_info[i].time_stamp,
4446 eop_desc->wb.status);
4447 netif_stop_subqueue(netdev, tx_ring->queue_index);
4450 tx_ring->total_bytes += total_bytes;
4451 tx_ring->total_packets += total_packets;
4452 tx_ring->tx_stats.bytes += total_bytes;
4453 tx_ring->tx_stats.packets += total_packets;
4454 adapter->net_stats.tx_bytes += total_bytes;
4455 adapter->net_stats.tx_packets += total_packets;
4456 return (count < tx_ring->count);
4460 * igb_receive_skb - helper function to handle rx indications
4461 * @ring: pointer to receive ring receving this packet
4462 * @status: descriptor status field as written by hardware
4463 * @rx_desc: receive descriptor containing vlan and type information.
4464 * @skb: pointer to sk_buff to be indicated to stack
4466 static void igb_receive_skb(struct igb_ring *ring, u8 status,
4467 union e1000_adv_rx_desc * rx_desc,
4468 struct sk_buff *skb)
4470 struct igb_adapter * adapter = ring->adapter;
4471 bool vlan_extracted = (adapter->vlgrp && (status & E1000_RXD_STAT_VP));
4473 skb_record_rx_queue(skb, ring->queue_index);
4475 vlan_gro_receive(&ring->napi, adapter->vlgrp,
4476 le16_to_cpu(rx_desc->wb.upper.vlan),
4479 napi_gro_receive(&ring->napi, skb);
4482 static inline void igb_rx_checksum_adv(struct igb_adapter *adapter,
4483 u32 status_err, struct sk_buff *skb)
4485 skb->ip_summed = CHECKSUM_NONE;
4487 /* Ignore Checksum bit is set or checksum is disabled through ethtool */
4488 if ((status_err & E1000_RXD_STAT_IXSM) ||
4489 (adapter->flags & IGB_FLAG_RX_CSUM_DISABLED))
4491 /* TCP/UDP checksum error bit is set */
4493 (E1000_RXDEXT_STATERR_TCPE | E1000_RXDEXT_STATERR_IPE)) {
4495 * work around errata with sctp packets where the TCPE aka
4496 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
4497 * packets, (aka let the stack check the crc32c)
4499 if (!((adapter->hw.mac.type == e1000_82576) &&
4501 adapter->hw_csum_err++;
4502 /* let the stack verify checksum errors */
4505 /* It must be a TCP or UDP packet with a valid checksum */
4506 if (status_err & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))
4507 skb->ip_summed = CHECKSUM_UNNECESSARY;
4509 dev_dbg(&adapter->pdev->dev, "cksum success: bits %08X\n", status_err);
4510 adapter->hw_csum_good++;
4513 static bool igb_clean_rx_irq_adv(struct igb_ring *rx_ring,
4514 int *work_done, int budget)
4516 struct igb_adapter *adapter = rx_ring->adapter;
4517 struct net_device *netdev = adapter->netdev;
4518 struct e1000_hw *hw = &adapter->hw;
4519 struct pci_dev *pdev = adapter->pdev;
4520 union e1000_adv_rx_desc *rx_desc , *next_rxd;
4521 struct igb_buffer *buffer_info , *next_buffer;
4522 struct sk_buff *skb;
4523 bool cleaned = false;
4524 int cleaned_count = 0;
4525 unsigned int total_bytes = 0, total_packets = 0;
4527 u32 length, hlen, staterr;
4529 i = rx_ring->next_to_clean;
4530 buffer_info = &rx_ring->buffer_info[i];
4531 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
4532 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
4534 while (staterr & E1000_RXD_STAT_DD) {
4535 if (*work_done >= budget)
4539 skb = buffer_info->skb;
4540 prefetch(skb->data - NET_IP_ALIGN);
4541 buffer_info->skb = NULL;
4544 if (i == rx_ring->count)
4546 next_rxd = E1000_RX_DESC_ADV(*rx_ring, i);
4548 next_buffer = &rx_ring->buffer_info[i];
4550 length = le16_to_cpu(rx_desc->wb.upper.length);
4554 if (!adapter->rx_ps_hdr_size) {
4555 pci_unmap_single(pdev, buffer_info->dma,
4556 adapter->rx_buffer_len +
4558 PCI_DMA_FROMDEVICE);
4559 skb_put(skb, length);
4563 /* HW will not DMA in data larger than the given buffer, even
4564 * if it parses the (NFS, of course) header to be larger. In
4565 * that case, it fills the header buffer and spills the rest
4568 hlen = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hdr_info) &
4569 E1000_RXDADV_HDRBUFLEN_MASK) >> E1000_RXDADV_HDRBUFLEN_SHIFT;
4570 if (hlen > adapter->rx_ps_hdr_size)
4571 hlen = adapter->rx_ps_hdr_size;
4573 if (!skb_shinfo(skb)->nr_frags) {
4574 pci_unmap_single(pdev, buffer_info->dma,
4575 adapter->rx_ps_hdr_size + NET_IP_ALIGN,
4576 PCI_DMA_FROMDEVICE);
4581 pci_unmap_page(pdev, buffer_info->page_dma,
4582 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
4583 buffer_info->page_dma = 0;
4585 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags++,
4587 buffer_info->page_offset,
4590 if ((adapter->rx_buffer_len > (PAGE_SIZE / 2)) ||
4591 (page_count(buffer_info->page) != 1))
4592 buffer_info->page = NULL;
4594 get_page(buffer_info->page);
4597 skb->data_len += length;
4599 skb->truesize += length;
4602 if (!(staterr & E1000_RXD_STAT_EOP)) {
4603 buffer_info->skb = next_buffer->skb;
4604 buffer_info->dma = next_buffer->dma;
4605 next_buffer->skb = skb;
4606 next_buffer->dma = 0;
4611 * If this bit is set, then the RX registers contain
4612 * the time stamp. No other packet will be time
4613 * stamped until we read these registers, so read the
4614 * registers to make them available again. Because
4615 * only one packet can be time stamped at a time, we
4616 * know that the register values must belong to this
4617 * one here and therefore we don't need to compare
4618 * any of the additional attributes stored for it.
4620 * If nothing went wrong, then it should have a
4621 * skb_shared_tx that we can turn into a
4622 * skb_shared_hwtstamps.
4624 * TODO: can time stamping be triggered (thus locking
4625 * the registers) without the packet reaching this point
4626 * here? In that case RX time stamping would get stuck.
4628 * TODO: in "time stamp all packets" mode this bit is
4629 * not set. Need a global flag for this mode and then
4630 * always read the registers. Cannot be done without
4633 if (unlikely(staterr & E1000_RXD_STAT_TS)) {
4636 struct skb_shared_hwtstamps *shhwtstamps =
4639 WARN(!(rd32(E1000_TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID),
4640 "igb: no RX time stamp available for time stamped packet");
4641 regval = rd32(E1000_RXSTMPL);
4642 regval |= (u64)rd32(E1000_RXSTMPH) << 32;
4643 ns = timecounter_cyc2time(&adapter->clock, regval);
4644 timecompare_update(&adapter->compare, ns);
4645 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
4646 shhwtstamps->hwtstamp = ns_to_ktime(ns);
4647 shhwtstamps->syststamp =
4648 timecompare_transform(&adapter->compare, ns);
4651 if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) {
4652 dev_kfree_skb_irq(skb);
4656 total_bytes += skb->len;
4659 igb_rx_checksum_adv(adapter, staterr, skb);
4661 skb->protocol = eth_type_trans(skb, netdev);
4663 igb_receive_skb(rx_ring, staterr, rx_desc, skb);
4666 rx_desc->wb.upper.status_error = 0;
4668 /* return some buffers to hardware, one at a time is too slow */
4669 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
4670 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
4674 /* use prefetched values */
4676 buffer_info = next_buffer;
4677 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
4680 rx_ring->next_to_clean = i;
4681 cleaned_count = igb_desc_unused(rx_ring);
4684 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
4686 rx_ring->total_packets += total_packets;
4687 rx_ring->total_bytes += total_bytes;
4688 rx_ring->rx_stats.packets += total_packets;
4689 rx_ring->rx_stats.bytes += total_bytes;
4690 adapter->net_stats.rx_bytes += total_bytes;
4691 adapter->net_stats.rx_packets += total_packets;
4696 * igb_alloc_rx_buffers_adv - Replace used receive buffers; packet split
4697 * @adapter: address of board private structure
4699 static void igb_alloc_rx_buffers_adv(struct igb_ring *rx_ring,
4702 struct igb_adapter *adapter = rx_ring->adapter;
4703 struct net_device *netdev = adapter->netdev;
4704 struct pci_dev *pdev = adapter->pdev;
4705 union e1000_adv_rx_desc *rx_desc;
4706 struct igb_buffer *buffer_info;
4707 struct sk_buff *skb;
4711 i = rx_ring->next_to_use;
4712 buffer_info = &rx_ring->buffer_info[i];
4714 if (adapter->rx_ps_hdr_size)
4715 bufsz = adapter->rx_ps_hdr_size;
4717 bufsz = adapter->rx_buffer_len;
4718 bufsz += NET_IP_ALIGN;
4720 while (cleaned_count--) {
4721 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
4723 if (adapter->rx_ps_hdr_size && !buffer_info->page_dma) {
4724 if (!buffer_info->page) {
4725 buffer_info->page = alloc_page(GFP_ATOMIC);
4726 if (!buffer_info->page) {
4727 adapter->alloc_rx_buff_failed++;
4730 buffer_info->page_offset = 0;
4732 buffer_info->page_offset ^= PAGE_SIZE / 2;
4734 buffer_info->page_dma =
4735 pci_map_page(pdev, buffer_info->page,
4736 buffer_info->page_offset,
4738 PCI_DMA_FROMDEVICE);
4741 if (!buffer_info->skb) {
4742 skb = netdev_alloc_skb(netdev, bufsz);
4744 adapter->alloc_rx_buff_failed++;
4748 /* Make buffer alignment 2 beyond a 16 byte boundary
4749 * this will result in a 16 byte aligned IP header after
4750 * the 14 byte MAC header is removed
4752 skb_reserve(skb, NET_IP_ALIGN);
4754 buffer_info->skb = skb;
4755 buffer_info->dma = pci_map_single(pdev, skb->data,
4757 PCI_DMA_FROMDEVICE);
4759 /* Refresh the desc even if buffer_addrs didn't change because
4760 * each write-back erases this info. */
4761 if (adapter->rx_ps_hdr_size) {
4762 rx_desc->read.pkt_addr =
4763 cpu_to_le64(buffer_info->page_dma);
4764 rx_desc->read.hdr_addr = cpu_to_le64(buffer_info->dma);
4766 rx_desc->read.pkt_addr =
4767 cpu_to_le64(buffer_info->dma);
4768 rx_desc->read.hdr_addr = 0;
4772 if (i == rx_ring->count)
4774 buffer_info = &rx_ring->buffer_info[i];
4778 if (rx_ring->next_to_use != i) {
4779 rx_ring->next_to_use = i;
4781 i = (rx_ring->count - 1);
4785 /* Force memory writes to complete before letting h/w
4786 * know there are new descriptors to fetch. (Only
4787 * applicable for weak-ordered memory model archs,
4788 * such as IA-64). */
4790 writel(i, adapter->hw.hw_addr + rx_ring->tail);
4800 static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4802 struct igb_adapter *adapter = netdev_priv(netdev);
4803 struct mii_ioctl_data *data = if_mii(ifr);
4805 if (adapter->hw.phy.media_type != e1000_media_type_copper)
4810 data->phy_id = adapter->hw.phy.addr;
4813 if (!capable(CAP_NET_ADMIN))
4815 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
4827 * igb_hwtstamp_ioctl - control hardware time stamping
4832 * Outgoing time stamping can be enabled and disabled. Play nice and
4833 * disable it when requested, although it shouldn't case any overhead
4834 * when no packet needs it. At most one packet in the queue may be
4835 * marked for time stamping, otherwise it would be impossible to tell
4836 * for sure to which packet the hardware time stamp belongs.
4838 * Incoming time stamping has to be configured via the hardware
4839 * filters. Not all combinations are supported, in particular event
4840 * type has to be specified. Matching the kind of event packet is
4841 * not supported, with the exception of "all V2 events regardless of
4845 static int igb_hwtstamp_ioctl(struct net_device *netdev,
4846 struct ifreq *ifr, int cmd)
4848 struct igb_adapter *adapter = netdev_priv(netdev);
4849 struct e1000_hw *hw = &adapter->hw;
4850 struct hwtstamp_config config;
4851 u32 tsync_tx_ctl_bit = E1000_TSYNCTXCTL_ENABLED;
4852 u32 tsync_rx_ctl_bit = E1000_TSYNCRXCTL_ENABLED;
4853 u32 tsync_rx_ctl_type = 0;
4854 u32 tsync_rx_cfg = 0;
4857 short port = 319; /* PTP */
4860 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
4863 /* reserved for future extensions */
4867 switch (config.tx_type) {
4868 case HWTSTAMP_TX_OFF:
4869 tsync_tx_ctl_bit = 0;
4871 case HWTSTAMP_TX_ON:
4872 tsync_tx_ctl_bit = E1000_TSYNCTXCTL_ENABLED;
4878 switch (config.rx_filter) {
4879 case HWTSTAMP_FILTER_NONE:
4880 tsync_rx_ctl_bit = 0;
4882 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
4883 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
4884 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
4885 case HWTSTAMP_FILTER_ALL:
4887 * register TSYNCRXCFG must be set, therefore it is not
4888 * possible to time stamp both Sync and Delay_Req messages
4889 * => fall back to time stamping all packets
4891 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_ALL;
4892 config.rx_filter = HWTSTAMP_FILTER_ALL;
4894 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
4895 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L4_V1;
4896 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE;
4899 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
4900 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L4_V1;
4901 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE;
4904 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
4905 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
4906 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
4907 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE;
4910 config.rx_filter = HWTSTAMP_FILTER_SOME;
4912 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
4913 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
4914 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
4915 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE;
4918 config.rx_filter = HWTSTAMP_FILTER_SOME;
4920 case HWTSTAMP_FILTER_PTP_V2_EVENT:
4921 case HWTSTAMP_FILTER_PTP_V2_SYNC:
4922 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
4923 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_EVENT_V2;
4924 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
4931 /* enable/disable TX */
4932 regval = rd32(E1000_TSYNCTXCTL);
4933 regval = (regval & ~E1000_TSYNCTXCTL_ENABLED) | tsync_tx_ctl_bit;
4934 wr32(E1000_TSYNCTXCTL, regval);
4936 /* enable/disable RX, define which PTP packets are time stamped */
4937 regval = rd32(E1000_TSYNCRXCTL);
4938 regval = (regval & ~E1000_TSYNCRXCTL_ENABLED) | tsync_rx_ctl_bit;
4939 regval = (regval & ~0xE) | tsync_rx_ctl_type;
4940 wr32(E1000_TSYNCRXCTL, regval);
4941 wr32(E1000_TSYNCRXCFG, tsync_rx_cfg);
4944 * Ethertype Filter Queue Filter[0][15:0] = 0x88F7
4945 * (Ethertype to filter on)
4946 * Ethertype Filter Queue Filter[0][26] = 0x1 (Enable filter)
4947 * Ethertype Filter Queue Filter[0][30] = 0x1 (Enable Timestamping)
4949 wr32(E1000_ETQF0, is_l2 ? 0x440088f7 : 0);
4951 /* L4 Queue Filter[0]: only filter by source and destination port */
4952 wr32(E1000_SPQF0, htons(port));
4953 wr32(E1000_IMIREXT(0), is_l4 ?
4954 ((1<<12) | (1<<19) /* bypass size and control flags */) : 0);
4955 wr32(E1000_IMIR(0), is_l4 ?
4957 | (0<<16) /* immediate interrupt disabled */
4958 | 0 /* (1<<17) bit cleared: do not bypass
4959 destination port check */)
4961 wr32(E1000_FTQF0, is_l4 ?
4963 | (1<<15) /* VF not compared */
4964 | (1<<27) /* Enable Timestamping */
4965 | (7<<28) /* only source port filter enabled,
4966 source/target address and protocol
4968 : ((1<<15) | (15<<28) /* all mask bits set = filter not
4973 adapter->hwtstamp_config = config;
4975 /* clear TX/RX time stamp registers, just to be sure */
4976 regval = rd32(E1000_TXSTMPH);
4977 regval = rd32(E1000_RXSTMPH);
4979 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
4989 static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4995 return igb_mii_ioctl(netdev, ifr, cmd);
4997 return igb_hwtstamp_ioctl(netdev, ifr, cmd);
5003 static void igb_vlan_rx_register(struct net_device *netdev,
5004 struct vlan_group *grp)
5006 struct igb_adapter *adapter = netdev_priv(netdev);
5007 struct e1000_hw *hw = &adapter->hw;
5010 igb_irq_disable(adapter);
5011 adapter->vlgrp = grp;
5014 /* enable VLAN tag insert/strip */
5015 ctrl = rd32(E1000_CTRL);
5016 ctrl |= E1000_CTRL_VME;
5017 wr32(E1000_CTRL, ctrl);
5019 /* enable VLAN receive filtering */
5020 rctl = rd32(E1000_RCTL);
5021 rctl &= ~E1000_RCTL_CFIEN;
5022 wr32(E1000_RCTL, rctl);
5023 igb_update_mng_vlan(adapter);
5025 /* disable VLAN tag insert/strip */
5026 ctrl = rd32(E1000_CTRL);
5027 ctrl &= ~E1000_CTRL_VME;
5028 wr32(E1000_CTRL, ctrl);
5030 if (adapter->mng_vlan_id != (u16)IGB_MNG_VLAN_NONE) {
5031 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
5032 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
5036 igb_rlpml_set(adapter);
5038 if (!test_bit(__IGB_DOWN, &adapter->state))
5039 igb_irq_enable(adapter);
5042 static void igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
5044 struct igb_adapter *adapter = netdev_priv(netdev);
5045 struct e1000_hw *hw = &adapter->hw;
5046 int pf_id = adapter->vfs_allocated_count;
5048 if ((hw->mng_cookie.status &
5049 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
5050 (vid == adapter->mng_vlan_id))
5053 /* add vid to vlvf if sr-iov is enabled,
5054 * if that fails add directly to filter table */
5055 if (igb_vlvf_set(adapter, vid, true, pf_id))
5056 igb_vfta_set(hw, vid, true);
5060 static void igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
5062 struct igb_adapter *adapter = netdev_priv(netdev);
5063 struct e1000_hw *hw = &adapter->hw;
5064 int pf_id = adapter->vfs_allocated_count;
5066 igb_irq_disable(adapter);
5067 vlan_group_set_device(adapter->vlgrp, vid, NULL);
5069 if (!test_bit(__IGB_DOWN, &adapter->state))
5070 igb_irq_enable(adapter);
5072 if ((adapter->hw.mng_cookie.status &
5073 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
5074 (vid == adapter->mng_vlan_id)) {
5075 /* release control to f/w */
5076 igb_release_hw_control(adapter);
5080 /* remove vid from vlvf if sr-iov is enabled,
5081 * if not in vlvf remove from vfta */
5082 if (igb_vlvf_set(adapter, vid, false, pf_id))
5083 igb_vfta_set(hw, vid, false);
5086 static void igb_restore_vlan(struct igb_adapter *adapter)
5088 igb_vlan_rx_register(adapter->netdev, adapter->vlgrp);
5090 if (adapter->vlgrp) {
5092 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
5093 if (!vlan_group_get_device(adapter->vlgrp, vid))
5095 igb_vlan_rx_add_vid(adapter->netdev, vid);
5100 int igb_set_spd_dplx(struct igb_adapter *adapter, u16 spddplx)
5102 struct e1000_mac_info *mac = &adapter->hw.mac;
5106 /* Fiber NICs only allow 1000 gbps Full duplex */
5107 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) &&
5108 spddplx != (SPEED_1000 + DUPLEX_FULL)) {
5109 dev_err(&adapter->pdev->dev,
5110 "Unsupported Speed/Duplex configuration\n");
5115 case SPEED_10 + DUPLEX_HALF:
5116 mac->forced_speed_duplex = ADVERTISE_10_HALF;
5118 case SPEED_10 + DUPLEX_FULL:
5119 mac->forced_speed_duplex = ADVERTISE_10_FULL;
5121 case SPEED_100 + DUPLEX_HALF:
5122 mac->forced_speed_duplex = ADVERTISE_100_HALF;
5124 case SPEED_100 + DUPLEX_FULL:
5125 mac->forced_speed_duplex = ADVERTISE_100_FULL;
5127 case SPEED_1000 + DUPLEX_FULL:
5129 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
5131 case SPEED_1000 + DUPLEX_HALF: /* not supported */
5133 dev_err(&adapter->pdev->dev,
5134 "Unsupported Speed/Duplex configuration\n");
5140 static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake)
5142 struct net_device *netdev = pci_get_drvdata(pdev);
5143 struct igb_adapter *adapter = netdev_priv(netdev);
5144 struct e1000_hw *hw = &adapter->hw;
5145 u32 ctrl, rctl, status;
5146 u32 wufc = adapter->wol;
5151 netif_device_detach(netdev);
5153 if (netif_running(netdev))
5156 igb_reset_interrupt_capability(adapter);
5158 igb_free_queues(adapter);
5161 retval = pci_save_state(pdev);
5166 status = rd32(E1000_STATUS);
5167 if (status & E1000_STATUS_LU)
5168 wufc &= ~E1000_WUFC_LNKC;
5171 igb_setup_rctl(adapter);
5172 igb_set_multi(netdev);
5174 /* turn on all-multi mode if wake on multicast is enabled */
5175 if (wufc & E1000_WUFC_MC) {
5176 rctl = rd32(E1000_RCTL);
5177 rctl |= E1000_RCTL_MPE;
5178 wr32(E1000_RCTL, rctl);
5181 ctrl = rd32(E1000_CTRL);
5182 /* advertise wake from D3Cold */
5183 #define E1000_CTRL_ADVD3WUC 0x00100000
5184 /* phy power management enable */
5185 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
5186 ctrl |= E1000_CTRL_ADVD3WUC;
5187 wr32(E1000_CTRL, ctrl);
5189 /* Allow time for pending master requests to run */
5190 igb_disable_pcie_master(&adapter->hw);
5192 wr32(E1000_WUC, E1000_WUC_PME_EN);
5193 wr32(E1000_WUFC, wufc);
5196 wr32(E1000_WUFC, 0);
5199 *enable_wake = wufc || adapter->en_mng_pt;
5201 igb_shutdown_fiber_serdes_link_82575(hw);
5203 /* Release control of h/w to f/w. If f/w is AMT enabled, this
5204 * would have already happened in close and is redundant. */
5205 igb_release_hw_control(adapter);
5207 pci_disable_device(pdev);
5213 static int igb_suspend(struct pci_dev *pdev, pm_message_t state)
5218 retval = __igb_shutdown(pdev, &wake);
5223 pci_prepare_to_sleep(pdev);
5225 pci_wake_from_d3(pdev, false);
5226 pci_set_power_state(pdev, PCI_D3hot);
5232 static int igb_resume(struct pci_dev *pdev)
5234 struct net_device *netdev = pci_get_drvdata(pdev);
5235 struct igb_adapter *adapter = netdev_priv(netdev);
5236 struct e1000_hw *hw = &adapter->hw;
5239 pci_set_power_state(pdev, PCI_D0);
5240 pci_restore_state(pdev);
5242 err = pci_enable_device_mem(pdev);
5245 "igb: Cannot enable PCI device from suspend\n");
5248 pci_set_master(pdev);
5250 pci_enable_wake(pdev, PCI_D3hot, 0);
5251 pci_enable_wake(pdev, PCI_D3cold, 0);
5253 igb_set_interrupt_capability(adapter);
5255 if (igb_alloc_queues(adapter)) {
5256 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
5260 /* e1000_power_up_phy(adapter); */
5264 /* let the f/w know that the h/w is now under the control of the
5266 igb_get_hw_control(adapter);
5268 wr32(E1000_WUS, ~0);
5270 if (netif_running(netdev)) {
5271 err = igb_open(netdev);
5276 netif_device_attach(netdev);
5282 static void igb_shutdown(struct pci_dev *pdev)
5286 __igb_shutdown(pdev, &wake);
5288 if (system_state == SYSTEM_POWER_OFF) {
5289 pci_wake_from_d3(pdev, wake);
5290 pci_set_power_state(pdev, PCI_D3hot);
5294 #ifdef CONFIG_NET_POLL_CONTROLLER
5296 * Polling 'interrupt' - used by things like netconsole to send skbs
5297 * without having to re-enable interrupts. It's not called while
5298 * the interrupt routine is executing.
5300 static void igb_netpoll(struct net_device *netdev)
5302 struct igb_adapter *adapter = netdev_priv(netdev);
5303 struct e1000_hw *hw = &adapter->hw;
5306 if (!adapter->msix_entries) {
5307 igb_irq_disable(adapter);
5308 napi_schedule(&adapter->rx_ring[0].napi);
5312 for (i = 0; i < adapter->num_tx_queues; i++) {
5313 struct igb_ring *tx_ring = &adapter->tx_ring[i];
5314 wr32(E1000_EIMC, tx_ring->eims_value);
5315 igb_clean_tx_irq(tx_ring);
5316 wr32(E1000_EIMS, tx_ring->eims_value);
5319 for (i = 0; i < adapter->num_rx_queues; i++) {
5320 struct igb_ring *rx_ring = &adapter->rx_ring[i];
5321 wr32(E1000_EIMC, rx_ring->eims_value);
5322 napi_schedule(&rx_ring->napi);
5325 #endif /* CONFIG_NET_POLL_CONTROLLER */
5328 * igb_io_error_detected - called when PCI error is detected
5329 * @pdev: Pointer to PCI device
5330 * @state: The current pci connection state
5332 * This function is called after a PCI bus error affecting
5333 * this device has been detected.
5335 static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
5336 pci_channel_state_t state)
5338 struct net_device *netdev = pci_get_drvdata(pdev);
5339 struct igb_adapter *adapter = netdev_priv(netdev);
5341 netif_device_detach(netdev);
5343 if (netif_running(netdev))
5345 pci_disable_device(pdev);
5347 /* Request a slot slot reset. */
5348 return PCI_ERS_RESULT_NEED_RESET;
5352 * igb_io_slot_reset - called after the pci bus has been reset.
5353 * @pdev: Pointer to PCI device
5355 * Restart the card from scratch, as if from a cold-boot. Implementation
5356 * resembles the first-half of the igb_resume routine.
5358 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
5360 struct net_device *netdev = pci_get_drvdata(pdev);
5361 struct igb_adapter *adapter = netdev_priv(netdev);
5362 struct e1000_hw *hw = &adapter->hw;
5363 pci_ers_result_t result;
5366 if (pci_enable_device_mem(pdev)) {
5368 "Cannot re-enable PCI device after reset.\n");
5369 result = PCI_ERS_RESULT_DISCONNECT;
5371 pci_set_master(pdev);
5372 pci_restore_state(pdev);
5374 pci_enable_wake(pdev, PCI_D3hot, 0);
5375 pci_enable_wake(pdev, PCI_D3cold, 0);
5378 wr32(E1000_WUS, ~0);
5379 result = PCI_ERS_RESULT_RECOVERED;
5382 err = pci_cleanup_aer_uncorrect_error_status(pdev);
5384 dev_err(&pdev->dev, "pci_cleanup_aer_uncorrect_error_status "
5385 "failed 0x%0x\n", err);
5386 /* non-fatal, continue */
5393 * igb_io_resume - called when traffic can start flowing again.
5394 * @pdev: Pointer to PCI device
5396 * This callback is called when the error recovery driver tells us that
5397 * its OK to resume normal operation. Implementation resembles the
5398 * second-half of the igb_resume routine.
5400 static void igb_io_resume(struct pci_dev *pdev)
5402 struct net_device *netdev = pci_get_drvdata(pdev);
5403 struct igb_adapter *adapter = netdev_priv(netdev);
5405 if (netif_running(netdev)) {
5406 if (igb_up(adapter)) {
5407 dev_err(&pdev->dev, "igb_up failed after reset\n");
5412 netif_device_attach(netdev);
5414 /* let the f/w know that the h/w is now under the control of the
5416 igb_get_hw_control(adapter);
5419 static inline void igb_set_vmolr(struct e1000_hw *hw, int vfn)
5423 reg_data = rd32(E1000_VMOLR(vfn));
5424 reg_data |= E1000_VMOLR_BAM | /* Accept broadcast */
5425 E1000_VMOLR_ROPE | /* Accept packets matched in UTA */
5426 E1000_VMOLR_ROMPE | /* Accept packets matched in MTA */
5427 E1000_VMOLR_AUPE | /* Accept untagged packets */
5428 E1000_VMOLR_STRVLAN; /* Strip vlan tags */
5429 wr32(E1000_VMOLR(vfn), reg_data);
5432 static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
5435 struct e1000_hw *hw = &adapter->hw;
5438 vmolr = rd32(E1000_VMOLR(vfn));
5439 vmolr &= ~E1000_VMOLR_RLPML_MASK;
5440 vmolr |= size | E1000_VMOLR_LPE;
5441 wr32(E1000_VMOLR(vfn), vmolr);
5446 static inline void igb_set_rah_pool(struct e1000_hw *hw, int pool, int entry)
5450 reg_data = rd32(E1000_RAH(entry));
5451 reg_data &= ~E1000_RAH_POOL_MASK;
5452 reg_data |= E1000_RAH_POOL_1 << pool;;
5453 wr32(E1000_RAH(entry), reg_data);
5456 static void igb_set_mc_list_pools(struct igb_adapter *adapter,
5457 int entry_count, u16 total_rar_filters)
5459 struct e1000_hw *hw = &adapter->hw;
5460 int i = adapter->vfs_allocated_count + 1;
5462 if ((i + entry_count) < total_rar_filters)
5463 total_rar_filters = i + entry_count;
5465 for (; i < total_rar_filters; i++)
5466 igb_set_rah_pool(hw, adapter->vfs_allocated_count, i);
5469 static int igb_set_vf_mac(struct igb_adapter *adapter,
5470 int vf, unsigned char *mac_addr)
5472 struct e1000_hw *hw = &adapter->hw;
5473 int rar_entry = vf + 1; /* VF MAC addresses start at entry 1 */
5475 igb_rar_set(hw, mac_addr, rar_entry);
5477 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
5479 igb_set_rah_pool(hw, vf, rar_entry);
5484 static void igb_vmm_control(struct igb_adapter *adapter)
5486 struct e1000_hw *hw = &adapter->hw;
5489 if (!adapter->vfs_allocated_count)
5492 /* VF's need PF reset indication before they
5493 * can send/receive mail */
5494 reg_data = rd32(E1000_CTRL_EXT);
5495 reg_data |= E1000_CTRL_EXT_PFRSTD;
5496 wr32(E1000_CTRL_EXT, reg_data);
5498 igb_vmdq_set_loopback_pf(hw, true);
5499 igb_vmdq_set_replication_pf(hw, true);