1 /*********************************************************************
3 * Description: Driver for the SMC Infrared Communications Controller
4 * Author: Daniele Peri (peri@csai.unipa.it)
9 * Copyright (c) 2002 Daniele Peri
10 * All Rights Reserved.
11 * Copyright (c) 2002 Jean Tourrilhes
12 * Copyright (c) 2006 Linus Walleij
15 * Based on smc-ircc.c:
17 * Copyright (c) 2001 Stefani Seibold
18 * Copyright (c) 1999-2001 Dag Brattli
19 * Copyright (c) 1998-1999 Thomas Davis,
23 * Copyright (c) 1997, 1998, 1999-2000 Dag Brattli, All Rights Reserved.
26 * This program is free software; you can redistribute it and/or
27 * modify it under the terms of the GNU General Public License as
28 * published by the Free Software Foundation; either version 2 of
29 * the License, or (at your option) any later version.
31 * This program is distributed in the hope that it will be useful,
32 * but WITHOUT ANY WARRANTY; without even the implied warranty of
33 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
34 * GNU General Public License for more details.
36 * You should have received a copy of the GNU General Public License
37 * along with this program; if not, write to the Free Software
38 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
41 ********************************************************************/
43 #include <linux/module.h>
44 #include <linux/kernel.h>
45 #include <linux/types.h>
46 #include <linux/skbuff.h>
47 #include <linux/netdevice.h>
48 #include <linux/ioport.h>
49 #include <linux/delay.h>
50 #include <linux/init.h>
51 #include <linux/interrupt.h>
52 #include <linux/rtnetlink.h>
53 #include <linux/serial_reg.h>
54 #include <linux/dma-mapping.h>
55 #include <linux/pnp.h>
56 #include <linux/platform_device.h>
57 #include <linux/gfp.h>
61 #include <asm/byteorder.h>
63 #include <linux/spinlock.h>
66 #include <linux/pci.h>
69 #include <net/irda/wrapper.h>
70 #include <net/irda/irda.h>
71 #include <net/irda/irda_device.h>
73 #include "smsc-ircc2.h"
77 MODULE_AUTHOR("Daniele Peri <peri@csai.unipa.it>");
78 MODULE_DESCRIPTION("SMC IrCC SIR/FIR controller driver");
79 MODULE_LICENSE("GPL");
81 static bool smsc_nopnp = true;
82 module_param_named(nopnp, smsc_nopnp, bool, 0);
83 MODULE_PARM_DESC(nopnp, "Do not use PNP to detect controller settings, defaults to true");
86 static int ircc_dma = DMA_INVAL;
87 module_param(ircc_dma, int, 0);
88 MODULE_PARM_DESC(ircc_dma, "DMA channel");
91 static int ircc_irq = IRQ_INVAL;
92 module_param(ircc_irq, int, 0);
93 MODULE_PARM_DESC(ircc_irq, "IRQ line");
96 module_param(ircc_fir, int, 0);
97 MODULE_PARM_DESC(ircc_fir, "FIR Base Address");
100 module_param(ircc_sir, int, 0);
101 MODULE_PARM_DESC(ircc_sir, "SIR Base Address");
104 module_param(ircc_cfg, int, 0);
105 MODULE_PARM_DESC(ircc_cfg, "Configuration register base address");
107 static int ircc_transceiver;
108 module_param(ircc_transceiver, int, 0);
109 MODULE_PARM_DESC(ircc_transceiver, "Transceiver type");
114 struct smsc_ircc_subsystem_configuration {
115 unsigned short vendor; /* PCI vendor ID */
116 unsigned short device; /* PCI vendor ID */
117 unsigned short subvendor; /* PCI subsystem vendor ID */
118 unsigned short subdevice; /* PCI subsystem device ID */
119 unsigned short sir_io; /* I/O port for SIR */
120 unsigned short fir_io; /* I/O port for FIR */
121 unsigned char fir_irq; /* FIR IRQ */
122 unsigned char fir_dma; /* FIR DMA */
123 unsigned short cfg_base; /* I/O port for chip configuration */
124 int (*preconfigure)(struct pci_dev *dev, struct smsc_ircc_subsystem_configuration *conf); /* Preconfig function */
125 const char *name; /* name shown as info */
129 struct smsc_transceiver {
131 void (*set_for_speed)(int fir_base, u32 speed);
132 int (*probe)(int fir_base);
145 struct smsc_chip_address {
146 unsigned int cfg_base;
150 /* Private data for each instance */
151 struct smsc_ircc_cb {
152 struct net_device *netdev; /* Yes! we are some kind of netdevice */
153 struct irlap_cb *irlap; /* The link layer we are binded to */
155 chipio_t io; /* IrDA controller information */
156 iobuff_t tx_buff; /* Transmit buffer */
157 iobuff_t rx_buff; /* Receive buffer */
158 dma_addr_t tx_buff_dma;
159 dma_addr_t rx_buff_dma;
161 struct qos_info qos; /* QoS capabilities for this device */
163 spinlock_t lock; /* For serializing operations */
166 __u32 flags; /* Interface flags */
168 int tx_buff_offsets[10]; /* Offsets between frames in tx_buff */
169 int tx_len; /* Number of frames in tx_buff */
172 struct platform_device *pldev;
177 #define SMSC_IRCC2_DRIVER_NAME "smsc-ircc2"
179 #define SMSC_IRCC2_C_IRDA_FALLBACK_SPEED 9600
180 #define SMSC_IRCC2_C_DEFAULT_TRANSCEIVER 1
181 #define SMSC_IRCC2_C_NET_TIMEOUT 0
182 #define SMSC_IRCC2_C_SIR_STOP 0
184 static const char *driver_name = SMSC_IRCC2_DRIVER_NAME;
188 static int smsc_ircc_open(unsigned int firbase, unsigned int sirbase, u8 dma, u8 irq);
189 static int smsc_ircc_present(unsigned int fir_base, unsigned int sir_base);
190 static void smsc_ircc_setup_io(struct smsc_ircc_cb *self, unsigned int fir_base, unsigned int sir_base, u8 dma, u8 irq);
191 static void smsc_ircc_setup_qos(struct smsc_ircc_cb *self);
192 static void smsc_ircc_init_chip(struct smsc_ircc_cb *self);
193 static int __exit smsc_ircc_close(struct smsc_ircc_cb *self);
194 static int smsc_ircc_dma_receive(struct smsc_ircc_cb *self);
195 static void smsc_ircc_dma_receive_complete(struct smsc_ircc_cb *self);
196 static void smsc_ircc_sir_receive(struct smsc_ircc_cb *self);
197 static netdev_tx_t smsc_ircc_hard_xmit_sir(struct sk_buff *skb,
198 struct net_device *dev);
199 static netdev_tx_t smsc_ircc_hard_xmit_fir(struct sk_buff *skb,
200 struct net_device *dev);
201 static void smsc_ircc_dma_xmit(struct smsc_ircc_cb *self, int bofs);
202 static void smsc_ircc_dma_xmit_complete(struct smsc_ircc_cb *self);
203 static void smsc_ircc_change_speed(struct smsc_ircc_cb *self, u32 speed);
204 static void smsc_ircc_set_sir_speed(struct smsc_ircc_cb *self, u32 speed);
205 static irqreturn_t smsc_ircc_interrupt(int irq, void *dev_id);
206 static irqreturn_t smsc_ircc_interrupt_sir(struct net_device *dev);
207 static void smsc_ircc_sir_start(struct smsc_ircc_cb *self);
208 #if SMSC_IRCC2_C_SIR_STOP
209 static void smsc_ircc_sir_stop(struct smsc_ircc_cb *self);
211 static void smsc_ircc_sir_write_wakeup(struct smsc_ircc_cb *self);
212 static int smsc_ircc_sir_write(int iobase, int fifo_size, __u8 *buf, int len);
213 static int smsc_ircc_net_open(struct net_device *dev);
214 static int smsc_ircc_net_close(struct net_device *dev);
215 static int smsc_ircc_net_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
216 #if SMSC_IRCC2_C_NET_TIMEOUT
217 static void smsc_ircc_timeout(struct net_device *dev);
219 static int smsc_ircc_is_receiving(struct smsc_ircc_cb *self);
220 static void smsc_ircc_probe_transceiver(struct smsc_ircc_cb *self);
221 static void smsc_ircc_set_transceiver_for_speed(struct smsc_ircc_cb *self, u32 speed);
222 static void smsc_ircc_sir_wait_hw_transmitter_finish(struct smsc_ircc_cb *self);
225 static int __init smsc_ircc_look_for_chips(void);
226 static const struct smsc_chip * __init smsc_ircc_probe(unsigned short cfg_base, u8 reg, const struct smsc_chip *chip, char *type);
227 static int __init smsc_superio_flat(const struct smsc_chip *chips, unsigned short cfg_base, char *type);
228 static int __init smsc_superio_paged(const struct smsc_chip *chips, unsigned short cfg_base, char *type);
229 static int __init smsc_superio_fdc(unsigned short cfg_base);
230 static int __init smsc_superio_lpc(unsigned short cfg_base);
232 static int __init preconfigure_smsc_chip(struct smsc_ircc_subsystem_configuration *conf);
233 static int __init preconfigure_through_82801(struct pci_dev *dev, struct smsc_ircc_subsystem_configuration *conf);
234 static void __init preconfigure_ali_port(struct pci_dev *dev,
235 unsigned short port);
236 static int __init preconfigure_through_ali(struct pci_dev *dev, struct smsc_ircc_subsystem_configuration *conf);
237 static int __init smsc_ircc_preconfigure_subsystems(unsigned short ircc_cfg,
238 unsigned short ircc_fir,
239 unsigned short ircc_sir,
240 unsigned char ircc_dma,
241 unsigned char ircc_irq);
244 /* Transceivers specific functions */
246 static void smsc_ircc_set_transceiver_toshiba_sat1800(int fir_base, u32 speed);
247 static int smsc_ircc_probe_transceiver_toshiba_sat1800(int fir_base);
248 static void smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(int fir_base, u32 speed);
249 static int smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(int fir_base);
250 static void smsc_ircc_set_transceiver_smsc_ircc_atc(int fir_base, u32 speed);
251 static int smsc_ircc_probe_transceiver_smsc_ircc_atc(int fir_base);
253 /* Power Management */
255 static int smsc_ircc_suspend(struct platform_device *dev, pm_message_t state);
256 static int smsc_ircc_resume(struct platform_device *dev);
258 static struct platform_driver smsc_ircc_driver = {
259 .suspend = smsc_ircc_suspend,
260 .resume = smsc_ircc_resume,
262 .name = SMSC_IRCC2_DRIVER_NAME,
266 /* Transceivers for SMSC-ircc */
268 static struct smsc_transceiver smsc_transceivers[] =
270 { "Toshiba Satellite 1800 (GP data pin select)", smsc_ircc_set_transceiver_toshiba_sat1800, smsc_ircc_probe_transceiver_toshiba_sat1800 },
271 { "Fast pin select", smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select, smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select },
272 { "ATC IRMode", smsc_ircc_set_transceiver_smsc_ircc_atc, smsc_ircc_probe_transceiver_smsc_ircc_atc },
275 #define SMSC_IRCC2_C_NUMBER_OF_TRANSCEIVERS (ARRAY_SIZE(smsc_transceivers) - 1)
277 /* SMC SuperIO chipsets definitions */
279 #define KEY55_1 0 /* SuperIO Configuration mode with Key <0x55> */
280 #define KEY55_2 1 /* SuperIO Configuration mode with Key <0x55,0x55> */
281 #define NoIRDA 2 /* SuperIO Chip has no IRDA Port */
282 #define SIR 0 /* SuperIO Chip has only slow IRDA */
283 #define FIR 4 /* SuperIO Chip has fast IRDA */
284 #define SERx4 8 /* SuperIO Chip supports 115,2 KBaud * 4=460,8 KBaud */
286 static struct smsc_chip __initdata fdc_chips_flat[] =
288 /* Base address 0x3f0 or 0x370 */
289 { "37C44", KEY55_1|NoIRDA, 0x00, 0x00 }, /* This chip cannot be detected */
290 { "37C665GT", KEY55_2|NoIRDA, 0x65, 0x01 },
291 { "37C665GT", KEY55_2|NoIRDA, 0x66, 0x01 },
292 { "37C669", KEY55_2|SIR|SERx4, 0x03, 0x02 },
293 { "37C669", KEY55_2|SIR|SERx4, 0x04, 0x02 }, /* ID? */
294 { "37C78", KEY55_2|NoIRDA, 0x78, 0x00 },
295 { "37N769", KEY55_1|FIR|SERx4, 0x28, 0x00 },
296 { "37N869", KEY55_1|FIR|SERx4, 0x29, 0x00 },
300 static struct smsc_chip __initdata fdc_chips_paged[] =
302 /* Base address 0x3f0 or 0x370 */
303 { "37B72X", KEY55_1|SIR|SERx4, 0x4c, 0x00 },
304 { "37B77X", KEY55_1|SIR|SERx4, 0x43, 0x00 },
305 { "37B78X", KEY55_1|SIR|SERx4, 0x44, 0x00 },
306 { "37B80X", KEY55_1|SIR|SERx4, 0x42, 0x00 },
307 { "37C67X", KEY55_1|FIR|SERx4, 0x40, 0x00 },
308 { "37C93X", KEY55_2|SIR|SERx4, 0x02, 0x01 },
309 { "37C93XAPM", KEY55_1|SIR|SERx4, 0x30, 0x01 },
310 { "37C93XFR", KEY55_2|FIR|SERx4, 0x03, 0x01 },
311 { "37M707", KEY55_1|SIR|SERx4, 0x42, 0x00 },
312 { "37M81X", KEY55_1|SIR|SERx4, 0x4d, 0x00 },
313 { "37N958FR", KEY55_1|FIR|SERx4, 0x09, 0x04 },
314 { "37N971", KEY55_1|FIR|SERx4, 0x0a, 0x00 },
315 { "37N972", KEY55_1|FIR|SERx4, 0x0b, 0x00 },
319 static struct smsc_chip __initdata lpc_chips_flat[] =
321 /* Base address 0x2E or 0x4E */
322 { "47N227", KEY55_1|FIR|SERx4, 0x5a, 0x00 },
323 { "47N227", KEY55_1|FIR|SERx4, 0x7a, 0x00 },
324 { "47N267", KEY55_1|FIR|SERx4, 0x5e, 0x00 },
328 static struct smsc_chip __initdata lpc_chips_paged[] =
330 /* Base address 0x2E or 0x4E */
331 { "47B27X", KEY55_1|SIR|SERx4, 0x51, 0x00 },
332 { "47B37X", KEY55_1|SIR|SERx4, 0x52, 0x00 },
333 { "47M10X", KEY55_1|SIR|SERx4, 0x59, 0x00 },
334 { "47M120", KEY55_1|NoIRDA|SERx4, 0x5c, 0x00 },
335 { "47M13X", KEY55_1|SIR|SERx4, 0x59, 0x00 },
336 { "47M14X", KEY55_1|SIR|SERx4, 0x5f, 0x00 },
337 { "47N252", KEY55_1|FIR|SERx4, 0x0e, 0x00 },
338 { "47S42X", KEY55_1|SIR|SERx4, 0x57, 0x00 },
342 #define SMSCSIO_TYPE_FDC 1
343 #define SMSCSIO_TYPE_LPC 2
344 #define SMSCSIO_TYPE_FLAT 4
345 #define SMSCSIO_TYPE_PAGED 8
347 static struct smsc_chip_address __initdata possible_addresses[] =
349 { 0x3f0, SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
350 { 0x370, SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
351 { 0xe0, SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
352 { 0x2e, SMSCSIO_TYPE_LPC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
353 { 0x4e, SMSCSIO_TYPE_LPC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
359 static struct smsc_ircc_cb *dev_self[] = { NULL, NULL };
360 static unsigned short dev_count;
362 static inline void register_bank(int iobase, int bank)
364 outb(((inb(iobase + IRCC_MASTER) & 0xf0) | (bank & 0x07)),
365 iobase + IRCC_MASTER);
368 /* PNP hotplug support */
369 static const struct pnp_device_id smsc_ircc_pnp_table[] = {
370 { .id = "SMCf010", .driver_data = 0 },
371 /* and presumably others */
374 MODULE_DEVICE_TABLE(pnp, smsc_ircc_pnp_table);
376 static int pnp_driver_registered;
379 static int smsc_ircc_pnp_probe(struct pnp_dev *dev,
380 const struct pnp_device_id *dev_id)
382 unsigned int firbase, sirbase;
385 if (!(pnp_port_valid(dev, 0) && pnp_port_valid(dev, 1) &&
386 pnp_dma_valid(dev, 0) && pnp_irq_valid(dev, 0)))
389 sirbase = pnp_port_start(dev, 0);
390 firbase = pnp_port_start(dev, 1);
391 dma = pnp_dma(dev, 0);
392 irq = pnp_irq(dev, 0);
394 if (smsc_ircc_open(firbase, sirbase, dma, irq))
400 static struct pnp_driver smsc_ircc_pnp_driver = {
401 .name = "smsc-ircc2",
402 .id_table = smsc_ircc_pnp_table,
403 .probe = smsc_ircc_pnp_probe,
405 #else /* CONFIG_PNP */
406 static struct pnp_driver smsc_ircc_pnp_driver;
409 /*******************************************************************************
415 *******************************************************************************/
417 static int __init smsc_ircc_legacy_probe(void)
422 if (smsc_ircc_preconfigure_subsystems(ircc_cfg, ircc_fir, ircc_sir, ircc_dma, ircc_irq) < 0) {
423 /* Ignore errors from preconfiguration */
424 IRDA_ERROR("%s, Preconfiguration failed !\n", driver_name);
428 if (ircc_fir > 0 && ircc_sir > 0) {
429 IRDA_MESSAGE(" Overriding FIR address 0x%04x\n", ircc_fir);
430 IRDA_MESSAGE(" Overriding SIR address 0x%04x\n", ircc_sir);
432 if (smsc_ircc_open(ircc_fir, ircc_sir, ircc_dma, ircc_irq))
437 /* try user provided configuration register base address */
439 IRDA_MESSAGE(" Overriding configuration address "
440 "0x%04x\n", ircc_cfg);
441 if (!smsc_superio_fdc(ircc_cfg))
443 if (!smsc_superio_lpc(ircc_cfg))
447 if (smsc_ircc_look_for_chips() > 0)
454 * Function smsc_ircc_init ()
456 * Initialize chip. Just try to find out how many chips we are dealing with
459 static int __init smsc_ircc_init(void)
463 IRDA_DEBUG(1, "%s\n", __func__);
465 ret = platform_driver_register(&smsc_ircc_driver);
467 IRDA_ERROR("%s, Can't register driver!\n", driver_name);
473 if (smsc_nopnp || !pnp_platform_devices ||
474 ircc_cfg || ircc_fir || ircc_sir ||
475 ircc_dma != DMA_INVAL || ircc_irq != IRQ_INVAL) {
476 ret = smsc_ircc_legacy_probe();
478 if (pnp_register_driver(&smsc_ircc_pnp_driver) == 0)
479 pnp_driver_registered = 1;
483 if (pnp_driver_registered)
484 pnp_unregister_driver(&smsc_ircc_pnp_driver);
485 platform_driver_unregister(&smsc_ircc_driver);
491 static netdev_tx_t smsc_ircc_net_xmit(struct sk_buff *skb,
492 struct net_device *dev)
494 struct smsc_ircc_cb *self = netdev_priv(dev);
496 if (self->io.speed > 115200)
497 return smsc_ircc_hard_xmit_fir(skb, dev);
499 return smsc_ircc_hard_xmit_sir(skb, dev);
502 static const struct net_device_ops smsc_ircc_netdev_ops = {
503 .ndo_open = smsc_ircc_net_open,
504 .ndo_stop = smsc_ircc_net_close,
505 .ndo_do_ioctl = smsc_ircc_net_ioctl,
506 .ndo_start_xmit = smsc_ircc_net_xmit,
507 #if SMSC_IRCC2_C_NET_TIMEOUT
508 .ndo_tx_timeout = smsc_ircc_timeout,
513 * Function smsc_ircc_open (firbase, sirbase, dma, irq)
515 * Try to open driver instance
518 static int smsc_ircc_open(unsigned int fir_base, unsigned int sir_base, u8 dma, u8 irq)
520 struct smsc_ircc_cb *self;
521 struct net_device *dev;
524 IRDA_DEBUG(1, "%s\n", __func__);
526 err = smsc_ircc_present(fir_base, sir_base);
531 if (dev_count >= ARRAY_SIZE(dev_self)) {
532 IRDA_WARNING("%s(), too many devices!\n", __func__);
537 * Allocate new instance of the driver
539 dev = alloc_irdadev(sizeof(struct smsc_ircc_cb));
541 IRDA_WARNING("%s() can't allocate net device\n", __func__);
545 #if SMSC_IRCC2_C_NET_TIMEOUT
546 dev->watchdog_timeo = HZ * 2; /* Allow enough time for speed change */
548 dev->netdev_ops = &smsc_ircc_netdev_ops;
550 self = netdev_priv(dev);
553 /* Make ifconfig display some details */
554 dev->base_addr = self->io.fir_base = fir_base;
555 dev->irq = self->io.irq = irq;
557 /* Need to store self somewhere */
558 dev_self[dev_count] = self;
559 spin_lock_init(&self->lock);
561 self->rx_buff.truesize = SMSC_IRCC2_RX_BUFF_TRUESIZE;
562 self->tx_buff.truesize = SMSC_IRCC2_TX_BUFF_TRUESIZE;
565 dma_alloc_coherent(NULL, self->rx_buff.truesize,
566 &self->rx_buff_dma, GFP_KERNEL);
567 if (self->rx_buff.head == NULL)
571 dma_alloc_coherent(NULL, self->tx_buff.truesize,
572 &self->tx_buff_dma, GFP_KERNEL);
573 if (self->tx_buff.head == NULL)
576 memset(self->rx_buff.head, 0, self->rx_buff.truesize);
577 memset(self->tx_buff.head, 0, self->tx_buff.truesize);
579 self->rx_buff.in_frame = FALSE;
580 self->rx_buff.state = OUTSIDE_FRAME;
581 self->tx_buff.data = self->tx_buff.head;
582 self->rx_buff.data = self->rx_buff.head;
584 smsc_ircc_setup_io(self, fir_base, sir_base, dma, irq);
585 smsc_ircc_setup_qos(self);
586 smsc_ircc_init_chip(self);
588 if (ircc_transceiver > 0 &&
589 ircc_transceiver < SMSC_IRCC2_C_NUMBER_OF_TRANSCEIVERS)
590 self->transceiver = ircc_transceiver;
592 smsc_ircc_probe_transceiver(self);
594 err = register_netdev(self->netdev);
596 IRDA_ERROR("%s, Network device registration failed!\n",
601 self->pldev = platform_device_register_simple(SMSC_IRCC2_DRIVER_NAME,
603 if (IS_ERR(self->pldev)) {
604 err = PTR_ERR(self->pldev);
607 platform_set_drvdata(self->pldev, self);
609 IRDA_MESSAGE("IrDA: Registered device %s\n", dev->name);
615 unregister_netdev(self->netdev);
618 dma_free_coherent(NULL, self->tx_buff.truesize,
619 self->tx_buff.head, self->tx_buff_dma);
621 dma_free_coherent(NULL, self->rx_buff.truesize,
622 self->rx_buff.head, self->rx_buff_dma);
624 free_netdev(self->netdev);
625 dev_self[dev_count] = NULL;
627 release_region(fir_base, SMSC_IRCC2_FIR_CHIP_IO_EXTENT);
628 release_region(sir_base, SMSC_IRCC2_SIR_CHIP_IO_EXTENT);
634 * Function smsc_ircc_present(fir_base, sir_base)
636 * Check the smsc-ircc chip presence
639 static int smsc_ircc_present(unsigned int fir_base, unsigned int sir_base)
641 unsigned char low, high, chip, config, dma, irq, version;
643 if (!request_region(fir_base, SMSC_IRCC2_FIR_CHIP_IO_EXTENT,
645 IRDA_WARNING("%s: can't get fir_base of 0x%03x\n",
650 if (!request_region(sir_base, SMSC_IRCC2_SIR_CHIP_IO_EXTENT,
652 IRDA_WARNING("%s: can't get sir_base of 0x%03x\n",
657 register_bank(fir_base, 3);
659 high = inb(fir_base + IRCC_ID_HIGH);
660 low = inb(fir_base + IRCC_ID_LOW);
661 chip = inb(fir_base + IRCC_CHIP_ID);
662 version = inb(fir_base + IRCC_VERSION);
663 config = inb(fir_base + IRCC_INTERFACE);
664 dma = config & IRCC_INTERFACE_DMA_MASK;
665 irq = (config & IRCC_INTERFACE_IRQ_MASK) >> 4;
667 if (high != 0x10 || low != 0xb8 || (chip != 0xf1 && chip != 0xf2)) {
668 IRDA_WARNING("%s(), addr 0x%04x - no device found!\n",
672 IRDA_MESSAGE("SMsC IrDA Controller found\n IrCC version %d.%d, "
673 "firport 0x%03x, sirport 0x%03x dma=%d, irq=%d\n",
674 chip & 0x0f, version, fir_base, sir_base, dma, irq);
679 release_region(sir_base, SMSC_IRCC2_SIR_CHIP_IO_EXTENT);
681 release_region(fir_base, SMSC_IRCC2_FIR_CHIP_IO_EXTENT);
687 * Function smsc_ircc_setup_io(self, fir_base, sir_base, dma, irq)
692 static void smsc_ircc_setup_io(struct smsc_ircc_cb *self,
693 unsigned int fir_base, unsigned int sir_base,
696 unsigned char config, chip_dma, chip_irq;
698 register_bank(fir_base, 3);
699 config = inb(fir_base + IRCC_INTERFACE);
700 chip_dma = config & IRCC_INTERFACE_DMA_MASK;
701 chip_irq = (config & IRCC_INTERFACE_IRQ_MASK) >> 4;
703 self->io.fir_base = fir_base;
704 self->io.sir_base = sir_base;
705 self->io.fir_ext = SMSC_IRCC2_FIR_CHIP_IO_EXTENT;
706 self->io.sir_ext = SMSC_IRCC2_SIR_CHIP_IO_EXTENT;
707 self->io.fifo_size = SMSC_IRCC2_FIFO_SIZE;
708 self->io.speed = SMSC_IRCC2_C_IRDA_FALLBACK_SPEED;
710 if (irq != IRQ_INVAL) {
712 IRDA_MESSAGE("%s, Overriding IRQ - chip says %d, using %d\n",
713 driver_name, chip_irq, irq);
716 self->io.irq = chip_irq;
718 if (dma != DMA_INVAL) {
720 IRDA_MESSAGE("%s, Overriding DMA - chip says %d, using %d\n",
721 driver_name, chip_dma, dma);
724 self->io.dma = chip_dma;
729 * Function smsc_ircc_setup_qos(self)
734 static void smsc_ircc_setup_qos(struct smsc_ircc_cb *self)
736 /* Initialize QoS for this device */
737 irda_init_max_qos_capabilies(&self->qos);
739 self->qos.baud_rate.bits = IR_9600|IR_19200|IR_38400|IR_57600|
740 IR_115200|IR_576000|IR_1152000|(IR_4000000 << 8);
742 self->qos.min_turn_time.bits = SMSC_IRCC2_MIN_TURN_TIME;
743 self->qos.window_size.bits = SMSC_IRCC2_WINDOW_SIZE;
744 irda_qos_bits_to_value(&self->qos);
748 * Function smsc_ircc_init_chip(self)
753 static void smsc_ircc_init_chip(struct smsc_ircc_cb *self)
755 int iobase = self->io.fir_base;
757 register_bank(iobase, 0);
758 outb(IRCC_MASTER_RESET, iobase + IRCC_MASTER);
759 outb(0x00, iobase + IRCC_MASTER);
761 register_bank(iobase, 1);
762 outb(((inb(iobase + IRCC_SCE_CFGA) & 0x87) | IRCC_CFGA_IRDA_SIR_A),
763 iobase + IRCC_SCE_CFGA);
765 #ifdef smsc_669 /* Uses pin 88/89 for Rx/Tx */
766 outb(((inb(iobase + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_COM),
767 iobase + IRCC_SCE_CFGB);
769 outb(((inb(iobase + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_IR),
770 iobase + IRCC_SCE_CFGB);
772 (void) inb(iobase + IRCC_FIFO_THRESHOLD);
773 outb(SMSC_IRCC2_FIFO_THRESHOLD, iobase + IRCC_FIFO_THRESHOLD);
775 register_bank(iobase, 4);
776 outb((inb(iobase + IRCC_CONTROL) & 0x30), iobase + IRCC_CONTROL);
778 register_bank(iobase, 0);
779 outb(0, iobase + IRCC_LCR_A);
781 smsc_ircc_set_sir_speed(self, SMSC_IRCC2_C_IRDA_FALLBACK_SPEED);
783 /* Power on device */
784 outb(0x00, iobase + IRCC_MASTER);
788 * Function smsc_ircc_net_ioctl (dev, rq, cmd)
790 * Process IOCTL commands for this device
793 static int smsc_ircc_net_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
795 struct if_irda_req *irq = (struct if_irda_req *) rq;
796 struct smsc_ircc_cb *self;
800 IRDA_ASSERT(dev != NULL, return -1;);
802 self = netdev_priv(dev);
804 IRDA_ASSERT(self != NULL, return -1;);
806 IRDA_DEBUG(2, "%s(), %s, (cmd=0x%X)\n", __func__, dev->name, cmd);
809 case SIOCSBANDWIDTH: /* Set bandwidth */
810 if (!capable(CAP_NET_ADMIN))
813 /* Make sure we are the only one touching
814 * self->io.speed and the hardware - Jean II */
815 spin_lock_irqsave(&self->lock, flags);
816 smsc_ircc_change_speed(self, irq->ifr_baudrate);
817 spin_unlock_irqrestore(&self->lock, flags);
820 case SIOCSMEDIABUSY: /* Set media busy */
821 if (!capable(CAP_NET_ADMIN)) {
826 irda_device_set_media_busy(self->netdev, TRUE);
828 case SIOCGRECEIVING: /* Check if we are receiving right now */
829 irq->ifr_receiving = smsc_ircc_is_receiving(self);
833 if (!capable(CAP_NET_ADMIN)) {
837 smsc_ircc_sir_set_dtr_rts(dev, irq->ifr_dtr, irq->ifr_rts);
847 #if SMSC_IRCC2_C_NET_TIMEOUT
849 * Function smsc_ircc_timeout (struct net_device *dev)
851 * The networking timeout management.
855 static void smsc_ircc_timeout(struct net_device *dev)
857 struct smsc_ircc_cb *self = netdev_priv(dev);
860 IRDA_WARNING("%s: transmit timed out, changing speed to: %d\n",
861 dev->name, self->io.speed);
862 spin_lock_irqsave(&self->lock, flags);
863 smsc_ircc_sir_start(self);
864 smsc_ircc_change_speed(self, self->io.speed);
865 dev->trans_start = jiffies; /* prevent tx timeout */
866 netif_wake_queue(dev);
867 spin_unlock_irqrestore(&self->lock, flags);
872 * Function smsc_ircc_hard_xmit_sir (struct sk_buff *skb, struct net_device *dev)
874 * Transmits the current frame until FIFO is full, then
875 * waits until the next transmit interrupt, and continues until the
876 * frame is transmitted.
878 static netdev_tx_t smsc_ircc_hard_xmit_sir(struct sk_buff *skb,
879 struct net_device *dev)
881 struct smsc_ircc_cb *self;
885 IRDA_DEBUG(1, "%s\n", __func__);
887 IRDA_ASSERT(dev != NULL, return NETDEV_TX_OK;);
889 self = netdev_priv(dev);
890 IRDA_ASSERT(self != NULL, return NETDEV_TX_OK;);
892 netif_stop_queue(dev);
894 /* Make sure test of self->io.speed & speed change are atomic */
895 spin_lock_irqsave(&self->lock, flags);
897 /* Check if we need to change the speed */
898 speed = irda_get_next_speed(skb);
899 if (speed != self->io.speed && speed != -1) {
900 /* Check for empty frame */
903 * We send frames one by one in SIR mode (no
904 * pipelining), so at this point, if we were sending
905 * a previous frame, we just received the interrupt
906 * telling us it is finished (UART_IIR_THRI).
907 * Therefore, waiting for the transmitter to really
908 * finish draining the fifo won't take too long.
909 * And the interrupt handler is not expected to run.
911 smsc_ircc_sir_wait_hw_transmitter_finish(self);
912 smsc_ircc_change_speed(self, speed);
913 spin_unlock_irqrestore(&self->lock, flags);
917 self->new_speed = speed;
921 self->tx_buff.data = self->tx_buff.head;
923 /* Copy skb to tx_buff while wrapping, stuffing and making CRC */
924 self->tx_buff.len = async_wrap_skb(skb, self->tx_buff.data,
925 self->tx_buff.truesize);
927 dev->stats.tx_bytes += self->tx_buff.len;
929 /* Turn on transmit finished interrupt. Will fire immediately! */
930 outb(UART_IER_THRI, self->io.sir_base + UART_IER);
932 spin_unlock_irqrestore(&self->lock, flags);
940 * Function smsc_ircc_set_fir_speed (self, baud)
942 * Change the speed of the device
945 static void smsc_ircc_set_fir_speed(struct smsc_ircc_cb *self, u32 speed)
947 int fir_base, ir_mode, ctrl, fast;
949 IRDA_ASSERT(self != NULL, return;);
950 fir_base = self->io.fir_base;
952 self->io.speed = speed;
957 ir_mode = IRCC_CFGA_IRDA_HDLC;
960 IRDA_DEBUG(0, "%s(), handling baud of 576000\n", __func__);
963 ir_mode = IRCC_CFGA_IRDA_HDLC;
964 ctrl = IRCC_1152 | IRCC_CRC;
965 fast = IRCC_LCR_A_FAST | IRCC_LCR_A_GP_DATA;
966 IRDA_DEBUG(0, "%s(), handling baud of 1152000\n",
970 ir_mode = IRCC_CFGA_IRDA_4PPM;
972 fast = IRCC_LCR_A_FAST;
973 IRDA_DEBUG(0, "%s(), handling baud of 4000000\n",
979 /* This causes an interrupt */
980 register_bank(fir_base, 0);
981 outb((inb(fir_base + IRCC_LCR_A) & 0xbf) | fast, fir_base + IRCC_LCR_A);
984 register_bank(fir_base, 1);
985 outb(((inb(fir_base + IRCC_SCE_CFGA) & IRCC_SCE_CFGA_BLOCK_CTRL_BITS_MASK) | ir_mode), fir_base + IRCC_SCE_CFGA);
987 register_bank(fir_base, 4);
988 outb((inb(fir_base + IRCC_CONTROL) & 0x30) | ctrl, fir_base + IRCC_CONTROL);
992 * Function smsc_ircc_fir_start(self)
994 * Change the speed of the device
997 static void smsc_ircc_fir_start(struct smsc_ircc_cb *self)
999 struct net_device *dev;
1002 IRDA_DEBUG(1, "%s\n", __func__);
1004 IRDA_ASSERT(self != NULL, return;);
1006 IRDA_ASSERT(dev != NULL, return;);
1008 fir_base = self->io.fir_base;
1010 /* Reset everything */
1013 outb(inb(fir_base + IRCC_LCR_A) | IRCC_LCR_A_FIFO_RESET, fir_base + IRCC_LCR_A);
1015 /* Enable interrupt */
1016 /*outb(IRCC_IER_ACTIVE_FRAME|IRCC_IER_EOM, fir_base + IRCC_IER);*/
1018 register_bank(fir_base, 1);
1020 /* Select the TX/RX interface */
1021 #ifdef SMSC_669 /* Uses pin 88/89 for Rx/Tx */
1022 outb(((inb(fir_base + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_COM),
1023 fir_base + IRCC_SCE_CFGB);
1025 outb(((inb(fir_base + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_IR),
1026 fir_base + IRCC_SCE_CFGB);
1028 (void) inb(fir_base + IRCC_FIFO_THRESHOLD);
1030 /* Enable SCE interrupts */
1031 outb(0, fir_base + IRCC_MASTER);
1032 register_bank(fir_base, 0);
1033 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, fir_base + IRCC_IER);
1034 outb(IRCC_MASTER_INT_EN, fir_base + IRCC_MASTER);
1038 * Function smsc_ircc_fir_stop(self, baud)
1040 * Change the speed of the device
1043 static void smsc_ircc_fir_stop(struct smsc_ircc_cb *self)
1047 IRDA_DEBUG(1, "%s\n", __func__);
1049 IRDA_ASSERT(self != NULL, return;);
1051 fir_base = self->io.fir_base;
1052 register_bank(fir_base, 0);
1053 /*outb(IRCC_MASTER_RESET, fir_base + IRCC_MASTER);*/
1054 outb(inb(fir_base + IRCC_LCR_B) & IRCC_LCR_B_SIP_ENABLE, fir_base + IRCC_LCR_B);
1059 * Function smsc_ircc_change_speed(self, baud)
1061 * Change the speed of the device
1063 * This function *must* be called with spinlock held, because it may
1064 * be called from the irq handler. - Jean II
1066 static void smsc_ircc_change_speed(struct smsc_ircc_cb *self, u32 speed)
1068 struct net_device *dev;
1069 int last_speed_was_sir;
1071 IRDA_DEBUG(0, "%s() changing speed to: %d\n", __func__, speed);
1073 IRDA_ASSERT(self != NULL, return;);
1076 last_speed_was_sir = self->io.speed <= SMSC_IRCC2_MAX_SIR_SPEED;
1081 self->io.speed = speed;
1082 last_speed_was_sir = 0;
1083 smsc_ircc_fir_start(self);
1086 if (self->io.speed == 0)
1087 smsc_ircc_sir_start(self);
1090 if (!last_speed_was_sir) speed = self->io.speed;
1093 if (self->io.speed != speed)
1094 smsc_ircc_set_transceiver_for_speed(self, speed);
1096 self->io.speed = speed;
1098 if (speed <= SMSC_IRCC2_MAX_SIR_SPEED) {
1099 if (!last_speed_was_sir) {
1100 smsc_ircc_fir_stop(self);
1101 smsc_ircc_sir_start(self);
1103 smsc_ircc_set_sir_speed(self, speed);
1105 if (last_speed_was_sir) {
1106 #if SMSC_IRCC2_C_SIR_STOP
1107 smsc_ircc_sir_stop(self);
1109 smsc_ircc_fir_start(self);
1111 smsc_ircc_set_fir_speed(self, speed);
1114 self->tx_buff.len = 10;
1115 self->tx_buff.data = self->tx_buff.head;
1117 smsc_ircc_dma_xmit(self, 4000);
1119 /* Be ready for incoming frames */
1120 smsc_ircc_dma_receive(self);
1123 netif_wake_queue(dev);
1127 * Function smsc_ircc_set_sir_speed (self, speed)
1129 * Set speed of IrDA port to specified baudrate
1132 static void smsc_ircc_set_sir_speed(struct smsc_ircc_cb *self, __u32 speed)
1135 int fcr; /* FIFO control reg */
1136 int lcr; /* Line control reg */
1139 IRDA_DEBUG(0, "%s(), Setting speed to: %d\n", __func__, speed);
1141 IRDA_ASSERT(self != NULL, return;);
1142 iobase = self->io.sir_base;
1144 /* Update accounting for new speed */
1145 self->io.speed = speed;
1147 /* Turn off interrupts */
1148 outb(0, iobase + UART_IER);
1150 divisor = SMSC_IRCC2_MAX_SIR_SPEED / speed;
1152 fcr = UART_FCR_ENABLE_FIFO;
1155 * Use trigger level 1 to avoid 3 ms. timeout delay at 9600 bps, and
1156 * almost 1,7 ms at 19200 bps. At speeds above that we can just forget
1157 * about this timeout since it will always be fast enough.
1159 fcr |= self->io.speed < 38400 ?
1160 UART_FCR_TRIGGER_1 : UART_FCR_TRIGGER_14;
1162 /* IrDA ports use 8N1 */
1163 lcr = UART_LCR_WLEN8;
1165 outb(UART_LCR_DLAB | lcr, iobase + UART_LCR); /* Set DLAB */
1166 outb(divisor & 0xff, iobase + UART_DLL); /* Set speed */
1167 outb(divisor >> 8, iobase + UART_DLM);
1168 outb(lcr, iobase + UART_LCR); /* Set 8N1 */
1169 outb(fcr, iobase + UART_FCR); /* Enable FIFO's */
1171 /* Turn on interrups */
1172 outb(UART_IER_RLSI | UART_IER_RDI | UART_IER_THRI, iobase + UART_IER);
1174 IRDA_DEBUG(2, "%s() speed changed to: %d\n", __func__, speed);
1179 * Function smsc_ircc_hard_xmit_fir (skb, dev)
1181 * Transmit the frame!
1184 static netdev_tx_t smsc_ircc_hard_xmit_fir(struct sk_buff *skb,
1185 struct net_device *dev)
1187 struct smsc_ircc_cb *self;
1188 unsigned long flags;
1192 IRDA_ASSERT(dev != NULL, return NETDEV_TX_OK;);
1193 self = netdev_priv(dev);
1194 IRDA_ASSERT(self != NULL, return NETDEV_TX_OK;);
1196 netif_stop_queue(dev);
1198 /* Make sure test of self->io.speed & speed change are atomic */
1199 spin_lock_irqsave(&self->lock, flags);
1201 /* Check if we need to change the speed after this frame */
1202 speed = irda_get_next_speed(skb);
1203 if (speed != self->io.speed && speed != -1) {
1204 /* Check for empty frame */
1206 /* Note : you should make sure that speed changes
1207 * are not going to corrupt any outgoing frame.
1208 * Look at nsc-ircc for the gory details - Jean II */
1209 smsc_ircc_change_speed(self, speed);
1210 spin_unlock_irqrestore(&self->lock, flags);
1212 return NETDEV_TX_OK;
1215 self->new_speed = speed;
1218 skb_copy_from_linear_data(skb, self->tx_buff.head, skb->len);
1220 self->tx_buff.len = skb->len;
1221 self->tx_buff.data = self->tx_buff.head;
1223 mtt = irda_get_mtt(skb);
1228 * Compute how many BOFs (STA or PA's) we need to waste the
1229 * min turn time given the speed of the link.
1231 bofs = mtt * (self->io.speed / 1000) / 8000;
1235 smsc_ircc_dma_xmit(self, bofs);
1237 /* Transmit frame */
1238 smsc_ircc_dma_xmit(self, 0);
1241 spin_unlock_irqrestore(&self->lock, flags);
1244 return NETDEV_TX_OK;
1248 * Function smsc_ircc_dma_xmit (self, bofs)
1250 * Transmit data using DMA
1253 static void smsc_ircc_dma_xmit(struct smsc_ircc_cb *self, int bofs)
1255 int iobase = self->io.fir_base;
1258 IRDA_DEBUG(3, "%s\n", __func__);
1261 register_bank(iobase, 0);
1262 outb(0x00, iobase + IRCC_LCR_B);
1264 register_bank(iobase, 1);
1265 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1266 iobase + IRCC_SCE_CFGB);
1268 self->io.direction = IO_XMIT;
1270 /* Set BOF additional count for generating the min turn time */
1271 register_bank(iobase, 4);
1272 outb(bofs & 0xff, iobase + IRCC_BOF_COUNT_LO);
1273 ctrl = inb(iobase + IRCC_CONTROL) & 0xf0;
1274 outb(ctrl | ((bofs >> 8) & 0x0f), iobase + IRCC_BOF_COUNT_HI);
1276 /* Set max Tx frame size */
1277 outb(self->tx_buff.len >> 8, iobase + IRCC_TX_SIZE_HI);
1278 outb(self->tx_buff.len & 0xff, iobase + IRCC_TX_SIZE_LO);
1280 /*outb(UART_MCR_OUT2, self->io.sir_base + UART_MCR);*/
1282 /* Enable burst mode chip Tx DMA */
1283 register_bank(iobase, 1);
1284 outb(inb(iobase + IRCC_SCE_CFGB) | IRCC_CFGB_DMA_ENABLE |
1285 IRCC_CFGB_DMA_BURST, iobase + IRCC_SCE_CFGB);
1287 /* Setup DMA controller (must be done after enabling chip DMA) */
1288 irda_setup_dma(self->io.dma, self->tx_buff_dma, self->tx_buff.len,
1291 /* Enable interrupt */
1293 register_bank(iobase, 0);
1294 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER);
1295 outb(IRCC_MASTER_INT_EN, iobase + IRCC_MASTER);
1297 /* Enable transmit */
1298 outb(IRCC_LCR_B_SCE_TRANSMIT | IRCC_LCR_B_SIP_ENABLE, iobase + IRCC_LCR_B);
1302 * Function smsc_ircc_dma_xmit_complete (self)
1304 * The transfer of a frame in finished. This function will only be called
1305 * by the interrupt handler
1308 static void smsc_ircc_dma_xmit_complete(struct smsc_ircc_cb *self)
1310 int iobase = self->io.fir_base;
1312 IRDA_DEBUG(3, "%s\n", __func__);
1315 register_bank(iobase, 0);
1316 outb(0x00, iobase + IRCC_LCR_B);
1318 register_bank(iobase, 1);
1319 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1320 iobase + IRCC_SCE_CFGB);
1322 /* Check for underrun! */
1323 register_bank(iobase, 0);
1324 if (inb(iobase + IRCC_LSR) & IRCC_LSR_UNDERRUN) {
1325 self->netdev->stats.tx_errors++;
1326 self->netdev->stats.tx_fifo_errors++;
1328 /* Reset error condition */
1329 register_bank(iobase, 0);
1330 outb(IRCC_MASTER_ERROR_RESET, iobase + IRCC_MASTER);
1331 outb(0x00, iobase + IRCC_MASTER);
1333 self->netdev->stats.tx_packets++;
1334 self->netdev->stats.tx_bytes += self->tx_buff.len;
1337 /* Check if it's time to change the speed */
1338 if (self->new_speed) {
1339 smsc_ircc_change_speed(self, self->new_speed);
1340 self->new_speed = 0;
1343 netif_wake_queue(self->netdev);
1347 * Function smsc_ircc_dma_receive(self)
1349 * Get ready for receiving a frame. The device will initiate a DMA
1350 * if it starts to receive a frame.
1353 static int smsc_ircc_dma_receive(struct smsc_ircc_cb *self)
1355 int iobase = self->io.fir_base;
1357 /* Turn off chip DMA */
1358 register_bank(iobase, 1);
1359 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1360 iobase + IRCC_SCE_CFGB);
1364 register_bank(iobase, 0);
1365 outb(0x00, iobase + IRCC_LCR_B);
1367 /* Turn off chip DMA */
1368 register_bank(iobase, 1);
1369 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1370 iobase + IRCC_SCE_CFGB);
1372 self->io.direction = IO_RECV;
1373 self->rx_buff.data = self->rx_buff.head;
1375 /* Set max Rx frame size */
1376 register_bank(iobase, 4);
1377 outb((2050 >> 8) & 0x0f, iobase + IRCC_RX_SIZE_HI);
1378 outb(2050 & 0xff, iobase + IRCC_RX_SIZE_LO);
1380 /* Setup DMA controller */
1381 irda_setup_dma(self->io.dma, self->rx_buff_dma, self->rx_buff.truesize,
1384 /* Enable burst mode chip Rx DMA */
1385 register_bank(iobase, 1);
1386 outb(inb(iobase + IRCC_SCE_CFGB) | IRCC_CFGB_DMA_ENABLE |
1387 IRCC_CFGB_DMA_BURST, iobase + IRCC_SCE_CFGB);
1389 /* Enable interrupt */
1390 register_bank(iobase, 0);
1391 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER);
1392 outb(IRCC_MASTER_INT_EN, iobase + IRCC_MASTER);
1394 /* Enable receiver */
1395 register_bank(iobase, 0);
1396 outb(IRCC_LCR_B_SCE_RECEIVE | IRCC_LCR_B_SIP_ENABLE,
1397 iobase + IRCC_LCR_B);
1403 * Function smsc_ircc_dma_receive_complete(self)
1405 * Finished with receiving frames
1408 static void smsc_ircc_dma_receive_complete(struct smsc_ircc_cb *self)
1410 struct sk_buff *skb;
1411 int len, msgcnt, lsr;
1412 int iobase = self->io.fir_base;
1414 register_bank(iobase, 0);
1416 IRDA_DEBUG(3, "%s\n", __func__);
1419 register_bank(iobase, 0);
1420 outb(0x00, iobase + IRCC_LCR_B);
1422 register_bank(iobase, 0);
1423 outb(inb(iobase + IRCC_LSAR) & ~IRCC_LSAR_ADDRESS_MASK, iobase + IRCC_LSAR);
1424 lsr= inb(iobase + IRCC_LSR);
1425 msgcnt = inb(iobase + IRCC_LCR_B) & 0x08;
1427 IRDA_DEBUG(2, "%s: dma count = %d\n", __func__,
1428 get_dma_residue(self->io.dma));
1430 len = self->rx_buff.truesize - get_dma_residue(self->io.dma);
1432 /* Look for errors */
1433 if (lsr & (IRCC_LSR_FRAME_ERROR | IRCC_LSR_CRC_ERROR | IRCC_LSR_SIZE_ERROR)) {
1434 self->netdev->stats.rx_errors++;
1435 if (lsr & IRCC_LSR_FRAME_ERROR)
1436 self->netdev->stats.rx_frame_errors++;
1437 if (lsr & IRCC_LSR_CRC_ERROR)
1438 self->netdev->stats.rx_crc_errors++;
1439 if (lsr & IRCC_LSR_SIZE_ERROR)
1440 self->netdev->stats.rx_length_errors++;
1441 if (lsr & (IRCC_LSR_UNDERRUN | IRCC_LSR_OVERRUN))
1442 self->netdev->stats.rx_length_errors++;
1447 len -= self->io.speed < 4000000 ? 2 : 4;
1449 if (len < 2 || len > 2050) {
1450 IRDA_WARNING("%s(), bogus len=%d\n", __func__, len);
1453 IRDA_DEBUG(2, "%s: msgcnt = %d, len=%d\n", __func__, msgcnt, len);
1455 skb = dev_alloc_skb(len + 1);
1457 IRDA_WARNING("%s(), memory squeeze, dropping frame.\n",
1461 /* Make sure IP header gets aligned */
1462 skb_reserve(skb, 1);
1464 memcpy(skb_put(skb, len), self->rx_buff.data, len);
1465 self->netdev->stats.rx_packets++;
1466 self->netdev->stats.rx_bytes += len;
1468 skb->dev = self->netdev;
1469 skb_reset_mac_header(skb);
1470 skb->protocol = htons(ETH_P_IRDA);
1475 * Function smsc_ircc_sir_receive (self)
1477 * Receive one frame from the infrared port
1480 static void smsc_ircc_sir_receive(struct smsc_ircc_cb *self)
1485 IRDA_ASSERT(self != NULL, return;);
1487 iobase = self->io.sir_base;
1490 * Receive all characters in Rx FIFO, unwrap and unstuff them.
1491 * async_unwrap_char will deliver all found frames
1494 async_unwrap_char(self->netdev, &self->netdev->stats, &self->rx_buff,
1495 inb(iobase + UART_RX));
1497 /* Make sure we don't stay here to long */
1498 if (boguscount++ > 32) {
1499 IRDA_DEBUG(2, "%s(), breaking!\n", __func__);
1502 } while (inb(iobase + UART_LSR) & UART_LSR_DR);
1507 * Function smsc_ircc_interrupt (irq, dev_id, regs)
1509 * An interrupt from the chip has arrived. Time to do some work
1512 static irqreturn_t smsc_ircc_interrupt(int dummy, void *dev_id)
1514 struct net_device *dev = dev_id;
1515 struct smsc_ircc_cb *self = netdev_priv(dev);
1516 int iobase, iir, lcra, lsr;
1517 irqreturn_t ret = IRQ_NONE;
1519 /* Serialise the interrupt handler in various CPUs, stop Tx path */
1520 spin_lock(&self->lock);
1522 /* Check if we should use the SIR interrupt handler */
1523 if (self->io.speed <= SMSC_IRCC2_MAX_SIR_SPEED) {
1524 ret = smsc_ircc_interrupt_sir(dev);
1525 goto irq_ret_unlock;
1528 iobase = self->io.fir_base;
1530 register_bank(iobase, 0);
1531 iir = inb(iobase + IRCC_IIR);
1533 goto irq_ret_unlock;
1536 /* Disable interrupts */
1537 outb(0, iobase + IRCC_IER);
1538 lcra = inb(iobase + IRCC_LCR_A);
1539 lsr = inb(iobase + IRCC_LSR);
1541 IRDA_DEBUG(2, "%s(), iir = 0x%02x\n", __func__, iir);
1543 if (iir & IRCC_IIR_EOM) {
1544 if (self->io.direction == IO_RECV)
1545 smsc_ircc_dma_receive_complete(self);
1547 smsc_ircc_dma_xmit_complete(self);
1549 smsc_ircc_dma_receive(self);
1552 if (iir & IRCC_IIR_ACTIVE_FRAME) {
1553 /*printk(KERN_WARNING "%s(): Active Frame\n", __func__);*/
1556 /* Enable interrupts again */
1558 register_bank(iobase, 0);
1559 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER);
1562 spin_unlock(&self->lock);
1568 * Function irport_interrupt_sir (irq, dev_id)
1570 * Interrupt handler for SIR modes
1572 static irqreturn_t smsc_ircc_interrupt_sir(struct net_device *dev)
1574 struct smsc_ircc_cb *self = netdev_priv(dev);
1579 /* Already locked coming here in smsc_ircc_interrupt() */
1580 /*spin_lock(&self->lock);*/
1582 iobase = self->io.sir_base;
1584 iir = inb(iobase + UART_IIR) & UART_IIR_ID;
1588 /* Clear interrupt */
1589 lsr = inb(iobase + UART_LSR);
1591 IRDA_DEBUG(4, "%s(), iir=%02x, lsr=%02x, iobase=%#x\n",
1592 __func__, iir, lsr, iobase);
1596 IRDA_DEBUG(2, "%s(), RLSI\n", __func__);
1599 /* Receive interrupt */
1600 smsc_ircc_sir_receive(self);
1603 if (lsr & UART_LSR_THRE)
1604 /* Transmitter ready for data */
1605 smsc_ircc_sir_write_wakeup(self);
1608 IRDA_DEBUG(0, "%s(), unhandled IIR=%#x\n",
1613 /* Make sure we don't stay here to long */
1614 if (boguscount++ > 100)
1617 iir = inb(iobase + UART_IIR) & UART_IIR_ID;
1619 /*spin_unlock(&self->lock);*/
1626 * Function ircc_is_receiving (self)
1628 * Return TRUE is we are currently receiving a frame
1631 static int ircc_is_receiving(struct smsc_ircc_cb *self)
1636 IRDA_DEBUG(1, "%s\n", __func__);
1638 IRDA_ASSERT(self != NULL, return FALSE;);
1640 IRDA_DEBUG(0, "%s: dma count = %d\n", __func__,
1641 get_dma_residue(self->io.dma));
1643 status = (self->rx_buff.state != OUTSIDE_FRAME);
1649 static int smsc_ircc_request_irq(struct smsc_ircc_cb *self)
1653 error = request_irq(self->io.irq, smsc_ircc_interrupt, 0,
1654 self->netdev->name, self->netdev);
1656 IRDA_DEBUG(0, "%s(), unable to allocate irq=%d, err=%d\n",
1657 __func__, self->io.irq, error);
1662 static void smsc_ircc_start_interrupts(struct smsc_ircc_cb *self)
1664 unsigned long flags;
1666 spin_lock_irqsave(&self->lock, flags);
1669 smsc_ircc_change_speed(self, SMSC_IRCC2_C_IRDA_FALLBACK_SPEED);
1671 spin_unlock_irqrestore(&self->lock, flags);
1674 static void smsc_ircc_stop_interrupts(struct smsc_ircc_cb *self)
1676 int iobase = self->io.fir_base;
1677 unsigned long flags;
1679 spin_lock_irqsave(&self->lock, flags);
1681 register_bank(iobase, 0);
1682 outb(0, iobase + IRCC_IER);
1683 outb(IRCC_MASTER_RESET, iobase + IRCC_MASTER);
1684 outb(0x00, iobase + IRCC_MASTER);
1686 spin_unlock_irqrestore(&self->lock, flags);
1691 * Function smsc_ircc_net_open (dev)
1696 static int smsc_ircc_net_open(struct net_device *dev)
1698 struct smsc_ircc_cb *self;
1701 IRDA_DEBUG(1, "%s\n", __func__);
1703 IRDA_ASSERT(dev != NULL, return -1;);
1704 self = netdev_priv(dev);
1705 IRDA_ASSERT(self != NULL, return 0;);
1707 if (self->io.suspended) {
1708 IRDA_DEBUG(0, "%s(), device is suspended\n", __func__);
1712 if (request_irq(self->io.irq, smsc_ircc_interrupt, 0, dev->name,
1714 IRDA_DEBUG(0, "%s(), unable to allocate irq=%d\n",
1715 __func__, self->io.irq);
1719 smsc_ircc_start_interrupts(self);
1721 /* Give self a hardware name */
1722 /* It would be cool to offer the chip revision here - Jean II */
1723 sprintf(hwname, "SMSC @ 0x%03x", self->io.fir_base);
1726 * Open new IrLAP layer instance, now that everything should be
1727 * initialized properly
1729 self->irlap = irlap_open(dev, &self->qos, hwname);
1732 * Always allocate the DMA channel after the IRQ,
1733 * and clean up on failure.
1735 if (request_dma(self->io.dma, dev->name)) {
1736 smsc_ircc_net_close(dev);
1738 IRDA_WARNING("%s(), unable to allocate DMA=%d\n",
1739 __func__, self->io.dma);
1743 netif_start_queue(dev);
1749 * Function smsc_ircc_net_close (dev)
1754 static int smsc_ircc_net_close(struct net_device *dev)
1756 struct smsc_ircc_cb *self;
1758 IRDA_DEBUG(1, "%s\n", __func__);
1760 IRDA_ASSERT(dev != NULL, return -1;);
1761 self = netdev_priv(dev);
1762 IRDA_ASSERT(self != NULL, return 0;);
1765 netif_stop_queue(dev);
1767 /* Stop and remove instance of IrLAP */
1769 irlap_close(self->irlap);
1772 smsc_ircc_stop_interrupts(self);
1774 /* if we are called from smsc_ircc_resume we don't have IRQ reserved */
1775 if (!self->io.suspended)
1776 free_irq(self->io.irq, dev);
1778 disable_dma(self->io.dma);
1779 free_dma(self->io.dma);
1784 static int smsc_ircc_suspend(struct platform_device *dev, pm_message_t state)
1786 struct smsc_ircc_cb *self = platform_get_drvdata(dev);
1788 if (!self->io.suspended) {
1789 IRDA_DEBUG(1, "%s, Suspending\n", driver_name);
1792 if (netif_running(self->netdev)) {
1793 netif_device_detach(self->netdev);
1794 smsc_ircc_stop_interrupts(self);
1795 free_irq(self->io.irq, self->netdev);
1796 disable_dma(self->io.dma);
1798 self->io.suspended = 1;
1805 static int smsc_ircc_resume(struct platform_device *dev)
1807 struct smsc_ircc_cb *self = platform_get_drvdata(dev);
1809 if (self->io.suspended) {
1810 IRDA_DEBUG(1, "%s, Waking up\n", driver_name);
1813 smsc_ircc_init_chip(self);
1814 if (netif_running(self->netdev)) {
1815 if (smsc_ircc_request_irq(self)) {
1817 * Don't fail resume process, just kill this
1820 unregister_netdevice(self->netdev);
1822 enable_dma(self->io.dma);
1823 smsc_ircc_start_interrupts(self);
1824 netif_device_attach(self->netdev);
1827 self->io.suspended = 0;
1834 * Function smsc_ircc_close (self)
1836 * Close driver instance
1839 static int __exit smsc_ircc_close(struct smsc_ircc_cb *self)
1841 IRDA_DEBUG(1, "%s\n", __func__);
1843 IRDA_ASSERT(self != NULL, return -1;);
1845 platform_device_unregister(self->pldev);
1847 /* Remove netdevice */
1848 unregister_netdev(self->netdev);
1850 smsc_ircc_stop_interrupts(self);
1852 /* Release the PORTS that this driver is using */
1853 IRDA_DEBUG(0, "%s(), releasing 0x%03x\n", __func__,
1856 release_region(self->io.fir_base, self->io.fir_ext);
1858 IRDA_DEBUG(0, "%s(), releasing 0x%03x\n", __func__,
1861 release_region(self->io.sir_base, self->io.sir_ext);
1863 if (self->tx_buff.head)
1864 dma_free_coherent(NULL, self->tx_buff.truesize,
1865 self->tx_buff.head, self->tx_buff_dma);
1867 if (self->rx_buff.head)
1868 dma_free_coherent(NULL, self->rx_buff.truesize,
1869 self->rx_buff.head, self->rx_buff_dma);
1871 free_netdev(self->netdev);
1876 static void __exit smsc_ircc_cleanup(void)
1880 IRDA_DEBUG(1, "%s\n", __func__);
1882 for (i = 0; i < 2; i++) {
1884 smsc_ircc_close(dev_self[i]);
1887 if (pnp_driver_registered)
1888 pnp_unregister_driver(&smsc_ircc_pnp_driver);
1890 platform_driver_unregister(&smsc_ircc_driver);
1894 * Start SIR operations
1896 * This function *must* be called with spinlock held, because it may
1897 * be called from the irq handler (via smsc_ircc_change_speed()). - Jean II
1899 static void smsc_ircc_sir_start(struct smsc_ircc_cb *self)
1901 struct net_device *dev;
1902 int fir_base, sir_base;
1904 IRDA_DEBUG(3, "%s\n", __func__);
1906 IRDA_ASSERT(self != NULL, return;);
1908 IRDA_ASSERT(dev != NULL, return;);
1910 fir_base = self->io.fir_base;
1911 sir_base = self->io.sir_base;
1913 /* Reset everything */
1914 outb(IRCC_MASTER_RESET, fir_base + IRCC_MASTER);
1916 #if SMSC_IRCC2_C_SIR_STOP
1917 /*smsc_ircc_sir_stop(self);*/
1920 register_bank(fir_base, 1);
1921 outb(((inb(fir_base + IRCC_SCE_CFGA) & IRCC_SCE_CFGA_BLOCK_CTRL_BITS_MASK) | IRCC_CFGA_IRDA_SIR_A), fir_base + IRCC_SCE_CFGA);
1923 /* Initialize UART */
1924 outb(UART_LCR_WLEN8, sir_base + UART_LCR); /* Reset DLAB */
1925 outb((UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2), sir_base + UART_MCR);
1927 /* Turn on interrups */
1928 outb(UART_IER_RLSI | UART_IER_RDI |UART_IER_THRI, sir_base + UART_IER);
1930 IRDA_DEBUG(3, "%s() - exit\n", __func__);
1932 outb(0x00, fir_base + IRCC_MASTER);
1935 #if SMSC_IRCC2_C_SIR_STOP
1936 void smsc_ircc_sir_stop(struct smsc_ircc_cb *self)
1940 IRDA_DEBUG(3, "%s\n", __func__);
1941 iobase = self->io.sir_base;
1944 outb(0, iobase + UART_MCR);
1946 /* Turn off interrupts */
1947 outb(0, iobase + UART_IER);
1952 * Function smsc_sir_write_wakeup (self)
1954 * Called by the SIR interrupt handler when there's room for more data.
1955 * If we have more packets to send, we send them here.
1958 static void smsc_ircc_sir_write_wakeup(struct smsc_ircc_cb *self)
1964 IRDA_ASSERT(self != NULL, return;);
1966 IRDA_DEBUG(4, "%s\n", __func__);
1968 iobase = self->io.sir_base;
1970 /* Finished with frame? */
1971 if (self->tx_buff.len > 0) {
1972 /* Write data left in transmit buffer */
1973 actual = smsc_ircc_sir_write(iobase, self->io.fifo_size,
1974 self->tx_buff.data, self->tx_buff.len);
1975 self->tx_buff.data += actual;
1976 self->tx_buff.len -= actual;
1979 /*if (self->tx_buff.len ==0) {*/
1982 * Now serial buffer is almost free & we can start
1983 * transmission of another packet. But first we must check
1984 * if we need to change the speed of the hardware
1986 if (self->new_speed) {
1987 IRDA_DEBUG(5, "%s(), Changing speed to %d.\n",
1988 __func__, self->new_speed);
1989 smsc_ircc_sir_wait_hw_transmitter_finish(self);
1990 smsc_ircc_change_speed(self, self->new_speed);
1991 self->new_speed = 0;
1993 /* Tell network layer that we want more frames */
1994 netif_wake_queue(self->netdev);
1996 self->netdev->stats.tx_packets++;
1998 if (self->io.speed <= 115200) {
2000 * Reset Rx FIFO to make sure that all reflected transmit data
2001 * is discarded. This is needed for half duplex operation
2003 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR;
2004 fcr |= self->io.speed < 38400 ?
2005 UART_FCR_TRIGGER_1 : UART_FCR_TRIGGER_14;
2007 outb(fcr, iobase + UART_FCR);
2009 /* Turn on receive interrupts */
2010 outb(UART_IER_RDI, iobase + UART_IER);
2016 * Function smsc_ircc_sir_write (iobase, fifo_size, buf, len)
2018 * Fill Tx FIFO with transmit data
2021 static int smsc_ircc_sir_write(int iobase, int fifo_size, __u8 *buf, int len)
2025 /* Tx FIFO should be empty! */
2026 if (!(inb(iobase + UART_LSR) & UART_LSR_THRE)) {
2027 IRDA_WARNING("%s(), failed, fifo not empty!\n", __func__);
2031 /* Fill FIFO with current frame */
2032 while (fifo_size-- > 0 && actual < len) {
2033 /* Transmit next byte */
2034 outb(buf[actual], iobase + UART_TX);
2041 * Function smsc_ircc_is_receiving (self)
2043 * Returns true is we are currently receiving data
2046 static int smsc_ircc_is_receiving(struct smsc_ircc_cb *self)
2048 return self->rx_buff.state != OUTSIDE_FRAME;
2053 * Function smsc_ircc_probe_transceiver(self)
2055 * Tries to find the used Transceiver
2058 static void smsc_ircc_probe_transceiver(struct smsc_ircc_cb *self)
2062 IRDA_ASSERT(self != NULL, return;);
2064 for (i = 0; smsc_transceivers[i].name != NULL; i++)
2065 if (smsc_transceivers[i].probe(self->io.fir_base)) {
2066 IRDA_MESSAGE(" %s transceiver found\n",
2067 smsc_transceivers[i].name);
2068 self->transceiver= i + 1;
2072 IRDA_MESSAGE("No transceiver found. Defaulting to %s\n",
2073 smsc_transceivers[SMSC_IRCC2_C_DEFAULT_TRANSCEIVER].name);
2075 self->transceiver = SMSC_IRCC2_C_DEFAULT_TRANSCEIVER;
2080 * Function smsc_ircc_set_transceiver_for_speed(self, speed)
2082 * Set the transceiver according to the speed
2085 static void smsc_ircc_set_transceiver_for_speed(struct smsc_ircc_cb *self, u32 speed)
2089 trx = self->transceiver;
2091 smsc_transceivers[trx - 1].set_for_speed(self->io.fir_base, speed);
2095 * Function smsc_ircc_wait_hw_transmitter_finish ()
2097 * Wait for the real end of HW transmission
2099 * The UART is a strict FIFO, and we get called only when we have finished
2100 * pushing data to the FIFO, so the maximum amount of time we must wait
2101 * is only for the FIFO to drain out.
2103 * We use a simple calibrated loop. We may need to adjust the loop
2104 * delay (udelay) to balance I/O traffic and latency. And we also need to
2105 * adjust the maximum timeout.
2106 * It would probably be better to wait for the proper interrupt,
2107 * but it doesn't seem to be available.
2109 * We can't use jiffies or kernel timers because :
2110 * 1) We are called from the interrupt handler, which disable softirqs,
2111 * so jiffies won't be increased
2112 * 2) Jiffies granularity is usually very coarse (10ms), and we don't
2113 * want to wait that long to detect stuck hardware.
2117 static void smsc_ircc_sir_wait_hw_transmitter_finish(struct smsc_ircc_cb *self)
2119 int iobase = self->io.sir_base;
2120 int count = SMSC_IRCC2_HW_TRANSMITTER_TIMEOUT_US;
2122 /* Calibrated busy loop */
2123 while (count-- > 0 && !(inb(iobase + UART_LSR) & UART_LSR_TEMT))
2127 IRDA_DEBUG(0, "%s(): stuck transmitter\n", __func__);
2133 * REVISIT we can be told about the device by PNP, and should use that info
2134 * instead of probing hardware and creating a platform_device ...
2137 static int __init smsc_ircc_look_for_chips(void)
2139 struct smsc_chip_address *address;
2141 unsigned int cfg_base, found;
2144 address = possible_addresses;
2146 while (address->cfg_base) {
2147 cfg_base = address->cfg_base;
2149 /*printk(KERN_WARNING "%s(): probing: 0x%02x for: 0x%02x\n", __func__, cfg_base, address->type);*/
2151 if (address->type & SMSCSIO_TYPE_FDC) {
2153 if (address->type & SMSCSIO_TYPE_FLAT)
2154 if (!smsc_superio_flat(fdc_chips_flat, cfg_base, type))
2157 if (address->type & SMSCSIO_TYPE_PAGED)
2158 if (!smsc_superio_paged(fdc_chips_paged, cfg_base, type))
2161 if (address->type & SMSCSIO_TYPE_LPC) {
2163 if (address->type & SMSCSIO_TYPE_FLAT)
2164 if (!smsc_superio_flat(lpc_chips_flat, cfg_base, type))
2167 if (address->type & SMSCSIO_TYPE_PAGED)
2168 if (!smsc_superio_paged(lpc_chips_paged, cfg_base, type))
2177 * Function smsc_superio_flat (chip, base, type)
2179 * Try to get configuration of a smc SuperIO chip with flat register model
2182 static int __init smsc_superio_flat(const struct smsc_chip *chips, unsigned short cfgbase, char *type)
2184 unsigned short firbase, sirbase;
2188 IRDA_DEBUG(1, "%s\n", __func__);
2190 if (smsc_ircc_probe(cfgbase, SMSCSIOFLAT_DEVICEID_REG, chips, type) == NULL)
2193 outb(SMSCSIOFLAT_UARTMODE0C_REG, cfgbase);
2194 mode = inb(cfgbase + 1);
2196 /*printk(KERN_WARNING "%s(): mode: 0x%02x\n", __func__, mode);*/
2198 if (!(mode & SMSCSIOFLAT_UART2MODE_VAL_IRDA))
2199 IRDA_WARNING("%s(): IrDA not enabled\n", __func__);
2201 outb(SMSCSIOFLAT_UART2BASEADDR_REG, cfgbase);
2202 sirbase = inb(cfgbase + 1) << 2;
2205 outb(SMSCSIOFLAT_FIRBASEADDR_REG, cfgbase);
2206 firbase = inb(cfgbase + 1) << 3;
2209 outb(SMSCSIOFLAT_FIRDMASELECT_REG, cfgbase);
2210 dma = inb(cfgbase + 1) & SMSCSIOFLAT_FIRDMASELECT_MASK;
2213 outb(SMSCSIOFLAT_UARTIRQSELECT_REG, cfgbase);
2214 irq = inb(cfgbase + 1) & SMSCSIOFLAT_UART2IRQSELECT_MASK;
2216 IRDA_MESSAGE("%s(): fir: 0x%02x, sir: 0x%02x, dma: %02d, irq: %d, mode: 0x%02x\n", __func__, firbase, sirbase, dma, irq, mode);
2218 if (firbase && smsc_ircc_open(firbase, sirbase, dma, irq) == 0)
2221 /* Exit configuration */
2222 outb(SMSCSIO_CFGEXITKEY, cfgbase);
2228 * Function smsc_superio_paged (chip, base, type)
2230 * Try to get configuration of a smc SuperIO chip with paged register model
2233 static int __init smsc_superio_paged(const struct smsc_chip *chips, unsigned short cfg_base, char *type)
2235 unsigned short fir_io, sir_io;
2238 IRDA_DEBUG(1, "%s\n", __func__);
2240 if (smsc_ircc_probe(cfg_base, 0x20, chips, type) == NULL)
2243 /* Select logical device (UART2) */
2244 outb(0x07, cfg_base);
2245 outb(0x05, cfg_base + 1);
2248 outb(0x60, cfg_base);
2249 sir_io = inb(cfg_base + 1) << 8;
2250 outb(0x61, cfg_base);
2251 sir_io |= inb(cfg_base + 1);
2254 outb(0x62, cfg_base);
2255 fir_io = inb(cfg_base + 1) << 8;
2256 outb(0x63, cfg_base);
2257 fir_io |= inb(cfg_base + 1);
2258 outb(0x2b, cfg_base); /* ??? */
2260 if (fir_io && smsc_ircc_open(fir_io, sir_io, ircc_dma, ircc_irq) == 0)
2263 /* Exit configuration */
2264 outb(SMSCSIO_CFGEXITKEY, cfg_base);
2270 static int __init smsc_access(unsigned short cfg_base, unsigned char reg)
2272 IRDA_DEBUG(1, "%s\n", __func__);
2274 outb(reg, cfg_base);
2275 return inb(cfg_base) != reg ? -1 : 0;
2278 static const struct smsc_chip * __init smsc_ircc_probe(unsigned short cfg_base, u8 reg, const struct smsc_chip *chip, char *type)
2280 u8 devid, xdevid, rev;
2282 IRDA_DEBUG(1, "%s\n", __func__);
2284 /* Leave configuration */
2286 outb(SMSCSIO_CFGEXITKEY, cfg_base);
2288 if (inb(cfg_base) == SMSCSIO_CFGEXITKEY) /* not a smc superio chip */
2291 outb(reg, cfg_base);
2293 xdevid = inb(cfg_base + 1);
2295 /* Enter configuration */
2297 outb(SMSCSIO_CFGACCESSKEY, cfg_base);
2300 if (smsc_access(cfg_base,0x55)) /* send second key and check */
2304 /* probe device ID */
2306 if (smsc_access(cfg_base, reg))
2309 devid = inb(cfg_base + 1);
2311 if (devid == 0 || devid == 0xff) /* typical values for unused port */
2314 /* probe revision ID */
2316 if (smsc_access(cfg_base, reg + 1))
2319 rev = inb(cfg_base + 1);
2321 if (rev >= 128) /* i think this will make no sense */
2324 if (devid == xdevid) /* protection against false positives */
2327 /* Check for expected device ID; are there others? */
2329 while (chip->devid != devid) {
2333 if (chip->name == NULL)
2337 IRDA_MESSAGE("found SMC SuperIO Chip (devid=0x%02x rev=%02X base=0x%04x): %s%s\n",
2338 devid, rev, cfg_base, type, chip->name);
2340 if (chip->rev > rev) {
2341 IRDA_MESSAGE("Revision higher than expected\n");
2345 if (chip->flags & NoIRDA)
2346 IRDA_MESSAGE("chipset does not support IRDA\n");
2351 static int __init smsc_superio_fdc(unsigned short cfg_base)
2355 if (!request_region(cfg_base, 2, driver_name)) {
2356 IRDA_WARNING("%s: can't get cfg_base of 0x%03x\n",
2357 __func__, cfg_base);
2359 if (!smsc_superio_flat(fdc_chips_flat, cfg_base, "FDC") ||
2360 !smsc_superio_paged(fdc_chips_paged, cfg_base, "FDC"))
2363 release_region(cfg_base, 2);
2369 static int __init smsc_superio_lpc(unsigned short cfg_base)
2373 if (!request_region(cfg_base, 2, driver_name)) {
2374 IRDA_WARNING("%s: can't get cfg_base of 0x%03x\n",
2375 __func__, cfg_base);
2377 if (!smsc_superio_flat(lpc_chips_flat, cfg_base, "LPC") ||
2378 !smsc_superio_paged(lpc_chips_paged, cfg_base, "LPC"))
2381 release_region(cfg_base, 2);
2387 * Look for some specific subsystem setups that need
2388 * pre-configuration not properly done by the BIOS (especially laptops)
2389 * This code is based in part on smcinit.c, tosh1800-smcinit.c
2390 * and tosh2450-smcinit.c. The table lists the device entries
2391 * for ISA bridges with an LPC (Low Pin Count) controller which
2392 * handles the communication with the SMSC device. After the LPC
2393 * controller is initialized through PCI, the SMSC device is initialized
2394 * through a dedicated port in the ISA port-mapped I/O area, this latter
2395 * area is used to configure the SMSC device with default
2396 * SIR and FIR I/O ports, DMA and IRQ. Different vendors have
2397 * used different sets of parameters and different control port
2398 * addresses making a subsystem device table necessary.
2401 static struct smsc_ircc_subsystem_configuration subsystem_configurations[] __initdata = {
2403 * Subsystems needing entries:
2404 * 0x10b9:0x1533 0x103c:0x0850 HP nx9010 family
2405 * 0x10b9:0x1533 0x0e11:0x005a Compaq nc4000 family
2406 * 0x8086:0x24cc 0x0e11:0x002a HP nx9000 family
2410 .vendor = PCI_VENDOR_ID_INTEL, /* Intel 82801DBM LPC bridge */
2412 .subvendor = 0x103c,
2413 .subdevice = 0x08bc,
2419 .preconfigure = preconfigure_through_82801,
2420 .name = "HP nx5000 family",
2423 .vendor = PCI_VENDOR_ID_INTEL, /* Intel 82801DBM LPC bridge */
2425 .subvendor = 0x103c,
2426 .subdevice = 0x088c,
2427 /* Quite certain these are the same for nc8000 as for nc6000 */
2433 .preconfigure = preconfigure_through_82801,
2434 .name = "HP nc8000 family",
2437 .vendor = PCI_VENDOR_ID_INTEL, /* Intel 82801DBM LPC bridge */
2439 .subvendor = 0x103c,
2440 .subdevice = 0x0890,
2446 .preconfigure = preconfigure_through_82801,
2447 .name = "HP nc6000 family",
2450 .vendor = PCI_VENDOR_ID_INTEL, /* Intel 82801DBM LPC bridge */
2452 .subvendor = 0x0e11,
2453 .subdevice = 0x0860,
2454 /* I assume these are the same for x1000 as for the others */
2460 .preconfigure = preconfigure_through_82801,
2461 .name = "Compaq x1000 family",
2464 /* Intel 82801DB/DBL (ICH4/ICH4-L) LPC Interface Bridge */
2465 .vendor = PCI_VENDOR_ID_INTEL,
2467 .subvendor = 0x1179,
2468 .subdevice = 0xffff, /* 0xffff is "any" */
2474 .preconfigure = preconfigure_through_82801,
2475 .name = "Toshiba laptop with Intel 82801DB/DBL LPC bridge",
2478 .vendor = PCI_VENDOR_ID_INTEL, /* Intel 82801CAM ISA bridge */
2480 .subvendor = 0x1179,
2481 .subdevice = 0xffff, /* 0xffff is "any" */
2487 .preconfigure = preconfigure_through_82801,
2488 .name = "Toshiba laptop with Intel 82801CAM ISA bridge",
2491 /* 82801DBM (ICH4-M) LPC Interface Bridge */
2492 .vendor = PCI_VENDOR_ID_INTEL,
2494 .subvendor = 0x1179,
2495 .subdevice = 0xffff, /* 0xffff is "any" */
2501 .preconfigure = preconfigure_through_82801,
2502 .name = "Toshiba laptop with Intel 8281DBM LPC bridge",
2505 /* ALi M1533/M1535 PCI to ISA Bridge [Aladdin IV/V/V+] */
2506 .vendor = PCI_VENDOR_ID_AL,
2508 .subvendor = 0x1179,
2509 .subdevice = 0xffff, /* 0xffff is "any" */
2515 .preconfigure = preconfigure_through_ali,
2516 .name = "Toshiba laptop with ALi ISA bridge",
2523 * This sets up the basic SMSC parameters
2524 * (FIR port, SIR port, FIR DMA, FIR IRQ)
2525 * through the chip configuration port.
2527 static int __init preconfigure_smsc_chip(struct
2528 smsc_ircc_subsystem_configuration
2531 unsigned short iobase = conf->cfg_base;
2532 unsigned char tmpbyte;
2534 outb(LPC47N227_CFGACCESSKEY, iobase); // enter configuration state
2535 outb(SMSCSIOFLAT_DEVICEID_REG, iobase); // set for device ID
2536 tmpbyte = inb(iobase +1); // Read device ID
2538 "Detected Chip id: 0x%02x, setting up registers...\n",
2541 /* Disable UART1 and set up SIR I/O port */
2542 outb(0x24, iobase); // select CR24 - UART1 base addr
2543 outb(0x00, iobase + 1); // disable UART1
2544 outb(SMSCSIOFLAT_UART2BASEADDR_REG, iobase); // select CR25 - UART2 base addr
2545 outb( (conf->sir_io >> 2), iobase + 1); // bits 2-9 of 0x3f8
2546 tmpbyte = inb(iobase + 1);
2547 if (tmpbyte != (conf->sir_io >> 2) ) {
2548 IRDA_WARNING("ERROR: could not configure SIR ioport.\n");
2549 IRDA_WARNING("Try to supply ircc_cfg argument.\n");
2553 /* Set up FIR IRQ channel for UART2 */
2554 outb(SMSCSIOFLAT_UARTIRQSELECT_REG, iobase); // select CR28 - UART1,2 IRQ select
2555 tmpbyte = inb(iobase + 1);
2556 tmpbyte &= SMSCSIOFLAT_UART1IRQSELECT_MASK; // Do not touch the UART1 portion
2557 tmpbyte |= (conf->fir_irq & SMSCSIOFLAT_UART2IRQSELECT_MASK);
2558 outb(tmpbyte, iobase + 1);
2559 tmpbyte = inb(iobase + 1) & SMSCSIOFLAT_UART2IRQSELECT_MASK;
2560 if (tmpbyte != conf->fir_irq) {
2561 IRDA_WARNING("ERROR: could not configure FIR IRQ channel.\n");
2565 /* Set up FIR I/O port */
2566 outb(SMSCSIOFLAT_FIRBASEADDR_REG, iobase); // CR2B - SCE (FIR) base addr
2567 outb((conf->fir_io >> 3), iobase + 1);
2568 tmpbyte = inb(iobase + 1);
2569 if (tmpbyte != (conf->fir_io >> 3) ) {
2570 IRDA_WARNING("ERROR: could not configure FIR I/O port.\n");
2574 /* Set up FIR DMA channel */
2575 outb(SMSCSIOFLAT_FIRDMASELECT_REG, iobase); // CR2C - SCE (FIR) DMA select
2576 outb((conf->fir_dma & LPC47N227_FIRDMASELECT_MASK), iobase + 1); // DMA
2577 tmpbyte = inb(iobase + 1) & LPC47N227_FIRDMASELECT_MASK;
2578 if (tmpbyte != (conf->fir_dma & LPC47N227_FIRDMASELECT_MASK)) {
2579 IRDA_WARNING("ERROR: could not configure FIR DMA channel.\n");
2583 outb(SMSCSIOFLAT_UARTMODE0C_REG, iobase); // CR0C - UART mode
2584 tmpbyte = inb(iobase + 1);
2585 tmpbyte &= ~SMSCSIOFLAT_UART2MODE_MASK |
2586 SMSCSIOFLAT_UART2MODE_VAL_IRDA;
2587 outb(tmpbyte, iobase + 1); // enable IrDA (HPSIR) mode, high speed
2589 outb(LPC47N227_APMBOOTDRIVE_REG, iobase); // CR07 - Auto Pwr Mgt/boot drive sel
2590 tmpbyte = inb(iobase + 1);
2591 outb(tmpbyte | LPC47N227_UART2AUTOPWRDOWN_MASK, iobase + 1); // enable UART2 autopower down
2593 /* This one was not part of tosh1800 */
2594 outb(0x0a, iobase); // CR0a - ecp fifo / ir mux
2595 tmpbyte = inb(iobase + 1);
2596 outb(tmpbyte | 0x40, iobase + 1); // send active device to ir port
2598 outb(LPC47N227_UART12POWER_REG, iobase); // CR02 - UART 1,2 power
2599 tmpbyte = inb(iobase + 1);
2600 outb(tmpbyte | LPC47N227_UART2POWERDOWN_MASK, iobase + 1); // UART2 power up mode, UART1 power down
2602 outb(LPC47N227_FDCPOWERVALIDCONF_REG, iobase); // CR00 - FDC Power/valid config cycle
2603 tmpbyte = inb(iobase + 1);
2604 outb(tmpbyte | LPC47N227_VALID_MASK, iobase + 1); // valid config cycle done
2606 outb(LPC47N227_CFGEXITKEY, iobase); // Exit configuration
2611 /* 82801CAM generic registers */
2614 #define PIRQ_A_D_ROUT 0x60
2615 #define SIRQ_CNTL 0x64
2616 #define PIRQ_E_H_ROUT 0x68
2617 #define PCI_DMA_C 0x90
2618 /* LPC-specific registers */
2619 #define COM_DEC 0xe0
2620 #define GEN1_DEC 0xe4
2622 #define GEN2_DEC 0xec
2624 * Sets up the I/O range using the 82801CAM ISA bridge, 82801DBM LPC bridge
2625 * or Intel 82801DB/DBL (ICH4/ICH4-L) LPC Interface Bridge.
2626 * They all work the same way!
2628 static int __init preconfigure_through_82801(struct pci_dev *dev,
2630 smsc_ircc_subsystem_configuration
2633 unsigned short tmpword;
2634 unsigned char tmpbyte;
2636 IRDA_MESSAGE("Setting up Intel 82801 controller and SMSC device\n");
2638 * Select the range for the COMA COM port (SIR)
2641 * Bit 6-4, COMB decode range
2643 * Bit 2-0, COMA decode range
2646 * 000 = 0x3f8-0x3ff (COM1)
2647 * 001 = 0x2f8-0x2ff (COM2)
2651 * 101 = 0x2e8-0x2ef (COM4)
2653 * 111 = 0x3e8-0x3ef (COM3)
2655 pci_read_config_byte(dev, COM_DEC, &tmpbyte);
2656 tmpbyte &= 0xf8; /* mask COMA bits */
2657 switch(conf->sir_io) {
2683 tmpbyte |= 0x01; /* COM2 default */
2685 IRDA_DEBUG(1, "COM_DEC (write): 0x%02x\n", tmpbyte);
2686 pci_write_config_byte(dev, COM_DEC, tmpbyte);
2688 /* Enable Low Pin Count interface */
2689 pci_read_config_word(dev, LPC_EN, &tmpword);
2690 /* These seem to be set up at all times,
2691 * just make sure it is properly set.
2693 switch(conf->cfg_base) {
2707 IRDA_WARNING("Uncommon I/O base address: 0x%04x\n",
2711 tmpword &= 0xfffd; /* disable LPC COMB */
2712 tmpword |= 0x0001; /* set bit 0 : enable LPC COMA addr range (GEN2) */
2713 IRDA_DEBUG(1, "LPC_EN (write): 0x%04x\n", tmpword);
2714 pci_write_config_word(dev, LPC_EN, tmpword);
2717 * Configure LPC DMA channel
2719 * Bit 15-14: DMA channel 7 select
2720 * Bit 13-12: DMA channel 6 select
2721 * Bit 11-10: DMA channel 5 select
2723 * Bit 7-6: DMA channel 3 select
2724 * Bit 5-4: DMA channel 2 select
2725 * Bit 3-2: DMA channel 1 select
2726 * Bit 1-0: DMA channel 0 select
2727 * 00 = Reserved value
2729 * 10 = Reserved value
2732 pci_read_config_word(dev, PCI_DMA_C, &tmpword);
2733 switch(conf->fir_dma) {
2756 break; /* do not change settings */
2758 IRDA_DEBUG(1, "PCI_DMA_C (write): 0x%04x\n", tmpword);
2759 pci_write_config_word(dev, PCI_DMA_C, tmpword);
2763 * Bit 15-4: Generic I/O range
2764 * Bit 3-1: reserved (read as 0)
2765 * Bit 0: enable GEN2 range on LPC I/F
2767 tmpword = conf->fir_io & 0xfff8;
2769 IRDA_DEBUG(1, "GEN2_DEC (write): 0x%04x\n", tmpword);
2770 pci_write_config_word(dev, GEN2_DEC, tmpword);
2772 /* Pre-configure chip */
2773 return preconfigure_smsc_chip(conf);
2777 * Pre-configure a certain port on the ALi 1533 bridge.
2778 * This is based on reverse-engineering since ALi does not
2779 * provide any data sheet for the 1533 chip.
2781 static void __init preconfigure_ali_port(struct pci_dev *dev,
2782 unsigned short port)
2785 /* These bits obviously control the different ports */
2787 unsigned char tmpbyte;
2808 IRDA_ERROR("Failed to configure unsupported port on ALi 1533 bridge: 0x%04x\n", port);
2812 pci_read_config_byte(dev, reg, &tmpbyte);
2813 /* Turn on the right bits */
2815 pci_write_config_byte(dev, reg, tmpbyte);
2816 IRDA_MESSAGE("Activated ALi 1533 ISA bridge port 0x%04x.\n", port);
2819 static int __init preconfigure_through_ali(struct pci_dev *dev,
2821 smsc_ircc_subsystem_configuration
2824 /* Configure the two ports on the ALi 1533 */
2825 preconfigure_ali_port(dev, conf->sir_io);
2826 preconfigure_ali_port(dev, conf->fir_io);
2828 /* Pre-configure chip */
2829 return preconfigure_smsc_chip(conf);
2832 static int __init smsc_ircc_preconfigure_subsystems(unsigned short ircc_cfg,
2833 unsigned short ircc_fir,
2834 unsigned short ircc_sir,
2835 unsigned char ircc_dma,
2836 unsigned char ircc_irq)
2838 struct pci_dev *dev = NULL;
2839 unsigned short ss_vendor = 0x0000;
2840 unsigned short ss_device = 0x0000;
2843 for_each_pci_dev(dev) {
2844 struct smsc_ircc_subsystem_configuration *conf;
2847 * Cache the subsystem vendor/device:
2848 * some manufacturers fail to set this for all components,
2849 * so we save it in case there is just 0x0000 0x0000 on the
2850 * device we want to check.
2852 if (dev->subsystem_vendor != 0x0000U) {
2853 ss_vendor = dev->subsystem_vendor;
2854 ss_device = dev->subsystem_device;
2856 conf = subsystem_configurations;
2857 for( ; conf->subvendor; conf++) {
2858 if(conf->vendor == dev->vendor &&
2859 conf->device == dev->device &&
2860 conf->subvendor == ss_vendor &&
2861 /* Sometimes these are cached values */
2862 (conf->subdevice == ss_device ||
2863 conf->subdevice == 0xffff)) {
2864 struct smsc_ircc_subsystem_configuration
2867 memcpy(&tmpconf, conf,
2868 sizeof(struct smsc_ircc_subsystem_configuration));
2871 * Override the default values with anything
2872 * passed in as parameter
2875 tmpconf.cfg_base = ircc_cfg;
2877 tmpconf.fir_io = ircc_fir;
2879 tmpconf.sir_io = ircc_sir;
2880 if (ircc_dma != DMA_INVAL)
2881 tmpconf.fir_dma = ircc_dma;
2882 if (ircc_irq != IRQ_INVAL)
2883 tmpconf.fir_irq = ircc_irq;
2885 IRDA_MESSAGE("Detected unconfigured %s SMSC IrDA chip, pre-configuring device.\n", conf->name);
2886 if (conf->preconfigure)
2887 ret = conf->preconfigure(dev, &tmpconf);
2896 #endif // CONFIG_PCI
2898 /************************************************
2900 * Transceivers specific functions
2902 ************************************************/
2906 * Function smsc_ircc_set_transceiver_smsc_ircc_atc(fir_base, speed)
2908 * Program transceiver through smsc-ircc ATC circuitry
2912 static void smsc_ircc_set_transceiver_smsc_ircc_atc(int fir_base, u32 speed)
2914 unsigned long jiffies_now, jiffies_timeout;
2917 jiffies_now = jiffies;
2918 jiffies_timeout = jiffies + SMSC_IRCC2_ATC_PROGRAMMING_TIMEOUT_JIFFIES;
2921 register_bank(fir_base, 4);
2922 outb((inb(fir_base + IRCC_ATC) & IRCC_ATC_MASK) | IRCC_ATC_nPROGREADY|IRCC_ATC_ENABLE,
2923 fir_base + IRCC_ATC);
2925 while ((val = (inb(fir_base + IRCC_ATC) & IRCC_ATC_nPROGREADY)) &&
2926 !time_after(jiffies, jiffies_timeout))
2930 IRDA_WARNING("%s(): ATC: 0x%02x\n", __func__,
2931 inb(fir_base + IRCC_ATC));
2935 * Function smsc_ircc_probe_transceiver_smsc_ircc_atc(fir_base)
2937 * Probe transceiver smsc-ircc ATC circuitry
2941 static int smsc_ircc_probe_transceiver_smsc_ircc_atc(int fir_base)
2947 * Function smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(self, speed)
2953 static void smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(int fir_base, u32 speed)
2964 fast_mode = IRCC_LCR_A_FAST;
2967 register_bank(fir_base, 0);
2968 outb((inb(fir_base + IRCC_LCR_A) & 0xbf) | fast_mode, fir_base + IRCC_LCR_A);
2972 * Function smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(fir_base)
2978 static int smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(int fir_base)
2984 * Function smsc_ircc_set_transceiver_toshiba_sat1800(fir_base, speed)
2990 static void smsc_ircc_set_transceiver_toshiba_sat1800(int fir_base, u32 speed)
3001 fast_mode = /*IRCC_LCR_A_FAST |*/ IRCC_LCR_A_GP_DATA;
3005 /* This causes an interrupt */
3006 register_bank(fir_base, 0);
3007 outb((inb(fir_base + IRCC_LCR_A) & 0xbf) | fast_mode, fir_base + IRCC_LCR_A);
3011 * Function smsc_ircc_probe_transceiver_toshiba_sat1800(fir_base)
3017 static int smsc_ircc_probe_transceiver_toshiba_sat1800(int fir_base)
3023 module_init(smsc_ircc_init);
3024 module_exit(smsc_ircc_cleanup);