drivers/net/ixgbe/ixgbe_main.c

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2009 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #include <linux/types.h>
  29 #include <linux/module.h>
  30 #include <linux/pci.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/vmalloc.h>
  33 #include <linux/string.h>
  34 #include <linux/in.h>
  35 #include <linux/ip.h>
  36 #include <linux/tcp.h>
  37 #include <linux/ipv6.h>
  38 #include <net/checksum.h>
  39 #include <net/ip6_checksum.h>
  40 #include <linux/ethtool.h>
  41 #include <linux/if_vlan.h>
  42
  43 #include "ixgbe.h"
  44 #include "ixgbe_common.h"
  45
  46 char ixgbe_driver_name[] = "ixgbe";
  47 static const char ixgbe_driver_string[] =
  48                               "Intel(R) 10 Gigabit PCI Express Network Driver";
  49
  50 #define DRV_VERSION "1.3.56-k2"
  51 const char ixgbe_driver_version[] = DRV_VERSION;
  52 static char ixgbe_copyright[] = "Copyright (c) 1999-2009 Intel Corporation.";
  53
  54 static const struct ixgbe_info *ixgbe_info_tbl[] = {
  55         [board_82598] = &ixgbe_82598_info,
  56 };
  57
  58 /* ixgbe_pci_tbl - PCI Device ID Table
  59  *
  60  * Wildcard entries (PCI_ANY_ID) should come last
  61  * Last entry must be all 0s
  62  *
  63  * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
  64  *   Class, Class Mask, private data (not used) }
  65  */
  66 static struct pci_device_id ixgbe_pci_tbl[] = {
  67         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
  68          board_82598 },
  69         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
  70          board_82598 },
  71         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
  72          board_82598 },
  73         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
  74          board_82598 },
  75         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
  76          board_82598 },
  77         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
  78          board_82598 },
  79         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
  80          board_82598 },
  81         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
  82          board_82598 },
  83         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
  84          board_82598 },
  85         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
  86          board_82598 },
  87         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
  88          board_82598 },
  89
  90         /* required last entry */
  91         {0, }
  92 };
  93 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
  94
  95 #ifdef CONFIG_IXGBE_DCA
  96 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
  97                             void *p);
  98 static struct notifier_block dca_notifier = {
  99         .notifier_call = ixgbe_notify_dca,
 100         .next          = NULL,
 101         .priority      = 0
 102 };
 103 #endif
 104
 105 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
 106 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
 107 MODULE_LICENSE("GPL");
 108 MODULE_VERSION(DRV_VERSION);
 109
 110 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
 111
 112 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
 113 {
 114         u32 ctrl_ext;
 115
 116         /* Let firmware take over control of h/w */
 117         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 118         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 119                         ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
 120 }
 121
 122 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
 123 {
 124         u32 ctrl_ext;
 125
 126         /* Let firmware know the driver has taken over */
 127         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 128         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 129                         ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
 130 }
 131
 132 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, u16 int_alloc_entry,
 133                            u8 msix_vector)
 134 {
 135         u32 ivar, index;
 136
 137         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 138         index = (int_alloc_entry >> 2) & 0x1F;
 139         ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR(index));
 140         ivar &= ~(0xFF << (8 * (int_alloc_entry & 0x3)));
 141         ivar |= (msix_vector << (8 * (int_alloc_entry & 0x3)));
 142         IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR(index), ivar);
 143 }
 144
 145 static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
 146                                              struct ixgbe_tx_buffer
 147                                              *tx_buffer_info)
 148 {
 149         if (tx_buffer_info->dma) {
 150                 pci_unmap_page(adapter->pdev, tx_buffer_info->dma,
 151                                tx_buffer_info->length, PCI_DMA_TODEVICE);
 152                 tx_buffer_info->dma = 0;
 153         }
 154         if (tx_buffer_info->skb) {
 155                 dev_kfree_skb_any(tx_buffer_info->skb);
 156                 tx_buffer_info->skb = NULL;
 157         }
 158         /* tx_buffer_info must be completely set up in the transmit path */
 159 }
 160
 161 static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
 162                                        struct ixgbe_ring *tx_ring,
 163                                        unsigned int eop)
 164 {
 165         struct ixgbe_hw *hw = &adapter->hw;
 166         u32 head, tail;
 167
 168         /* Detect a transmit hang in hardware, this serializes the
 169          * check with the clearing of time_stamp and movement of eop */
 170         head = IXGBE_READ_REG(hw, tx_ring->head);
 171         tail = IXGBE_READ_REG(hw, tx_ring->tail);
 172         adapter->detect_tx_hung = false;
 173         if ((head != tail) &&
 174             tx_ring->tx_buffer_info[eop].time_stamp &&
 175             time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
 176             !(IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & IXGBE_TFCS_TXOFF)) {
 177                 /* detected Tx unit hang */
 178                 union ixgbe_adv_tx_desc *tx_desc;
 179                 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
 180                 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
 181                         "  Tx Queue             <%d>\n"
 182                         "  TDH, TDT             <%x>, <%x>\n"
 183                         "  next_to_use          <%x>\n"
 184                         "  next_to_clean        <%x>\n"
 185                         "tx_buffer_info[next_to_clean]\n"
 186                         "  time_stamp           <%lx>\n"
 187                         "  jiffies              <%lx>\n",
 188                         tx_ring->queue_index,
 189                         head, tail,
 190                         tx_ring->next_to_use, eop,
 191                         tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
 192                 return true;
 193         }
 194
 195         return false;
 196 }
 197
 198 #define IXGBE_MAX_TXD_PWR       14
 199 #define IXGBE_MAX_DATA_PER_TXD  (1 << IXGBE_MAX_TXD_PWR)
 200
 201 /* Tx Descriptors needed, worst case */
 202 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
 203                          (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
 204 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
 205         MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
 206
 207 static void ixgbe_tx_timeout(struct net_device *netdev);
 208
 209 /**
 210  * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
 211  * @adapter: board private structure
 212  * @tx_ring: tx ring to clean
 213  **/
 214 static bool ixgbe_clean_tx_irq(struct ixgbe_adapter *adapter,
 215                                struct ixgbe_ring *tx_ring)
 216 {
 217         struct net_device *netdev = adapter->netdev;
 218         union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
 219         struct ixgbe_tx_buffer *tx_buffer_info;
 220         unsigned int i, eop, count = 0;
 221         unsigned int total_bytes = 0, total_packets = 0;
 222
 223         i = tx_ring->next_to_clean;
 224         eop = tx_ring->tx_buffer_info[i].next_to_watch;
 225         eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
 226
 227         while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
 228                (count < tx_ring->count)) {
 229                 bool cleaned = false;
 230                 for ( ; !cleaned; count++) {
 231                         struct sk_buff *skb;
 232                         tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
 233                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
 234                         cleaned = (i == eop);
 235                         skb = tx_buffer_info->skb;
 236
 237                         if (cleaned && skb) {
 238                                 unsigned int segs, bytecount;
 239
 240                                 /* gso_segs is currently only valid for tcp */
 241                                 segs = skb_shinfo(skb)->gso_segs ?: 1;
 242                                 /* multiply data chunks by size of headers */
 243                                 bytecount = ((segs - 1) * skb_headlen(skb)) +
 244                                             skb->len;
 245                                 total_packets += segs;
 246                                 total_bytes += bytecount;
 247                         }
 248
 249                         ixgbe_unmap_and_free_tx_resource(adapter,
 250                                                          tx_buffer_info);
 251
 252                         tx_desc->wb.status = 0;
 253
 254                         i++;
 255                         if (i == tx_ring->count)
 256                                 i = 0;
 257                 }
 258
 259                 eop = tx_ring->tx_buffer_info[i].next_to_watch;
 260                 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
 261         }
 262
 263         tx_ring->next_to_clean = i;
 264
 265 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
 266         if (unlikely(count && netif_carrier_ok(netdev) &&
 267                      (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
 268                 /* Make sure that anybody stopping the queue after this
 269                  * sees the new next_to_clean.
 270                  */
 271                 smp_mb();
 272                 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
 273                     !test_bit(__IXGBE_DOWN, &adapter->state)) {
 274                         netif_wake_subqueue(netdev, tx_ring->queue_index);
 275                         ++adapter->restart_queue;
 276                 }
 277         }
 278
 279         if (adapter->detect_tx_hung) {
 280                 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
 281                         /* schedule immediate reset if we believe we hung */
 282                         DPRINTK(PROBE, INFO,
 283                                 "tx hang %d detected, resetting adapter\n",
 284                                 adapter->tx_timeout_count + 1);
 285                         ixgbe_tx_timeout(adapter->netdev);
 286                 }
 287         }
 288
 289         /* re-arm the interrupt */
 290         if ((total_packets >= tx_ring->work_limit) ||
 291             (count == tx_ring->count))
 292                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, tx_ring->v_idx);
 293
 294         tx_ring->total_bytes += total_bytes;
 295         tx_ring->total_packets += total_packets;
 296         tx_ring->stats.packets += total_packets;
 297         tx_ring->stats.bytes += total_bytes;
 298         adapter->net_stats.tx_bytes += total_bytes;
 299         adapter->net_stats.tx_packets += total_packets;
 300         return (total_packets ? true : false);
 301 }
 302
 303 #ifdef CONFIG_IXGBE_DCA
 304 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
 305                                 struct ixgbe_ring *rx_ring)
 306 {
 307         u32 rxctrl;
 308         int cpu = get_cpu();
 309         int q = rx_ring - adapter->rx_ring;
 310
 311         if (rx_ring->cpu != cpu) {
 312                 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
 313                 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
 314                 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 315                 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
 316                 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
 317                 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
 318                 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
 319                             IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
 320                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
 321                 rx_ring->cpu = cpu;
 322         }
 323         put_cpu();
 324 }
 325
 326 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
 327                                 struct ixgbe_ring *tx_ring)
 328 {
 329         u32 txctrl;
 330         int cpu = get_cpu();
 331         int q = tx_ring - adapter->tx_ring;
 332
 333         if (tx_ring->cpu != cpu) {
 334                 txctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q));
 335                 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
 336                 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 337                 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 338                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q), txctrl);
 339                 tx_ring->cpu = cpu;
 340         }
 341         put_cpu();
 342 }
 343
 344 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
 345 {
 346         int i;
 347
 348         if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
 349                 return;
 350
 351         for (i = 0; i < adapter->num_tx_queues; i++) {
 352                 adapter->tx_ring[i].cpu = -1;
 353                 ixgbe_update_tx_dca(adapter, &adapter->tx_ring[i]);
 354         }
 355         for (i = 0; i < adapter->num_rx_queues; i++) {
 356                 adapter->rx_ring[i].cpu = -1;
 357                 ixgbe_update_rx_dca(adapter, &adapter->rx_ring[i]);
 358         }
 359 }
 360
 361 static int __ixgbe_notify_dca(struct device *dev, void *data)
 362 {
 363         struct net_device *netdev = dev_get_drvdata(dev);
 364         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 365         unsigned long event = *(unsigned long *)data;
 366
 367         switch (event) {
 368         case DCA_PROVIDER_ADD:
 369                 /* if we're already enabled, don't do it again */
 370                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
 371                         break;
 372                 /* Always use CB2 mode, difference is masked
 373                  * in the CB driver. */
 374                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
 375                 if (dca_add_requester(dev) == 0) {
 376                         adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
 377                         ixgbe_setup_dca(adapter);
 378                         break;
 379                 }
 380                 /* Fall Through since DCA is disabled. */
 381         case DCA_PROVIDER_REMOVE:
 382                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
 383                         dca_remove_requester(dev);
 384                         adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
 385                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
 386                 }
 387                 break;
 388         }
 389
 390         return 0;
 391 }
 392
 393 #endif /* CONFIG_IXGBE_DCA */
 394 /**
 395  * ixgbe_receive_skb - Send a completed packet up the stack
 396  * @adapter: board private structure
 397  * @skb: packet to send up
 398  * @status: hardware indication of status of receive
 399  * @rx_ring: rx descriptor ring (for a specific queue) to setup
 400  * @rx_desc: rx descriptor
 401  **/
 402 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
 403                               struct sk_buff *skb, u8 status,
 404                               union ixgbe_adv_rx_desc *rx_desc)
 405 {
 406         struct ixgbe_adapter *adapter = q_vector->adapter;
 407         struct napi_struct *napi = &q_vector->napi;
 408         bool is_vlan = (status & IXGBE_RXD_STAT_VP);
 409         u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
 410
 411         skb_record_rx_queue(skb, q_vector - &adapter->q_vector[0]);
 412         if (skb->ip_summed == CHECKSUM_UNNECESSARY) {
 413                 if (adapter->vlgrp && is_vlan && (tag != 0))
 414                         vlan_gro_receive(napi, adapter->vlgrp, tag, skb);
 415                 else
 416                         napi_gro_receive(napi, skb);
 417         } else {
 418                 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
 419                         if (adapter->vlgrp && is_vlan && (tag != 0))
 420                                 vlan_hwaccel_receive_skb(skb, adapter->vlgrp, tag);
 421                         else
 422                                 netif_receive_skb(skb);
 423                 } else {
 424                         if (adapter->vlgrp && is_vlan && (tag != 0))
 425                                 vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
 426                         else
 427                                 netif_rx(skb);
 428                 }
 429         }
 430 }
 431
 432 /**
 433  * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
 434  * @adapter: address of board private structure
 435  * @status_err: hardware indication of status of receive
 436  * @skb: skb currently being received and modified
 437  **/
 438 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
 439                                      u32 status_err, struct sk_buff *skb)
 440 {
 441         skb->ip_summed = CHECKSUM_NONE;
 442
 443         /* Rx csum disabled */
 444         if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
 445                 return;
 446
 447         /* if IP and error */
 448         if ((status_err & IXGBE_RXD_STAT_IPCS) &&
 449             (status_err & IXGBE_RXDADV_ERR_IPE)) {
 450                 adapter->hw_csum_rx_error++;
 451                 return;
 452         }
 453
 454         if (!(status_err & IXGBE_RXD_STAT_L4CS))
 455                 return;
 456
 457         if (status_err & IXGBE_RXDADV_ERR_TCPE) {
 458                 adapter->hw_csum_rx_error++;
 459                 return;
 460         }
 461
 462         /* It must be a TCP or UDP packet with a valid checksum */
 463         skb->ip_summed = CHECKSUM_UNNECESSARY;
 464         adapter->hw_csum_rx_good++;
 465 }
 466
 467 /**
 468  * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
 469  * @adapter: address of board private structure
 470  **/
 471 static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
 472                                    struct ixgbe_ring *rx_ring,
 473                                    int cleaned_count)
 474 {
 475         struct pci_dev *pdev = adapter->pdev;
 476         union ixgbe_adv_rx_desc *rx_desc;
 477         struct ixgbe_rx_buffer *bi;
 478         unsigned int i;
 479
 480         i = rx_ring->next_to_use;
 481         bi = &rx_ring->rx_buffer_info[i];
 482
 483         while (cleaned_count--) {
 484                 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
 485
 486                 if (!bi->page_dma &&
 487                     (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)) {
 488                         if (!bi->page) {
 489                                 bi->page = alloc_page(GFP_ATOMIC);
 490                                 if (!bi->page) {
 491                                         adapter->alloc_rx_page_failed++;
 492                                         goto no_buffers;
 493                                 }
 494                                 bi->page_offset = 0;
 495                         } else {
 496                                 /* use a half page if we're re-using */
 497                                 bi->page_offset ^= (PAGE_SIZE / 2);
 498                         }
 499
 500                         bi->page_dma = pci_map_page(pdev, bi->page,
 501                                                     bi->page_offset,
 502                                                     (PAGE_SIZE / 2),
 503                                                     PCI_DMA_FROMDEVICE);
 504                 }
 505
 506                 if (!bi->skb) {
 507                         struct sk_buff *skb;
 508                         skb = netdev_alloc_skb(adapter->netdev,
 509                                                (rx_ring->rx_buf_len +
 510                                                 NET_IP_ALIGN));
 511
 512                         if (!skb) {
 513                                 adapter->alloc_rx_buff_failed++;
 514                                 goto no_buffers;
 515                         }
 516
 517                         /*
 518                          * Make buffer alignment 2 beyond a 16 byte boundary
 519                          * this will result in a 16 byte aligned IP header after
 520                          * the 14 byte MAC header is removed
 521                          */
 522                         skb_reserve(skb, NET_IP_ALIGN);
 523
 524                         bi->skb = skb;
 525                         bi->dma = pci_map_single(pdev, skb->data,
 526                                                  rx_ring->rx_buf_len,
 527                                                  PCI_DMA_FROMDEVICE);
 528                 }
 529                 /* Refresh the desc even if buffer_addrs didn't change because
 530                  * each write-back erases this info. */
 531                 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
 532                         rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
 533                         rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
 534                 } else {
 535                         rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
 536                 }
 537
 538                 i++;
 539                 if (i == rx_ring->count)
 540                         i = 0;
 541                 bi = &rx_ring->rx_buffer_info[i];
 542         }
 543
 544 no_buffers:
 545         if (rx_ring->next_to_use != i) {
 546                 rx_ring->next_to_use = i;
 547                 if (i-- == 0)
 548                         i = (rx_ring->count - 1);
 549
 550                 /*
 551                  * Force memory writes to complete before letting h/w
 552                  * know there are new descriptors to fetch.  (Only
 553                  * applicable for weak-ordered memory model archs,
 554                  * such as IA-64).
 555                  */
 556                 wmb();
 557                 writel(i, adapter->hw.hw_addr + rx_ring->tail);
 558         }
 559 }
 560
 561 static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
 562 {
 563         return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
 564 }
 565
 566 static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
 567 {
 568         return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
 569 }
 570
 571 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
 572                                struct ixgbe_ring *rx_ring,
 573                                int *work_done, int work_to_do)
 574 {
 575         struct ixgbe_adapter *adapter = q_vector->adapter;
 576         struct pci_dev *pdev = adapter->pdev;
 577         union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
 578         struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
 579         struct sk_buff *skb;
 580         unsigned int i;
 581         u32 len, staterr;
 582         u16 hdr_info;
 583         bool cleaned = false;
 584         int cleaned_count = 0;
 585         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
 586
 587         i = rx_ring->next_to_clean;
 588         rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
 589         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 590         rx_buffer_info = &rx_ring->rx_buffer_info[i];
 591
 592         while (staterr & IXGBE_RXD_STAT_DD) {
 593                 u32 upper_len = 0;
 594                 if (*work_done >= work_to_do)
 595                         break;
 596                 (*work_done)++;
 597
 598                 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
 599                         hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
 600                         len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
 601                                IXGBE_RXDADV_HDRBUFLEN_SHIFT;
 602                         if (hdr_info & IXGBE_RXDADV_SPH)
 603                                 adapter->rx_hdr_split++;
 604                         if (len > IXGBE_RX_HDR_SIZE)
 605                                 len = IXGBE_RX_HDR_SIZE;
 606                         upper_len = le16_to_cpu(rx_desc->wb.upper.length);
 607                 } else {
 608                         len = le16_to_cpu(rx_desc->wb.upper.length);
 609                 }
 610
 611                 cleaned = true;
 612                 skb = rx_buffer_info->skb;
 613                 prefetch(skb->data - NET_IP_ALIGN);
 614                 rx_buffer_info->skb = NULL;
 615
 616                 if (len && !skb_shinfo(skb)->nr_frags) {
 617                         pci_unmap_single(pdev, rx_buffer_info->dma,
 618                                          rx_ring->rx_buf_len,
 619                                          PCI_DMA_FROMDEVICE);
 620                         skb_put(skb, len);
 621                 }
 622
 623                 if (upper_len) {
 624                         pci_unmap_page(pdev, rx_buffer_info->page_dma,
 625                                        PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
 626                         rx_buffer_info->page_dma = 0;
 627                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
 628                                            rx_buffer_info->page,
 629                                            rx_buffer_info->page_offset,
 630                                            upper_len);
 631
 632                         if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
 633                             (page_count(rx_buffer_info->page) != 1))
 634                                 rx_buffer_info->page = NULL;
 635                         else
 636                                 get_page(rx_buffer_info->page);
 637
 638                         skb->len += upper_len;
 639                         skb->data_len += upper_len;
 640                         skb->truesize += upper_len;
 641                 }
 642
 643                 i++;
 644                 if (i == rx_ring->count)
 645                         i = 0;
 646                 next_buffer = &rx_ring->rx_buffer_info[i];
 647
 648                 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
 649                 prefetch(next_rxd);
 650
 651                 cleaned_count++;
 652                 if (staterr & IXGBE_RXD_STAT_EOP) {
 653                         rx_ring->stats.packets++;
 654                         rx_ring->stats.bytes += skb->len;
 655                 } else {
 656                         rx_buffer_info->skb = next_buffer->skb;
 657                         rx_buffer_info->dma = next_buffer->dma;
 658                         next_buffer->skb = skb;
 659                         next_buffer->dma = 0;
 660                         adapter->non_eop_descs++;
 661                         goto next_desc;
 662                 }
 663
 664                 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
 665                         dev_kfree_skb_irq(skb);
 666                         goto next_desc;
 667                 }
 668
 669                 ixgbe_rx_checksum(adapter, staterr, skb);
 670
 671                 /* probably a little skewed due to removing CRC */
 672                 total_rx_bytes += skb->len;
 673                 total_rx_packets++;
 674
 675                 skb->protocol = eth_type_trans(skb, adapter->netdev);
 676                 ixgbe_receive_skb(q_vector, skb, staterr, rx_desc);
 677
 678 next_desc:
 679                 rx_desc->wb.upper.status_error = 0;
 680
 681                 /* return some buffers to hardware, one at a time is too slow */
 682                 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
 683                         ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
 684                         cleaned_count = 0;
 685                 }
 686
 687                 /* use prefetched values */
 688                 rx_desc = next_rxd;
 689                 rx_buffer_info = next_buffer;
 690
 691                 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 692         }
 693
 694         rx_ring->next_to_clean = i;
 695         cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
 696
 697         if (cleaned_count)
 698                 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
 699
 700         rx_ring->total_packets += total_rx_packets;
 701         rx_ring->total_bytes += total_rx_bytes;
 702         adapter->net_stats.rx_bytes += total_rx_bytes;
 703         adapter->net_stats.rx_packets += total_rx_packets;
 704
 705         return cleaned;
 706 }
 707
 708 static int ixgbe_clean_rxonly(struct napi_struct *, int);
 709 /**
 710  * ixgbe_configure_msix - Configure MSI-X hardware
 711  * @adapter: board private structure
 712  *
 713  * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
 714  * interrupts.
 715  **/
 716 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
 717 {
 718         struct ixgbe_q_vector *q_vector;
 719         int i, j, q_vectors, v_idx, r_idx;
 720         u32 mask;
 721
 722         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
 723
 724         /* Populate the IVAR table and set the ITR values to the
 725          * corresponding register.
 726          */
 727         for (v_idx = 0; v_idx < q_vectors; v_idx++) {
 728                 q_vector = &adapter->q_vector[v_idx];
 729                 /* XXX for_each_bit(...) */
 730                 r_idx = find_first_bit(q_vector->rxr_idx,
 731                                        adapter->num_rx_queues);
 732
 733                 for (i = 0; i < q_vector->rxr_count; i++) {
 734                         j = adapter->rx_ring[r_idx].reg_idx;
 735                         ixgbe_set_ivar(adapter, IXGBE_IVAR_RX_QUEUE(j), v_idx);
 736                         r_idx = find_next_bit(q_vector->rxr_idx,
 737                                               adapter->num_rx_queues,
 738                                               r_idx + 1);
 739                 }
 740                 r_idx = find_first_bit(q_vector->txr_idx,
 741                                        adapter->num_tx_queues);
 742
 743                 for (i = 0; i < q_vector->txr_count; i++) {
 744                         j = adapter->tx_ring[r_idx].reg_idx;
 745                         ixgbe_set_ivar(adapter, IXGBE_IVAR_TX_QUEUE(j), v_idx);
 746                         r_idx = find_next_bit(q_vector->txr_idx,
 747                                               adapter->num_tx_queues,
 748                                               r_idx + 1);
 749                 }
 750
 751                 /* if this is a tx only vector halve the interrupt rate */
 752                 if (q_vector->txr_count && !q_vector->rxr_count)
 753                         q_vector->eitr = (adapter->eitr_param >> 1);
 754                 else
 755                         /* rx only */
 756                         q_vector->eitr = adapter->eitr_param;
 757
 758                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx),
 759                                 EITR_INTS_PER_SEC_TO_REG(q_vector->eitr));
 760         }
 761
 762         ixgbe_set_ivar(adapter, IXGBE_IVAR_OTHER_CAUSES_INDEX, v_idx);
 763         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
 764
 765         /* set up to autoclear timer, and the vectors */
 766         mask = IXGBE_EIMS_ENABLE_MASK;
 767         mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
 768         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
 769 }
 770
 771 enum latency_range {
 772         lowest_latency = 0,
 773         low_latency = 1,
 774         bulk_latency = 2,
 775         latency_invalid = 255
 776 };
 777
 778 /**
 779  * ixgbe_update_itr - update the dynamic ITR value based on statistics
 780  * @adapter: pointer to adapter
 781  * @eitr: eitr setting (ints per sec) to give last timeslice
 782  * @itr_setting: current throttle rate in ints/second
 783  * @packets: the number of packets during this measurement interval
 784  * @bytes: the number of bytes during this measurement interval
 785  *
 786  *      Stores a new ITR value based on packets and byte
 787  *      counts during the last interrupt.  The advantage of per interrupt
 788  *      computation is faster updates and more accurate ITR for the current
 789  *      traffic pattern.  Constants in this function were computed
 790  *      based on theoretical maximum wire speed and thresholds were set based
 791  *      on testing data as well as attempting to minimize response time
 792  *      while increasing bulk throughput.
 793  *      this functionality is controlled by the InterruptThrottleRate module
 794  *      parameter (see ixgbe_param.c)
 795  **/
 796 static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
 797                            u32 eitr, u8 itr_setting,
 798                            int packets, int bytes)
 799 {
 800         unsigned int retval = itr_setting;
 801         u32 timepassed_us;
 802         u64 bytes_perint;
 803
 804         if (packets == 0)
 805                 goto update_itr_done;
 806
 807
 808         /* simple throttlerate management
 809          *    0-20MB/s lowest (100000 ints/s)
 810          *   20-100MB/s low   (20000 ints/s)
 811          *  100-1249MB/s bulk (8000 ints/s)
 812          */
 813         /* what was last interrupt timeslice? */
 814         timepassed_us = 1000000/eitr;
 815         bytes_perint = bytes / timepassed_us; /* bytes/usec */
 816
 817         switch (itr_setting) {
 818         case lowest_latency:
 819                 if (bytes_perint > adapter->eitr_low)
 820                         retval = low_latency;
 821                 break;
 822         case low_latency:
 823                 if (bytes_perint > adapter->eitr_high)
 824                         retval = bulk_latency;
 825                 else if (bytes_perint <= adapter->eitr_low)
 826                         retval = lowest_latency;
 827                 break;
 828         case bulk_latency:
 829                 if (bytes_perint <= adapter->eitr_high)
 830                         retval = low_latency;
 831                 break;
 832         }
 833
 834 update_itr_done:
 835         return retval;
 836 }
 837
 838 static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
 839 {
 840         struct ixgbe_adapter *adapter = q_vector->adapter;
 841         struct ixgbe_hw *hw = &adapter->hw;
 842         u32 new_itr;
 843         u8 current_itr, ret_itr;
 844         int i, r_idx, v_idx = ((void *)q_vector - (void *)(adapter->q_vector)) /
 845                                sizeof(struct ixgbe_q_vector);
 846         struct ixgbe_ring *rx_ring, *tx_ring;
 847
 848         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
 849         for (i = 0; i < q_vector->txr_count; i++) {
 850                 tx_ring = &(adapter->tx_ring[r_idx]);
 851                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
 852                                            q_vector->tx_itr,
 853                                            tx_ring->total_packets,
 854                                            tx_ring->total_bytes);
 855                 /* if the result for this queue would decrease interrupt
 856                  * rate for this vector then use that result */
 857                 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
 858                                     q_vector->tx_itr - 1 : ret_itr);
 859                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
 860                                       r_idx + 1);
 861         }
 862
 863         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
 864         for (i = 0; i < q_vector->rxr_count; i++) {
 865                 rx_ring = &(adapter->rx_ring[r_idx]);
 866                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
 867                                            q_vector->rx_itr,
 868                                            rx_ring->total_packets,
 869                                            rx_ring->total_bytes);
 870                 /* if the result for this queue would decrease interrupt
 871                  * rate for this vector then use that result */
 872                 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
 873                                     q_vector->rx_itr - 1 : ret_itr);
 874                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
 875                                       r_idx + 1);
 876         }
 877
 878         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
 879
 880         switch (current_itr) {
 881         /* counts and packets in update_itr are dependent on these numbers */
 882         case lowest_latency:
 883                 new_itr = 100000;
 884                 break;
 885         case low_latency:
 886                 new_itr = 20000; /* aka hwitr = ~200 */
 887                 break;
 888         case bulk_latency:
 889         default:
 890                 new_itr = 8000;
 891                 break;
 892         }
 893
 894         if (new_itr != q_vector->eitr) {
 895                 u32 itr_reg;
 896                 /* do an exponential smoothing */
 897                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
 898                 q_vector->eitr = new_itr;
 899                 itr_reg = EITR_INTS_PER_SEC_TO_REG(new_itr);
 900                 /* must write high and low 16 bits to reset counter */
 901                 DPRINTK(TX_ERR, DEBUG, "writing eitr(%d): %08X\n", v_idx,
 902                         itr_reg);
 903                 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg | (itr_reg)<<16);
 904         }
 905
 906         return;
 907 }
 908
 909 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
 910 {
 911         struct ixgbe_hw *hw = &adapter->hw;
 912
 913         if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
 914             (eicr & IXGBE_EICR_GPI_SDP1)) {
 915                 DPRINTK(PROBE, CRIT, "Fan has stopped, replace the adapter\n");
 916                 /* write to clear the interrupt */
 917                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
 918         }
 919 }
 920
 921 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
 922 {
 923         struct ixgbe_hw *hw = &adapter->hw;
 924
 925         adapter->lsc_int++;
 926         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
 927         adapter->link_check_timeout = jiffies;
 928         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
 929                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
 930                 schedule_work(&adapter->watchdog_task);
 931         }
 932 }
 933
 934 static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
 935 {
 936         struct net_device *netdev = data;
 937         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 938         struct ixgbe_hw *hw = &adapter->hw;
 939         u32 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
 940
 941         if (eicr & IXGBE_EICR_LSC)
 942                 ixgbe_check_lsc(adapter);
 943
 944         ixgbe_check_fan_failure(adapter, eicr);
 945
 946         if (!test_bit(__IXGBE_DOWN, &adapter->state))
 947                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
 948
 949         return IRQ_HANDLED;
 950 }
 951
 952 static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
 953 {
 954         struct ixgbe_q_vector *q_vector = data;
 955         struct ixgbe_adapter  *adapter = q_vector->adapter;
 956         struct ixgbe_ring     *tx_ring;
 957         int i, r_idx;
 958
 959         if (!q_vector->txr_count)
 960                 return IRQ_HANDLED;
 961
 962         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
 963         for (i = 0; i < q_vector->txr_count; i++) {
 964                 tx_ring = &(adapter->tx_ring[r_idx]);
 965 #ifdef CONFIG_IXGBE_DCA
 966                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
 967                         ixgbe_update_tx_dca(adapter, tx_ring);
 968 #endif
 969                 tx_ring->total_bytes = 0;
 970                 tx_ring->total_packets = 0;
 971                 ixgbe_clean_tx_irq(adapter, tx_ring);
 972                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
 973                                       r_idx + 1);
 974         }
 975
 976         return IRQ_HANDLED;
 977 }
 978
 979 /**
 980  * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
 981  * @irq: unused
 982  * @data: pointer to our q_vector struct for this interrupt vector
 983  **/
 984 static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
 985 {
 986         struct ixgbe_q_vector *q_vector = data;
 987         struct ixgbe_adapter  *adapter = q_vector->adapter;
 988         struct ixgbe_ring  *rx_ring;
 989         int r_idx;
 990         int i;
 991
 992         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
 993         for (i = 0;  i < q_vector->rxr_count; i++) {
 994                 rx_ring = &(adapter->rx_ring[r_idx]);
 995                 rx_ring->total_bytes = 0;
 996                 rx_ring->total_packets = 0;
 997                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
 998                                       r_idx + 1);
 999         }
1000
1001         if (!q_vector->rxr_count)
1002                 return IRQ_HANDLED;
1003
1004         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1005         rx_ring = &(adapter->rx_ring[r_idx]);
1006         /* disable interrupts on this vector only */
1007         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, rx_ring->v_idx);
1008         napi_schedule(&q_vector->napi);
1009
1010         return IRQ_HANDLED;
1011 }
1012
1013 static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1014 {
1015         ixgbe_msix_clean_rx(irq, data);
1016         ixgbe_msix_clean_tx(irq, data);
1017
1018         return IRQ_HANDLED;
1019 }
1020
1021 /**
1022  * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1023  * @napi: napi struct with our devices info in it
1024  * @budget: amount of work driver is allowed to do this pass, in packets
1025  *
1026  * This function is optimized for cleaning one queue only on a single
1027  * q_vector!!!
1028  **/
1029 static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1030 {
1031         struct ixgbe_q_vector *q_vector =
1032                                container_of(napi, struct ixgbe_q_vector, napi);
1033         struct ixgbe_adapter *adapter = q_vector->adapter;
1034         struct ixgbe_ring *rx_ring = NULL;
1035         int work_done = 0;
1036         long r_idx;
1037
1038         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1039         rx_ring = &(adapter->rx_ring[r_idx]);
1040 #ifdef CONFIG_IXGBE_DCA
1041         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1042                 ixgbe_update_rx_dca(adapter, rx_ring);
1043 #endif
1044
1045         ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
1046
1047         /* If all Rx work done, exit the polling mode */
1048         if (work_done < budget) {
1049                 napi_complete(napi);
1050                 if (adapter->itr_setting & 3)
1051                         ixgbe_set_itr_msix(q_vector);
1052                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1053                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, rx_ring->v_idx);
1054         }
1055
1056         return work_done;
1057 }
1058
1059 /**
1060  * ixgbe_clean_rxonly_many - msix (aka one shot) rx clean routine
1061  * @napi: napi struct with our devices info in it
1062  * @budget: amount of work driver is allowed to do this pass, in packets
1063  *
1064  * This function will clean more than one rx queue associated with a
1065  * q_vector.
1066  **/
1067 static int ixgbe_clean_rxonly_many(struct napi_struct *napi, int budget)
1068 {
1069         struct ixgbe_q_vector *q_vector =
1070                                container_of(napi, struct ixgbe_q_vector, napi);
1071         struct ixgbe_adapter *adapter = q_vector->adapter;
1072         struct ixgbe_ring *rx_ring = NULL;
1073         int work_done = 0, i;
1074         long r_idx;
1075         u16 enable_mask = 0;
1076
1077         /* attempt to distribute budget to each queue fairly, but don't allow
1078          * the budget to go below 1 because we'll exit polling */
1079         budget /= (q_vector->rxr_count ?: 1);
1080         budget = max(budget, 1);
1081         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1082         for (i = 0; i < q_vector->rxr_count; i++) {
1083                 rx_ring = &(adapter->rx_ring[r_idx]);
1084 #ifdef CONFIG_IXGBE_DCA
1085                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1086                         ixgbe_update_rx_dca(adapter, rx_ring);
1087 #endif
1088                 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
1089                 enable_mask |= rx_ring->v_idx;
1090                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1091                                       r_idx + 1);
1092         }
1093
1094         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1095         rx_ring = &(adapter->rx_ring[r_idx]);
1096         /* If all Rx work done, exit the polling mode */
1097         if (work_done < budget) {
1098                 napi_complete(napi);
1099                 if (adapter->itr_setting & 3)
1100                         ixgbe_set_itr_msix(q_vector);
1101                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1102                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, enable_mask);
1103                 return 0;
1104         }
1105
1106         return work_done;
1107 }
1108 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
1109                                      int r_idx)
1110 {
1111         a->q_vector[v_idx].adapter = a;
1112         set_bit(r_idx, a->q_vector[v_idx].rxr_idx);
1113         a->q_vector[v_idx].rxr_count++;
1114         a->rx_ring[r_idx].v_idx = 1 << v_idx;
1115 }
1116
1117 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
1118                                      int r_idx)
1119 {
1120         a->q_vector[v_idx].adapter = a;
1121         set_bit(r_idx, a->q_vector[v_idx].txr_idx);
1122         a->q_vector[v_idx].txr_count++;
1123         a->tx_ring[r_idx].v_idx = 1 << v_idx;
1124 }
1125
1126 /**
1127  * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
1128  * @adapter: board private structure to initialize
1129  * @vectors: allotted vector count for descriptor rings
1130  *
1131  * This function maps descriptor rings to the queue-specific vectors
1132  * we were allotted through the MSI-X enabling code.  Ideally, we'd have
1133  * one vector per ring/queue, but on a constrained vector budget, we
1134  * group the rings as "efficiently" as possible.  You would add new
1135  * mapping configurations in here.
1136  **/
1137 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
1138                                       int vectors)
1139 {
1140         int v_start = 0;
1141         int rxr_idx = 0, txr_idx = 0;
1142         int rxr_remaining = adapter->num_rx_queues;
1143         int txr_remaining = adapter->num_tx_queues;
1144         int i, j;
1145         int rqpv, tqpv;
1146         int err = 0;
1147
1148         /* No mapping required if MSI-X is disabled. */
1149         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1150                 goto out;
1151
1152         /*
1153          * The ideal configuration...
1154          * We have enough vectors to map one per queue.
1155          */
1156         if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
1157                 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
1158                         map_vector_to_rxq(adapter, v_start, rxr_idx);
1159
1160                 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
1161                         map_vector_to_txq(adapter, v_start, txr_idx);
1162
1163                 goto out;
1164         }
1165
1166         /*
1167          * If we don't have enough vectors for a 1-to-1
1168          * mapping, we'll have to group them so there are
1169          * multiple queues per vector.
1170          */
1171         /* Re-adjusting *qpv takes care of the remainder. */
1172         for (i = v_start; i < vectors; i++) {
1173                 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
1174                 for (j = 0; j < rqpv; j++) {
1175                         map_vector_to_rxq(adapter, i, rxr_idx);
1176                         rxr_idx++;
1177                         rxr_remaining--;
1178                 }
1179         }
1180         for (i = v_start; i < vectors; i++) {
1181                 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
1182                 for (j = 0; j < tqpv; j++) {
1183                         map_vector_to_txq(adapter, i, txr_idx);
1184                         txr_idx++;
1185                         txr_remaining--;
1186                 }
1187         }
1188
1189 out:
1190         return err;
1191 }
1192
1193 /**
1194  * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
1195  * @adapter: board private structure
1196  *
1197  * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
1198  * interrupts from the kernel.
1199  **/
1200 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
1201 {
1202         struct net_device *netdev = adapter->netdev;
1203         irqreturn_t (*handler)(int, void *);
1204         int i, vector, q_vectors, err;
1205         int ri=0, ti=0;
1206
1207         /* Decrement for Other and TCP Timer vectors */
1208         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1209
1210         /* Map the Tx/Rx rings to the vectors we were allotted. */
1211         err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
1212         if (err)
1213                 goto out;
1214
1215 #define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
1216                          (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
1217                          &ixgbe_msix_clean_many)
1218         for (vector = 0; vector < q_vectors; vector++) {
1219                 handler = SET_HANDLER(&adapter->q_vector[vector]);
1220
1221                 if(handler == &ixgbe_msix_clean_rx) {
1222                         sprintf(adapter->name[vector], "%s-%s-%d",
1223                                 netdev->name, "rx", ri++);
1224                 }
1225                 else if(handler == &ixgbe_msix_clean_tx) {
1226                         sprintf(adapter->name[vector], "%s-%s-%d",
1227                                 netdev->name, "tx", ti++);
1228                 }
1229                 else
1230                         sprintf(adapter->name[vector], "%s-%s-%d",
1231                                 netdev->name, "TxRx", vector);
1232
1233                 err = request_irq(adapter->msix_entries[vector].vector,
1234                                   handler, 0, adapter->name[vector],
1235                                   &(adapter->q_vector[vector]));
1236                 if (err) {
1237                         DPRINTK(PROBE, ERR,
1238                                 "request_irq failed for MSIX interrupt "
1239                                 "Error: %d\n", err);
1240                         goto free_queue_irqs;
1241                 }
1242         }
1243
1244         sprintf(adapter->name[vector], "%s:lsc", netdev->name);
1245         err = request_irq(adapter->msix_entries[vector].vector,
1246                           &ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
1247         if (err) {
1248                 DPRINTK(PROBE, ERR,
1249                         "request_irq for msix_lsc failed: %d\n", err);
1250                 goto free_queue_irqs;
1251         }
1252
1253         return 0;
1254
1255 free_queue_irqs:
1256         for (i = vector - 1; i >= 0; i--)
1257                 free_irq(adapter->msix_entries[--vector].vector,
1258                          &(adapter->q_vector[i]));
1259         adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
1260         pci_disable_msix(adapter->pdev);
1261         kfree(adapter->msix_entries);
1262         adapter->msix_entries = NULL;
1263 out:
1264         return err;
1265 }
1266
1267 static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
1268 {
1269         struct ixgbe_hw *hw = &adapter->hw;
1270         struct ixgbe_q_vector *q_vector = adapter->q_vector;
1271         u8 current_itr;
1272         u32 new_itr = q_vector->eitr;
1273         struct ixgbe_ring *rx_ring = &adapter->rx_ring[0];
1274         struct ixgbe_ring *tx_ring = &adapter->tx_ring[0];
1275
1276         q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
1277                                             q_vector->tx_itr,
1278                                             tx_ring->total_packets,
1279                                             tx_ring->total_bytes);
1280         q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
1281                                             q_vector->rx_itr,
1282                                             rx_ring->total_packets,
1283                                             rx_ring->total_bytes);
1284
1285         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1286
1287         switch (current_itr) {
1288         /* counts and packets in update_itr are dependent on these numbers */
1289         case lowest_latency:
1290                 new_itr = 100000;
1291                 break;
1292         case low_latency:
1293                 new_itr = 20000; /* aka hwitr = ~200 */
1294                 break;
1295         case bulk_latency:
1296                 new_itr = 8000;
1297                 break;
1298         default:
1299                 break;
1300         }
1301
1302         if (new_itr != q_vector->eitr) {
1303                 u32 itr_reg;
1304                 /* do an exponential smoothing */
1305                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1306                 q_vector->eitr = new_itr;
1307                 itr_reg = EITR_INTS_PER_SEC_TO_REG(new_itr);
1308                 /* must write high and low 16 bits to reset counter */
1309                 IXGBE_WRITE_REG(hw, IXGBE_EITR(0), itr_reg | (itr_reg)<<16);
1310         }
1311
1312         return;
1313 }
1314
1315 /**
1316  * ixgbe_irq_disable - Mask off interrupt generation on the NIC
1317  * @adapter: board private structure
1318  **/
1319 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
1320 {
1321         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
1322         IXGBE_WRITE_FLUSH(&adapter->hw);
1323         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1324                 int i;
1325                 for (i = 0; i < adapter->num_msix_vectors; i++)
1326                         synchronize_irq(adapter->msix_entries[i].vector);
1327         } else {
1328                 synchronize_irq(adapter->pdev->irq);
1329         }
1330 }
1331
1332 /**
1333  * ixgbe_irq_enable - Enable default interrupt generation settings
1334  * @adapter: board private structure
1335  **/
1336 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
1337 {
1338         u32 mask;
1339         mask = IXGBE_EIMS_ENABLE_MASK;
1340         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
1341                 mask |= IXGBE_EIMS_GPI_SDP1;
1342         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1343         IXGBE_WRITE_FLUSH(&adapter->hw);
1344 }
1345
1346 /**
1347  * ixgbe_intr - legacy mode Interrupt Handler
1348  * @irq: interrupt number
1349  * @data: pointer to a network interface device structure
1350  **/
1351 static irqreturn_t ixgbe_intr(int irq, void *data)
1352 {
1353         struct net_device *netdev = data;
1354         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1355         struct ixgbe_hw *hw = &adapter->hw;
1356         u32 eicr;
1357
1358         /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
1359          * therefore no explict interrupt disable is necessary */
1360         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
1361         if (!eicr) {
1362                 /* shared interrupt alert!
1363                  * make sure interrupts are enabled because the read will
1364                  * have disabled interrupts due to EIAM */
1365                 ixgbe_irq_enable(adapter);
1366                 return IRQ_NONE;        /* Not our interrupt */
1367         }
1368
1369         if (eicr & IXGBE_EICR_LSC)
1370                 ixgbe_check_lsc(adapter);
1371
1372         ixgbe_check_fan_failure(adapter, eicr);
1373
1374         if (napi_schedule_prep(&adapter->q_vector[0].napi)) {
1375                 adapter->tx_ring[0].total_packets = 0;
1376                 adapter->tx_ring[0].total_bytes = 0;
1377                 adapter->rx_ring[0].total_packets = 0;
1378                 adapter->rx_ring[0].total_bytes = 0;
1379                 /* would disable interrupts here but EIAM disabled it */
1380                 __napi_schedule(&adapter->q_vector[0].napi);
1381         }
1382
1383         return IRQ_HANDLED;
1384 }
1385
1386 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
1387 {
1388         int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1389
1390         for (i = 0; i < q_vectors; i++) {
1391                 struct ixgbe_q_vector *q_vector = &adapter->q_vector[i];
1392                 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
1393                 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
1394                 q_vector->rxr_count = 0;
1395                 q_vector->txr_count = 0;
1396         }
1397 }
1398
1399 /**
1400  * ixgbe_request_irq - initialize interrupts
1401  * @adapter: board private structure
1402  *
1403  * Attempts to configure interrupts using the best available
1404  * capabilities of the hardware and kernel.
1405  **/
1406 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
1407 {
1408         struct net_device *netdev = adapter->netdev;
1409         int err;
1410
1411         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1412                 err = ixgbe_request_msix_irqs(adapter);
1413         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1414                 err = request_irq(adapter->pdev->irq, &ixgbe_intr, 0,
1415                                   netdev->name, netdev);
1416         } else {
1417                 err = request_irq(adapter->pdev->irq, &ixgbe_intr, IRQF_SHARED,
1418                                   netdev->name, netdev);
1419         }
1420
1421         if (err)
1422                 DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err);
1423
1424         return err;
1425 }
1426
1427 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
1428 {
1429         struct net_device *netdev = adapter->netdev;
1430
1431         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1432                 int i, q_vectors;
1433
1434                 q_vectors = adapter->num_msix_vectors;
1435
1436                 i = q_vectors - 1;
1437                 free_irq(adapter->msix_entries[i].vector, netdev);
1438
1439                 i--;
1440                 for (; i >= 0; i--) {
1441                         free_irq(adapter->msix_entries[i].vector,
1442                                  &(adapter->q_vector[i]));
1443                 }
1444
1445                 ixgbe_reset_q_vectors(adapter);
1446         } else {
1447                 free_irq(adapter->pdev->irq, netdev);
1448         }
1449 }
1450
1451 /**
1452  * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
1453  *
1454  **/
1455 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
1456 {
1457         struct ixgbe_hw *hw = &adapter->hw;
1458
1459         IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
1460                         EITR_INTS_PER_SEC_TO_REG(adapter->eitr_param));
1461
1462         ixgbe_set_ivar(adapter, IXGBE_IVAR_RX_QUEUE(0), 0);
1463         ixgbe_set_ivar(adapter, IXGBE_IVAR_TX_QUEUE(0), 0);
1464
1465         map_vector_to_rxq(adapter, 0, 0);
1466         map_vector_to_txq(adapter, 0, 0);
1467
1468         DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n");
1469 }
1470
1471 /**
1472  * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
1473  * @adapter: board private structure
1474  *
1475  * Configure the Tx unit of the MAC after a reset.
1476  **/
1477 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
1478 {
1479         u64 tdba;
1480         struct ixgbe_hw *hw = &adapter->hw;
1481         u32 i, j, tdlen, txctrl;
1482
1483         /* Setup the HW Tx Head and Tail descriptor pointers */
1484         for (i = 0; i < adapter->num_tx_queues; i++) {
1485                 struct ixgbe_ring *ring = &adapter->tx_ring[i];
1486                 j = ring->reg_idx;
1487                 tdba = ring->dma;
1488                 tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc);
1489                 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
1490                                 (tdba & DMA_32BIT_MASK));
1491                 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
1492                 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen);
1493                 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
1494                 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
1495                 adapter->tx_ring[i].head = IXGBE_TDH(j);
1496                 adapter->tx_ring[i].tail = IXGBE_TDT(j);
1497                 /* Disable Tx Head Writeback RO bit, since this hoses
1498                  * bookkeeping if things aren't delivered in order.
1499                  */
1500                 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j));
1501                 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
1502                 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl);
1503         }
1504 }
1505
1506 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
1507
1508 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, int index)
1509 {
1510         struct ixgbe_ring *rx_ring;
1511         u32 srrctl;
1512         int queue0;
1513         unsigned long mask;
1514
1515         /* program one srrctl register per VMDq index */
1516         if (adapter->flags & IXGBE_FLAG_VMDQ_ENABLED) {
1517                 long shift, len;
1518                 mask = (unsigned long) adapter->ring_feature[RING_F_RSS].mask;
1519                 len = sizeof(adapter->ring_feature[RING_F_VMDQ].mask) * 8;
1520                 shift = find_first_bit(&mask, len);
1521                 queue0 = index & mask;
1522                 index = (index & mask) >> shift;
1523         /* program one srrctl per RSS queue since RDRXCTL.MVMEN is enabled */
1524         } else {
1525                 mask = (unsigned long) adapter->ring_feature[RING_F_RSS].mask;
1526                 queue0 = index & mask;
1527                 index = index & mask;
1528         }
1529
1530         rx_ring = &adapter->rx_ring[queue0];
1531
1532         srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
1533
1534         srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
1535         srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
1536
1537         if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
1538                 srrctl |= IXGBE_RXBUFFER_2048 >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1539                 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
1540                 srrctl |= ((IXGBE_RX_HDR_SIZE <<
1541                             IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
1542                            IXGBE_SRRCTL_BSIZEHDR_MASK);
1543         } else {
1544                 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
1545
1546                 if (rx_ring->rx_buf_len == MAXIMUM_ETHERNET_VLAN_SIZE)
1547                         srrctl |= IXGBE_RXBUFFER_2048 >>
1548                                   IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1549                 else
1550                         srrctl |= rx_ring->rx_buf_len >>
1551                                   IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1552         }
1553         IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
1554 }
1555
1556 /**
1557  * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
1558  * @adapter: board private structure
1559  *
1560  * Configure the Rx unit of the MAC after a reset.
1561  **/
1562 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
1563 {
1564         u64 rdba;
1565         struct ixgbe_hw *hw = &adapter->hw;
1566         struct net_device *netdev = adapter->netdev;
1567         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1568         int i, j;
1569         u32 rdlen, rxctrl, rxcsum;
1570         static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
1571                           0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
1572                           0x6A3E67EA, 0x14364D17, 0x3BED200D};
1573         u32 fctrl, hlreg0;
1574         u32 reta = 0, mrqc;
1575         u32 rdrxctl;
1576         int rx_buf_len;
1577
1578         /* Decide whether to use packet split mode or not */
1579         adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
1580
1581         /* Set the RX buffer length according to the mode */
1582         if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
1583                 rx_buf_len = IXGBE_RX_HDR_SIZE;
1584         } else {
1585                 if (netdev->mtu <= ETH_DATA_LEN)
1586                         rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
1587                 else
1588                         rx_buf_len = ALIGN(max_frame, 1024);
1589         }
1590
1591         fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
1592         fctrl |= IXGBE_FCTRL_BAM;
1593         fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
1594         IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl);
1595
1596         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
1597         if (adapter->netdev->mtu <= ETH_DATA_LEN)
1598                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
1599         else
1600                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
1601         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
1602
1603         rdlen = adapter->rx_ring[0].count * sizeof(union ixgbe_adv_rx_desc);
1604         /* disable receives while setting up the descriptors */
1605         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1606         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
1607
1608         /* Setup the HW Rx Head and Tail Descriptor Pointers and
1609          * the Base and Length of the Rx Descriptor Ring */
1610         for (i = 0; i < adapter->num_rx_queues; i++) {
1611                 rdba = adapter->rx_ring[i].dma;
1612                 j = adapter->rx_ring[i].reg_idx;
1613                 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_32BIT_MASK));
1614                 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32));
1615                 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen);
1616                 IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0);
1617                 IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0);
1618                 adapter->rx_ring[i].head = IXGBE_RDH(j);
1619                 adapter->rx_ring[i].tail = IXGBE_RDT(j);
1620                 adapter->rx_ring[i].rx_buf_len = rx_buf_len;
1621
1622                 ixgbe_configure_srrctl(adapter, j);
1623         }
1624
1625         /*
1626          * For VMDq support of different descriptor types or
1627          * buffer sizes through the use of multiple SRRCTL
1628          * registers, RDRXCTL.MVMEN must be set to 1
1629          *
1630          * also, the manual doesn't mention it clearly but DCA hints
1631          * will only use queue 0's tags unless this bit is set.  Side
1632          * effects of setting this bit are only that SRRCTL must be
1633          * fully programmed [0..15]
1634          */
1635         if (adapter->flags &
1636             (IXGBE_FLAG_RSS_ENABLED | IXGBE_FLAG_VMDQ_ENABLED)) {
1637                 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1638                 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
1639                 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
1640         }
1641
1642         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
1643                 /* Fill out redirection table */
1644                 for (i = 0, j = 0; i < 128; i++, j++) {
1645                         if (j == adapter->ring_feature[RING_F_RSS].indices)
1646                                 j = 0;
1647                         /* reta = 4-byte sliding window of
1648                          * 0x00..(indices-1)(indices-1)00..etc. */
1649                         reta = (reta << 8) | (j * 0x11);
1650                         if ((i & 3) == 3)
1651                                 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
1652                 }
1653
1654                 /* Fill out hash function seeds */
1655                 for (i = 0; i < 10; i++)
1656                         IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
1657
1658                 mrqc = IXGBE_MRQC_RSSEN
1659                     /* Perform hash on these packet types */
1660                        | IXGBE_MRQC_RSS_FIELD_IPV4
1661                        | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
1662                        | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
1663                        | IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP
1664                        | IXGBE_MRQC_RSS_FIELD_IPV6_EX
1665                        | IXGBE_MRQC_RSS_FIELD_IPV6
1666                        | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
1667                        | IXGBE_MRQC_RSS_FIELD_IPV6_UDP
1668                        | IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP;
1669                 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
1670         }
1671
1672         rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
1673
1674         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED ||
1675             adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) {
1676                 /* Disable indicating checksum in descriptor, enables
1677                  * RSS hash */
1678                 rxcsum |= IXGBE_RXCSUM_PCSD;
1679         }
1680         if (!(rxcsum & IXGBE_RXCSUM_PCSD)) {
1681                 /* Enable IPv4 payload checksum for UDP fragments
1682                  * if PCSD is not set */
1683                 rxcsum |= IXGBE_RXCSUM_IPPCSE;
1684         }
1685
1686         IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
1687 }
1688
1689 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
1690 {
1691         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1692         struct ixgbe_hw *hw = &adapter->hw;
1693
1694         /* add VID to filter table */
1695         hw->mac.ops.set_vfta(&adapter->hw, vid, 0, true);
1696 }
1697
1698 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
1699 {
1700         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1701         struct ixgbe_hw *hw = &adapter->hw;
1702
1703         if (!test_bit(__IXGBE_DOWN, &adapter->state))
1704                 ixgbe_irq_disable(adapter);
1705
1706         vlan_group_set_device(adapter->vlgrp, vid, NULL);
1707
1708         if (!test_bit(__IXGBE_DOWN, &adapter->state))
1709                 ixgbe_irq_enable(adapter);
1710
1711         /* remove VID from filter table */
1712         hw->mac.ops.set_vfta(&adapter->hw, vid, 0, false);
1713 }
1714
1715 static void ixgbe_vlan_rx_register(struct net_device *netdev,
1716                                    struct vlan_group *grp)
1717 {
1718         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1719         u32 ctrl;
1720
1721         if (!test_bit(__IXGBE_DOWN, &adapter->state))
1722                 ixgbe_irq_disable(adapter);
1723         adapter->vlgrp = grp;
1724
1725         /*
1726          * For a DCB driver, always enable VLAN tag stripping so we can
1727          * still receive traffic from a DCB-enabled host even if we're
1728          * not in DCB mode.
1729          */
1730         ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
1731         ctrl |= IXGBE_VLNCTRL_VME;
1732         ctrl &= ~IXGBE_VLNCTRL_CFIEN;
1733         IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
1734         ixgbe_vlan_rx_add_vid(netdev, 0);
1735
1736         if (grp) {
1737                 /* enable VLAN tag insert/strip */
1738                 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
1739                 ctrl |= IXGBE_VLNCTRL_VME;
1740                 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
1741                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
1742         }
1743
1744         if (!test_bit(__IXGBE_DOWN, &adapter->state))
1745                 ixgbe_irq_enable(adapter);
1746 }
1747
1748 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
1749 {
1750         ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
1751
1752         if (adapter->vlgrp) {
1753                 u16 vid;
1754                 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
1755                         if (!vlan_group_get_device(adapter->vlgrp, vid))
1756                                 continue;
1757                         ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
1758                 }
1759         }
1760 }
1761
1762 static u8 *ixgbe_addr_list_itr(struct ixgbe_hw *hw, u8 **mc_addr_ptr, u32 *vmdq)
1763 {
1764         struct dev_mc_list *mc_ptr;
1765         u8 *addr = *mc_addr_ptr;
1766         *vmdq = 0;
1767
1768         mc_ptr = container_of(addr, struct dev_mc_list, dmi_addr[0]);
1769         if (mc_ptr->next)
1770                 *mc_addr_ptr = mc_ptr->next->dmi_addr;
1771         else
1772                 *mc_addr_ptr = NULL;
1773
1774         return addr;
1775 }
1776
1777 /**
1778  * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
1779  * @netdev: network interface device structure
1780  *
1781  * The set_rx_method entry point is called whenever the unicast/multicast
1782  * address list or the network interface flags are updated.  This routine is
1783  * responsible for configuring the hardware for proper unicast, multicast and
1784  * promiscuous mode.
1785  **/
1786 static void ixgbe_set_rx_mode(struct net_device *netdev)
1787 {
1788         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1789         struct ixgbe_hw *hw = &adapter->hw;
1790         u32 fctrl, vlnctrl;
1791         u8 *addr_list = NULL;
1792         int addr_count = 0;
1793
1794         /* Check for Promiscuous and All Multicast modes */
1795
1796         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1797         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1798
1799         if (netdev->flags & IFF_PROMISC) {
1800                 hw->addr_ctrl.user_set_promisc = 1;
1801                 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
1802                 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1803         } else {
1804                 if (netdev->flags & IFF_ALLMULTI) {
1805                         fctrl |= IXGBE_FCTRL_MPE;
1806                         fctrl &= ~IXGBE_FCTRL_UPE;
1807                 } else {
1808                         fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
1809                 }
1810                 vlnctrl |= IXGBE_VLNCTRL_VFE;
1811                 hw->addr_ctrl.user_set_promisc = 0;
1812         }
1813
1814         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1815         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1816
1817         /* reprogram secondary unicast list */
1818         addr_count = netdev->uc_count;
1819         if (addr_count)
1820                 addr_list = netdev->uc_list->dmi_addr;
1821         hw->mac.ops.update_uc_addr_list(hw, addr_list, addr_count,
1822                                           ixgbe_addr_list_itr);
1823
1824         /* reprogram multicast list */
1825         addr_count = netdev->mc_count;
1826         if (addr_count)
1827                 addr_list = netdev->mc_list->dmi_addr;
1828         hw->mac.ops.update_mc_addr_list(hw, addr_list, addr_count,
1829                                         ixgbe_addr_list_itr);
1830 }
1831
1832 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
1833 {
1834         int q_idx;
1835         struct ixgbe_q_vector *q_vector;
1836         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1837
1838         /* legacy and MSI only use one vector */
1839         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1840                 q_vectors = 1;
1841
1842         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
1843                 struct napi_struct *napi;
1844                 q_vector = &adapter->q_vector[q_idx];
1845                 if (!q_vector->rxr_count)
1846                         continue;
1847                 napi = &q_vector->napi;
1848                 if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) &&
1849                     (q_vector->rxr_count > 1))
1850                         napi->poll = &ixgbe_clean_rxonly_many;
1851
1852                 napi_enable(napi);
1853         }
1854 }
1855
1856 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
1857 {
1858         int q_idx;
1859         struct ixgbe_q_vector *q_vector;
1860         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1861
1862         /* legacy and MSI only use one vector */
1863         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1864                 q_vectors = 1;
1865
1866         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
1867                 q_vector = &adapter->q_vector[q_idx];
1868                 if (!q_vector->rxr_count)
1869                         continue;
1870                 napi_disable(&q_vector->napi);
1871         }
1872 }
1873
1874 #ifdef CONFIG_IXGBE_DCB
1875 /*
1876  * ixgbe_configure_dcb - Configure DCB hardware
1877  * @adapter: ixgbe adapter struct
1878  *
1879  * This is called by the driver on open to configure the DCB hardware.
1880  * This is also called by the gennetlink interface when reconfiguring
1881  * the DCB state.
1882  */
1883 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
1884 {
1885         struct ixgbe_hw *hw = &adapter->hw;
1886         u32 txdctl, vlnctrl;
1887         int i, j;
1888
1889         ixgbe_dcb_check_config(&adapter->dcb_cfg);
1890         ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG);
1891         ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG);
1892
1893         /* reconfigure the hardware */
1894         ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
1895
1896         for (i = 0; i < adapter->num_tx_queues; i++) {
1897                 j = adapter->tx_ring[i].reg_idx;
1898                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
1899                 /* PThresh workaround for Tx hang with DFP enabled. */
1900                 txdctl |= 32;
1901                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
1902         }
1903         /* Enable VLAN tag insert/strip */
1904         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1905         vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
1906         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1907         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1908         hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
1909 }
1910
1911 #endif
1912 static void ixgbe_configure(struct ixgbe_adapter *adapter)
1913 {
1914         struct net_device *netdev = adapter->netdev;
1915         int i;
1916
1917         ixgbe_set_rx_mode(netdev);
1918
1919         ixgbe_restore_vlan(adapter);
1920 #ifdef CONFIG_IXGBE_DCB
1921         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
1922                 netif_set_gso_max_size(netdev, 32768);
1923                 ixgbe_configure_dcb(adapter);
1924         } else {
1925                 netif_set_gso_max_size(netdev, 65536);
1926         }
1927 #else
1928         netif_set_gso_max_size(netdev, 65536);
1929 #endif
1930
1931         ixgbe_configure_tx(adapter);
1932         ixgbe_configure_rx(adapter);
1933         for (i = 0; i < adapter->num_rx_queues; i++)
1934                 ixgbe_alloc_rx_buffers(adapter, &adapter->rx_ring[i],
1935                                        (adapter->rx_ring[i].count - 1));
1936 }
1937
1938 /**
1939  * ixgbe_link_config - set up initial link with default speed and duplex
1940  * @hw: pointer to private hardware struct
1941  *
1942  * Returns 0 on success, negative on failure
1943  **/
1944 static int ixgbe_link_config(struct ixgbe_hw *hw)
1945 {
1946         u32 autoneg;
1947         bool link_up = false;
1948         u32 ret = IXGBE_ERR_LINK_SETUP;
1949
1950         if (hw->mac.ops.check_link)
1951                 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
1952
1953         if (ret)
1954                 goto link_cfg_out;
1955
1956         if (hw->mac.ops.get_link_capabilities)
1957                 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
1958                                                         &hw->mac.autoneg);
1959         if (ret)
1960                 goto link_cfg_out;
1961
1962         if (hw->mac.ops.setup_link_speed)
1963                 ret = hw->mac.ops.setup_link_speed(hw, autoneg, true, link_up);
1964
1965 link_cfg_out:
1966         return ret;
1967 }
1968
1969 static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
1970 {
1971         struct net_device *netdev = adapter->netdev;
1972         struct ixgbe_hw *hw = &adapter->hw;
1973         int i, j = 0;
1974         int err;
1975         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1976         u32 txdctl, rxdctl, mhadd;
1977         u32 gpie;
1978
1979         ixgbe_get_hw_control(adapter);
1980
1981         if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
1982             (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
1983                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1984                         gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
1985                                 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
1986                 } else {
1987                         /* MSI only */
1988                         gpie = 0;
1989                 }
1990                 /* XXX: to interrupt immediately for EICS writes, enable this */
1991                 /* gpie |= IXGBE_GPIE_EIMEN; */
1992                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
1993         }
1994
1995         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
1996                 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
1997                  * specifically only auto mask tx and rx interrupts */
1998                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
1999         }
2000
2001         /* Enable fan failure interrupt if media type is copper */
2002         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2003                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2004                 gpie |= IXGBE_SDP1_GPIEN;
2005                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2006         }
2007
2008         mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
2009         if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2010                 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2011                 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2012
2013                 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2014         }
2015
2016         for (i = 0; i < adapter->num_tx_queues; i++) {
2017                 j = adapter->tx_ring[i].reg_idx;
2018                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2019                 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2020                 txdctl |= (8 << 16);
2021                 txdctl |= IXGBE_TXDCTL_ENABLE;
2022                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2023         }
2024
2025         for (i = 0; i < adapter->num_rx_queues; i++) {
2026                 j = adapter->rx_ring[i].reg_idx;
2027                 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2028                 /* enable PTHRESH=32 descriptors (half the internal cache)
2029                  * and HTHRESH=0 descriptors (to minimize latency on fetch),
2030                  * this also removes a pesky rx_no_buffer_count increment */
2031                 rxdctl |= 0x0020;
2032                 rxdctl |= IXGBE_RXDCTL_ENABLE;
2033                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
2034         }
2035         /* enable all receives */
2036         rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2037         rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
2038         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxdctl);
2039
2040         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2041                 ixgbe_configure_msix(adapter);
2042         else
2043                 ixgbe_configure_msi_and_legacy(adapter);
2044
2045         ixgbe_napi_add_all(adapter);
2046
2047         clear_bit(__IXGBE_DOWN, &adapter->state);
2048         ixgbe_napi_enable_all(adapter);
2049
2050         /* clear any pending interrupts, may auto mask */
2051         IXGBE_READ_REG(hw, IXGBE_EICR);
2052
2053         ixgbe_irq_enable(adapter);
2054
2055         err = ixgbe_link_config(hw);
2056         if (err)
2057                 dev_err(&adapter->pdev->dev, "link_config FAILED %d\n", err);
2058
2059         /* enable transmits */
2060         netif_tx_start_all_queues(netdev);
2061
2062         /* bring the link up in the watchdog, this could race with our first
2063          * link up interrupt but shouldn't be a problem */
2064         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2065         adapter->link_check_timeout = jiffies;
2066         mod_timer(&adapter->watchdog_timer, jiffies);
2067         return 0;
2068 }
2069
2070 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
2071 {
2072         WARN_ON(in_interrupt());
2073         while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
2074                 msleep(1);
2075         ixgbe_down(adapter);
2076         ixgbe_up(adapter);
2077         clear_bit(__IXGBE_RESETTING, &adapter->state);
2078 }
2079
2080 int ixgbe_up(struct ixgbe_adapter *adapter)
2081 {
2082         /* hardware has been reset, we need to reload some things */
2083         ixgbe_configure(adapter);
2084
2085         return ixgbe_up_complete(adapter);
2086 }
2087
2088 void ixgbe_reset(struct ixgbe_adapter *adapter)
2089 {
2090         struct ixgbe_hw *hw = &adapter->hw;
2091         if (hw->mac.ops.init_hw(hw))
2092                 dev_err(&adapter->pdev->dev, "Hardware Error\n");
2093
2094         /* reprogram the RAR[0] in case user changed it. */
2095         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2096
2097 }
2098
2099 /**
2100  * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
2101  * @adapter: board private structure
2102  * @rx_ring: ring to free buffers from
2103  **/
2104 static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
2105                                 struct ixgbe_ring *rx_ring)
2106 {
2107         struct pci_dev *pdev = adapter->pdev;
2108         unsigned long size;
2109         unsigned int i;
2110
2111         /* Free all the Rx ring sk_buffs */
2112
2113         for (i = 0; i < rx_ring->count; i++) {
2114                 struct ixgbe_rx_buffer *rx_buffer_info;
2115
2116                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
2117                 if (rx_buffer_info->dma) {
2118                         pci_unmap_single(pdev, rx_buffer_info->dma,
2119                                          rx_ring->rx_buf_len,
2120                                          PCI_DMA_FROMDEVICE);
2121                         rx_buffer_info->dma = 0;
2122                 }
2123                 if (rx_buffer_info->skb) {
2124                         dev_kfree_skb(rx_buffer_info->skb);
2125                         rx_buffer_info->skb = NULL;
2126                 }
2127                 if (!rx_buffer_info->page)
2128                         continue;
2129                 pci_unmap_page(pdev, rx_buffer_info->page_dma, PAGE_SIZE / 2,
2130                                PCI_DMA_FROMDEVICE);
2131                 rx_buffer_info->page_dma = 0;
2132                 put_page(rx_buffer_info->page);
2133                 rx_buffer_info->page = NULL;
2134                 rx_buffer_info->page_offset = 0;
2135         }
2136
2137         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
2138         memset(rx_ring->rx_buffer_info, 0, size);
2139
2140         /* Zero out the descriptor ring */
2141         memset(rx_ring->desc, 0, rx_ring->size);
2142
2143         rx_ring->next_to_clean = 0;
2144         rx_ring->next_to_use = 0;
2145
2146         writel(0, adapter->hw.hw_addr + rx_ring->head);
2147         writel(0, adapter->hw.hw_addr + rx_ring->tail);
2148 }
2149
2150 /**
2151  * ixgbe_clean_tx_ring - Free Tx Buffers
2152  * @adapter: board private structure
2153  * @tx_ring: ring to be cleaned
2154  **/
2155 static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
2156                                 struct ixgbe_ring *tx_ring)
2157 {
2158         struct ixgbe_tx_buffer *tx_buffer_info;
2159         unsigned long size;
2160         unsigned int i;
2161
2162         /* Free all the Tx ring sk_buffs */
2163
2164         for (i = 0; i < tx_ring->count; i++) {
2165                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
2166                 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
2167         }
2168
2169         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
2170         memset(tx_ring->tx_buffer_info, 0, size);
2171
2172         /* Zero out the descriptor ring */
2173         memset(tx_ring->desc, 0, tx_ring->size);
2174
2175         tx_ring->next_to_use = 0;
2176         tx_ring->next_to_clean = 0;
2177
2178         writel(0, adapter->hw.hw_addr + tx_ring->head);
2179         writel(0, adapter->hw.hw_addr + tx_ring->tail);
2180 }
2181
2182 /**
2183  * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
2184  * @adapter: board private structure
2185  **/
2186 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
2187 {
2188         int i;
2189
2190         for (i = 0; i < adapter->num_rx_queues; i++)
2191                 ixgbe_clean_rx_ring(adapter, &adapter->rx_ring[i]);
2192 }
2193
2194 /**
2195  * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
2196  * @adapter: board private structure
2197  **/
2198 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
2199 {
2200         int i;
2201
2202         for (i = 0; i < adapter->num_tx_queues; i++)
2203                 ixgbe_clean_tx_ring(adapter, &adapter->tx_ring[i]);
2204 }
2205
2206 void ixgbe_down(struct ixgbe_adapter *adapter)
2207 {
2208         struct net_device *netdev = adapter->netdev;
2209         struct ixgbe_hw *hw = &adapter->hw;
2210         u32 rxctrl;
2211         u32 txdctl;
2212         int i, j;
2213
2214         /* signal that we are down to the interrupt handler */
2215         set_bit(__IXGBE_DOWN, &adapter->state);
2216
2217         /* disable receives */
2218         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2219         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
2220
2221         netif_tx_disable(netdev);
2222
2223         IXGBE_WRITE_FLUSH(hw);
2224         msleep(10);
2225
2226         netif_tx_stop_all_queues(netdev);
2227
2228         ixgbe_irq_disable(adapter);
2229
2230         ixgbe_napi_disable_all(adapter);
2231
2232         del_timer_sync(&adapter->watchdog_timer);
2233         cancel_work_sync(&adapter->watchdog_task);
2234
2235         /* disable transmits in the hardware now that interrupts are off */
2236         for (i = 0; i < adapter->num_tx_queues; i++) {
2237                 j = adapter->tx_ring[i].reg_idx;
2238                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2239                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
2240                                 (txdctl & ~IXGBE_TXDCTL_ENABLE));
2241         }
2242
2243         netif_carrier_off(netdev);
2244
2245 #ifdef CONFIG_IXGBE_DCA
2246         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
2247                 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
2248                 dca_remove_requester(&adapter->pdev->dev);
2249         }
2250
2251 #endif
2252         if (!pci_channel_offline(adapter->pdev))
2253                 ixgbe_reset(adapter);
2254         ixgbe_clean_all_tx_rings(adapter);
2255         ixgbe_clean_all_rx_rings(adapter);
2256
2257 #ifdef CONFIG_IXGBE_DCA
2258         /* since we reset the hardware DCA settings were cleared */
2259         if (dca_add_requester(&adapter->pdev->dev) == 0) {
2260                 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
2261                 /* always use CB2 mode, difference is masked
2262                  * in the CB driver */
2263                 IXGBE_WRITE_REG(hw, IXGBE_DCA_CTRL, 2);
2264                 ixgbe_setup_dca(adapter);
2265         }
2266 #endif
2267 }
2268
2269 /**
2270  * ixgbe_poll - NAPI Rx polling callback
2271  * @napi: structure for representing this polling device
2272  * @budget: how many packets driver is allowed to clean
2273  *
2274  * This function is used for legacy and MSI, NAPI mode
2275  **/
2276 static int ixgbe_poll(struct napi_struct *napi, int budget)
2277 {
2278         struct ixgbe_q_vector *q_vector = container_of(napi,
2279                                                   struct ixgbe_q_vector, napi);
2280         struct ixgbe_adapter *adapter = q_vector->adapter;
2281         int tx_cleaned, work_done = 0;
2282
2283 #ifdef CONFIG_IXGBE_DCA
2284         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
2285                 ixgbe_update_tx_dca(adapter, adapter->tx_ring);
2286                 ixgbe_update_rx_dca(adapter, adapter->rx_ring);
2287         }
2288 #endif
2289
2290         tx_cleaned = ixgbe_clean_tx_irq(adapter, adapter->tx_ring);
2291         ixgbe_clean_rx_irq(q_vector, adapter->rx_ring, &work_done, budget);
2292
2293         if (tx_cleaned)
2294                 work_done = budget;
2295
2296         /* If budget not fully consumed, exit the polling mode */
2297         if (work_done < budget) {
2298                 napi_complete(napi);
2299                 if (adapter->itr_setting & 3)
2300                         ixgbe_set_itr(adapter);
2301                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2302                         ixgbe_irq_enable(adapter);
2303         }
2304         return work_done;
2305 }
2306
2307 /**
2308  * ixgbe_tx_timeout - Respond to a Tx Hang
2309  * @netdev: network interface device structure
2310  **/
2311 static void ixgbe_tx_timeout(struct net_device *netdev)
2312 {
2313         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2314
2315         /* Do the reset outside of interrupt context */
2316         schedule_work(&adapter->reset_task);
2317 }
2318
2319 static void ixgbe_reset_task(struct work_struct *work)
2320 {
2321         struct ixgbe_adapter *adapter;
2322         adapter = container_of(work, struct ixgbe_adapter, reset_task);
2323
2324         /* If we're already down or resetting, just bail */
2325         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
2326             test_bit(__IXGBE_RESETTING, &adapter->state))
2327                 return;
2328
2329         adapter->tx_timeout_count++;
2330
2331         ixgbe_reinit_locked(adapter);
2332 }
2333
2334 #ifdef CONFIG_IXGBE_DCB
2335 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
2336 {
2337         bool ret = false;
2338
2339         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2340                 adapter->ring_feature[RING_F_DCB].mask = 0x7 << 3;
2341                 adapter->num_rx_queues =
2342                                       adapter->ring_feature[RING_F_DCB].indices;
2343                 adapter->num_tx_queues =
2344                                       adapter->ring_feature[RING_F_DCB].indices;
2345                 ret = true;
2346         } else {
2347                 ret = false;
2348         }
2349
2350         return ret;
2351 }
2352 #endif
2353
2354 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
2355 {
2356         bool ret = false;
2357
2358         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
2359                 adapter->ring_feature[RING_F_RSS].mask = 0xF;
2360                 adapter->num_rx_queues =
2361                                       adapter->ring_feature[RING_F_RSS].indices;
2362                 adapter->num_tx_queues =
2363                                       adapter->ring_feature[RING_F_RSS].indices;
2364                 ret = true;
2365         } else {
2366                 ret = false;
2367         }
2368
2369         return ret;
2370 }
2371
2372 static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
2373 {
2374         /* Start with base case */
2375         adapter->num_rx_queues = 1;
2376         adapter->num_tx_queues = 1;
2377
2378 #ifdef CONFIG_IXGBE_DCB
2379         if (ixgbe_set_dcb_queues(adapter))
2380                 return;
2381
2382 #endif
2383         if (ixgbe_set_rss_queues(adapter))
2384                 return;
2385 }
2386
2387 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
2388                                        int vectors)
2389 {
2390         int err, vector_threshold;
2391
2392         /* We'll want at least 3 (vector_threshold):
2393          * 1) TxQ[0] Cleanup
2394          * 2) RxQ[0] Cleanup
2395          * 3) Other (Link Status Change, etc.)
2396          * 4) TCP Timer (optional)
2397          */
2398         vector_threshold = MIN_MSIX_COUNT;
2399
2400         /* The more we get, the more we will assign to Tx/Rx Cleanup
2401          * for the separate queues...where Rx Cleanup >= Tx Cleanup.
2402          * Right now, we simply care about how many we'll get; we'll
2403          * set them up later while requesting irq's.
2404          */
2405         while (vectors >= vector_threshold) {
2406                 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
2407                                       vectors);
2408                 if (!err) /* Success in acquiring all requested vectors. */
2409                         break;
2410                 else if (err < 0)
2411                         vectors = 0; /* Nasty failure, quit now */
2412                 else /* err == number of vectors we should try again with */
2413                         vectors = err;
2414         }
2415
2416         if (vectors < vector_threshold) {
2417                 /* Can't allocate enough MSI-X interrupts?  Oh well.
2418                  * This just means we'll go with either a single MSI
2419                  * vector or fall back to legacy interrupts.
2420                  */
2421                 DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n");
2422                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2423                 kfree(adapter->msix_entries);
2424                 adapter->msix_entries = NULL;
2425                 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
2426                 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
2427                 ixgbe_set_num_queues(adapter);
2428         } else {
2429                 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
2430                 /*
2431                  * Adjust for only the vectors we'll use, which is minimum
2432                  * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
2433                  * vectors we were allocated.
2434                  */
2435                 adapter->num_msix_vectors = min(vectors,
2436                                    adapter->max_msix_q_vectors + NON_Q_VECTORS);
2437         }
2438 }
2439
2440 /**
2441  * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
2442  * @adapter: board private structure to initialize
2443  *
2444  * Cache the descriptor ring offsets for RSS to the assigned rings.
2445  *
2446  **/
2447 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
2448 {
2449         int i;
2450         bool ret = false;
2451
2452         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
2453                 for (i = 0; i < adapter->num_rx_queues; i++)
2454                         adapter->rx_ring[i].reg_idx = i;
2455                 for (i = 0; i < adapter->num_tx_queues; i++)
2456                         adapter->tx_ring[i].reg_idx = i;
2457                 ret = true;
2458         } else {
2459                 ret = false;
2460         }
2461
2462         return ret;
2463 }
2464
2465 #ifdef CONFIG_IXGBE_DCB
2466 /**
2467  * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
2468  * @adapter: board private structure to initialize
2469  *
2470  * Cache the descriptor ring offsets for DCB to the assigned rings.
2471  *
2472  **/
2473 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
2474 {
2475         int i;
2476         bool ret = false;
2477         int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
2478
2479         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2480                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2481                         /* the number of queues is assumed to be symmetric */
2482                         for (i = 0; i < dcb_i; i++) {
2483                                 adapter->rx_ring[i].reg_idx = i << 3;
2484                                 adapter->tx_ring[i].reg_idx = i << 2;
2485                         }
2486                         ret = true;
2487                 } else {
2488                         ret = false;
2489                 }
2490         } else {
2491                 ret = false;
2492         }
2493
2494         return ret;
2495 }
2496 #endif
2497
2498 /**
2499  * ixgbe_cache_ring_register - Descriptor ring to register mapping
2500  * @adapter: board private structure to initialize
2501  *
2502  * Once we know the feature-set enabled for the device, we'll cache
2503  * the register offset the descriptor ring is assigned to.
2504  *
2505  * Note, the order the various feature calls is important.  It must start with
2506  * the "most" features enabled at the same time, then trickle down to the
2507  * least amount of features turned on at once.
2508  **/
2509 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
2510 {
2511         /* start with default case */
2512         adapter->rx_ring[0].reg_idx = 0;
2513         adapter->tx_ring[0].reg_idx = 0;
2514
2515 #ifdef CONFIG_IXGBE_DCB
2516         if (ixgbe_cache_ring_dcb(adapter))
2517                 return;
2518
2519 #endif
2520         if (ixgbe_cache_ring_rss(adapter))
2521                 return;
2522 }
2523
2524 /**
2525  * ixgbe_alloc_queues - Allocate memory for all rings
2526  * @adapter: board private structure to initialize
2527  *
2528  * We allocate one ring per queue at run-time since we don't know the
2529  * number of queues at compile-time.
2530  **/
2531 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
2532 {
2533         int i;
2534
2535         adapter->tx_ring = kcalloc(adapter->num_tx_queues,
2536                                    sizeof(struct ixgbe_ring), GFP_KERNEL);
2537         if (!adapter->tx_ring)
2538                 goto err_tx_ring_allocation;
2539
2540         adapter->rx_ring = kcalloc(adapter->num_rx_queues,
2541                                    sizeof(struct ixgbe_ring), GFP_KERNEL);
2542         if (!adapter->rx_ring)
2543                 goto err_rx_ring_allocation;
2544
2545         for (i = 0; i < adapter->num_tx_queues; i++) {
2546                 adapter->tx_ring[i].count = adapter->tx_ring_count;
2547                 adapter->tx_ring[i].queue_index = i;
2548         }
2549
2550         for (i = 0; i < adapter->num_rx_queues; i++) {
2551                 adapter->rx_ring[i].count = adapter->rx_ring_count;
2552                 adapter->rx_ring[i].queue_index = i;
2553         }
2554
2555         ixgbe_cache_ring_register(adapter);
2556
2557         return 0;
2558
2559 err_rx_ring_allocation:
2560         kfree(adapter->tx_ring);
2561 err_tx_ring_allocation:
2562         return -ENOMEM;
2563 }
2564
2565 /**
2566  * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
2567  * @adapter: board private structure to initialize
2568  *
2569  * Attempt to configure the interrupts using the best available
2570  * capabilities of the hardware and the kernel.
2571  **/
2572 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
2573 {
2574         int err = 0;
2575         int vector, v_budget;
2576
2577         /*
2578          * It's easy to be greedy for MSI-X vectors, but it really
2579          * doesn't do us much good if we have a lot more vectors
2580          * than CPU's.  So let's be conservative and only ask for
2581          * (roughly) twice the number of vectors as there are CPU's.
2582          */
2583         v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
2584                        (int)(num_online_cpus() * 2)) + NON_Q_VECTORS;
2585
2586         /*
2587          * At the same time, hardware can only support a maximum of
2588          * MAX_MSIX_COUNT vectors.  With features such as RSS and VMDq,
2589          * we can easily reach upwards of 64 Rx descriptor queues and
2590          * 32 Tx queues.  Thus, we cap it off in those rare cases where
2591          * the cpu count also exceeds our vector limit.
2592          */
2593         v_budget = min(v_budget, MAX_MSIX_COUNT);
2594
2595         /* A failure in MSI-X entry allocation isn't fatal, but it does
2596          * mean we disable MSI-X capabilities of the adapter. */
2597         adapter->msix_entries = kcalloc(v_budget,
2598                                         sizeof(struct msix_entry), GFP_KERNEL);
2599         if (!adapter->msix_entries) {
2600                 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
2601                 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
2602                 ixgbe_set_num_queues(adapter);
2603                 kfree(adapter->tx_ring);
2604                 kfree(adapter->rx_ring);
2605                 err = ixgbe_alloc_queues(adapter);
2606                 if (err) {
2607                         DPRINTK(PROBE, ERR, "Unable to allocate memory "
2608                                 "for queues\n");
2609                         goto out;
2610                 }
2611
2612                 goto try_msi;
2613         }
2614
2615         for (vector = 0; vector < v_budget; vector++)
2616                 adapter->msix_entries[vector].entry = vector;
2617
2618         ixgbe_acquire_msix_vectors(adapter, v_budget);
2619
2620         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2621                 goto out;
2622
2623 try_msi:
2624         err = pci_enable_msi(adapter->pdev);
2625         if (!err) {
2626                 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
2627         } else {
2628                 DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, "
2629                         "falling back to legacy.  Error: %d\n", err);
2630                 /* reset err */
2631                 err = 0;
2632         }
2633
2634 out:
2635         /* Notify the stack of the (possibly) reduced Tx Queue count. */
2636         adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
2637
2638         return err;
2639 }
2640
2641 void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
2642 {
2643         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2644                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2645                 pci_disable_msix(adapter->pdev);
2646                 kfree(adapter->msix_entries);
2647                 adapter->msix_entries = NULL;
2648         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
2649                 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
2650                 pci_disable_msi(adapter->pdev);
2651         }
2652         return;
2653 }
2654
2655 /**
2656  * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
2657  * @adapter: board private structure to initialize
2658  *
2659  * We determine which interrupt scheme to use based on...
2660  * - Kernel support (MSI, MSI-X)
2661  *   - which can be user-defined (via MODULE_PARAM)
2662  * - Hardware queue count (num_*_queues)
2663  *   - defined by miscellaneous hardware support/features (RSS, etc.)
2664  **/
2665 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
2666 {
2667         int err;
2668
2669         /* Number of supported queues */
2670         ixgbe_set_num_queues(adapter);
2671
2672         err = ixgbe_alloc_queues(adapter);
2673         if (err) {
2674                 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
2675                 goto err_alloc_queues;
2676         }
2677
2678         err = ixgbe_set_interrupt_capability(adapter);
2679         if (err) {
2680                 DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n");
2681                 goto err_set_interrupt;
2682         }
2683
2684         DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, "
2685                 "Tx Queue count = %u\n",
2686                 (adapter->num_rx_queues > 1) ? "Enabled" :
2687                 "Disabled", adapter->num_rx_queues, adapter->num_tx_queues);
2688
2689         set_bit(__IXGBE_DOWN, &adapter->state);
2690
2691         return 0;
2692
2693 err_set_interrupt:
2694         kfree(adapter->tx_ring);
2695         kfree(adapter->rx_ring);
2696 err_alloc_queues:
2697         return err;
2698 }
2699
2700 /**
2701  * ixgbe_sfp_timer - worker thread to find a missing module
2702  * @data: pointer to our adapter struct
2703  **/
2704 static void ixgbe_sfp_timer(unsigned long data)
2705 {
2706         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
2707
2708         /* Do the sfp_timer outside of interrupt context due to the
2709          * delays that sfp+ detection requires
2710          */
2711         schedule_work(&adapter->sfp_task);
2712 }
2713
2714 /**
2715  * ixgbe_sfp_task - worker thread to find a missing module
2716  * @work: pointer to work_struct containing our data
2717  **/
2718 static void ixgbe_sfp_task(struct work_struct *work)
2719 {
2720         struct ixgbe_adapter *adapter = container_of(work,
2721                                                      struct ixgbe_adapter,
2722                                                      sfp_task);
2723         struct ixgbe_hw *hw = &adapter->hw;
2724
2725         if ((hw->phy.type == ixgbe_phy_nl) &&
2726             (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
2727                 s32 ret = hw->phy.ops.identify_sfp(hw);
2728                 if (ret)
2729                         goto reschedule;
2730                 ret = hw->phy.ops.reset(hw);
2731                 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
2732                         DPRINTK(PROBE, ERR, "failed to initialize because an "
2733                                 "unsupported SFP+ module type was detected.\n"
2734                                 "Reload the driver after installing a "
2735                                 "supported module.\n");
2736                         unregister_netdev(adapter->netdev);
2737                 } else {
2738                         DPRINTK(PROBE, INFO, "detected SFP+: %d\n",
2739                                 hw->phy.sfp_type);
2740                 }
2741                 /* don't need this routine any more */
2742                 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
2743         }
2744         return;
2745 reschedule:
2746         if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
2747                 mod_timer(&adapter->sfp_timer,
2748                           round_jiffies(jiffies + (2 * HZ)));
2749 }
2750
2751 /**
2752  * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
2753  * @adapter: board private structure to initialize
2754  *
2755  * ixgbe_sw_init initializes the Adapter private data structure.
2756  * Fields are initialized based on PCI device information and
2757  * OS network device settings (MTU size).
2758  **/
2759 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
2760 {
2761         struct ixgbe_hw *hw = &adapter->hw;
2762         struct pci_dev *pdev = adapter->pdev;
2763         unsigned int rss;
2764 #ifdef CONFIG_IXGBE_DCB
2765         int j;
2766         struct tc_configuration *tc;
2767 #endif
2768
2769         /* PCI config space info */
2770
2771         hw->vendor_id = pdev->vendor;
2772         hw->device_id = pdev->device;
2773         hw->revision_id = pdev->revision;
2774         hw->subsystem_vendor_id = pdev->subsystem_vendor;
2775         hw->subsystem_device_id = pdev->subsystem_device;
2776
2777         /* Set capability flags */
2778         rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
2779         adapter->ring_feature[RING_F_RSS].indices = rss;
2780         adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
2781         adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
2782         adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
2783
2784 #ifdef CONFIG_IXGBE_DCB
2785         /* Configure DCB traffic classes */
2786         for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
2787                 tc = &adapter->dcb_cfg.tc_config[j];
2788                 tc->path[DCB_TX_CONFIG].bwg_id = 0;
2789                 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
2790                 tc->path[DCB_RX_CONFIG].bwg_id = 0;
2791                 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
2792                 tc->dcb_pfc = pfc_disabled;
2793         }
2794         adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
2795         adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
2796         adapter->dcb_cfg.rx_pba_cfg = pba_equal;
2797         adapter->dcb_cfg.round_robin_enable = false;
2798         adapter->dcb_set_bitmap = 0x00;
2799         ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
2800                            adapter->ring_feature[RING_F_DCB].indices);
2801
2802 #endif
2803         if (hw->mac.ops.get_media_type &&
2804             (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper))
2805                 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
2806
2807         /* default flow control settings */
2808         hw->fc.requested_mode = ixgbe_fc_none;
2809         hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
2810         hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
2811         hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
2812         hw->fc.send_xon = true;
2813
2814         /* enable itr by default in dynamic mode */
2815         adapter->itr_setting = 1;
2816         adapter->eitr_param = 20000;
2817
2818         /* set defaults for eitr in MegaBytes */
2819         adapter->eitr_low = 10;
2820         adapter->eitr_high = 20;
2821
2822         /* set default ring sizes */
2823         adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
2824         adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
2825
2826         /* initialize eeprom parameters */
2827         if (ixgbe_init_eeprom_params_generic(hw)) {
2828                 dev_err(&pdev->dev, "EEPROM initialization failed\n");
2829                 return -EIO;
2830         }
2831
2832         /* enable rx csum by default */
2833         adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
2834
2835         set_bit(__IXGBE_DOWN, &adapter->state);
2836
2837         return 0;
2838 }
2839
2840 /**
2841  * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
2842  * @adapter: board private structure
2843  * @tx_ring:    tx descriptor ring (for a specific queue) to setup
2844  *
2845  * Return 0 on success, negative on failure
2846  **/
2847 int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
2848                              struct ixgbe_ring *tx_ring)
2849 {
2850         struct pci_dev *pdev = adapter->pdev;
2851         int size;
2852
2853         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
2854         tx_ring->tx_buffer_info = vmalloc(size);
2855         if (!tx_ring->tx_buffer_info)
2856                 goto err;
2857         memset(tx_ring->tx_buffer_info, 0, size);
2858
2859         /* round up to nearest 4K */
2860         tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
2861         tx_ring->size = ALIGN(tx_ring->size, 4096);
2862
2863         tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
2864                                              &tx_ring->dma);
2865         if (!tx_ring->desc)
2866                 goto err;
2867
2868         tx_ring->next_to_use = 0;
2869         tx_ring->next_to_clean = 0;
2870         tx_ring->work_limit = tx_ring->count;
2871         return 0;
2872
2873 err:
2874         vfree(tx_ring->tx_buffer_info);
2875         tx_ring->tx_buffer_info = NULL;
2876         DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit "
2877                             "descriptor ring\n");
2878         return -ENOMEM;
2879 }
2880
2881 /**
2882  * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
2883  * @adapter: board private structure
2884  *
2885  * If this function returns with an error, then it's possible one or
2886  * more of the rings is populated (while the rest are not).  It is the
2887  * callers duty to clean those orphaned rings.
2888  *
2889  * Return 0 on success, negative on failure
2890  **/
2891 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
2892 {
2893         int i, err = 0;
2894
2895         for (i = 0; i < adapter->num_tx_queues; i++) {
2896                 err = ixgbe_setup_tx_resources(adapter, &adapter->tx_ring[i]);
2897                 if (!err)
2898                         continue;
2899                 DPRINTK(PROBE, ERR, "Allocation for Tx Queue %u failed\n", i);
2900                 break;
2901         }
2902
2903         return err;
2904 }
2905
2906 /**
2907  * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
2908  * @adapter: board private structure
2909  * @rx_ring:    rx descriptor ring (for a specific queue) to setup
2910  *
2911  * Returns 0 on success, negative on failure
2912  **/
2913 int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
2914                              struct ixgbe_ring *rx_ring)
2915 {
2916         struct pci_dev *pdev = adapter->pdev;
2917         int size;
2918
2919         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
2920         rx_ring->rx_buffer_info = vmalloc(size);
2921         if (!rx_ring->rx_buffer_info) {
2922                 DPRINTK(PROBE, ERR,
2923                         "vmalloc allocation failed for the rx desc ring\n");
2924                 goto alloc_failed;
2925         }
2926         memset(rx_ring->rx_buffer_info, 0, size);
2927
2928         /* Round up to nearest 4K */
2929         rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
2930         rx_ring->size = ALIGN(rx_ring->size, 4096);
2931
2932         rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, &rx_ring->dma);
2933
2934         if (!rx_ring->desc) {
2935                 DPRINTK(PROBE, ERR,
2936                         "Memory allocation failed for the rx desc ring\n");
2937                 vfree(rx_ring->rx_buffer_info);
2938                 goto alloc_failed;
2939         }
2940
2941         rx_ring->next_to_clean = 0;
2942         rx_ring->next_to_use = 0;
2943
2944         return 0;
2945
2946 alloc_failed:
2947         return -ENOMEM;
2948 }
2949
2950 /**
2951  * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
2952  * @adapter: board private structure
2953  *
2954  * If this function returns with an error, then it's possible one or
2955  * more of the rings is populated (while the rest are not).  It is the
2956  * callers duty to clean those orphaned rings.
2957  *
2958  * Return 0 on success, negative on failure
2959  **/
2960
2961 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
2962 {
2963         int i, err = 0;
2964
2965         for (i = 0; i < adapter->num_rx_queues; i++) {
2966                 err = ixgbe_setup_rx_resources(adapter, &adapter->rx_ring[i]);
2967                 if (!err)
2968                         continue;
2969                 DPRINTK(PROBE, ERR, "Allocation for Rx Queue %u failed\n", i);
2970                 break;
2971         }
2972
2973         return err;
2974 }
2975
2976 /**
2977  * ixgbe_free_tx_resources - Free Tx Resources per Queue
2978  * @adapter: board private structure
2979  * @tx_ring: Tx descriptor ring for a specific queue
2980  *
2981  * Free all transmit software resources
2982  **/
2983 void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
2984                              struct ixgbe_ring *tx_ring)
2985 {
2986         struct pci_dev *pdev = adapter->pdev;
2987
2988         ixgbe_clean_tx_ring(adapter, tx_ring);
2989
2990         vfree(tx_ring->tx_buffer_info);
2991         tx_ring->tx_buffer_info = NULL;
2992
2993         pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
2994
2995         tx_ring->desc = NULL;
2996 }
2997
2998 /**
2999  * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
3000  * @adapter: board private structure
3001  *
3002  * Free all transmit software resources
3003  **/
3004 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
3005 {
3006         int i;
3007
3008         for (i = 0; i < adapter->num_tx_queues; i++)
3009                 ixgbe_free_tx_resources(adapter, &adapter->tx_ring[i]);
3010 }
3011
3012 /**
3013  * ixgbe_free_rx_resources - Free Rx Resources
3014  * @adapter: board private structure
3015  * @rx_ring: ring to clean the resources from
3016  *
3017  * Free all receive software resources
3018  **/
3019 void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
3020                              struct ixgbe_ring *rx_ring)
3021 {
3022         struct pci_dev *pdev = adapter->pdev;
3023
3024         ixgbe_clean_rx_ring(adapter, rx_ring);
3025
3026         vfree(rx_ring->rx_buffer_info);
3027         rx_ring->rx_buffer_info = NULL;
3028
3029         pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
3030
3031         rx_ring->desc = NULL;
3032 }
3033
3034 /**
3035  * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
3036  * @adapter: board private structure
3037  *
3038  * Free all receive software resources
3039  **/
3040 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
3041 {
3042         int i;
3043
3044         for (i = 0; i < adapter->num_rx_queues; i++)
3045                 ixgbe_free_rx_resources(adapter, &adapter->rx_ring[i]);
3046 }
3047
3048 /**
3049  * ixgbe_change_mtu - Change the Maximum Transfer Unit
3050  * @netdev: network interface device structure
3051  * @new_mtu: new value for maximum frame size
3052  *
3053  * Returns 0 on success, negative on failure
3054  **/
3055 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
3056 {
3057         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3058         int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
3059
3060         /* MTU < 68 is an error and causes problems on some kernels */
3061         if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
3062                 return -EINVAL;
3063
3064         DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n",
3065                 netdev->mtu, new_mtu);
3066         /* must set new MTU before calling down or up */
3067         netdev->mtu = new_mtu;
3068
3069         if (netif_running(netdev))
3070                 ixgbe_reinit_locked(adapter);
3071
3072         return 0;
3073 }
3074
3075 /**
3076  * ixgbe_open - Called when a network interface is made active
3077  * @netdev: network interface device structure
3078  *
3079  * Returns 0 on success, negative value on failure
3080  *
3081  * The open entry point is called when a network interface is made
3082  * active by the system (IFF_UP).  At this point all resources needed
3083  * for transmit and receive operations are allocated, the interrupt
3084  * handler is registered with the OS, the watchdog timer is started,
3085  * and the stack is notified that the interface is ready.
3086  **/
3087 static int ixgbe_open(struct net_device *netdev)
3088 {
3089         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3090         int err;
3091
3092         /* disallow open during test */
3093         if (test_bit(__IXGBE_TESTING, &adapter->state))
3094                 return -EBUSY;
3095
3096         /* allocate transmit descriptors */
3097         err = ixgbe_setup_all_tx_resources(adapter);
3098         if (err)
3099                 goto err_setup_tx;
3100
3101         /* allocate receive descriptors */
3102         err = ixgbe_setup_all_rx_resources(adapter);
3103         if (err)
3104                 goto err_setup_rx;
3105
3106         ixgbe_configure(adapter);
3107
3108         err = ixgbe_request_irq(adapter);
3109         if (err)
3110                 goto err_req_irq;
3111
3112         err = ixgbe_up_complete(adapter);
3113         if (err)
3114                 goto err_up;
3115
3116         netif_tx_start_all_queues(netdev);
3117
3118         return 0;
3119
3120 err_up:
3121         ixgbe_release_hw_control(adapter);
3122         ixgbe_free_irq(adapter);
3123 err_req_irq:
3124         ixgbe_free_all_rx_resources(adapter);
3125 err_setup_rx:
3126         ixgbe_free_all_tx_resources(adapter);
3127 err_setup_tx:
3128         ixgbe_reset(adapter);
3129
3130         return err;
3131 }
3132
3133 /**
3134  * ixgbe_close - Disables a network interface
3135  * @netdev: network interface device structure
3136  *
3137  * Returns 0, this is not allowed to fail
3138  *
3139  * The close entry point is called when an interface is de-activated
3140  * by the OS.  The hardware is still under the drivers control, but
3141  * needs to be disabled.  A global MAC reset is issued to stop the
3142  * hardware, and all transmit and receive resources are freed.
3143  **/
3144 static int ixgbe_close(struct net_device *netdev)
3145 {
3146         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3147
3148         ixgbe_down(adapter);
3149         ixgbe_free_irq(adapter);
3150
3151         ixgbe_free_all_tx_resources(adapter);
3152         ixgbe_free_all_rx_resources(adapter);
3153
3154         ixgbe_release_hw_control(adapter);
3155
3156         return 0;
3157 }
3158
3159 /**
3160  * ixgbe_napi_add_all - prep napi structs for use
3161  * @adapter: private struct
3162  * helper function to napi_add each possible q_vector->napi
3163  */
3164 void ixgbe_napi_add_all(struct ixgbe_adapter *adapter)
3165 {
3166         int q_idx, q_vectors;
3167         struct net_device *netdev = adapter->netdev;
3168         int (*poll)(struct napi_struct *, int);
3169
3170         /* check if we already have our netdev->napi_list populated */
3171         if (&netdev->napi_list != netdev->napi_list.next)
3172                 return;
3173
3174         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3175                 poll = &ixgbe_clean_rxonly;
3176                 /* Only enable as many vectors as we have rx queues. */
3177                 q_vectors = adapter->num_rx_queues;
3178         } else {
3179                 poll = &ixgbe_poll;
3180                 /* only one q_vector for legacy modes */
3181                 q_vectors = 1;
3182         }
3183
3184         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3185                 struct ixgbe_q_vector *q_vector = &adapter->q_vector[q_idx];
3186                 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
3187         }
3188 }
3189
3190 void ixgbe_napi_del_all(struct ixgbe_adapter *adapter)
3191 {
3192         int q_idx;
3193         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3194
3195         /* legacy and MSI only use one vector */
3196         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3197                 q_vectors = 1;
3198
3199         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3200                 struct ixgbe_q_vector *q_vector = &adapter->q_vector[q_idx];
3201                 if (!q_vector->rxr_count)
3202                         continue;
3203                 netif_napi_del(&q_vector->napi);
3204         }
3205 }
3206
3207 #ifdef CONFIG_PM
3208 static int ixgbe_resume(struct pci_dev *pdev)
3209 {
3210         struct net_device *netdev = pci_get_drvdata(pdev);
3211         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3212         u32 err;
3213
3214         pci_set_power_state(pdev, PCI_D0);
3215         pci_restore_state(pdev);
3216         err = pci_enable_device(pdev);
3217         if (err) {
3218                 printk(KERN_ERR "ixgbe: Cannot enable PCI device from "
3219                                 "suspend\n");
3220                 return err;
3221         }
3222         pci_set_master(pdev);
3223
3224         pci_enable_wake(pdev, PCI_D3hot, 0);
3225         pci_enable_wake(pdev, PCI_D3cold, 0);
3226
3227         err = ixgbe_init_interrupt_scheme(adapter);
3228         if (err) {
3229                 printk(KERN_ERR "ixgbe: Cannot initialize interrupts for "
3230                                 "device\n");
3231                 return err;
3232         }
3233
3234         ixgbe_napi_add_all(adapter);
3235         ixgbe_reset(adapter);
3236
3237         if (netif_running(netdev)) {
3238                 err = ixgbe_open(adapter->netdev);
3239                 if (err)
3240                         return err;
3241         }
3242
3243         netif_device_attach(netdev);
3244
3245         return 0;
3246 }
3247
3248 #endif /* CONFIG_PM */
3249 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
3250 {
3251         struct net_device *netdev = pci_get_drvdata(pdev);
3252         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3253 #ifdef CONFIG_PM
3254         int retval = 0;
3255 #endif
3256
3257         netif_device_detach(netdev);
3258
3259         if (netif_running(netdev)) {
3260                 ixgbe_down(adapter);
3261                 ixgbe_free_irq(adapter);
3262                 ixgbe_free_all_tx_resources(adapter);
3263                 ixgbe_free_all_rx_resources(adapter);
3264         }
3265         ixgbe_reset_interrupt_capability(adapter);
3266         ixgbe_napi_del_all(adapter);
3267         INIT_LIST_HEAD(&netdev->napi_list);
3268         kfree(adapter->tx_ring);
3269         kfree(adapter->rx_ring);
3270
3271 #ifdef CONFIG_PM
3272         retval = pci_save_state(pdev);
3273         if (retval)
3274                 return retval;
3275 #endif
3276
3277         pci_enable_wake(pdev, PCI_D3hot, 0);
3278         pci_enable_wake(pdev, PCI_D3cold, 0);
3279
3280         ixgbe_release_hw_control(adapter);
3281
3282         pci_disable_device(pdev);
3283
3284         pci_set_power_state(pdev, pci_choose_state(pdev, state));
3285
3286         return 0;
3287 }
3288
3289 static void ixgbe_shutdown(struct pci_dev *pdev)
3290 {
3291         ixgbe_suspend(pdev, PMSG_SUSPEND);
3292 }
3293
3294 /**
3295  * ixgbe_update_stats - Update the board statistics counters.
3296  * @adapter: board private structure
3297  **/
3298 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
3299 {
3300         struct ixgbe_hw *hw = &adapter->hw;
3301         u64 total_mpc = 0;
3302         u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
3303
3304         adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
3305         for (i = 0; i < 8; i++) {
3306                 /* for packet buffers not used, the register should read 0 */
3307                 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
3308                 missed_rx += mpc;
3309                 adapter->stats.mpc[i] += mpc;
3310                 total_mpc += adapter->stats.mpc[i];
3311                 adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
3312                 adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
3313                 adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
3314                 adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
3315                 adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
3316                 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
3317                                                             IXGBE_PXONRXC(i));
3318                 adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw,
3319                                                             IXGBE_PXONTXC(i));
3320                 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
3321                                                             IXGBE_PXOFFRXC(i));
3322                 adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw,
3323                                                             IXGBE_PXOFFTXC(i));
3324         }
3325         adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
3326         /* work around hardware counting issue */
3327         adapter->stats.gprc -= missed_rx;
3328
3329         /* 82598 hardware only has a 32 bit counter in the high register */
3330         adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
3331         adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
3332         adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
3333         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3334         adapter->stats.bprc += bprc;
3335         adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3336         adapter->stats.mprc -= bprc;
3337         adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3338         adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3339         adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3340         adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3341         adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3342         adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3343         adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
3344         adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
3345         adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
3346         adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
3347         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3348         adapter->stats.lxontxc += lxon;
3349         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3350         adapter->stats.lxofftxc += lxoff;
3351         adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3352         adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
3353         adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3354         /*
3355          * 82598 errata - tx of flow control packets is included in tx counters
3356          */
3357         xon_off_tot = lxon + lxoff;
3358         adapter->stats.gptc -= xon_off_tot;
3359         adapter->stats.mptc -= xon_off_tot;
3360         adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
3361         adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3362         adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3363         adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3364         adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
3365         adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3366         adapter->stats.ptc64 -= xon_off_tot;
3367         adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3368         adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3369         adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3370         adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3371         adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3372         adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3373
3374         /* Fill out the OS statistics structure */
3375         adapter->net_stats.multicast = adapter->stats.mprc;
3376
3377         /* Rx Errors */
3378         adapter->net_stats.rx_errors = adapter->stats.crcerrs +
3379                                        adapter->stats.rlec;
3380         adapter->net_stats.rx_dropped = 0;
3381         adapter->net_stats.rx_length_errors = adapter->stats.rlec;
3382         adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
3383         adapter->net_stats.rx_missed_errors = total_mpc;
3384 }
3385
3386 /**
3387  * ixgbe_watchdog - Timer Call-back
3388  * @data: pointer to adapter cast into an unsigned long
3389  **/
3390 static void ixgbe_watchdog(unsigned long data)
3391 {
3392         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
3393         struct ixgbe_hw *hw = &adapter->hw;
3394
3395         /* Do the watchdog outside of interrupt context due to the lovely
3396          * delays that some of the newer hardware requires */
3397         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
3398                 /* Cause software interrupt to ensure rx rings are cleaned */
3399                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3400                         u32 eics =
3401                          (1 << (adapter->num_msix_vectors - NON_Q_VECTORS)) - 1;
3402                         IXGBE_WRITE_REG(hw, IXGBE_EICS, eics);
3403                 } else {
3404                         /* For legacy and MSI interrupts don't set any bits that
3405                          * are enabled for EIAM, because this operation would
3406                          * set *both* EIMS and EICS for any bit in EIAM */
3407                         IXGBE_WRITE_REG(hw, IXGBE_EICS,
3408                                     (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
3409                 }
3410                 /* Reset the timer */
3411                 mod_timer(&adapter->watchdog_timer,
3412                           round_jiffies(jiffies + 2 * HZ));
3413         }
3414
3415         schedule_work(&adapter->watchdog_task);
3416 }
3417
3418 /**
3419  * ixgbe_watchdog_task - worker thread to bring link up
3420  * @work: pointer to work_struct containing our data
3421  **/
3422 static void ixgbe_watchdog_task(struct work_struct *work)
3423 {
3424         struct ixgbe_adapter *adapter = container_of(work,
3425                                                      struct ixgbe_adapter,
3426                                                      watchdog_task);
3427         struct net_device *netdev = adapter->netdev;
3428         struct ixgbe_hw *hw = &adapter->hw;
3429         u32 link_speed = adapter->link_speed;
3430         bool link_up = adapter->link_up;
3431
3432         adapter->flags |= IXGBE_FLAG_IN_WATCHDOG_TASK;
3433
3434         if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3435                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
3436                 if (link_up ||
3437                     time_after(jiffies, (adapter->link_check_timeout +
3438                                          IXGBE_TRY_LINK_TIMEOUT))) {
3439                         IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
3440                         adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3441                 }
3442                 adapter->link_up = link_up;
3443                 adapter->link_speed = link_speed;
3444         }
3445
3446         if (link_up) {
3447                 if (!netif_carrier_ok(netdev)) {
3448                         u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3449                         u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
3450 #define FLOW_RX (frctl & IXGBE_FCTRL_RFCE)
3451 #define FLOW_TX (rmcs & IXGBE_RMCS_TFCE_802_3X)
3452                         printk(KERN_INFO "ixgbe: %s NIC Link is Up %s, "
3453                                "Flow Control: %s\n",
3454                                netdev->name,
3455                                (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
3456                                 "10 Gbps" :
3457                                 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
3458                                  "1 Gbps" : "unknown speed")),
3459                                ((FLOW_RX && FLOW_TX) ? "RX/TX" :
3460                                 (FLOW_RX ? "RX" :
3461                                 (FLOW_TX ? "TX" : "None"))));
3462
3463                         netif_carrier_on(netdev);
3464                 } else {
3465                         /* Force detection of hung controller */
3466                         adapter->detect_tx_hung = true;
3467                 }
3468         } else {
3469                 adapter->link_up = false;
3470                 adapter->link_speed = 0;
3471                 if (netif_carrier_ok(netdev)) {
3472                         printk(KERN_INFO "ixgbe: %s NIC Link is Down\n",
3473                                netdev->name);
3474                         netif_carrier_off(netdev);
3475                 }
3476         }
3477
3478         ixgbe_update_stats(adapter);
3479         adapter->flags &= ~IXGBE_FLAG_IN_WATCHDOG_TASK;
3480 }
3481
3482 static int ixgbe_tso(struct ixgbe_adapter *adapter,
3483                      struct ixgbe_ring *tx_ring, struct sk_buff *skb,
3484                      u32 tx_flags, u8 *hdr_len)
3485 {
3486         struct ixgbe_adv_tx_context_desc *context_desc;
3487         unsigned int i;
3488         int err;
3489         struct ixgbe_tx_buffer *tx_buffer_info;
3490         u32 vlan_macip_lens = 0, type_tucmd_mlhl;
3491         u32 mss_l4len_idx, l4len;
3492
3493         if (skb_is_gso(skb)) {
3494                 if (skb_header_cloned(skb)) {
3495                         err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
3496                         if (err)
3497                                 return err;
3498                 }
3499                 l4len = tcp_hdrlen(skb);
3500                 *hdr_len += l4len;
3501
3502                 if (skb->protocol == htons(ETH_P_IP)) {
3503                         struct iphdr *iph = ip_hdr(skb);
3504                         iph->tot_len = 0;
3505                         iph->check = 0;
3506                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
3507                                                                  iph->daddr, 0,
3508                                                                  IPPROTO_TCP,
3509                                                                  0);
3510                         adapter->hw_tso_ctxt++;
3511                 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
3512                         ipv6_hdr(skb)->payload_len = 0;
3513                         tcp_hdr(skb)->check =
3514                             ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
3515                                              &ipv6_hdr(skb)->daddr,
3516                                              0, IPPROTO_TCP, 0);
3517                         adapter->hw_tso6_ctxt++;
3518                 }
3519
3520                 i = tx_ring->next_to_use;
3521
3522                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3523                 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
3524
3525                 /* VLAN MACLEN IPLEN */
3526                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
3527                         vlan_macip_lens |=
3528                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
3529                 vlan_macip_lens |= ((skb_network_offset(skb)) <<
3530                                     IXGBE_ADVTXD_MACLEN_SHIFT);
3531                 *hdr_len += skb_network_offset(skb);
3532                 vlan_macip_lens |=
3533                     (skb_transport_header(skb) - skb_network_header(skb));
3534                 *hdr_len +=
3535                     (skb_transport_header(skb) - skb_network_header(skb));
3536                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
3537                 context_desc->seqnum_seed = 0;
3538
3539                 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
3540                 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
3541                                    IXGBE_ADVTXD_DTYP_CTXT);
3542
3543                 if (skb->protocol == htons(ETH_P_IP))
3544                         type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
3545                 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
3546                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
3547
3548                 /* MSS L4LEN IDX */
3549                 mss_l4len_idx =
3550                     (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
3551                 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
3552                 /* use index 1 for TSO */
3553                 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
3554                 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
3555
3556                 tx_buffer_info->time_stamp = jiffies;
3557                 tx_buffer_info->next_to_watch = i;
3558
3559                 i++;
3560                 if (i == tx_ring->count)
3561                         i = 0;
3562                 tx_ring->next_to_use = i;
3563
3564                 return true;
3565         }
3566         return false;
3567 }
3568
3569 static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
3570                           struct ixgbe_ring *tx_ring,
3571                           struct sk_buff *skb, u32 tx_flags)
3572 {
3573         struct ixgbe_adv_tx_context_desc *context_desc;
3574         unsigned int i;
3575         struct ixgbe_tx_buffer *tx_buffer_info;
3576         u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
3577
3578         if (skb->ip_summed == CHECKSUM_PARTIAL ||
3579             (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
3580                 i = tx_ring->next_to_use;
3581                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3582                 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
3583
3584                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
3585                         vlan_macip_lens |=
3586                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
3587                 vlan_macip_lens |= (skb_network_offset(skb) <<
3588                                     IXGBE_ADVTXD_MACLEN_SHIFT);
3589                 if (skb->ip_summed == CHECKSUM_PARTIAL)
3590                         vlan_macip_lens |= (skb_transport_header(skb) -
3591                                             skb_network_header(skb));
3592
3593                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
3594                 context_desc->seqnum_seed = 0;
3595
3596                 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
3597                                     IXGBE_ADVTXD_DTYP_CTXT);
3598
3599                 if (skb->ip_summed == CHECKSUM_PARTIAL) {
3600                         switch (skb->protocol) {
3601                         case cpu_to_be16(ETH_P_IP):
3602                                 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
3603                                 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
3604                                         type_tucmd_mlhl |=
3605                                                 IXGBE_ADVTXD_TUCMD_L4T_TCP;
3606                                 break;
3607                         case cpu_to_be16(ETH_P_IPV6):
3608                                 /* XXX what about other V6 headers?? */
3609                                 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
3610                                         type_tucmd_mlhl |=
3611                                                 IXGBE_ADVTXD_TUCMD_L4T_TCP;
3612                                 break;
3613                         default:
3614                                 if (unlikely(net_ratelimit())) {
3615                                         DPRINTK(PROBE, WARNING,
3616                                          "partial checksum but proto=%x!\n",
3617                                          skb->protocol);
3618                                 }
3619                                 break;
3620                         }
3621                 }
3622
3623                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
3624                 /* use index zero for tx checksum offload */
3625                 context_desc->mss_l4len_idx = 0;
3626
3627                 tx_buffer_info->time_stamp = jiffies;
3628                 tx_buffer_info->next_to_watch = i;
3629
3630                 adapter->hw_csum_tx_good++;
3631                 i++;
3632                 if (i == tx_ring->count)
3633                         i = 0;
3634                 tx_ring->next_to_use = i;
3635
3636                 return true;
3637         }
3638
3639         return false;
3640 }
3641
3642 static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
3643                         struct ixgbe_ring *tx_ring,
3644                         struct sk_buff *skb, unsigned int first)
3645 {
3646         struct ixgbe_tx_buffer *tx_buffer_info;
3647         unsigned int len = skb->len;
3648         unsigned int offset = 0, size, count = 0, i;
3649         unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
3650         unsigned int f;
3651
3652         len -= skb->data_len;
3653
3654         i = tx_ring->next_to_use;
3655
3656         while (len) {
3657                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3658                 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
3659
3660                 tx_buffer_info->length = size;
3661                 tx_buffer_info->dma = pci_map_single(adapter->pdev,
3662                                                      skb->data + offset,
3663                                                      size, PCI_DMA_TODEVICE);
3664                 tx_buffer_info->time_stamp = jiffies;
3665                 tx_buffer_info->next_to_watch = i;
3666
3667                 len -= size;
3668                 offset += size;
3669                 count++;
3670                 i++;
3671                 if (i == tx_ring->count)
3672                         i = 0;
3673         }
3674
3675         for (f = 0; f < nr_frags; f++) {
3676                 struct skb_frag_struct *frag;
3677
3678                 frag = &skb_shinfo(skb)->frags[f];
3679                 len = frag->size;
3680                 offset = frag->page_offset;
3681
3682                 while (len) {
3683                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
3684                         size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
3685
3686                         tx_buffer_info->length = size;
3687                         tx_buffer_info->dma = pci_map_page(adapter->pdev,
3688                                                            frag->page,
3689                                                            offset,
3690                                                            size,
3691                                                            PCI_DMA_TODEVICE);
3692                         tx_buffer_info->time_stamp = jiffies;
3693                         tx_buffer_info->next_to_watch = i;
3694
3695                         len -= size;
3696                         offset += size;
3697                         count++;
3698                         i++;
3699                         if (i == tx_ring->count)
3700                                 i = 0;
3701                 }
3702         }
3703         if (i == 0)
3704                 i = tx_ring->count - 1;
3705         else
3706                 i = i - 1;
3707         tx_ring->tx_buffer_info[i].skb = skb;
3708         tx_ring->tx_buffer_info[first].next_to_watch = i;
3709
3710         return count;
3711 }
3712
3713 static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
3714                            struct ixgbe_ring *tx_ring,
3715                            int tx_flags, int count, u32 paylen, u8 hdr_len)
3716 {
3717         union ixgbe_adv_tx_desc *tx_desc = NULL;
3718         struct ixgbe_tx_buffer *tx_buffer_info;
3719         u32 olinfo_status = 0, cmd_type_len = 0;
3720         unsigned int i;
3721         u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
3722
3723         cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
3724
3725         cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
3726
3727         if (tx_flags & IXGBE_TX_FLAGS_VLAN)
3728                 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
3729
3730         if (tx_flags & IXGBE_TX_FLAGS_TSO) {
3731                 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
3732
3733                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
3734                                  IXGBE_ADVTXD_POPTS_SHIFT;
3735
3736                 /* use index 1 context for tso */
3737                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
3738                 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
3739                         olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
3740                                          IXGBE_ADVTXD_POPTS_SHIFT;
3741
3742         } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
3743                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
3744                                  IXGBE_ADVTXD_POPTS_SHIFT;
3745
3746         olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
3747
3748         i = tx_ring->next_to_use;
3749         while (count--) {
3750                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3751                 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
3752                 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
3753                 tx_desc->read.cmd_type_len =
3754                         cpu_to_le32(cmd_type_len | tx_buffer_info->length);
3755                 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
3756                 i++;
3757                 if (i == tx_ring->count)
3758                         i = 0;
3759         }
3760
3761         tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
3762
3763         /*
3764          * Force memory writes to complete before letting h/w
3765          * know there are new descriptors to fetch.  (Only
3766          * applicable for weak-ordered memory model archs,
3767          * such as IA-64).
3768          */
3769         wmb();
3770
3771         tx_ring->next_to_use = i;
3772         writel(i, adapter->hw.hw_addr + tx_ring->tail);
3773 }
3774
3775 static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
3776                                  struct ixgbe_ring *tx_ring, int size)
3777 {
3778         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3779
3780         netif_stop_subqueue(netdev, tx_ring->queue_index);
3781         /* Herbert's original patch had:
3782          *  smp_mb__after_netif_stop_queue();
3783          * but since that doesn't exist yet, just open code it. */
3784         smp_mb();
3785
3786         /* We need to check again in a case another CPU has just
3787          * made room available. */
3788         if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
3789                 return -EBUSY;
3790
3791         /* A reprieve! - use start_queue because it doesn't call schedule */
3792         netif_start_subqueue(netdev, tx_ring->queue_index);
3793         ++adapter->restart_queue;
3794         return 0;
3795 }
3796
3797 static int ixgbe_maybe_stop_tx(struct net_device *netdev,
3798                               struct ixgbe_ring *tx_ring, int size)
3799 {
3800         if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
3801                 return 0;
3802         return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
3803 }
3804
3805 static int ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
3806 {
3807         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3808         struct ixgbe_ring *tx_ring;
3809         unsigned int first;
3810         unsigned int tx_flags = 0;
3811         u8 hdr_len = 0;
3812         int r_idx = 0, tso;
3813         int count = 0;
3814         unsigned int f;
3815
3816         r_idx = (adapter->num_tx_queues - 1) & skb->queue_mapping;
3817         tx_ring = &adapter->tx_ring[r_idx];
3818
3819         if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
3820                 tx_flags |= vlan_tx_tag_get(skb);
3821                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3822                         tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
3823                         tx_flags |= (skb->queue_mapping << 13);
3824                 }
3825                 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
3826                 tx_flags |= IXGBE_TX_FLAGS_VLAN;
3827         } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3828                 tx_flags |= (skb->queue_mapping << 13);
3829                 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
3830                 tx_flags |= IXGBE_TX_FLAGS_VLAN;
3831         }
3832         /* three things can cause us to need a context descriptor */
3833         if (skb_is_gso(skb) ||
3834             (skb->ip_summed == CHECKSUM_PARTIAL) ||
3835             (tx_flags & IXGBE_TX_FLAGS_VLAN))
3836                 count++;
3837
3838         count += TXD_USE_COUNT(skb_headlen(skb));
3839         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
3840                 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
3841
3842         if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
3843                 adapter->tx_busy++;
3844                 return NETDEV_TX_BUSY;
3845         }
3846
3847         if (skb->protocol == htons(ETH_P_IP))
3848                 tx_flags |= IXGBE_TX_FLAGS_IPV4;
3849         first = tx_ring->next_to_use;
3850         tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
3851         if (tso < 0) {
3852                 dev_kfree_skb_any(skb);
3853                 return NETDEV_TX_OK;
3854         }
3855
3856         if (tso)
3857                 tx_flags |= IXGBE_TX_FLAGS_TSO;
3858         else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
3859                  (skb->ip_summed == CHECKSUM_PARTIAL))
3860                 tx_flags |= IXGBE_TX_FLAGS_CSUM;
3861
3862         ixgbe_tx_queue(adapter, tx_ring, tx_flags,
3863                        ixgbe_tx_map(adapter, tx_ring, skb, first),
3864                        skb->len, hdr_len);
3865
3866         netdev->trans_start = jiffies;
3867
3868         ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
3869
3870         return NETDEV_TX_OK;
3871 }
3872
3873 /**
3874  * ixgbe_get_stats - Get System Network Statistics
3875  * @netdev: network interface device structure
3876  *
3877  * Returns the address of the device statistics structure.
3878  * The statistics are actually updated from the timer callback.
3879  **/
3880 static struct net_device_stats *ixgbe_get_stats(struct net_device *netdev)
3881 {
3882         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3883
3884         /* only return the current stats */
3885         return &adapter->net_stats;
3886 }
3887
3888 /**
3889  * ixgbe_set_mac - Change the Ethernet Address of the NIC
3890  * @netdev: network interface device structure
3891  * @p: pointer to an address structure
3892  *
3893  * Returns 0 on success, negative on failure
3894  **/
3895 static int ixgbe_set_mac(struct net_device *netdev, void *p)
3896 {
3897         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3898         struct ixgbe_hw *hw = &adapter->hw;
3899         struct sockaddr *addr = p;
3900
3901         if (!is_valid_ether_addr(addr->sa_data))
3902                 return -EADDRNOTAVAIL;
3903
3904         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
3905         memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
3906
3907         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
3908
3909         return 0;
3910 }
3911
3912 #ifdef CONFIG_NET_POLL_CONTROLLER
3913 /*
3914  * Polling 'interrupt' - used by things like netconsole to send skbs
3915  * without having to re-enable interrupts. It's not called while
3916  * the interrupt routine is executing.
3917  */
3918 static void ixgbe_netpoll(struct net_device *netdev)
3919 {
3920         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3921
3922         disable_irq(adapter->pdev->irq);
3923         adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
3924         ixgbe_intr(adapter->pdev->irq, netdev);
3925         adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
3926         enable_irq(adapter->pdev->irq);
3927 }
3928 #endif
3929
3930 static const struct net_device_ops ixgbe_netdev_ops = {
3931         .ndo_open               = ixgbe_open,
3932         .ndo_stop               = ixgbe_close,
3933         .ndo_start_xmit         = ixgbe_xmit_frame,
3934         .ndo_get_stats          = ixgbe_get_stats,
3935         .ndo_set_multicast_list = ixgbe_set_rx_mode,
3936         .ndo_validate_addr      = eth_validate_addr,
3937         .ndo_set_mac_address    = ixgbe_set_mac,
3938         .ndo_change_mtu         = ixgbe_change_mtu,
3939         .ndo_tx_timeout         = ixgbe_tx_timeout,
3940         .ndo_vlan_rx_register   = ixgbe_vlan_rx_register,
3941         .ndo_vlan_rx_add_vid    = ixgbe_vlan_rx_add_vid,
3942         .ndo_vlan_rx_kill_vid   = ixgbe_vlan_rx_kill_vid,
3943 #ifdef CONFIG_NET_POLL_CONTROLLER
3944         .ndo_poll_controller    = ixgbe_netpoll,
3945 #endif
3946 };
3947
3948 /**
3949  * ixgbe_probe - Device Initialization Routine
3950  * @pdev: PCI device information struct
3951  * @ent: entry in ixgbe_pci_tbl
3952  *
3953  * Returns 0 on success, negative on failure
3954  *
3955  * ixgbe_probe initializes an adapter identified by a pci_dev structure.
3956  * The OS initialization, configuring of the adapter private structure,
3957  * and a hardware reset occur.
3958  **/
3959 static int __devinit ixgbe_probe(struct pci_dev *pdev,
3960                                  const struct pci_device_id *ent)
3961 {
3962         struct net_device *netdev;
3963         struct ixgbe_adapter *adapter = NULL;
3964         struct ixgbe_hw *hw;
3965         const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
3966         static int cards_found;
3967         int i, err, pci_using_dac;
3968         u16 link_status, link_speed, link_width;
3969         u32 part_num, eec;
3970
3971         err = pci_enable_device(pdev);
3972         if (err)
3973                 return err;
3974
3975         if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK) &&
3976             !pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK)) {
3977                 pci_using_dac = 1;
3978         } else {
3979                 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3980                 if (err) {
3981                         err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3982                         if (err) {
3983                                 dev_err(&pdev->dev, "No usable DMA "
3984                                         "configuration, aborting\n");
3985                                 goto err_dma;
3986                         }
3987                 }
3988                 pci_using_dac = 0;
3989         }
3990
3991         err = pci_request_regions(pdev, ixgbe_driver_name);
3992         if (err) {
3993                 dev_err(&pdev->dev, "pci_request_regions failed 0x%x\n", err);
3994                 goto err_pci_reg;
3995         }
3996
3997         err = pci_enable_pcie_error_reporting(pdev);
3998         if (err) {
3999                 dev_err(&pdev->dev, "pci_enable_pcie_error_reporting failed "
4000                                     "0x%x\n", err);
4001                 /* non-fatal, continue */
4002         }
4003
4004         pci_set_master(pdev);
4005         pci_save_state(pdev);
4006
4007         netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), MAX_TX_QUEUES);
4008         if (!netdev) {
4009                 err = -ENOMEM;
4010                 goto err_alloc_etherdev;
4011         }
4012
4013         SET_NETDEV_DEV(netdev, &pdev->dev);
4014
4015         pci_set_drvdata(pdev, netdev);
4016         adapter = netdev_priv(netdev);
4017
4018         adapter->netdev = netdev;
4019         adapter->pdev = pdev;
4020         hw = &adapter->hw;
4021         hw->back = adapter;
4022         adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
4023
4024         hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
4025                               pci_resource_len(pdev, 0));
4026         if (!hw->hw_addr) {
4027                 err = -EIO;
4028                 goto err_ioremap;
4029         }
4030
4031         for (i = 1; i <= 5; i++) {
4032                 if (pci_resource_len(pdev, i) == 0)
4033                         continue;
4034         }
4035
4036         netdev->netdev_ops = &ixgbe_netdev_ops;
4037         ixgbe_set_ethtool_ops(netdev);
4038         netdev->watchdog_timeo = 5 * HZ;
4039         strcpy(netdev->name, pci_name(pdev));
4040
4041         adapter->bd_number = cards_found;
4042
4043         /* Setup hw api */
4044         memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
4045         hw->mac.type  = ii->mac;
4046
4047         /* EEPROM */
4048         memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
4049         eec = IXGBE_READ_REG(hw, IXGBE_EEC);
4050         /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
4051         if (!(eec & (1 << 8)))
4052                 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
4053
4054         /* PHY */
4055         memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
4056         hw->phy.sfp_type = ixgbe_sfp_type_unknown;
4057
4058         /* set up this timer and work struct before calling get_invariants
4059          * which might start the timer
4060          */
4061         init_timer(&adapter->sfp_timer);
4062         adapter->sfp_timer.function = &ixgbe_sfp_timer;
4063         adapter->sfp_timer.data = (unsigned long) adapter;
4064
4065         INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
4066
4067         err = ii->get_invariants(hw);
4068         if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
4069                 /* start a kernel thread to watch for a module to arrive */
4070                 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4071                 mod_timer(&adapter->sfp_timer,
4072                           round_jiffies(jiffies + (2 * HZ)));
4073                 err = 0;
4074         } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4075                 DPRINTK(PROBE, ERR, "failed to load because an "
4076                         "unsupported SFP+ module type was detected.\n");
4077                 goto err_hw_init;
4078         } else if (err) {
4079                 goto err_hw_init;
4080         }
4081
4082         /* setup the private structure */
4083         err = ixgbe_sw_init(adapter);
4084         if (err)
4085                 goto err_sw_init;
4086
4087         /* reset_hw fills in the perm_addr as well */
4088         err = hw->mac.ops.reset_hw(hw);
4089         if (err) {
4090                 dev_err(&adapter->pdev->dev, "HW Init failed: %d\n", err);
4091                 goto err_sw_init;
4092         }
4093
4094         netdev->features = NETIF_F_SG |
4095                            NETIF_F_IP_CSUM |
4096                            NETIF_F_HW_VLAN_TX |
4097                            NETIF_F_HW_VLAN_RX |
4098                            NETIF_F_HW_VLAN_FILTER;
4099
4100         netdev->features |= NETIF_F_IPV6_CSUM;
4101         netdev->features |= NETIF_F_TSO;
4102         netdev->features |= NETIF_F_TSO6;
4103         netdev->features |= NETIF_F_GRO;
4104
4105         netdev->vlan_features |= NETIF_F_TSO;
4106         netdev->vlan_features |= NETIF_F_TSO6;
4107         netdev->vlan_features |= NETIF_F_IP_CSUM;
4108         netdev->vlan_features |= NETIF_F_SG;
4109
4110         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
4111                 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
4112
4113 #ifdef CONFIG_IXGBE_DCB
4114         netdev->dcbnl_ops = &dcbnl_ops;
4115 #endif
4116
4117         if (pci_using_dac)
4118                 netdev->features |= NETIF_F_HIGHDMA;
4119
4120         /* make sure the EEPROM is good */
4121         if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
4122                 dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n");
4123                 err = -EIO;
4124                 goto err_eeprom;
4125         }
4126
4127         memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
4128         memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
4129
4130         if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
4131                 dev_err(&pdev->dev, "invalid MAC address\n");
4132                 err = -EIO;
4133                 goto err_eeprom;
4134         }
4135
4136         init_timer(&adapter->watchdog_timer);
4137         adapter->watchdog_timer.function = &ixgbe_watchdog;
4138         adapter->watchdog_timer.data = (unsigned long)adapter;
4139
4140         INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
4141         INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
4142
4143         err = ixgbe_init_interrupt_scheme(adapter);
4144         if (err)
4145                 goto err_sw_init;
4146
4147         /* print bus type/speed/width info */
4148         pci_read_config_word(pdev, IXGBE_PCI_LINK_STATUS, &link_status);
4149         link_speed = link_status & IXGBE_PCI_LINK_SPEED;
4150         link_width = link_status & IXGBE_PCI_LINK_WIDTH;
4151         dev_info(&pdev->dev, "(PCI Express:%s:%s) %pM\n",
4152                 ((link_speed == IXGBE_PCI_LINK_SPEED_5000) ? "5.0Gb/s" :
4153                  (link_speed == IXGBE_PCI_LINK_SPEED_2500) ? "2.5Gb/s" :
4154                  "Unknown"),
4155                 ((link_width == IXGBE_PCI_LINK_WIDTH_8) ? "Width x8" :
4156                  (link_width == IXGBE_PCI_LINK_WIDTH_4) ? "Width x4" :
4157                  (link_width == IXGBE_PCI_LINK_WIDTH_2) ? "Width x2" :
4158                  (link_width == IXGBE_PCI_LINK_WIDTH_1) ? "Width x1" :
4159                  "Unknown"),
4160                 netdev->dev_addr);
4161         ixgbe_read_pba_num_generic(hw, &part_num);
4162         dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
4163                  hw->mac.type, hw->phy.type,
4164                  (part_num >> 8), (part_num & 0xff));
4165
4166         if (link_width <= IXGBE_PCI_LINK_WIDTH_4) {
4167                 dev_warn(&pdev->dev, "PCI-Express bandwidth available for "
4168                          "this card is not sufficient for optimal "
4169                          "performance.\n");
4170                 dev_warn(&pdev->dev, "For optimal performance a x8 "
4171                          "PCI-Express slot is required.\n");
4172         }
4173
4174         /* save off EEPROM version number */
4175         hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
4176
4177         /* reset the hardware with the new settings */
4178         hw->mac.ops.start_hw(hw);
4179
4180         netif_carrier_off(netdev);
4181
4182         strcpy(netdev->name, "eth%d");
4183         err = register_netdev(netdev);
4184         if (err)
4185                 goto err_register;
4186
4187 #ifdef CONFIG_IXGBE_DCA
4188         if (dca_add_requester(&pdev->dev) == 0) {
4189                 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
4190                 /* always use CB2 mode, difference is masked
4191                  * in the CB driver */
4192                 IXGBE_WRITE_REG(hw, IXGBE_DCA_CTRL, 2);
4193                 ixgbe_setup_dca(adapter);
4194         }
4195 #endif
4196
4197         dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n");
4198         cards_found++;
4199         return 0;
4200
4201 err_register:
4202         ixgbe_release_hw_control(adapter);
4203 err_hw_init:
4204 err_sw_init:
4205         ixgbe_reset_interrupt_capability(adapter);
4206 err_eeprom:
4207         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4208         del_timer_sync(&adapter->sfp_timer);
4209         cancel_work_sync(&adapter->sfp_task);
4210         iounmap(hw->hw_addr);
4211 err_ioremap:
4212         free_netdev(netdev);
4213 err_alloc_etherdev:
4214         pci_release_regions(pdev);
4215 err_pci_reg:
4216 err_dma:
4217         pci_disable_device(pdev);
4218         return err;
4219 }
4220
4221 /**
4222  * ixgbe_remove - Device Removal Routine
4223  * @pdev: PCI device information struct
4224  *
4225  * ixgbe_remove is called by the PCI subsystem to alert the driver
4226  * that it should release a PCI device.  The could be caused by a
4227  * Hot-Plug event, or because the driver is going to be removed from
4228  * memory.
4229  **/
4230 static void __devexit ixgbe_remove(struct pci_dev *pdev)
4231 {
4232         struct net_device *netdev = pci_get_drvdata(pdev);
4233         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4234         int err;
4235
4236         set_bit(__IXGBE_DOWN, &adapter->state);
4237         /* clear the module not found bit to make sure the worker won't
4238          * reschedule
4239          */
4240         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4241         del_timer_sync(&adapter->watchdog_timer);
4242
4243         del_timer_sync(&adapter->sfp_timer);
4244         cancel_work_sync(&adapter->watchdog_task);
4245         cancel_work_sync(&adapter->sfp_task);
4246         flush_scheduled_work();
4247
4248 #ifdef CONFIG_IXGBE_DCA
4249         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
4250                 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
4251                 dca_remove_requester(&pdev->dev);
4252                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
4253         }
4254
4255 #endif
4256         if (netdev->reg_state == NETREG_REGISTERED)
4257                 unregister_netdev(netdev);
4258
4259         ixgbe_reset_interrupt_capability(adapter);
4260
4261         ixgbe_release_hw_control(adapter);
4262
4263         iounmap(adapter->hw.hw_addr);
4264         pci_release_regions(pdev);
4265
4266         DPRINTK(PROBE, INFO, "complete\n");
4267         kfree(adapter->tx_ring);
4268         kfree(adapter->rx_ring);
4269
4270         free_netdev(netdev);
4271
4272         err = pci_disable_pcie_error_reporting(pdev);
4273         if (err)
4274                 dev_err(&pdev->dev,
4275                         "pci_disable_pcie_error_reporting failed 0x%x\n", err);
4276
4277         pci_disable_device(pdev);
4278 }
4279
4280 /**
4281  * ixgbe_io_error_detected - called when PCI error is detected
4282  * @pdev: Pointer to PCI device
4283  * @state: The current pci connection state
4284  *
4285  * This function is called after a PCI bus error affecting
4286  * this device has been detected.
4287  */
4288 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
4289                                                 pci_channel_state_t state)
4290 {
4291         struct net_device *netdev = pci_get_drvdata(pdev);
4292         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4293
4294         netif_device_detach(netdev);
4295
4296         if (netif_running(netdev))
4297                 ixgbe_down(adapter);
4298         pci_disable_device(pdev);
4299
4300         /* Request a slot reset. */
4301         return PCI_ERS_RESULT_NEED_RESET;
4302 }
4303
4304 /**
4305  * ixgbe_io_slot_reset - called after the pci bus has been reset.
4306  * @pdev: Pointer to PCI device
4307  *
4308  * Restart the card from scratch, as if from a cold-boot.
4309  */
4310 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
4311 {
4312         struct net_device *netdev = pci_get_drvdata(pdev);
4313         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4314         pci_ers_result_t result;
4315         int err;
4316
4317         if (pci_enable_device(pdev)) {
4318                 DPRINTK(PROBE, ERR,
4319                         "Cannot re-enable PCI device after reset.\n");
4320                 result = PCI_ERS_RESULT_DISCONNECT;
4321         } else {
4322                 pci_set_master(pdev);
4323                 pci_restore_state(pdev);
4324
4325                 pci_enable_wake(pdev, PCI_D3hot, 0);
4326                 pci_enable_wake(pdev, PCI_D3cold, 0);
4327
4328                 ixgbe_reset(adapter);
4329
4330                 result = PCI_ERS_RESULT_RECOVERED;
4331         }
4332
4333         err = pci_cleanup_aer_uncorrect_error_status(pdev);
4334         if (err) {
4335                 dev_err(&pdev->dev,
4336                   "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", err);
4337                 /* non-fatal, continue */
4338         }
4339
4340         return result;
4341 }
4342
4343 /**
4344  * ixgbe_io_resume - called when traffic can start flowing again.
4345  * @pdev: Pointer to PCI device
4346  *
4347  * This callback is called when the error recovery driver tells us that
4348  * its OK to resume normal operation.
4349  */
4350 static void ixgbe_io_resume(struct pci_dev *pdev)
4351 {
4352         struct net_device *netdev = pci_get_drvdata(pdev);
4353         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4354
4355         if (netif_running(netdev)) {
4356                 if (ixgbe_up(adapter)) {
4357                         DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n");
4358                         return;
4359                 }
4360         }
4361
4362         netif_device_attach(netdev);
4363 }
4364
4365 static struct pci_error_handlers ixgbe_err_handler = {
4366         .error_detected = ixgbe_io_error_detected,
4367         .slot_reset = ixgbe_io_slot_reset,
4368         .resume = ixgbe_io_resume,
4369 };
4370
4371 static struct pci_driver ixgbe_driver = {
4372         .name     = ixgbe_driver_name,
4373         .id_table = ixgbe_pci_tbl,
4374         .probe    = ixgbe_probe,
4375         .remove   = __devexit_p(ixgbe_remove),
4376 #ifdef CONFIG_PM
4377         .suspend  = ixgbe_suspend,
4378         .resume   = ixgbe_resume,
4379 #endif
4380         .shutdown = ixgbe_shutdown,
4381         .err_handler = &ixgbe_err_handler
4382 };
4383
4384 /**
4385  * ixgbe_init_module - Driver Registration Routine
4386  *
4387  * ixgbe_init_module is the first routine called when the driver is
4388  * loaded. All it does is register with the PCI subsystem.
4389  **/
4390 static int __init ixgbe_init_module(void)
4391 {
4392         int ret;
4393         printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name,
4394                ixgbe_driver_string, ixgbe_driver_version);
4395
4396         printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright);
4397
4398 #ifdef CONFIG_IXGBE_DCA
4399         dca_register_notify(&dca_notifier);
4400 #endif
4401
4402         ret = pci_register_driver(&ixgbe_driver);
4403         return ret;
4404 }
4405
4406 module_init(ixgbe_init_module);
4407
4408 /**
4409  * ixgbe_exit_module - Driver Exit Cleanup Routine
4410  *
4411  * ixgbe_exit_module is called just before the driver is removed
4412  * from memory.
4413  **/
4414 static void __exit ixgbe_exit_module(void)
4415 {
4416 #ifdef CONFIG_IXGBE_DCA
4417         dca_unregister_notify(&dca_notifier);
4418 #endif
4419         pci_unregister_driver(&ixgbe_driver);
4420 }
4421
4422 #ifdef CONFIG_IXGBE_DCA
4423 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
4424                             void *p)
4425 {
4426         int ret_val;
4427
4428         ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
4429                                          __ixgbe_notify_dca);
4430
4431         return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
4432 }
4433 #endif /* CONFIG_IXGBE_DCA */
4434
4435 module_exit(ixgbe_exit_module);
4436
4437 /* ixgbe_main.c */