2 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
3 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 #include <linux/init.h>
35 #include <linux/interrupt.h>
37 #include <linux/dma-mapping.h>
39 #include <linux/mlx4/cmd.h>
45 MLX4_NUM_ASYNC_EQE = 0x100,
46 MLX4_NUM_SPARE_EQE = 0x80,
47 MLX4_EQ_ENTRY_SIZE = 0x20
51 * Must be packed because start is 64 bits but only aligned to 32 bits.
53 struct mlx4_eq_context {
67 __be32 mtt_base_addr_l;
69 __be32 consumer_index;
70 __be32 producer_index;
74 #define MLX4_EQ_STATUS_OK ( 0 << 28)
75 #define MLX4_EQ_STATUS_WRITE_FAIL (10 << 28)
76 #define MLX4_EQ_OWNER_SW ( 0 << 24)
77 #define MLX4_EQ_OWNER_HW ( 1 << 24)
78 #define MLX4_EQ_FLAG_EC ( 1 << 18)
79 #define MLX4_EQ_FLAG_OI ( 1 << 17)
80 #define MLX4_EQ_STATE_ARMED ( 9 << 8)
81 #define MLX4_EQ_STATE_FIRED (10 << 8)
82 #define MLX4_EQ_STATE_ALWAYS_ARMED (11 << 8)
84 #define MLX4_ASYNC_EVENT_MASK ((1ull << MLX4_EVENT_TYPE_PATH_MIG) | \
85 (1ull << MLX4_EVENT_TYPE_COMM_EST) | \
86 (1ull << MLX4_EVENT_TYPE_SQ_DRAINED) | \
87 (1ull << MLX4_EVENT_TYPE_CQ_ERROR) | \
88 (1ull << MLX4_EVENT_TYPE_WQ_CATAS_ERROR) | \
89 (1ull << MLX4_EVENT_TYPE_EEC_CATAS_ERROR) | \
90 (1ull << MLX4_EVENT_TYPE_PATH_MIG_FAILED) | \
91 (1ull << MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR) | \
92 (1ull << MLX4_EVENT_TYPE_WQ_ACCESS_ERROR) | \
93 (1ull << MLX4_EVENT_TYPE_PORT_CHANGE) | \
94 (1ull << MLX4_EVENT_TYPE_ECC_DETECT) | \
95 (1ull << MLX4_EVENT_TYPE_SRQ_CATAS_ERROR) | \
96 (1ull << MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE) | \
97 (1ull << MLX4_EVENT_TYPE_SRQ_LIMIT) | \
98 (1ull << MLX4_EVENT_TYPE_CMD))
109 } __attribute__((packed)) comp;
117 } __attribute__((packed)) cmd;
120 } __attribute__((packed)) qp;
123 } __attribute__((packed)) srq;
129 } __attribute__((packed)) cq_err;
133 } __attribute__((packed)) port_change;
137 } __attribute__((packed));
139 static void eq_set_ci(struct mlx4_eq *eq, int req_not)
141 __raw_writel((__force u32) cpu_to_be32((eq->cons_index & 0xffffff) |
144 /* We still want ordering, just not swabbing, so add a barrier */
148 static struct mlx4_eqe *get_eqe(struct mlx4_eq *eq, u32 entry)
150 unsigned long off = (entry & (eq->nent - 1)) * MLX4_EQ_ENTRY_SIZE;
151 return eq->page_list[off / PAGE_SIZE].buf + off % PAGE_SIZE;
154 static struct mlx4_eqe *next_eqe_sw(struct mlx4_eq *eq)
156 struct mlx4_eqe *eqe = get_eqe(eq, eq->cons_index);
157 return !!(eqe->owner & 0x80) ^ !!(eq->cons_index & eq->nent) ? NULL : eqe;
160 static int mlx4_eq_int(struct mlx4_dev *dev, struct mlx4_eq *eq)
162 struct mlx4_eqe *eqe;
168 while ((eqe = next_eqe_sw(eq))) {
170 * Make sure we read EQ entry contents after we've
171 * checked the ownership bit.
176 case MLX4_EVENT_TYPE_COMP:
177 cqn = be32_to_cpu(eqe->event.comp.cqn) & 0xffffff;
178 mlx4_cq_completion(dev, cqn);
181 case MLX4_EVENT_TYPE_PATH_MIG:
182 case MLX4_EVENT_TYPE_COMM_EST:
183 case MLX4_EVENT_TYPE_SQ_DRAINED:
184 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE:
185 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR:
186 case MLX4_EVENT_TYPE_PATH_MIG_FAILED:
187 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
188 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR:
189 mlx4_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) & 0xffffff,
193 case MLX4_EVENT_TYPE_SRQ_LIMIT:
194 case MLX4_EVENT_TYPE_SRQ_CATAS_ERROR:
195 mlx4_srq_event(dev, be32_to_cpu(eqe->event.srq.srqn) & 0xffffff,
199 case MLX4_EVENT_TYPE_CMD:
201 be16_to_cpu(eqe->event.cmd.token),
202 eqe->event.cmd.status,
203 be64_to_cpu(eqe->event.cmd.out_param));
206 case MLX4_EVENT_TYPE_PORT_CHANGE:
207 port = be32_to_cpu(eqe->event.port_change.port) >> 28;
208 if (eqe->subtype == MLX4_PORT_CHANGE_SUBTYPE_DOWN) {
209 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_PORT_DOWN,
211 mlx4_priv(dev)->sense.do_sense_port[port] = 1;
213 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_PORT_UP,
215 mlx4_priv(dev)->sense.do_sense_port[port] = 0;
219 case MLX4_EVENT_TYPE_CQ_ERROR:
220 mlx4_warn(dev, "CQ %s on CQN %06x\n",
221 eqe->event.cq_err.syndrome == 1 ?
222 "overrun" : "access violation",
223 be32_to_cpu(eqe->event.cq_err.cqn) & 0xffffff);
224 mlx4_cq_event(dev, be32_to_cpu(eqe->event.cq_err.cqn),
228 case MLX4_EVENT_TYPE_EQ_OVERFLOW:
229 mlx4_warn(dev, "EQ overrun on EQN %d\n", eq->eqn);
232 case MLX4_EVENT_TYPE_EEC_CATAS_ERROR:
233 case MLX4_EVENT_TYPE_ECC_DETECT:
235 mlx4_warn(dev, "Unhandled event %02x(%02x) on EQ %d at index %u\n",
236 eqe->type, eqe->subtype, eq->eqn, eq->cons_index);
245 * The HCA will think the queue has overflowed if we
246 * don't tell it we've been processing events. We
247 * create our EQs with MLX4_NUM_SPARE_EQE extra
248 * entries, so we must update our consumer index at
251 if (unlikely(set_ci >= MLX4_NUM_SPARE_EQE)) {
262 static irqreturn_t mlx4_interrupt(int irq, void *dev_ptr)
264 struct mlx4_dev *dev = dev_ptr;
265 struct mlx4_priv *priv = mlx4_priv(dev);
269 writel(priv->eq_table.clr_mask, priv->eq_table.clr_int);
271 for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i)
272 work |= mlx4_eq_int(dev, &priv->eq_table.eq[i]);
274 return IRQ_RETVAL(work);
277 static irqreturn_t mlx4_msi_x_interrupt(int irq, void *eq_ptr)
279 struct mlx4_eq *eq = eq_ptr;
280 struct mlx4_dev *dev = eq->dev;
282 mlx4_eq_int(dev, eq);
284 /* MSI-X vectors always belong to us */
288 static int mlx4_MAP_EQ(struct mlx4_dev *dev, u64 event_mask, int unmap,
291 return mlx4_cmd(dev, event_mask, (unmap << 31) | eq_num,
292 0, MLX4_CMD_MAP_EQ, MLX4_CMD_TIME_CLASS_B);
295 static int mlx4_SW2HW_EQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
298 return mlx4_cmd(dev, mailbox->dma, eq_num, 0, MLX4_CMD_SW2HW_EQ,
299 MLX4_CMD_TIME_CLASS_A);
302 static int mlx4_HW2SW_EQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
305 return mlx4_cmd_box(dev, 0, mailbox->dma, eq_num, 0, MLX4_CMD_HW2SW_EQ,
306 MLX4_CMD_TIME_CLASS_A);
309 static int mlx4_num_eq_uar(struct mlx4_dev *dev)
312 * Each UAR holds 4 EQ doorbells. To figure out how many UARs
313 * we need to map, take the difference of highest index and
314 * the lowest index we'll use and add 1.
316 return (dev->caps.num_comp_vectors + 1 + dev->caps.reserved_eqs) / 4 -
317 dev->caps.reserved_eqs / 4 + 1;
320 static void __iomem *mlx4_get_eq_uar(struct mlx4_dev *dev, struct mlx4_eq *eq)
322 struct mlx4_priv *priv = mlx4_priv(dev);
325 index = eq->eqn / 4 - dev->caps.reserved_eqs / 4;
327 if (!priv->eq_table.uar_map[index]) {
328 priv->eq_table.uar_map[index] =
329 ioremap(pci_resource_start(dev->pdev, 2) +
330 ((eq->eqn / 4) << PAGE_SHIFT),
332 if (!priv->eq_table.uar_map[index]) {
333 mlx4_err(dev, "Couldn't map EQ doorbell for EQN 0x%06x\n",
339 return priv->eq_table.uar_map[index] + 0x800 + 8 * (eq->eqn % 4);
342 static int mlx4_create_eq(struct mlx4_dev *dev, int nent,
343 u8 intr, struct mlx4_eq *eq)
345 struct mlx4_priv *priv = mlx4_priv(dev);
346 struct mlx4_cmd_mailbox *mailbox;
347 struct mlx4_eq_context *eq_context;
349 u64 *dma_list = NULL;
356 eq->nent = roundup_pow_of_two(max(nent, 2));
357 npages = PAGE_ALIGN(eq->nent * MLX4_EQ_ENTRY_SIZE) / PAGE_SIZE;
359 eq->page_list = kmalloc(npages * sizeof *eq->page_list,
364 for (i = 0; i < npages; ++i)
365 eq->page_list[i].buf = NULL;
367 dma_list = kmalloc(npages * sizeof *dma_list, GFP_KERNEL);
371 mailbox = mlx4_alloc_cmd_mailbox(dev);
374 eq_context = mailbox->buf;
376 for (i = 0; i < npages; ++i) {
377 eq->page_list[i].buf = dma_alloc_coherent(&dev->pdev->dev,
378 PAGE_SIZE, &t, GFP_KERNEL);
379 if (!eq->page_list[i].buf)
380 goto err_out_free_pages;
383 eq->page_list[i].map = t;
385 memset(eq->page_list[i].buf, 0, PAGE_SIZE);
388 eq->eqn = mlx4_bitmap_alloc(&priv->eq_table.bitmap);
390 goto err_out_free_pages;
392 eq->doorbell = mlx4_get_eq_uar(dev, eq);
395 goto err_out_free_eq;
398 err = mlx4_mtt_init(dev, npages, PAGE_SHIFT, &eq->mtt);
400 goto err_out_free_eq;
402 err = mlx4_write_mtt(dev, &eq->mtt, 0, npages, dma_list);
404 goto err_out_free_mtt;
406 memset(eq_context, 0, sizeof *eq_context);
407 eq_context->flags = cpu_to_be32(MLX4_EQ_STATUS_OK |
408 MLX4_EQ_STATE_ARMED);
409 eq_context->log_eq_size = ilog2(eq->nent);
410 eq_context->intr = intr;
411 eq_context->log_page_size = PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT;
413 mtt_addr = mlx4_mtt_addr(dev, &eq->mtt);
414 eq_context->mtt_base_addr_h = mtt_addr >> 32;
415 eq_context->mtt_base_addr_l = cpu_to_be32(mtt_addr & 0xffffffff);
417 err = mlx4_SW2HW_EQ(dev, mailbox, eq->eqn);
419 mlx4_warn(dev, "SW2HW_EQ failed (%d)\n", err);
420 goto err_out_free_mtt;
424 mlx4_free_cmd_mailbox(dev, mailbox);
431 mlx4_mtt_cleanup(dev, &eq->mtt);
434 mlx4_bitmap_free(&priv->eq_table.bitmap, eq->eqn);
437 for (i = 0; i < npages; ++i)
438 if (eq->page_list[i].buf)
439 dma_free_coherent(&dev->pdev->dev, PAGE_SIZE,
440 eq->page_list[i].buf,
441 eq->page_list[i].map);
443 mlx4_free_cmd_mailbox(dev, mailbox);
446 kfree(eq->page_list);
453 static void mlx4_free_eq(struct mlx4_dev *dev,
456 struct mlx4_priv *priv = mlx4_priv(dev);
457 struct mlx4_cmd_mailbox *mailbox;
459 int npages = PAGE_ALIGN(MLX4_EQ_ENTRY_SIZE * eq->nent) / PAGE_SIZE;
462 mailbox = mlx4_alloc_cmd_mailbox(dev);
466 err = mlx4_HW2SW_EQ(dev, mailbox, eq->eqn);
468 mlx4_warn(dev, "HW2SW_EQ failed (%d)\n", err);
471 mlx4_dbg(dev, "Dumping EQ context %02x:\n", eq->eqn);
472 for (i = 0; i < sizeof (struct mlx4_eq_context) / 4; ++i) {
474 printk("[%02x] ", i * 4);
475 printk(" %08x", be32_to_cpup(mailbox->buf + i * 4));
476 if ((i + 1) % 4 == 0)
481 mlx4_mtt_cleanup(dev, &eq->mtt);
482 for (i = 0; i < npages; ++i)
483 pci_free_consistent(dev->pdev, PAGE_SIZE,
484 eq->page_list[i].buf,
485 eq->page_list[i].map);
487 kfree(eq->page_list);
488 mlx4_bitmap_free(&priv->eq_table.bitmap, eq->eqn);
489 mlx4_free_cmd_mailbox(dev, mailbox);
492 static void mlx4_free_irqs(struct mlx4_dev *dev)
494 struct mlx4_eq_table *eq_table = &mlx4_priv(dev)->eq_table;
497 if (eq_table->have_irq)
498 free_irq(dev->pdev->irq, dev);
499 for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i)
500 if (eq_table->eq[i].have_irq)
501 free_irq(eq_table->eq[i].irq, eq_table->eq + i);
503 kfree(eq_table->irq_names);
506 static int mlx4_map_clr_int(struct mlx4_dev *dev)
508 struct mlx4_priv *priv = mlx4_priv(dev);
510 priv->clr_base = ioremap(pci_resource_start(dev->pdev, priv->fw.clr_int_bar) +
511 priv->fw.clr_int_base, MLX4_CLR_INT_SIZE);
512 if (!priv->clr_base) {
513 mlx4_err(dev, "Couldn't map interrupt clear register, aborting.\n");
520 static void mlx4_unmap_clr_int(struct mlx4_dev *dev)
522 struct mlx4_priv *priv = mlx4_priv(dev);
524 iounmap(priv->clr_base);
527 int mlx4_map_eq_icm(struct mlx4_dev *dev, u64 icm_virt)
529 struct mlx4_priv *priv = mlx4_priv(dev);
533 * We assume that mapping one page is enough for the whole EQ
534 * context table. This is fine with all current HCAs, because
535 * we only use 32 EQs and each EQ uses 64 bytes of context
536 * memory, or 1 KB total.
538 priv->eq_table.icm_virt = icm_virt;
539 priv->eq_table.icm_page = alloc_page(GFP_HIGHUSER);
540 if (!priv->eq_table.icm_page)
542 priv->eq_table.icm_dma = pci_map_page(dev->pdev, priv->eq_table.icm_page, 0,
543 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
544 if (pci_dma_mapping_error(dev->pdev, priv->eq_table.icm_dma)) {
545 __free_page(priv->eq_table.icm_page);
549 ret = mlx4_MAP_ICM_page(dev, priv->eq_table.icm_dma, icm_virt);
551 pci_unmap_page(dev->pdev, priv->eq_table.icm_dma, PAGE_SIZE,
552 PCI_DMA_BIDIRECTIONAL);
553 __free_page(priv->eq_table.icm_page);
559 void mlx4_unmap_eq_icm(struct mlx4_dev *dev)
561 struct mlx4_priv *priv = mlx4_priv(dev);
563 mlx4_UNMAP_ICM(dev, priv->eq_table.icm_virt, 1);
564 pci_unmap_page(dev->pdev, priv->eq_table.icm_dma, PAGE_SIZE,
565 PCI_DMA_BIDIRECTIONAL);
566 __free_page(priv->eq_table.icm_page);
569 int mlx4_alloc_eq_table(struct mlx4_dev *dev)
571 struct mlx4_priv *priv = mlx4_priv(dev);
573 priv->eq_table.eq = kcalloc(dev->caps.num_eqs - dev->caps.reserved_eqs,
574 sizeof *priv->eq_table.eq, GFP_KERNEL);
575 if (!priv->eq_table.eq)
581 void mlx4_free_eq_table(struct mlx4_dev *dev)
583 kfree(mlx4_priv(dev)->eq_table.eq);
586 int mlx4_init_eq_table(struct mlx4_dev *dev)
588 struct mlx4_priv *priv = mlx4_priv(dev);
592 priv->eq_table.uar_map = kcalloc(sizeof *priv->eq_table.uar_map,
593 mlx4_num_eq_uar(dev), GFP_KERNEL);
594 if (!priv->eq_table.uar_map) {
599 err = mlx4_bitmap_init(&priv->eq_table.bitmap, dev->caps.num_eqs,
600 dev->caps.num_eqs - 1, dev->caps.reserved_eqs, 0);
604 for (i = 0; i < mlx4_num_eq_uar(dev); ++i)
605 priv->eq_table.uar_map[i] = NULL;
607 err = mlx4_map_clr_int(dev);
611 priv->eq_table.clr_mask =
612 swab32(1 << (priv->eq_table.inta_pin & 31));
613 priv->eq_table.clr_int = priv->clr_base +
614 (priv->eq_table.inta_pin < 32 ? 4 : 0);
616 priv->eq_table.irq_names = kmalloc(16 * dev->caps.num_comp_vectors, GFP_KERNEL);
617 if (!priv->eq_table.irq_names) {
622 for (i = 0; i < dev->caps.num_comp_vectors; ++i) {
623 err = mlx4_create_eq(dev, dev->caps.num_cqs + MLX4_NUM_SPARE_EQE,
624 (dev->flags & MLX4_FLAG_MSI_X) ? i : 0,
625 &priv->eq_table.eq[i]);
632 err = mlx4_create_eq(dev, MLX4_NUM_ASYNC_EQE + MLX4_NUM_SPARE_EQE,
633 (dev->flags & MLX4_FLAG_MSI_X) ? dev->caps.num_comp_vectors : 0,
634 &priv->eq_table.eq[dev->caps.num_comp_vectors]);
638 if (dev->flags & MLX4_FLAG_MSI_X) {
639 static const char async_eq_name[] = "mlx4-async";
642 for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i) {
643 if (i < dev->caps.num_comp_vectors) {
644 snprintf(priv->eq_table.irq_names + i * 16, 16,
646 eq_name = priv->eq_table.irq_names + i * 16;
648 eq_name = async_eq_name;
650 err = request_irq(priv->eq_table.eq[i].irq,
651 mlx4_msi_x_interrupt, 0, eq_name,
652 priv->eq_table.eq + i);
656 priv->eq_table.eq[i].have_irq = 1;
659 err = request_irq(dev->pdev->irq, mlx4_interrupt,
660 IRQF_SHARED, DRV_NAME, dev);
664 priv->eq_table.have_irq = 1;
667 err = mlx4_MAP_EQ(dev, MLX4_ASYNC_EVENT_MASK, 0,
668 priv->eq_table.eq[dev->caps.num_comp_vectors].eqn);
670 mlx4_warn(dev, "MAP_EQ for async EQ %d failed (%d)\n",
671 priv->eq_table.eq[dev->caps.num_comp_vectors].eqn, err);
673 for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i)
674 eq_set_ci(&priv->eq_table.eq[i], 1);
679 mlx4_free_eq(dev, &priv->eq_table.eq[dev->caps.num_comp_vectors]);
682 i = dev->caps.num_comp_vectors - 1;
686 mlx4_free_eq(dev, &priv->eq_table.eq[i]);
689 mlx4_unmap_clr_int(dev);
693 mlx4_bitmap_cleanup(&priv->eq_table.bitmap);
696 kfree(priv->eq_table.uar_map);
701 void mlx4_cleanup_eq_table(struct mlx4_dev *dev)
703 struct mlx4_priv *priv = mlx4_priv(dev);
706 mlx4_MAP_EQ(dev, MLX4_ASYNC_EVENT_MASK, 1,
707 priv->eq_table.eq[dev->caps.num_comp_vectors].eqn);
711 for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i)
712 mlx4_free_eq(dev, &priv->eq_table.eq[i]);
714 mlx4_unmap_clr_int(dev);
716 for (i = 0; i < mlx4_num_eq_uar(dev); ++i)
717 if (priv->eq_table.uar_map[i])
718 iounmap(priv->eq_table.uar_map[i]);
720 mlx4_bitmap_cleanup(&priv->eq_table.bitmap);
722 kfree(priv->eq_table.uar_map);