2 * Copyright (c) 2004 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/init.h>
36 #include <linux/errno.h>
38 #include <linux/mlx4/cmd.h>
44 * Must be packed because mtt_seg is 64 bits but only aligned to 32 bits.
46 struct mlx4_mpt_entry {
60 __be32 first_byte_offset;
61 } __attribute__((packed));
63 #define MLX4_MPT_FLAG_SW_OWNS (0xfUL << 28)
64 #define MLX4_MPT_FLAG_MIO (1 << 17)
65 #define MLX4_MPT_FLAG_BIND_ENABLE (1 << 15)
66 #define MLX4_MPT_FLAG_PHYSICAL (1 << 9)
67 #define MLX4_MPT_FLAG_REGION (1 << 8)
69 #define MLX4_MTT_FLAG_PRESENT 1
71 #define MLX4_MPT_STATUS_SW 0xF0
72 #define MLX4_MPT_STATUS_HW 0x00
74 static u32 mlx4_buddy_alloc(struct mlx4_buddy *buddy, int order)
80 spin_lock(&buddy->lock);
82 for (o = order; o <= buddy->max_order; ++o)
83 if (buddy->num_free[o]) {
84 m = 1 << (buddy->max_order - o);
85 seg = find_first_bit(buddy->bits[o], m);
90 spin_unlock(&buddy->lock);
94 clear_bit(seg, buddy->bits[o]);
100 set_bit(seg ^ 1, buddy->bits[o]);
101 ++buddy->num_free[o];
104 spin_unlock(&buddy->lock);
111 static void mlx4_buddy_free(struct mlx4_buddy *buddy, u32 seg, int order)
115 spin_lock(&buddy->lock);
117 while (test_bit(seg ^ 1, buddy->bits[order])) {
118 clear_bit(seg ^ 1, buddy->bits[order]);
119 --buddy->num_free[order];
124 set_bit(seg, buddy->bits[order]);
125 ++buddy->num_free[order];
127 spin_unlock(&buddy->lock);
130 static int mlx4_buddy_init(struct mlx4_buddy *buddy, int max_order)
134 buddy->max_order = max_order;
135 spin_lock_init(&buddy->lock);
137 buddy->bits = kzalloc((buddy->max_order + 1) * sizeof (long *),
139 buddy->num_free = kzalloc((buddy->max_order + 1) * sizeof (int *),
141 if (!buddy->bits || !buddy->num_free)
144 for (i = 0; i <= buddy->max_order; ++i) {
145 s = BITS_TO_LONGS(1 << (buddy->max_order - i));
146 buddy->bits[i] = kmalloc(s * sizeof (long), GFP_KERNEL);
149 bitmap_zero(buddy->bits[i], 1 << (buddy->max_order - i));
152 set_bit(0, buddy->bits[buddy->max_order]);
153 buddy->num_free[buddy->max_order] = 1;
158 for (i = 0; i <= buddy->max_order; ++i)
159 kfree(buddy->bits[i]);
163 kfree(buddy->num_free);
168 static void mlx4_buddy_cleanup(struct mlx4_buddy *buddy)
172 for (i = 0; i <= buddy->max_order; ++i)
173 kfree(buddy->bits[i]);
176 kfree(buddy->num_free);
179 static u32 mlx4_alloc_mtt_range(struct mlx4_dev *dev, int order)
181 struct mlx4_mr_table *mr_table = &mlx4_priv(dev)->mr_table;
184 seg = mlx4_buddy_alloc(&mr_table->mtt_buddy, order);
188 if (mlx4_table_get_range(dev, &mr_table->mtt_table, seg,
189 seg + (1 << order) - 1)) {
190 mlx4_buddy_free(&mr_table->mtt_buddy, seg, order);
197 int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift,
198 struct mlx4_mtt *mtt)
204 mtt->page_shift = MLX4_ICM_PAGE_SHIFT;
207 mtt->page_shift = page_shift;
209 for (mtt->order = 0, i = MLX4_MTT_ENTRY_PER_SEG; i < npages; i <<= 1)
212 mtt->first_seg = mlx4_alloc_mtt_range(dev, mtt->order);
213 if (mtt->first_seg == -1)
218 EXPORT_SYMBOL_GPL(mlx4_mtt_init);
220 void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt)
222 struct mlx4_mr_table *mr_table = &mlx4_priv(dev)->mr_table;
227 mlx4_buddy_free(&mr_table->mtt_buddy, mtt->first_seg, mtt->order);
228 mlx4_table_put_range(dev, &mr_table->mtt_table, mtt->first_seg,
229 mtt->first_seg + (1 << mtt->order) - 1);
231 EXPORT_SYMBOL_GPL(mlx4_mtt_cleanup);
233 u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt)
235 return (u64) mtt->first_seg * dev->caps.mtt_entry_sz;
237 EXPORT_SYMBOL_GPL(mlx4_mtt_addr);
239 static u32 hw_index_to_key(u32 ind)
241 return (ind >> 24) | (ind << 8);
244 static u32 key_to_hw_index(u32 key)
246 return (key << 24) | (key >> 8);
249 static int mlx4_SW2HW_MPT(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
252 return mlx4_cmd(dev, mailbox->dma, mpt_index, 0, MLX4_CMD_SW2HW_MPT,
253 MLX4_CMD_TIME_CLASS_B);
256 static int mlx4_HW2SW_MPT(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
259 return mlx4_cmd_box(dev, 0, mailbox ? mailbox->dma : 0, mpt_index,
260 !mailbox, MLX4_CMD_HW2SW_MPT, MLX4_CMD_TIME_CLASS_B);
263 int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access,
264 int npages, int page_shift, struct mlx4_mr *mr)
266 struct mlx4_priv *priv = mlx4_priv(dev);
270 index = mlx4_bitmap_alloc(&priv->mr_table.mpt_bitmap);
279 mr->key = hw_index_to_key(index);
281 err = mlx4_mtt_init(dev, npages, page_shift, &mr->mtt);
283 mlx4_bitmap_free(&priv->mr_table.mpt_bitmap, index);
287 EXPORT_SYMBOL_GPL(mlx4_mr_alloc);
289 void mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr)
291 struct mlx4_priv *priv = mlx4_priv(dev);
295 err = mlx4_HW2SW_MPT(dev, NULL,
296 key_to_hw_index(mr->key) &
297 (dev->caps.num_mpts - 1));
299 mlx4_warn(dev, "HW2SW_MPT failed (%d)\n", err);
302 mlx4_mtt_cleanup(dev, &mr->mtt);
303 mlx4_bitmap_free(&priv->mr_table.mpt_bitmap, key_to_hw_index(mr->key));
305 EXPORT_SYMBOL_GPL(mlx4_mr_free);
307 int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr)
309 struct mlx4_mr_table *mr_table = &mlx4_priv(dev)->mr_table;
310 struct mlx4_cmd_mailbox *mailbox;
311 struct mlx4_mpt_entry *mpt_entry;
314 err = mlx4_table_get(dev, &mr_table->dmpt_table, key_to_hw_index(mr->key));
318 mailbox = mlx4_alloc_cmd_mailbox(dev);
319 if (IS_ERR(mailbox)) {
320 err = PTR_ERR(mailbox);
323 mpt_entry = mailbox->buf;
325 memset(mpt_entry, 0, sizeof *mpt_entry);
327 mpt_entry->flags = cpu_to_be32(MLX4_MPT_FLAG_SW_OWNS |
329 MLX4_MPT_FLAG_REGION |
332 mpt_entry->key = cpu_to_be32(key_to_hw_index(mr->key));
333 mpt_entry->pd = cpu_to_be32(mr->pd);
334 mpt_entry->start = cpu_to_be64(mr->iova);
335 mpt_entry->length = cpu_to_be64(mr->size);
336 mpt_entry->entity_size = cpu_to_be32(mr->mtt.page_shift);
337 if (mr->mtt.order < 0) {
338 mpt_entry->flags |= cpu_to_be32(MLX4_MPT_FLAG_PHYSICAL);
339 mpt_entry->mtt_seg = 0;
341 mpt_entry->mtt_seg = cpu_to_be64(mlx4_mtt_addr(dev, &mr->mtt));
343 err = mlx4_SW2HW_MPT(dev, mailbox,
344 key_to_hw_index(mr->key) & (dev->caps.num_mpts - 1));
346 mlx4_warn(dev, "SW2HW_MPT failed (%d)\n", err);
352 mlx4_free_cmd_mailbox(dev, mailbox);
357 mlx4_free_cmd_mailbox(dev, mailbox);
360 mlx4_table_put(dev, &mr_table->dmpt_table, key_to_hw_index(mr->key));
363 EXPORT_SYMBOL_GPL(mlx4_mr_enable);
365 static int mlx4_write_mtt_chunk(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
366 int start_index, int npages, u64 *page_list)
368 struct mlx4_priv *priv = mlx4_priv(dev);
370 dma_addr_t dma_handle;
372 int s = start_index * sizeof (u64);
374 /* All MTTs must fit in the same page */
375 if (start_index / (PAGE_SIZE / sizeof (u64)) !=
376 (start_index + npages - 1) / (PAGE_SIZE / sizeof (u64)))
379 if (start_index & (MLX4_MTT_ENTRY_PER_SEG - 1))
382 mtts = mlx4_table_find(&priv->mr_table.mtt_table, mtt->first_seg +
383 s / dev->caps.mtt_entry_sz, &dma_handle);
387 for (i = 0; i < npages; ++i)
388 mtts[i] = cpu_to_be64(page_list[i] | MLX4_MTT_FLAG_PRESENT);
390 dma_sync_single(&dev->pdev->dev, dma_handle, npages * sizeof (u64), DMA_TO_DEVICE);
395 int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
396 int start_index, int npages, u64 *page_list)
405 chunk = min_t(int, PAGE_SIZE / sizeof(u64), npages);
406 err = mlx4_write_mtt_chunk(dev, mtt, start_index, chunk, page_list);
411 start_index += chunk;
417 EXPORT_SYMBOL_GPL(mlx4_write_mtt);
419 int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
420 struct mlx4_buf *buf)
426 page_list = kmalloc(buf->npages * sizeof *page_list, GFP_KERNEL);
430 for (i = 0; i < buf->npages; ++i)
432 page_list[i] = buf->direct.map + (i << buf->page_shift);
434 page_list[i] = buf->page_list[i].map;
436 err = mlx4_write_mtt(dev, mtt, 0, buf->npages, page_list);
441 EXPORT_SYMBOL_GPL(mlx4_buf_write_mtt);
443 int mlx4_init_mr_table(struct mlx4_dev *dev)
445 struct mlx4_mr_table *mr_table = &mlx4_priv(dev)->mr_table;
448 err = mlx4_bitmap_init(&mr_table->mpt_bitmap, dev->caps.num_mpts,
449 ~0, dev->caps.reserved_mrws);
453 err = mlx4_buddy_init(&mr_table->mtt_buddy,
454 ilog2(dev->caps.num_mtt_segs));
458 if (dev->caps.reserved_mtts) {
459 if (mlx4_alloc_mtt_range(dev, fls(dev->caps.reserved_mtts - 1)) == -1) {
460 mlx4_warn(dev, "MTT table of order %d is too small.\n",
461 mr_table->mtt_buddy.max_order);
463 goto err_reserve_mtts;
470 mlx4_buddy_cleanup(&mr_table->mtt_buddy);
473 mlx4_bitmap_cleanup(&mr_table->mpt_bitmap);
478 void mlx4_cleanup_mr_table(struct mlx4_dev *dev)
480 struct mlx4_mr_table *mr_table = &mlx4_priv(dev)->mr_table;
482 mlx4_buddy_cleanup(&mr_table->mtt_buddy);
483 mlx4_bitmap_cleanup(&mr_table->mpt_bitmap);
486 static inline int mlx4_check_fmr(struct mlx4_fmr *fmr, u64 *page_list,
487 int npages, u64 iova)
491 if (npages > fmr->max_pages)
494 page_mask = (1 << fmr->page_shift) - 1;
496 /* We are getting page lists, so va must be page aligned. */
497 if (iova & page_mask)
500 /* Trust the user not to pass misaligned data in page_list */
502 for (i = 0; i < npages; ++i) {
503 if (page_list[i] & ~page_mask)
507 if (fmr->maps >= fmr->max_maps)
513 int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list,
514 int npages, u64 iova, u32 *lkey, u32 *rkey)
519 err = mlx4_check_fmr(fmr, page_list, npages, iova);
525 key = key_to_hw_index(fmr->mr.key);
526 key += dev->caps.num_mpts;
527 *lkey = *rkey = fmr->mr.key = hw_index_to_key(key);
529 *(u8 *) fmr->mpt = MLX4_MPT_STATUS_SW;
531 /* Make sure MPT status is visible before writing MTT entries */
534 for (i = 0; i < npages; ++i)
535 fmr->mtts[i] = cpu_to_be64(page_list[i] | MLX4_MTT_FLAG_PRESENT);
537 dma_sync_single(&dev->pdev->dev, fmr->dma_handle,
538 npages * sizeof(u64), DMA_TO_DEVICE);
540 fmr->mpt->key = cpu_to_be32(key);
541 fmr->mpt->lkey = cpu_to_be32(key);
542 fmr->mpt->length = cpu_to_be64(npages * (1ull << fmr->page_shift));
543 fmr->mpt->start = cpu_to_be64(iova);
545 /* Make MTT entries are visible before setting MPT status */
548 *(u8 *) fmr->mpt = MLX4_MPT_STATUS_HW;
550 /* Make sure MPT status is visible before consumer can use FMR */
555 EXPORT_SYMBOL_GPL(mlx4_map_phys_fmr);
557 int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages,
558 int max_maps, u8 page_shift, struct mlx4_fmr *fmr)
560 struct mlx4_priv *priv = mlx4_priv(dev);
564 if (page_shift < (ffs(dev->caps.page_size_cap) - 1) || page_shift >= 32)
567 /* All MTTs must fit in the same page */
568 if (max_pages * sizeof *fmr->mtts > PAGE_SIZE)
571 fmr->page_shift = page_shift;
572 fmr->max_pages = max_pages;
573 fmr->max_maps = max_maps;
576 err = mlx4_mr_alloc(dev, pd, 0, 0, access, max_pages,
577 page_shift, &fmr->mr);
581 mtt_seg = fmr->mr.mtt.first_seg * dev->caps.mtt_entry_sz;
583 fmr->mtts = mlx4_table_find(&priv->mr_table.mtt_table,
584 fmr->mr.mtt.first_seg,
594 mlx4_mr_free(dev, &fmr->mr);
597 EXPORT_SYMBOL_GPL(mlx4_fmr_alloc);
599 int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr)
601 struct mlx4_priv *priv = mlx4_priv(dev);
604 err = mlx4_mr_enable(dev, &fmr->mr);
608 fmr->mpt = mlx4_table_find(&priv->mr_table.dmpt_table,
609 key_to_hw_index(fmr->mr.key), NULL);
615 EXPORT_SYMBOL_GPL(mlx4_fmr_enable);
617 void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr,
618 u32 *lkey, u32 *rkey)
625 *(u8 *) fmr->mpt = MLX4_MPT_STATUS_SW;
627 EXPORT_SYMBOL_GPL(mlx4_fmr_unmap);
629 int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr)
635 mlx4_mr_free(dev, &fmr->mr);
639 EXPORT_SYMBOL_GPL(mlx4_fmr_free);
641 int mlx4_SYNC_TPT(struct mlx4_dev *dev)
643 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_SYNC_TPT, 1000);
645 EXPORT_SYMBOL_GPL(mlx4_SYNC_TPT);