2 * Copyright (C) 2003 - 2006 NetXen, Inc.
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
20 * The full GNU General Public License is included in this distribution
21 * in the file called LICENSE.
23 * Contact Information:
26 * 3965 Freedom Circle, Fourth floor,
27 * Santa Clara, CA 95054
30 #ifndef _NETXEN_NIC_H_
31 #define _NETXEN_NIC_H_
33 #include <linux/module.h>
34 #include <linux/kernel.h>
35 #include <linux/types.h>
36 #include <linux/compiler.h>
37 #include <linux/slab.h>
38 #include <linux/delay.h>
39 #include <linux/init.h>
40 #include <linux/ioport.h>
41 #include <linux/pci.h>
42 #include <linux/netdevice.h>
43 #include <linux/etherdevice.h>
46 #include <linux/tcp.h>
47 #include <linux/skbuff.h>
48 #include <linux/version.h>
50 #include <linux/ethtool.h>
51 #include <linux/mii.h>
52 #include <linux/interrupt.h>
53 #include <linux/timer.h>
56 #include <linux/mman.h>
58 #include <asm/system.h>
60 #include <asm/byteorder.h>
61 #include <asm/uaccess.h>
62 #include <asm/pgtable.h>
64 #include "netxen_nic_hw.h"
66 #define _NETXEN_NIC_LINUX_MAJOR 3
67 #define _NETXEN_NIC_LINUX_MINOR 3
68 #define _NETXEN_NIC_LINUX_SUBVERSION 3
69 #define NETXEN_NIC_LINUX_VERSIONID "3.3.3"
71 #define NUM_FLASH_SECTORS (64)
72 #define FLASH_SECTOR_SIZE (64 * 1024)
73 #define FLASH_TOTAL_SIZE (NUM_FLASH_SECTORS * FLASH_SECTOR_SIZE)
75 #define RCV_DESC_RINGSIZE \
76 (sizeof(struct rcv_desc) * adapter->max_rx_desc_count)
77 #define STATUS_DESC_RINGSIZE \
78 (sizeof(struct status_desc)* adapter->max_rx_desc_count)
79 #define LRO_DESC_RINGSIZE \
80 (sizeof(rcvDesc_t) * adapter->max_lro_rx_desc_count)
82 (sizeof(struct netxen_cmd_buffer) * adapter->max_tx_desc_count)
83 #define RCV_BUFFSIZE \
84 (sizeof(struct netxen_rx_buffer) * rcv_desc->max_rx_desc_count)
85 #define find_diff_among(a,b,range) ((a)<(b)?((b)-(a)):((b)+(range)-(a)))
87 #define NETXEN_NETDEV_STATUS 0x1
88 #define NETXEN_RCV_PRODUCER_OFFSET 0
89 #define NETXEN_RCV_PEG_DB_ID 2
90 #define NETXEN_HOST_DUMMY_DMA_SIZE 1024
91 #define FLASH_SUCCESS 0
93 #define ADDR_IN_WINDOW1(off) \
94 ((off > NETXEN_CRB_PCIX_HOST2) && (off < NETXEN_CRB_MAX)) ? 1 : 0
96 * In netxen_nic_down(), we must wait for any pending callback requests into
97 * netxen_watchdog_task() to complete; eg otherwise the watchdog_timer could be
98 * reenabled right after it is deleted in netxen_nic_down(). FLUSH_SCHEDULED_WORK()
99 * does this synchronization.
101 * Normally, schedule_work()/flush_scheduled_work() could have worked, but
102 * netxen_nic_close() is invoked with kernel rtnl lock held. netif_carrier_off()
103 * call in netxen_nic_close() triggers a schedule_work(&linkwatch_work), and a
104 * subsequent call to flush_scheduled_work() in netxen_nic_down() would cause
105 * linkwatch_event() to be executed which also attempts to acquire the rtnl
106 * lock thus causing a deadlock.
109 #define SCHEDULE_WORK(tp) queue_work(netxen_workq, tp)
110 #define FLUSH_SCHEDULED_WORK() flush_workqueue(netxen_workq)
111 extern struct workqueue_struct *netxen_workq;
114 * normalize a 64MB crb address to 32MB PCI window
115 * To use NETXEN_CRB_NORMALIZE, window _must_ be set to 1
117 #define NETXEN_CRB_NORMAL(reg) \
118 ((reg) - NETXEN_CRB_PCIX_HOST2 + NETXEN_CRB_PCIX_HOST)
120 #define NETXEN_CRB_NORMALIZE(adapter, reg) \
121 pci_base_offset(adapter, NETXEN_CRB_NORMAL(reg))
123 #define DB_NORMALIZE(adapter, off) \
124 (adapter->ahw.db_base + (off))
126 #define NX_P2_C0 0x24
127 #define NX_P2_C1 0x25
129 #define FIRST_PAGE_GROUP_START 0
130 #define FIRST_PAGE_GROUP_END 0x100000
132 #define SECOND_PAGE_GROUP_START 0x4000000
133 #define SECOND_PAGE_GROUP_END 0x66BC000
135 #define THIRD_PAGE_GROUP_START 0x70E4000
136 #define THIRD_PAGE_GROUP_END 0x8000000
138 #define FIRST_PAGE_GROUP_SIZE FIRST_PAGE_GROUP_END - FIRST_PAGE_GROUP_START
139 #define SECOND_PAGE_GROUP_SIZE SECOND_PAGE_GROUP_END - SECOND_PAGE_GROUP_START
140 #define THIRD_PAGE_GROUP_SIZE THIRD_PAGE_GROUP_END - THIRD_PAGE_GROUP_START
142 #define MAX_RX_BUFFER_LENGTH 1760
143 #define MAX_RX_JUMBO_BUFFER_LENGTH 8062
144 #define MAX_RX_LRO_BUFFER_LENGTH ((48*1024)-512)
145 #define RX_DMA_MAP_LEN (MAX_RX_BUFFER_LENGTH - 2)
146 #define RX_JUMBO_DMA_MAP_LEN \
147 (MAX_RX_JUMBO_BUFFER_LENGTH - 2)
148 #define RX_LRO_DMA_MAP_LEN (MAX_RX_LRO_BUFFER_LENGTH - 2)
149 #define NETXEN_ROM_ROUNDUP 0x80000000ULL
152 * Maximum number of ring contexts
154 #define MAX_RING_CTX 1
156 /* Opcodes to be used with the commands */
159 /* The following opcodes are for IP checksum */
168 /* The following opcodes are for internal consumption. */
169 #define NETXEN_CONTROL_OP 0x10
170 #define PEGNET_REQUEST 0x11
172 #define MAX_NUM_CARDS 4
174 #define MAX_BUFFERS_PER_CMD 32
177 * Following are the states of the Phantom. Phantom will set them and
178 * Host will read to check if the fields are correct.
180 #define PHAN_INITIALIZE_START 0xff00
181 #define PHAN_INITIALIZE_FAILED 0xffff
182 #define PHAN_INITIALIZE_COMPLETE 0xff01
184 /* Host writes the following to notify that it has done the init-handshake */
185 #define PHAN_INITIALIZE_ACK 0xf00f
187 #define NUM_RCV_DESC_RINGS 3 /* No of Rcv Descriptor contexts */
189 /* descriptor types */
190 #define RCV_DESC_NORMAL 0x01
191 #define RCV_DESC_JUMBO 0x02
192 #define RCV_DESC_LRO 0x04
193 #define RCV_DESC_NORMAL_CTXID 0
194 #define RCV_DESC_JUMBO_CTXID 1
195 #define RCV_DESC_LRO_CTXID 2
197 #define RCV_DESC_TYPE(ID) \
198 ((ID == RCV_DESC_JUMBO_CTXID) \
200 : ((ID == RCV_DESC_LRO_CTXID) \
204 #define MAX_CMD_DESCRIPTORS 1024
205 #define MAX_RCV_DESCRIPTORS 16384
206 #define MAX_JUMBO_RCV_DESCRIPTORS 1024
207 #define MAX_LRO_RCV_DESCRIPTORS 64
208 #define MAX_RCVSTATUS_DESCRIPTORS MAX_RCV_DESCRIPTORS
209 #define MAX_JUMBO_RCV_DESC MAX_JUMBO_RCV_DESCRIPTORS
210 #define MAX_RCV_DESC MAX_RCV_DESCRIPTORS
211 #define MAX_RCVSTATUS_DESC MAX_RCV_DESCRIPTORS
212 #define MAX_EPG_DESCRIPTORS (MAX_CMD_DESCRIPTORS * 8)
213 #define NUM_RCV_DESC (MAX_RCV_DESC + MAX_JUMBO_RCV_DESCRIPTORS + \
214 MAX_LRO_RCV_DESCRIPTORS)
215 #define MIN_TX_COUNT 4096
216 #define MIN_RX_COUNT 4096
217 #define NETXEN_CTX_SIGNATURE 0xdee0
218 #define NETXEN_RCV_PRODUCER(ringid) (ringid)
219 #define MAX_FRAME_SIZE 0x10000 /* 64K MAX size for LSO */
221 #define PHAN_PEG_RCV_INITIALIZED 0xff01
222 #define PHAN_PEG_RCV_START_INITIALIZE 0xff00
224 #define get_next_index(index, length) \
225 (((index) + 1) & ((length) - 1))
227 #define get_index_range(index,length,count) \
228 (((index) + (count)) & ((length) - 1))
230 #define MPORT_SINGLE_FUNCTION_MODE 0x1111
232 extern unsigned long long netxen_dma_mask;
235 * NetXen host-peg signal message structure
237 * Bit 0-1 : peg_id => 0x2 for tx and 01 for rx
238 * Bit 2 : priv_id => must be 1
239 * Bit 3-17 : count => for doorbell
240 * Bit 18-27 : ctx_id => Context id
244 typedef u32 netxen_ctx_msg;
246 #define netxen_set_msg_peg_id(config_word, val) \
247 ((config_word) &= ~3, (config_word) |= val & 3)
248 #define netxen_set_msg_privid(config_word) \
249 ((config_word) |= 1 << 2)
250 #define netxen_set_msg_count(config_word, val) \
251 ((config_word) &= ~(0x7fff<<3), (config_word) |= (val & 0x7fff) << 3)
252 #define netxen_set_msg_ctxid(config_word, val) \
253 ((config_word) &= ~(0x3ff<<18), (config_word) |= (val & 0x3ff) << 18)
254 #define netxen_set_msg_opcode(config_word, val) \
255 ((config_word) &= ~(0xf<<24), (config_word) |= (val & 0xf) << 24)
257 struct netxen_rcv_context {
258 __le64 rcv_ring_addr;
259 __le32 rcv_ring_size;
263 struct netxen_ring_ctx {
265 /* one command ring */
266 __le64 cmd_consumer_offset;
267 __le64 cmd_ring_addr;
268 __le32 cmd_ring_size;
271 /* three receive rings */
272 struct netxen_rcv_context rcv_ctx[3];
274 /* one status ring */
275 __le64 sts_ring_addr;
276 __le32 sts_ring_size;
279 } __attribute__ ((aligned(64)));
282 * Following data structures describe the descriptors that will be used.
283 * Added fileds of tcpHdrSize and ipHdrSize, The driver needs to do it only when
284 * we are doing LSO (above the 1500 size packet) only.
288 * The size of reference handle been changed to 16 bits to pass the MSS fields
292 #define FLAGS_CHECKSUM_ENABLED 0x01
293 #define FLAGS_LSO_ENABLED 0x02
294 #define FLAGS_IPSEC_SA_ADD 0x04
295 #define FLAGS_IPSEC_SA_DELETE 0x08
296 #define FLAGS_VLAN_TAGGED 0x10
298 #define netxen_set_cmd_desc_port(cmd_desc, var) \
299 ((cmd_desc)->port_ctxid |= ((var) & 0x0F))
301 #define netxen_set_cmd_desc_flags(cmd_desc, val) \
302 ((cmd_desc)->flags_opcode &= ~cpu_to_le16(0x7f), \
303 (cmd_desc)->flags_opcode |= cpu_to_le16((val) & 0x7f))
304 #define netxen_set_cmd_desc_opcode(cmd_desc, val) \
305 ((cmd_desc)->flags_opcode &= ~cpu_to_le16(0x3f<<7), \
306 (cmd_desc)->flags_opcode |= cpu_to_le16((val) & (0x3f<<7)))
308 #define netxen_set_cmd_desc_num_of_buff(cmd_desc, val) \
309 ((cmd_desc)->num_of_buffers_total_length &= ~cpu_to_le32(0xff), \
310 (cmd_desc)->num_of_buffers_total_length |= cpu_to_le32((val) & 0xff))
311 #define netxen_set_cmd_desc_totallength(cmd_desc, val) \
312 ((cmd_desc)->num_of_buffers_total_length &= cpu_to_le32(0xff), \
313 (cmd_desc)->num_of_buffers_total_length |= cpu_to_le32(val << 24))
315 #define netxen_get_cmd_desc_opcode(cmd_desc) \
316 ((le16_to_cpu((cmd_desc)->flags_opcode) >> 7) & 0x003F)
317 #define netxen_get_cmd_desc_totallength(cmd_desc) \
318 (le32_to_cpu((cmd_desc)->num_of_buffers_total_length) >> 8)
320 struct cmd_desc_type0 {
321 u8 tcp_hdr_offset; /* For LSO only */
322 u8 ip_hdr_offset; /* For LSO only */
323 /* Bit pattern: 0-6 flags, 7-12 opcode, 13-15 unused */
325 /* Bit pattern: 0-7 total number of segments,
326 8-31 Total size of the packet */
327 __le32 num_of_buffers_total_length;
330 __le32 addr_low_part2;
331 __le32 addr_high_part2;
336 __le16 reference_handle; /* changed to u16 to add mss */
337 __le16 mss; /* passed by NDIS_PACKET for LSO */
338 /* Bit pattern 0-3 port, 0-3 ctx id */
340 u8 total_hdr_length; /* LSO only : MAC+IP+TCP Hdr size */
341 __le16 conn_id; /* IPSec offoad only */
345 __le32 addr_low_part3;
346 __le32 addr_high_part3;
352 __le32 addr_low_part1;
353 __le32 addr_high_part1;
358 __le16 buffer1_length;
359 __le16 buffer2_length;
360 __le16 buffer3_length;
361 __le16 buffer4_length;
365 __le32 addr_low_part4;
366 __le32 addr_high_part4;
373 } __attribute__ ((aligned(64)));
375 /* Note: sizeof(rcv_desc) should always be a mutliple of 2 */
377 __le16 reference_handle;
379 __le32 buffer_length; /* allocated buffer length (usually 2K) */
383 /* opcode field in status_desc */
384 #define RCV_NIC_PKT (0xA)
385 #define STATUS_NIC_PKT ((RCV_NIC_PKT) << 12)
387 /* for status field in status_desc */
388 #define STATUS_NEED_CKSUM (1)
389 #define STATUS_CKSUM_OK (2)
391 /* owner bits of status_desc */
392 #define STATUS_OWNER_HOST (0x1)
393 #define STATUS_OWNER_PHANTOM (0x2)
395 #define NETXEN_PROT_IP (1)
396 #define NETXEN_PROT_UNKNOWN (0)
398 /* Note: sizeof(status_desc) should always be a mutliple of 2 */
400 #define netxen_get_sts_desc_lro_cnt(status_desc) \
401 ((status_desc)->lro & 0x7F)
402 #define netxen_get_sts_desc_lro_last_frag(status_desc) \
403 (((status_desc)->lro & 0x80) >> 7)
405 #define netxen_get_sts_port(status_desc) \
406 (le64_to_cpu((status_desc)->status_desc_data) & 0x0F)
407 #define netxen_get_sts_status(status_desc) \
408 ((le64_to_cpu((status_desc)->status_desc_data) >> 4) & 0x0F)
409 #define netxen_get_sts_type(status_desc) \
410 ((le64_to_cpu((status_desc)->status_desc_data) >> 8) & 0x0F)
411 #define netxen_get_sts_totallength(status_desc) \
412 ((le64_to_cpu((status_desc)->status_desc_data) >> 12) & 0xFFFF)
413 #define netxen_get_sts_refhandle(status_desc) \
414 ((le64_to_cpu((status_desc)->status_desc_data) >> 28) & 0xFFFF)
415 #define netxen_get_sts_prot(status_desc) \
416 ((le64_to_cpu((status_desc)->status_desc_data) >> 44) & 0x0F)
417 #define netxen_get_sts_owner(status_desc) \
418 ((le64_to_cpu((status_desc)->status_desc_data) >> 56) & 0x03)
419 #define netxen_get_sts_opcode(status_desc) \
420 ((le64_to_cpu((status_desc)->status_desc_data) >> 58) & 0x03F)
422 #define netxen_clear_sts_owner(status_desc) \
423 ((status_desc)->status_desc_data &= \
424 ~cpu_to_le64(((unsigned long long)3) << 56 ))
425 #define netxen_set_sts_owner(status_desc, val) \
426 ((status_desc)->status_desc_data |= \
427 cpu_to_le64(((unsigned long long)((val) & 0x3)) << 56 ))
430 /* Bit pattern: 0-3 port, 4-7 status, 8-11 type, 12-27 total_length
431 28-43 reference_handle, 44-47 protocol, 48-52 unused
432 53-55 desc_cnt, 56-57 owner, 58-63 opcode
434 __le64 status_desc_data;
439 /* Bit pattern: 0-6 lro_count indicates frag sequence,
440 7 last_frag indicates last frag */
442 } __attribute__ ((aligned(8)));
445 NETXEN_RCV_PEG_0 = 0,
448 /* The version of the main data structure */
449 #define NETXEN_BDINFO_VERSION 1
451 /* Magic number to let user know flash is programmed */
452 #define NETXEN_BDINFO_MAGIC 0x12345678
454 /* Max number of Gig ports on a Phantom board */
455 #define NETXEN_MAX_PORTS 4
458 NETXEN_BRDTYPE_P1_BD = 0x0000,
459 NETXEN_BRDTYPE_P1_SB = 0x0001,
460 NETXEN_BRDTYPE_P1_SMAX = 0x0002,
461 NETXEN_BRDTYPE_P1_SOCK = 0x0003,
463 NETXEN_BRDTYPE_P2_SOCK_31 = 0x0008,
464 NETXEN_BRDTYPE_P2_SOCK_35 = 0x0009,
465 NETXEN_BRDTYPE_P2_SB35_4G = 0x000a,
466 NETXEN_BRDTYPE_P2_SB31_10G = 0x000b,
467 NETXEN_BRDTYPE_P2_SB31_2G = 0x000c,
469 NETXEN_BRDTYPE_P2_SB31_10G_IMEZ = 0x000d,
470 NETXEN_BRDTYPE_P2_SB31_10G_HMEZ = 0x000e,
471 NETXEN_BRDTYPE_P2_SB31_10G_CX4 = 0x000f
475 NETXEN_BRDMFG_INVENTEC = 1
479 MEM_ORG_128Mbx4 = 0x0, /* DDR1 only */
480 MEM_ORG_128Mbx8 = 0x1, /* DDR1 only */
481 MEM_ORG_128Mbx16 = 0x2, /* DDR1 only */
482 MEM_ORG_256Mbx4 = 0x3,
483 MEM_ORG_256Mbx8 = 0x4,
484 MEM_ORG_256Mbx16 = 0x5,
485 MEM_ORG_512Mbx4 = 0x6,
486 MEM_ORG_512Mbx8 = 0x7,
487 MEM_ORG_512Mbx16 = 0x8,
490 MEM_ORG_1Gbx16 = 0xb,
493 MEM_ORG_2Gbx16 = 0xe,
494 MEM_ORG_128Mbx32 = 0x10002, /* GDDR only */
495 MEM_ORG_256Mbx32 = 0x10005 /* GDDR only */
496 } netxen_mn_mem_org_t;
499 MEM_ORG_512Kx36 = 0x0,
502 } netxen_sn_mem_org_t;
507 MEM_DEPTH_16MB = 0x3,
508 MEM_DEPTH_32MB = 0x4,
509 MEM_DEPTH_64MB = 0x5,
510 MEM_DEPTH_128MB = 0x6,
511 MEM_DEPTH_256MB = 0x7,
512 MEM_DEPTH_512MB = 0x8,
517 MEM_DEPTH_16GB = 0xd,
519 } netxen_mem_depth_t;
521 struct netxen_board_info {
533 u32 port_mask; /* available niu ports */
534 u32 peg_mask; /* available pegs */
535 u32 icache_ok; /* can we run with icache? */
536 u32 dcache_ok; /* can we run with dcache? */
544 /* MN-related config */
545 u32 mn_sync_mode; /* enable/ sync shift cclk/ sync shift mclk */
546 u32 mn_sync_shift_cclk;
547 u32 mn_sync_shift_mclk;
549 u32 mn_crystal_freq; /* in MHz */
550 u32 mn_speed; /* in MHz */
553 u32 mn_ranks_0; /* ranks per slot */
554 u32 mn_ranks_1; /* ranks per slot */
565 u32 mn_mode_reg; /* MIU DDR Mode Register */
566 u32 mn_ext_mode_reg; /* MIU DDR Extended Mode Register */
567 u32 mn_timing_0; /* MIU Memory Control Timing Rgister */
568 u32 mn_timing_1; /* MIU Extended Memory Ctrl Timing Register */
569 u32 mn_timing_2; /* MIU Extended Memory Ctrl Timing2 Register */
571 /* SN-related config */
572 u32 sn_sync_mode; /* enable/ sync shift cclk / sync shift mclk */
573 u32 sn_pt_mode; /* pass through mode */
588 u32 magic; /* indicates flash has been initialized */
595 #define FLASH_NUM_PORTS (4)
597 struct netxen_flash_mac_addr {
601 struct netxen_user_old_info {
613 /* primary image status */
615 u32 secondary_present;
617 /* MAC address , 4 ports */
618 struct netxen_flash_mac_addr mac_addr[FLASH_NUM_PORTS];
620 #define FLASH_NUM_MAC_PER_PORT 32
621 struct netxen_user_info {
622 u8 flash_md5[16 * 64];
629 /* primary image status */
631 u32 secondary_present;
633 /* MAC address , 4 ports, 32 address per port */
634 u64 mac_addr[FLASH_NUM_PORTS * FLASH_NUM_MAC_PER_PORT];
638 /* Any user defined data */
642 * Flash Layout - new format.
644 struct netxen_new_user_info {
645 u8 flash_md5[16 * 64];
652 /* primary image status */
654 u32 secondary_present;
656 /* MAC address , 4 ports, 32 address per port */
657 u64 mac_addr[FLASH_NUM_PORTS * FLASH_NUM_MAC_PER_PORT];
661 /* Any user defined data */
664 #define SECONDARY_IMAGE_PRESENT 0xb3b4b5b6
665 #define SECONDARY_IMAGE_ABSENT 0xffffffff
666 #define PRIMARY_IMAGE_GOOD 0x5a5a5a5a
667 #define PRIMARY_IMAGE_BAD 0xffffffff
669 /* Flash memory map */
671 CRBINIT_START = 0, /* Crbinit section */
672 BRDCFG_START = 0x4000, /* board config */
673 INITCODE_START = 0x6000, /* pegtune code */
674 BOOTLD_START = 0x10000, /* bootld */
675 IMAGE_START = 0x43000, /* compressed image */
676 SECONDARY_START = 0x200000, /* backup images */
677 PXE_START = 0x3E0000, /* user defined region */
678 USER_START = 0x3E8000, /* User defined region for new boards */
679 FIXED_START = 0x3F0000 /* backup of crbinit */
680 } netxen_flash_map_t;
682 #define USER_START_OLD PXE_START /* for backward compatibility */
684 #define FLASH_START (CRBINIT_START)
685 #define INIT_SECTOR (0)
686 #define PRIMARY_START (BOOTLD_START)
687 #define FLASH_CRBINIT_SIZE (0x4000)
688 #define FLASH_BRDCFG_SIZE (sizeof(struct netxen_board_info))
689 #define FLASH_USER_SIZE (sizeof(struct netxen_user_info)/sizeof(u32))
690 #define FLASH_SECONDARY_SIZE (USER_START-SECONDARY_START)
691 #define NUM_PRIMARY_SECTORS (0x20)
692 #define NUM_CONFIG_SECTORS (1)
693 #define PFX "NetXen: "
694 extern char netxen_nic_driver_name[];
696 /* Note: Make sure to not call this before adapter->port is valid */
697 #if !defined(NETXEN_DEBUG)
698 #define DPRINTK(klevel, fmt, args...) do { \
701 #define DPRINTK(klevel, fmt, args...) do { \
702 printk(KERN_##klevel PFX "%s: %s: " fmt, __FUNCTION__,\
703 (adapter != NULL && \
704 adapter->port[0] != NULL && \
705 adapter->port[0]->netdev != NULL) ? \
706 adapter->port[0]->netdev->name : NULL, \
710 /* Number of status descriptors to handle per interrupt */
711 #define MAX_STATUS_HANDLE (128)
714 * netxen_skb_frag{} is to contain mapping info for each SG list. This
715 * has to be freed when DMA is complete. This is part of netxen_tx_buffer{}.
717 struct netxen_skb_frag {
722 /* Following defines are for the state of the buffers */
723 #define NETXEN_BUFFER_FREE 0
724 #define NETXEN_BUFFER_BUSY 1
727 * There will be one netxen_buffer per skb packet. These will be
728 * used to save the dma info for pci_unmap_page()
730 struct netxen_cmd_buffer {
732 struct netxen_skb_frag frag_array[MAX_BUFFERS_PER_CMD + 1];
738 unsigned long time_stamp;
742 /* In rx_buffer, we do not need multiple fragments as is a single buffer */
743 struct netxen_rx_buffer {
748 u32 lro_expected_frags;
749 u32 lro_current_frags;
754 #define NETXEN_NIC_GBE 0x01
755 #define NETXEN_NIC_XGBE 0x02
758 * One hardware_context{} per adapter
759 * contains interrupt info as well shared hardware info.
761 struct netxen_hardware_context {
762 struct pci_dev *pdev;
763 void __iomem *pci_base0;
764 void __iomem *pci_base1;
765 void __iomem *pci_base2;
766 void __iomem *db_base;
767 unsigned long db_len;
772 struct netxen_board_info boardcfg;
775 /* Address of cmd ring in Phantom */
776 struct cmd_desc_type0 *cmd_desc_head;
777 struct pci_dev *cmd_desc_pdev;
778 dma_addr_t cmd_desc_phys_addr;
779 struct netxen_adapter *adapter;
782 #define RCV_RING_LRO RCV_DESC_LRO
784 #define MINIMUM_ETHERNET_FRAME_SIZE 64 /* With FCS */
785 #define ETHERNET_FCS_SIZE 4
787 struct netxen_adapter_stats {
802 * Rcv Descriptor Context. One such per Rcv Descriptor. There may
803 * be one Rcv Descriptor for normal packets, one for jumbo and may be others.
805 struct netxen_rcv_desc_ctx {
808 u32 rcv_pending; /* Num of bufs posted in phantom */
809 u32 rcv_free; /* Num of bufs in free list */
810 dma_addr_t phys_addr;
811 struct pci_dev *phys_pdev;
812 struct rcv_desc *desc_head; /* address of rx ring in Phantom */
813 u32 max_rx_desc_count;
816 struct netxen_rx_buffer *rx_buf_arr; /* rx buffers for receive */
821 * Receive context. There is one such structure per instance of the
822 * receive processing. Any state information that is relevant to
823 * the receive, and is must be in this structure. The global data may be
826 struct netxen_recv_context {
827 struct netxen_rcv_desc_ctx rcv_desc[NUM_RCV_DESC_RINGS];
828 u32 status_rx_producer;
829 u32 status_rx_consumer;
830 dma_addr_t rcv_status_desc_phys_addr;
831 struct pci_dev *rcv_status_desc_pdev;
832 struct status_desc *rcv_status_desc_head;
835 #define NETXEN_NIC_MSI_ENABLED 0x02
836 #define NETXEN_DMA_MASK 0xfffffffe
837 #define NETXEN_DB_MAPSIZE_BYTES 0x1000
839 struct netxen_dummy_dma {
841 dma_addr_t phys_addr;
844 struct netxen_adapter {
845 struct netxen_hardware_context ahw;
846 int port_count; /* Number of configured ports */
847 int active_ports; /* Number of open ports */
848 struct netxen_port *port[NETXEN_MAX_PORTS]; /* ptr to each port */
851 struct work_struct watchdog_task;
852 struct timer_list watchdog_timer;
859 u32 last_cmd_consumer;
860 u32 max_tx_desc_count;
861 u32 max_rx_desc_count;
862 u32 max_jumbo_rx_desc_count;
863 u32 max_lro_rx_desc_count;
864 /* Num of instances active on cmd buffer ring */
865 u32 proc_cmd_buf_counter;
867 u32 num_threads, total_threads; /*Use to keep track of xmit threads */
874 struct netxen_adapter_stats stats;
876 struct netxen_cmd_buffer *cmd_buf_arr; /* Command buffers for xmit */
879 * Receive instances. These can be either one per port,
880 * or one per peg, etc.
882 struct netxen_recv_context recv_ctx[MAX_RCV_CTX];
885 struct netxen_dummy_dma dummy_dma;
887 /* Context interface shared between card and host */
888 struct netxen_ring_ctx *ctx_desc;
889 struct pci_dev *ctx_desc_pdev;
890 dma_addr_t ctx_desc_phys_addr;
891 int (*enable_phy_interrupts) (struct netxen_adapter *, int);
892 int (*disable_phy_interrupts) (struct netxen_adapter *, int);
893 void (*handle_phy_intr) (struct netxen_adapter *);
894 int (*macaddr_set) (struct netxen_port *, netxen_ethernet_macaddr_t);
895 int (*set_mtu) (struct netxen_port *, int);
896 int (*set_promisc) (struct netxen_adapter *, int,
897 netxen_niu_prom_mode_t);
898 int (*unset_promisc) (struct netxen_adapter *, int,
899 netxen_niu_prom_mode_t);
900 int (*phy_read) (struct netxen_adapter *, long phy, long reg, u32 *);
901 int (*phy_write) (struct netxen_adapter *, long phy, long reg, u32 val);
902 int (*init_port) (struct netxen_adapter *, int);
903 void (*init_niu) (struct netxen_adapter *);
904 int (*stop_port) (struct netxen_adapter *, int);
905 }; /* netxen_adapter structure */
907 /* Max number of xmit producer threads that can run simultaneously */
908 #define MAX_XMIT_PRODUCERS 16
910 struct netxen_port_stats {
934 struct netxen_adapter *adapter;
936 u16 portnum; /* GBE port number */
943 struct net_device *netdev;
944 struct pci_dev *pdev;
945 struct net_device_stats net_stats;
946 struct netxen_port_stats stats;
947 struct work_struct tx_timeout_task;
950 #define PCI_OFFSET_FIRST_RANGE(adapter, off) \
951 ((adapter)->ahw.pci_base0 + (off))
952 #define PCI_OFFSET_SECOND_RANGE(adapter, off) \
953 ((adapter)->ahw.pci_base1 + (off) - SECOND_PAGE_GROUP_START)
954 #define PCI_OFFSET_THIRD_RANGE(adapter, off) \
955 ((adapter)->ahw.pci_base2 + (off) - THIRD_PAGE_GROUP_START)
957 static inline void __iomem *pci_base_offset(struct netxen_adapter *adapter,
960 if ((off < FIRST_PAGE_GROUP_END) && (off >= FIRST_PAGE_GROUP_START)) {
961 return (adapter->ahw.pci_base0 + off);
962 } else if ((off < SECOND_PAGE_GROUP_END) &&
963 (off >= SECOND_PAGE_GROUP_START)) {
964 return (adapter->ahw.pci_base1 + off - SECOND_PAGE_GROUP_START);
965 } else if ((off < THIRD_PAGE_GROUP_END) &&
966 (off >= THIRD_PAGE_GROUP_START)) {
967 return (adapter->ahw.pci_base2 + off - THIRD_PAGE_GROUP_START);
972 static inline void __iomem *pci_base(struct netxen_adapter *adapter,
975 if ((off < FIRST_PAGE_GROUP_END) && (off >= FIRST_PAGE_GROUP_START)) {
976 return adapter->ahw.pci_base0;
977 } else if ((off < SECOND_PAGE_GROUP_END) &&
978 (off >= SECOND_PAGE_GROUP_START)) {
979 return adapter->ahw.pci_base1;
980 } else if ((off < THIRD_PAGE_GROUP_END) &&
981 (off >= THIRD_PAGE_GROUP_START)) {
982 return adapter->ahw.pci_base2;
987 int netxen_niu_xgbe_enable_phy_interrupts(struct netxen_adapter *adapter,
989 int netxen_niu_gbe_enable_phy_interrupts(struct netxen_adapter *adapter,
991 int netxen_niu_xgbe_disable_phy_interrupts(struct netxen_adapter *adapter,
993 int netxen_niu_gbe_disable_phy_interrupts(struct netxen_adapter *adapter,
995 int netxen_niu_xgbe_clear_phy_interrupts(struct netxen_adapter *adapter,
997 int netxen_niu_gbe_clear_phy_interrupts(struct netxen_adapter *adapter,
999 void netxen_nic_xgbe_handle_phy_intr(struct netxen_adapter *adapter);
1000 void netxen_nic_gbe_handle_phy_intr(struct netxen_adapter *adapter);
1001 void netxen_niu_gbe_set_mii_mode(struct netxen_adapter *adapter, int port,
1003 void netxen_niu_gbe_set_gmii_mode(struct netxen_adapter *adapter, int port,
1005 int netxen_niu_gbe_phy_read(struct netxen_adapter *adapter, long phy, long reg,
1007 int netxen_niu_gbe_phy_write(struct netxen_adapter *adapter, long phy,
1008 long reg, __u32 val);
1010 /* Functions available from netxen_nic_hw.c */
1011 int netxen_nic_set_mtu_xgb(struct netxen_port *port, int new_mtu);
1012 int netxen_nic_set_mtu_gb(struct netxen_port *port, int new_mtu);
1013 void netxen_nic_init_niu_gb(struct netxen_adapter *adapter);
1014 void netxen_nic_pci_change_crbwindow(struct netxen_adapter *adapter, u32 wndw);
1015 void netxen_nic_reg_write(struct netxen_adapter *adapter, u64 off, u32 val);
1016 int netxen_nic_reg_read(struct netxen_adapter *adapter, u64 off);
1017 void netxen_nic_write_w0(struct netxen_adapter *adapter, u32 index, u32 value);
1018 void netxen_nic_read_w0(struct netxen_adapter *adapter, u32 index, u32 * value);
1020 int netxen_nic_get_board_info(struct netxen_adapter *adapter);
1021 int netxen_nic_hw_read_wx(struct netxen_adapter *adapter, u64 off, void *data,
1023 int netxen_nic_hw_write_wx(struct netxen_adapter *adapter, u64 off, void *data,
1025 void netxen_crb_writelit_adapter(struct netxen_adapter *adapter,
1026 unsigned long off, int data);
1028 /* Functions from netxen_nic_init.c */
1029 void netxen_free_adapter_offload(struct netxen_adapter *adapter);
1030 int netxen_initialize_adapter_offload(struct netxen_adapter *adapter);
1031 void netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val);
1032 void netxen_load_firmware(struct netxen_adapter *adapter);
1033 int netxen_pinit_from_rom(struct netxen_adapter *adapter, int verbose);
1034 int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp);
1035 int netxen_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
1036 u8 *bytes, size_t size);
1037 int netxen_rom_fast_write_words(struct netxen_adapter *adapter, int addr,
1038 u8 *bytes, size_t size);
1039 int netxen_flash_unlock(struct netxen_adapter *adapter);
1040 int netxen_backup_crbinit(struct netxen_adapter *adapter);
1041 int netxen_flash_erase_secondary(struct netxen_adapter *adapter);
1042 int netxen_flash_erase_primary(struct netxen_adapter *adapter);
1044 int netxen_rom_fast_write(struct netxen_adapter *adapter, int addr, int data);
1045 int netxen_rom_se(struct netxen_adapter *adapter, int addr);
1046 int netxen_do_rom_se(struct netxen_adapter *adapter, int addr);
1048 /* Functions from netxen_nic_isr.c */
1049 void netxen_nic_isr_other(struct netxen_adapter *adapter);
1050 void netxen_indicate_link_status(struct netxen_adapter *adapter, u32 port,
1052 void netxen_handle_port_int(struct netxen_adapter *adapter, u32 port,
1054 void netxen_nic_stop_all_ports(struct netxen_adapter *adapter);
1055 void netxen_initialize_adapter_sw(struct netxen_adapter *adapter);
1056 void netxen_initialize_adapter_hw(struct netxen_adapter *adapter);
1057 void *netxen_alloc(struct pci_dev *pdev, size_t sz, dma_addr_t * ptr,
1058 struct pci_dev **used_dev);
1059 void netxen_initialize_adapter_ops(struct netxen_adapter *adapter);
1060 int netxen_init_firmware(struct netxen_adapter *adapter);
1061 void netxen_free_hw_resources(struct netxen_adapter *adapter);
1062 void netxen_tso_check(struct netxen_adapter *adapter,
1063 struct cmd_desc_type0 *desc, struct sk_buff *skb);
1064 int netxen_nic_hw_resources(struct netxen_adapter *adapter);
1065 void netxen_nic_clear_stats(struct netxen_adapter *adapter);
1066 int netxen_nic_rx_has_work(struct netxen_adapter *adapter);
1067 int netxen_nic_tx_has_work(struct netxen_adapter *adapter);
1068 void netxen_watchdog_task(struct work_struct *work);
1069 void netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ctx,
1071 void netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter, u32 ctx,
1073 int netxen_process_cmd_ring(unsigned long data);
1074 u32 netxen_process_rcv_ring(struct netxen_adapter *adapter, int ctx, int max);
1075 void netxen_nic_set_multi(struct net_device *netdev);
1076 int netxen_nic_change_mtu(struct net_device *netdev, int new_mtu);
1077 int netxen_nic_set_mac(struct net_device *netdev, void *p);
1078 struct net_device_stats *netxen_nic_get_stats(struct net_device *netdev);
1080 static inline void netxen_nic_disable_int(struct netxen_adapter *adapter)
1083 * ISR_INT_MASK: Can be read from window 0 or 1.
1085 writel(0x7ff, PCI_OFFSET_SECOND_RANGE(adapter, ISR_INT_MASK));
1089 static inline void netxen_nic_enable_int(struct netxen_adapter *adapter)
1093 switch (adapter->ahw.board_type) {
1094 case NETXEN_NIC_GBE:
1097 case NETXEN_NIC_XGBE:
1105 writel(mask, PCI_OFFSET_SECOND_RANGE(adapter, ISR_INT_MASK));
1107 if (!(adapter->flags & NETXEN_NIC_MSI_ENABLED)) {
1109 writel(mask, PCI_OFFSET_SECOND_RANGE(adapter,
1110 ISR_INT_TARGET_MASK));
1115 * NetXen Board information
1118 #define NETXEN_MAX_SHORT_NAME 16
1119 struct netxen_brdinfo {
1120 netxen_brdtype_t brdtype; /* type of board */
1121 long ports; /* max no of physical ports */
1122 char short_name[NETXEN_MAX_SHORT_NAME];
1125 static const struct netxen_brdinfo netxen_boards[] = {
1126 {NETXEN_BRDTYPE_P2_SB31_10G_CX4, 1, "XGb CX4"},
1127 {NETXEN_BRDTYPE_P2_SB31_10G_HMEZ, 1, "XGb HMEZ"},
1128 {NETXEN_BRDTYPE_P2_SB31_10G_IMEZ, 2, "XGb IMEZ"},
1129 {NETXEN_BRDTYPE_P2_SB31_10G, 1, "XGb XFP"},
1130 {NETXEN_BRDTYPE_P2_SB35_4G, 4, "Quad Gb"},
1131 {NETXEN_BRDTYPE_P2_SB31_2G, 2, "Dual Gb"},
1134 #define NUM_SUPPORTED_BOARDS (sizeof(netxen_boards)/sizeof(struct netxen_brdinfo))
1136 static inline void get_brd_port_by_type(u32 type, int *ports)
1139 for (i = 0; i < NUM_SUPPORTED_BOARDS; ++i) {
1140 if (netxen_boards[i].brdtype == type) {
1141 *ports = netxen_boards[i].ports;
1150 static inline void get_brd_name_by_type(u32 type, char *name)
1153 for (i = 0; i < NUM_SUPPORTED_BOARDS; ++i) {
1154 if (netxen_boards[i].brdtype == type) {
1155 strcpy(name, netxen_boards[i].short_name);
1165 int netxen_is_flash_supported(struct netxen_adapter *adapter);
1166 int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, u64 mac[]);
1167 extern void netxen_change_ringparam(struct netxen_adapter *adapter);
1168 extern int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr,
1171 extern struct ethtool_ops netxen_nic_ethtool_ops;
1173 #endif /* __NETXEN_NIC_H_ */