2 * Copyright (C) 2003 - 2006 NetXen, Inc.
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
20 * The full GNU General Public License is included in this distribution
21 * in the file called LICENSE.
23 * Contact Information:
26 * 3965 Freedom Circle, Fourth floor,
27 * Santa Clara, CA 95054
30 * Source file for NIC routines to access the Phantom hardware
34 #include "netxen_nic.h"
35 #include "netxen_nic_hw.h"
36 #include "netxen_nic_phan_reg.h"
41 #define MASK(n) ((1ULL<<(n))-1)
42 #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | ((addr >> 25) & 0x3ff))
43 #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | ((addr >> 25) & 0x3ff))
44 #define MS_WIN(addr) (addr & 0x0ffc0000)
46 #define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
48 #define CRB_BLK(off) ((off >> 20) & 0x3f)
49 #define CRB_SUBBLK(off) ((off >> 16) & 0xf)
50 #define CRB_WINDOW_2M (0x130060)
51 #define CRB_HI(off) ((crb_hub_agt[CRB_BLK(off)] << 20) | ((off) & 0xf0000))
52 #define CRB_INDIRECT_2M (0x1e0000UL)
54 #define CRB_WIN_LOCK_TIMEOUT 100000000
55 static crb_128M_2M_block_map_t crb_128M_2M_map[64] = {
56 {{{0, 0, 0, 0} } }, /* 0: PCI */
57 {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */
58 {1, 0x0110000, 0x0120000, 0x130000},
59 {1, 0x0120000, 0x0122000, 0x124000},
60 {1, 0x0130000, 0x0132000, 0x126000},
61 {1, 0x0140000, 0x0142000, 0x128000},
62 {1, 0x0150000, 0x0152000, 0x12a000},
63 {1, 0x0160000, 0x0170000, 0x110000},
64 {1, 0x0170000, 0x0172000, 0x12e000},
65 {0, 0x0000000, 0x0000000, 0x000000},
66 {0, 0x0000000, 0x0000000, 0x000000},
67 {0, 0x0000000, 0x0000000, 0x000000},
68 {0, 0x0000000, 0x0000000, 0x000000},
69 {0, 0x0000000, 0x0000000, 0x000000},
70 {0, 0x0000000, 0x0000000, 0x000000},
71 {1, 0x01e0000, 0x01e0800, 0x122000},
72 {0, 0x0000000, 0x0000000, 0x000000} } },
73 {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */
74 {{{0, 0, 0, 0} } }, /* 3: */
75 {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */
76 {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE */
77 {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU */
78 {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM */
79 {{{1, 0x0800000, 0x0802000, 0x170000}, /* 8: SQM0 */
80 {0, 0x0000000, 0x0000000, 0x000000},
81 {0, 0x0000000, 0x0000000, 0x000000},
82 {0, 0x0000000, 0x0000000, 0x000000},
83 {0, 0x0000000, 0x0000000, 0x000000},
84 {0, 0x0000000, 0x0000000, 0x000000},
85 {0, 0x0000000, 0x0000000, 0x000000},
86 {0, 0x0000000, 0x0000000, 0x000000},
87 {0, 0x0000000, 0x0000000, 0x000000},
88 {0, 0x0000000, 0x0000000, 0x000000},
89 {0, 0x0000000, 0x0000000, 0x000000},
90 {0, 0x0000000, 0x0000000, 0x000000},
91 {0, 0x0000000, 0x0000000, 0x000000},
92 {0, 0x0000000, 0x0000000, 0x000000},
93 {0, 0x0000000, 0x0000000, 0x000000},
94 {1, 0x08f0000, 0x08f2000, 0x172000} } },
95 {{{1, 0x0900000, 0x0902000, 0x174000}, /* 9: SQM1*/
96 {0, 0x0000000, 0x0000000, 0x000000},
97 {0, 0x0000000, 0x0000000, 0x000000},
98 {0, 0x0000000, 0x0000000, 0x000000},
99 {0, 0x0000000, 0x0000000, 0x000000},
100 {0, 0x0000000, 0x0000000, 0x000000},
101 {0, 0x0000000, 0x0000000, 0x000000},
102 {0, 0x0000000, 0x0000000, 0x000000},
103 {0, 0x0000000, 0x0000000, 0x000000},
104 {0, 0x0000000, 0x0000000, 0x000000},
105 {0, 0x0000000, 0x0000000, 0x000000},
106 {0, 0x0000000, 0x0000000, 0x000000},
107 {0, 0x0000000, 0x0000000, 0x000000},
108 {0, 0x0000000, 0x0000000, 0x000000},
109 {0, 0x0000000, 0x0000000, 0x000000},
110 {1, 0x09f0000, 0x09f2000, 0x176000} } },
111 {{{0, 0x0a00000, 0x0a02000, 0x178000}, /* 10: SQM2*/
112 {0, 0x0000000, 0x0000000, 0x000000},
113 {0, 0x0000000, 0x0000000, 0x000000},
114 {0, 0x0000000, 0x0000000, 0x000000},
115 {0, 0x0000000, 0x0000000, 0x000000},
116 {0, 0x0000000, 0x0000000, 0x000000},
117 {0, 0x0000000, 0x0000000, 0x000000},
118 {0, 0x0000000, 0x0000000, 0x000000},
119 {0, 0x0000000, 0x0000000, 0x000000},
120 {0, 0x0000000, 0x0000000, 0x000000},
121 {0, 0x0000000, 0x0000000, 0x000000},
122 {0, 0x0000000, 0x0000000, 0x000000},
123 {0, 0x0000000, 0x0000000, 0x000000},
124 {0, 0x0000000, 0x0000000, 0x000000},
125 {0, 0x0000000, 0x0000000, 0x000000},
126 {1, 0x0af0000, 0x0af2000, 0x17a000} } },
127 {{{0, 0x0b00000, 0x0b02000, 0x17c000}, /* 11: SQM3*/
128 {0, 0x0000000, 0x0000000, 0x000000},
129 {0, 0x0000000, 0x0000000, 0x000000},
130 {0, 0x0000000, 0x0000000, 0x000000},
131 {0, 0x0000000, 0x0000000, 0x000000},
132 {0, 0x0000000, 0x0000000, 0x000000},
133 {0, 0x0000000, 0x0000000, 0x000000},
134 {0, 0x0000000, 0x0000000, 0x000000},
135 {0, 0x0000000, 0x0000000, 0x000000},
136 {0, 0x0000000, 0x0000000, 0x000000},
137 {0, 0x0000000, 0x0000000, 0x000000},
138 {0, 0x0000000, 0x0000000, 0x000000},
139 {0, 0x0000000, 0x0000000, 0x000000},
140 {0, 0x0000000, 0x0000000, 0x000000},
141 {0, 0x0000000, 0x0000000, 0x000000},
142 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
143 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */
144 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */
145 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */
146 {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */
147 {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */
148 {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */
149 {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */
150 {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */
151 {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */
152 {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */
153 {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */
154 {{{0, 0, 0, 0} } }, /* 23: */
155 {{{0, 0, 0, 0} } }, /* 24: */
156 {{{0, 0, 0, 0} } }, /* 25: */
157 {{{0, 0, 0, 0} } }, /* 26: */
158 {{{0, 0, 0, 0} } }, /* 27: */
159 {{{0, 0, 0, 0} } }, /* 28: */
160 {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */
161 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */
162 {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */
163 {{{0} } }, /* 32: PCI */
164 {{{1, 0x2100000, 0x2102000, 0x120000}, /* 33: PCIE */
165 {1, 0x2110000, 0x2120000, 0x130000},
166 {1, 0x2120000, 0x2122000, 0x124000},
167 {1, 0x2130000, 0x2132000, 0x126000},
168 {1, 0x2140000, 0x2142000, 0x128000},
169 {1, 0x2150000, 0x2152000, 0x12a000},
170 {1, 0x2160000, 0x2170000, 0x110000},
171 {1, 0x2170000, 0x2172000, 0x12e000},
172 {0, 0x0000000, 0x0000000, 0x000000},
173 {0, 0x0000000, 0x0000000, 0x000000},
174 {0, 0x0000000, 0x0000000, 0x000000},
175 {0, 0x0000000, 0x0000000, 0x000000},
176 {0, 0x0000000, 0x0000000, 0x000000},
177 {0, 0x0000000, 0x0000000, 0x000000},
178 {0, 0x0000000, 0x0000000, 0x000000},
179 {0, 0x0000000, 0x0000000, 0x000000} } },
180 {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */
186 {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */
187 {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */
188 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */
189 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */
190 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */
191 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */
192 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */
193 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */
194 {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */
195 {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */
196 {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */
197 {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */
199 {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */
200 {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */
201 {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */
202 {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */
203 {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */
204 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */
205 {{{0} } }, /* 59: I2C0 */
206 {{{0} } }, /* 60: I2C1 */
207 {{{1, 0x3d00000, 0x3d04000, 0x1d8000} } },/* 61: LPC */
208 {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */
209 {{{1, 0x3f00000, 0x3f01000, 0x168000} } } /* 63: P2NR0 */
213 * top 12 bits of crb internal address (hub, agent)
215 static unsigned crb_hub_agt[64] =
218 NETXEN_HW_CRB_HUB_AGT_ADR_PS,
219 NETXEN_HW_CRB_HUB_AGT_ADR_MN,
220 NETXEN_HW_CRB_HUB_AGT_ADR_MS,
222 NETXEN_HW_CRB_HUB_AGT_ADR_SRE,
223 NETXEN_HW_CRB_HUB_AGT_ADR_NIU,
224 NETXEN_HW_CRB_HUB_AGT_ADR_QMN,
225 NETXEN_HW_CRB_HUB_AGT_ADR_SQN0,
226 NETXEN_HW_CRB_HUB_AGT_ADR_SQN1,
227 NETXEN_HW_CRB_HUB_AGT_ADR_SQN2,
228 NETXEN_HW_CRB_HUB_AGT_ADR_SQN3,
229 NETXEN_HW_CRB_HUB_AGT_ADR_I2Q,
230 NETXEN_HW_CRB_HUB_AGT_ADR_TIMR,
231 NETXEN_HW_CRB_HUB_AGT_ADR_ROMUSB,
232 NETXEN_HW_CRB_HUB_AGT_ADR_PGN4,
233 NETXEN_HW_CRB_HUB_AGT_ADR_XDMA,
234 NETXEN_HW_CRB_HUB_AGT_ADR_PGN0,
235 NETXEN_HW_CRB_HUB_AGT_ADR_PGN1,
236 NETXEN_HW_CRB_HUB_AGT_ADR_PGN2,
237 NETXEN_HW_CRB_HUB_AGT_ADR_PGN3,
238 NETXEN_HW_CRB_HUB_AGT_ADR_PGND,
239 NETXEN_HW_CRB_HUB_AGT_ADR_PGNI,
240 NETXEN_HW_CRB_HUB_AGT_ADR_PGS0,
241 NETXEN_HW_CRB_HUB_AGT_ADR_PGS1,
242 NETXEN_HW_CRB_HUB_AGT_ADR_PGS2,
243 NETXEN_HW_CRB_HUB_AGT_ADR_PGS3,
245 NETXEN_HW_CRB_HUB_AGT_ADR_PGSI,
246 NETXEN_HW_CRB_HUB_AGT_ADR_SN,
248 NETXEN_HW_CRB_HUB_AGT_ADR_EG,
250 NETXEN_HW_CRB_HUB_AGT_ADR_PS,
251 NETXEN_HW_CRB_HUB_AGT_ADR_CAM,
257 NETXEN_HW_CRB_HUB_AGT_ADR_TIMR,
259 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX1,
260 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX2,
261 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX3,
262 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX4,
263 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX5,
264 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX6,
265 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX7,
266 NETXEN_HW_CRB_HUB_AGT_ADR_XDMA,
267 NETXEN_HW_CRB_HUB_AGT_ADR_I2Q,
268 NETXEN_HW_CRB_HUB_AGT_ADR_ROMUSB,
270 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX0,
271 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX8,
272 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX9,
273 NETXEN_HW_CRB_HUB_AGT_ADR_OCM0,
275 NETXEN_HW_CRB_HUB_AGT_ADR_SMB,
276 NETXEN_HW_CRB_HUB_AGT_ADR_I2C0,
277 NETXEN_HW_CRB_HUB_AGT_ADR_I2C1,
279 NETXEN_HW_CRB_HUB_AGT_ADR_PGNC,
283 /* PCI Windowing for DDR regions. */
285 #define ADDR_IN_RANGE(addr, low, high) \
286 (((addr) <= (high)) && ((addr) >= (low)))
288 #define NETXEN_WINDOW_ONE 0x2000000 /*CRB Window: bit 25 of CRB address */
290 #define NETXEN_NIC_ZERO_PAUSE_ADDR 0ULL
291 #define NETXEN_NIC_UNIT_PAUSE_ADDR 0x200ULL
292 #define NETXEN_NIC_EPG_PAUSE_ADDR1 0x2200010000c28001ULL
293 #define NETXEN_NIC_EPG_PAUSE_ADDR2 0x0100088866554433ULL
295 #define NETXEN_NIC_WINDOW_MARGIN 0x100000
297 int netxen_nic_set_mac(struct net_device *netdev, void *p)
299 struct netxen_adapter *adapter = netdev_priv(netdev);
300 struct sockaddr *addr = p;
302 if (netif_running(netdev))
305 if (!is_valid_ether_addr(addr->sa_data))
306 return -EADDRNOTAVAIL;
308 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
310 /* For P3, MAC addr is not set in NIU */
311 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
312 if (adapter->macaddr_set)
313 adapter->macaddr_set(adapter, addr->sa_data);
318 #define NETXEN_UNICAST_ADDR(port, index) \
319 (NETXEN_UNICAST_ADDR_BASE+(port*32)+(index*8))
320 #define NETXEN_MCAST_ADDR(port, index) \
321 (NETXEN_MULTICAST_ADDR_BASE+(port*0x80)+(index*8))
322 #define MAC_HI(addr) \
323 ((addr[2] << 16) | (addr[1] << 8) | (addr[0]))
324 #define MAC_LO(addr) \
325 ((addr[5] << 16) | (addr[4] << 8) | (addr[3]))
328 netxen_nic_enable_mcast_filter(struct netxen_adapter *adapter)
331 u16 port = adapter->physical_port;
332 u8 *addr = adapter->netdev->dev_addr;
334 if (adapter->mc_enabled)
337 adapter->hw_read_wx(adapter, NETXEN_MAC_ADDR_CNTL_REG, &val, 4);
338 val |= (1UL << (28+port));
339 adapter->hw_write_wx(adapter, NETXEN_MAC_ADDR_CNTL_REG, &val, 4);
341 /* add broadcast addr to filter */
343 netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 0), val);
344 netxen_crb_writelit_adapter(adapter,
345 NETXEN_UNICAST_ADDR(port, 0)+4, val);
347 /* add station addr to filter */
349 netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 1), val);
351 netxen_crb_writelit_adapter(adapter,
352 NETXEN_UNICAST_ADDR(port, 1)+4, val);
354 adapter->mc_enabled = 1;
359 netxen_nic_disable_mcast_filter(struct netxen_adapter *adapter)
362 u16 port = adapter->physical_port;
363 u8 *addr = adapter->netdev->dev_addr;
365 if (!adapter->mc_enabled)
368 adapter->hw_read_wx(adapter, NETXEN_MAC_ADDR_CNTL_REG, &val, 4);
369 val &= ~(1UL << (28+port));
370 adapter->hw_write_wx(adapter, NETXEN_MAC_ADDR_CNTL_REG, &val, 4);
373 netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 0), val);
375 netxen_crb_writelit_adapter(adapter,
376 NETXEN_UNICAST_ADDR(port, 0)+4, val);
378 netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 1), 0);
379 netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 1)+4, 0);
381 adapter->mc_enabled = 0;
386 netxen_nic_set_mcast_addr(struct netxen_adapter *adapter,
390 u16 port = adapter->physical_port;
395 netxen_crb_writelit_adapter(adapter,
396 NETXEN_MCAST_ADDR(port, index), hi);
397 netxen_crb_writelit_adapter(adapter,
398 NETXEN_MCAST_ADDR(port, index)+4, lo);
403 void netxen_p2_nic_set_multi(struct net_device *netdev)
405 struct netxen_adapter *adapter = netdev_priv(netdev);
406 struct dev_mc_list *mc_ptr;
410 memset(null_addr, 0, 6);
412 if (netdev->flags & IFF_PROMISC) {
414 adapter->set_promisc(adapter,
415 NETXEN_NIU_PROMISC_MODE);
417 /* Full promiscuous mode */
418 netxen_nic_disable_mcast_filter(adapter);
423 if (netdev->mc_count == 0) {
424 adapter->set_promisc(adapter,
425 NETXEN_NIU_NON_PROMISC_MODE);
426 netxen_nic_disable_mcast_filter(adapter);
430 adapter->set_promisc(adapter, NETXEN_NIU_ALLMULTI_MODE);
431 if (netdev->flags & IFF_ALLMULTI ||
432 netdev->mc_count > adapter->max_mc_count) {
433 netxen_nic_disable_mcast_filter(adapter);
437 netxen_nic_enable_mcast_filter(adapter);
439 for (mc_ptr = netdev->mc_list; mc_ptr; mc_ptr = mc_ptr->next, index++)
440 netxen_nic_set_mcast_addr(adapter, index, mc_ptr->dmi_addr);
442 if (index != netdev->mc_count)
443 printk(KERN_WARNING "%s: %s multicast address count mismatch\n",
444 netxen_nic_driver_name, netdev->name);
446 /* Clear out remaining addresses */
447 for (; index < adapter->max_mc_count; index++)
448 netxen_nic_set_mcast_addr(adapter, index, null_addr);
451 static int nx_p3_nic_add_mac(struct netxen_adapter *adapter,
452 u8 *addr, nx_mac_list_t **add_list, nx_mac_list_t **del_list)
454 nx_mac_list_t *cur, *prev;
456 /* if in del_list, move it to adapter->mac_list */
457 for (cur = *del_list, prev = NULL; cur;) {
458 if (memcmp(addr, cur->mac_addr, ETH_ALEN) == 0) {
460 *del_list = cur->next;
462 prev->next = cur->next;
463 cur->next = adapter->mac_list;
464 adapter->mac_list = cur;
471 /* make sure to add each mac address only once */
472 for (cur = adapter->mac_list; cur; cur = cur->next) {
473 if (memcmp(addr, cur->mac_addr, ETH_ALEN) == 0)
476 /* not in del_list, create new entry and add to add_list */
477 cur = kmalloc(sizeof(*cur), in_atomic()? GFP_ATOMIC : GFP_KERNEL);
479 printk(KERN_ERR "%s: cannot allocate memory. MAC filtering may"
480 "not work properly from now.\n", __func__);
484 memcpy(cur->mac_addr, addr, ETH_ALEN);
485 cur->next = *add_list;
491 netxen_send_cmd_descs(struct netxen_adapter *adapter,
492 struct cmd_desc_type0 *cmd_desc_arr, int nr_elements)
494 uint32_t i, producer;
495 struct netxen_cmd_buffer *pbuf;
496 struct cmd_desc_type0 *cmd_desc;
498 if (nr_elements > MAX_PENDING_DESC_BLOCK_SIZE || nr_elements == 0) {
499 printk(KERN_WARNING "%s: Too many command descriptors in a "
500 "request\n", __func__);
506 producer = adapter->cmd_producer;
508 cmd_desc = &cmd_desc_arr[i];
510 pbuf = &adapter->cmd_buf_arr[producer];
512 pbuf->frag_count = 0;
514 /* adapter->ahw.cmd_desc_head[producer] = *cmd_desc; */
515 memcpy(&adapter->ahw.cmd_desc_head[producer],
516 &cmd_desc_arr[i], sizeof(struct cmd_desc_type0));
518 producer = get_next_index(producer,
519 adapter->max_tx_desc_count);
522 } while (i != nr_elements);
524 adapter->cmd_producer = producer;
526 /* write producer index to start the xmit */
528 netxen_nic_update_cmd_producer(adapter, adapter->cmd_producer);
533 static int nx_p3_sre_macaddr_change(struct net_device *dev,
534 u8 *addr, unsigned op)
536 struct netxen_adapter *adapter = netdev_priv(dev);
538 nx_mac_req_t *mac_req;
542 memset(&req, 0, sizeof(nx_nic_req_t));
543 req.qhdr = cpu_to_le64(NX_NIC_REQUEST << 23);
545 word = NX_MAC_EVENT | ((u64)adapter->portnum << 16);
546 req.req_hdr = cpu_to_le64(word);
548 mac_req = (nx_mac_req_t *)&req.words[0];
550 memcpy(mac_req->mac_addr, addr, 6);
552 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
554 printk(KERN_ERR "ERROR. Could not send mac update\n");
561 void netxen_p3_nic_set_multi(struct net_device *netdev)
563 struct netxen_adapter *adapter = netdev_priv(netdev);
564 nx_mac_list_t *cur, *next, *del_list, *add_list = NULL;
565 struct dev_mc_list *mc_ptr;
566 u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
567 u32 mode = VPORT_MISS_MODE_DROP;
569 del_list = adapter->mac_list;
570 adapter->mac_list = NULL;
572 nx_p3_nic_add_mac(adapter, netdev->dev_addr, &add_list, &del_list);
573 nx_p3_nic_add_mac(adapter, bcast_addr, &add_list, &del_list);
575 if (netdev->flags & IFF_PROMISC) {
576 mode = VPORT_MISS_MODE_ACCEPT_ALL;
580 if ((netdev->flags & IFF_ALLMULTI) ||
581 (netdev->mc_count > adapter->max_mc_count)) {
582 mode = VPORT_MISS_MODE_ACCEPT_MULTI;
586 if (netdev->mc_count > 0) {
587 for (mc_ptr = netdev->mc_list; mc_ptr;
588 mc_ptr = mc_ptr->next) {
589 nx_p3_nic_add_mac(adapter, mc_ptr->dmi_addr,
590 &add_list, &del_list);
595 adapter->set_promisc(adapter, mode);
596 for (cur = del_list; cur;) {
597 nx_p3_sre_macaddr_change(netdev, cur->mac_addr, NETXEN_MAC_DEL);
602 for (cur = add_list; cur;) {
603 nx_p3_sre_macaddr_change(netdev, cur->mac_addr, NETXEN_MAC_ADD);
605 cur->next = adapter->mac_list;
606 adapter->mac_list = cur;
611 int netxen_p3_nic_set_promisc(struct netxen_adapter *adapter, u32 mode)
616 memset(&req, 0, sizeof(nx_nic_req_t));
618 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
620 word = NX_NIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE |
621 ((u64)adapter->portnum << 16);
622 req.req_hdr = cpu_to_le64(word);
624 req.words[0] = cpu_to_le64(mode);
626 return netxen_send_cmd_descs(adapter,
627 (struct cmd_desc_type0 *)&req, 1);
630 void netxen_p3_free_mac_list(struct netxen_adapter *adapter)
632 nx_mac_list_t *cur, *next;
634 cur = adapter->mac_list;
643 #define NETXEN_CONFIG_INTR_COALESCE 3
646 * Send the interrupt coalescing parameter set by ethtool to the card.
648 int netxen_config_intr_coalesce(struct netxen_adapter *adapter)
654 memset(&req, 0, sizeof(nx_nic_req_t));
656 req.qhdr = cpu_to_le64(NX_NIC_REQUEST << 23);
658 word = NETXEN_CONFIG_INTR_COALESCE | ((u64)adapter->portnum << 16);
659 req.req_hdr = cpu_to_le64(word);
661 memcpy(&req.words[0], &adapter->coal, sizeof(adapter->coal));
663 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
665 printk(KERN_ERR "ERROR. Could not send "
666 "interrupt coalescing parameters\n");
673 * netxen_nic_change_mtu - Change the Maximum Transfer Unit
674 * @returns 0 on success, negative on failure
677 #define MTU_FUDGE_FACTOR 100
679 int netxen_nic_change_mtu(struct net_device *netdev, int mtu)
681 struct netxen_adapter *adapter = netdev_priv(netdev);
685 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
686 max_mtu = P3_MAX_MTU;
688 max_mtu = P2_MAX_MTU;
691 printk(KERN_ERR "%s: mtu > %d bytes unsupported\n",
692 netdev->name, max_mtu);
696 if (adapter->set_mtu)
697 rc = adapter->set_mtu(adapter, mtu);
705 int netxen_is_flash_supported(struct netxen_adapter *adapter)
707 const int locs[] = { 0, 0x4, 0x100, 0x4000, 0x4128 };
708 int addr, val01, val02, i, j;
710 /* if the flash size less than 4Mb, make huge war cry and die */
711 for (j = 1; j < 4; j++) {
712 addr = j * NETXEN_NIC_WINDOW_MARGIN;
713 for (i = 0; i < ARRAY_SIZE(locs); i++) {
714 if (netxen_rom_fast_read(adapter, locs[i], &val01) == 0
715 && netxen_rom_fast_read(adapter, (addr + locs[i]),
727 static int netxen_get_flash_block(struct netxen_adapter *adapter, int base,
728 int size, __le32 * buf)
736 for (i = 0; i < size / sizeof(u32); i++) {
737 if (netxen_rom_fast_read(adapter, addr, &v) == -1)
739 *ptr32 = cpu_to_le32(v);
743 if ((char *)buf + size > (char *)ptr32) {
745 if (netxen_rom_fast_read(adapter, addr, &v) == -1)
747 local = cpu_to_le32(v);
748 memcpy(ptr32, &local, (char *)buf + size - (char *)ptr32);
754 int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, __le64 *mac)
756 __le32 *pmac = (__le32 *) mac;
759 offset = NETXEN_USER_START +
760 offsetof(struct netxen_new_user_info, mac_addr) +
761 adapter->portnum * sizeof(u64);
763 if (netxen_get_flash_block(adapter, offset, sizeof(u64), pmac) == -1)
766 if (*mac == cpu_to_le64(~0ULL)) {
768 offset = NETXEN_USER_START_OLD +
769 offsetof(struct netxen_user_old_info, mac_addr) +
770 adapter->portnum * sizeof(u64);
772 if (netxen_get_flash_block(adapter,
773 offset, sizeof(u64), pmac) == -1)
776 if (*mac == cpu_to_le64(~0ULL))
782 int netxen_p3_get_mac_addr(struct netxen_adapter *adapter, __le64 *mac)
784 uint32_t crbaddr, mac_hi, mac_lo;
785 int pci_func = adapter->ahw.pci_func;
787 crbaddr = CRB_MAC_BLOCK_START +
788 (4 * ((pci_func/2) * 3)) + (4 * (pci_func & 1));
790 adapter->hw_read_wx(adapter, crbaddr, &mac_lo, 4);
791 adapter->hw_read_wx(adapter, crbaddr+4, &mac_hi, 4);
794 *mac = le64_to_cpu((mac_lo >> 16) | ((u64)mac_hi << 16));
796 *mac = le64_to_cpu((u64)mac_lo | ((u64)mac_hi << 32));
801 #define CRB_WIN_LOCK_TIMEOUT 100000000
803 static int crb_win_lock(struct netxen_adapter *adapter)
805 int done = 0, timeout = 0;
808 /* acquire semaphore3 from PCI HW block */
809 adapter->hw_read_wx(adapter,
810 NETXEN_PCIE_REG(PCIE_SEM7_LOCK), &done, 4);
813 if (timeout >= CRB_WIN_LOCK_TIMEOUT)
818 netxen_crb_writelit_adapter(adapter,
819 NETXEN_CRB_WIN_LOCK_ID, adapter->portnum);
823 static void crb_win_unlock(struct netxen_adapter *adapter)
827 adapter->hw_read_wx(adapter,
828 NETXEN_PCIE_REG(PCIE_SEM7_UNLOCK), &val, 4);
832 * Changes the CRB window to the specified window.
835 netxen_nic_pci_change_crbwindow_128M(struct netxen_adapter *adapter, u32 wndw)
837 void __iomem *offset;
840 uint8_t func = adapter->ahw.pci_func;
842 if (adapter->curr_window == wndw)
845 * Move the CRB window.
846 * We need to write to the "direct access" region of PCI
847 * to avoid a race condition where the window register has
848 * not been successfully written across CRB before the target
849 * register address is received by PCI. The direct region bypasses
852 offset = PCI_OFFSET_SECOND_RANGE(adapter,
853 NETXEN_PCIX_PH_REG(PCIE_CRB_WINDOW_REG(func)));
856 wndw = NETXEN_WINDOW_ONE;
858 writel(wndw, offset);
860 /* MUST make sure window is set before we forge on... */
861 while ((tmp = readl(offset)) != wndw) {
862 printk(KERN_WARNING "%s: %s WARNING: CRB window value not "
863 "registered properly: 0x%08x.\n",
864 netxen_nic_driver_name, __func__, tmp);
871 if (wndw == NETXEN_WINDOW_ONE)
872 adapter->curr_window = 1;
874 adapter->curr_window = 0;
878 * Return -1 if off is not valid,
879 * 1 if window access is needed. 'off' is set to offset from
880 * CRB space in 128M pci map
881 * 0 if no window access is needed. 'off' is set to 2M addr
882 * In: 'off' is offset from base in 128M pci map
885 netxen_nic_pci_get_crb_addr_2M(struct netxen_adapter *adapter,
888 unsigned long end = *off + len;
889 crb_128M_2M_sub_block_map_t *m;
892 if (*off >= NETXEN_CRB_MAX)
895 if (*off >= NETXEN_PCI_CAMQM && (end <= NETXEN_PCI_CAMQM_2M_END)) {
896 *off = (*off - NETXEN_PCI_CAMQM) + NETXEN_PCI_CAMQM_2M_BASE +
897 (ulong)adapter->ahw.pci_base0;
901 if (*off < NETXEN_PCI_CRBSPACE)
904 *off -= NETXEN_PCI_CRBSPACE;
910 m = &crb_128M_2M_map[CRB_BLK(*off)].sub_block[CRB_SUBBLK(*off)];
912 if (m->valid && (m->start_128M <= *off) && (m->end_128M >= end)) {
913 *off = *off + m->start_2M - m->start_128M +
914 (ulong)adapter->ahw.pci_base0;
919 * Not in direct map, use crb window
925 * In: 'off' is offset from CRB space in 128M pci map
926 * Out: 'off' is 2M pci map addr
927 * side effect: lock crb window
930 netxen_nic_pci_set_crbwindow_2M(struct netxen_adapter *adapter, ulong *off)
934 adapter->crb_win = CRB_HI(*off);
935 writel(adapter->crb_win, (void *)(CRB_WINDOW_2M +
936 adapter->ahw.pci_base0));
938 * Read back value to make sure write has gone through before trying
941 win_read = readl((void *)(CRB_WINDOW_2M + adapter->ahw.pci_base0));
942 if (win_read != adapter->crb_win) {
943 printk(KERN_ERR "%s: Written crbwin (0x%x) != "
944 "Read crbwin (0x%x), off=0x%lx\n",
945 __func__, adapter->crb_win, win_read, *off);
947 *off = (*off & MASK(16)) + CRB_INDIRECT_2M +
948 (ulong)adapter->ahw.pci_base0;
951 int netxen_load_firmware(struct netxen_adapter *adapter)
955 u32 flashaddr = NETXEN_BOOTLD_START;
957 size = (NETXEN_IMAGE_START - NETXEN_BOOTLD_START)/4;
959 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
960 adapter->pci_write_normalize(adapter,
961 NETXEN_ROMUSB_GLB_CAS_RST, 1);
963 for (i = 0; i < size; i++) {
964 if (netxen_rom_fast_read(adapter, flashaddr, (int *)&data) != 0)
967 adapter->pci_mem_write(adapter, flashaddr, &data, 4);
972 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
973 adapter->pci_write_normalize(adapter,
974 NETXEN_ROMUSB_GLB_SW_RESET, 0x80001d);
976 adapter->pci_write_normalize(adapter,
977 NETXEN_ROMUSB_GLB_CHIP_CLK_CTRL, 0x3fff);
978 adapter->pci_write_normalize(adapter,
979 NETXEN_ROMUSB_GLB_CAS_RST, 0);
986 netxen_nic_hw_write_wx_128M(struct netxen_adapter *adapter,
987 ulong off, void *data, int len)
991 if (ADDR_IN_WINDOW1(off)) {
992 addr = NETXEN_CRB_NORMALIZE(adapter, off);
993 } else { /* Window 0 */
994 addr = pci_base_offset(adapter, off);
995 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
998 DPRINTK(INFO, "writing to base %lx offset %llx addr %p"
999 " data %llx len %d\n",
1000 pci_base(adapter, off), off, addr,
1001 *(unsigned long long *)data, len);
1003 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1009 writeb(*(u8 *) data, addr);
1012 writew(*(u16 *) data, addr);
1015 writel(*(u32 *) data, addr);
1018 writeq(*(u64 *) data, addr);
1022 "writing data %lx to offset %llx, num words=%d\n",
1023 *(unsigned long *)data, off, (len >> 3));
1025 netxen_nic_hw_block_write64((u64 __iomem *) data, addr,
1029 if (!ADDR_IN_WINDOW1(off))
1030 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1036 netxen_nic_hw_read_wx_128M(struct netxen_adapter *adapter,
1037 ulong off, void *data, int len)
1041 if (ADDR_IN_WINDOW1(off)) { /* Window 1 */
1042 addr = NETXEN_CRB_NORMALIZE(adapter, off);
1043 } else { /* Window 0 */
1044 addr = pci_base_offset(adapter, off);
1045 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1048 DPRINTK(INFO, "reading from base %lx offset %llx addr %p\n",
1049 pci_base(adapter, off), off, addr);
1051 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1056 *(u8 *) data = readb(addr);
1059 *(u16 *) data = readw(addr);
1062 *(u32 *) data = readl(addr);
1065 *(u64 *) data = readq(addr);
1068 netxen_nic_hw_block_read64((u64 __iomem *) data, addr,
1072 DPRINTK(INFO, "read %lx\n", *(unsigned long *)data);
1074 if (!ADDR_IN_WINDOW1(off))
1075 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1081 netxen_nic_hw_write_wx_2M(struct netxen_adapter *adapter,
1082 ulong off, void *data, int len)
1084 unsigned long flags = 0;
1087 rv = netxen_nic_pci_get_crb_addr_2M(adapter, &off, len);
1090 printk(KERN_ERR "%s: invalid offset: 0x%016lx\n",
1097 write_lock_irqsave(&adapter->adapter_lock, flags);
1098 crb_win_lock(adapter);
1099 netxen_nic_pci_set_crbwindow_2M(adapter, &off);
1102 DPRINTK(1, INFO, "write data %lx to offset %llx, len=%d\n",
1103 *(unsigned long *)data, off, len);
1107 writeb(*(uint8_t *)data, (void *)off);
1110 writew(*(uint16_t *)data, (void *)off);
1113 writel(*(uint32_t *)data, (void *)off);
1116 writeq(*(uint64_t *)data, (void *)off);
1120 "writing data %lx to offset %llx, num words=%d\n",
1121 *(unsigned long *)data, off, (len>>3));
1125 crb_win_unlock(adapter);
1126 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1133 netxen_nic_hw_read_wx_2M(struct netxen_adapter *adapter,
1134 ulong off, void *data, int len)
1136 unsigned long flags = 0;
1139 rv = netxen_nic_pci_get_crb_addr_2M(adapter, &off, len);
1142 printk(KERN_ERR "%s: invalid offset: 0x%016lx\n",
1149 write_lock_irqsave(&adapter->adapter_lock, flags);
1150 crb_win_lock(adapter);
1151 netxen_nic_pci_set_crbwindow_2M(adapter, &off);
1154 DPRINTK(1, INFO, "read from offset %lx, len=%d\n", off, len);
1158 *(uint8_t *)data = readb((void *)off);
1161 *(uint16_t *)data = readw((void *)off);
1164 *(uint32_t *)data = readl((void *)off);
1167 *(uint64_t *)data = readq((void *)off);
1173 DPRINTK(1, INFO, "read %lx\n", *(unsigned long *)data);
1176 crb_win_unlock(adapter);
1177 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1183 void netxen_nic_reg_write(struct netxen_adapter *adapter, u64 off, u32 val)
1185 adapter->hw_write_wx(adapter, off, &val, 4);
1188 int netxen_nic_reg_read(struct netxen_adapter *adapter, u64 off)
1191 adapter->hw_read_wx(adapter, off, &val, 4);
1195 /* Change the window to 0, write and change back to window 1. */
1196 void netxen_nic_write_w0(struct netxen_adapter *adapter, u32 index, u32 value)
1198 adapter->hw_write_wx(adapter, index, &value, 4);
1201 /* Change the window to 0, read and change back to window 1. */
1202 void netxen_nic_read_w0(struct netxen_adapter *adapter, u32 index, u32 *value)
1204 adapter->hw_read_wx(adapter, index, value, 4);
1207 void netxen_nic_write_w1(struct netxen_adapter *adapter, u32 index, u32 value)
1209 adapter->hw_write_wx(adapter, index, &value, 4);
1212 void netxen_nic_read_w1(struct netxen_adapter *adapter, u32 index, u32 *value)
1214 adapter->hw_read_wx(adapter, index, value, 4);
1218 * check memory access boundary.
1219 * used by test agent. support ddr access only for now
1221 static unsigned long
1222 netxen_nic_pci_mem_bound_check(struct netxen_adapter *adapter,
1223 unsigned long long addr, int size)
1225 if (!ADDR_IN_RANGE(addr,
1226 NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX) ||
1227 !ADDR_IN_RANGE(addr+size-1,
1228 NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX) ||
1229 ((size != 1) && (size != 2) && (size != 4) && (size != 8))) {
1236 static int netxen_pci_set_window_warning_count;
1239 netxen_nic_pci_set_window_128M(struct netxen_adapter *adapter,
1240 unsigned long long addr)
1242 void __iomem *offset;
1244 unsigned long long qdr_max;
1245 uint8_t func = adapter->ahw.pci_func;
1247 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
1248 qdr_max = NETXEN_ADDR_QDR_NET_MAX_P2;
1250 qdr_max = NETXEN_ADDR_QDR_NET_MAX_P3;
1253 if (ADDR_IN_RANGE(addr, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1254 /* DDR network side */
1255 addr -= NETXEN_ADDR_DDR_NET;
1256 window = (addr >> 25) & 0x3ff;
1257 if (adapter->ahw.ddr_mn_window != window) {
1258 adapter->ahw.ddr_mn_window = window;
1259 offset = PCI_OFFSET_SECOND_RANGE(adapter,
1260 NETXEN_PCIX_PH_REG(PCIE_MN_WINDOW_REG(func)));
1261 writel(window, offset);
1262 /* MUST make sure window is set before we forge on... */
1265 addr -= (window * NETXEN_WINDOW_ONE);
1266 addr += NETXEN_PCI_DDR_NET;
1267 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
1268 addr -= NETXEN_ADDR_OCM0;
1269 addr += NETXEN_PCI_OCM0;
1270 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) {
1271 addr -= NETXEN_ADDR_OCM1;
1272 addr += NETXEN_PCI_OCM1;
1273 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_QDR_NET, qdr_max)) {
1274 /* QDR network side */
1275 addr -= NETXEN_ADDR_QDR_NET;
1276 window = (addr >> 22) & 0x3f;
1277 if (adapter->ahw.qdr_sn_window != window) {
1278 adapter->ahw.qdr_sn_window = window;
1279 offset = PCI_OFFSET_SECOND_RANGE(adapter,
1280 NETXEN_PCIX_PH_REG(PCIE_SN_WINDOW_REG(func)));
1281 writel((window << 22), offset);
1282 /* MUST make sure window is set before we forge on... */
1285 addr -= (window * 0x400000);
1286 addr += NETXEN_PCI_QDR_NET;
1289 * peg gdb frequently accesses memory that doesn't exist,
1290 * this limits the chit chat so debugging isn't slowed down.
1292 if ((netxen_pci_set_window_warning_count++ < 8)
1293 || (netxen_pci_set_window_warning_count % 64 == 0))
1294 printk("%s: Warning:netxen_nic_pci_set_window()"
1295 " Unknown address range!\n",
1296 netxen_nic_driver_name);
1303 * Note : only 32-bit writes!
1305 int netxen_nic_pci_write_immediate_128M(struct netxen_adapter *adapter,
1308 writel(data, (void __iomem *)(PCI_OFFSET_SECOND_RANGE(adapter, off)));
1312 u32 netxen_nic_pci_read_immediate_128M(struct netxen_adapter *adapter, u64 off)
1314 return readl((void __iomem *)(pci_base_offset(adapter, off)));
1317 void netxen_nic_pci_write_normalize_128M(struct netxen_adapter *adapter,
1320 writel(data, NETXEN_CRB_NORMALIZE(adapter, off));
1323 u32 netxen_nic_pci_read_normalize_128M(struct netxen_adapter *adapter, u64 off)
1325 return readl(NETXEN_CRB_NORMALIZE(adapter, off));
1329 netxen_nic_pci_set_window_2M(struct netxen_adapter *adapter,
1330 unsigned long long addr)
1335 if (ADDR_IN_RANGE(addr, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1336 /* DDR network side */
1337 window = MN_WIN(addr);
1338 adapter->ahw.ddr_mn_window = window;
1339 adapter->hw_write_wx(adapter,
1340 adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE,
1342 adapter->hw_read_wx(adapter,
1343 adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE,
1345 if ((win_read << 17) != window) {
1346 printk(KERN_INFO "Written MNwin (0x%x) != "
1347 "Read MNwin (0x%x)\n", window, win_read);
1349 addr = GET_MEM_OFFS_2M(addr) + NETXEN_PCI_DDR_NET;
1350 } else if (ADDR_IN_RANGE(addr,
1351 NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
1352 if ((addr & 0x00ff800) == 0xff800) {
1353 printk("%s: QM access not handled.\n", __func__);
1357 window = OCM_WIN(addr);
1358 adapter->ahw.ddr_mn_window = window;
1359 adapter->hw_write_wx(adapter,
1360 adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE,
1362 adapter->hw_read_wx(adapter,
1363 adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE,
1365 if ((win_read >> 7) != window) {
1366 printk(KERN_INFO "%s: Written OCMwin (0x%x) != "
1367 "Read OCMwin (0x%x)\n",
1368 __func__, window, win_read);
1370 addr = GET_MEM_OFFS_2M(addr) + NETXEN_PCI_OCM0_2M;
1372 } else if (ADDR_IN_RANGE(addr,
1373 NETXEN_ADDR_QDR_NET, NETXEN_ADDR_QDR_NET_MAX_P3)) {
1374 /* QDR network side */
1375 window = MS_WIN(addr);
1376 adapter->ahw.qdr_sn_window = window;
1377 adapter->hw_write_wx(adapter,
1378 adapter->ahw.ms_win_crb | NETXEN_PCI_CRBSPACE,
1380 adapter->hw_read_wx(adapter,
1381 adapter->ahw.ms_win_crb | NETXEN_PCI_CRBSPACE,
1383 if (win_read != window) {
1384 printk(KERN_INFO "%s: Written MSwin (0x%x) != "
1385 "Read MSwin (0x%x)\n",
1386 __func__, window, win_read);
1388 addr = GET_MEM_OFFS_2M(addr) + NETXEN_PCI_QDR_NET;
1392 * peg gdb frequently accesses memory that doesn't exist,
1393 * this limits the chit chat so debugging isn't slowed down.
1395 if ((netxen_pci_set_window_warning_count++ < 8)
1396 || (netxen_pci_set_window_warning_count%64 == 0)) {
1397 printk("%s: Warning:%s Unknown address range!\n",
1398 __func__, netxen_nic_driver_name);
1405 static int netxen_nic_pci_is_same_window(struct netxen_adapter *adapter,
1406 unsigned long long addr)
1409 unsigned long long qdr_max;
1411 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
1412 qdr_max = NETXEN_ADDR_QDR_NET_MAX_P2;
1414 qdr_max = NETXEN_ADDR_QDR_NET_MAX_P3;
1416 if (ADDR_IN_RANGE(addr,
1417 NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1418 /* DDR network side */
1419 BUG(); /* MN access can not come here */
1420 } else if (ADDR_IN_RANGE(addr,
1421 NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
1423 } else if (ADDR_IN_RANGE(addr,
1424 NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) {
1426 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_QDR_NET, qdr_max)) {
1427 /* QDR network side */
1428 window = ((addr - NETXEN_ADDR_QDR_NET) >> 22) & 0x3f;
1429 if (adapter->ahw.qdr_sn_window == window)
1436 static int netxen_nic_pci_mem_read_direct(struct netxen_adapter *adapter,
1437 u64 off, void *data, int size)
1439 unsigned long flags;
1443 uint8_t *mem_ptr = NULL;
1444 unsigned long mem_base;
1445 unsigned long mem_page;
1447 write_lock_irqsave(&adapter->adapter_lock, flags);
1450 * If attempting to access unknown address or straddle hw windows,
1453 start = adapter->pci_set_window(adapter, off);
1454 if ((start == -1UL) ||
1455 (netxen_nic_pci_is_same_window(adapter, off+size-1) == 0)) {
1456 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1457 printk(KERN_ERR "%s out of bound pci memory access. "
1458 "offset is 0x%llx\n", netxen_nic_driver_name,
1459 (unsigned long long)off);
1463 addr = (void *)(pci_base_offset(adapter, start));
1465 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1466 mem_base = pci_resource_start(adapter->pdev, 0);
1467 mem_page = start & PAGE_MASK;
1468 /* Map two pages whenever user tries to access addresses in two
1471 if (mem_page != ((start + size - 1) & PAGE_MASK))
1472 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2);
1474 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
1475 if (mem_ptr == NULL) {
1476 *(uint8_t *)data = 0;
1480 addr += start & (PAGE_SIZE - 1);
1481 write_lock_irqsave(&adapter->adapter_lock, flags);
1486 *(uint8_t *)data = readb(addr);
1489 *(uint16_t *)data = readw(addr);
1492 *(uint32_t *)data = readl(addr);
1495 *(uint64_t *)data = readq(addr);
1501 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1502 DPRINTK(1, INFO, "read %llx\n", *(unsigned long long *)data);
1510 netxen_nic_pci_mem_write_direct(struct netxen_adapter *adapter, u64 off,
1511 void *data, int size)
1513 unsigned long flags;
1517 uint8_t *mem_ptr = NULL;
1518 unsigned long mem_base;
1519 unsigned long mem_page;
1521 write_lock_irqsave(&adapter->adapter_lock, flags);
1524 * If attempting to access unknown address or straddle hw windows,
1527 start = adapter->pci_set_window(adapter, off);
1528 if ((start == -1UL) ||
1529 (netxen_nic_pci_is_same_window(adapter, off+size-1) == 0)) {
1530 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1531 printk(KERN_ERR "%s out of bound pci memory access. "
1532 "offset is 0x%llx\n", netxen_nic_driver_name,
1533 (unsigned long long)off);
1537 addr = (void *)(pci_base_offset(adapter, start));
1539 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1540 mem_base = pci_resource_start(adapter->pdev, 0);
1541 mem_page = start & PAGE_MASK;
1542 /* Map two pages whenever user tries to access addresses in two
1543 * consecutive pages.
1545 if (mem_page != ((start + size - 1) & PAGE_MASK))
1546 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2);
1548 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
1549 if (mem_ptr == NULL)
1552 addr += start & (PAGE_SIZE - 1);
1553 write_lock_irqsave(&adapter->adapter_lock, flags);
1558 writeb(*(uint8_t *)data, addr);
1561 writew(*(uint16_t *)data, addr);
1564 writel(*(uint32_t *)data, addr);
1567 writeq(*(uint64_t *)data, addr);
1573 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1574 DPRINTK(1, INFO, "writing data %llx to offset %llx\n",
1575 *(unsigned long long *)data, start);
1581 #define MAX_CTL_CHECK 1000
1584 netxen_nic_pci_mem_write_128M(struct netxen_adapter *adapter,
1585 u64 off, void *data, int size)
1587 unsigned long flags, mem_crb;
1588 int i, j, ret = 0, loop, sz[2], off0;
1590 uint64_t off8, tmpw, word[2] = {0, 0};
1593 * If not MN, go check for MS or invalid.
1595 if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0)
1596 return netxen_nic_pci_mem_write_direct(adapter,
1599 off8 = off & 0xfffffff8;
1601 sz[0] = (size < (8 - off0)) ? size : (8 - off0);
1602 sz[1] = size - sz[0];
1603 loop = ((off0 + size - 1) >> 3) + 1;
1604 mem_crb = (unsigned long)pci_base_offset(adapter, NETXEN_CRB_DDR_NET);
1606 if ((size != 8) || (off0 != 0)) {
1607 for (i = 0; i < loop; i++) {
1608 if (adapter->pci_mem_read(adapter,
1609 off8 + (i << 3), &word[i], 8))
1616 tmpw = *((uint8_t *)data);
1619 tmpw = *((uint16_t *)data);
1622 tmpw = *((uint32_t *)data);
1626 tmpw = *((uint64_t *)data);
1629 word[0] &= ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8));
1630 word[0] |= tmpw << (off0 * 8);
1633 word[1] &= ~(~0ULL << (sz[1] * 8));
1634 word[1] |= tmpw >> (sz[0] * 8);
1637 write_lock_irqsave(&adapter->adapter_lock, flags);
1638 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1640 for (i = 0; i < loop; i++) {
1641 writel((uint32_t)(off8 + (i << 3)),
1642 (void *)(mem_crb+MIU_TEST_AGT_ADDR_LO));
1644 (void *)(mem_crb+MIU_TEST_AGT_ADDR_HI));
1645 writel(word[i] & 0xffffffff,
1646 (void *)(mem_crb+MIU_TEST_AGT_WRDATA_LO));
1647 writel((word[i] >> 32) & 0xffffffff,
1648 (void *)(mem_crb+MIU_TEST_AGT_WRDATA_HI));
1649 writel(MIU_TA_CTL_ENABLE|MIU_TA_CTL_WRITE,
1650 (void *)(mem_crb+MIU_TEST_AGT_CTRL));
1651 writel(MIU_TA_CTL_START|MIU_TA_CTL_ENABLE|MIU_TA_CTL_WRITE,
1652 (void *)(mem_crb+MIU_TEST_AGT_CTRL));
1654 for (j = 0; j < MAX_CTL_CHECK; j++) {
1656 (void *)(mem_crb+MIU_TEST_AGT_CTRL));
1657 if ((temp & MIU_TA_CTL_BUSY) == 0)
1661 if (j >= MAX_CTL_CHECK) {
1662 printk("%s: %s Fail to write through agent\n",
1663 __func__, netxen_nic_driver_name);
1669 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1670 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1675 netxen_nic_pci_mem_read_128M(struct netxen_adapter *adapter,
1676 u64 off, void *data, int size)
1678 unsigned long flags, mem_crb;
1679 int i, j = 0, k, start, end, loop, sz[2], off0[2];
1681 uint64_t off8, val, word[2] = {0, 0};
1685 * If not MN, go check for MS or invalid.
1687 if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0)
1688 return netxen_nic_pci_mem_read_direct(adapter, off, data, size);
1690 off8 = off & 0xfffffff8;
1691 off0[0] = off & 0x7;
1693 sz[0] = (size < (8 - off0[0])) ? size : (8 - off0[0]);
1694 sz[1] = size - sz[0];
1695 loop = ((off0[0] + size - 1) >> 3) + 1;
1696 mem_crb = (unsigned long)pci_base_offset(adapter, NETXEN_CRB_DDR_NET);
1698 write_lock_irqsave(&adapter->adapter_lock, flags);
1699 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1701 for (i = 0; i < loop; i++) {
1702 writel((uint32_t)(off8 + (i << 3)),
1703 (void *)(mem_crb+MIU_TEST_AGT_ADDR_LO));
1705 (void *)(mem_crb+MIU_TEST_AGT_ADDR_HI));
1706 writel(MIU_TA_CTL_ENABLE,
1707 (void *)(mem_crb+MIU_TEST_AGT_CTRL));
1708 writel(MIU_TA_CTL_START|MIU_TA_CTL_ENABLE,
1709 (void *)(mem_crb+MIU_TEST_AGT_CTRL));
1711 for (j = 0; j < MAX_CTL_CHECK; j++) {
1713 (void *)(mem_crb+MIU_TEST_AGT_CTRL));
1714 if ((temp & MIU_TA_CTL_BUSY) == 0)
1718 if (j >= MAX_CTL_CHECK) {
1719 printk(KERN_ERR "%s: %s Fail to read through agent\n",
1720 __func__, netxen_nic_driver_name);
1724 start = off0[i] >> 2;
1725 end = (off0[i] + sz[i] - 1) >> 2;
1726 for (k = start; k <= end; k++) {
1727 word[i] |= ((uint64_t) readl(
1729 MIU_TEST_AGT_RDDATA(k))) << (32*k));
1733 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1734 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1736 if (j >= MAX_CTL_CHECK)
1742 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) |
1743 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8));
1748 *(uint8_t *)data = val;
1751 *(uint16_t *)data = val;
1754 *(uint32_t *)data = val;
1757 *(uint64_t *)data = val;
1760 DPRINTK(1, INFO, "read %llx\n", *(unsigned long long *)data);
1765 netxen_nic_pci_mem_write_2M(struct netxen_adapter *adapter,
1766 u64 off, void *data, int size)
1768 int i, j, ret = 0, loop, sz[2], off0;
1770 uint64_t off8, mem_crb, tmpw, word[2] = {0, 0};
1773 * If not MN, go check for MS or invalid.
1775 if (off >= NETXEN_ADDR_QDR_NET && off <= NETXEN_ADDR_QDR_NET_MAX_P3)
1776 mem_crb = NETXEN_CRB_QDR_NET;
1778 mem_crb = NETXEN_CRB_DDR_NET;
1779 if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0)
1780 return netxen_nic_pci_mem_write_direct(adapter,
1784 off8 = off & 0xfffffff8;
1786 sz[0] = (size < (8 - off0)) ? size : (8 - off0);
1787 sz[1] = size - sz[0];
1788 loop = ((off0 + size - 1) >> 3) + 1;
1790 if ((size != 8) || (off0 != 0)) {
1791 for (i = 0; i < loop; i++) {
1792 if (adapter->pci_mem_read(adapter, off8 + (i << 3),
1800 tmpw = *((uint8_t *)data);
1803 tmpw = *((uint16_t *)data);
1806 tmpw = *((uint32_t *)data);
1810 tmpw = *((uint64_t *)data);
1814 word[0] &= ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8));
1815 word[0] |= tmpw << (off0 * 8);
1818 word[1] &= ~(~0ULL << (sz[1] * 8));
1819 word[1] |= tmpw >> (sz[0] * 8);
1823 * don't lock here - write_wx gets the lock if each time
1824 * write_lock_irqsave(&adapter->adapter_lock, flags);
1825 * netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1828 for (i = 0; i < loop; i++) {
1829 temp = off8 + (i << 3);
1830 adapter->hw_write_wx(adapter,
1831 mem_crb+MIU_TEST_AGT_ADDR_LO, &temp, 4);
1833 adapter->hw_write_wx(adapter,
1834 mem_crb+MIU_TEST_AGT_ADDR_HI, &temp, 4);
1835 temp = word[i] & 0xffffffff;
1836 adapter->hw_write_wx(adapter,
1837 mem_crb+MIU_TEST_AGT_WRDATA_LO, &temp, 4);
1838 temp = (word[i] >> 32) & 0xffffffff;
1839 adapter->hw_write_wx(adapter,
1840 mem_crb+MIU_TEST_AGT_WRDATA_HI, &temp, 4);
1841 temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
1842 adapter->hw_write_wx(adapter,
1843 mem_crb+MIU_TEST_AGT_CTRL, &temp, 4);
1844 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
1845 adapter->hw_write_wx(adapter,
1846 mem_crb+MIU_TEST_AGT_CTRL, &temp, 4);
1848 for (j = 0; j < MAX_CTL_CHECK; j++) {
1849 adapter->hw_read_wx(adapter,
1850 mem_crb + MIU_TEST_AGT_CTRL, &temp, 4);
1851 if ((temp & MIU_TA_CTL_BUSY) == 0)
1855 if (j >= MAX_CTL_CHECK) {
1856 printk(KERN_ERR "%s: Fail to write through agent\n",
1857 netxen_nic_driver_name);
1864 * netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1865 * write_unlock_irqrestore(&adapter->adapter_lock, flags);
1871 netxen_nic_pci_mem_read_2M(struct netxen_adapter *adapter,
1872 u64 off, void *data, int size)
1874 int i, j = 0, k, start, end, loop, sz[2], off0[2];
1876 uint64_t off8, val, mem_crb, word[2] = {0, 0};
1879 * If not MN, go check for MS or invalid.
1882 if (off >= NETXEN_ADDR_QDR_NET && off <= NETXEN_ADDR_QDR_NET_MAX_P3)
1883 mem_crb = NETXEN_CRB_QDR_NET;
1885 mem_crb = NETXEN_CRB_DDR_NET;
1886 if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0)
1887 return netxen_nic_pci_mem_read_direct(adapter,
1891 off8 = off & 0xfffffff8;
1892 off0[0] = off & 0x7;
1894 sz[0] = (size < (8 - off0[0])) ? size : (8 - off0[0]);
1895 sz[1] = size - sz[0];
1896 loop = ((off0[0] + size - 1) >> 3) + 1;
1899 * don't lock here - write_wx gets the lock if each time
1900 * write_lock_irqsave(&adapter->adapter_lock, flags);
1901 * netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1904 for (i = 0; i < loop; i++) {
1905 temp = off8 + (i << 3);
1906 adapter->hw_write_wx(adapter,
1907 mem_crb + MIU_TEST_AGT_ADDR_LO, &temp, 4);
1909 adapter->hw_write_wx(adapter,
1910 mem_crb + MIU_TEST_AGT_ADDR_HI, &temp, 4);
1911 temp = MIU_TA_CTL_ENABLE;
1912 adapter->hw_write_wx(adapter,
1913 mem_crb + MIU_TEST_AGT_CTRL, &temp, 4);
1914 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE;
1915 adapter->hw_write_wx(adapter,
1916 mem_crb + MIU_TEST_AGT_CTRL, &temp, 4);
1918 for (j = 0; j < MAX_CTL_CHECK; j++) {
1919 adapter->hw_read_wx(adapter,
1920 mem_crb + MIU_TEST_AGT_CTRL, &temp, 4);
1921 if ((temp & MIU_TA_CTL_BUSY) == 0)
1925 if (j >= MAX_CTL_CHECK) {
1926 printk(KERN_ERR "%s: Fail to read through agent\n",
1927 netxen_nic_driver_name);
1931 start = off0[i] >> 2;
1932 end = (off0[i] + sz[i] - 1) >> 2;
1933 for (k = start; k <= end; k++) {
1934 adapter->hw_read_wx(adapter,
1935 mem_crb + MIU_TEST_AGT_RDDATA(k), &temp, 4);
1936 word[i] |= ((uint64_t)temp << (32 * k));
1941 * netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1942 * write_unlock_irqrestore(&adapter->adapter_lock, flags);
1945 if (j >= MAX_CTL_CHECK)
1951 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) |
1952 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8));
1957 *(uint8_t *)data = val;
1960 *(uint16_t *)data = val;
1963 *(uint32_t *)data = val;
1966 *(uint64_t *)data = val;
1969 DPRINTK(1, INFO, "read %llx\n", *(unsigned long long *)data);
1974 * Note : only 32-bit writes!
1976 int netxen_nic_pci_write_immediate_2M(struct netxen_adapter *adapter,
1979 adapter->hw_write_wx(adapter, off, &data, 4);
1984 u32 netxen_nic_pci_read_immediate_2M(struct netxen_adapter *adapter, u64 off)
1987 adapter->hw_read_wx(adapter, off, &temp, 4);
1991 void netxen_nic_pci_write_normalize_2M(struct netxen_adapter *adapter,
1994 adapter->hw_write_wx(adapter, off, &data, 4);
1997 u32 netxen_nic_pci_read_normalize_2M(struct netxen_adapter *adapter, u64 off)
2000 adapter->hw_read_wx(adapter, off, &temp, 4);
2006 netxen_nic_erase_pxe(struct netxen_adapter *adapter)
2008 if (netxen_rom_fast_write(adapter, NETXEN_PXE_START, 0) == -1) {
2009 printk(KERN_ERR "%s: erase pxe failed\n",
2010 netxen_nic_driver_name);
2017 int netxen_nic_get_board_info(struct netxen_adapter *adapter)
2020 int addr = NETXEN_BRDCFG_START;
2021 struct netxen_board_info *boardinfo;
2025 boardinfo = &adapter->ahw.boardcfg;
2026 ptr32 = (u32 *) boardinfo;
2028 for (index = 0; index < sizeof(struct netxen_board_info) / sizeof(u32);
2030 if (netxen_rom_fast_read(adapter, addr, ptr32) == -1) {
2034 addr += sizeof(u32);
2036 if (boardinfo->magic != NETXEN_BDINFO_MAGIC) {
2037 printk("%s: ERROR reading %s board config."
2038 " Read %x, expected %x\n", netxen_nic_driver_name,
2039 netxen_nic_driver_name,
2040 boardinfo->magic, NETXEN_BDINFO_MAGIC);
2043 if (boardinfo->header_version != NETXEN_BDINFO_VERSION) {
2044 printk("%s: Unknown board config version."
2045 " Read %x, expected %x\n", netxen_nic_driver_name,
2046 boardinfo->header_version, NETXEN_BDINFO_VERSION);
2050 if (boardinfo->board_type == NETXEN_BRDTYPE_P3_4_GB_MM) {
2051 u32 gpio = netxen_nic_reg_read(adapter,
2052 NETXEN_ROMUSB_GLB_PAD_GPIO_I);
2053 if ((gpio & 0x8000) == 0)
2054 boardinfo->board_type = NETXEN_BRDTYPE_P3_10G_TP;
2057 switch ((netxen_brdtype_t) boardinfo->board_type) {
2058 case NETXEN_BRDTYPE_P2_SB35_4G:
2059 adapter->ahw.board_type = NETXEN_NIC_GBE;
2061 case NETXEN_BRDTYPE_P2_SB31_10G:
2062 case NETXEN_BRDTYPE_P2_SB31_10G_IMEZ:
2063 case NETXEN_BRDTYPE_P2_SB31_10G_HMEZ:
2064 case NETXEN_BRDTYPE_P2_SB31_10G_CX4:
2065 case NETXEN_BRDTYPE_P3_HMEZ:
2066 case NETXEN_BRDTYPE_P3_XG_LOM:
2067 case NETXEN_BRDTYPE_P3_10G_CX4:
2068 case NETXEN_BRDTYPE_P3_10G_CX4_LP:
2069 case NETXEN_BRDTYPE_P3_IMEZ:
2070 case NETXEN_BRDTYPE_P3_10G_SFP_PLUS:
2071 case NETXEN_BRDTYPE_P3_10G_SFP_CT:
2072 case NETXEN_BRDTYPE_P3_10G_SFP_QT:
2073 case NETXEN_BRDTYPE_P3_10G_XFP:
2074 case NETXEN_BRDTYPE_P3_10000_BASE_T:
2075 adapter->ahw.board_type = NETXEN_NIC_XGBE;
2077 case NETXEN_BRDTYPE_P1_BD:
2078 case NETXEN_BRDTYPE_P1_SB:
2079 case NETXEN_BRDTYPE_P1_SMAX:
2080 case NETXEN_BRDTYPE_P1_SOCK:
2081 case NETXEN_BRDTYPE_P3_REF_QG:
2082 case NETXEN_BRDTYPE_P3_4_GB:
2083 case NETXEN_BRDTYPE_P3_4_GB_MM:
2084 adapter->ahw.board_type = NETXEN_NIC_GBE;
2086 case NETXEN_BRDTYPE_P3_10G_TP:
2087 adapter->ahw.board_type = (adapter->portnum < 2) ?
2088 NETXEN_NIC_XGBE : NETXEN_NIC_GBE;
2091 printk("%s: Unknown(%x)\n", netxen_nic_driver_name,
2092 boardinfo->board_type);
2100 /* NIU access sections */
2102 int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu)
2104 new_mtu += MTU_FUDGE_FACTOR;
2105 netxen_nic_write_w0(adapter,
2106 NETXEN_NIU_GB_MAX_FRAME_SIZE(adapter->physical_port),
2111 int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu)
2113 new_mtu += MTU_FUDGE_FACTOR;
2114 if (adapter->physical_port == 0)
2115 netxen_nic_write_w0(adapter, NETXEN_NIU_XGE_MAX_FRAME_SIZE,
2118 netxen_nic_write_w0(adapter, NETXEN_NIU_XG1_MAX_FRAME_SIZE,
2124 netxen_crb_writelit_adapter(struct netxen_adapter *adapter,
2125 unsigned long off, int data)
2127 adapter->hw_write_wx(adapter, off, &data, 4);
2130 void netxen_nic_set_link_parameters(struct netxen_adapter *adapter)
2136 if (!netif_carrier_ok(adapter->netdev)) {
2137 adapter->link_speed = 0;
2138 adapter->link_duplex = -1;
2139 adapter->link_autoneg = AUTONEG_ENABLE;
2143 if (adapter->ahw.board_type == NETXEN_NIC_GBE) {
2144 adapter->hw_read_wx(adapter,
2145 NETXEN_PORT_MODE_ADDR, &port_mode, 4);
2146 if (port_mode == NETXEN_PORT_MODE_802_3_AP) {
2147 adapter->link_speed = SPEED_1000;
2148 adapter->link_duplex = DUPLEX_FULL;
2149 adapter->link_autoneg = AUTONEG_DISABLE;
2153 if (adapter->phy_read
2154 && adapter->phy_read(adapter,
2155 NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS,
2157 if (netxen_get_phy_link(status)) {
2158 switch (netxen_get_phy_speed(status)) {
2160 adapter->link_speed = SPEED_10;
2163 adapter->link_speed = SPEED_100;
2166 adapter->link_speed = SPEED_1000;
2169 adapter->link_speed = 0;
2172 switch (netxen_get_phy_duplex(status)) {
2174 adapter->link_duplex = DUPLEX_HALF;
2177 adapter->link_duplex = DUPLEX_FULL;
2180 adapter->link_duplex = -1;
2183 if (adapter->phy_read
2184 && adapter->phy_read(adapter,
2185 NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG,
2187 adapter->link_autoneg = autoneg;
2192 adapter->link_speed = 0;
2193 adapter->link_duplex = -1;
2198 void netxen_nic_flash_print(struct netxen_adapter *adapter)
2203 char brd_name[NETXEN_MAX_SHORT_NAME];
2204 char serial_num[32];
2208 struct netxen_board_info *board_info = &(adapter->ahw.boardcfg);
2210 adapter->driver_mismatch = 0;
2212 ptr32 = (u32 *)&serial_num;
2213 addr = NETXEN_USER_START +
2214 offsetof(struct netxen_new_user_info, serial_num);
2215 for (i = 0; i < 8; i++) {
2216 if (netxen_rom_fast_read(adapter, addr, ptr32) == -1) {
2217 printk("%s: ERROR reading %s board userarea.\n",
2218 netxen_nic_driver_name,
2219 netxen_nic_driver_name);
2220 adapter->driver_mismatch = 1;
2224 addr += sizeof(u32);
2227 adapter->hw_read_wx(adapter, NETXEN_FW_VERSION_MAJOR, &fw_major, 4);
2228 adapter->hw_read_wx(adapter, NETXEN_FW_VERSION_MINOR, &fw_minor, 4);
2229 adapter->hw_read_wx(adapter, NETXEN_FW_VERSION_SUB, &fw_build, 4);
2231 adapter->fw_major = fw_major;
2233 if (adapter->portnum == 0) {
2234 get_brd_name_by_type(board_info->board_type, brd_name);
2236 printk(KERN_INFO "NetXen %s Board S/N %s Chip rev 0x%x\n",
2237 brd_name, serial_num, adapter->ahw.revision_id);
2238 printk(KERN_INFO "NetXen Firmware version %d.%d.%d\n",
2239 fw_major, fw_minor, fw_build);
2242 if (NETXEN_VERSION_CODE(fw_major, fw_minor, fw_build) <
2243 NETXEN_VERSION_CODE(3, 4, 216)) {
2244 adapter->driver_mismatch = 1;
2245 printk(KERN_ERR "%s: firmware version %d.%d.%d unsupported\n",
2246 netxen_nic_driver_name,
2247 fw_major, fw_minor, fw_build);