drivers/net/niu.c

   1 /* niu.c: Neptune ethernet driver.
   2  *
   3  * Copyright (C) 2007 David S. Miller (davem@davemloft.net)
   4  */
   5
   6 #include <linux/module.h>
   7 #include <linux/init.h>
   8 #include <linux/pci.h>
   9 #include <linux/dma-mapping.h>
  10 #include <linux/netdevice.h>
  11 #include <linux/ethtool.h>
  12 #include <linux/etherdevice.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/delay.h>
  15 #include <linux/bitops.h>
  16 #include <linux/mii.h>
  17 #include <linux/if_ether.h>
  18 #include <linux/if_vlan.h>
  19 #include <linux/ip.h>
  20 #include <linux/in.h>
  21 #include <linux/ipv6.h>
  22 #include <linux/log2.h>
  23 #include <linux/jiffies.h>
  24 #include <linux/crc32.h>
  25
  26 #include <linux/io.h>
  27
  28 #ifdef CONFIG_SPARC64
  29 #include <linux/of_device.h>
  30 #endif
  31
  32 #include "niu.h"
  33
  34 #define DRV_MODULE_NAME         "niu"
  35 #define PFX DRV_MODULE_NAME     ": "
  36 #define DRV_MODULE_VERSION      "0.5"
  37 #define DRV_MODULE_RELDATE      "October 5, 2007"
  38
  39 static char version[] __devinitdata =
  40         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
  41
  42 MODULE_AUTHOR("David S. Miller (davem@davemloft.net)");
  43 MODULE_DESCRIPTION("NIU ethernet driver");
  44 MODULE_LICENSE("GPL");
  45 MODULE_VERSION(DRV_MODULE_VERSION);
  46
  47 #ifndef DMA_44BIT_MASK
  48 #define DMA_44BIT_MASK  0x00000fffffffffffULL
  49 #endif
  50
  51 #ifndef readq
  52 static u64 readq(void __iomem *reg)
  53 {
  54         return (((u64)readl(reg + 0x4UL) << 32) |
  55                 (u64)readl(reg));
  56 }
  57
  58 static void writeq(u64 val, void __iomem *reg)
  59 {
  60         writel(val & 0xffffffff, reg);
  61         writel(val >> 32, reg + 0x4UL);
  62 }
  63 #endif
  64
  65 static struct pci_device_id niu_pci_tbl[] = {
  66         {PCI_DEVICE(PCI_VENDOR_ID_SUN, 0xabcd)},
  67         {}
  68 };
  69
  70 MODULE_DEVICE_TABLE(pci, niu_pci_tbl);
  71
  72 #define NIU_TX_TIMEOUT                  (5 * HZ)
  73
  74 #define nr64(reg)               readq(np->regs + (reg))
  75 #define nw64(reg, val)          writeq((val), np->regs + (reg))
  76
  77 #define nr64_mac(reg)           readq(np->mac_regs + (reg))
  78 #define nw64_mac(reg, val)      writeq((val), np->mac_regs + (reg))
  79
  80 #define nr64_ipp(reg)           readq(np->regs + np->ipp_off + (reg))
  81 #define nw64_ipp(reg, val)      writeq((val), np->regs + np->ipp_off + (reg))
  82
  83 #define nr64_pcs(reg)           readq(np->regs + np->pcs_off + (reg))
  84 #define nw64_pcs(reg, val)      writeq((val), np->regs + np->pcs_off + (reg))
  85
  86 #define nr64_xpcs(reg)          readq(np->regs + np->xpcs_off + (reg))
  87 #define nw64_xpcs(reg, val)     writeq((val), np->regs + np->xpcs_off + (reg))
  88
  89 #define NIU_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
  90
  91 static int niu_debug;
  92 static int debug = -1;
  93 module_param(debug, int, 0);
  94 MODULE_PARM_DESC(debug, "NIU debug level");
  95
  96 #define niudbg(TYPE, f, a...) \
  97 do {    if ((np)->msg_enable & NETIF_MSG_##TYPE) \
  98                 printk(KERN_DEBUG PFX f, ## a); \
  99 } while (0)
 100
 101 #define niuinfo(TYPE, f, a...) \
 102 do {    if ((np)->msg_enable & NETIF_MSG_##TYPE) \
 103                 printk(KERN_INFO PFX f, ## a); \
 104 } while (0)
 105
 106 #define niuwarn(TYPE, f, a...) \
 107 do {    if ((np)->msg_enable & NETIF_MSG_##TYPE) \
 108                 printk(KERN_WARNING PFX f, ## a); \
 109 } while (0)
 110
 111 #define niu_lock_parent(np, flags) \
 112         spin_lock_irqsave(&np->parent->lock, flags)
 113 #define niu_unlock_parent(np, flags) \
 114         spin_unlock_irqrestore(&np->parent->lock, flags)
 115
 116 static int __niu_wait_bits_clear_mac(struct niu *np, unsigned long reg,
 117                                      u64 bits, int limit, int delay)
 118 {
 119         while (--limit >= 0) {
 120                 u64 val = nr64_mac(reg);
 121
 122                 if (!(val & bits))
 123                         break;
 124                 udelay(delay);
 125         }
 126         if (limit < 0)
 127                 return -ENODEV;
 128         return 0;
 129 }
 130
 131 static int __niu_set_and_wait_clear_mac(struct niu *np, unsigned long reg,
 132                                         u64 bits, int limit, int delay,
 133                                         const char *reg_name)
 134 {
 135         int err;
 136
 137         nw64_mac(reg, bits);
 138         err = __niu_wait_bits_clear_mac(np, reg, bits, limit, delay);
 139         if (err)
 140                 dev_err(np->device, PFX "%s: bits (%llx) of register %s "
 141                         "would not clear, val[%llx]\n",
 142                         np->dev->name, (unsigned long long) bits, reg_name,
 143                         (unsigned long long) nr64_mac(reg));
 144         return err;
 145 }
 146
 147 #define niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
 148 ({      BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
 149         __niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
 150 })
 151
 152 static int __niu_wait_bits_clear_ipp(struct niu *np, unsigned long reg,
 153                                      u64 bits, int limit, int delay)
 154 {
 155         while (--limit >= 0) {
 156                 u64 val = nr64_ipp(reg);
 157
 158                 if (!(val & bits))
 159                         break;
 160                 udelay(delay);
 161         }
 162         if (limit < 0)
 163                 return -ENODEV;
 164         return 0;
 165 }
 166
 167 static int __niu_set_and_wait_clear_ipp(struct niu *np, unsigned long reg,
 168                                         u64 bits, int limit, int delay,
 169                                         const char *reg_name)
 170 {
 171         int err;
 172         u64 val;
 173
 174         val = nr64_ipp(reg);
 175         val |= bits;
 176         nw64_ipp(reg, val);
 177
 178         err = __niu_wait_bits_clear_ipp(np, reg, bits, limit, delay);
 179         if (err)
 180                 dev_err(np->device, PFX "%s: bits (%llx) of register %s "
 181                         "would not clear, val[%llx]\n",
 182                         np->dev->name, (unsigned long long) bits, reg_name,
 183                         (unsigned long long) nr64_ipp(reg));
 184         return err;
 185 }
 186
 187 #define niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
 188 ({      BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
 189         __niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
 190 })
 191
 192 static int __niu_wait_bits_clear(struct niu *np, unsigned long reg,
 193                                  u64 bits, int limit, int delay)
 194 {
 195         while (--limit >= 0) {
 196                 u64 val = nr64(reg);
 197
 198                 if (!(val & bits))
 199                         break;
 200                 udelay(delay);
 201         }
 202         if (limit < 0)
 203                 return -ENODEV;
 204         return 0;
 205 }
 206
 207 #define niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY) \
 208 ({      BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
 209         __niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY); \
 210 })
 211
 212 static int __niu_set_and_wait_clear(struct niu *np, unsigned long reg,
 213                                     u64 bits, int limit, int delay,
 214                                     const char *reg_name)
 215 {
 216         int err;
 217
 218         nw64(reg, bits);
 219         err = __niu_wait_bits_clear(np, reg, bits, limit, delay);
 220         if (err)
 221                 dev_err(np->device, PFX "%s: bits (%llx) of register %s "
 222                         "would not clear, val[%llx]\n",
 223                         np->dev->name, (unsigned long long) bits, reg_name,
 224                         (unsigned long long) nr64(reg));
 225         return err;
 226 }
 227
 228 #define niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
 229 ({      BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
 230         __niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
 231 })
 232
 233 static void niu_ldg_rearm(struct niu *np, struct niu_ldg *lp, int on)
 234 {
 235         u64 val = (u64) lp->timer;
 236
 237         if (on)
 238                 val |= LDG_IMGMT_ARM;
 239
 240         nw64(LDG_IMGMT(lp->ldg_num), val);
 241 }
 242
 243 static int niu_ldn_irq_enable(struct niu *np, int ldn, int on)
 244 {
 245         unsigned long mask_reg, bits;
 246         u64 val;
 247
 248         if (ldn < 0 || ldn > LDN_MAX)
 249                 return -EINVAL;
 250
 251         if (ldn < 64) {
 252                 mask_reg = LD_IM0(ldn);
 253                 bits = LD_IM0_MASK;
 254         } else {
 255                 mask_reg = LD_IM1(ldn - 64);
 256                 bits = LD_IM1_MASK;
 257         }
 258
 259         val = nr64(mask_reg);
 260         if (on)
 261                 val &= ~bits;
 262         else
 263                 val |= bits;
 264         nw64(mask_reg, val);
 265
 266         return 0;
 267 }
 268
 269 static int niu_enable_ldn_in_ldg(struct niu *np, struct niu_ldg *lp, int on)
 270 {
 271         struct niu_parent *parent = np->parent;
 272         int i;
 273
 274         for (i = 0; i <= LDN_MAX; i++) {
 275                 int err;
 276
 277                 if (parent->ldg_map[i] != lp->ldg_num)
 278                         continue;
 279
 280                 err = niu_ldn_irq_enable(np, i, on);
 281                 if (err)
 282                         return err;
 283         }
 284         return 0;
 285 }
 286
 287 static int niu_enable_interrupts(struct niu *np, int on)
 288 {
 289         int i;
 290
 291         for (i = 0; i < np->num_ldg; i++) {
 292                 struct niu_ldg *lp = &np->ldg[i];
 293                 int err;
 294
 295                 err = niu_enable_ldn_in_ldg(np, lp, on);
 296                 if (err)
 297                         return err;
 298         }
 299         for (i = 0; i < np->num_ldg; i++)
 300                 niu_ldg_rearm(np, &np->ldg[i], on);
 301
 302         return 0;
 303 }
 304
 305 static u32 phy_encode(u32 type, int port)
 306 {
 307         return (type << (port * 2));
 308 }
 309
 310 static u32 phy_decode(u32 val, int port)
 311 {
 312         return (val >> (port * 2)) & PORT_TYPE_MASK;
 313 }
 314
 315 static int mdio_wait(struct niu *np)
 316 {
 317         int limit = 1000;
 318         u64 val;
 319
 320         while (--limit > 0) {
 321                 val = nr64(MIF_FRAME_OUTPUT);
 322                 if ((val >> MIF_FRAME_OUTPUT_TA_SHIFT) & 0x1)
 323                         return val & MIF_FRAME_OUTPUT_DATA;
 324
 325                 udelay(10);
 326         }
 327
 328         return -ENODEV;
 329 }
 330
 331 static int mdio_read(struct niu *np, int port, int dev, int reg)
 332 {
 333         int err;
 334
 335         nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg));
 336         err = mdio_wait(np);
 337         if (err < 0)
 338                 return err;
 339
 340         nw64(MIF_FRAME_OUTPUT, MDIO_READ_OP(port, dev));
 341         return mdio_wait(np);
 342 }
 343
 344 static int mdio_write(struct niu *np, int port, int dev, int reg, int data)
 345 {
 346         int err;
 347
 348         nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg));
 349         err = mdio_wait(np);
 350         if (err < 0)
 351                 return err;
 352
 353         nw64(MIF_FRAME_OUTPUT, MDIO_WRITE_OP(port, dev, data));
 354         err = mdio_wait(np);
 355         if (err < 0)
 356                 return err;
 357
 358         return 0;
 359 }
 360
 361 static int mii_read(struct niu *np, int port, int reg)
 362 {
 363         nw64(MIF_FRAME_OUTPUT, MII_READ_OP(port, reg));
 364         return mdio_wait(np);
 365 }
 366
 367 static int mii_write(struct niu *np, int port, int reg, int data)
 368 {
 369         int err;
 370
 371         nw64(MIF_FRAME_OUTPUT, MII_WRITE_OP(port, reg, data));
 372         err = mdio_wait(np);
 373         if (err < 0)
 374                 return err;
 375
 376         return 0;
 377 }
 378
 379 static int esr2_set_tx_cfg(struct niu *np, unsigned long channel, u32 val)
 380 {
 381         int err;
 382
 383         err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 384                          ESR2_TI_PLL_TX_CFG_L(channel),
 385                          val & 0xffff);
 386         if (!err)
 387                 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 388                                  ESR2_TI_PLL_TX_CFG_H(channel),
 389                                  val >> 16);
 390         return err;
 391 }
 392
 393 static int esr2_set_rx_cfg(struct niu *np, unsigned long channel, u32 val)
 394 {
 395         int err;
 396
 397         err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 398                          ESR2_TI_PLL_RX_CFG_L(channel),
 399                          val & 0xffff);
 400         if (!err)
 401                 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 402                                  ESR2_TI_PLL_RX_CFG_H(channel),
 403                                  val >> 16);
 404         return err;
 405 }
 406
 407 /* Mode is always 10G fiber.  */
 408 static int serdes_init_niu(struct niu *np)
 409 {
 410         struct niu_link_config *lp = &np->link_config;
 411         u32 tx_cfg, rx_cfg;
 412         unsigned long i;
 413
 414         tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV);
 415         rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
 416                   PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
 417                   PLL_RX_CFG_EQ_LP_ADAPTIVE);
 418
 419         if (lp->loopback_mode == LOOPBACK_PHY) {
 420                 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
 421
 422                 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 423                            ESR2_TI_PLL_TEST_CFG_L, test_cfg);
 424
 425                 tx_cfg |= PLL_TX_CFG_ENTEST;
 426                 rx_cfg |= PLL_RX_CFG_ENTEST;
 427         }
 428
 429         /* Initialize all 4 lanes of the SERDES.  */
 430         for (i = 0; i < 4; i++) {
 431                 int err = esr2_set_tx_cfg(np, i, tx_cfg);
 432                 if (err)
 433                         return err;
 434         }
 435
 436         for (i = 0; i < 4; i++) {
 437                 int err = esr2_set_rx_cfg(np, i, rx_cfg);
 438                 if (err)
 439                         return err;
 440         }
 441
 442         return 0;
 443 }
 444
 445 static int esr_read_rxtx_ctrl(struct niu *np, unsigned long chan, u32 *val)
 446 {
 447         int err;
 448
 449         err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR, ESR_RXTX_CTRL_L(chan));
 450         if (err >= 0) {
 451                 *val = (err & 0xffff);
 452                 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
 453                                 ESR_RXTX_CTRL_H(chan));
 454                 if (err >= 0)
 455                         *val |= ((err & 0xffff) << 16);
 456                 err = 0;
 457         }
 458         return err;
 459 }
 460
 461 static int esr_read_glue0(struct niu *np, unsigned long chan, u32 *val)
 462 {
 463         int err;
 464
 465         err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
 466                         ESR_GLUE_CTRL0_L(chan));
 467         if (err >= 0) {
 468                 *val = (err & 0xffff);
 469                 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
 470                                 ESR_GLUE_CTRL0_H(chan));
 471                 if (err >= 0) {
 472                         *val |= ((err & 0xffff) << 16);
 473                         err = 0;
 474                 }
 475         }
 476         return err;
 477 }
 478
 479 static int esr_read_reset(struct niu *np, u32 *val)
 480 {
 481         int err;
 482
 483         err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
 484                         ESR_RXTX_RESET_CTRL_L);
 485         if (err >= 0) {
 486                 *val = (err & 0xffff);
 487                 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
 488                                 ESR_RXTX_RESET_CTRL_H);
 489                 if (err >= 0) {
 490                         *val |= ((err & 0xffff) << 16);
 491                         err = 0;
 492                 }
 493         }
 494         return err;
 495 }
 496
 497 static int esr_write_rxtx_ctrl(struct niu *np, unsigned long chan, u32 val)
 498 {
 499         int err;
 500
 501         err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
 502                          ESR_RXTX_CTRL_L(chan), val & 0xffff);
 503         if (!err)
 504                 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
 505                                  ESR_RXTX_CTRL_H(chan), (val >> 16));
 506         return err;
 507 }
 508
 509 static int esr_write_glue0(struct niu *np, unsigned long chan, u32 val)
 510 {
 511         int err;
 512
 513         err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
 514                         ESR_GLUE_CTRL0_L(chan), val & 0xffff);
 515         if (!err)
 516                 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
 517                                  ESR_GLUE_CTRL0_H(chan), (val >> 16));
 518         return err;
 519 }
 520
 521 static int esr_reset(struct niu *np)
 522 {
 523         u32 reset;
 524         int err;
 525
 526         err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
 527                          ESR_RXTX_RESET_CTRL_L, 0x0000);
 528         if (err)
 529                 return err;
 530         err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
 531                          ESR_RXTX_RESET_CTRL_H, 0xffff);
 532         if (err)
 533                 return err;
 534         udelay(200);
 535
 536         err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
 537                          ESR_RXTX_RESET_CTRL_L, 0xffff);
 538         if (err)
 539                 return err;
 540         udelay(200);
 541
 542         err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
 543                          ESR_RXTX_RESET_CTRL_H, 0x0000);
 544         if (err)
 545                 return err;
 546         udelay(200);
 547
 548         err = esr_read_reset(np, &reset);
 549         if (err)
 550                 return err;
 551         if (reset != 0) {
 552                 dev_err(np->device, PFX "Port %u ESR_RESET "
 553                         "did not clear [%08x]\n",
 554                         np->port, reset);
 555                 return -ENODEV;
 556         }
 557
 558         return 0;
 559 }
 560
 561 static int serdes_init_10g(struct niu *np)
 562 {
 563         struct niu_link_config *lp = &np->link_config;
 564         unsigned long ctrl_reg, test_cfg_reg, i;
 565         u64 ctrl_val, test_cfg_val, sig, mask, val;
 566         int err;
 567
 568         switch (np->port) {
 569         case 0:
 570                 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
 571                 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
 572                 break;
 573         case 1:
 574                 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
 575                 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
 576                 break;
 577
 578         default:
 579                 return -EINVAL;
 580         }
 581         ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
 582                     ENET_SERDES_CTRL_SDET_1 |
 583                     ENET_SERDES_CTRL_SDET_2 |
 584                     ENET_SERDES_CTRL_SDET_3 |
 585                     (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
 586                     (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
 587                     (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
 588                     (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
 589                     (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
 590                     (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
 591                     (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
 592                     (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
 593         test_cfg_val = 0;
 594
 595         if (lp->loopback_mode == LOOPBACK_PHY) {
 596                 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
 597                                   ENET_SERDES_TEST_MD_0_SHIFT) |
 598                                  (ENET_TEST_MD_PAD_LOOPBACK <<
 599                                   ENET_SERDES_TEST_MD_1_SHIFT) |
 600                                  (ENET_TEST_MD_PAD_LOOPBACK <<
 601                                   ENET_SERDES_TEST_MD_2_SHIFT) |
 602                                  (ENET_TEST_MD_PAD_LOOPBACK <<
 603                                   ENET_SERDES_TEST_MD_3_SHIFT));
 604         }
 605
 606         nw64(ctrl_reg, ctrl_val);
 607         nw64(test_cfg_reg, test_cfg_val);
 608
 609         /* Initialize all 4 lanes of the SERDES.  */
 610         for (i = 0; i < 4; i++) {
 611                 u32 rxtx_ctrl, glue0;
 612
 613                 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
 614                 if (err)
 615                         return err;
 616                 err = esr_read_glue0(np, i, &glue0);
 617                 if (err)
 618                         return err;
 619
 620                 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
 621                 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
 622                               (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
 623
 624                 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
 625                            ESR_GLUE_CTRL0_THCNT |
 626                            ESR_GLUE_CTRL0_BLTIME);
 627                 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
 628                           (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
 629                           (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
 630                           (BLTIME_300_CYCLES <<
 631                            ESR_GLUE_CTRL0_BLTIME_SHIFT));
 632
 633                 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
 634                 if (err)
 635                         return err;
 636                 err = esr_write_glue0(np, i, glue0);
 637                 if (err)
 638                         return err;
 639         }
 640
 641         err = esr_reset(np);
 642         if (err)
 643                 return err;
 644
 645         sig = nr64(ESR_INT_SIGNALS);
 646         switch (np->port) {
 647         case 0:
 648                 mask = ESR_INT_SIGNALS_P0_BITS;
 649                 val = (ESR_INT_SRDY0_P0 |
 650                        ESR_INT_DET0_P0 |
 651                        ESR_INT_XSRDY_P0 |
 652                        ESR_INT_XDP_P0_CH3 |
 653                        ESR_INT_XDP_P0_CH2 |
 654                        ESR_INT_XDP_P0_CH1 |
 655                        ESR_INT_XDP_P0_CH0);
 656                 break;
 657
 658         case 1:
 659                 mask = ESR_INT_SIGNALS_P1_BITS;
 660                 val = (ESR_INT_SRDY0_P1 |
 661                        ESR_INT_DET0_P1 |
 662                        ESR_INT_XSRDY_P1 |
 663                        ESR_INT_XDP_P1_CH3 |
 664                        ESR_INT_XDP_P1_CH2 |
 665                        ESR_INT_XDP_P1_CH1 |
 666                        ESR_INT_XDP_P1_CH0);
 667                 break;
 668
 669         default:
 670                 return -EINVAL;
 671         }
 672
 673         if ((sig & mask) != val) {
 674                 dev_err(np->device, PFX "Port %u signal bits [%08x] are not "
 675                         "[%08x]\n", np->port, (int) (sig & mask), (int) val);
 676                 return -ENODEV;
 677         }
 678
 679         return 0;
 680 }
 681
 682 static int serdes_init_1g(struct niu *np)
 683 {
 684         u64 val;
 685
 686         val = nr64(ENET_SERDES_1_PLL_CFG);
 687         val &= ~ENET_SERDES_PLL_FBDIV2;
 688         switch (np->port) {
 689         case 0:
 690                 val |= ENET_SERDES_PLL_HRATE0;
 691                 break;
 692         case 1:
 693                 val |= ENET_SERDES_PLL_HRATE1;
 694                 break;
 695         case 2:
 696                 val |= ENET_SERDES_PLL_HRATE2;
 697                 break;
 698         case 3:
 699                 val |= ENET_SERDES_PLL_HRATE3;
 700                 break;
 701         default:
 702                 return -EINVAL;
 703         }
 704         nw64(ENET_SERDES_1_PLL_CFG, val);
 705
 706         return 0;
 707 }
 708
 709 static int bcm8704_reset(struct niu *np)
 710 {
 711         int err, limit;
 712
 713         err = mdio_read(np, np->phy_addr,
 714                         BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
 715         if (err < 0)
 716                 return err;
 717         err |= BMCR_RESET;
 718         err = mdio_write(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
 719                          MII_BMCR, err);
 720         if (err)
 721                 return err;
 722
 723         limit = 1000;
 724         while (--limit >= 0) {
 725                 err = mdio_read(np, np->phy_addr,
 726                                 BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
 727                 if (err < 0)
 728                         return err;
 729                 if (!(err & BMCR_RESET))
 730                         break;
 731         }
 732         if (limit < 0) {
 733                 dev_err(np->device, PFX "Port %u PHY will not reset "
 734                         "(bmcr=%04x)\n", np->port, (err & 0xffff));
 735                 return -ENODEV;
 736         }
 737         return 0;
 738 }
 739
 740 /* When written, certain PHY registers need to be read back twice
 741  * in order for the bits to settle properly.
 742  */
 743 static int bcm8704_user_dev3_readback(struct niu *np, int reg)
 744 {
 745         int err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg);
 746         if (err < 0)
 747                 return err;
 748         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg);
 749         if (err < 0)
 750                 return err;
 751         return 0;
 752 }
 753
 754 static int bcm8704_init_user_dev3(struct niu *np)
 755 {
 756         int err;
 757
 758         err = mdio_write(np, np->phy_addr,
 759                          BCM8704_USER_DEV3_ADDR, BCM8704_USER_CONTROL,
 760                          (USER_CONTROL_OPTXRST_LVL |
 761                           USER_CONTROL_OPBIASFLT_LVL |
 762                           USER_CONTROL_OBTMPFLT_LVL |
 763                           USER_CONTROL_OPPRFLT_LVL |
 764                           USER_CONTROL_OPTXFLT_LVL |
 765                           USER_CONTROL_OPRXLOS_LVL |
 766                           USER_CONTROL_OPRXFLT_LVL |
 767                           USER_CONTROL_OPTXON_LVL |
 768                           (0x3f << USER_CONTROL_RES1_SHIFT)));
 769         if (err)
 770                 return err;
 771
 772         err = mdio_write(np, np->phy_addr,
 773                          BCM8704_USER_DEV3_ADDR, BCM8704_USER_PMD_TX_CONTROL,
 774                          (USER_PMD_TX_CTL_XFP_CLKEN |
 775                           (1 << USER_PMD_TX_CTL_TX_DAC_TXD_SH) |
 776                           (2 << USER_PMD_TX_CTL_TX_DAC_TXCK_SH) |
 777                           USER_PMD_TX_CTL_TSCK_LPWREN));
 778         if (err)
 779                 return err;
 780
 781         err = bcm8704_user_dev3_readback(np, BCM8704_USER_CONTROL);
 782         if (err)
 783                 return err;
 784         err = bcm8704_user_dev3_readback(np, BCM8704_USER_PMD_TX_CONTROL);
 785         if (err)
 786                 return err;
 787
 788         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
 789                         BCM8704_USER_OPT_DIGITAL_CTRL);
 790         if (err < 0)
 791                 return err;
 792         err &= ~USER_ODIG_CTRL_GPIOS;
 793         err |= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT);
 794         err = mdio_write(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
 795                          BCM8704_USER_OPT_DIGITAL_CTRL, err);
 796         if (err)
 797                 return err;
 798
 799         mdelay(1000);
 800
 801         return 0;
 802 }
 803
 804 static int xcvr_init_10g(struct niu *np)
 805 {
 806         struct niu_link_config *lp = &np->link_config;
 807         u16 analog_stat0, tx_alarm_status;
 808         int err;
 809         u64 val;
 810
 811         val = nr64_mac(XMAC_CONFIG);
 812         val &= ~XMAC_CONFIG_LED_POLARITY;
 813         val |= XMAC_CONFIG_FORCE_LED_ON;
 814         nw64_mac(XMAC_CONFIG, val);
 815
 816         /* XXX shared resource, lock parent XXX */
 817         val = nr64(MIF_CONFIG);
 818         val |= MIF_CONFIG_INDIRECT_MODE;
 819         nw64(MIF_CONFIG, val);
 820
 821         err = bcm8704_reset(np);
 822         if (err)
 823                 return err;
 824
 825         err = bcm8704_init_user_dev3(np);
 826         if (err)
 827                 return err;
 828
 829         err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
 830                         MII_BMCR);
 831         if (err < 0)
 832                 return err;
 833         err &= ~BMCR_LOOPBACK;
 834
 835         if (lp->loopback_mode == LOOPBACK_MAC)
 836                 err |= BMCR_LOOPBACK;
 837
 838         err = mdio_write(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
 839                          MII_BMCR, err);
 840         if (err)
 841                 return err;
 842
 843 #if 1
 844         err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
 845                         MII_STAT1000);
 846         if (err < 0)
 847                 return err;
 848         pr_info(PFX "Port %u PMA_PMD(MII_STAT1000) [%04x]\n",
 849                 np->port, err);
 850
 851         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, 0x20);
 852         if (err < 0)
 853                 return err;
 854         pr_info(PFX "Port %u USER_DEV3(0x20) [%04x]\n",
 855                 np->port, err);
 856
 857         err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
 858                         MII_NWAYTEST);
 859         if (err < 0)
 860                 return err;
 861         pr_info(PFX "Port %u PHYXS(MII_NWAYTEST) [%04x]\n",
 862                 np->port, err);
 863 #endif
 864
 865         /* XXX dig this out it might not be so useful XXX */
 866         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
 867                         BCM8704_USER_ANALOG_STATUS0);
 868         if (err < 0)
 869                 return err;
 870         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
 871                         BCM8704_USER_ANALOG_STATUS0);
 872         if (err < 0)
 873                 return err;
 874         analog_stat0 = err;
 875
 876         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
 877                         BCM8704_USER_TX_ALARM_STATUS);
 878         if (err < 0)
 879                 return err;
 880         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
 881                         BCM8704_USER_TX_ALARM_STATUS);
 882         if (err < 0)
 883                 return err;
 884         tx_alarm_status = err;
 885
 886         if (analog_stat0 != 0x03fc) {
 887                 if ((analog_stat0 == 0x43bc) && (tx_alarm_status != 0)) {
 888                         pr_info(PFX "Port %u cable not connected "
 889                                 "or bad cable.\n", np->port);
 890                 } else if (analog_stat0 == 0x639c) {
 891                         pr_info(PFX "Port %u optical module is bad "
 892                                 "or missing.\n", np->port);
 893                 }
 894         }
 895
 896         return 0;
 897 }
 898
 899 static int mii_reset(struct niu *np)
 900 {
 901         int limit, err;
 902
 903         err = mii_write(np, np->phy_addr, MII_BMCR, BMCR_RESET);
 904         if (err)
 905                 return err;
 906
 907         limit = 1000;
 908         while (--limit >= 0) {
 909                 udelay(500);
 910                 err = mii_read(np, np->phy_addr, MII_BMCR);
 911                 if (err < 0)
 912                         return err;
 913                 if (!(err & BMCR_RESET))
 914                         break;
 915         }
 916         if (limit < 0) {
 917                 dev_err(np->device, PFX "Port %u MII would not reset, "
 918                         "bmcr[%04x]\n", np->port, err);
 919                 return -ENODEV;
 920         }
 921
 922         return 0;
 923 }
 924
 925 static int mii_init_common(struct niu *np)
 926 {
 927         struct niu_link_config *lp = &np->link_config;
 928         u16 bmcr, bmsr, adv, estat;
 929         int err;
 930
 931         err = mii_reset(np);
 932         if (err)
 933                 return err;
 934
 935         err = mii_read(np, np->phy_addr, MII_BMSR);
 936         if (err < 0)
 937                 return err;
 938         bmsr = err;
 939
 940         estat = 0;
 941         if (bmsr & BMSR_ESTATEN) {
 942                 err = mii_read(np, np->phy_addr, MII_ESTATUS);
 943                 if (err < 0)
 944                         return err;
 945                 estat = err;
 946         }
 947
 948         bmcr = 0;
 949         err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
 950         if (err)
 951                 return err;
 952
 953         if (lp->loopback_mode == LOOPBACK_MAC) {
 954                 bmcr |= BMCR_LOOPBACK;
 955                 if (lp->active_speed == SPEED_1000)
 956                         bmcr |= BMCR_SPEED1000;
 957                 if (lp->active_duplex == DUPLEX_FULL)
 958                         bmcr |= BMCR_FULLDPLX;
 959         }
 960
 961         if (lp->loopback_mode == LOOPBACK_PHY) {
 962                 u16 aux;
 963
 964                 aux = (BCM5464R_AUX_CTL_EXT_LB |
 965                        BCM5464R_AUX_CTL_WRITE_1);
 966                 err = mii_write(np, np->phy_addr, BCM5464R_AUX_CTL, aux);
 967                 if (err)
 968                         return err;
 969         }
 970
 971         /* XXX configurable XXX */
 972         /* XXX for now don't advertise half-duplex or asym pause... XXX */
 973         adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
 974         if (bmsr & BMSR_10FULL)
 975                 adv |= ADVERTISE_10FULL;
 976         if (bmsr & BMSR_100FULL)
 977                 adv |= ADVERTISE_100FULL;
 978         err = mii_write(np, np->phy_addr, MII_ADVERTISE, adv);
 979         if (err)
 980                 return err;
 981
 982         if (bmsr & BMSR_ESTATEN) {
 983                 u16 ctrl1000 = 0;
 984
 985                 if (estat & ESTATUS_1000_TFULL)
 986                         ctrl1000 |= ADVERTISE_1000FULL;
 987                 err = mii_write(np, np->phy_addr, MII_CTRL1000, ctrl1000);
 988                 if (err)
 989                         return err;
 990         }
 991         bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
 992
 993         err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
 994         if (err)
 995                 return err;
 996
 997         err = mii_read(np, np->phy_addr, MII_BMCR);
 998         if (err < 0)
 999                 return err;
1000         err = mii_read(np, np->phy_addr, MII_BMSR);
1001         if (err < 0)
1002                 return err;
1003 #if 0
1004         pr_info(PFX "Port %u after MII init bmcr[%04x] bmsr[%04x]\n",
1005                 np->port, bmcr, bmsr);
1006 #endif
1007
1008         return 0;
1009 }
1010
1011 static int xcvr_init_1g(struct niu *np)
1012 {
1013         u64 val;
1014
1015         /* XXX shared resource, lock parent XXX */
1016         val = nr64(MIF_CONFIG);
1017         val &= ~MIF_CONFIG_INDIRECT_MODE;
1018         nw64(MIF_CONFIG, val);
1019
1020         return mii_init_common(np);
1021 }
1022
1023 static int niu_xcvr_init(struct niu *np)
1024 {
1025         const struct niu_phy_ops *ops = np->phy_ops;
1026         int err;
1027
1028         err = 0;
1029         if (ops->xcvr_init)
1030                 err = ops->xcvr_init(np);
1031
1032         return err;
1033 }
1034
1035 static int niu_serdes_init(struct niu *np)
1036 {
1037         const struct niu_phy_ops *ops = np->phy_ops;
1038         int err;
1039
1040         err = 0;
1041         if (ops->serdes_init)
1042                 err = ops->serdes_init(np);
1043
1044         return err;
1045 }
1046
1047 static void niu_init_xif(struct niu *);
1048 static void niu_handle_led(struct niu *, int status);
1049
1050 static int niu_link_status_common(struct niu *np, int link_up)
1051 {
1052         struct niu_link_config *lp = &np->link_config;
1053         struct net_device *dev = np->dev;
1054         unsigned long flags;
1055
1056         if (!netif_carrier_ok(dev) && link_up) {
1057                 niuinfo(LINK, "%s: Link is up at %s, %s duplex\n",
1058                        dev->name,
1059                        (lp->active_speed == SPEED_10000 ?
1060                         "10Gb/sec" :
1061                         (lp->active_speed == SPEED_1000 ?
1062                          "1Gb/sec" :
1063                          (lp->active_speed == SPEED_100 ?
1064                           "100Mbit/sec" : "10Mbit/sec"))),
1065                        (lp->active_duplex == DUPLEX_FULL ?
1066                         "full" : "half"));
1067
1068                 spin_lock_irqsave(&np->lock, flags);
1069                 niu_init_xif(np);
1070                 niu_handle_led(np, 1);
1071                 spin_unlock_irqrestore(&np->lock, flags);
1072
1073                 netif_carrier_on(dev);
1074         } else if (netif_carrier_ok(dev) && !link_up) {
1075                 niuwarn(LINK, "%s: Link is down\n", dev->name);
1076                 spin_lock_irqsave(&np->lock, flags);
1077                 niu_handle_led(np, 0);
1078                 spin_unlock_irqrestore(&np->lock, flags);
1079                 netif_carrier_off(dev);
1080         }
1081
1082         return 0;
1083 }
1084
1085 static int link_status_10g(struct niu *np, int *link_up_p)
1086 {
1087         unsigned long flags;
1088         int err, link_up;
1089
1090         link_up = 0;
1091
1092         spin_lock_irqsave(&np->lock, flags);
1093
1094         err = -EINVAL;
1095         if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
1096                 goto out;
1097
1098         err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
1099                         BCM8704_PMD_RCV_SIGDET);
1100         if (err < 0)
1101                 goto out;
1102         if (!(err & PMD_RCV_SIGDET_GLOBAL)) {
1103                 err = 0;
1104                 goto out;
1105         }
1106
1107         err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
1108                         BCM8704_PCS_10G_R_STATUS);
1109         if (err < 0)
1110                 goto out;
1111         if (!(err & PCS_10G_R_STATUS_BLK_LOCK)) {
1112                 err = 0;
1113                 goto out;
1114         }
1115
1116         err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
1117                         BCM8704_PHYXS_XGXS_LANE_STAT);
1118         if (err < 0)
1119                 goto out;
1120
1121         if (err != (PHYXS_XGXS_LANE_STAT_ALINGED |
1122                     PHYXS_XGXS_LANE_STAT_MAGIC |
1123                     PHYXS_XGXS_LANE_STAT_LANE3 |
1124                     PHYXS_XGXS_LANE_STAT_LANE2 |
1125                     PHYXS_XGXS_LANE_STAT_LANE1 |
1126                     PHYXS_XGXS_LANE_STAT_LANE0)) {
1127                 err = 0;
1128                 goto out;
1129         }
1130
1131         link_up = 1;
1132         np->link_config.active_speed = SPEED_10000;
1133         np->link_config.active_duplex = DUPLEX_FULL;
1134         err = 0;
1135
1136 out:
1137         spin_unlock_irqrestore(&np->lock, flags);
1138
1139         *link_up_p = link_up;
1140         return err;
1141 }
1142
1143 static int link_status_1g(struct niu *np, int *link_up_p)
1144 {
1145         u16 current_speed, bmsr;
1146         unsigned long flags;
1147         u8 current_duplex;
1148         int err, link_up;
1149
1150         link_up = 0;
1151         current_speed = SPEED_INVALID;
1152         current_duplex = DUPLEX_INVALID;
1153
1154         spin_lock_irqsave(&np->lock, flags);
1155
1156         err = -EINVAL;
1157         if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
1158                 goto out;
1159
1160         err = mii_read(np, np->phy_addr, MII_BMSR);
1161         if (err < 0)
1162                 goto out;
1163
1164         bmsr = err;
1165         if (bmsr & BMSR_LSTATUS) {
1166                 u16 adv, lpa, common, estat;
1167
1168                 err = mii_read(np, np->phy_addr, MII_ADVERTISE);
1169                 if (err < 0)
1170                         goto out;
1171                 adv = err;
1172
1173                 err = mii_read(np, np->phy_addr, MII_LPA);
1174                 if (err < 0)
1175                         goto out;
1176                 lpa = err;
1177
1178                 common = adv & lpa;
1179
1180                 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1181                 if (err < 0)
1182                         goto out;
1183                 estat = err;
1184
1185                 link_up = 1;
1186                 if (estat & (ESTATUS_1000_TFULL | ESTATUS_1000_THALF)) {
1187                         current_speed = SPEED_1000;
1188                         if (estat & ESTATUS_1000_TFULL)
1189                                 current_duplex = DUPLEX_FULL;
1190                         else
1191                                 current_duplex = DUPLEX_HALF;
1192                 } else {
1193                         if (common & ADVERTISE_100BASE4) {
1194                                 current_speed = SPEED_100;
1195                                 current_duplex = DUPLEX_HALF;
1196                         } else if (common & ADVERTISE_100FULL) {
1197                                 current_speed = SPEED_100;
1198                                 current_duplex = DUPLEX_FULL;
1199                         } else if (common & ADVERTISE_100HALF) {
1200                                 current_speed = SPEED_100;
1201                                 current_duplex = DUPLEX_HALF;
1202                         } else if (common & ADVERTISE_10FULL) {
1203                                 current_speed = SPEED_10;
1204                                 current_duplex = DUPLEX_FULL;
1205                         } else if (common & ADVERTISE_10HALF) {
1206                                 current_speed = SPEED_10;
1207                                 current_duplex = DUPLEX_HALF;
1208                         } else
1209                                 link_up = 0;
1210                 }
1211         }
1212         err = 0;
1213
1214 out:
1215         spin_unlock_irqrestore(&np->lock, flags);
1216
1217         *link_up_p = link_up;
1218         return err;
1219 }
1220
1221 static int niu_link_status(struct niu *np, int *link_up_p)
1222 {
1223         const struct niu_phy_ops *ops = np->phy_ops;
1224         int err;
1225
1226         err = 0;
1227         if (ops->link_status)
1228                 err = ops->link_status(np, link_up_p);
1229
1230         return err;
1231 }
1232
1233 static void niu_timer(unsigned long __opaque)
1234 {
1235         struct niu *np = (struct niu *) __opaque;
1236         unsigned long off;
1237         int err, link_up;
1238
1239         err = niu_link_status(np, &link_up);
1240         if (!err)
1241                 niu_link_status_common(np, link_up);
1242
1243         if (netif_carrier_ok(np->dev))
1244                 off = 5 * HZ;
1245         else
1246                 off = 1 * HZ;
1247         np->timer.expires = jiffies + off;
1248
1249         add_timer(&np->timer);
1250 }
1251
1252 static const struct niu_phy_ops phy_ops_10g_fiber_niu = {
1253         .serdes_init            = serdes_init_niu,
1254         .xcvr_init              = xcvr_init_10g,
1255         .link_status            = link_status_10g,
1256 };
1257
1258 static const struct niu_phy_ops phy_ops_10g_fiber = {
1259         .serdes_init            = serdes_init_10g,
1260         .xcvr_init              = xcvr_init_10g,
1261         .link_status            = link_status_10g,
1262 };
1263
1264 static const struct niu_phy_ops phy_ops_10g_copper = {
1265         .serdes_init            = serdes_init_10g,
1266         .link_status            = link_status_10g, /* XXX */
1267 };
1268
1269 static const struct niu_phy_ops phy_ops_1g_fiber = {
1270         .serdes_init            = serdes_init_1g,
1271         .xcvr_init              = xcvr_init_1g,
1272         .link_status            = link_status_1g,
1273 };
1274
1275 static const struct niu_phy_ops phy_ops_1g_copper = {
1276         .xcvr_init              = xcvr_init_1g,
1277         .link_status            = link_status_1g,
1278 };
1279
1280 struct niu_phy_template {
1281         const struct niu_phy_ops        *ops;
1282         u32                             phy_addr_base;
1283 };
1284
1285 static const struct niu_phy_template phy_template_niu = {
1286         .ops            = &phy_ops_10g_fiber_niu,
1287         .phy_addr_base  = 16,
1288 };
1289
1290 static const struct niu_phy_template phy_template_10g_fiber = {
1291         .ops            = &phy_ops_10g_fiber,
1292         .phy_addr_base  = 8,
1293 };
1294
1295 static const struct niu_phy_template phy_template_10g_copper = {
1296         .ops            = &phy_ops_10g_copper,
1297         .phy_addr_base  = 10,
1298 };
1299
1300 static const struct niu_phy_template phy_template_1g_fiber = {
1301         .ops            = &phy_ops_1g_fiber,
1302         .phy_addr_base  = 0,
1303 };
1304
1305 static const struct niu_phy_template phy_template_1g_copper = {
1306         .ops            = &phy_ops_1g_copper,
1307         .phy_addr_base  = 0,
1308 };
1309
1310 static int niu_determine_phy_disposition(struct niu *np)
1311 {
1312         struct niu_parent *parent = np->parent;
1313         u8 plat_type = parent->plat_type;
1314         const struct niu_phy_template *tp;
1315         u32 phy_addr_off = 0;
1316
1317         if (plat_type == PLAT_TYPE_NIU) {
1318                 tp = &phy_template_niu;
1319                 phy_addr_off += np->port;
1320         } else {
1321                 switch (np->flags & (NIU_FLAGS_10G | NIU_FLAGS_FIBER)) {
1322                 case 0:
1323                         /* 1G copper */
1324                         tp = &phy_template_1g_copper;
1325                         if (plat_type == PLAT_TYPE_VF_P0)
1326                                 phy_addr_off = 10;
1327                         else if (plat_type == PLAT_TYPE_VF_P1)
1328                                 phy_addr_off = 26;
1329
1330                         phy_addr_off += (np->port ^ 0x3);
1331                         break;
1332
1333                 case NIU_FLAGS_10G:
1334                         /* 10G copper */
1335                         tp = &phy_template_1g_copper;
1336                         break;
1337
1338                 case NIU_FLAGS_FIBER:
1339                         /* 1G fiber */
1340                         tp = &phy_template_1g_fiber;
1341                         break;
1342
1343                 case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
1344                         /* 10G fiber */
1345                         tp = &phy_template_10g_fiber;
1346                         if (plat_type == PLAT_TYPE_VF_P0 ||
1347                             plat_type == PLAT_TYPE_VF_P1)
1348                                 phy_addr_off = 8;
1349                         phy_addr_off += np->port;
1350                         break;
1351
1352                 default:
1353                         return -EINVAL;
1354                 }
1355         }
1356
1357         np->phy_ops = tp->ops;
1358         np->phy_addr = tp->phy_addr_base + phy_addr_off;
1359
1360         return 0;
1361 }
1362
1363 static int niu_init_link(struct niu *np)
1364 {
1365         struct niu_parent *parent = np->parent;
1366         int err, ignore;
1367
1368         if (parent->plat_type == PLAT_TYPE_NIU) {
1369                 err = niu_xcvr_init(np);
1370                 if (err)
1371                         return err;
1372                 msleep(200);
1373         }
1374         err = niu_serdes_init(np);
1375         if (err)
1376                 return err;
1377         msleep(200);
1378         err = niu_xcvr_init(np);
1379         if (!err)
1380                 niu_link_status(np, &ignore);
1381         return 0;
1382 }
1383
1384 static void niu_set_primary_mac(struct niu *np, unsigned char *addr)
1385 {
1386         u16 reg0 = addr[4] << 8 | addr[5];
1387         u16 reg1 = addr[2] << 8 | addr[3];
1388         u16 reg2 = addr[0] << 8 | addr[1];
1389
1390         if (np->flags & NIU_FLAGS_XMAC) {
1391                 nw64_mac(XMAC_ADDR0, reg0);
1392                 nw64_mac(XMAC_ADDR1, reg1);
1393                 nw64_mac(XMAC_ADDR2, reg2);
1394         } else {
1395                 nw64_mac(BMAC_ADDR0, reg0);
1396                 nw64_mac(BMAC_ADDR1, reg1);
1397                 nw64_mac(BMAC_ADDR2, reg2);
1398         }
1399 }
1400
1401 static int niu_num_alt_addr(struct niu *np)
1402 {
1403         if (np->flags & NIU_FLAGS_XMAC)
1404                 return XMAC_NUM_ALT_ADDR;
1405         else
1406                 return BMAC_NUM_ALT_ADDR;
1407 }
1408
1409 static int niu_set_alt_mac(struct niu *np, int index, unsigned char *addr)
1410 {
1411         u16 reg0 = addr[4] << 8 | addr[5];
1412         u16 reg1 = addr[2] << 8 | addr[3];
1413         u16 reg2 = addr[0] << 8 | addr[1];
1414
1415         if (index >= niu_num_alt_addr(np))
1416                 return -EINVAL;
1417
1418         if (np->flags & NIU_FLAGS_XMAC) {
1419                 nw64_mac(XMAC_ALT_ADDR0(index), reg0);
1420                 nw64_mac(XMAC_ALT_ADDR1(index), reg1);
1421                 nw64_mac(XMAC_ALT_ADDR2(index), reg2);
1422         } else {
1423                 nw64_mac(BMAC_ALT_ADDR0(index), reg0);
1424                 nw64_mac(BMAC_ALT_ADDR1(index), reg1);
1425                 nw64_mac(BMAC_ALT_ADDR2(index), reg2);
1426         }
1427
1428         return 0;
1429 }
1430
1431 static int niu_enable_alt_mac(struct niu *np, int index, int on)
1432 {
1433         unsigned long reg;
1434         u64 val, mask;
1435
1436         if (index >= niu_num_alt_addr(np))
1437                 return -EINVAL;
1438
1439         if (np->flags & NIU_FLAGS_XMAC)
1440                 reg = XMAC_ADDR_CMPEN;
1441         else
1442                 reg = BMAC_ADDR_CMPEN;
1443
1444         mask = 1 << index;
1445
1446         val = nr64_mac(reg);
1447         if (on)
1448                 val |= mask;
1449         else
1450                 val &= ~mask;
1451         nw64_mac(reg, val);
1452
1453         return 0;
1454 }
1455
1456 static void __set_rdc_table_num_hw(struct niu *np, unsigned long reg,
1457                                    int num, int mac_pref)
1458 {
1459         u64 val = nr64_mac(reg);
1460         val &= ~(HOST_INFO_MACRDCTBLN | HOST_INFO_MPR);
1461         val |= num;
1462         if (mac_pref)
1463                 val |= HOST_INFO_MPR;
1464         nw64_mac(reg, val);
1465 }
1466
1467 static int __set_rdc_table_num(struct niu *np,
1468                                int xmac_index, int bmac_index,
1469                                int rdc_table_num, int mac_pref)
1470 {
1471         unsigned long reg;
1472
1473         if (rdc_table_num & ~HOST_INFO_MACRDCTBLN)
1474                 return -EINVAL;
1475         if (np->flags & NIU_FLAGS_XMAC)
1476                 reg = XMAC_HOST_INFO(xmac_index);
1477         else
1478                 reg = BMAC_HOST_INFO(bmac_index);
1479         __set_rdc_table_num_hw(np, reg, rdc_table_num, mac_pref);
1480         return 0;
1481 }
1482
1483 static int niu_set_primary_mac_rdc_table(struct niu *np, int table_num,
1484                                          int mac_pref)
1485 {
1486         return __set_rdc_table_num(np, 17, 0, table_num, mac_pref);
1487 }
1488
1489 static int niu_set_multicast_mac_rdc_table(struct niu *np, int table_num,
1490                                            int mac_pref)
1491 {
1492         return __set_rdc_table_num(np, 16, 8, table_num, mac_pref);
1493 }
1494
1495 static int niu_set_alt_mac_rdc_table(struct niu *np, int idx,
1496                                      int table_num, int mac_pref)
1497 {
1498         if (idx >= niu_num_alt_addr(np))
1499                 return -EINVAL;
1500         return __set_rdc_table_num(np, idx, idx + 1, table_num, mac_pref);
1501 }
1502
1503 static u64 vlan_entry_set_parity(u64 reg_val)
1504 {
1505         u64 port01_mask;
1506         u64 port23_mask;
1507
1508         port01_mask = 0x00ff;
1509         port23_mask = 0xff00;
1510
1511         if (hweight64(reg_val & port01_mask) & 1)
1512                 reg_val |= ENET_VLAN_TBL_PARITY0;
1513         else
1514                 reg_val &= ~ENET_VLAN_TBL_PARITY0;
1515
1516         if (hweight64(reg_val & port23_mask) & 1)
1517                 reg_val |= ENET_VLAN_TBL_PARITY1;
1518         else
1519                 reg_val &= ~ENET_VLAN_TBL_PARITY1;
1520
1521         return reg_val;
1522 }
1523
1524 static void vlan_tbl_write(struct niu *np, unsigned long index,
1525                            int port, int vpr, int rdc_table)
1526 {
1527         u64 reg_val = nr64(ENET_VLAN_TBL(index));
1528
1529         reg_val &= ~((ENET_VLAN_TBL_VPR |
1530                       ENET_VLAN_TBL_VLANRDCTBLN) <<
1531                      ENET_VLAN_TBL_SHIFT(port));
1532         if (vpr)
1533                 reg_val |= (ENET_VLAN_TBL_VPR <<
1534                             ENET_VLAN_TBL_SHIFT(port));
1535         reg_val |= (rdc_table << ENET_VLAN_TBL_SHIFT(port));
1536
1537         reg_val = vlan_entry_set_parity(reg_val);
1538
1539         nw64(ENET_VLAN_TBL(index), reg_val);
1540 }
1541
1542 static void vlan_tbl_clear(struct niu *np)
1543 {
1544         int i;
1545
1546         for (i = 0; i < ENET_VLAN_TBL_NUM_ENTRIES; i++)
1547                 nw64(ENET_VLAN_TBL(i), 0);
1548 }
1549
1550 static int tcam_wait_bit(struct niu *np, u64 bit)
1551 {
1552         int limit = 1000;
1553
1554         while (--limit > 0) {
1555                 if (nr64(TCAM_CTL) & bit)
1556                         break;
1557                 udelay(1);
1558         }
1559         if (limit < 0)
1560                 return -ENODEV;
1561
1562         return 0;
1563 }
1564
1565 static int tcam_flush(struct niu *np, int index)
1566 {
1567         nw64(TCAM_KEY_0, 0x00);
1568         nw64(TCAM_KEY_MASK_0, 0xff);
1569         nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index));
1570
1571         return tcam_wait_bit(np, TCAM_CTL_STAT);
1572 }
1573
1574 #if 0
1575 static int tcam_read(struct niu *np, int index,
1576                      u64 *key, u64 *mask)
1577 {
1578         int err;
1579
1580         nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_READ | index));
1581         err = tcam_wait_bit(np, TCAM_CTL_STAT);
1582         if (!err) {
1583                 key[0] = nr64(TCAM_KEY_0);
1584                 key[1] = nr64(TCAM_KEY_1);
1585                 key[2] = nr64(TCAM_KEY_2);
1586                 key[3] = nr64(TCAM_KEY_3);
1587                 mask[0] = nr64(TCAM_KEY_MASK_0);
1588                 mask[1] = nr64(TCAM_KEY_MASK_1);
1589                 mask[2] = nr64(TCAM_KEY_MASK_2);
1590                 mask[3] = nr64(TCAM_KEY_MASK_3);
1591         }
1592         return err;
1593 }
1594 #endif
1595
1596 static int tcam_write(struct niu *np, int index,
1597                       u64 *key, u64 *mask)
1598 {
1599         nw64(TCAM_KEY_0, key[0]);
1600         nw64(TCAM_KEY_1, key[1]);
1601         nw64(TCAM_KEY_2, key[2]);
1602         nw64(TCAM_KEY_3, key[3]);
1603         nw64(TCAM_KEY_MASK_0, mask[0]);
1604         nw64(TCAM_KEY_MASK_1, mask[1]);
1605         nw64(TCAM_KEY_MASK_2, mask[2]);
1606         nw64(TCAM_KEY_MASK_3, mask[3]);
1607         nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index));
1608
1609         return tcam_wait_bit(np, TCAM_CTL_STAT);
1610 }
1611
1612 #if 0
1613 static int tcam_assoc_read(struct niu *np, int index, u64 *data)
1614 {
1615         int err;
1616
1617         nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_READ | index));
1618         err = tcam_wait_bit(np, TCAM_CTL_STAT);
1619         if (!err)
1620                 *data = nr64(TCAM_KEY_1);
1621
1622         return err;
1623 }
1624 #endif
1625
1626 static int tcam_assoc_write(struct niu *np, int index, u64 assoc_data)
1627 {
1628         nw64(TCAM_KEY_1, assoc_data);
1629         nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_WRITE | index));
1630
1631         return tcam_wait_bit(np, TCAM_CTL_STAT);
1632 }
1633
1634 static void tcam_enable(struct niu *np, int on)
1635 {
1636         u64 val = nr64(FFLP_CFG_1);
1637
1638         if (on)
1639                 val &= ~FFLP_CFG_1_TCAM_DIS;
1640         else
1641                 val |= FFLP_CFG_1_TCAM_DIS;
1642         nw64(FFLP_CFG_1, val);
1643 }
1644
1645 static void tcam_set_lat_and_ratio(struct niu *np, u64 latency, u64 ratio)
1646 {
1647         u64 val = nr64(FFLP_CFG_1);
1648
1649         val &= ~(FFLP_CFG_1_FFLPINITDONE |
1650                  FFLP_CFG_1_CAMLAT |
1651                  FFLP_CFG_1_CAMRATIO);
1652         val |= (latency << FFLP_CFG_1_CAMLAT_SHIFT);
1653         val |= (ratio << FFLP_CFG_1_CAMRATIO_SHIFT);
1654         nw64(FFLP_CFG_1, val);
1655
1656         val = nr64(FFLP_CFG_1);
1657         val |= FFLP_CFG_1_FFLPINITDONE;
1658         nw64(FFLP_CFG_1, val);
1659 }
1660
1661 static int tcam_user_eth_class_enable(struct niu *np, unsigned long class,
1662                                       int on)
1663 {
1664         unsigned long reg;
1665         u64 val;
1666
1667         if (class < CLASS_CODE_ETHERTYPE1 ||
1668             class > CLASS_CODE_ETHERTYPE2)
1669                 return -EINVAL;
1670
1671         reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1);
1672         val = nr64(reg);
1673         if (on)
1674                 val |= L2_CLS_VLD;
1675         else
1676                 val &= ~L2_CLS_VLD;
1677         nw64(reg, val);
1678
1679         return 0;
1680 }
1681
1682 #if 0
1683 static int tcam_user_eth_class_set(struct niu *np, unsigned long class,
1684                                    u64 ether_type)
1685 {
1686         unsigned long reg;
1687         u64 val;
1688
1689         if (class < CLASS_CODE_ETHERTYPE1 ||
1690             class > CLASS_CODE_ETHERTYPE2 ||
1691             (ether_type & ~(u64)0xffff) != 0)
1692                 return -EINVAL;
1693
1694         reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1);
1695         val = nr64(reg);
1696         val &= ~L2_CLS_ETYPE;
1697         val |= (ether_type << L2_CLS_ETYPE_SHIFT);
1698         nw64(reg, val);
1699
1700         return 0;
1701 }
1702 #endif
1703
1704 static int tcam_user_ip_class_enable(struct niu *np, unsigned long class,
1705                                      int on)
1706 {
1707         unsigned long reg;
1708         u64 val;
1709
1710         if (class < CLASS_CODE_USER_PROG1 ||
1711             class > CLASS_CODE_USER_PROG4)
1712                 return -EINVAL;
1713
1714         reg = L3_CLS(class - CLASS_CODE_USER_PROG1);
1715         val = nr64(reg);
1716         if (on)
1717                 val |= L3_CLS_VALID;
1718         else
1719                 val &= ~L3_CLS_VALID;
1720         nw64(reg, val);
1721
1722         return 0;
1723 }
1724
1725 #if 0
1726 static int tcam_user_ip_class_set(struct niu *np, unsigned long class,
1727                                   int ipv6, u64 protocol_id,
1728                                   u64 tos_mask, u64 tos_val)
1729 {
1730         unsigned long reg;
1731         u64 val;
1732
1733         if (class < CLASS_CODE_USER_PROG1 ||
1734             class > CLASS_CODE_USER_PROG4 ||
1735             (protocol_id & ~(u64)0xff) != 0 ||
1736             (tos_mask & ~(u64)0xff) != 0 ||
1737             (tos_val & ~(u64)0xff) != 0)
1738                 return -EINVAL;
1739
1740         reg = L3_CLS(class - CLASS_CODE_USER_PROG1);
1741         val = nr64(reg);
1742         val &= ~(L3_CLS_IPVER | L3_CLS_PID |
1743                  L3_CLS_TOSMASK | L3_CLS_TOS);
1744         if (ipv6)
1745                 val |= L3_CLS_IPVER;
1746         val |= (protocol_id << L3_CLS_PID_SHIFT);
1747         val |= (tos_mask << L3_CLS_TOSMASK_SHIFT);
1748         val |= (tos_val << L3_CLS_TOS_SHIFT);
1749         nw64(reg, val);
1750
1751         return 0;
1752 }
1753 #endif
1754
1755 static int tcam_early_init(struct niu *np)
1756 {
1757         unsigned long i;
1758         int err;
1759
1760         tcam_enable(np, 0);
1761         tcam_set_lat_and_ratio(np,
1762                                DEFAULT_TCAM_LATENCY,
1763                                DEFAULT_TCAM_ACCESS_RATIO);
1764         for (i = CLASS_CODE_ETHERTYPE1; i <= CLASS_CODE_ETHERTYPE2; i++) {
1765                 err = tcam_user_eth_class_enable(np, i, 0);
1766                 if (err)
1767                         return err;
1768         }
1769         for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_USER_PROG4; i++) {
1770                 err = tcam_user_ip_class_enable(np, i, 0);
1771                 if (err)
1772                         return err;
1773         }
1774
1775         return 0;
1776 }
1777
1778 static int tcam_flush_all(struct niu *np)
1779 {
1780         unsigned long i;
1781
1782         for (i = 0; i < np->parent->tcam_num_entries; i++) {
1783                 int err = tcam_flush(np, i);
1784                 if (err)
1785                         return err;
1786         }
1787         return 0;
1788 }
1789
1790 static u64 hash_addr_regval(unsigned long index, unsigned long num_entries)
1791 {
1792         return ((u64)index | (num_entries == 1 ?
1793                               HASH_TBL_ADDR_AUTOINC : 0));
1794 }
1795
1796 #if 0
1797 static int hash_read(struct niu *np, unsigned long partition,
1798                      unsigned long index, unsigned long num_entries,
1799                      u64 *data)
1800 {
1801         u64 val = hash_addr_regval(index, num_entries);
1802         unsigned long i;
1803
1804         if (partition >= FCRAM_NUM_PARTITIONS ||
1805             index + num_entries > FCRAM_SIZE)
1806                 return -EINVAL;
1807
1808         nw64(HASH_TBL_ADDR(partition), val);
1809         for (i = 0; i < num_entries; i++)
1810                 data[i] = nr64(HASH_TBL_DATA(partition));
1811
1812         return 0;
1813 }
1814 #endif
1815
1816 static int hash_write(struct niu *np, unsigned long partition,
1817                       unsigned long index, unsigned long num_entries,
1818                       u64 *data)
1819 {
1820         u64 val = hash_addr_regval(index, num_entries);
1821         unsigned long i;
1822
1823         if (partition >= FCRAM_NUM_PARTITIONS ||
1824             index + (num_entries * 8) > FCRAM_SIZE)
1825                 return -EINVAL;
1826
1827         nw64(HASH_TBL_ADDR(partition), val);
1828         for (i = 0; i < num_entries; i++)
1829                 nw64(HASH_TBL_DATA(partition), data[i]);
1830
1831         return 0;
1832 }
1833
1834 static void fflp_reset(struct niu *np)
1835 {
1836         u64 val;
1837
1838         nw64(FFLP_CFG_1, FFLP_CFG_1_PIO_FIO_RST);
1839         udelay(10);
1840         nw64(FFLP_CFG_1, 0);
1841
1842         val = FFLP_CFG_1_FCRAMOUTDR_NORMAL | FFLP_CFG_1_FFLPINITDONE;
1843         nw64(FFLP_CFG_1, val);
1844 }
1845
1846 static void fflp_set_timings(struct niu *np)
1847 {
1848         u64 val = nr64(FFLP_CFG_1);
1849
1850         val &= ~FFLP_CFG_1_FFLPINITDONE;
1851         val |= (DEFAULT_FCRAMRATIO << FFLP_CFG_1_FCRAMRATIO_SHIFT);
1852         nw64(FFLP_CFG_1, val);
1853
1854         val = nr64(FFLP_CFG_1);
1855         val |= FFLP_CFG_1_FFLPINITDONE;
1856         nw64(FFLP_CFG_1, val);
1857
1858         val = nr64(FCRAM_REF_TMR);
1859         val &= ~(FCRAM_REF_TMR_MAX | FCRAM_REF_TMR_MIN);
1860         val |= (DEFAULT_FCRAM_REFRESH_MAX << FCRAM_REF_TMR_MAX_SHIFT);
1861         val |= (DEFAULT_FCRAM_REFRESH_MIN << FCRAM_REF_TMR_MIN_SHIFT);
1862         nw64(FCRAM_REF_TMR, val);
1863 }
1864
1865 static int fflp_set_partition(struct niu *np, u64 partition,
1866                               u64 mask, u64 base, int enable)
1867 {
1868         unsigned long reg;
1869         u64 val;
1870
1871         if (partition >= FCRAM_NUM_PARTITIONS ||
1872             (mask & ~(u64)0x1f) != 0 ||
1873             (base & ~(u64)0x1f) != 0)
1874                 return -EINVAL;
1875
1876         reg = FLW_PRT_SEL(partition);
1877
1878         val = nr64(reg);
1879         val &= ~(FLW_PRT_SEL_EXT | FLW_PRT_SEL_MASK | FLW_PRT_SEL_BASE);
1880         val |= (mask << FLW_PRT_SEL_MASK_SHIFT);
1881         val |= (base << FLW_PRT_SEL_BASE_SHIFT);
1882         if (enable)
1883                 val |= FLW_PRT_SEL_EXT;
1884         nw64(reg, val);
1885
1886         return 0;
1887 }
1888
1889 static int fflp_disable_all_partitions(struct niu *np)
1890 {
1891         unsigned long i;
1892
1893         for (i = 0; i < FCRAM_NUM_PARTITIONS; i++) {
1894                 int err = fflp_set_partition(np, 0, 0, 0, 0);
1895                 if (err)
1896                         return err;
1897         }
1898         return 0;
1899 }
1900
1901 static void fflp_llcsnap_enable(struct niu *np, int on)
1902 {
1903         u64 val = nr64(FFLP_CFG_1);
1904
1905         if (on)
1906                 val |= FFLP_CFG_1_LLCSNAP;
1907         else
1908                 val &= ~FFLP_CFG_1_LLCSNAP;
1909         nw64(FFLP_CFG_1, val);
1910 }
1911
1912 static void fflp_errors_enable(struct niu *np, int on)
1913 {
1914         u64 val = nr64(FFLP_CFG_1);
1915
1916         if (on)
1917                 val &= ~FFLP_CFG_1_ERRORDIS;
1918         else
1919                 val |= FFLP_CFG_1_ERRORDIS;
1920         nw64(FFLP_CFG_1, val);
1921 }
1922
1923 static int fflp_hash_clear(struct niu *np)
1924 {
1925         struct fcram_hash_ipv4 ent;
1926         unsigned long i;
1927
1928         /* IPV4 hash entry with valid bit clear, rest is don't care.  */
1929         memset(&ent, 0, sizeof(ent));
1930         ent.header = HASH_HEADER_EXT;
1931
1932         for (i = 0; i < FCRAM_SIZE; i += sizeof(ent)) {
1933                 int err = hash_write(np, 0, i, 1, (u64 *) &ent);
1934                 if (err)
1935                         return err;
1936         }
1937         return 0;
1938 }
1939
1940 static int fflp_early_init(struct niu *np)
1941 {
1942         struct niu_parent *parent;
1943         unsigned long flags;
1944         int err;
1945
1946         niu_lock_parent(np, flags);
1947
1948         parent = np->parent;
1949         err = 0;
1950         if (!(parent->flags & PARENT_FLGS_CLS_HWINIT)) {
1951                 niudbg(PROBE, "fflp_early_init: Initting hw on port %u\n",
1952                        np->port);
1953                 if (np->parent->plat_type != PLAT_TYPE_NIU) {
1954                         fflp_reset(np);
1955                         fflp_set_timings(np);
1956                         err = fflp_disable_all_partitions(np);
1957                         if (err) {
1958                                 niudbg(PROBE, "fflp_disable_all_partitions "
1959                                        "failed, err=%d\n", err);
1960                                 goto out;
1961                         }
1962                 }
1963
1964                 err = tcam_early_init(np);
1965                 if (err) {
1966                         niudbg(PROBE, "tcam_early_init failed, err=%d\n",
1967                                err);
1968                         goto out;
1969                 }
1970                 fflp_llcsnap_enable(np, 1);
1971                 fflp_errors_enable(np, 0);
1972                 nw64(H1POLY, 0);
1973                 nw64(H2POLY, 0);
1974
1975                 err = tcam_flush_all(np);
1976                 if (err) {
1977                         niudbg(PROBE, "tcam_flush_all failed, err=%d\n",
1978                                err);
1979                         goto out;
1980                 }
1981                 if (np->parent->plat_type != PLAT_TYPE_NIU) {
1982                         err = fflp_hash_clear(np);
1983                         if (err) {
1984                                 niudbg(PROBE, "fflp_hash_clear failed, "
1985                                        "err=%d\n", err);
1986                                 goto out;
1987                         }
1988                 }
1989
1990                 vlan_tbl_clear(np);
1991
1992                 niudbg(PROBE, "fflp_early_init: Success\n");
1993                 parent->flags |= PARENT_FLGS_CLS_HWINIT;
1994         }
1995 out:
1996         niu_unlock_parent(np, flags);
1997         return err;
1998 }
1999
2000 static int niu_set_flow_key(struct niu *np, unsigned long class_code, u64 key)
2001 {
2002         if (class_code < CLASS_CODE_USER_PROG1 ||
2003             class_code > CLASS_CODE_SCTP_IPV6)
2004                 return -EINVAL;
2005
2006         nw64(FLOW_KEY(class_code - CLASS_CODE_USER_PROG1), key);
2007         return 0;
2008 }
2009
2010 static int niu_set_tcam_key(struct niu *np, unsigned long class_code, u64 key)
2011 {
2012         if (class_code < CLASS_CODE_USER_PROG1 ||
2013             class_code > CLASS_CODE_SCTP_IPV6)
2014                 return -EINVAL;
2015
2016         nw64(TCAM_KEY(class_code - CLASS_CODE_USER_PROG1), key);
2017         return 0;
2018 }
2019
2020 static void niu_rx_skb_append(struct sk_buff *skb, struct page *page,
2021                               u32 offset, u32 size)
2022 {
2023         int i = skb_shinfo(skb)->nr_frags;
2024         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2025
2026         frag->page = page;
2027         frag->page_offset = offset;
2028         frag->size = size;
2029
2030         skb->len += size;
2031         skb->data_len += size;
2032         skb->truesize += size;
2033
2034         skb_shinfo(skb)->nr_frags = i + 1;
2035 }
2036
2037 static unsigned int niu_hash_rxaddr(struct rx_ring_info *rp, u64 a)
2038 {
2039         a >>= PAGE_SHIFT;
2040         a ^= (a >> ilog2(MAX_RBR_RING_SIZE));
2041
2042         return (a & (MAX_RBR_RING_SIZE - 1));
2043 }
2044
2045 static struct page *niu_find_rxpage(struct rx_ring_info *rp, u64 addr,
2046                                     struct page ***link)
2047 {
2048         unsigned int h = niu_hash_rxaddr(rp, addr);
2049         struct page *p, **pp;
2050
2051         addr &= PAGE_MASK;
2052         pp = &rp->rxhash[h];
2053         for (; (p = *pp) != NULL; pp = (struct page **) &p->mapping) {
2054                 if (p->index == addr) {
2055                         *link = pp;
2056                         break;
2057                 }
2058         }
2059
2060         return p;
2061 }
2062
2063 static void niu_hash_page(struct rx_ring_info *rp, struct page *page, u64 base)
2064 {
2065         unsigned int h = niu_hash_rxaddr(rp, base);
2066
2067         page->index = base;
2068         page->mapping = (struct address_space *) rp->rxhash[h];
2069         rp->rxhash[h] = page;
2070 }
2071
2072 static int niu_rbr_add_page(struct niu *np, struct rx_ring_info *rp,
2073                             gfp_t mask, int start_index)
2074 {
2075         struct page *page;
2076         u64 addr;
2077         int i;
2078
2079         page = alloc_page(mask);
2080         if (!page)
2081                 return -ENOMEM;
2082
2083         addr = np->ops->map_page(np->device, page, 0,
2084                                  PAGE_SIZE, DMA_FROM_DEVICE);
2085
2086         niu_hash_page(rp, page, addr);
2087         if (rp->rbr_blocks_per_page > 1)
2088                 atomic_add(rp->rbr_blocks_per_page - 1,
2089                            &compound_head(page)->_count);
2090
2091         for (i = 0; i < rp->rbr_blocks_per_page; i++) {
2092                 __le32 *rbr = &rp->rbr[start_index + i];
2093
2094                 *rbr = cpu_to_le32(addr >> RBR_DESCR_ADDR_SHIFT);
2095                 addr += rp->rbr_block_size;
2096         }
2097
2098         return 0;
2099 }
2100
2101 static void niu_rbr_refill(struct niu *np, struct rx_ring_info *rp, gfp_t mask)
2102 {
2103         int index = rp->rbr_index;
2104
2105         rp->rbr_pending++;
2106         if ((rp->rbr_pending % rp->rbr_blocks_per_page) == 0) {
2107                 int err = niu_rbr_add_page(np, rp, mask, index);
2108
2109                 if (unlikely(err)) {
2110                         rp->rbr_pending--;
2111                         return;
2112                 }
2113
2114                 rp->rbr_index += rp->rbr_blocks_per_page;
2115                 BUG_ON(rp->rbr_index > rp->rbr_table_size);
2116                 if (rp->rbr_index == rp->rbr_table_size)
2117                         rp->rbr_index = 0;
2118
2119                 if (rp->rbr_pending >= rp->rbr_kick_thresh) {
2120                         nw64(RBR_KICK(rp->rx_channel), rp->rbr_pending);
2121                         rp->rbr_pending = 0;
2122                 }
2123         }
2124 }
2125
2126 static int niu_rx_pkt_ignore(struct niu *np, struct rx_ring_info *rp)
2127 {
2128         unsigned int index = rp->rcr_index;
2129         int num_rcr = 0;
2130
2131         rp->rx_dropped++;
2132         while (1) {
2133                 struct page *page, **link;
2134                 u64 addr, val;
2135                 u32 rcr_size;
2136
2137                 num_rcr++;
2138
2139                 val = le64_to_cpup(&rp->rcr[index]);
2140                 addr = (val & RCR_ENTRY_PKT_BUF_ADDR) <<
2141                         RCR_ENTRY_PKT_BUF_ADDR_SHIFT;
2142                 page = niu_find_rxpage(rp, addr, &link);
2143
2144                 rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >>
2145                                          RCR_ENTRY_PKTBUFSZ_SHIFT];
2146                 if ((page->index + PAGE_SIZE) - rcr_size == addr) {
2147                         *link = (struct page *) page->mapping;
2148                         np->ops->unmap_page(np->device, page->index,
2149                                             PAGE_SIZE, DMA_FROM_DEVICE);
2150                         page->index = 0;
2151                         page->mapping = NULL;
2152                         __free_page(page);
2153                         rp->rbr_refill_pending++;
2154                 }
2155
2156                 index = NEXT_RCR(rp, index);
2157                 if (!(val & RCR_ENTRY_MULTI))
2158                         break;
2159
2160         }
2161         rp->rcr_index = index;
2162
2163         return num_rcr;
2164 }
2165
2166 static int niu_process_rx_pkt(struct niu *np, struct rx_ring_info *rp)
2167 {
2168         unsigned int index = rp->rcr_index;
2169         struct sk_buff *skb;
2170         int len, num_rcr;
2171
2172         skb = netdev_alloc_skb(np->dev, RX_SKB_ALLOC_SIZE);
2173         if (unlikely(!skb))
2174                 return niu_rx_pkt_ignore(np, rp);
2175
2176         num_rcr = 0;
2177         while (1) {
2178                 struct page *page, **link;
2179                 u32 rcr_size, append_size;
2180                 u64 addr, val, off;
2181
2182                 num_rcr++;
2183
2184                 val = le64_to_cpup(&rp->rcr[index]);
2185
2186                 len = (val & RCR_ENTRY_L2_LEN) >>
2187                         RCR_ENTRY_L2_LEN_SHIFT;
2188                 len -= ETH_FCS_LEN;
2189
2190                 addr = (val & RCR_ENTRY_PKT_BUF_ADDR) <<
2191                         RCR_ENTRY_PKT_BUF_ADDR_SHIFT;
2192                 page = niu_find_rxpage(rp, addr, &link);
2193
2194                 rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >>
2195                                          RCR_ENTRY_PKTBUFSZ_SHIFT];
2196
2197                 off = addr & ~PAGE_MASK;
2198                 append_size = rcr_size;
2199                 if (num_rcr == 1) {
2200                         int ptype;
2201
2202                         off += 2;
2203                         append_size -= 2;
2204
2205                         ptype = (val >> RCR_ENTRY_PKT_TYPE_SHIFT);
2206                         if ((ptype == RCR_PKT_TYPE_TCP ||
2207                              ptype == RCR_PKT_TYPE_UDP) &&
2208                             !(val & (RCR_ENTRY_NOPORT |
2209                                      RCR_ENTRY_ERROR)))
2210                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2211                         else
2212                                 skb->ip_summed = CHECKSUM_NONE;
2213                 }
2214                 if (!(val & RCR_ENTRY_MULTI))
2215                         append_size = len - skb->len;
2216
2217                 niu_rx_skb_append(skb, page, off, append_size);
2218                 if ((page->index + rp->rbr_block_size) - rcr_size == addr) {
2219                         *link = (struct page *) page->mapping;
2220                         np->ops->unmap_page(np->device, page->index,
2221                                             PAGE_SIZE, DMA_FROM_DEVICE);
2222                         page->index = 0;
2223                         page->mapping = NULL;
2224                         rp->rbr_refill_pending++;
2225                 } else
2226                         get_page(page);
2227
2228                 index = NEXT_RCR(rp, index);
2229                 if (!(val & RCR_ENTRY_MULTI))
2230                         break;
2231
2232         }
2233         rp->rcr_index = index;
2234
2235         skb_reserve(skb, NET_IP_ALIGN);
2236         __pskb_pull_tail(skb, min(len, NIU_RXPULL_MAX));
2237
2238         rp->rx_packets++;
2239         rp->rx_bytes += skb->len;
2240
2241         skb->protocol = eth_type_trans(skb, np->dev);
2242         netif_receive_skb(skb);
2243
2244         return num_rcr;
2245 }
2246
2247 static int niu_rbr_fill(struct niu *np, struct rx_ring_info *rp, gfp_t mask)
2248 {
2249         int blocks_per_page = rp->rbr_blocks_per_page;
2250         int err, index = rp->rbr_index;
2251
2252         err = 0;
2253         while (index < (rp->rbr_table_size - blocks_per_page)) {
2254                 err = niu_rbr_add_page(np, rp, mask, index);
2255                 if (err)
2256                         break;
2257
2258                 index += blocks_per_page;
2259         }
2260
2261         rp->rbr_index = index;
2262         return err;
2263 }
2264
2265 static void niu_rbr_free(struct niu *np, struct rx_ring_info *rp)
2266 {
2267         int i;
2268
2269         for (i = 0; i < MAX_RBR_RING_SIZE; i++) {
2270                 struct page *page;
2271
2272                 page = rp->rxhash[i];
2273                 while (page) {
2274                         struct page *next = (struct page *) page->mapping;
2275                         u64 base = page->index;
2276
2277                         np->ops->unmap_page(np->device, base, PAGE_SIZE,
2278                                             DMA_FROM_DEVICE);
2279                         page->index = 0;
2280                         page->mapping = NULL;
2281
2282                         __free_page(page);
2283
2284                         page = next;
2285                 }
2286         }
2287
2288         for (i = 0; i < rp->rbr_table_size; i++)
2289                 rp->rbr[i] = cpu_to_le32(0);
2290         rp->rbr_index = 0;
2291 }
2292
2293 static int release_tx_packet(struct niu *np, struct tx_ring_info *rp, int idx)
2294 {
2295         struct tx_buff_info *tb = &rp->tx_buffs[idx];
2296         struct sk_buff *skb = tb->skb;
2297         struct tx_pkt_hdr *tp;
2298         u64 tx_flags;
2299         int i, len;
2300
2301         tp = (struct tx_pkt_hdr *) skb->data;
2302         tx_flags = le64_to_cpup(&tp->flags);
2303
2304         rp->tx_packets++;
2305         rp->tx_bytes += (((tx_flags & TXHDR_LEN) >> TXHDR_LEN_SHIFT) -
2306                          ((tx_flags & TXHDR_PAD) / 2));
2307
2308         len = skb_headlen(skb);
2309         np->ops->unmap_single(np->device, tb->mapping,
2310                               len, DMA_TO_DEVICE);
2311
2312         if (le64_to_cpu(rp->descr[idx]) & TX_DESC_MARK)
2313                 rp->mark_pending--;
2314
2315         tb->skb = NULL;
2316         do {
2317                 idx = NEXT_TX(rp, idx);
2318                 len -= MAX_TX_DESC_LEN;
2319         } while (len > 0);
2320
2321         for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2322                 tb = &rp->tx_buffs[idx];
2323                 BUG_ON(tb->skb != NULL);
2324                 np->ops->unmap_page(np->device, tb->mapping,
2325                                     skb_shinfo(skb)->frags[i].size,
2326                                     DMA_TO_DEVICE);
2327                 idx = NEXT_TX(rp, idx);
2328         }
2329
2330         dev_kfree_skb(skb);
2331
2332         return idx;
2333 }
2334
2335 #define NIU_TX_WAKEUP_THRESH(rp)                ((rp)->pending / 4)
2336
2337 static void niu_tx_work(struct niu *np, struct tx_ring_info *rp)
2338 {
2339         u16 pkt_cnt, tmp;
2340         int cons;
2341         u64 cs;
2342
2343         cs = rp->tx_cs;
2344         if (unlikely(!(cs & (TX_CS_MK | TX_CS_MMK))))
2345                 goto out;
2346
2347         tmp = pkt_cnt = (cs & TX_CS_PKT_CNT) >> TX_CS_PKT_CNT_SHIFT;
2348         pkt_cnt = (pkt_cnt - rp->last_pkt_cnt) &
2349                 (TX_CS_PKT_CNT >> TX_CS_PKT_CNT_SHIFT);
2350
2351         rp->last_pkt_cnt = tmp;
2352
2353         cons = rp->cons;
2354
2355         niudbg(TX_DONE, "%s: niu_tx_work() pkt_cnt[%u] cons[%d]\n",
2356                np->dev->name, pkt_cnt, cons);
2357
2358         while (pkt_cnt--)
2359                 cons = release_tx_packet(np, rp, cons);
2360
2361         rp->cons = cons;
2362         smp_mb();
2363
2364 out:
2365         if (unlikely(netif_queue_stopped(np->dev) &&
2366                      (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)))) {
2367                 netif_tx_lock(np->dev);
2368                 if (netif_queue_stopped(np->dev) &&
2369                     (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)))
2370                         netif_wake_queue(np->dev);
2371                 netif_tx_unlock(np->dev);
2372         }
2373 }
2374
2375 static int niu_rx_work(struct niu *np, struct rx_ring_info *rp, int budget)
2376 {
2377         int qlen, rcr_done = 0, work_done = 0;
2378         struct rxdma_mailbox *mbox = rp->mbox;
2379         u64 stat;
2380
2381 #if 1
2382         stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel));
2383         qlen = nr64(RCRSTAT_A(rp->rx_channel)) & RCRSTAT_A_QLEN;
2384 #else
2385         stat = le64_to_cpup(&mbox->rx_dma_ctl_stat);
2386         qlen = (le64_to_cpup(&mbox->rcrstat_a) & RCRSTAT_A_QLEN);
2387 #endif
2388         mbox->rx_dma_ctl_stat = 0;
2389         mbox->rcrstat_a = 0;
2390
2391         niudbg(RX_STATUS, "%s: niu_rx_work(chan[%d]), stat[%llx] qlen=%d\n",
2392                np->dev->name, rp->rx_channel, (unsigned long long) stat, qlen);
2393
2394         rcr_done = work_done = 0;
2395         qlen = min(qlen, budget);
2396         while (work_done < qlen) {
2397                 rcr_done += niu_process_rx_pkt(np, rp);
2398                 work_done++;
2399         }
2400
2401         if (rp->rbr_refill_pending >= rp->rbr_kick_thresh) {
2402                 unsigned int i;
2403
2404                 for (i = 0; i < rp->rbr_refill_pending; i++)
2405                         niu_rbr_refill(np, rp, GFP_ATOMIC);
2406                 rp->rbr_refill_pending = 0;
2407         }
2408
2409         stat = (RX_DMA_CTL_STAT_MEX |
2410                 ((u64)work_done << RX_DMA_CTL_STAT_PKTREAD_SHIFT) |
2411                 ((u64)rcr_done << RX_DMA_CTL_STAT_PTRREAD_SHIFT));
2412
2413         nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat);
2414
2415         return work_done;
2416 }
2417
2418 static int niu_poll_core(struct niu *np, struct niu_ldg *lp, int budget)
2419 {
2420         u64 v0 = lp->v0;
2421         u32 tx_vec = (v0 >> 32);
2422         u32 rx_vec = (v0 & 0xffffffff);
2423         int i, work_done = 0;
2424
2425         niudbg(INTR, "%s: niu_poll_core() v0[%016llx]\n",
2426                np->dev->name, (unsigned long long) v0);
2427
2428         for (i = 0; i < np->num_tx_rings; i++) {
2429                 struct tx_ring_info *rp = &np->tx_rings[i];
2430                 if (tx_vec & (1 << rp->tx_channel))
2431                         niu_tx_work(np, rp);
2432                 nw64(LD_IM0(LDN_TXDMA(rp->tx_channel)), 0);
2433         }
2434
2435         for (i = 0; i < np->num_rx_rings; i++) {
2436                 struct rx_ring_info *rp = &np->rx_rings[i];
2437
2438                 if (rx_vec & (1 << rp->rx_channel)) {
2439                         int this_work_done;
2440
2441                         this_work_done = niu_rx_work(np, rp,
2442                                                      budget);
2443
2444                         budget -= this_work_done;
2445                         work_done += this_work_done;
2446                 }
2447                 nw64(LD_IM0(LDN_RXDMA(rp->rx_channel)), 0);
2448         }
2449
2450         return work_done;
2451 }
2452
2453 static int niu_poll(struct napi_struct *napi, int budget)
2454 {
2455         struct niu_ldg *lp = container_of(napi, struct niu_ldg, napi);
2456         struct niu *np = lp->np;
2457         int work_done;
2458
2459         work_done = niu_poll_core(np, lp, budget);
2460
2461         if (work_done < budget) {
2462                 netif_rx_complete(np->dev, napi);
2463                 niu_ldg_rearm(np, lp, 1);
2464         }
2465         return work_done;
2466 }
2467
2468 static void niu_log_rxchan_errors(struct niu *np, struct rx_ring_info *rp,
2469                                   u64 stat)
2470 {
2471         dev_err(np->device, PFX "%s: RX channel %u errors ( ",
2472                 np->dev->name, rp->rx_channel);
2473
2474         if (stat & RX_DMA_CTL_STAT_RBR_TMOUT)
2475                 printk("RBR_TMOUT ");
2476         if (stat & RX_DMA_CTL_STAT_RSP_CNT_ERR)
2477                 printk("RSP_CNT ");
2478         if (stat & RX_DMA_CTL_STAT_BYTE_EN_BUS)
2479                 printk("BYTE_EN_BUS ");
2480         if (stat & RX_DMA_CTL_STAT_RSP_DAT_ERR)
2481                 printk("RSP_DAT ");
2482         if (stat & RX_DMA_CTL_STAT_RCR_ACK_ERR)
2483                 printk("RCR_ACK ");
2484         if (stat & RX_DMA_CTL_STAT_RCR_SHA_PAR)
2485                 printk("RCR_SHA_PAR ");
2486         if (stat & RX_DMA_CTL_STAT_RBR_PRE_PAR)
2487                 printk("RBR_PRE_PAR ");
2488         if (stat & RX_DMA_CTL_STAT_CONFIG_ERR)
2489                 printk("CONFIG ");
2490         if (stat & RX_DMA_CTL_STAT_RCRINCON)
2491                 printk("RCRINCON ");
2492         if (stat & RX_DMA_CTL_STAT_RCRFULL)
2493                 printk("RCRFULL ");
2494         if (stat & RX_DMA_CTL_STAT_RBRFULL)
2495                 printk("RBRFULL ");
2496         if (stat & RX_DMA_CTL_STAT_RBRLOGPAGE)
2497                 printk("RBRLOGPAGE ");
2498         if (stat & RX_DMA_CTL_STAT_CFIGLOGPAGE)
2499                 printk("CFIGLOGPAGE ");
2500         if (stat & RX_DMA_CTL_STAT_DC_FIFO_ERR)
2501                 printk("DC_FIDO ");
2502
2503         printk(")\n");
2504 }
2505
2506 static int niu_rx_error(struct niu *np, struct rx_ring_info *rp)
2507 {
2508         u64 stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel));
2509         int err = 0;
2510
2511
2512         if (stat & (RX_DMA_CTL_STAT_CHAN_FATAL |
2513                     RX_DMA_CTL_STAT_PORT_FATAL))
2514                 err = -EINVAL;
2515
2516         if (err) {
2517                 dev_err(np->device, PFX "%s: RX channel %u error, stat[%llx]\n",
2518                         np->dev->name, rp->rx_channel,
2519                         (unsigned long long) stat);
2520
2521                 niu_log_rxchan_errors(np, rp, stat);
2522         }
2523
2524         nw64(RX_DMA_CTL_STAT(rp->rx_channel),
2525              stat & RX_DMA_CTL_WRITE_CLEAR_ERRS);
2526
2527         return err;
2528 }
2529
2530 static void niu_log_txchan_errors(struct niu *np, struct tx_ring_info *rp,
2531                                   u64 cs)
2532 {
2533         dev_err(np->device, PFX "%s: TX channel %u errors ( ",
2534                 np->dev->name, rp->tx_channel);
2535
2536         if (cs & TX_CS_MBOX_ERR)
2537                 printk("MBOX ");
2538         if (cs & TX_CS_PKT_SIZE_ERR)
2539                 printk("PKT_SIZE ");
2540         if (cs & TX_CS_TX_RING_OFLOW)
2541                 printk("TX_RING_OFLOW ");
2542         if (cs & TX_CS_PREF_BUF_PAR_ERR)
2543                 printk("PREF_BUF_PAR ");
2544         if (cs & TX_CS_NACK_PREF)
2545                 printk("NACK_PREF ");
2546         if (cs & TX_CS_NACK_PKT_RD)
2547                 printk("NACK_PKT_RD ");
2548         if (cs & TX_CS_CONF_PART_ERR)
2549                 printk("CONF_PART ");
2550         if (cs & TX_CS_PKT_PRT_ERR)
2551                 printk("PKT_PTR ");
2552
2553         printk(")\n");
2554 }
2555
2556 static int niu_tx_error(struct niu *np, struct tx_ring_info *rp)
2557 {
2558         u64 cs, logh, logl;
2559
2560         cs = nr64(TX_CS(rp->tx_channel));
2561         logh = nr64(TX_RNG_ERR_LOGH(rp->tx_channel));
2562         logl = nr64(TX_RNG_ERR_LOGL(rp->tx_channel));
2563
2564         dev_err(np->device, PFX "%s: TX channel %u error, "
2565                 "cs[%llx] logh[%llx] logl[%llx]\n",
2566                 np->dev->name, rp->tx_channel,
2567                 (unsigned long long) cs,
2568                 (unsigned long long) logh,
2569                 (unsigned long long) logl);
2570
2571         niu_log_txchan_errors(np, rp, cs);
2572
2573         return -ENODEV;
2574 }
2575
2576 static int niu_mif_interrupt(struct niu *np)
2577 {
2578         u64 mif_status = nr64(MIF_STATUS);
2579         int phy_mdint = 0;
2580
2581         if (np->flags & NIU_FLAGS_XMAC) {
2582                 u64 xrxmac_stat = nr64_mac(XRXMAC_STATUS);
2583
2584                 if (xrxmac_stat & XRXMAC_STATUS_PHY_MDINT)
2585                         phy_mdint = 1;
2586         }
2587
2588         dev_err(np->device, PFX "%s: MIF interrupt, "
2589                 "stat[%llx] phy_mdint(%d)\n",
2590                 np->dev->name, (unsigned long long) mif_status, phy_mdint);
2591
2592         return -ENODEV;
2593 }
2594
2595 static void niu_xmac_interrupt(struct niu *np)
2596 {
2597         struct niu_xmac_stats *mp = &np->mac_stats.xmac;
2598         u64 val;
2599
2600         val = nr64_mac(XTXMAC_STATUS);
2601         if (val & XTXMAC_STATUS_FRAME_CNT_EXP)
2602                 mp->tx_frames += TXMAC_FRM_CNT_COUNT;
2603         if (val & XTXMAC_STATUS_BYTE_CNT_EXP)
2604                 mp->tx_bytes += TXMAC_BYTE_CNT_COUNT;
2605         if (val & XTXMAC_STATUS_TXFIFO_XFR_ERR)
2606                 mp->tx_fifo_errors++;
2607         if (val & XTXMAC_STATUS_TXMAC_OFLOW)
2608                 mp->tx_overflow_errors++;
2609         if (val & XTXMAC_STATUS_MAX_PSIZE_ERR)
2610                 mp->tx_max_pkt_size_errors++;
2611         if (val & XTXMAC_STATUS_TXMAC_UFLOW)
2612                 mp->tx_underflow_errors++;
2613
2614         val = nr64_mac(XRXMAC_STATUS);
2615         if (val & XRXMAC_STATUS_LCL_FLT_STATUS)
2616                 mp->rx_local_faults++;
2617         if (val & XRXMAC_STATUS_RFLT_DET)
2618                 mp->rx_remote_faults++;
2619         if (val & XRXMAC_STATUS_LFLT_CNT_EXP)
2620                 mp->rx_link_faults += LINK_FAULT_CNT_COUNT;
2621         if (val & XRXMAC_STATUS_ALIGNERR_CNT_EXP)
2622                 mp->rx_align_errors += RXMAC_ALIGN_ERR_CNT_COUNT;
2623         if (val & XRXMAC_STATUS_RXFRAG_CNT_EXP)
2624                 mp->rx_frags += RXMAC_FRAG_CNT_COUNT;
2625         if (val & XRXMAC_STATUS_RXMULTF_CNT_EXP)
2626                 mp->rx_mcasts += RXMAC_MC_FRM_CNT_COUNT;
2627         if (val & XRXMAC_STATUS_RXBCAST_CNT_EXP)
2628                 mp->rx_bcasts += RXMAC_BC_FRM_CNT_COUNT;
2629         if (val & XRXMAC_STATUS_RXBCAST_CNT_EXP)
2630                 mp->rx_bcasts += RXMAC_BC_FRM_CNT_COUNT;
2631         if (val & XRXMAC_STATUS_RXHIST1_CNT_EXP)
2632                 mp->rx_hist_cnt1 += RXMAC_HIST_CNT1_COUNT;
2633         if (val & XRXMAC_STATUS_RXHIST2_CNT_EXP)
2634                 mp->rx_hist_cnt2 += RXMAC_HIST_CNT2_COUNT;
2635         if (val & XRXMAC_STATUS_RXHIST3_CNT_EXP)
2636                 mp->rx_hist_cnt3 += RXMAC_HIST_CNT3_COUNT;
2637         if (val & XRXMAC_STATUS_RXHIST4_CNT_EXP)
2638                 mp->rx_hist_cnt4 += RXMAC_HIST_CNT4_COUNT;
2639         if (val & XRXMAC_STATUS_RXHIST5_CNT_EXP)
2640                 mp->rx_hist_cnt5 += RXMAC_HIST_CNT5_COUNT;
2641         if (val & XRXMAC_STATUS_RXHIST6_CNT_EXP)
2642                 mp->rx_hist_cnt6 += RXMAC_HIST_CNT6_COUNT;
2643         if (val & XRXMAC_STATUS_RXHIST7_CNT_EXP)
2644                 mp->rx_hist_cnt7 += RXMAC_HIST_CNT7_COUNT;
2645         if (val & XRXMAC_STAT_MSK_RXOCTET_CNT_EXP)
2646                 mp->rx_octets += RXMAC_BT_CNT_COUNT;
2647         if (val & XRXMAC_STATUS_CVIOLERR_CNT_EXP)
2648                 mp->rx_code_violations += RXMAC_CD_VIO_CNT_COUNT;
2649         if (val & XRXMAC_STATUS_LENERR_CNT_EXP)
2650                 mp->rx_len_errors += RXMAC_MPSZER_CNT_COUNT;
2651         if (val & XRXMAC_STATUS_CRCERR_CNT_EXP)
2652                 mp->rx_crc_errors += RXMAC_CRC_ER_CNT_COUNT;
2653         if (val & XRXMAC_STATUS_RXUFLOW)
2654                 mp->rx_underflows++;
2655         if (val & XRXMAC_STATUS_RXOFLOW)
2656                 mp->rx_overflows++;
2657
2658         val = nr64_mac(XMAC_FC_STAT);
2659         if (val & XMAC_FC_STAT_TX_MAC_NPAUSE)
2660                 mp->pause_off_state++;
2661         if (val & XMAC_FC_STAT_TX_MAC_PAUSE)
2662                 mp->pause_on_state++;
2663         if (val & XMAC_FC_STAT_RX_MAC_RPAUSE)
2664                 mp->pause_received++;
2665 }
2666
2667 static void niu_bmac_interrupt(struct niu *np)
2668 {
2669         struct niu_bmac_stats *mp = &np->mac_stats.bmac;
2670         u64 val;
2671
2672         val = nr64_mac(BTXMAC_STATUS);
2673         if (val & BTXMAC_STATUS_UNDERRUN)
2674                 mp->tx_underflow_errors++;
2675         if (val & BTXMAC_STATUS_MAX_PKT_ERR)
2676                 mp->tx_max_pkt_size_errors++;
2677         if (val & BTXMAC_STATUS_BYTE_CNT_EXP)
2678                 mp->tx_bytes += BTXMAC_BYTE_CNT_COUNT;
2679         if (val & BTXMAC_STATUS_FRAME_CNT_EXP)
2680                 mp->tx_frames += BTXMAC_FRM_CNT_COUNT;
2681
2682         val = nr64_mac(BRXMAC_STATUS);
2683         if (val & BRXMAC_STATUS_OVERFLOW)
2684                 mp->rx_overflows++;
2685         if (val & BRXMAC_STATUS_FRAME_CNT_EXP)
2686                 mp->rx_frames += BRXMAC_FRAME_CNT_COUNT;
2687         if (val & BRXMAC_STATUS_ALIGN_ERR_EXP)
2688                 mp->rx_align_errors += BRXMAC_ALIGN_ERR_CNT_COUNT;
2689         if (val & BRXMAC_STATUS_CRC_ERR_EXP)
2690                 mp->rx_crc_errors += BRXMAC_ALIGN_ERR_CNT_COUNT;
2691         if (val & BRXMAC_STATUS_LEN_ERR_EXP)
2692                 mp->rx_len_errors += BRXMAC_CODE_VIOL_ERR_CNT_COUNT;
2693
2694         val = nr64_mac(BMAC_CTRL_STATUS);
2695         if (val & BMAC_CTRL_STATUS_NOPAUSE)
2696                 mp->pause_off_state++;
2697         if (val & BMAC_CTRL_STATUS_PAUSE)
2698                 mp->pause_on_state++;
2699         if (val & BMAC_CTRL_STATUS_PAUSE_RECV)
2700                 mp->pause_received++;
2701 }
2702
2703 static int niu_mac_interrupt(struct niu *np)
2704 {
2705         if (np->flags & NIU_FLAGS_XMAC)
2706                 niu_xmac_interrupt(np);
2707         else
2708                 niu_bmac_interrupt(np);
2709
2710         return 0;
2711 }
2712
2713 static void niu_log_device_error(struct niu *np, u64 stat)
2714 {
2715         dev_err(np->device, PFX "%s: Core device errors ( ",
2716                 np->dev->name);
2717
2718         if (stat & SYS_ERR_MASK_META2)
2719                 printk("META2 ");
2720         if (stat & SYS_ERR_MASK_META1)
2721                 printk("META1 ");
2722         if (stat & SYS_ERR_MASK_PEU)
2723                 printk("PEU ");
2724         if (stat & SYS_ERR_MASK_TXC)
2725                 printk("TXC ");
2726         if (stat & SYS_ERR_MASK_RDMC)
2727                 printk("RDMC ");
2728         if (stat & SYS_ERR_MASK_TDMC)
2729                 printk("TDMC ");
2730         if (stat & SYS_ERR_MASK_ZCP)
2731                 printk("ZCP ");
2732         if (stat & SYS_ERR_MASK_FFLP)
2733                 printk("FFLP ");
2734         if (stat & SYS_ERR_MASK_IPP)
2735                 printk("IPP ");
2736         if (stat & SYS_ERR_MASK_MAC)
2737                 printk("MAC ");
2738         if (stat & SYS_ERR_MASK_SMX)
2739                 printk("SMX ");
2740
2741         printk(")\n");
2742 }
2743
2744 static int niu_device_error(struct niu *np)
2745 {
2746         u64 stat = nr64(SYS_ERR_STAT);
2747
2748         dev_err(np->device, PFX "%s: Core device error, stat[%llx]\n",
2749                 np->dev->name, (unsigned long long) stat);
2750
2751         niu_log_device_error(np, stat);
2752
2753         return -ENODEV;
2754 }
2755
2756 static int niu_slowpath_interrupt(struct niu *np, struct niu_ldg *lp,
2757                               u64 v0, u64 v1, u64 v2)
2758 {
2759
2760         int i, err = 0;
2761
2762         lp->v0 = v0;
2763         lp->v1 = v1;
2764         lp->v2 = v2;
2765
2766         if (v1 & 0x00000000ffffffffULL) {
2767                 u32 rx_vec = (v1 & 0xffffffff);
2768
2769                 for (i = 0; i < np->num_rx_rings; i++) {
2770                         struct rx_ring_info *rp = &np->rx_rings[i];
2771
2772                         if (rx_vec & (1 << rp->rx_channel)) {
2773                                 int r = niu_rx_error(np, rp);
2774                                 if (r) {
2775                                         err = r;
2776                                 } else {
2777                                         if (!v0)
2778                                                 nw64(RX_DMA_CTL_STAT(rp->rx_channel),
2779                                                      RX_DMA_CTL_STAT_MEX);
2780                                 }
2781                         }
2782                 }
2783         }
2784         if (v1 & 0x7fffffff00000000ULL) {
2785                 u32 tx_vec = (v1 >> 32) & 0x7fffffff;
2786
2787                 for (i = 0; i < np->num_tx_rings; i++) {
2788                         struct tx_ring_info *rp = &np->tx_rings[i];
2789
2790                         if (tx_vec & (1 << rp->tx_channel)) {
2791                                 int r = niu_tx_error(np, rp);
2792                                 if (r)
2793                                         err = r;
2794                         }
2795                 }
2796         }
2797         if ((v0 | v1) & 0x8000000000000000ULL) {
2798                 int r = niu_mif_interrupt(np);
2799                 if (r)
2800                         err = r;
2801         }
2802         if (v2) {
2803                 if (v2 & 0x01ef) {
2804                         int r = niu_mac_interrupt(np);
2805                         if (r)
2806                                 err = r;
2807                 }
2808                 if (v2 & 0x0210) {
2809                         int r = niu_device_error(np);
2810                         if (r)
2811                                 err = r;
2812                 }
2813         }
2814
2815         if (err)
2816                 niu_enable_interrupts(np, 0);
2817
2818         return err;
2819 }
2820
2821 static void niu_rxchan_intr(struct niu *np, struct rx_ring_info *rp,
2822                             int ldn)
2823 {
2824         struct rxdma_mailbox *mbox = rp->mbox;
2825         u64 stat_write, stat = le64_to_cpup(&mbox->rx_dma_ctl_stat);
2826
2827         stat_write = (RX_DMA_CTL_STAT_RCRTHRES |
2828                       RX_DMA_CTL_STAT_RCRTO);
2829         nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat_write);
2830
2831         niudbg(INTR, "%s: rxchan_intr stat[%llx]\n",
2832                np->dev->name, (unsigned long long) stat);
2833 }
2834
2835 static void niu_txchan_intr(struct niu *np, struct tx_ring_info *rp,
2836                             int ldn)
2837 {
2838         rp->tx_cs = nr64(TX_CS(rp->tx_channel));
2839
2840         niudbg(INTR, "%s: txchan_intr cs[%llx]\n",
2841                np->dev->name, (unsigned long long) rp->tx_cs);
2842 }
2843
2844 static void __niu_fastpath_interrupt(struct niu *np, int ldg, u64 v0)
2845 {
2846         struct niu_parent *parent = np->parent;
2847         u32 rx_vec, tx_vec;
2848         int i;
2849
2850         tx_vec = (v0 >> 32);
2851         rx_vec = (v0 & 0xffffffff);
2852
2853         for (i = 0; i < np->num_rx_rings; i++) {
2854                 struct rx_ring_info *rp = &np->rx_rings[i];
2855                 int ldn = LDN_RXDMA(rp->rx_channel);
2856
2857                 if (parent->ldg_map[ldn] != ldg)
2858                         continue;
2859
2860                 nw64(LD_IM0(ldn), LD_IM0_MASK);
2861                 if (rx_vec & (1 << rp->rx_channel))
2862                         niu_rxchan_intr(np, rp, ldn);
2863         }
2864
2865         for (i = 0; i < np->num_tx_rings; i++) {
2866                 struct tx_ring_info *rp = &np->tx_rings[i];
2867                 int ldn = LDN_TXDMA(rp->tx_channel);
2868
2869                 if (parent->ldg_map[ldn] != ldg)
2870                         continue;
2871
2872                 nw64(LD_IM0(ldn), LD_IM0_MASK);
2873                 if (tx_vec & (1 << rp->tx_channel))
2874                         niu_txchan_intr(np, rp, ldn);
2875         }
2876 }
2877
2878 static void niu_schedule_napi(struct niu *np, struct niu_ldg *lp,
2879                               u64 v0, u64 v1, u64 v2)
2880 {
2881         if (likely(netif_rx_schedule_prep(np->dev, &lp->napi))) {
2882                 lp->v0 = v0;
2883                 lp->v1 = v1;
2884                 lp->v2 = v2;
2885                 __niu_fastpath_interrupt(np, lp->ldg_num, v0);
2886                 __netif_rx_schedule(np->dev, &lp->napi);
2887         }
2888 }
2889
2890 static irqreturn_t niu_interrupt(int irq, void *dev_id)
2891 {
2892         struct niu_ldg *lp = dev_id;
2893         struct niu *np = lp->np;
2894         int ldg = lp->ldg_num;
2895         unsigned long flags;
2896         u64 v0, v1, v2;
2897
2898         if (netif_msg_intr(np))
2899                 printk(KERN_DEBUG PFX "niu_interrupt() ldg[%p](%d) ",
2900                        lp, ldg);
2901
2902         spin_lock_irqsave(&np->lock, flags);
2903
2904         v0 = nr64(LDSV0(ldg));
2905         v1 = nr64(LDSV1(ldg));
2906         v2 = nr64(LDSV2(ldg));
2907
2908         if (netif_msg_intr(np))
2909                 printk("v0[%llx] v1[%llx] v2[%llx]\n",
2910                        (unsigned long long) v0,
2911                        (unsigned long long) v1,
2912                        (unsigned long long) v2);
2913
2914         if (unlikely(!v0 && !v1 && !v2)) {
2915                 spin_unlock_irqrestore(&np->lock, flags);
2916                 return IRQ_NONE;
2917         }
2918
2919         if (unlikely((v0 & ((u64)1 << LDN_MIF)) || v1 || v2)) {
2920                 int err = niu_slowpath_interrupt(np, lp, v0, v1, v2);
2921                 if (err)
2922                         goto out;
2923         }
2924         if (likely(v0 & ~((u64)1 << LDN_MIF)))
2925                 niu_schedule_napi(np, lp, v0, v1, v2);
2926         else
2927                 niu_ldg_rearm(np, lp, 1);
2928 out:
2929         spin_unlock_irqrestore(&np->lock, flags);
2930
2931         return IRQ_HANDLED;
2932 }
2933
2934 static void niu_free_rx_ring_info(struct niu *np, struct rx_ring_info *rp)
2935 {
2936         if (rp->mbox) {
2937                 np->ops->free_coherent(np->device,
2938                                        sizeof(struct rxdma_mailbox),
2939                                        rp->mbox, rp->mbox_dma);
2940                 rp->mbox = NULL;
2941         }
2942         if (rp->rcr) {
2943                 np->ops->free_coherent(np->device,
2944                                        MAX_RCR_RING_SIZE * sizeof(__le64),
2945                                        rp->rcr, rp->rcr_dma);
2946                 rp->rcr = NULL;
2947                 rp->rcr_table_size = 0;
2948                 rp->rcr_index = 0;
2949         }
2950         if (rp->rbr) {
2951                 niu_rbr_free(np, rp);
2952
2953                 np->ops->free_coherent(np->device,
2954                                        MAX_RBR_RING_SIZE * sizeof(__le32),
2955                                        rp->rbr, rp->rbr_dma);
2956                 rp->rbr = NULL;
2957                 rp->rbr_table_size = 0;
2958                 rp->rbr_index = 0;
2959         }
2960         kfree(rp->rxhash);
2961         rp->rxhash = NULL;
2962 }
2963
2964 static void niu_free_tx_ring_info(struct niu *np, struct tx_ring_info *rp)
2965 {
2966         if (rp->mbox) {
2967                 np->ops->free_coherent(np->device,
2968                                        sizeof(struct txdma_mailbox),
2969                                        rp->mbox, rp->mbox_dma);
2970                 rp->mbox = NULL;
2971         }
2972         if (rp->descr) {
2973                 int i;
2974
2975                 for (i = 0; i < MAX_TX_RING_SIZE; i++) {
2976                         if (rp->tx_buffs[i].skb)
2977                                 (void) release_tx_packet(np, rp, i);
2978                 }
2979
2980                 np->ops->free_coherent(np->device,
2981                                        MAX_TX_RING_SIZE * sizeof(__le64),
2982                                        rp->descr, rp->descr_dma);
2983                 rp->descr = NULL;
2984                 rp->pending = 0;
2985                 rp->prod = 0;
2986                 rp->cons = 0;
2987                 rp->wrap_bit = 0;
2988         }
2989 }
2990
2991 static void niu_free_channels(struct niu *np)
2992 {
2993         int i;
2994
2995         if (np->rx_rings) {
2996                 for (i = 0; i < np->num_rx_rings; i++) {
2997                         struct rx_ring_info *rp = &np->rx_rings[i];
2998
2999                         niu_free_rx_ring_info(np, rp);
3000                 }
3001                 kfree(np->rx_rings);
3002                 np->rx_rings = NULL;
3003                 np->num_rx_rings = 0;
3004         }
3005
3006         if (np->tx_rings) {
3007                 for (i = 0; i < np->num_tx_rings; i++) {
3008                         struct tx_ring_info *rp = &np->tx_rings[i];
3009
3010                         niu_free_tx_ring_info(np, rp);
3011                 }
3012                 kfree(np->tx_rings);
3013                 np->tx_rings = NULL;
3014                 np->num_tx_rings = 0;
3015         }
3016 }
3017
3018 static int niu_alloc_rx_ring_info(struct niu *np,
3019                                   struct rx_ring_info *rp)
3020 {
3021         BUILD_BUG_ON(sizeof(struct rxdma_mailbox) != 64);
3022
3023         rp->rxhash = kzalloc(MAX_RBR_RING_SIZE * sizeof(struct page *),
3024                              GFP_KERNEL);
3025         if (!rp->rxhash)
3026                 return -ENOMEM;
3027
3028         rp->mbox = np->ops->alloc_coherent(np->device,
3029                                            sizeof(struct rxdma_mailbox),
3030                                            &rp->mbox_dma, GFP_KERNEL);
3031         if (!rp->mbox)
3032                 return -ENOMEM;
3033         if ((unsigned long)rp->mbox & (64UL - 1)) {
3034                 dev_err(np->device, PFX "%s: Coherent alloc gives misaligned "
3035                         "RXDMA mailbox %p\n", np->dev->name, rp->mbox);
3036                 return -EINVAL;
3037         }
3038
3039         rp->rcr = np->ops->alloc_coherent(np->device,
3040                                           MAX_RCR_RING_SIZE * sizeof(__le64),
3041                                           &rp->rcr_dma, GFP_KERNEL);
3042         if (!rp->rcr)
3043                 return -ENOMEM;
3044         if ((unsigned long)rp->rcr & (64UL - 1)) {
3045                 dev_err(np->device, PFX "%s: Coherent alloc gives misaligned "
3046                         "RXDMA RCR table %p\n", np->dev->name, rp->rcr);
3047                 return -EINVAL;
3048         }
3049         rp->rcr_table_size = MAX_RCR_RING_SIZE;
3050         rp->rcr_index = 0;
3051
3052         rp->rbr = np->ops->alloc_coherent(np->device,
3053                                           MAX_RBR_RING_SIZE * sizeof(__le32),
3054                                           &rp->rbr_dma, GFP_KERNEL);
3055         if (!rp->rbr)
3056                 return -ENOMEM;
3057         if ((unsigned long)rp->rbr & (64UL - 1)) {
3058                 dev_err(np->device, PFX "%s: Coherent alloc gives misaligned "
3059                         "RXDMA RBR table %p\n", np->dev->name, rp->rbr);
3060                 return -EINVAL;
3061         }
3062         rp->rbr_table_size = MAX_RBR_RING_SIZE;
3063         rp->rbr_index = 0;
3064         rp->rbr_pending = 0;
3065
3066         return 0;
3067 }
3068
3069 static void niu_set_max_burst(struct niu *np, struct tx_ring_info *rp)
3070 {
3071         int mtu = np->dev->mtu;
3072
3073         /* These values are recommended by the HW designers for fair
3074          * utilization of DRR amongst the rings.
3075          */
3076         rp->max_burst = mtu + 32;
3077         if (rp->max_burst > 4096)
3078                 rp->max_burst = 4096;
3079 }
3080
3081 static int niu_alloc_tx_ring_info(struct niu *np,
3082                                   struct tx_ring_info *rp)
3083 {
3084         BUILD_BUG_ON(sizeof(struct txdma_mailbox) != 64);
3085
3086         rp->mbox = np->ops->alloc_coherent(np->device,
3087                                            sizeof(struct txdma_mailbox),
3088                                            &rp->mbox_dma, GFP_KERNEL);
3089         if (!rp->mbox)
3090                 return -ENOMEM;
3091         if ((unsigned long)rp->mbox & (64UL - 1)) {
3092                 dev_err(np->device, PFX "%s: Coherent alloc gives misaligned "
3093                         "TXDMA mailbox %p\n", np->dev->name, rp->mbox);
3094                 return -EINVAL;
3095         }
3096
3097         rp->descr = np->ops->alloc_coherent(np->device,
3098                                             MAX_TX_RING_SIZE * sizeof(__le64),
3099                                             &rp->descr_dma, GFP_KERNEL);
3100         if (!rp->descr)
3101                 return -ENOMEM;
3102         if ((unsigned long)rp->descr & (64UL - 1)) {
3103                 dev_err(np->device, PFX "%s: Coherent alloc gives misaligned "
3104                         "TXDMA descr table %p\n", np->dev->name, rp->descr);
3105                 return -EINVAL;
3106         }
3107
3108         rp->pending = MAX_TX_RING_SIZE;
3109         rp->prod = 0;
3110         rp->cons = 0;
3111         rp->wrap_bit = 0;
3112
3113         /* XXX make these configurable... XXX */
3114         rp->mark_freq = rp->pending / 4;
3115
3116         niu_set_max_burst(np, rp);
3117
3118         return 0;
3119 }
3120
3121 static void niu_size_rbr(struct niu *np, struct rx_ring_info *rp)
3122 {
3123         u16 bss;
3124
3125         bss = min(PAGE_SHIFT, 15);
3126
3127         rp->rbr_block_size = 1 << bss;
3128         rp->rbr_blocks_per_page = 1 << (PAGE_SHIFT-bss);
3129
3130         rp->rbr_sizes[0] = 256;
3131         rp->rbr_sizes[1] = 1024;
3132         if (np->dev->mtu > ETH_DATA_LEN) {
3133                 switch (PAGE_SIZE) {
3134                 case 4 * 1024:
3135                         rp->rbr_sizes[2] = 4096;
3136                         break;
3137
3138                 default:
3139                         rp->rbr_sizes[2] = 8192;
3140                         break;
3141                 }
3142         } else {
3143                 rp->rbr_sizes[2] = 2048;
3144         }
3145         rp->rbr_sizes[3] = rp->rbr_block_size;
3146 }
3147
3148 static int niu_alloc_channels(struct niu *np)
3149 {
3150         struct niu_parent *parent = np->parent;
3151         int first_rx_channel, first_tx_channel;
3152         int i, port, err;
3153
3154         port = np->port;
3155         first_rx_channel = first_tx_channel = 0;
3156         for (i = 0; i < port; i++) {
3157                 first_rx_channel += parent->rxchan_per_port[i];
3158                 first_tx_channel += parent->txchan_per_port[i];
3159         }
3160
3161         np->num_rx_rings = parent->rxchan_per_port[port];
3162         np->num_tx_rings = parent->txchan_per_port[port];
3163
3164         np->rx_rings = kzalloc(np->num_rx_rings * sizeof(struct rx_ring_info),
3165                                GFP_KERNEL);
3166         err = -ENOMEM;
3167         if (!np->rx_rings)
3168                 goto out_err;
3169
3170         for (i = 0; i < np->num_rx_rings; i++) {
3171                 struct rx_ring_info *rp = &np->rx_rings[i];
3172
3173                 rp->np = np;
3174                 rp->rx_channel = first_rx_channel + i;
3175
3176                 err = niu_alloc_rx_ring_info(np, rp);
3177                 if (err)
3178                         goto out_err;
3179
3180                 niu_size_rbr(np, rp);
3181
3182                 /* XXX better defaults, configurable, etc... XXX */
3183                 rp->nonsyn_window = 64;
3184                 rp->nonsyn_threshold = rp->rcr_table_size - 64;
3185                 rp->syn_window = 64;
3186                 rp->syn_threshold = rp->rcr_table_size - 64;
3187                 rp->rcr_pkt_threshold = 16;
3188                 rp->rcr_timeout = 8;
3189                 rp->rbr_kick_thresh = RBR_REFILL_MIN;
3190                 if (rp->rbr_kick_thresh < rp->rbr_blocks_per_page)
3191                         rp->rbr_kick_thresh = rp->rbr_blocks_per_page;
3192
3193                 err = niu_rbr_fill(np, rp, GFP_KERNEL);
3194                 if (err)
3195                         return err;
3196         }
3197
3198         np->tx_rings = kzalloc(np->num_tx_rings * sizeof(struct tx_ring_info),
3199                                GFP_KERNEL);
3200         err = -ENOMEM;
3201         if (!np->tx_rings)
3202                 goto out_err;
3203
3204         for (i = 0; i < np->num_tx_rings; i++) {
3205                 struct tx_ring_info *rp = &np->tx_rings[i];
3206
3207                 rp->np = np;
3208                 rp->tx_channel = first_tx_channel + i;
3209
3210                 err = niu_alloc_tx_ring_info(np, rp);
3211                 if (err)
3212                         goto out_err;
3213         }
3214
3215         return 0;
3216
3217 out_err:
3218         niu_free_channels(np);
3219         return err;
3220 }
3221
3222 static int niu_tx_cs_sng_poll(struct niu *np, int channel)
3223 {
3224         int limit = 1000;
3225
3226         while (--limit > 0) {
3227                 u64 val = nr64(TX_CS(channel));
3228                 if (val & TX_CS_SNG_STATE)
3229                         return 0;
3230         }
3231         return -ENODEV;
3232 }
3233
3234 static int niu_tx_channel_stop(struct niu *np, int channel)
3235 {
3236         u64 val = nr64(TX_CS(channel));
3237
3238         val |= TX_CS_STOP_N_GO;
3239         nw64(TX_CS(channel), val);
3240
3241         return niu_tx_cs_sng_poll(np, channel);
3242 }
3243
3244 static int niu_tx_cs_reset_poll(struct niu *np, int channel)
3245 {
3246         int limit = 1000;
3247
3248         while (--limit > 0) {
3249                 u64 val = nr64(TX_CS(channel));
3250                 if (!(val & TX_CS_RST))
3251                         return 0;
3252         }
3253         return -ENODEV;
3254 }
3255
3256 static int niu_tx_channel_reset(struct niu *np, int channel)
3257 {
3258         u64 val = nr64(TX_CS(channel));
3259         int err;
3260
3261         val |= TX_CS_RST;
3262         nw64(TX_CS(channel), val);
3263
3264         err = niu_tx_cs_reset_poll(np, channel);
3265         if (!err)
3266                 nw64(TX_RING_KICK(channel), 0);
3267
3268         return err;
3269 }
3270
3271 static int niu_tx_channel_lpage_init(struct niu *np, int channel)
3272 {
3273         u64 val;
3274
3275         nw64(TX_LOG_MASK1(channel), 0);
3276         nw64(TX_LOG_VAL1(channel), 0);
3277         nw64(TX_LOG_MASK2(channel), 0);
3278         nw64(TX_LOG_VAL2(channel), 0);
3279         nw64(TX_LOG_PAGE_RELO1(channel), 0);
3280         nw64(TX_LOG_PAGE_RELO2(channel), 0);
3281         nw64(TX_LOG_PAGE_HDL(channel), 0);
3282
3283         val  = (u64)np->port << TX_LOG_PAGE_VLD_FUNC_SHIFT;
3284         val |= (TX_LOG_PAGE_VLD_PAGE0 | TX_LOG_PAGE_VLD_PAGE1);
3285         nw64(TX_LOG_PAGE_VLD(channel), val);
3286
3287         /* XXX TXDMA 32bit mode? XXX */
3288
3289         return 0;
3290 }
3291
3292 static void niu_txc_enable_port(struct niu *np, int on)
3293 {
3294         unsigned long flags;
3295         u64 val, mask;
3296
3297         niu_lock_parent(np, flags);
3298         val = nr64(TXC_CONTROL);
3299         mask = (u64)1 << np->port;
3300         if (on) {
3301                 val |= TXC_CONTROL_ENABLE | mask;
3302         } else {
3303                 val &= ~mask;
3304                 if ((val & ~TXC_CONTROL_ENABLE) == 0)
3305                         val &= ~TXC_CONTROL_ENABLE;
3306         }
3307         nw64(TXC_CONTROL, val);
3308         niu_unlock_parent(np, flags);
3309 }
3310
3311 static void niu_txc_set_imask(struct niu *np, u64 imask)
3312 {
3313         unsigned long flags;
3314         u64 val;
3315
3316         niu_lock_parent(np, flags);
3317         val = nr64(TXC_INT_MASK);
3318         val &= ~TXC_INT_MASK_VAL(np->port);
3319         val |= (imask << TXC_INT_MASK_VAL_SHIFT(np->port));
3320         niu_unlock_parent(np, flags);
3321 }
3322
3323 static void niu_txc_port_dma_enable(struct niu *np, int on)
3324 {
3325         u64 val = 0;
3326
3327         if (on) {
3328                 int i;
3329
3330                 for (i = 0; i < np->num_tx_rings; i++)
3331                         val |= (1 << np->tx_rings[i].tx_channel);
3332         }
3333         nw64(TXC_PORT_DMA(np->port), val);
3334 }
3335
3336 static int niu_init_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
3337 {
3338         int err, channel = rp->tx_channel;
3339         u64 val, ring_len;
3340
3341         err = niu_tx_channel_stop(np, channel);
3342         if (err)
3343                 return err;
3344
3345         err = niu_tx_channel_reset(np, channel);
3346         if (err)
3347                 return err;
3348
3349         err = niu_tx_channel_lpage_init(np, channel);
3350         if (err)
3351                 return err;
3352
3353         nw64(TXC_DMA_MAX(channel), rp->max_burst);
3354         nw64(TX_ENT_MSK(channel), 0);
3355
3356         if (rp->descr_dma & ~(TX_RNG_CFIG_STADDR_BASE |
3357                               TX_RNG_CFIG_STADDR)) {
3358                 dev_err(np->device, PFX "%s: TX ring channel %d "
3359                         "DMA addr (%llx) is not aligned.\n",
3360                         np->dev->name, channel,
3361                         (unsigned long long) rp->descr_dma);
3362                 return -EINVAL;
3363         }
3364
3365         /* The length field in TX_RNG_CFIG is measured in 64-byte
3366          * blocks.  rp->pending is the number of TX descriptors in
3367          * our ring, 8 bytes each, thus we divide by 8 bytes more
3368          * to get the proper value the chip wants.
3369          */
3370         ring_len = (rp->pending / 8);
3371
3372         val = ((ring_len << TX_RNG_CFIG_LEN_SHIFT) |
3373                rp->descr_dma);
3374         nw64(TX_RNG_CFIG(channel), val);
3375
3376         if (((rp->mbox_dma >> 32) & ~TXDMA_MBH_MBADDR) ||
3377             ((u32)rp->mbox_dma & ~TXDMA_MBL_MBADDR)) {
3378                 dev_err(np->device, PFX "%s: TX ring channel %d "
3379                         "MBOX addr (%llx) is has illegal bits.\n",
3380                         np->dev->name, channel,
3381                         (unsigned long long) rp->mbox_dma);
3382                 return -EINVAL;
3383         }
3384         nw64(TXDMA_MBH(channel), rp->mbox_dma >> 32);
3385         nw64(TXDMA_MBL(channel), rp->mbox_dma & TXDMA_MBL_MBADDR);
3386
3387         nw64(TX_CS(channel), 0);
3388
3389         rp->last_pkt_cnt = 0;
3390
3391         return 0;
3392 }
3393
3394 static void niu_init_rdc_groups(struct niu *np)
3395 {
3396         struct niu_rdc_tables *tp = &np->parent->rdc_group_cfg[np->port];
3397         int i, first_table_num = tp->first_table_num;
3398
3399         for (i = 0; i < tp->num_tables; i++) {
3400                 struct rdc_table *tbl = &tp->tables[i];
3401                 int this_table = first_table_num + i;
3402                 int slot;
3403
3404                 for (slot = 0; slot < NIU_RDC_TABLE_SLOTS; slot++)
3405                         nw64(RDC_TBL(this_table, slot),
3406                              tbl->rxdma_channel[slot]);
3407         }
3408
3409         nw64(DEF_RDC(np->port), np->parent->rdc_default[np->port]);
3410 }
3411
3412 static void niu_init_drr_weight(struct niu *np)
3413 {
3414         int type = phy_decode(np->parent->port_phy, np->port);
3415         u64 val;
3416
3417         switch (type) {
3418         case PORT_TYPE_10G:
3419                 val = PT_DRR_WEIGHT_DEFAULT_10G;
3420                 break;
3421
3422         case PORT_TYPE_1G:
3423         default:
3424                 val = PT_DRR_WEIGHT_DEFAULT_1G;
3425                 break;
3426         }
3427         nw64(PT_DRR_WT(np->port), val);
3428 }
3429
3430 static int niu_init_hostinfo(struct niu *np)
3431 {
3432         struct niu_parent *parent = np->parent;
3433         struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
3434         int i, err, num_alt = niu_num_alt_addr(np);
3435         int first_rdc_table = tp->first_table_num;
3436
3437         err = niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
3438         if (err)
3439                 return err;
3440
3441         err = niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
3442         if (err)
3443                 return err;
3444
3445         for (i = 0; i < num_alt; i++) {
3446                 err = niu_set_alt_mac_rdc_table(np, i, first_rdc_table, 1);
3447                 if (err)
3448                         return err;
3449         }
3450
3451         return 0;
3452 }
3453
3454 static int niu_rx_channel_reset(struct niu *np, int channel)
3455 {
3456         return niu_set_and_wait_clear(np, RXDMA_CFIG1(channel),
3457                                       RXDMA_CFIG1_RST, 1000, 10,
3458                                       "RXDMA_CFIG1");
3459 }
3460
3461 static int niu_rx_channel_lpage_init(struct niu *np, int channel)
3462 {
3463         u64 val;
3464
3465         nw64(RX_LOG_MASK1(channel), 0);
3466         nw64(RX_LOG_VAL1(channel), 0);
3467         nw64(RX_LOG_MASK2(channel), 0);
3468         nw64(RX_LOG_VAL2(channel), 0);
3469         nw64(RX_LOG_PAGE_RELO1(channel), 0);
3470         nw64(RX_LOG_PAGE_RELO2(channel), 0);
3471         nw64(RX_LOG_PAGE_HDL(channel), 0);
3472
3473         val  = (u64)np->port << RX_LOG_PAGE_VLD_FUNC_SHIFT;
3474         val |= (RX_LOG_PAGE_VLD_PAGE0 | RX_LOG_PAGE_VLD_PAGE1);
3475         nw64(RX_LOG_PAGE_VLD(channel), val);
3476
3477         return 0;
3478 }
3479
3480 static void niu_rx_channel_wred_init(struct niu *np, struct rx_ring_info *rp)
3481 {
3482         u64 val;
3483
3484         val = (((u64)rp->nonsyn_window << RDC_RED_PARA_WIN_SHIFT) |
3485                ((u64)rp->nonsyn_threshold << RDC_RED_PARA_THRE_SHIFT) |
3486                ((u64)rp->syn_window << RDC_RED_PARA_WIN_SYN_SHIFT) |
3487                ((u64)rp->syn_threshold << RDC_RED_PARA_THRE_SYN_SHIFT));
3488         nw64(RDC_RED_PARA(rp->rx_channel), val);
3489 }
3490
3491 static int niu_compute_rbr_cfig_b(struct rx_ring_info *rp, u64 *ret)
3492 {
3493         u64 val = 0;
3494
3495         switch (rp->rbr_block_size) {
3496         case 4 * 1024:
3497                 val |= (RBR_BLKSIZE_4K << RBR_CFIG_B_BLKSIZE_SHIFT);
3498                 break;
3499         case 8 * 1024:
3500                 val |= (RBR_BLKSIZE_8K << RBR_CFIG_B_BLKSIZE_SHIFT);
3501                 break;
3502         case 16 * 1024:
3503                 val |= (RBR_BLKSIZE_16K << RBR_CFIG_B_BLKSIZE_SHIFT);
3504                 break;
3505         case 32 * 1024:
3506                 val |= (RBR_BLKSIZE_32K << RBR_CFIG_B_BLKSIZE_SHIFT);
3507                 break;
3508         default:
3509                 return -EINVAL;
3510         }
3511         val |= RBR_CFIG_B_VLD2;
3512         switch (rp->rbr_sizes[2]) {
3513         case 2 * 1024:
3514                 val |= (RBR_BUFSZ2_2K << RBR_CFIG_B_BUFSZ2_SHIFT);
3515                 break;
3516         case 4 * 1024:
3517                 val |= (RBR_BUFSZ2_4K << RBR_CFIG_B_BUFSZ2_SHIFT);
3518                 break;
3519         case 8 * 1024:
3520                 val |= (RBR_BUFSZ2_8K << RBR_CFIG_B_BUFSZ2_SHIFT);
3521                 break;
3522         case 16 * 1024:
3523                 val |= (RBR_BUFSZ2_16K << RBR_CFIG_B_BUFSZ2_SHIFT);
3524                 break;
3525
3526         default:
3527                 return -EINVAL;
3528         }
3529         val |= RBR_CFIG_B_VLD1;
3530         switch (rp->rbr_sizes[1]) {
3531         case 1 * 1024:
3532                 val |= (RBR_BUFSZ1_1K << RBR_CFIG_B_BUFSZ1_SHIFT);
3533                 break;
3534         case 2 * 1024:
3535                 val |= (RBR_BUFSZ1_2K << RBR_CFIG_B_BUFSZ1_SHIFT);
3536                 break;
3537         case 4 * 1024:
3538                 val |= (RBR_BUFSZ1_4K << RBR_CFIG_B_BUFSZ1_SHIFT);
3539                 break;
3540         case 8 * 1024:
3541                 val |= (RBR_BUFSZ1_8K << RBR_CFIG_B_BUFSZ1_SHIFT);
3542                 break;
3543
3544         default:
3545                 return -EINVAL;
3546         }
3547         val |= RBR_CFIG_B_VLD0;
3548         switch (rp->rbr_sizes[0]) {
3549         case 256:
3550                 val |= (RBR_BUFSZ0_256 << RBR_CFIG_B_BUFSZ0_SHIFT);
3551                 break;
3552         case 512:
3553                 val |= (RBR_BUFSZ0_512 << RBR_CFIG_B_BUFSZ0_SHIFT);
3554                 break;
3555         case 1 * 1024:
3556                 val |= (RBR_BUFSZ0_1K << RBR_CFIG_B_BUFSZ0_SHIFT);
3557                 break;
3558         case 2 * 1024:
3559                 val |= (RBR_BUFSZ0_2K << RBR_CFIG_B_BUFSZ0_SHIFT);
3560                 break;
3561
3562         default:
3563                 return -EINVAL;
3564         }
3565
3566         *ret = val;
3567         return 0;
3568 }
3569
3570 static int niu_enable_rx_channel(struct niu *np, int channel, int on)
3571 {
3572         u64 val = nr64(RXDMA_CFIG1(channel));
3573         int limit;
3574
3575         if (on)
3576                 val |= RXDMA_CFIG1_EN;
3577         else
3578                 val &= ~RXDMA_CFIG1_EN;
3579         nw64(RXDMA_CFIG1(channel), val);
3580
3581         limit = 1000;
3582         while (--limit > 0) {
3583                 if (nr64(RXDMA_CFIG1(channel)) & RXDMA_CFIG1_QST)
3584                         break;
3585                 udelay(10);
3586         }
3587         if (limit <= 0)
3588                 return -ENODEV;
3589         return 0;
3590 }
3591
3592 static int niu_init_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
3593 {
3594         int err, channel = rp->rx_channel;
3595         u64 val;
3596
3597         err = niu_rx_channel_reset(np, channel);
3598         if (err)
3599                 return err;
3600
3601         err = niu_rx_channel_lpage_init(np, channel);
3602         if (err)
3603                 return err;
3604
3605         niu_rx_channel_wred_init(np, rp);
3606
3607         nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_RBR_EMPTY);
3608         nw64(RX_DMA_CTL_STAT(channel),
3609              (RX_DMA_CTL_STAT_MEX |
3610               RX_DMA_CTL_STAT_RCRTHRES |
3611               RX_DMA_CTL_STAT_RCRTO |
3612               RX_DMA_CTL_STAT_RBR_EMPTY));
3613         nw64(RXDMA_CFIG1(channel), rp->mbox_dma >> 32);
3614         nw64(RXDMA_CFIG2(channel), (rp->mbox_dma & 0x00000000ffffffc0));
3615         nw64(RBR_CFIG_A(channel),
3616              ((u64)rp->rbr_table_size << RBR_CFIG_A_LEN_SHIFT) |
3617              (rp->rbr_dma & (RBR_CFIG_A_STADDR_BASE | RBR_CFIG_A_STADDR)));
3618         err = niu_compute_rbr_cfig_b(rp, &val);
3619         if (err)
3620                 return err;
3621         nw64(RBR_CFIG_B(channel), val);
3622         nw64(RCRCFIG_A(channel),
3623              ((u64)rp->rcr_table_size << RCRCFIG_A_LEN_SHIFT) |
3624              (rp->rcr_dma & (RCRCFIG_A_STADDR_BASE | RCRCFIG_A_STADDR)));
3625         nw64(RCRCFIG_B(channel),
3626              ((u64)rp->rcr_pkt_threshold << RCRCFIG_B_PTHRES_SHIFT) |
3627              RCRCFIG_B_ENTOUT |
3628              ((u64)rp->rcr_timeout << RCRCFIG_B_TIMEOUT_SHIFT));
3629
3630         err = niu_enable_rx_channel(np, channel, 1);
3631         if (err)
3632                 return err;
3633
3634         nw64(RBR_KICK(channel), rp->rbr_index);
3635
3636         val = nr64(RX_DMA_CTL_STAT(channel));
3637         val |= RX_DMA_CTL_STAT_RBR_EMPTY;
3638         nw64(RX_DMA_CTL_STAT(channel), val);
3639
3640         return 0;
3641 }
3642
3643 static int niu_init_rx_channels(struct niu *np)
3644 {
3645         unsigned long flags;
3646         u64 seed = jiffies_64;
3647         int err, i;
3648
3649         niu_lock_parent(np, flags);
3650         nw64(RX_DMA_CK_DIV, np->parent->rxdma_clock_divider);
3651         nw64(RED_RAN_INIT, RED_RAN_INIT_OPMODE | (seed & RED_RAN_INIT_VAL));
3652         niu_unlock_parent(np, flags);
3653
3654         /* XXX RXDMA 32bit mode? XXX */
3655
3656         niu_init_rdc_groups(np);
3657         niu_init_drr_weight(np);
3658
3659         err = niu_init_hostinfo(np);
3660         if (err)
3661                 return err;
3662
3663         for (i = 0; i < np->num_rx_rings; i++) {
3664                 struct rx_ring_info *rp = &np->rx_rings[i];
3665
3666                 err = niu_init_one_rx_channel(np, rp);
3667                 if (err)
3668                         return err;
3669         }
3670
3671         return 0;
3672 }
3673
3674 static int niu_set_ip_frag_rule(struct niu *np)
3675 {
3676         struct niu_parent *parent = np->parent;
3677         struct niu_classifier *cp = &np->clas;
3678         struct niu_tcam_entry *tp;
3679         int index, err;
3680
3681         /* XXX fix this allocation scheme XXX */
3682         index = cp->tcam_index;
3683         tp = &parent->tcam[index];
3684
3685         /* Note that the noport bit is the same in both ipv4 and
3686          * ipv6 format TCAM entries.
3687          */
3688         memset(tp, 0, sizeof(*tp));
3689         tp->key[1] = TCAM_V4KEY1_NOPORT;
3690         tp->key_mask[1] = TCAM_V4KEY1_NOPORT;
3691         tp->assoc_data = (TCAM_ASSOCDATA_TRES_USE_OFFSET |
3692                           ((u64)0 << TCAM_ASSOCDATA_OFFSET_SHIFT));
3693         err = tcam_write(np, index, tp->key, tp->key_mask);
3694         if (err)
3695                 return err;
3696         err = tcam_assoc_write(np, index, tp->assoc_data);
3697         if (err)
3698                 return err;
3699
3700         return 0;
3701 }
3702
3703 static int niu_init_classifier_hw(struct niu *np)
3704 {
3705         struct niu_parent *parent = np->parent;
3706         struct niu_classifier *cp = &np->clas;
3707         int i, err;
3708
3709         nw64(H1POLY, cp->h1_init);
3710         nw64(H2POLY, cp->h2_init);
3711
3712         err = niu_init_hostinfo(np);
3713         if (err)
3714                 return err;
3715
3716         for (i = 0; i < ENET_VLAN_TBL_NUM_ENTRIES; i++) {
3717                 struct niu_vlan_rdc *vp = &cp->vlan_mappings[i];
3718
3719                 vlan_tbl_write(np, i, np->port,
3720                                vp->vlan_pref, vp->rdc_num);
3721         }
3722
3723         for (i = 0; i < cp->num_alt_mac_mappings; i++) {
3724                 struct niu_altmac_rdc *ap = &cp->alt_mac_mappings[i];
3725
3726                 err = niu_set_alt_mac_rdc_table(np, ap->alt_mac_num,
3727                                                 ap->rdc_num, ap->mac_pref);
3728                 if (err)
3729                         return err;
3730         }
3731
3732         for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_SCTP_IPV6; i++) {
3733                 int index = i - CLASS_CODE_USER_PROG1;
3734
3735                 err = niu_set_tcam_key(np, i, parent->tcam_key[index]);
3736                 if (err)
3737                         return err;
3738                 err = niu_set_flow_key(np, i, parent->flow_key[index]);
3739                 if (err)
3740                         return err;
3741         }
3742
3743         err = niu_set_ip_frag_rule(np);
3744         if (err)
3745                 return err;
3746
3747         tcam_enable(np, 1);
3748
3749         return 0;
3750 }
3751
3752 static int niu_zcp_write(struct niu *np, int index, u64 *data)
3753 {
3754         nw64(ZCP_RAM_DATA0, data[0]);
3755         nw64(ZCP_RAM_DATA1, data[1]);
3756         nw64(ZCP_RAM_DATA2, data[2]);
3757         nw64(ZCP_RAM_DATA3, data[3]);
3758         nw64(ZCP_RAM_DATA4, data[4]);
3759         nw64(ZCP_RAM_BE, ZCP_RAM_BE_VAL);
3760         nw64(ZCP_RAM_ACC,
3761              (ZCP_RAM_ACC_WRITE |
3762               (0 << ZCP_RAM_ACC_ZFCID_SHIFT) |
3763               (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT)));
3764
3765         return niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
3766                                    1000, 100);
3767 }
3768
3769 static int niu_zcp_read(struct niu *np, int index, u64 *data)
3770 {
3771         int err;
3772
3773         err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
3774                                   1000, 100);
3775         if (err) {
3776                 dev_err(np->device, PFX "%s: ZCP read busy won't clear, "
3777                         "ZCP_RAM_ACC[%llx]\n", np->dev->name,
3778                         (unsigned long long) nr64(ZCP_RAM_ACC));
3779                 return err;
3780         }
3781
3782         nw64(ZCP_RAM_ACC,
3783              (ZCP_RAM_ACC_READ |
3784               (0 << ZCP_RAM_ACC_ZFCID_SHIFT) |
3785               (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT)));
3786
3787         err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
3788                                   1000, 100);
3789         if (err) {
3790                 dev_err(np->device, PFX "%s: ZCP read busy2 won't clear, "
3791                         "ZCP_RAM_ACC[%llx]\n", np->dev->name,
3792                         (unsigned long long) nr64(ZCP_RAM_ACC));
3793                 return err;
3794         }
3795
3796         data[0] = nr64(ZCP_RAM_DATA0);
3797         data[1] = nr64(ZCP_RAM_DATA1);
3798         data[2] = nr64(ZCP_RAM_DATA2);
3799         data[3] = nr64(ZCP_RAM_DATA3);
3800         data[4] = nr64(ZCP_RAM_DATA4);
3801
3802         return 0;
3803 }
3804
3805 static void niu_zcp_cfifo_reset(struct niu *np)
3806 {
3807         u64 val = nr64(RESET_CFIFO);
3808
3809         val |= RESET_CFIFO_RST(np->port);
3810         nw64(RESET_CFIFO, val);
3811         udelay(10);
3812
3813         val &= ~RESET_CFIFO_RST(np->port);
3814         nw64(RESET_CFIFO, val);
3815 }
3816
3817 static int niu_init_zcp(struct niu *np)
3818 {
3819         u64 data[5], rbuf[5];
3820         int i, max, err;
3821
3822         if (np->parent->plat_type != PLAT_TYPE_NIU) {
3823                 if (np->port == 0 || np->port == 1)
3824                         max = ATLAS_P0_P1_CFIFO_ENTRIES;
3825                 else
3826                         max = ATLAS_P2_P3_CFIFO_ENTRIES;
3827         } else
3828                 max = NIU_CFIFO_ENTRIES;
3829
3830         data[0] = 0;
3831         data[1] = 0;
3832         data[2] = 0;
3833         data[3] = 0;
3834         data[4] = 0;
3835
3836         for (i = 0; i < max; i++) {
3837                 err = niu_zcp_write(np, i, data);
3838                 if (err)
3839                         return err;
3840                 err = niu_zcp_read(np, i, rbuf);
3841                 if (err)
3842                         return err;
3843         }
3844
3845         niu_zcp_cfifo_reset(np);
3846         nw64(CFIFO_ECC(np->port), 0);
3847         nw64(ZCP_INT_STAT, ZCP_INT_STAT_ALL);
3848         (void) nr64(ZCP_INT_STAT);
3849         nw64(ZCP_INT_MASK, ZCP_INT_MASK_ALL);
3850
3851         return 0;
3852 }
3853
3854 static void niu_ipp_write(struct niu *np, int index, u64 *data)
3855 {
3856         u64 val = nr64_ipp(IPP_CFIG);
3857
3858         nw64_ipp(IPP_CFIG, val | IPP_CFIG_DFIFO_PIO_W);
3859         nw64_ipp(IPP_DFIFO_WR_PTR, index);
3860         nw64_ipp(IPP_DFIFO_WR0, data[0]);
3861         nw64_ipp(IPP_DFIFO_WR1, data[1]);
3862         nw64_ipp(IPP_DFIFO_WR2, data[2]);
3863         nw64_ipp(IPP_DFIFO_WR3, data[3]);
3864         nw64_ipp(IPP_DFIFO_WR4, data[4]);
3865         nw64_ipp(IPP_CFIG, val & ~IPP_CFIG_DFIFO_PIO_W);
3866 }
3867
3868 static void niu_ipp_read(struct niu *np, int index, u64 *data)
3869 {
3870         nw64_ipp(IPP_DFIFO_RD_PTR, index);
3871         data[0] = nr64_ipp(IPP_DFIFO_RD0);
3872         data[1] = nr64_ipp(IPP_DFIFO_RD1);
3873         data[2] = nr64_ipp(IPP_DFIFO_RD2);
3874         data[3] = nr64_ipp(IPP_DFIFO_RD3);
3875         data[4] = nr64_ipp(IPP_DFIFO_RD4);
3876 }
3877
3878 static int niu_ipp_reset(struct niu *np)
3879 {
3880         return niu_set_and_wait_clear_ipp(np, IPP_CFIG, IPP_CFIG_SOFT_RST,
3881                                           1000, 100, "IPP_CFIG");
3882 }
3883
3884 static int niu_init_ipp(struct niu *np)
3885 {
3886         u64 data[5], rbuf[5], val;
3887         int i, max, err;
3888
3889         if (np->parent->plat_type != PLAT_TYPE_NIU) {
3890                 if (np->port == 0 || np->port == 1)
3891                         max = ATLAS_P0_P1_DFIFO_ENTRIES;
3892                 else
3893                         max = ATLAS_P2_P3_DFIFO_ENTRIES;
3894         } else
3895                 max = NIU_DFIFO_ENTRIES;
3896
3897         data[0] = 0;
3898         data[1] = 0;
3899         data[2] = 0;
3900         data[3] = 0;
3901         data[4] = 0;
3902
3903         for (i = 0; i < max; i++) {
3904                 niu_ipp_write(np, i, data);
3905                 niu_ipp_read(np, i, rbuf);
3906         }
3907
3908         (void) nr64_ipp(IPP_INT_STAT);
3909         (void) nr64_ipp(IPP_INT_STAT);
3910
3911         err = niu_ipp_reset(np);
3912         if (err)
3913                 return err;
3914
3915         (void) nr64_ipp(IPP_PKT_DIS);
3916         (void) nr64_ipp(IPP_BAD_CS_CNT);
3917         (void) nr64_ipp(IPP_ECC);
3918
3919         (void) nr64_ipp(IPP_INT_STAT);
3920
3921         nw64_ipp(IPP_MSK, ~IPP_MSK_ALL);
3922
3923         val = nr64_ipp(IPP_CFIG);
3924         val &= ~IPP_CFIG_IP_MAX_PKT;
3925         val |= (IPP_CFIG_IPP_ENABLE |
3926                 IPP_CFIG_DFIFO_ECC_EN |
3927                 IPP_CFIG_DROP_BAD_CRC |
3928                 IPP_CFIG_CKSUM_EN |
3929                 (0x1ffff << IPP_CFIG_IP_MAX_PKT_SHIFT));
3930         nw64_ipp(IPP_CFIG, val);
3931
3932         return 0;
3933 }
3934
3935 static void niu_handle_led(struct niu *np, int status)
3936 {
3937         u64 val;
3938         val = nr64_mac(XMAC_CONFIG);
3939
3940         if ((np->flags & NIU_FLAGS_10G) != 0 &&
3941             (np->flags & NIU_FLAGS_FIBER) != 0) {
3942                 if (status) {
3943                         val |= XMAC_CONFIG_LED_POLARITY;
3944                         val &= ~XMAC_CONFIG_FORCE_LED_ON;
3945                 } else {
3946                         val |= XMAC_CONFIG_FORCE_LED_ON;
3947                         val &= ~XMAC_CONFIG_LED_POLARITY;
3948                 }
3949         }
3950
3951         nw64_mac(XMAC_CONFIG, val);
3952 }
3953
3954 static void niu_init_xif_xmac(struct niu *np)
3955 {
3956         struct niu_link_config *lp = &np->link_config;
3957         u64 val;
3958
3959         val = nr64_mac(XMAC_CONFIG);
3960         val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC;
3961
3962         val |= XMAC_CONFIG_TX_OUTPUT_EN;
3963
3964         if (lp->loopback_mode == LOOPBACK_MAC) {
3965                 val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC;
3966                 val |= XMAC_CONFIG_LOOPBACK;
3967         } else {
3968                 val &= ~XMAC_CONFIG_LOOPBACK;
3969         }
3970
3971         if (np->flags & NIU_FLAGS_10G) {
3972                 val &= ~XMAC_CONFIG_LFS_DISABLE;
3973         } else {
3974                 val |= XMAC_CONFIG_LFS_DISABLE;
3975                 if (!(np->flags & NIU_FLAGS_FIBER))
3976                         val |= XMAC_CONFIG_1G_PCS_BYPASS;
3977                 else
3978                         val &= ~XMAC_CONFIG_1G_PCS_BYPASS;
3979         }
3980
3981         val &= ~XMAC_CONFIG_10G_XPCS_BYPASS;
3982
3983         if (lp->active_speed == SPEED_100)
3984                 val |= XMAC_CONFIG_SEL_CLK_25MHZ;
3985         else
3986                 val &= ~XMAC_CONFIG_SEL_CLK_25MHZ;
3987
3988         nw64_mac(XMAC_CONFIG, val);
3989
3990         val = nr64_mac(XMAC_CONFIG);
3991         val &= ~XMAC_CONFIG_MODE_MASK;
3992         if (np->flags & NIU_FLAGS_10G) {
3993                 val |= XMAC_CONFIG_MODE_XGMII;
3994         } else {
3995                 if (lp->active_speed == SPEED_100)
3996                         val |= XMAC_CONFIG_MODE_MII;
3997                 else
3998                         val |= XMAC_CONFIG_MODE_GMII;
3999         }
4000
4001         nw64_mac(XMAC_CONFIG, val);
4002 }
4003
4004 static void niu_init_xif_bmac(struct niu *np)
4005 {
4006         struct niu_link_config *lp = &np->link_config;
4007         u64 val;
4008
4009         val = BMAC_XIF_CONFIG_TX_OUTPUT_EN;
4010
4011         if (lp->loopback_mode == LOOPBACK_MAC)
4012                 val |= BMAC_XIF_CONFIG_MII_LOOPBACK;
4013         else
4014                 val &= ~BMAC_XIF_CONFIG_MII_LOOPBACK;
4015
4016         if (lp->active_speed == SPEED_1000)
4017                 val |= BMAC_XIF_CONFIG_GMII_MODE;
4018         else
4019                 val &= ~BMAC_XIF_CONFIG_GMII_MODE;
4020
4021         val &= ~(BMAC_XIF_CONFIG_LINK_LED |
4022                  BMAC_XIF_CONFIG_LED_POLARITY);
4023
4024         if (!(np->flags & NIU_FLAGS_10G) &&
4025             !(np->flags & NIU_FLAGS_FIBER) &&
4026             lp->active_speed == SPEED_100)
4027                 val |= BMAC_XIF_CONFIG_25MHZ_CLOCK;
4028         else
4029                 val &= ~BMAC_XIF_CONFIG_25MHZ_CLOCK;
4030
4031         nw64_mac(BMAC_XIF_CONFIG, val);
4032 }
4033
4034 static void niu_init_xif(struct niu *np)
4035 {
4036         if (np->flags & NIU_FLAGS_XMAC)
4037                 niu_init_xif_xmac(np);
4038         else
4039                 niu_init_xif_bmac(np);
4040 }
4041
4042 static void niu_pcs_mii_reset(struct niu *np)
4043 {
4044         u64 val = nr64_pcs(PCS_MII_CTL);
4045         val |= PCS_MII_CTL_RST;
4046         nw64_pcs(PCS_MII_CTL, val);
4047 }
4048
4049 static void niu_xpcs_reset(struct niu *np)
4050 {
4051         u64 val = nr64_xpcs(XPCS_CONTROL1);
4052         val |= XPCS_CONTROL1_RESET;
4053         nw64_xpcs(XPCS_CONTROL1, val);
4054 }
4055
4056 static int niu_init_pcs(struct niu *np)
4057 {
4058         struct niu_link_config *lp = &np->link_config;
4059         u64 val;
4060
4061         switch (np->flags & (NIU_FLAGS_10G | NIU_FLAGS_FIBER)) {
4062         case NIU_FLAGS_FIBER:
4063                 /* 1G fiber */
4064                 nw64_pcs(PCS_CONF, PCS_CONF_MASK | PCS_CONF_ENABLE);
4065                 nw64_pcs(PCS_DPATH_MODE, 0);
4066                 niu_pcs_mii_reset(np);
4067                 break;
4068
4069         case NIU_FLAGS_10G:
4070         case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
4071                 if (!(np->flags & NIU_FLAGS_XMAC))
4072                         return -EINVAL;
4073
4074                 /* 10G copper or fiber */
4075                 val = nr64_mac(XMAC_CONFIG);
4076                 val &= ~XMAC_CONFIG_10G_XPCS_BYPASS;
4077                 nw64_mac(XMAC_CONFIG, val);
4078
4079                 niu_xpcs_reset(np);
4080
4081                 val = nr64_xpcs(XPCS_CONTROL1);
4082                 if (lp->loopback_mode == LOOPBACK_PHY)
4083                         val |= XPCS_CONTROL1_LOOPBACK;
4084                 else
4085                         val &= ~XPCS_CONTROL1_LOOPBACK;
4086                 nw64_xpcs(XPCS_CONTROL1, val);
4087
4088                 nw64_xpcs(XPCS_DESKEW_ERR_CNT, 0);
4089                 (void) nr64_xpcs(XPCS_SYMERR_CNT01);
4090                 (void) nr64_xpcs(XPCS_SYMERR_CNT23);
4091                 break;
4092
4093         case 0:
4094                 /* 1G copper */
4095                 nw64_pcs(PCS_DPATH_MODE, PCS_DPATH_MODE_MII);
4096                 niu_pcs_mii_reset(np);
4097                 break;
4098
4099         default:
4100                 return -EINVAL;
4101         }
4102
4103         return 0;
4104 }
4105
4106 static int niu_reset_tx_xmac(struct niu *np)
4107 {
4108         return niu_set_and_wait_clear_mac(np, XTXMAC_SW_RST,
4109                                           (XTXMAC_SW_RST_REG_RS |
4110                                            XTXMAC_SW_RST_SOFT_RST),
4111                                           1000, 100, "XTXMAC_SW_RST");
4112 }
4113
4114 static int niu_reset_tx_bmac(struct niu *np)
4115 {
4116         int limit;
4117
4118         nw64_mac(BTXMAC_SW_RST, BTXMAC_SW_RST_RESET);
4119         limit = 1000;
4120         while (--limit >= 0) {
4121                 if (!(nr64_mac(BTXMAC_SW_RST) & BTXMAC_SW_RST_RESET))
4122                         break;
4123                 udelay(100);
4124         }
4125         if (limit < 0) {
4126                 dev_err(np->device, PFX "Port %u TX BMAC would not reset, "
4127                         "BTXMAC_SW_RST[%llx]\n",
4128                         np->port,
4129                         (unsigned long long) nr64_mac(BTXMAC_SW_RST));
4130                 return -ENODEV;
4131         }
4132
4133         return 0;
4134 }
4135
4136 static int niu_reset_tx_mac(struct niu *np)
4137 {
4138         if (np->flags & NIU_FLAGS_XMAC)
4139                 return niu_reset_tx_xmac(np);
4140         else
4141                 return niu_reset_tx_bmac(np);
4142 }
4143
4144 static void niu_init_tx_xmac(struct niu *np, u64 min, u64 max)
4145 {
4146         u64 val;
4147
4148         val = nr64_mac(XMAC_MIN);
4149         val &= ~(XMAC_MIN_TX_MIN_PKT_SIZE |
4150                  XMAC_MIN_RX_MIN_PKT_SIZE);
4151         val |= (min << XMAC_MIN_RX_MIN_PKT_SIZE_SHFT);
4152         val |= (min << XMAC_MIN_TX_MIN_PKT_SIZE_SHFT);
4153         nw64_mac(XMAC_MIN, val);
4154
4155         nw64_mac(XMAC_MAX, max);
4156
4157         nw64_mac(XTXMAC_STAT_MSK, ~(u64)0);
4158
4159         val = nr64_mac(XMAC_IPG);
4160         if (np->flags & NIU_FLAGS_10G) {
4161                 val &= ~XMAC_IPG_IPG_XGMII;
4162                 val |= (IPG_12_15_XGMII << XMAC_IPG_IPG_XGMII_SHIFT);
4163         } else {
4164                 val &= ~XMAC_IPG_IPG_MII_GMII;
4165                 val |= (IPG_12_MII_GMII << XMAC_IPG_IPG_MII_GMII_SHIFT);
4166         }
4167         nw64_mac(XMAC_IPG, val);
4168
4169         val = nr64_mac(XMAC_CONFIG);
4170         val &= ~(XMAC_CONFIG_ALWAYS_NO_CRC |
4171                  XMAC_CONFIG_STRETCH_MODE |
4172                  XMAC_CONFIG_VAR_MIN_IPG_EN |
4173                  XMAC_CONFIG_TX_ENABLE);
4174         nw64_mac(XMAC_CONFIG, val);
4175
4176         nw64_mac(TXMAC_FRM_CNT, 0);
4177         nw64_mac(TXMAC_BYTE_CNT, 0);
4178 }
4179
4180 static void niu_init_tx_bmac(struct niu *np, u64 min, u64 max)
4181 {
4182         u64 val;
4183
4184         nw64_mac(BMAC_MIN_FRAME, min);
4185         nw64_mac(BMAC_MAX_FRAME, max);
4186
4187         nw64_mac(BTXMAC_STATUS_MASK, ~(u64)0);
4188         nw64_mac(BMAC_CTRL_TYPE, 0x8808);
4189         nw64_mac(BMAC_PREAMBLE_SIZE, 7);
4190
4191         val = nr64_mac(BTXMAC_CONFIG);
4192         val &= ~(BTXMAC_CONFIG_FCS_DISABLE |
4193                  BTXMAC_CONFIG_ENABLE);
4194         nw64_mac(BTXMAC_CONFIG, val);
4195 }
4196
4197 static void niu_init_tx_mac(struct niu *np)
4198 {
4199         u64 min, max;
4200
4201         min = 64;
4202         if (np->dev->mtu > ETH_DATA_LEN)
4203                 max = 9216;
4204         else
4205                 max = 1522;
4206
4207         /* The XMAC_MIN register only accepts values for TX min which
4208          * have the low 3 bits cleared.
4209          */
4210         BUILD_BUG_ON(min & 0x7);
4211
4212         if (np->flags & NIU_FLAGS_XMAC)
4213                 niu_init_tx_xmac(np, min, max);
4214         else
4215                 niu_init_tx_bmac(np, min, max);
4216 }
4217
4218 static int niu_reset_rx_xmac(struct niu *np)
4219 {
4220         int limit;
4221
4222         nw64_mac(XRXMAC_SW_RST,
4223                  XRXMAC_SW_RST_REG_RS | XRXMAC_SW_RST_SOFT_RST);
4224         limit = 1000;
4225         while (--limit >= 0) {
4226                 if (!(nr64_mac(XRXMAC_SW_RST) & (XRXMAC_SW_RST_REG_RS |
4227                                                  XRXMAC_SW_RST_SOFT_RST)))
4228                     break;
4229                 udelay(100);
4230         }
4231         if (limit < 0) {
4232                 dev_err(np->device, PFX "Port %u RX XMAC would not reset, "
4233                         "XRXMAC_SW_RST[%llx]\n",
4234                         np->port,
4235                         (unsigned long long) nr64_mac(XRXMAC_SW_RST));
4236                 return -ENODEV;
4237         }
4238
4239         return 0;
4240 }
4241
4242 static int niu_reset_rx_bmac(struct niu *np)
4243 {
4244         int limit;
4245
4246         nw64_mac(BRXMAC_SW_RST, BRXMAC_SW_RST_RESET);
4247         limit = 1000;
4248         while (--limit >= 0) {
4249                 if (!(nr64_mac(BRXMAC_SW_RST) & BRXMAC_SW_RST_RESET))
4250                         break;
4251                 udelay(100);
4252         }
4253         if (limit < 0) {
4254                 dev_err(np->device, PFX "Port %u RX BMAC would not reset, "
4255                         "BRXMAC_SW_RST[%llx]\n",
4256                         np->port,
4257                         (unsigned long long) nr64_mac(BRXMAC_SW_RST));
4258                 return -ENODEV;
4259         }
4260
4261         return 0;
4262 }
4263
4264 static int niu_reset_rx_mac(struct niu *np)
4265 {
4266         if (np->flags & NIU_FLAGS_XMAC)
4267                 return niu_reset_rx_xmac(np);
4268         else
4269                 return niu_reset_rx_bmac(np);
4270 }
4271
4272 static void niu_init_rx_xmac(struct niu *np)
4273 {
4274         struct niu_parent *parent = np->parent;
4275         struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
4276         int first_rdc_table = tp->first_table_num;
4277         unsigned long i;
4278         u64 val;
4279
4280         nw64_mac(XMAC_ADD_FILT0, 0);
4281         nw64_mac(XMAC_ADD_FILT1, 0);
4282         nw64_mac(XMAC_ADD_FILT2, 0);
4283         nw64_mac(XMAC_ADD_FILT12_MASK, 0);
4284         nw64_mac(XMAC_ADD_FILT00_MASK, 0);
4285         for (i = 0; i < MAC_NUM_HASH; i++)
4286                 nw64_mac(XMAC_HASH_TBL(i), 0);
4287         nw64_mac(XRXMAC_STAT_MSK, ~(u64)0);
4288         niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
4289         niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
4290
4291         val = nr64_mac(XMAC_CONFIG);
4292         val &= ~(XMAC_CONFIG_RX_MAC_ENABLE |
4293                  XMAC_CONFIG_PROMISCUOUS |
4294                  XMAC_CONFIG_PROMISC_GROUP |
4295                  XMAC_CONFIG_ERR_CHK_DIS |
4296                  XMAC_CONFIG_RX_CRC_CHK_DIS |
4297                  XMAC_CONFIG_RESERVED_MULTICAST |
4298                  XMAC_CONFIG_RX_CODEV_CHK_DIS |
4299                  XMAC_CONFIG_ADDR_FILTER_EN |
4300                  XMAC_CONFIG_RCV_PAUSE_ENABLE |
4301                  XMAC_CONFIG_STRIP_CRC |
4302                  XMAC_CONFIG_PASS_FLOW_CTRL |
4303                  XMAC_CONFIG_MAC2IPP_PKT_CNT_EN);
4304         val |= (XMAC_CONFIG_HASH_FILTER_EN);
4305         nw64_mac(XMAC_CONFIG, val);
4306
4307         nw64_mac(RXMAC_BT_CNT, 0);
4308         nw64_mac(RXMAC_BC_FRM_CNT, 0);
4309         nw64_mac(RXMAC_MC_FRM_CNT, 0);
4310         nw64_mac(RXMAC_FRAG_CNT, 0);
4311         nw64_mac(RXMAC_HIST_CNT1, 0);
4312         nw64_mac(RXMAC_HIST_CNT2, 0);
4313         nw64_mac(RXMAC_HIST_CNT3, 0);
4314         nw64_mac(RXMAC_HIST_CNT4, 0);
4315         nw64_mac(RXMAC_HIST_CNT5, 0);
4316         nw64_mac(RXMAC_HIST_CNT6, 0);
4317         nw64_mac(RXMAC_HIST_CNT7, 0);
4318         nw64_mac(RXMAC_MPSZER_CNT, 0);
4319         nw64_mac(RXMAC_CRC_ER_CNT, 0);
4320         nw64_mac(RXMAC_CD_VIO_CNT, 0);
4321         nw64_mac(LINK_FAULT_CNT, 0);
4322 }
4323
4324 static void niu_init_rx_bmac(struct niu *np)
4325 {
4326         struct niu_parent *parent = np->parent;
4327         struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
4328         int first_rdc_table = tp->first_table_num;
4329         unsigned long i;
4330         u64 val;
4331
4332         nw64_mac(BMAC_ADD_FILT0, 0);
4333         nw64_mac(BMAC_ADD_FILT1, 0);
4334         nw64_mac(BMAC_ADD_FILT2, 0);
4335         nw64_mac(BMAC_ADD_FILT12_MASK, 0);
4336         nw64_mac(BMAC_ADD_FILT00_MASK, 0);
4337         for (i = 0; i < MAC_NUM_HASH; i++)
4338                 nw64_mac(BMAC_HASH_TBL(i), 0);
4339         niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
4340         niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
4341         nw64_mac(BRXMAC_STATUS_MASK, ~(u64)0);
4342
4343         val = nr64_mac(BRXMAC_CONFIG);
4344         val &= ~(BRXMAC_CONFIG_ENABLE |
4345                  BRXMAC_CONFIG_STRIP_PAD |
4346                  BRXMAC_CONFIG_STRIP_FCS |
4347                  BRXMAC_CONFIG_PROMISC |
4348                  BRXMAC_CONFIG_PROMISC_GRP |
4349                  BRXMAC_CONFIG_ADDR_FILT_EN |
4350                  BRXMAC_CONFIG_DISCARD_DIS);
4351         val |= (BRXMAC_CONFIG_HASH_FILT_EN);
4352         nw64_mac(BRXMAC_CONFIG, val);
4353
4354         val = nr64_mac(BMAC_ADDR_CMPEN);
4355         val |= BMAC_ADDR_CMPEN_EN0;
4356         nw64_mac(BMAC_ADDR_CMPEN, val);
4357 }
4358
4359 static void niu_init_rx_mac(struct niu *np)
4360 {
4361         niu_set_primary_mac(np, np->dev->dev_addr);
4362
4363         if (np->flags & NIU_FLAGS_XMAC)
4364                 niu_init_rx_xmac(np);
4365         else
4366                 niu_init_rx_bmac(np);
4367 }
4368
4369 static void niu_enable_tx_xmac(struct niu *np, int on)
4370 {
4371         u64 val = nr64_mac(XMAC_CONFIG);
4372
4373         if (on)
4374                 val |= XMAC_CONFIG_TX_ENABLE;
4375         else
4376                 val &= ~XMAC_CONFIG_TX_ENABLE;
4377         nw64_mac(XMAC_CONFIG, val);
4378 }
4379
4380 static void niu_enable_tx_bmac(struct niu *np, int on)
4381 {
4382         u64 val = nr64_mac(BTXMAC_CONFIG);
4383
4384         if (on)
4385                 val |= BTXMAC_CONFIG_ENABLE;
4386         else
4387                 val &= ~BTXMAC_CONFIG_ENABLE;
4388         nw64_mac(BTXMAC_CONFIG, val);
4389 }
4390
4391 static void niu_enable_tx_mac(struct niu *np, int on)
4392 {
4393         if (np->flags & NIU_FLAGS_XMAC)
4394                 niu_enable_tx_xmac(np, on);
4395         else
4396                 niu_enable_tx_bmac(np, on);
4397 }
4398
4399 static void niu_enable_rx_xmac(struct niu *np, int on)
4400 {
4401         u64 val = nr64_mac(XMAC_CONFIG);
4402
4403         val &= ~(XMAC_CONFIG_HASH_FILTER_EN |
4404                  XMAC_CONFIG_PROMISCUOUS);
4405
4406         if (np->flags & NIU_FLAGS_MCAST)
4407                 val |= XMAC_CONFIG_HASH_FILTER_EN;
4408         if (np->flags & NIU_FLAGS_PROMISC)
4409                 val |= XMAC_CONFIG_PROMISCUOUS;
4410
4411         if (on)
4412                 val |= XMAC_CONFIG_RX_MAC_ENABLE;
4413         else
4414                 val &= ~XMAC_CONFIG_RX_MAC_ENABLE;
4415         nw64_mac(XMAC_CONFIG, val);
4416 }
4417
4418 static void niu_enable_rx_bmac(struct niu *np, int on)
4419 {
4420         u64 val = nr64_mac(BRXMAC_CONFIG);
4421
4422         val &= ~(BRXMAC_CONFIG_HASH_FILT_EN |
4423                  BRXMAC_CONFIG_PROMISC);
4424
4425         if (np->flags & NIU_FLAGS_MCAST)
4426                 val |= BRXMAC_CONFIG_HASH_FILT_EN;
4427         if (np->flags & NIU_FLAGS_PROMISC)
4428                 val |= BRXMAC_CONFIG_PROMISC;
4429
4430         if (on)
4431                 val |= BRXMAC_CONFIG_ENABLE;
4432         else
4433                 val &= ~BRXMAC_CONFIG_ENABLE;
4434         nw64_mac(BRXMAC_CONFIG, val);
4435 }
4436
4437 static void niu_enable_rx_mac(struct niu *np, int on)
4438 {
4439         if (np->flags & NIU_FLAGS_XMAC)
4440                 niu_enable_rx_xmac(np, on);
4441         else
4442                 niu_enable_rx_bmac(np, on);
4443 }
4444
4445 static int niu_init_mac(struct niu *np)
4446 {
4447         int err;
4448
4449         niu_init_xif(np);
4450         err = niu_init_pcs(np);
4451         if (err)
4452                 return err;
4453
4454         err = niu_reset_tx_mac(np);
4455         if (err)
4456                 return err;
4457         niu_init_tx_mac(np);
4458         err = niu_reset_rx_mac(np);
4459         if (err)
4460                 return err;
4461         niu_init_rx_mac(np);
4462
4463         /* This looks hookey but the RX MAC reset we just did will
4464          * undo some of the state we setup in niu_init_tx_mac() so we
4465          * have to call it again.  In particular, the RX MAC reset will
4466          * set the XMAC_MAX register back to it's default value.
4467          */
4468         niu_init_tx_mac(np);
4469         niu_enable_tx_mac(np, 1);
4470
4471         niu_enable_rx_mac(np, 1);
4472
4473         return 0;
4474 }
4475
4476 static void niu_stop_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
4477 {
4478         (void) niu_tx_channel_stop(np, rp->tx_channel);
4479 }
4480
4481 static void niu_stop_tx_channels(struct niu *np)
4482 {
4483         int i;
4484
4485         for (i = 0; i < np->num_tx_rings; i++) {
4486                 struct tx_ring_info *rp = &np->tx_rings[i];
4487
4488                 niu_stop_one_tx_channel(np, rp);
4489         }
4490 }
4491
4492 static void niu_reset_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
4493 {
4494         (void) niu_tx_channel_reset(np, rp->tx_channel);
4495 }
4496
4497 static void niu_reset_tx_channels(struct niu *np)
4498 {
4499         int i;
4500
4501         for (i = 0; i < np->num_tx_rings; i++) {
4502                 struct tx_ring_info *rp = &np->tx_rings[i];
4503
4504                 niu_reset_one_tx_channel(np, rp);
4505         }
4506 }
4507
4508 static void niu_stop_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
4509 {
4510         (void) niu_enable_rx_channel(np, rp->rx_channel, 0);
4511 }
4512
4513 static void niu_stop_rx_channels(struct niu *np)
4514 {
4515         int i;
4516
4517         for (i = 0; i < np->num_rx_rings; i++) {
4518                 struct rx_ring_info *rp = &np->rx_rings[i];
4519
4520                 niu_stop_one_rx_channel(np, rp);
4521         }
4522 }
4523
4524 static void niu_reset_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
4525 {
4526         int channel = rp->rx_channel;
4527
4528         (void) niu_rx_channel_reset(np, channel);
4529         nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_ALL);
4530         nw64(RX_DMA_CTL_STAT(channel), 0);
4531         (void) niu_enable_rx_channel(np, channel, 0);
4532 }
4533
4534 static void niu_reset_rx_channels(struct niu *np)
4535 {
4536         int i;
4537
4538         for (i = 0; i < np->num_rx_rings; i++) {
4539                 struct rx_ring_info *rp = &np->rx_rings[i];
4540
4541                 niu_reset_one_rx_channel(np, rp);
4542         }
4543 }
4544
4545 static void niu_disable_ipp(struct niu *np)
4546 {
4547         u64 rd, wr, val;
4548         int limit;
4549
4550         rd = nr64_ipp(IPP_DFIFO_RD_PTR);
4551         wr = nr64_ipp(IPP_DFIFO_WR_PTR);
4552         limit = 100;
4553         while (--limit >= 0 && (rd != wr)) {
4554                 rd = nr64_ipp(IPP_DFIFO_RD_PTR);
4555                 wr = nr64_ipp(IPP_DFIFO_WR_PTR);
4556         }
4557         if (limit < 0 &&
4558             (rd != 0 && wr != 1)) {
4559                 dev_err(np->device, PFX "%s: IPP would not quiesce, "
4560                         "rd_ptr[%llx] wr_ptr[%llx]\n",
4561                         np->dev->name,
4562                         (unsigned long long) nr64_ipp(IPP_DFIFO_RD_PTR),
4563                         (unsigned long long) nr64_ipp(IPP_DFIFO_WR_PTR));
4564         }
4565
4566         val = nr64_ipp(IPP_CFIG);
4567         val &= ~(IPP_CFIG_IPP_ENABLE |
4568                  IPP_CFIG_DFIFO_ECC_EN |
4569                  IPP_CFIG_DROP_BAD_CRC |
4570                  IPP_CFIG_CKSUM_EN);
4571         nw64_ipp(IPP_CFIG, val);
4572
4573         (void) niu_ipp_reset(np);
4574 }
4575
4576 static int niu_init_hw(struct niu *np)
4577 {
4578         int i, err;
4579
4580         niudbg(IFUP, "%s: Initialize TXC\n", np->dev->name);
4581         niu_txc_enable_port(np, 1);
4582         niu_txc_port_dma_enable(np, 1);
4583         niu_txc_set_imask(np, 0);
4584
4585         niudbg(IFUP, "%s: Initialize TX channels\n", np->dev->name);
4586         for (i = 0; i < np->num_tx_rings; i++) {
4587                 struct tx_ring_info *rp = &np->tx_rings[i];
4588
4589                 err = niu_init_one_tx_channel(np, rp);
4590                 if (err)
4591                         return err;
4592         }
4593
4594         niudbg(IFUP, "%s: Initialize RX channels\n", np->dev->name);
4595         err = niu_init_rx_channels(np);
4596         if (err)
4597                 goto out_uninit_tx_channels;
4598
4599         niudbg(IFUP, "%s: Initialize classifier\n", np->dev->name);
4600         err = niu_init_classifier_hw(np);
4601         if (err)
4602                 goto out_uninit_rx_channels;
4603
4604         niudbg(IFUP, "%s: Initialize ZCP\n", np->dev->name);
4605         err = niu_init_zcp(np);
4606         if (err)
4607                 goto out_uninit_rx_channels;
4608
4609         niudbg(IFUP, "%s: Initialize IPP\n", np->dev->name);
4610         err = niu_init_ipp(np);
4611         if (err)
4612                 goto out_uninit_rx_channels;
4613
4614         niudbg(IFUP, "%s: Initialize MAC\n", np->dev->name);
4615         err = niu_init_mac(np);
4616         if (err)
4617                 goto out_uninit_ipp;
4618
4619         return 0;
4620
4621 out_uninit_ipp:
4622         niudbg(IFUP, "%s: Uninit IPP\n", np->dev->name);
4623         niu_disable_ipp(np);
4624
4625 out_uninit_rx_channels:
4626         niudbg(IFUP, "%s: Uninit RX channels\n", np->dev->name);
4627         niu_stop_rx_channels(np);
4628         niu_reset_rx_channels(np);
4629
4630 out_uninit_tx_channels:
4631         niudbg(IFUP, "%s: Uninit TX channels\n", np->dev->name);
4632         niu_stop_tx_channels(np);
4633         niu_reset_tx_channels(np);
4634
4635         return err;
4636 }
4637
4638 static void niu_stop_hw(struct niu *np)
4639 {
4640         niudbg(IFDOWN, "%s: Disable interrupts\n", np->dev->name);
4641         niu_enable_interrupts(np, 0);
4642
4643         niudbg(IFDOWN, "%s: Disable RX MAC\n", np->dev->name);
4644         niu_enable_rx_mac(np, 0);
4645
4646         niudbg(IFDOWN, "%s: Disable IPP\n", np->dev->name);
4647         niu_disable_ipp(np);
4648
4649         niudbg(IFDOWN, "%s: Stop TX channels\n", np->dev->name);
4650         niu_stop_tx_channels(np);
4651
4652         niudbg(IFDOWN, "%s: Stop RX channels\n", np->dev->name);
4653         niu_stop_rx_channels(np);
4654
4655         niudbg(IFDOWN, "%s: Reset TX channels\n", np->dev->name);
4656         niu_reset_tx_channels(np);
4657
4658         niudbg(IFDOWN, "%s: Reset RX channels\n", np->dev->name);
4659         niu_reset_rx_channels(np);
4660 }
4661
4662 static int niu_request_irq(struct niu *np)
4663 {
4664         int i, j, err;
4665
4666         err = 0;
4667         for (i = 0; i < np->num_ldg; i++) {
4668                 struct niu_ldg *lp = &np->ldg[i];
4669
4670                 err = request_irq(lp->irq, niu_interrupt,
4671                                   IRQF_SHARED | IRQF_SAMPLE_RANDOM,
4672                                   np->dev->name, lp);
4673                 if (err)
4674                         goto out_free_irqs;
4675
4676         }
4677
4678         return 0;
4679
4680 out_free_irqs:
4681         for (j = 0; j < i; j++) {
4682                 struct niu_ldg *lp = &np->ldg[j];
4683
4684                 free_irq(lp->irq, lp);
4685         }
4686         return err;
4687 }
4688
4689 static void niu_free_irq(struct niu *np)
4690 {
4691         int i;
4692
4693         for (i = 0; i < np->num_ldg; i++) {
4694                 struct niu_ldg *lp = &np->ldg[i];
4695
4696                 free_irq(lp->irq, lp);
4697         }
4698 }
4699
4700 static void niu_enable_napi(struct niu *np)
4701 {
4702         int i;
4703
4704         for (i = 0; i < np->num_ldg; i++)
4705                 napi_enable(&np->ldg[i].napi);
4706 }
4707
4708 static void niu_disable_napi(struct niu *np)
4709 {
4710         int i;
4711
4712         for (i = 0; i < np->num_ldg; i++)
4713                 napi_disable(&np->ldg[i].napi);
4714 }
4715
4716 static int niu_open(struct net_device *dev)
4717 {
4718         struct niu *np = netdev_priv(dev);
4719         int err;
4720
4721         netif_carrier_off(dev);
4722
4723         err = niu_alloc_channels(np);
4724         if (err)
4725                 goto out_err;
4726
4727         err = niu_enable_interrupts(np, 0);
4728         if (err)
4729                 goto out_free_channels;
4730
4731         err = niu_request_irq(np);
4732         if (err)
4733                 goto out_free_channels;
4734
4735         niu_enable_napi(np);
4736
4737         spin_lock_irq(&np->lock);
4738
4739         err = niu_init_hw(np);
4740         if (!err) {
4741                 init_timer(&np->timer);
4742                 np->timer.expires = jiffies + HZ;
4743                 np->timer.data = (unsigned long) np;
4744                 np->timer.function = niu_timer;
4745
4746                 err = niu_enable_interrupts(np, 1);
4747                 if (err)
4748                         niu_stop_hw(np);
4749         }
4750
4751         spin_unlock_irq(&np->lock);
4752
4753         if (err) {
4754                 niu_disable_napi(np);
4755                 goto out_free_irq;
4756         }
4757
4758         netif_start_queue(dev);
4759
4760         if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
4761                 netif_carrier_on(dev);
4762
4763         add_timer(&np->timer);
4764
4765         return 0;
4766
4767 out_free_irq:
4768         niu_free_irq(np);
4769
4770 out_free_channels:
4771         niu_free_channels(np);
4772
4773 out_err:
4774         return err;
4775 }
4776
4777 static void niu_full_shutdown(struct niu *np, struct net_device *dev)
4778 {
4779         cancel_work_sync(&np->reset_task);
4780
4781         niu_disable_napi(np);
4782         netif_stop_queue(dev);
4783
4784         del_timer_sync(&np->timer);
4785
4786         spin_lock_irq(&np->lock);
4787
4788         niu_stop_hw(np);
4789
4790         spin_unlock_irq(&np->lock);
4791 }
4792
4793 static int niu_close(struct net_device *dev)
4794 {
4795         struct niu *np = netdev_priv(dev);
4796
4797         niu_full_shutdown(np, dev);
4798
4799         niu_free_irq(np);
4800
4801         niu_free_channels(np);
4802
4803         niu_handle_led(np, 0);
4804
4805         return 0;
4806 }
4807
4808 static void niu_sync_xmac_stats(struct niu *np)
4809 {
4810         struct niu_xmac_stats *mp = &np->mac_stats.xmac;
4811
4812         mp->tx_frames += nr64_mac(TXMAC_FRM_CNT);
4813         mp->tx_bytes += nr64_mac(TXMAC_BYTE_CNT);
4814
4815         mp->rx_link_faults += nr64_mac(LINK_FAULT_CNT);
4816         mp->rx_align_errors += nr64_mac(RXMAC_ALIGN_ERR_CNT);
4817         mp->rx_frags += nr64_mac(RXMAC_FRAG_CNT);
4818         mp->rx_mcasts += nr64_mac(RXMAC_MC_FRM_CNT);
4819         mp->rx_bcasts += nr64_mac(RXMAC_BC_FRM_CNT);
4820         mp->rx_hist_cnt1 += nr64_mac(RXMAC_HIST_CNT1);
4821         mp->rx_hist_cnt2 += nr64_mac(RXMAC_HIST_CNT2);
4822         mp->rx_hist_cnt3 += nr64_mac(RXMAC_HIST_CNT3);
4823         mp->rx_hist_cnt4 += nr64_mac(RXMAC_HIST_CNT4);
4824         mp->rx_hist_cnt5 += nr64_mac(RXMAC_HIST_CNT5);
4825         mp->rx_hist_cnt6 += nr64_mac(RXMAC_HIST_CNT6);
4826         mp->rx_hist_cnt7 += nr64_mac(RXMAC_HIST_CNT7);
4827         mp->rx_octets += nr64_mac(RXMAC_BT_CNT);
4828         mp->rx_code_violations += nr64_mac(RXMAC_CD_VIO_CNT);
4829         mp->rx_len_errors += nr64_mac(RXMAC_MPSZER_CNT);
4830         mp->rx_crc_errors += nr64_mac(RXMAC_CRC_ER_CNT);
4831 }
4832
4833 static void niu_sync_bmac_stats(struct niu *np)
4834 {
4835         struct niu_bmac_stats *mp = &np->mac_stats.bmac;
4836
4837         mp->tx_bytes += nr64_mac(BTXMAC_BYTE_CNT);
4838         mp->tx_frames += nr64_mac(BTXMAC_FRM_CNT);
4839
4840         mp->rx_frames += nr64_mac(BRXMAC_FRAME_CNT);
4841         mp->rx_align_errors += nr64_mac(BRXMAC_ALIGN_ERR_CNT);
4842         mp->rx_crc_errors += nr64_mac(BRXMAC_ALIGN_ERR_CNT);
4843         mp->rx_len_errors += nr64_mac(BRXMAC_CODE_VIOL_ERR_CNT);
4844 }
4845
4846 static void niu_sync_mac_stats(struct niu *np)
4847 {
4848         if (np->flags & NIU_FLAGS_XMAC)
4849                 niu_sync_xmac_stats(np);
4850         else
4851                 niu_sync_bmac_stats(np);
4852 }
4853
4854 static void niu_get_rx_stats(struct niu *np)
4855 {
4856         unsigned long pkts, dropped, errors, bytes;
4857         int i;
4858
4859         pkts = dropped = errors = bytes = 0;
4860         for (i = 0; i < np->num_rx_rings; i++) {
4861                 struct rx_ring_info *rp = &np->rx_rings[i];
4862
4863                 pkts += rp->rx_packets;
4864                 bytes += rp->rx_bytes;
4865                 dropped += rp->rx_dropped;
4866                 errors += rp->rx_errors;
4867         }
4868         np->net_stats.rx_packets = pkts;
4869         np->net_stats.rx_bytes = bytes;
4870         np->net_stats.rx_dropped = dropped;
4871         np->net_stats.rx_errors = errors;
4872 }
4873
4874 static void niu_get_tx_stats(struct niu *np)
4875 {
4876         unsigned long pkts, errors, bytes;
4877         int i;
4878
4879         pkts = errors = bytes = 0;
4880         for (i = 0; i < np->num_tx_rings; i++) {
4881                 struct tx_ring_info *rp = &np->tx_rings[i];
4882
4883                 pkts += rp->tx_packets;
4884                 bytes += rp->tx_bytes;
4885                 errors += rp->tx_errors;
4886         }
4887         np->net_stats.tx_packets = pkts;
4888         np->net_stats.tx_bytes = bytes;
4889         np->net_stats.tx_errors = errors;
4890 }
4891
4892 static struct net_device_stats *niu_get_stats(struct net_device *dev)
4893 {
4894         struct niu *np = netdev_priv(dev);
4895
4896         niu_get_rx_stats(np);
4897         niu_get_tx_stats(np);
4898
4899         return &np->net_stats;
4900 }
4901
4902 static void niu_load_hash_xmac(struct niu *np, u16 *hash)
4903 {
4904         int i;
4905
4906         for (i = 0; i < 16; i++)
4907                 nw64_mac(XMAC_HASH_TBL(i), hash[i]);
4908 }
4909
4910 static void niu_load_hash_bmac(struct niu *np, u16 *hash)
4911 {
4912         int i;
4913
4914         for (i = 0; i < 16; i++)
4915                 nw64_mac(BMAC_HASH_TBL(i), hash[i]);
4916 }
4917
4918 static void niu_load_hash(struct niu *np, u16 *hash)
4919 {
4920         if (np->flags & NIU_FLAGS_XMAC)
4921                 niu_load_hash_xmac(np, hash);
4922         else
4923                 niu_load_hash_bmac(np, hash);
4924 }
4925
4926 static void niu_set_rx_mode(struct net_device *dev)
4927 {
4928         struct niu *np = netdev_priv(dev);
4929         int i, alt_cnt, err;
4930         struct dev_addr_list *addr;
4931         unsigned long flags;
4932         u16 hash[16] = { 0, };
4933
4934         spin_lock_irqsave(&np->lock, flags);
4935         niu_enable_rx_mac(np, 0);
4936
4937         np->flags &= ~(NIU_FLAGS_MCAST | NIU_FLAGS_PROMISC);
4938         if (dev->flags & IFF_PROMISC)
4939                 np->flags |= NIU_FLAGS_PROMISC;
4940         if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 0))
4941                 np->flags |= NIU_FLAGS_MCAST;
4942
4943         alt_cnt = dev->uc_count;
4944         if (alt_cnt > niu_num_alt_addr(np)) {
4945                 alt_cnt = 0;
4946                 np->flags |= NIU_FLAGS_PROMISC;
4947         }
4948
4949         if (alt_cnt) {
4950                 int index = 0;
4951
4952                 for (addr = dev->uc_list; addr; addr = addr->next) {
4953                         err = niu_set_alt_mac(np, index,
4954                                               addr->da_addr);
4955                         if (err)
4956                                 printk(KERN_WARNING PFX "%s: Error %d "
4957                                        "adding alt mac %d\n",
4958                                        dev->name, err, index);
4959                         err = niu_enable_alt_mac(np, index, 1);
4960                         if (err)
4961                                 printk(KERN_WARNING PFX "%s: Error %d "
4962                                        "enabling alt mac %d\n",
4963                                        dev->name, err, index);
4964
4965                         index++;
4966                 }
4967         } else {
4968                 for (i = 0; i < niu_num_alt_addr(np); i++) {
4969                         err = niu_enable_alt_mac(np, i, 0);
4970                         if (err)
4971                                 printk(KERN_WARNING PFX "%s: Error %d "
4972                                        "disabling alt mac %d\n",
4973                                        dev->name, err, i);
4974                 }
4975         }
4976         if (dev->flags & IFF_ALLMULTI) {
4977                 for (i = 0; i < 16; i++)
4978                         hash[i] = 0xffff;
4979         } else if (dev->mc_count > 0) {
4980                 for (addr = dev->mc_list; addr; addr = addr->next) {
4981                         u32 crc = ether_crc_le(ETH_ALEN, addr->da_addr);
4982
4983                         crc >>= 24;
4984                         hash[crc >> 4] |= (1 << (15 - (crc & 0xf)));
4985                 }
4986         }
4987
4988         if (np->flags & NIU_FLAGS_MCAST)
4989                 niu_load_hash(np, hash);
4990
4991         niu_enable_rx_mac(np, 1);
4992         spin_unlock_irqrestore(&np->lock, flags);
4993 }
4994
4995 static int niu_set_mac_addr(struct net_device *dev, void *p)
4996 {
4997         struct niu *np = netdev_priv(dev);
4998         struct sockaddr *addr = p;
4999         unsigned long flags;
5000
5001         if (!is_valid_ether_addr(addr->sa_data))
5002                 return -EINVAL;
5003
5004         memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
5005
5006         if (!netif_running(dev))
5007                 return 0;
5008
5009         spin_lock_irqsave(&np->lock, flags);
5010         niu_enable_rx_mac(np, 0);
5011         niu_set_primary_mac(np, dev->dev_addr);
5012         niu_enable_rx_mac(np, 1);
5013         spin_unlock_irqrestore(&np->lock, flags);
5014
5015         return 0;
5016 }
5017
5018 static int niu_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
5019 {
5020         return -EOPNOTSUPP;
5021 }
5022
5023 static void niu_netif_stop(struct niu *np)
5024 {
5025         np->dev->trans_start = jiffies; /* prevent tx timeout */
5026
5027         niu_disable_napi(np);
5028
5029         netif_tx_disable(np->dev);
5030 }
5031
5032 static void niu_netif_start(struct niu *np)
5033 {
5034         /* NOTE: unconditional netif_wake_queue is only appropriate
5035          * so long as all callers are assured to have free tx slots
5036          * (such as after niu_init_hw).
5037          */
5038         netif_wake_queue(np->dev);
5039
5040         niu_enable_napi(np);
5041
5042         niu_enable_interrupts(np, 1);
5043 }
5044
5045 static void niu_reset_task(struct work_struct *work)
5046 {
5047         struct niu *np = container_of(work, struct niu, reset_task);
5048         unsigned long flags;
5049         int err;
5050
5051         spin_lock_irqsave(&np->lock, flags);
5052         if (!netif_running(np->dev)) {
5053                 spin_unlock_irqrestore(&np->lock, flags);
5054                 return;
5055         }
5056
5057         spin_unlock_irqrestore(&np->lock, flags);
5058
5059         del_timer_sync(&np->timer);
5060
5061         niu_netif_stop(np);
5062
5063         spin_lock_irqsave(&np->lock, flags);
5064
5065         niu_stop_hw(np);
5066
5067         err = niu_init_hw(np);
5068         if (!err) {
5069                 np->timer.expires = jiffies + HZ;
5070                 add_timer(&np->timer);
5071                 niu_netif_start(np);
5072         }
5073
5074         spin_unlock_irqrestore(&np->lock, flags);
5075 }
5076
5077 static void niu_tx_timeout(struct net_device *dev)
5078 {
5079         struct niu *np = netdev_priv(dev);
5080
5081         dev_err(np->device, PFX "%s: Transmit timed out, resetting\n",
5082                 dev->name);
5083
5084         schedule_work(&np->reset_task);
5085 }
5086
5087 static void niu_set_txd(struct tx_ring_info *rp, int index,
5088                         u64 mapping, u64 len, u64 mark,
5089                         u64 n_frags)
5090 {
5091         __le64 *desc = &rp->descr[index];
5092
5093         *desc = cpu_to_le64(mark |
5094                             (n_frags << TX_DESC_NUM_PTR_SHIFT) |
5095                             (len << TX_DESC_TR_LEN_SHIFT) |
5096                             (mapping & TX_DESC_SAD));
5097 }
5098
5099 static u64 niu_compute_tx_flags(struct sk_buff *skb, struct ethhdr *ehdr,
5100                                 u64 pad_bytes, u64 len)
5101 {
5102         u16 eth_proto, eth_proto_inner;
5103         u64 csum_bits, l3off, ihl, ret;
5104         u8 ip_proto;
5105         int ipv6;
5106
5107         eth_proto = be16_to_cpu(ehdr->h_proto);
5108         eth_proto_inner = eth_proto;
5109         if (eth_proto == ETH_P_8021Q) {
5110                 struct vlan_ethhdr *vp = (struct vlan_ethhdr *) ehdr;
5111                 __be16 val = vp->h_vlan_encapsulated_proto;
5112
5113                 eth_proto_inner = be16_to_cpu(val);
5114         }
5115
5116         ipv6 = ihl = 0;
5117         switch (skb->protocol) {
5118         case __constant_htons(ETH_P_IP):
5119                 ip_proto = ip_hdr(skb)->protocol;
5120                 ihl = ip_hdr(skb)->ihl;
5121                 break;
5122         case __constant_htons(ETH_P_IPV6):
5123                 ip_proto = ipv6_hdr(skb)->nexthdr;
5124                 ihl = (40 >> 2);
5125                 ipv6 = 1;
5126                 break;
5127         default:
5128                 ip_proto = ihl = 0;
5129                 break;
5130         }
5131
5132         csum_bits = TXHDR_CSUM_NONE;
5133         if (skb->ip_summed == CHECKSUM_PARTIAL) {
5134                 u64 start, stuff;
5135
5136                 csum_bits = (ip_proto == IPPROTO_TCP ?
5137                              TXHDR_CSUM_TCP :
5138                              (ip_proto == IPPROTO_UDP ?
5139                               TXHDR_CSUM_UDP : TXHDR_CSUM_SCTP));
5140
5141                 start = skb_transport_offset(skb) -
5142                         (pad_bytes + sizeof(struct tx_pkt_hdr));
5143                 stuff = start + skb->csum_offset;
5144
5145                 csum_bits |= (start / 2) << TXHDR_L4START_SHIFT;
5146                 csum_bits |= (stuff / 2) << TXHDR_L4STUFF_SHIFT;
5147         }
5148
5149         l3off = skb_network_offset(skb) -
5150                 (pad_bytes + sizeof(struct tx_pkt_hdr));
5151
5152         ret = (((pad_bytes / 2) << TXHDR_PAD_SHIFT) |
5153                (len << TXHDR_LEN_SHIFT) |
5154                ((l3off / 2) << TXHDR_L3START_SHIFT) |
5155                (ihl << TXHDR_IHL_SHIFT) |
5156                ((eth_proto_inner < 1536) ? TXHDR_LLC : 0) |
5157                ((eth_proto == ETH_P_8021Q) ? TXHDR_VLAN : 0) |
5158                (ipv6 ? TXHDR_IP_VER : 0) |
5159                csum_bits);
5160
5161         return ret;
5162 }
5163
5164 static struct tx_ring_info *tx_ring_select(struct niu *np, struct sk_buff *skb)
5165 {
5166         return &np->tx_rings[0];
5167 }
5168
5169 static int niu_start_xmit(struct sk_buff *skb, struct net_device *dev)
5170 {
5171         struct niu *np = netdev_priv(dev);
5172         unsigned long align, headroom;
5173         struct tx_ring_info *rp;
5174         struct tx_pkt_hdr *tp;
5175         unsigned int len, nfg;
5176         struct ethhdr *ehdr;
5177         int prod, i, tlen;
5178         u64 mapping, mrk;
5179
5180         rp = tx_ring_select(np, skb);
5181
5182         if (niu_tx_avail(rp) <= (skb_shinfo(skb)->nr_frags + 1)) {
5183                 netif_stop_queue(dev);
5184                 dev_err(np->device, PFX "%s: BUG! Tx ring full when "
5185                         "queue awake!\n", dev->name);
5186                 rp->tx_errors++;
5187                 return NETDEV_TX_BUSY;
5188         }
5189
5190         if (skb->len < ETH_ZLEN) {
5191                 unsigned int pad_bytes = ETH_ZLEN - skb->len;
5192
5193                 if (skb_pad(skb, pad_bytes))
5194                         goto out;
5195                 skb_put(skb, pad_bytes);
5196         }
5197
5198         len = sizeof(struct tx_pkt_hdr) + 15;
5199         if (skb_headroom(skb) < len) {
5200                 struct sk_buff *skb_new;
5201
5202                 skb_new = skb_realloc_headroom(skb, len);
5203                 if (!skb_new) {
5204                         rp->tx_errors++;
5205                         goto out_drop;
5206                 }
5207                 kfree_skb(skb);
5208                 skb = skb_new;
5209         }
5210
5211         align = ((unsigned long) skb->data & (16 - 1));
5212         headroom = align + sizeof(struct tx_pkt_hdr);
5213
5214         ehdr = (struct ethhdr *) skb->data;
5215         tp = (struct tx_pkt_hdr *) skb_push(skb, headroom);
5216
5217         len = skb->len - sizeof(struct tx_pkt_hdr);
5218         tp->flags = cpu_to_le64(niu_compute_tx_flags(skb, ehdr, align, len));
5219         tp->resv = 0;
5220
5221         len = skb_headlen(skb);
5222         mapping = np->ops->map_single(np->device, skb->data,
5223                                       len, DMA_TO_DEVICE);
5224
5225         prod = rp->prod;
5226
5227         rp->tx_buffs[prod].skb = skb;
5228         rp->tx_buffs[prod].mapping = mapping;
5229
5230         mrk = TX_DESC_SOP;
5231         if (++rp->mark_counter == rp->mark_freq) {
5232                 rp->mark_counter = 0;
5233                 mrk |= TX_DESC_MARK;
5234                 rp->mark_pending++;
5235         }
5236
5237         tlen = len;
5238         nfg = skb_shinfo(skb)->nr_frags;
5239         while (tlen > 0) {
5240                 tlen -= MAX_TX_DESC_LEN;
5241                 nfg++;
5242         }
5243
5244         while (len > 0) {
5245                 unsigned int this_len = len;
5246
5247                 if (this_len > MAX_TX_DESC_LEN)
5248                         this_len = MAX_TX_DESC_LEN;
5249
5250                 niu_set_txd(rp, prod, mapping, this_len, mrk, nfg);
5251                 mrk = nfg = 0;
5252
5253                 prod = NEXT_TX(rp, prod);
5254                 mapping += this_len;
5255                 len -= this_len;
5256         }
5257
5258         for (i = 0; i <  skb_shinfo(skb)->nr_frags; i++) {
5259                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5260
5261                 len = frag->size;
5262                 mapping = np->ops->map_page(np->device, frag->page,
5263                                             frag->page_offset, len,
5264                                             DMA_TO_DEVICE);
5265
5266                 rp->tx_buffs[prod].skb = NULL;
5267                 rp->tx_buffs[prod].mapping = mapping;
5268
5269                 niu_set_txd(rp, prod, mapping, len, 0, 0);
5270
5271                 prod = NEXT_TX(rp, prod);
5272         }
5273
5274         if (prod < rp->prod)
5275                 rp->wrap_bit ^= TX_RING_KICK_WRAP;
5276         rp->prod = prod;
5277
5278         nw64(TX_RING_KICK(rp->tx_channel), rp->wrap_bit | (prod << 3));
5279
5280         if (unlikely(niu_tx_avail(rp) <= (MAX_SKB_FRAGS + 1))) {
5281                 netif_stop_queue(dev);
5282                 if (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp))
5283                         netif_wake_queue(dev);
5284         }
5285
5286         dev->trans_start = jiffies;
5287
5288 out:
5289         return NETDEV_TX_OK;
5290
5291 out_drop:
5292         rp->tx_errors++;
5293         kfree_skb(skb);
5294         goto out;
5295 }
5296
5297 static int niu_change_mtu(struct net_device *dev, int new_mtu)
5298 {
5299         struct niu *np = netdev_priv(dev);
5300         int err, orig_jumbo, new_jumbo;
5301
5302         if (new_mtu < 68 || new_mtu > NIU_MAX_MTU)
5303                 return -EINVAL;
5304
5305         orig_jumbo = (dev->mtu > ETH_DATA_LEN);
5306         new_jumbo = (new_mtu > ETH_DATA_LEN);
5307
5308         dev->mtu = new_mtu;
5309
5310         if (!netif_running(dev) ||
5311             (orig_jumbo == new_jumbo))
5312                 return 0;
5313
5314         niu_full_shutdown(np, dev);
5315
5316         niu_free_channels(np);
5317
5318         niu_enable_napi(np);
5319
5320         err = niu_alloc_channels(np);
5321         if (err)
5322                 return err;
5323
5324         spin_lock_irq(&np->lock);
5325
5326         err = niu_init_hw(np);
5327         if (!err) {
5328                 init_timer(&np->timer);
5329                 np->timer.expires = jiffies + HZ;
5330                 np->timer.data = (unsigned long) np;
5331                 np->timer.function = niu_timer;
5332
5333                 err = niu_enable_interrupts(np, 1);
5334                 if (err)
5335                         niu_stop_hw(np);
5336         }
5337
5338         spin_unlock_irq(&np->lock);
5339
5340         if (!err) {
5341                 netif_start_queue(dev);
5342                 if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
5343                         netif_carrier_on(dev);
5344
5345                 add_timer(&np->timer);
5346         }
5347
5348         return err;
5349 }
5350
5351 static void niu_get_drvinfo(struct net_device *dev,
5352                             struct ethtool_drvinfo *info)
5353 {
5354         struct niu *np = netdev_priv(dev);
5355         struct niu_vpd *vpd = &np->vpd;
5356
5357         strcpy(info->driver, DRV_MODULE_NAME);
5358         strcpy(info->version, DRV_MODULE_VERSION);
5359         sprintf(info->fw_version, "%d.%d",
5360                 vpd->fcode_major, vpd->fcode_minor);
5361         if (np->parent->plat_type != PLAT_TYPE_NIU)
5362                 strcpy(info->bus_info, pci_name(np->pdev));
5363 }
5364
5365 static int niu_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
5366 {
5367         struct niu *np = netdev_priv(dev);
5368         struct niu_link_config *lp;
5369
5370         lp = &np->link_config;
5371
5372         memset(cmd, 0, sizeof(*cmd));
5373         cmd->phy_address = np->phy_addr;
5374         cmd->supported = lp->supported;
5375         cmd->advertising = lp->advertising;
5376         cmd->autoneg = lp->autoneg;
5377         cmd->speed = lp->active_speed;
5378         cmd->duplex = lp->active_duplex;
5379
5380         return 0;
5381 }
5382
5383 static int niu_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
5384 {
5385         return -EINVAL;
5386 }
5387
5388 static u32 niu_get_msglevel(struct net_device *dev)
5389 {
5390         struct niu *np = netdev_priv(dev);
5391         return np->msg_enable;
5392 }
5393
5394 static void niu_set_msglevel(struct net_device *dev, u32 value)
5395 {
5396         struct niu *np = netdev_priv(dev);
5397         np->msg_enable = value;
5398 }
5399
5400 static int niu_get_eeprom_len(struct net_device *dev)
5401 {
5402         struct niu *np = netdev_priv(dev);
5403
5404         return np->eeprom_len;
5405 }
5406
5407 static int niu_get_eeprom(struct net_device *dev,
5408                           struct ethtool_eeprom *eeprom, u8 *data)
5409 {
5410         struct niu *np = netdev_priv(dev);
5411         u32 offset, len, val;
5412
5413         offset = eeprom->offset;
5414         len = eeprom->len;
5415
5416         if (offset + len < offset)
5417                 return -EINVAL;
5418         if (offset >= np->eeprom_len)
5419                 return -EINVAL;
5420         if (offset + len > np->eeprom_len)
5421                 len = eeprom->len = np->eeprom_len - offset;
5422
5423         if (offset & 3) {
5424                 u32 b_offset, b_count;
5425
5426                 b_offset = offset & 3;
5427                 b_count = 4 - b_offset;
5428                 if (b_count > len)
5429                         b_count = len;
5430
5431                 val = nr64(ESPC_NCR((offset - b_offset) / 4));
5432                 memcpy(data, ((char *)&val) + b_offset, b_count);
5433                 data += b_count;
5434                 len -= b_count;
5435                 offset += b_count;
5436         }
5437         while (len >= 4) {
5438                 val = nr64(ESPC_NCR(offset / 4));
5439                 memcpy(data, &val, 4);
5440                 data += 4;
5441                 len -= 4;
5442                 offset += 4;
5443         }
5444         if (len) {
5445                 val = nr64(ESPC_NCR(offset / 4));
5446                 memcpy(data, &val, len);
5447         }
5448         return 0;
5449 }
5450
5451 static const struct {
5452         const char string[ETH_GSTRING_LEN];
5453 } niu_xmac_stat_keys[] = {
5454         { "tx_frames" },
5455         { "tx_bytes" },
5456         { "tx_fifo_errors" },
5457         { "tx_overflow_errors" },
5458         { "tx_max_pkt_size_errors" },
5459         { "tx_underflow_errors" },
5460         { "rx_local_faults" },
5461         { "rx_remote_faults" },
5462         { "rx_link_faults" },
5463         { "rx_align_errors" },
5464         { "rx_frags" },
5465         { "rx_mcasts" },
5466         { "rx_bcasts" },
5467         { "rx_hist_cnt1" },
5468         { "rx_hist_cnt2" },
5469         { "rx_hist_cnt3" },
5470         { "rx_hist_cnt4" },
5471         { "rx_hist_cnt5" },
5472         { "rx_hist_cnt6" },
5473         { "rx_hist_cnt7" },
5474         { "rx_octets" },
5475         { "rx_code_violations" },
5476         { "rx_len_errors" },
5477         { "rx_crc_errors" },
5478         { "rx_underflows" },
5479         { "rx_overflows" },
5480         { "pause_off_state" },
5481         { "pause_on_state" },
5482         { "pause_received" },
5483 };
5484
5485 #define NUM_XMAC_STAT_KEYS      ARRAY_SIZE(niu_xmac_stat_keys)
5486
5487 static const struct {
5488         const char string[ETH_GSTRING_LEN];
5489 } niu_bmac_stat_keys[] = {
5490         { "tx_underflow_errors" },
5491         { "tx_max_pkt_size_errors" },
5492         { "tx_bytes" },
5493         { "tx_frames" },
5494         { "rx_overflows" },
5495         { "rx_frames" },
5496         { "rx_align_errors" },
5497         { "rx_crc_errors" },
5498         { "rx_len_errors" },
5499         { "pause_off_state" },
5500         { "pause_on_state" },
5501         { "pause_received" },
5502 };
5503
5504 #define NUM_BMAC_STAT_KEYS      ARRAY_SIZE(niu_bmac_stat_keys)
5505
5506 static const struct {
5507         const char string[ETH_GSTRING_LEN];
5508 } niu_rxchan_stat_keys[] = {
5509         { "rx_channel" },
5510         { "rx_packets" },
5511         { "rx_bytes" },
5512         { "rx_dropped" },
5513         { "rx_errors" },
5514 };
5515
5516 #define NUM_RXCHAN_STAT_KEYS    ARRAY_SIZE(niu_rxchan_stat_keys)
5517
5518 static const struct {
5519         const char string[ETH_GSTRING_LEN];
5520 } niu_txchan_stat_keys[] = {
5521         { "tx_channel" },
5522         { "tx_packets" },
5523         { "tx_bytes" },
5524         { "tx_errors" },
5525 };
5526
5527 #define NUM_TXCHAN_STAT_KEYS    ARRAY_SIZE(niu_txchan_stat_keys)
5528
5529 static void niu_get_strings(struct net_device *dev, u32 stringset, u8 *data)
5530 {
5531         struct niu *np = netdev_priv(dev);
5532         int i;
5533
5534         if (stringset != ETH_SS_STATS)
5535                 return;
5536
5537         if (np->flags & NIU_FLAGS_XMAC) {
5538                 memcpy(data, niu_xmac_stat_keys,
5539                        sizeof(niu_xmac_stat_keys));
5540                 data += sizeof(niu_xmac_stat_keys);
5541         } else {
5542                 memcpy(data, niu_bmac_stat_keys,
5543                        sizeof(niu_bmac_stat_keys));
5544                 data += sizeof(niu_bmac_stat_keys);
5545         }
5546         for (i = 0; i < np->num_rx_rings; i++) {
5547                 memcpy(data, niu_rxchan_stat_keys,
5548                        sizeof(niu_rxchan_stat_keys));
5549                 data += sizeof(niu_rxchan_stat_keys);
5550         }
5551         for (i = 0; i < np->num_tx_rings; i++) {
5552                 memcpy(data, niu_txchan_stat_keys,
5553                        sizeof(niu_txchan_stat_keys));
5554                 data += sizeof(niu_txchan_stat_keys);
5555         }
5556 }
5557
5558 static int niu_get_stats_count(struct net_device *dev)
5559 {
5560         struct niu *np = netdev_priv(dev);
5561
5562         return ((np->flags & NIU_FLAGS_XMAC ?
5563                  NUM_XMAC_STAT_KEYS :
5564                  NUM_BMAC_STAT_KEYS) +
5565                 (np->num_rx_rings * NUM_RXCHAN_STAT_KEYS) +
5566                 (np->num_tx_rings * NUM_TXCHAN_STAT_KEYS));
5567 }
5568
5569 static void niu_get_ethtool_stats(struct net_device *dev,
5570                                   struct ethtool_stats *stats, u64 *data)
5571 {
5572         struct niu *np = netdev_priv(dev);
5573         int i;
5574
5575         niu_sync_mac_stats(np);
5576         if (np->flags & NIU_FLAGS_XMAC) {
5577                 memcpy(data, &np->mac_stats.xmac,
5578                        sizeof(struct niu_xmac_stats));
5579                 data += (sizeof(struct niu_xmac_stats) / sizeof(u64));
5580         } else {
5581                 memcpy(data, &np->mac_stats.bmac,
5582                        sizeof(struct niu_bmac_stats));
5583                 data += (sizeof(struct niu_bmac_stats) / sizeof(u64));
5584         }
5585         for (i = 0; i < np->num_rx_rings; i++) {
5586                 struct rx_ring_info *rp = &np->rx_rings[i];
5587
5588                 data[0] = rp->rx_channel;
5589                 data[1] = rp->rx_packets;
5590                 data[2] = rp->rx_bytes;
5591                 data[3] = rp->rx_dropped;
5592                 data[4] = rp->rx_errors;
5593                 data += 5;
5594         }
5595         for (i = 0; i < np->num_tx_rings; i++) {
5596                 struct tx_ring_info *rp = &np->tx_rings[i];
5597
5598                 data[0] = rp->tx_channel;
5599                 data[1] = rp->tx_packets;
5600                 data[2] = rp->tx_bytes;
5601                 data[3] = rp->tx_errors;
5602                 data += 4;
5603         }
5604 }
5605
5606 static u64 niu_led_state_save(struct niu *np)
5607 {
5608         if (np->flags & NIU_FLAGS_XMAC)
5609                 return nr64_mac(XMAC_CONFIG);
5610         else
5611                 return nr64_mac(BMAC_XIF_CONFIG);
5612 }
5613
5614 static void niu_led_state_restore(struct niu *np, u64 val)
5615 {
5616         if (np->flags & NIU_FLAGS_XMAC)
5617                 nw64_mac(XMAC_CONFIG, val);
5618         else
5619                 nw64_mac(BMAC_XIF_CONFIG, val);
5620 }
5621
5622 static void niu_force_led(struct niu *np, int on)
5623 {
5624         u64 val, reg, bit;
5625
5626         if (np->flags & NIU_FLAGS_XMAC) {
5627                 reg = XMAC_CONFIG;
5628                 bit = XMAC_CONFIG_FORCE_LED_ON;
5629         } else {
5630                 reg = BMAC_XIF_CONFIG;
5631                 bit = BMAC_XIF_CONFIG_LINK_LED;
5632         }
5633
5634         val = nr64_mac(reg);
5635         if (on)
5636                 val |= bit;
5637         else
5638                 val &= ~bit;
5639         nw64_mac(reg, val);
5640 }
5641
5642 static int niu_phys_id(struct net_device *dev, u32 data)
5643 {
5644         struct niu *np = netdev_priv(dev);
5645         u64 orig_led_state;
5646         int i;
5647
5648         if (!netif_running(dev))
5649                 return -EAGAIN;
5650
5651         if (data == 0)
5652                 data = 2;
5653
5654         orig_led_state = niu_led_state_save(np);
5655         for (i = 0; i < (data * 2); i++) {
5656                 int on = ((i % 2) == 0);
5657
5658                 niu_force_led(np, on);
5659
5660                 if (msleep_interruptible(500))
5661                         break;
5662         }
5663         niu_led_state_restore(np, orig_led_state);
5664
5665         return 0;
5666 }
5667
5668 static const struct ethtool_ops niu_ethtool_ops = {
5669         .get_drvinfo            = niu_get_drvinfo,
5670         .get_link               = ethtool_op_get_link,
5671         .get_msglevel           = niu_get_msglevel,
5672         .set_msglevel           = niu_set_msglevel,
5673         .get_eeprom_len         = niu_get_eeprom_len,
5674         .get_eeprom             = niu_get_eeprom,
5675         .get_settings           = niu_get_settings,
5676         .set_settings           = niu_set_settings,
5677         .get_strings            = niu_get_strings,
5678         .get_stats_count        = niu_get_stats_count,
5679         .get_ethtool_stats      = niu_get_ethtool_stats,
5680         .phys_id                = niu_phys_id,
5681 };
5682
5683 static int niu_ldg_assign_ldn(struct niu *np, struct niu_parent *parent,
5684                               int ldg, int ldn)
5685 {
5686         if (ldg < NIU_LDG_MIN || ldg > NIU_LDG_MAX)
5687                 return -EINVAL;
5688         if (ldn < 0 || ldn > LDN_MAX)
5689                 return -EINVAL;
5690
5691         parent->ldg_map[ldn] = ldg;
5692
5693         if (np->parent->plat_type == PLAT_TYPE_NIU) {
5694                 /* On N2 NIU, the ldn-->ldg assignments are setup and fixed by
5695                  * the firmware, and we're not supposed to change them.
5696                  * Validate the mapping, because if it's wrong we probably
5697                  * won't get any interrupts and that's painful to debug.
5698                  */
5699                 if (nr64(LDG_NUM(ldn)) != ldg) {
5700                         dev_err(np->device, PFX "Port %u, mis-matched "
5701                                 "LDG assignment "
5702                                 "for ldn %d, should be %d is %llu\n",
5703                                 np->port, ldn, ldg,
5704                                 (unsigned long long) nr64(LDG_NUM(ldn)));
5705                         return -EINVAL;
5706                 }
5707         } else
5708                 nw64(LDG_NUM(ldn), ldg);
5709
5710         return 0;
5711 }
5712
5713 static int niu_set_ldg_timer_res(struct niu *np, int res)
5714 {
5715         if (res < 0 || res > LDG_TIMER_RES_VAL)
5716                 return -EINVAL;
5717
5718
5719         nw64(LDG_TIMER_RES, res);
5720
5721         return 0;
5722 }
5723
5724 static int niu_set_ldg_sid(struct niu *np, int ldg, int func, int vector)
5725 {
5726         if ((ldg < NIU_LDG_MIN || ldg > NIU_LDG_MAX) ||
5727             (func < 0 || func > 3) ||
5728             (vector < 0 || vector > 0x1f))
5729                 return -EINVAL;
5730
5731         nw64(SID(ldg), (func << SID_FUNC_SHIFT) | vector);
5732
5733         return 0;
5734 }
5735
5736 static int __devinit niu_pci_eeprom_read(struct niu *np, u32 addr)
5737 {
5738         u64 frame, frame_base = (ESPC_PIO_STAT_READ_START |
5739                                  (addr << ESPC_PIO_STAT_ADDR_SHIFT));
5740         int limit;
5741
5742         if (addr > (ESPC_PIO_STAT_ADDR >> ESPC_PIO_STAT_ADDR_SHIFT))
5743                 return -EINVAL;
5744
5745         frame = frame_base;
5746         nw64(ESPC_PIO_STAT, frame);
5747         limit = 64;
5748         do {
5749                 udelay(5);
5750                 frame = nr64(ESPC_PIO_STAT);
5751                 if (frame & ESPC_PIO_STAT_READ_END)
5752                         break;
5753         } while (limit--);
5754         if (!(frame & ESPC_PIO_STAT_READ_END)) {
5755                 dev_err(np->device, PFX "EEPROM read timeout frame[%llx]\n",
5756                         (unsigned long long) frame);
5757                 return -ENODEV;
5758         }
5759
5760         frame = frame_base;
5761         nw64(ESPC_PIO_STAT, frame);
5762         limit = 64;
5763         do {
5764                 udelay(5);
5765                 frame = nr64(ESPC_PIO_STAT);
5766                 if (frame & ESPC_PIO_STAT_READ_END)
5767                         break;
5768         } while (limit--);
5769         if (!(frame & ESPC_PIO_STAT_READ_END)) {
5770                 dev_err(np->device, PFX "EEPROM read timeout frame[%llx]\n",
5771                         (unsigned long long) frame);
5772                 return -ENODEV;
5773         }
5774
5775         frame = nr64(ESPC_PIO_STAT);
5776         return (frame & ESPC_PIO_STAT_DATA) >> ESPC_PIO_STAT_DATA_SHIFT;
5777 }
5778
5779 static int __devinit niu_pci_eeprom_read16(struct niu *np, u32 off)
5780 {
5781         int err = niu_pci_eeprom_read(np, off);
5782         u16 val;
5783
5784         if (err < 0)
5785                 return err;
5786         val = (err << 8);
5787         err = niu_pci_eeprom_read(np, off + 1);
5788         if (err < 0)
5789                 return err;
5790         val |= (err & 0xff);
5791
5792         return val;
5793 }
5794
5795 static int __devinit niu_pci_eeprom_read16_swp(struct niu *np, u32 off)
5796 {
5797         int err = niu_pci_eeprom_read(np, off);
5798         u16 val;
5799
5800         if (err < 0)
5801                 return err;
5802
5803         val = (err & 0xff);
5804         err = niu_pci_eeprom_read(np, off + 1);
5805         if (err < 0)
5806                 return err;
5807
5808         val |= (err & 0xff) << 8;
5809
5810         return val;
5811 }
5812
5813 static int __devinit niu_pci_vpd_get_propname(struct niu *np,
5814                                               u32 off,
5815                                               char *namebuf,
5816                                               int namebuf_len)
5817 {
5818         int i;
5819
5820         for (i = 0; i < namebuf_len; i++) {
5821                 int err = niu_pci_eeprom_read(np, off + i);
5822                 if (err < 0)
5823                         return err;
5824                 *namebuf++ = err;
5825                 if (!err)
5826                         break;
5827         }
5828         if (i >= namebuf_len)
5829                 return -EINVAL;
5830
5831         return i + 1;
5832 }
5833
5834 static void __devinit niu_vpd_parse_version(struct niu *np)
5835 {
5836         struct niu_vpd *vpd = &np->vpd;
5837         int len = strlen(vpd->version) + 1;
5838         const char *s = vpd->version;
5839         int i;
5840
5841         for (i = 0; i < len - 5; i++) {
5842                 if (!strncmp(s + i, "FCode ", 5))
5843                         break;
5844         }
5845         if (i >= len - 5)
5846                 return;
5847
5848         s += i + 5;
5849         sscanf(s, "%d.%d", &vpd->fcode_major, &vpd->fcode_minor);
5850
5851         niudbg(PROBE, "VPD_SCAN: FCODE major(%d) minor(%d)\n",
5852                vpd->fcode_major, vpd->fcode_minor);
5853         if (vpd->fcode_major > NIU_VPD_MIN_MAJOR ||
5854             (vpd->fcode_major == NIU_VPD_MIN_MAJOR &&
5855              vpd->fcode_minor >= NIU_VPD_MIN_MINOR))
5856                 np->flags |= NIU_FLAGS_VPD_VALID;
5857 }
5858
5859 /* ESPC_PIO_EN_ENABLE must be set */
5860 static int __devinit niu_pci_vpd_scan_props(struct niu *np,
5861                                             u32 start, u32 end)
5862 {
5863         unsigned int found_mask = 0;
5864 #define FOUND_MASK_MODEL        0x00000001
5865 #define FOUND_MASK_BMODEL       0x00000002
5866 #define FOUND_MASK_VERS         0x00000004
5867 #define FOUND_MASK_MAC          0x00000008
5868 #define FOUND_MASK_NMAC         0x00000010
5869 #define FOUND_MASK_PHY          0x00000020
5870 #define FOUND_MASK_ALL          0x0000003f
5871
5872         niudbg(PROBE, "VPD_SCAN: start[%x] end[%x]\n",
5873                start, end);
5874         while (start < end) {
5875                 int len, err, instance, type, prop_len;
5876                 char namebuf[64];
5877                 u8 *prop_buf;
5878                 int max_len;
5879
5880                 if (found_mask == FOUND_MASK_ALL) {
5881                         niu_vpd_parse_version(np);
5882                         return 1;
5883                 }
5884
5885                 err = niu_pci_eeprom_read(np, start + 2);
5886                 if (err < 0)
5887                         return err;
5888                 len = err;
5889                 start += 3;
5890
5891                 instance = niu_pci_eeprom_read(np, start);
5892                 type = niu_pci_eeprom_read(np, start + 3);
5893                 prop_len = niu_pci_eeprom_read(np, start + 4);
5894                 err = niu_pci_vpd_get_propname(np, start + 5, namebuf, 64);
5895                 if (err < 0)
5896                         return err;
5897
5898                 prop_buf = NULL;
5899                 max_len = 0;
5900                 if (!strcmp(namebuf, "model")) {
5901                         prop_buf = np->vpd.model;
5902                         max_len = NIU_VPD_MODEL_MAX;
5903                         found_mask |= FOUND_MASK_MODEL;
5904                 } else if (!strcmp(namebuf, "board-model")) {
5905                         prop_buf = np->vpd.board_model;
5906                         max_len = NIU_VPD_BD_MODEL_MAX;
5907                         found_mask |= FOUND_MASK_BMODEL;
5908                 } else if (!strcmp(namebuf, "version")) {
5909                         prop_buf = np->vpd.version;
5910                         max_len = NIU_VPD_VERSION_MAX;
5911                         found_mask |= FOUND_MASK_VERS;
5912                 } else if (!strcmp(namebuf, "local-mac-address")) {
5913                         prop_buf = np->vpd.local_mac;
5914                         max_len = ETH_ALEN;
5915                         found_mask |= FOUND_MASK_MAC;
5916                 } else if (!strcmp(namebuf, "num-mac-addresses")) {
5917                         prop_buf = &np->vpd.mac_num;
5918                         max_len = 1;
5919                         found_mask |= FOUND_MASK_NMAC;
5920                 } else if (!strcmp(namebuf, "phy-type")) {
5921                         prop_buf = np->vpd.phy_type;
5922                         max_len = NIU_VPD_PHY_TYPE_MAX;
5923                         found_mask |= FOUND_MASK_PHY;
5924                 }
5925
5926                 if (max_len && prop_len > max_len) {
5927                         dev_err(np->device, PFX "Property '%s' length (%d) is "
5928                                 "too long.\n", namebuf, prop_len);
5929                         return -EINVAL;
5930                 }
5931
5932                 if (prop_buf) {
5933                         u32 off = start + 5 + err;
5934                         int i;
5935
5936                         niudbg(PROBE, "VPD_SCAN: Reading in property [%s] "
5937                                "len[%d]\n", namebuf, prop_len);
5938                         for (i = 0; i < prop_len; i++)
5939                                 *prop_buf++ = niu_pci_eeprom_read(np, off + i);
5940                 }
5941
5942                 start += len;
5943         }
5944
5945         return 0;
5946 }
5947
5948 /* ESPC_PIO_EN_ENABLE must be set */
5949 static void __devinit niu_pci_vpd_fetch(struct niu *np, u32 start)
5950 {
5951         u32 offset;
5952         int err;
5953
5954         err = niu_pci_eeprom_read16_swp(np, start + 1);
5955         if (err < 0)
5956                 return;
5957
5958         offset = err + 3;
5959
5960         while (start + offset < ESPC_EEPROM_SIZE) {
5961                 u32 here = start + offset;
5962                 u32 end;
5963
5964                 err = niu_pci_eeprom_read(np, here);
5965                 if (err != 0x90)
5966                         return;
5967
5968                 err = niu_pci_eeprom_read16_swp(np, here + 1);
5969                 if (err < 0)
5970                         return;
5971
5972                 here = start + offset + 3;
5973                 end = start + offset + err;
5974
5975                 offset += err;
5976
5977                 err = niu_pci_vpd_scan_props(np, here, end);
5978                 if (err < 0 || err == 1)
5979                         return;
5980         }
5981 }
5982
5983 /* ESPC_PIO_EN_ENABLE must be set */
5984 static u32 __devinit niu_pci_vpd_offset(struct niu *np)
5985 {
5986         u32 start = 0, end = ESPC_EEPROM_SIZE, ret;
5987         int err;
5988
5989         while (start < end) {
5990                 ret = start;
5991
5992                 /* ROM header signature?  */
5993                 err = niu_pci_eeprom_read16(np, start +  0);
5994                 if (err != 0x55aa)
5995                         return 0;
5996
5997                 /* Apply offset to PCI data structure.  */
5998                 err = niu_pci_eeprom_read16(np, start + 23);
5999                 if (err < 0)
6000                         return 0;
6001                 start += err;
6002
6003                 /* Check for "PCIR" signature.  */
6004                 err = niu_pci_eeprom_read16(np, start +  0);
6005                 if (err != 0x5043)
6006                         return 0;
6007                 err = niu_pci_eeprom_read16(np, start +  2);
6008                 if (err != 0x4952)
6009                         return 0;
6010
6011                 /* Check for OBP image type.  */
6012                 err = niu_pci_eeprom_read(np, start + 20);
6013                 if (err < 0)
6014                         return 0;
6015                 if (err != 0x01) {
6016                         err = niu_pci_eeprom_read(np, ret + 2);
6017                         if (err < 0)
6018                                 return 0;
6019
6020                         start = ret + (err * 512);
6021                         continue;
6022                 }
6023
6024                 err = niu_pci_eeprom_read16_swp(np, start + 8);
6025                 if (err < 0)
6026                         return err;
6027                 ret += err;
6028
6029                 err = niu_pci_eeprom_read(np, ret + 0);
6030                 if (err != 0x82)
6031                         return 0;
6032
6033                 return ret;
6034         }
6035
6036         return 0;
6037 }
6038
6039 static int __devinit niu_phy_type_prop_decode(struct niu *np,
6040                                               const char *phy_prop)
6041 {
6042         if (!strcmp(phy_prop, "mif")) {
6043                 /* 1G copper, MII */
6044                 np->flags &= ~(NIU_FLAGS_FIBER |
6045                                NIU_FLAGS_10G);
6046                 np->mac_xcvr = MAC_XCVR_MII;
6047         } else if (!strcmp(phy_prop, "xgf")) {
6048                 /* 10G fiber, XPCS */
6049                 np->flags |= (NIU_FLAGS_10G |
6050                               NIU_FLAGS_FIBER);
6051                 np->mac_xcvr = MAC_XCVR_XPCS;
6052         } else if (!strcmp(phy_prop, "pcs")) {
6053                 /* 1G fiber, PCS */
6054                 np->flags &= ~NIU_FLAGS_10G;
6055                 np->flags |= NIU_FLAGS_FIBER;
6056                 np->mac_xcvr = MAC_XCVR_PCS;
6057         } else if (!strcmp(phy_prop, "xgc")) {
6058                 /* 10G copper, XPCS */
6059                 np->flags |= NIU_FLAGS_10G;
6060                 np->flags &= ~NIU_FLAGS_FIBER;
6061                 np->mac_xcvr = MAC_XCVR_XPCS;
6062         } else {
6063                 return -EINVAL;
6064         }
6065         return 0;
6066 }
6067
6068 static void __devinit niu_pci_vpd_validate(struct niu *np)
6069 {
6070         struct net_device *dev = np->dev;
6071         struct niu_vpd *vpd = &np->vpd;
6072         u8 val8;
6073
6074         if (!is_valid_ether_addr(&vpd->local_mac[0])) {
6075                 dev_err(np->device, PFX "VPD MAC invalid, "
6076                         "falling back to SPROM.\n");
6077
6078                 np->flags &= ~NIU_FLAGS_VPD_VALID;
6079                 return;
6080         }
6081
6082         if (niu_phy_type_prop_decode(np, np->vpd.phy_type)) {
6083                 dev_err(np->device, PFX "Illegal phy string [%s].\n",
6084                         np->vpd.phy_type);
6085                 dev_err(np->device, PFX "Falling back to SPROM.\n");
6086                 np->flags &= ~NIU_FLAGS_VPD_VALID;
6087                 return;
6088         }
6089
6090         memcpy(dev->perm_addr, vpd->local_mac, ETH_ALEN);
6091
6092         val8 = dev->perm_addr[5];
6093         dev->perm_addr[5] += np->port;
6094         if (dev->perm_addr[5] < val8)
6095                 dev->perm_addr[4]++;
6096
6097         memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len);
6098 }
6099
6100 static int __devinit niu_pci_probe_sprom(struct niu *np)
6101 {
6102         struct net_device *dev = np->dev;
6103         int len, i;
6104         u64 val, sum;
6105         u8 val8;
6106
6107         val = (nr64(ESPC_VER_IMGSZ) & ESPC_VER_IMGSZ_IMGSZ);
6108         val >>= ESPC_VER_IMGSZ_IMGSZ_SHIFT;
6109         len = val / 4;
6110
6111         np->eeprom_len = len;
6112
6113         niudbg(PROBE, "SPROM: Image size %llu\n", (unsigned long long) val);
6114
6115         sum = 0;
6116         for (i = 0; i < len; i++) {
6117                 val = nr64(ESPC_NCR(i));
6118                 sum += (val >>  0) & 0xff;
6119                 sum += (val >>  8) & 0xff;
6120                 sum += (val >> 16) & 0xff;
6121                 sum += (val >> 24) & 0xff;
6122         }
6123         niudbg(PROBE, "SPROM: Checksum %x\n", (int)(sum & 0xff));
6124         if ((sum & 0xff) != 0xab) {
6125                 dev_err(np->device, PFX "Bad SPROM checksum "
6126                         "(%x, should be 0xab)\n", (int) (sum & 0xff));
6127                 return -EINVAL;
6128         }
6129
6130         val = nr64(ESPC_PHY_TYPE);
6131         switch (np->port) {
6132         case 0:
6133                 val8 = (val & ESPC_PHY_TYPE_PORT0) >>
6134                         ESPC_PHY_TYPE_PORT0_SHIFT;
6135                 break;
6136         case 1:
6137                 val8 = (val & ESPC_PHY_TYPE_PORT1) >>
6138                         ESPC_PHY_TYPE_PORT1_SHIFT;
6139                 break;
6140         case 2:
6141                 val8 = (val & ESPC_PHY_TYPE_PORT2) >>
6142                         ESPC_PHY_TYPE_PORT2_SHIFT;
6143                 break;
6144         case 3:
6145                 val8 = (val & ESPC_PHY_TYPE_PORT3) >>
6146                         ESPC_PHY_TYPE_PORT3_SHIFT;
6147                 break;
6148         default:
6149                 dev_err(np->device, PFX "Bogus port number %u\n",
6150                         np->port);
6151                 return -EINVAL;
6152         }
6153         niudbg(PROBE, "SPROM: PHY type %x\n", val8);
6154
6155         switch (val8) {
6156         case ESPC_PHY_TYPE_1G_COPPER:
6157                 /* 1G copper, MII */
6158                 np->flags &= ~(NIU_FLAGS_FIBER |
6159                                NIU_FLAGS_10G);
6160                 np->mac_xcvr = MAC_XCVR_MII;
6161                 break;
6162
6163         case ESPC_PHY_TYPE_1G_FIBER:
6164                 /* 1G fiber, PCS */
6165                 np->flags &= ~NIU_FLAGS_10G;
6166                 np->flags |= NIU_FLAGS_FIBER;
6167                 np->mac_xcvr = MAC_XCVR_PCS;
6168                 break;
6169
6170         case ESPC_PHY_TYPE_10G_COPPER:
6171                 /* 10G copper, XPCS */
6172                 np->flags |= NIU_FLAGS_10G;
6173                 np->flags &= ~NIU_FLAGS_FIBER;
6174                 np->mac_xcvr = MAC_XCVR_XPCS;
6175                 break;
6176
6177         case ESPC_PHY_TYPE_10G_FIBER:
6178                 /* 10G fiber, XPCS */
6179                 np->flags |= (NIU_FLAGS_10G |
6180                               NIU_FLAGS_FIBER);
6181                 np->mac_xcvr = MAC_XCVR_XPCS;
6182                 break;
6183
6184         default:
6185                 dev_err(np->device, PFX "Bogus SPROM phy type %u\n", val8);
6186                 return -EINVAL;
6187         }
6188
6189         val = nr64(ESPC_MAC_ADDR0);
6190         niudbg(PROBE, "SPROM: MAC_ADDR0[%08llx]\n",
6191                (unsigned long long) val);
6192         dev->perm_addr[0] = (val >>  0) & 0xff;
6193         dev->perm_addr[1] = (val >>  8) & 0xff;
6194         dev->perm_addr[2] = (val >> 16) & 0xff;
6195         dev->perm_addr[3] = (val >> 24) & 0xff;
6196
6197         val = nr64(ESPC_MAC_ADDR1);
6198         niudbg(PROBE, "SPROM: MAC_ADDR1[%08llx]\n",
6199                (unsigned long long) val);
6200         dev->perm_addr[4] = (val >>  0) & 0xff;
6201         dev->perm_addr[5] = (val >>  8) & 0xff;
6202
6203         if (!is_valid_ether_addr(&dev->perm_addr[0])) {
6204                 dev_err(np->device, PFX "SPROM MAC address invalid\n");
6205                 dev_err(np->device, PFX "[ \n");
6206                 for (i = 0; i < 6; i++)
6207                         printk("%02x ", dev->perm_addr[i]);
6208                 printk("]\n");
6209                 return -EINVAL;
6210         }
6211
6212         val8 = dev->perm_addr[5];
6213         dev->perm_addr[5] += np->port;
6214         if (dev->perm_addr[5] < val8)
6215                 dev->perm_addr[4]++;
6216
6217         memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len);
6218
6219         val = nr64(ESPC_MOD_STR_LEN);
6220         niudbg(PROBE, "SPROM: MOD_STR_LEN[%llu]\n",
6221                (unsigned long long) val);
6222         if (val >= 8 * 4)
6223                 return -EINVAL;
6224
6225         for (i = 0; i < val; i += 4) {
6226                 u64 tmp = nr64(ESPC_NCR(5 + (i / 4)));
6227
6228                 np->vpd.model[i + 3] = (tmp >>  0) & 0xff;
6229                 np->vpd.model[i + 2] = (tmp >>  8) & 0xff;
6230                 np->vpd.model[i + 1] = (tmp >> 16) & 0xff;
6231                 np->vpd.model[i + 0] = (tmp >> 24) & 0xff;
6232         }
6233         np->vpd.model[val] = '\0';
6234
6235         val = nr64(ESPC_BD_MOD_STR_LEN);
6236         niudbg(PROBE, "SPROM: BD_MOD_STR_LEN[%llu]\n",
6237                (unsigned long long) val);
6238         if (val >= 4 * 4)
6239                 return -EINVAL;
6240
6241         for (i = 0; i < val; i += 4) {
6242                 u64 tmp = nr64(ESPC_NCR(14 + (i / 4)));
6243
6244                 np->vpd.board_model[i + 3] = (tmp >>  0) & 0xff;
6245                 np->vpd.board_model[i + 2] = (tmp >>  8) & 0xff;
6246                 np->vpd.board_model[i + 1] = (tmp >> 16) & 0xff;
6247                 np->vpd.board_model[i + 0] = (tmp >> 24) & 0xff;
6248         }
6249         np->vpd.board_model[val] = '\0';
6250
6251         np->vpd.mac_num =
6252                 nr64(ESPC_NUM_PORTS_MACS) & ESPC_NUM_PORTS_MACS_VAL;
6253         niudbg(PROBE, "SPROM: NUM_PORTS_MACS[%d]\n",
6254                np->vpd.mac_num);
6255
6256         return 0;
6257 }
6258
6259 static int __devinit niu_get_and_validate_port(struct niu *np)
6260 {
6261         struct niu_parent *parent = np->parent;
6262
6263         if (np->port <= 1)
6264                 np->flags |= NIU_FLAGS_XMAC;
6265
6266         if (!parent->num_ports) {
6267                 if (parent->plat_type == PLAT_TYPE_NIU) {
6268                         parent->num_ports = 2;
6269                 } else {
6270                         parent->num_ports = nr64(ESPC_NUM_PORTS_MACS) &
6271                                 ESPC_NUM_PORTS_MACS_VAL;
6272
6273                         if (!parent->num_ports)
6274                                 parent->num_ports = 4;
6275                 }
6276         }
6277
6278         niudbg(PROBE, "niu_get_and_validate_port: port[%d] num_ports[%d]\n",
6279                np->port, parent->num_ports);
6280         if (np->port >= parent->num_ports)
6281                 return -ENODEV;
6282
6283         return 0;
6284 }
6285
6286 static int __devinit phy_record(struct niu_parent *parent,
6287                                 struct phy_probe_info *p,
6288                                 int dev_id_1, int dev_id_2, u8 phy_port,
6289                                 int type)
6290 {
6291         u32 id = (dev_id_1 << 16) | dev_id_2;
6292         u8 idx;
6293
6294         if (dev_id_1 < 0 || dev_id_2 < 0)
6295                 return 0;
6296         if (type == PHY_TYPE_PMA_PMD || type == PHY_TYPE_PCS) {
6297                 if ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM8704)
6298                         return 0;
6299         } else {
6300                 if ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM5464R)
6301                         return 0;
6302         }
6303
6304         pr_info("niu%d: Found PHY %08x type %s at phy_port %u\n",
6305                 parent->index, id,
6306                 (type == PHY_TYPE_PMA_PMD ?
6307                  "PMA/PMD" :
6308                  (type == PHY_TYPE_PCS ?
6309                   "PCS" : "MII")),
6310                 phy_port);
6311
6312         if (p->cur[type] >= NIU_MAX_PORTS) {
6313                 printk(KERN_ERR PFX "Too many PHY ports.\n");
6314                 return -EINVAL;
6315         }
6316         idx = p->cur[type];
6317         p->phy_id[type][idx] = id;
6318         p->phy_port[type][idx] = phy_port;
6319         p->cur[type] = idx + 1;
6320         return 0;
6321 }
6322
6323 static int __devinit port_has_10g(struct phy_probe_info *p, int port)
6324 {
6325         int i;
6326
6327         for (i = 0; i < p->cur[PHY_TYPE_PMA_PMD]; i++) {
6328                 if (p->phy_port[PHY_TYPE_PMA_PMD][i] == port)
6329                         return 1;
6330         }
6331         for (i = 0; i < p->cur[PHY_TYPE_PCS]; i++) {
6332                 if (p->phy_port[PHY_TYPE_PCS][i] == port)
6333                         return 1;
6334         }
6335
6336         return 0;
6337 }
6338
6339 static int __devinit count_10g_ports(struct phy_probe_info *p, int *lowest)
6340 {
6341         int port, cnt;
6342
6343         cnt = 0;
6344         *lowest = 32;
6345         for (port = 8; port < 32; port++) {
6346                 if (port_has_10g(p, port)) {
6347                         if (!cnt)
6348                                 *lowest = port;
6349                         cnt++;
6350                 }
6351         }
6352
6353         return cnt;
6354 }
6355
6356 static int __devinit count_1g_ports(struct phy_probe_info *p, int *lowest)
6357 {
6358         *lowest = 32;
6359         if (p->cur[PHY_TYPE_MII])
6360                 *lowest = p->phy_port[PHY_TYPE_MII][0];
6361
6362         return p->cur[PHY_TYPE_MII];
6363 }
6364
6365 static void __devinit niu_n2_divide_channels(struct niu_parent *parent)
6366 {
6367         int num_ports = parent->num_ports;
6368         int i;
6369
6370         for (i = 0; i < num_ports; i++) {
6371                 parent->rxchan_per_port[i] = (16 / num_ports);
6372                 parent->txchan_per_port[i] = (16 / num_ports);
6373
6374                 pr_info(PFX "niu%d: Port %u [%u RX chans] "
6375                         "[%u TX chans]\n",
6376                         parent->index, i,
6377                         parent->rxchan_per_port[i],
6378                         parent->txchan_per_port[i]);
6379         }
6380 }
6381
6382 static void __devinit niu_divide_channels(struct niu_parent *parent,
6383                                           int num_10g, int num_1g)
6384 {
6385         int num_ports = parent->num_ports;
6386         int rx_chans_per_10g, rx_chans_per_1g;
6387         int tx_chans_per_10g, tx_chans_per_1g;
6388         int i, tot_rx, tot_tx;
6389
6390         if (!num_10g || !num_1g) {
6391                 rx_chans_per_10g = rx_chans_per_1g =
6392                         (NIU_NUM_RXCHAN / num_ports);
6393                 tx_chans_per_10g = tx_chans_per_1g =
6394                         (NIU_NUM_TXCHAN / num_ports);
6395         } else {
6396                 rx_chans_per_1g = NIU_NUM_RXCHAN / 8;
6397                 rx_chans_per_10g = (NIU_NUM_RXCHAN -
6398                                     (rx_chans_per_1g * num_1g)) /
6399                         num_10g;
6400
6401                 tx_chans_per_1g = NIU_NUM_TXCHAN / 6;
6402                 tx_chans_per_10g = (NIU_NUM_TXCHAN -
6403                                     (tx_chans_per_1g * num_1g)) /
6404                         num_10g;
6405         }
6406
6407         tot_rx = tot_tx = 0;
6408         for (i = 0; i < num_ports; i++) {
6409                 int type = phy_decode(parent->port_phy, i);
6410
6411                 if (type == PORT_TYPE_10G) {
6412                         parent->rxchan_per_port[i] = rx_chans_per_10g;
6413                         parent->txchan_per_port[i] = tx_chans_per_10g;
6414                 } else {
6415                         parent->rxchan_per_port[i] = rx_chans_per_1g;
6416                         parent->txchan_per_port[i] = tx_chans_per_1g;
6417                 }
6418                 pr_info(PFX "niu%d: Port %u [%u RX chans] "
6419                         "[%u TX chans]\n",
6420                         parent->index, i,
6421                         parent->rxchan_per_port[i],
6422                         parent->txchan_per_port[i]);
6423                 tot_rx += parent->rxchan_per_port[i];
6424                 tot_tx += parent->txchan_per_port[i];
6425         }
6426
6427         if (tot_rx > NIU_NUM_RXCHAN) {
6428                 printk(KERN_ERR PFX "niu%d: Too many RX channels (%d), "
6429                        "resetting to one per port.\n",
6430                        parent->index, tot_rx);
6431                 for (i = 0; i < num_ports; i++)
6432                         parent->rxchan_per_port[i] = 1;
6433         }
6434         if (tot_tx > NIU_NUM_TXCHAN) {
6435                 printk(KERN_ERR PFX "niu%d: Too many TX channels (%d), "
6436                        "resetting to one per port.\n",
6437                        parent->index, tot_tx);
6438                 for (i = 0; i < num_ports; i++)
6439                         parent->txchan_per_port[i] = 1;
6440         }
6441         if (tot_rx < NIU_NUM_RXCHAN || tot_tx < NIU_NUM_TXCHAN) {
6442                 printk(KERN_WARNING PFX "niu%d: Driver bug, wasted channels, "
6443                        "RX[%d] TX[%d]\n",
6444                        parent->index, tot_rx, tot_tx);
6445         }
6446 }
6447
6448 static void __devinit niu_divide_rdc_groups(struct niu_parent *parent,
6449                                             int num_10g, int num_1g)
6450 {
6451         int i, num_ports = parent->num_ports;
6452         int rdc_group, rdc_groups_per_port;
6453         int rdc_channel_base;
6454
6455         rdc_group = 0;
6456         rdc_groups_per_port = NIU_NUM_RDC_TABLES / num_ports;
6457
6458         rdc_channel_base = 0;
6459
6460         for (i = 0; i < num_ports; i++) {
6461                 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[i];
6462                 int grp, num_channels = parent->rxchan_per_port[i];
6463                 int this_channel_offset;
6464
6465                 tp->first_table_num = rdc_group;
6466                 tp->num_tables = rdc_groups_per_port;
6467                 this_channel_offset = 0;
6468                 for (grp = 0; grp < tp->num_tables; grp++) {
6469                         struct rdc_table *rt = &tp->tables[grp];
6470                         int slot;
6471
6472                         pr_info(PFX "niu%d: Port %d RDC tbl(%d) [ ",
6473                                 parent->index, i, tp->first_table_num + grp);
6474                         for (slot = 0; slot < NIU_RDC_TABLE_SLOTS; slot++) {
6475                                 rt->rxdma_channel[slot] =
6476                                         rdc_channel_base + this_channel_offset;
6477
6478                                 printk("%d ", rt->rxdma_channel[slot]);
6479
6480                                 if (++this_channel_offset == num_channels)
6481                                         this_channel_offset = 0;
6482                         }
6483                         printk("]\n");
6484                 }
6485
6486                 parent->rdc_default[i] = rdc_channel_base;
6487
6488                 rdc_channel_base += num_channels;
6489                 rdc_group += rdc_groups_per_port;
6490         }
6491 }
6492
6493 static int __devinit fill_phy_probe_info(struct niu *np,
6494                                          struct niu_parent *parent,
6495                                          struct phy_probe_info *info)
6496 {
6497         unsigned long flags;
6498         int port, err;
6499
6500         memset(info, 0, sizeof(*info));
6501
6502         /* Port 0 to 7 are reserved for onboard Serdes, probe the rest.  */
6503         niu_lock_parent(np, flags);
6504         err = 0;
6505         for (port = 8; port < 32; port++) {
6506                 int dev_id_1, dev_id_2;
6507
6508                 dev_id_1 = mdio_read(np, port,
6509                                      NIU_PMA_PMD_DEV_ADDR, MII_PHYSID1);
6510                 dev_id_2 = mdio_read(np, port,
6511                                      NIU_PMA_PMD_DEV_ADDR, MII_PHYSID2);
6512                 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
6513                                  PHY_TYPE_PMA_PMD);
6514                 if (err)
6515                         break;
6516                 dev_id_1 = mdio_read(np, port,
6517                                      NIU_PCS_DEV_ADDR, MII_PHYSID1);
6518                 dev_id_2 = mdio_read(np, port,
6519                                      NIU_PCS_DEV_ADDR, MII_PHYSID2);
6520                 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
6521                                  PHY_TYPE_PCS);
6522                 if (err)
6523                         break;
6524                 dev_id_1 = mii_read(np, port, MII_PHYSID1);
6525                 dev_id_2 = mii_read(np, port, MII_PHYSID2);
6526                 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
6527                                  PHY_TYPE_MII);
6528                 if (err)
6529                         break;
6530         }
6531         niu_unlock_parent(np, flags);
6532
6533         return err;
6534 }
6535
6536 static int __devinit walk_phys(struct niu *np, struct niu_parent *parent)
6537 {
6538         struct phy_probe_info *info = &parent->phy_probe_info;
6539         int lowest_10g, lowest_1g;
6540         int num_10g, num_1g;
6541         u32 val;
6542         int err;
6543
6544         err = fill_phy_probe_info(np, parent, info);
6545         if (err)
6546                 return err;
6547
6548         num_10g = count_10g_ports(info, &lowest_10g);
6549         num_1g = count_1g_ports(info, &lowest_1g);
6550
6551         switch ((num_10g << 4) | num_1g) {
6552         case 0x24:
6553                 if (lowest_1g == 10)
6554                         parent->plat_type = PLAT_TYPE_VF_P0;
6555                 else if (lowest_1g == 26)
6556                         parent->plat_type = PLAT_TYPE_VF_P1;
6557                 else
6558                         goto unknown_vg_1g_port;
6559
6560                 /* fallthru */
6561         case 0x22:
6562                 val = (phy_encode(PORT_TYPE_10G, 0) |
6563                        phy_encode(PORT_TYPE_10G, 1) |
6564                        phy_encode(PORT_TYPE_1G, 2) |
6565                        phy_encode(PORT_TYPE_1G, 3));
6566                 break;
6567
6568         case 0x20:
6569                 val = (phy_encode(PORT_TYPE_10G, 0) |
6570                        phy_encode(PORT_TYPE_10G, 1));
6571                 break;
6572
6573         case 0x10:
6574                 val = phy_encode(PORT_TYPE_10G, np->port);
6575                 break;
6576
6577         case 0x14:
6578                 if (lowest_1g == 10)
6579                         parent->plat_type = PLAT_TYPE_VF_P0;
6580                 else if (lowest_1g == 26)
6581                         parent->plat_type = PLAT_TYPE_VF_P1;
6582                 else
6583                         goto unknown_vg_1g_port;
6584
6585                 /* fallthru */
6586         case 0x13:
6587                 if ((lowest_10g & 0x7) == 0)
6588                         val = (phy_encode(PORT_TYPE_10G, 0) |
6589                                phy_encode(PORT_TYPE_1G, 1) |
6590                                phy_encode(PORT_TYPE_1G, 2) |
6591                                phy_encode(PORT_TYPE_1G, 3));
6592                 else
6593                         val = (phy_encode(PORT_TYPE_1G, 0) |
6594                                phy_encode(PORT_TYPE_10G, 1) |
6595                                phy_encode(PORT_TYPE_1G, 2) |
6596                                phy_encode(PORT_TYPE_1G, 3));
6597                 break;
6598
6599         case 0x04:
6600                 if (lowest_1g == 10)
6601                         parent->plat_type = PLAT_TYPE_VF_P0;
6602                 else if (lowest_1g == 26)
6603                         parent->plat_type = PLAT_TYPE_VF_P1;
6604                 else
6605                         goto unknown_vg_1g_port;
6606
6607                 val = (phy_encode(PORT_TYPE_1G, 0) |
6608                        phy_encode(PORT_TYPE_1G, 1) |
6609                        phy_encode(PORT_TYPE_1G, 2) |
6610                        phy_encode(PORT_TYPE_1G, 3));
6611                 break;
6612
6613         default:
6614                 printk(KERN_ERR PFX "Unsupported port config "
6615                        "10G[%d] 1G[%d]\n",
6616                        num_10g, num_1g);
6617                 return -EINVAL;
6618         }
6619
6620         parent->port_phy = val;
6621
6622         if (parent->plat_type == PLAT_TYPE_NIU)
6623                 niu_n2_divide_channels(parent);
6624         else
6625                 niu_divide_channels(parent, num_10g, num_1g);
6626
6627         niu_divide_rdc_groups(parent, num_10g, num_1g);
6628
6629         return 0;
6630
6631 unknown_vg_1g_port:
6632         printk(KERN_ERR PFX "Cannot identify platform type, 1gport=%d\n",
6633                lowest_1g);
6634         return -EINVAL;
6635 }
6636
6637 static int __devinit niu_probe_ports(struct niu *np)
6638 {
6639         struct niu_parent *parent = np->parent;
6640         int err, i;
6641
6642         niudbg(PROBE, "niu_probe_ports(): port_phy[%08x]\n",
6643                parent->port_phy);
6644
6645         if (parent->port_phy == PORT_PHY_UNKNOWN) {
6646                 err = walk_phys(np, parent);
6647                 if (err)
6648                         return err;
6649
6650                 niu_set_ldg_timer_res(np, 2);
6651                 for (i = 0; i <= LDN_MAX; i++)
6652                         niu_ldn_irq_enable(np, i, 0);
6653         }
6654
6655         if (parent->port_phy == PORT_PHY_INVALID)
6656                 return -EINVAL;
6657
6658         return 0;
6659 }
6660
6661 static int __devinit niu_classifier_swstate_init(struct niu *np)
6662 {
6663         struct niu_classifier *cp = &np->clas;
6664
6665         niudbg(PROBE, "niu_classifier_swstate_init: num_tcam(%d)\n",
6666                np->parent->tcam_num_entries);
6667
6668         cp->tcam_index = (u16) np->port;
6669         cp->h1_init = 0xffffffff;
6670         cp->h2_init = 0xffff;
6671
6672         return fflp_early_init(np);
6673 }
6674
6675 static void __devinit niu_link_config_init(struct niu *np)
6676 {
6677         struct niu_link_config *lp = &np->link_config;
6678
6679         lp->advertising = (ADVERTISED_10baseT_Half |
6680                            ADVERTISED_10baseT_Full |
6681                            ADVERTISED_100baseT_Half |
6682                            ADVERTISED_100baseT_Full |
6683                            ADVERTISED_1000baseT_Half |
6684                            ADVERTISED_1000baseT_Full |
6685                            ADVERTISED_10000baseT_Full |
6686                            ADVERTISED_Autoneg);
6687         lp->speed = lp->active_speed = SPEED_INVALID;
6688         lp->duplex = lp->active_duplex = DUPLEX_INVALID;
6689 #if 0
6690         lp->loopback_mode = LOOPBACK_MAC;
6691         lp->active_speed = SPEED_10000;
6692         lp->active_duplex = DUPLEX_FULL;
6693 #else
6694         lp->loopback_mode = LOOPBACK_DISABLED;
6695 #endif
6696 }
6697
6698 static int __devinit niu_init_mac_ipp_pcs_base(struct niu *np)
6699 {
6700         switch (np->port) {
6701         case 0:
6702                 np->mac_regs = np->regs + XMAC_PORT0_OFF;
6703                 np->ipp_off  = 0x00000;
6704                 np->pcs_off  = 0x04000;
6705                 np->xpcs_off = 0x02000;
6706                 break;
6707
6708         case 1:
6709                 np->mac_regs = np->regs + XMAC_PORT1_OFF;
6710                 np->ipp_off  = 0x08000;
6711                 np->pcs_off  = 0x0a000;
6712                 np->xpcs_off = 0x08000;
6713                 break;
6714
6715         case 2:
6716                 np->mac_regs = np->regs + BMAC_PORT2_OFF;
6717                 np->ipp_off  = 0x04000;
6718                 np->pcs_off  = 0x0e000;
6719                 np->xpcs_off = ~0UL;
6720                 break;
6721
6722         case 3:
6723                 np->mac_regs = np->regs + BMAC_PORT3_OFF;
6724                 np->ipp_off  = 0x0c000;
6725                 np->pcs_off  = 0x12000;
6726                 np->xpcs_off = ~0UL;
6727                 break;
6728
6729         default:
6730                 dev_err(np->device, PFX "Port %u is invalid, cannot "
6731                         "compute MAC block offset.\n", np->port);
6732                 return -EINVAL;
6733         }
6734
6735         return 0;
6736 }
6737
6738 static void __devinit niu_try_msix(struct niu *np, u8 *ldg_num_map)
6739 {
6740         struct msix_entry msi_vec[NIU_NUM_LDG];
6741         struct niu_parent *parent = np->parent;
6742         struct pci_dev *pdev = np->pdev;
6743         int i, num_irqs, err;
6744         u8 first_ldg;
6745
6746         first_ldg = (NIU_NUM_LDG / parent->num_ports) * np->port;
6747         for (i = 0; i < (NIU_NUM_LDG / parent->num_ports); i++)
6748                 ldg_num_map[i] = first_ldg + i;
6749
6750         num_irqs = (parent->rxchan_per_port[np->port] +
6751                     parent->txchan_per_port[np->port] +
6752                     (np->port == 0 ? 3 : 1));
6753         BUG_ON(num_irqs > (NIU_NUM_LDG / parent->num_ports));
6754
6755 retry:
6756         for (i = 0; i < num_irqs; i++) {
6757                 msi_vec[i].vector = 0;
6758                 msi_vec[i].entry = i;
6759         }
6760
6761         err = pci_enable_msix(pdev, msi_vec, num_irqs);
6762         if (err < 0) {
6763                 np->flags &= ~NIU_FLAGS_MSIX;
6764                 return;
6765         }
6766         if (err > 0) {
6767                 num_irqs = err;
6768                 goto retry;
6769         }
6770
6771         np->flags |= NIU_FLAGS_MSIX;
6772         for (i = 0; i < num_irqs; i++)
6773                 np->ldg[i].irq = msi_vec[i].vector;
6774         np->num_ldg = num_irqs;
6775 }
6776
6777 static int __devinit niu_n2_irq_init(struct niu *np, u8 *ldg_num_map)
6778 {
6779 #ifdef CONFIG_SPARC64
6780         struct of_device *op = np->op;
6781         const u32 *int_prop;
6782         int i;
6783
6784         int_prop = of_get_property(op->node, "interrupts", NULL);
6785         if (!int_prop)
6786                 return -ENODEV;
6787
6788         for (i = 0; i < op->num_irqs; i++) {
6789                 ldg_num_map[i] = int_prop[i];
6790                 np->ldg[i].irq = op->irqs[i];
6791         }
6792
6793         np->num_ldg = op->num_irqs;
6794
6795         return 0;
6796 #else
6797         return -EINVAL;
6798 #endif
6799 }
6800
6801 static int __devinit niu_ldg_init(struct niu *np)
6802 {
6803         struct niu_parent *parent = np->parent;
6804         u8 ldg_num_map[NIU_NUM_LDG];
6805         int first_chan, num_chan;
6806         int i, err, ldg_rotor;
6807         u8 port;
6808
6809         np->num_ldg = 1;
6810         np->ldg[0].irq = np->dev->irq;
6811         if (parent->plat_type == PLAT_TYPE_NIU) {
6812                 err = niu_n2_irq_init(np, ldg_num_map);
6813                 if (err)
6814                         return err;
6815         } else
6816                 niu_try_msix(np, ldg_num_map);
6817
6818         port = np->port;
6819         for (i = 0; i < np->num_ldg; i++) {
6820                 struct niu_ldg *lp = &np->ldg[i];
6821
6822                 netif_napi_add(np->dev, &lp->napi, niu_poll, 64);
6823
6824                 lp->np = np;
6825                 lp->ldg_num = ldg_num_map[i];
6826                 lp->timer = 2; /* XXX */
6827
6828                 /* On N2 NIU the firmware has setup the SID mappings so they go
6829                  * to the correct values that will route the LDG to the proper
6830                  * interrupt in the NCU interrupt table.
6831                  */
6832                 if (np->parent->plat_type != PLAT_TYPE_NIU) {
6833                         err = niu_set_ldg_sid(np, lp->ldg_num, port, i);
6834                         if (err)
6835                                 return err;
6836                 }
6837         }
6838
6839         /* We adopt the LDG assignment ordering used by the N2 NIU
6840          * 'interrupt' properties because that simplifies a lot of
6841          * things.  This ordering is:
6842          *
6843          *      MAC
6844          *      MIF     (if port zero)
6845          *      SYSERR  (if port zero)
6846          *      RX channels
6847          *      TX channels
6848          */
6849
6850         ldg_rotor = 0;
6851
6852         err = niu_ldg_assign_ldn(np, parent, ldg_num_map[ldg_rotor],
6853                                   LDN_MAC(port));
6854         if (err)
6855                 return err;
6856
6857         ldg_rotor++;
6858         if (ldg_rotor == np->num_ldg)
6859                 ldg_rotor = 0;
6860
6861         if (port == 0) {
6862                 err = niu_ldg_assign_ldn(np, parent,
6863                                          ldg_num_map[ldg_rotor],
6864                                          LDN_MIF);
6865                 if (err)
6866                         return err;
6867
6868                 ldg_rotor++;
6869                 if (ldg_rotor == np->num_ldg)
6870                         ldg_rotor = 0;
6871
6872                 err = niu_ldg_assign_ldn(np, parent,
6873                                          ldg_num_map[ldg_rotor],
6874                                          LDN_DEVICE_ERROR);
6875                 if (err)
6876                         return err;
6877
6878                 ldg_rotor++;
6879                 if (ldg_rotor == np->num_ldg)
6880                         ldg_rotor = 0;
6881
6882         }
6883
6884         first_chan = 0;
6885         for (i = 0; i < port; i++)
6886                 first_chan += parent->rxchan_per_port[port];
6887         num_chan = parent->rxchan_per_port[port];
6888
6889         for (i = first_chan; i < (first_chan + num_chan); i++) {
6890                 err = niu_ldg_assign_ldn(np, parent,
6891                                          ldg_num_map[ldg_rotor],
6892                                          LDN_RXDMA(i));
6893                 if (err)
6894                         return err;
6895                 ldg_rotor++;
6896                 if (ldg_rotor == np->num_ldg)
6897                         ldg_rotor = 0;
6898         }
6899
6900         first_chan = 0;
6901         for (i = 0; i < port; i++)
6902                 first_chan += parent->txchan_per_port[port];
6903         num_chan = parent->txchan_per_port[port];
6904         for (i = first_chan; i < (first_chan + num_chan); i++) {
6905                 err = niu_ldg_assign_ldn(np, parent,
6906                                          ldg_num_map[ldg_rotor],
6907                                          LDN_TXDMA(i));
6908                 if (err)
6909                         return err;
6910                 ldg_rotor++;
6911                 if (ldg_rotor == np->num_ldg)
6912                         ldg_rotor = 0;
6913         }
6914
6915         return 0;
6916 }
6917
6918 static void __devexit niu_ldg_free(struct niu *np)
6919 {
6920         if (np->flags & NIU_FLAGS_MSIX)
6921                 pci_disable_msix(np->pdev);
6922 }
6923
6924 static int __devinit niu_get_of_props(struct niu *np)
6925 {
6926 #ifdef CONFIG_SPARC64
6927         struct net_device *dev = np->dev;
6928         struct device_node *dp;
6929         const char *phy_type;
6930         const u8 *mac_addr;
6931         int prop_len;
6932
6933         if (np->parent->plat_type == PLAT_TYPE_NIU)
6934                 dp = np->op->node;
6935         else
6936                 dp = pci_device_to_OF_node(np->pdev);
6937
6938         phy_type = of_get_property(dp, "phy-type", &prop_len);
6939         if (!phy_type) {
6940                 dev_err(np->device, PFX "%s: OF node lacks "
6941                         "phy-type property\n",
6942                         dp->full_name);
6943                 return -EINVAL;
6944         }
6945
6946         if (!strcmp(phy_type, "none"))
6947                 return -ENODEV;
6948
6949         strcpy(np->vpd.phy_type, phy_type);
6950
6951         if (niu_phy_type_prop_decode(np, np->vpd.phy_type)) {
6952                 dev_err(np->device, PFX "%s: Illegal phy string [%s].\n",
6953                         dp->full_name, np->vpd.phy_type);
6954                 return -EINVAL;
6955         }
6956
6957         mac_addr = of_get_property(dp, "local-mac-address", &prop_len);
6958         if (!mac_addr) {
6959                 dev_err(np->device, PFX "%s: OF node lacks "
6960                         "local-mac-address property\n",
6961                         dp->full_name);
6962                 return -EINVAL;
6963         }
6964         if (prop_len != dev->addr_len) {
6965                 dev_err(np->device, PFX "%s: OF MAC address prop len (%d) "
6966                         "is wrong.\n",
6967                         dp->full_name, prop_len);
6968         }
6969         memcpy(dev->perm_addr, mac_addr, dev->addr_len);
6970         if (!is_valid_ether_addr(&dev->perm_addr[0])) {
6971                 int i;
6972
6973                 dev_err(np->device, PFX "%s: OF MAC address is invalid\n",
6974                         dp->full_name);
6975                 dev_err(np->device, PFX "%s: [ \n",
6976                         dp->full_name);
6977                 for (i = 0; i < 6; i++)
6978                         printk("%02x ", dev->perm_addr[i]);
6979                 printk("]\n");
6980                 return -EINVAL;
6981         }
6982
6983         memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len);
6984
6985         return 0;
6986 #else
6987         return -EINVAL;
6988 #endif
6989 }
6990
6991 static int __devinit niu_get_invariants(struct niu *np)
6992 {
6993         int err, have_props;
6994         u32 offset;
6995
6996         err = niu_get_of_props(np);
6997         if (err == -ENODEV)
6998                 return err;
6999
7000         have_props = !err;
7001
7002         err = niu_get_and_validate_port(np);
7003         if (err)
7004                 return err;
7005
7006         err = niu_init_mac_ipp_pcs_base(np);
7007         if (err)
7008                 return err;
7009
7010         if (!have_props) {
7011                 if (np->parent->plat_type == PLAT_TYPE_NIU)
7012                         return -EINVAL;
7013
7014                 nw64(ESPC_PIO_EN, ESPC_PIO_EN_ENABLE);
7015                 offset = niu_pci_vpd_offset(np);
7016                 niudbg(PROBE, "niu_get_invariants: VPD offset [%08x]\n",
7017                        offset);
7018                 if (offset)
7019                         niu_pci_vpd_fetch(np, offset);
7020                 nw64(ESPC_PIO_EN, 0);
7021
7022                 if (np->flags & NIU_FLAGS_VPD_VALID)
7023                         niu_pci_vpd_validate(np);
7024
7025                 if (!(np->flags & NIU_FLAGS_VPD_VALID)) {
7026                         err = niu_pci_probe_sprom(np);
7027                         if (err)
7028                                 return err;
7029                 }
7030         }
7031
7032         err = niu_probe_ports(np);
7033         if (err)
7034                 return err;
7035
7036         niu_ldg_init(np);
7037
7038         niu_classifier_swstate_init(np);
7039         niu_link_config_init(np);
7040
7041         err = niu_determine_phy_disposition(np);
7042         if (!err)
7043                 err = niu_init_link(np);
7044
7045         return err;
7046 }
7047
7048 static LIST_HEAD(niu_parent_list);
7049 static DEFINE_MUTEX(niu_parent_lock);
7050 static int niu_parent_index;
7051
7052 static ssize_t show_port_phy(struct device *dev,
7053                              struct device_attribute *attr, char *buf)
7054 {
7055         struct platform_device *plat_dev = to_platform_device(dev);
7056         struct niu_parent *p = plat_dev->dev.platform_data;
7057         u32 port_phy = p->port_phy;
7058         char *orig_buf = buf;
7059         int i;
7060
7061         if (port_phy == PORT_PHY_UNKNOWN ||
7062             port_phy == PORT_PHY_INVALID)
7063                 return 0;
7064
7065         for (i = 0; i < p->num_ports; i++) {
7066                 const char *type_str;
7067                 int type;
7068
7069                 type = phy_decode(port_phy, i);
7070                 if (type == PORT_TYPE_10G)
7071                         type_str = "10G";
7072                 else
7073                         type_str = "1G";
7074                 buf += sprintf(buf,
7075                                (i == 0) ? "%s" : " %s",
7076                                type_str);
7077         }
7078         buf += sprintf(buf, "\n");
7079         return buf - orig_buf;
7080 }
7081
7082 static ssize_t show_plat_type(struct device *dev,
7083                               struct device_attribute *attr, char *buf)
7084 {
7085         struct platform_device *plat_dev = to_platform_device(dev);
7086         struct niu_parent *p = plat_dev->dev.platform_data;
7087         const char *type_str;
7088
7089         switch (p->plat_type) {
7090         case PLAT_TYPE_ATLAS:
7091                 type_str = "atlas";
7092                 break;
7093         case PLAT_TYPE_NIU:
7094                 type_str = "niu";
7095                 break;
7096         case PLAT_TYPE_VF_P0:
7097                 type_str = "vf_p0";
7098                 break;
7099         case PLAT_TYPE_VF_P1:
7100                 type_str = "vf_p1";
7101                 break;
7102         default:
7103                 type_str = "unknown";
7104                 break;
7105         }
7106
7107         return sprintf(buf, "%s\n", type_str);
7108 }
7109
7110 static ssize_t __show_chan_per_port(struct device *dev,
7111                                     struct device_attribute *attr, char *buf,
7112                                     int rx)
7113 {
7114         struct platform_device *plat_dev = to_platform_device(dev);
7115         struct niu_parent *p = plat_dev->dev.platform_data;
7116         char *orig_buf = buf;
7117         u8 *arr;
7118         int i;
7119
7120         arr = (rx ? p->rxchan_per_port : p->txchan_per_port);
7121
7122         for (i = 0; i < p->num_ports; i++) {
7123                 buf += sprintf(buf,
7124                                (i == 0) ? "%d" : " %d",
7125                                arr[i]);
7126         }
7127         buf += sprintf(buf, "\n");
7128
7129         return buf - orig_buf;
7130 }
7131
7132 static ssize_t show_rxchan_per_port(struct device *dev,
7133                                     struct device_attribute *attr, char *buf)
7134 {
7135         return __show_chan_per_port(dev, attr, buf, 1);
7136 }
7137
7138 static ssize_t show_txchan_per_port(struct device *dev,
7139                                     struct device_attribute *attr, char *buf)
7140 {
7141         return __show_chan_per_port(dev, attr, buf, 1);
7142 }
7143
7144 static ssize_t show_num_ports(struct device *dev,
7145                               struct device_attribute *attr, char *buf)
7146 {
7147         struct platform_device *plat_dev = to_platform_device(dev);
7148         struct niu_parent *p = plat_dev->dev.platform_data;
7149
7150         return sprintf(buf, "%d\n", p->num_ports);
7151 }
7152
7153 static struct device_attribute niu_parent_attributes[] = {
7154         __ATTR(port_phy, S_IRUGO, show_port_phy, NULL),
7155         __ATTR(plat_type, S_IRUGO, show_plat_type, NULL),
7156         __ATTR(rxchan_per_port, S_IRUGO, show_rxchan_per_port, NULL),
7157         __ATTR(txchan_per_port, S_IRUGO, show_txchan_per_port, NULL),
7158         __ATTR(num_ports, S_IRUGO, show_num_ports, NULL),
7159         {}
7160 };
7161
7162 static struct niu_parent * __devinit niu_new_parent(struct niu *np,
7163                                                     union niu_parent_id *id,
7164                                                     u8 ptype)
7165 {
7166         struct platform_device *plat_dev;
7167         struct niu_parent *p;
7168         int i;
7169
7170         niudbg(PROBE, "niu_new_parent: Creating new parent.\n");
7171
7172         plat_dev = platform_device_register_simple("niu", niu_parent_index,
7173                                                    NULL, 0);
7174         if (!plat_dev)
7175                 return NULL;
7176
7177         for (i = 0; attr_name(niu_parent_attributes[i]); i++) {
7178                 int err = device_create_file(&plat_dev->dev,
7179                                              &niu_parent_attributes[i]);
7180                 if (err)
7181                         goto fail_unregister;
7182         }
7183
7184         p = kzalloc(sizeof(*p), GFP_KERNEL);
7185         if (!p)
7186                 goto fail_unregister;
7187
7188         p->index = niu_parent_index++;
7189
7190         plat_dev->dev.platform_data = p;
7191         p->plat_dev = plat_dev;
7192
7193         memcpy(&p->id, id, sizeof(*id));
7194         p->plat_type = ptype;
7195         INIT_LIST_HEAD(&p->list);
7196         atomic_set(&p->refcnt, 0);
7197         list_add(&p->list, &niu_parent_list);
7198         spin_lock_init(&p->lock);
7199
7200         p->rxdma_clock_divider = 7500;
7201
7202         p->tcam_num_entries = NIU_PCI_TCAM_ENTRIES;
7203         if (p->plat_type == PLAT_TYPE_NIU)
7204                 p->tcam_num_entries = NIU_NONPCI_TCAM_ENTRIES;
7205
7206         for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_SCTP_IPV6; i++) {
7207                 int index = i - CLASS_CODE_USER_PROG1;
7208
7209                 p->tcam_key[index] = TCAM_KEY_TSEL;
7210                 p->flow_key[index] = (FLOW_KEY_IPSA |
7211                                       FLOW_KEY_IPDA |
7212                                       FLOW_KEY_PROTO |
7213                                       (FLOW_KEY_L4_BYTE12 <<
7214                                        FLOW_KEY_L4_0_SHIFT) |
7215                                       (FLOW_KEY_L4_BYTE12 <<
7216                                        FLOW_KEY_L4_1_SHIFT));
7217         }
7218
7219         for (i = 0; i < LDN_MAX + 1; i++)
7220                 p->ldg_map[i] = LDG_INVALID;
7221
7222         return p;
7223
7224 fail_unregister:
7225         platform_device_unregister(plat_dev);
7226         return NULL;
7227 }
7228
7229 static struct niu_parent * __devinit niu_get_parent(struct niu *np,
7230                                                     union niu_parent_id *id,
7231                                                     u8 ptype)
7232 {
7233         struct niu_parent *p, *tmp;
7234         int port = np->port;
7235
7236         niudbg(PROBE, "niu_get_parent: platform_type[%u] port[%u]\n",
7237                ptype, port);
7238
7239         mutex_lock(&niu_parent_lock);
7240         p = NULL;
7241         list_for_each_entry(tmp, &niu_parent_list, list) {
7242                 if (!memcmp(id, &tmp->id, sizeof(*id))) {
7243                         p = tmp;
7244                         break;
7245                 }
7246         }
7247         if (!p)
7248                 p = niu_new_parent(np, id, ptype);
7249
7250         if (p) {
7251                 char port_name[6];
7252                 int err;
7253
7254                 sprintf(port_name, "port%d", port);
7255                 err = sysfs_create_link(&p->plat_dev->dev.kobj,
7256                                         &np->device->kobj,
7257                                         port_name);
7258                 if (!err) {
7259                         p->ports[port] = np;
7260                         atomic_inc(&p->refcnt);
7261                 }
7262         }
7263         mutex_unlock(&niu_parent_lock);
7264
7265         return p;
7266 }
7267
7268 static void niu_put_parent(struct niu *np)
7269 {
7270         struct niu_parent *p = np->parent;
7271         u8 port = np->port;
7272         char port_name[6];
7273
7274         BUG_ON(!p || p->ports[port] != np);
7275
7276         niudbg(PROBE, "niu_put_parent: port[%u]\n", port);
7277
7278         sprintf(port_name, "port%d", port);
7279
7280         mutex_lock(&niu_parent_lock);
7281
7282         sysfs_remove_link(&p->plat_dev->dev.kobj, port_name);
7283
7284         p->ports[port] = NULL;
7285         np->parent = NULL;
7286
7287         if (atomic_dec_and_test(&p->refcnt)) {
7288                 list_del(&p->list);
7289                 platform_device_unregister(p->plat_dev);
7290         }
7291
7292         mutex_unlock(&niu_parent_lock);
7293 }
7294
7295 static void *niu_pci_alloc_coherent(struct device *dev, size_t size,
7296                                     u64 *handle, gfp_t flag)
7297 {
7298         dma_addr_t dh;
7299         void *ret;
7300
7301         ret = dma_alloc_coherent(dev, size, &dh, flag);
7302         if (ret)
7303                 *handle = dh;
7304         return ret;
7305 }
7306
7307 static void niu_pci_free_coherent(struct device *dev, size_t size,
7308                                   void *cpu_addr, u64 handle)
7309 {
7310         dma_free_coherent(dev, size, cpu_addr, handle);
7311 }
7312
7313 static u64 niu_pci_map_page(struct device *dev, struct page *page,
7314                             unsigned long offset, size_t size,
7315                             enum dma_data_direction direction)
7316 {
7317         return dma_map_page(dev, page, offset, size, direction);
7318 }
7319
7320 static void niu_pci_unmap_page(struct device *dev, u64 dma_address,
7321                                size_t size, enum dma_data_direction direction)
7322 {
7323         return dma_unmap_page(dev, dma_address, size, direction);
7324 }
7325
7326 static u64 niu_pci_map_single(struct device *dev, void *cpu_addr,
7327                               size_t size,
7328                               enum dma_data_direction direction)
7329 {
7330         return dma_map_single(dev, cpu_addr, size, direction);
7331 }
7332
7333 static void niu_pci_unmap_single(struct device *dev, u64 dma_address,
7334                                  size_t size,
7335                                  enum dma_data_direction direction)
7336 {
7337         dma_unmap_single(dev, dma_address, size, direction);
7338 }
7339
7340 static const struct niu_ops niu_pci_ops = {
7341         .alloc_coherent = niu_pci_alloc_coherent,
7342         .free_coherent  = niu_pci_free_coherent,
7343         .map_page       = niu_pci_map_page,
7344         .unmap_page     = niu_pci_unmap_page,
7345         .map_single     = niu_pci_map_single,
7346         .unmap_single   = niu_pci_unmap_single,
7347 };
7348
7349 static void __devinit niu_driver_version(void)
7350 {
7351         static int niu_version_printed;
7352
7353         if (niu_version_printed++ == 0)
7354                 pr_info("%s", version);
7355 }
7356
7357 static struct net_device * __devinit niu_alloc_and_init(
7358         struct device *gen_dev, struct pci_dev *pdev,
7359         struct of_device *op, const struct niu_ops *ops,
7360         u8 port)
7361 {
7362         struct net_device *dev = alloc_etherdev(sizeof(struct niu));
7363         struct niu *np;
7364
7365         if (!dev) {
7366                 dev_err(gen_dev, PFX "Etherdev alloc failed, aborting.\n");
7367                 return NULL;
7368         }
7369
7370         SET_NETDEV_DEV(dev, gen_dev);
7371
7372         np = netdev_priv(dev);
7373         np->dev = dev;
7374         np->pdev = pdev;
7375         np->op = op;
7376         np->device = gen_dev;
7377         np->ops = ops;
7378
7379         np->msg_enable = niu_debug;
7380
7381         spin_lock_init(&np->lock);
7382         INIT_WORK(&np->reset_task, niu_reset_task);
7383
7384         np->port = port;
7385
7386         return dev;
7387 }
7388
7389 static void __devinit niu_assign_netdev_ops(struct net_device *dev)
7390 {
7391         dev->open = niu_open;
7392         dev->stop = niu_close;
7393         dev->get_stats = niu_get_stats;
7394         dev->set_multicast_list = niu_set_rx_mode;
7395         dev->set_mac_address = niu_set_mac_addr;
7396         dev->do_ioctl = niu_ioctl;
7397         dev->tx_timeout = niu_tx_timeout;
7398         dev->hard_start_xmit = niu_start_xmit;
7399         dev->ethtool_ops = &niu_ethtool_ops;
7400         dev->watchdog_timeo = NIU_TX_TIMEOUT;
7401         dev->change_mtu = niu_change_mtu;
7402 }
7403
7404 static void __devinit niu_device_announce(struct niu *np)
7405 {
7406         struct net_device *dev = np->dev;
7407         int i;
7408
7409         pr_info("%s: NIU Ethernet ", dev->name);
7410         for (i = 0; i < 6; i++)
7411                 printk("%2.2x%c", dev->dev_addr[i],
7412                        i == 5 ? '\n' : ':');
7413
7414         pr_info("%s: Port type[%s] mode[%s:%s] XCVR[%s] phy[%s]\n",
7415                 dev->name,
7416                 (np->flags & NIU_FLAGS_XMAC ? "XMAC" : "BMAC"),
7417                 (np->flags & NIU_FLAGS_10G ? "10G" : "1G"),
7418                 (np->flags & NIU_FLAGS_FIBER ? "FIBER" : "COPPER"),
7419                 (np->mac_xcvr == MAC_XCVR_MII ? "MII" :
7420                  (np->mac_xcvr == MAC_XCVR_PCS ? "PCS" : "XPCS")),
7421                 np->vpd.phy_type);
7422 }
7423
7424 static int __devinit niu_pci_init_one(struct pci_dev *pdev,
7425                                       const struct pci_device_id *ent)
7426 {
7427         unsigned long niureg_base, niureg_len;
7428         union niu_parent_id parent_id;
7429         struct net_device *dev;
7430         struct niu *np;
7431         int err, pos;
7432         u64 dma_mask;
7433         u16 val16;
7434
7435         niu_driver_version();
7436
7437         err = pci_enable_device(pdev);
7438         if (err) {
7439                 dev_err(&pdev->dev, PFX "Cannot enable PCI device, "
7440                         "aborting.\n");
7441                 return err;
7442         }
7443
7444         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM) ||
7445             !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
7446                 dev_err(&pdev->dev, PFX "Cannot find proper PCI device "
7447                         "base addresses, aborting.\n");
7448                 err = -ENODEV;
7449                 goto err_out_disable_pdev;
7450         }
7451
7452         err = pci_request_regions(pdev, DRV_MODULE_NAME);
7453         if (err) {
7454                 dev_err(&pdev->dev, PFX "Cannot obtain PCI resources, "
7455                         "aborting.\n");
7456                 goto err_out_disable_pdev;
7457         }
7458
7459         pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
7460         if (pos <= 0) {
7461                 dev_err(&pdev->dev, PFX "Cannot find PCI Express capability, "
7462                         "aborting.\n");
7463                 goto err_out_free_res;
7464         }
7465
7466         dev = niu_alloc_and_init(&pdev->dev, pdev, NULL,
7467                                  &niu_pci_ops, PCI_FUNC(pdev->devfn));
7468         if (!dev) {
7469                 err = -ENOMEM;
7470                 goto err_out_free_res;
7471         }
7472         np = netdev_priv(dev);
7473
7474         memset(&parent_id, 0, sizeof(parent_id));
7475         parent_id.pci.domain = pci_domain_nr(pdev->bus);
7476         parent_id.pci.bus = pdev->bus->number;
7477         parent_id.pci.device = PCI_SLOT(pdev->devfn);
7478
7479         np->parent = niu_get_parent(np, &parent_id,
7480                                     PLAT_TYPE_ATLAS);
7481         if (!np->parent) {
7482                 err = -ENOMEM;
7483                 goto err_out_free_dev;
7484         }
7485
7486         pci_read_config_word(pdev, pos + PCI_EXP_DEVCTL, &val16);
7487         val16 &= ~PCI_EXP_DEVCTL_NOSNOOP_EN;
7488         val16 |= (PCI_EXP_DEVCTL_CERE |
7489                   PCI_EXP_DEVCTL_NFERE |
7490                   PCI_EXP_DEVCTL_FERE |
7491                   PCI_EXP_DEVCTL_URRE |
7492                   PCI_EXP_DEVCTL_RELAX_EN);
7493         pci_write_config_word(pdev, pos + PCI_EXP_DEVCTL, val16);
7494
7495         dma_mask = DMA_44BIT_MASK;
7496         err = pci_set_dma_mask(pdev, dma_mask);
7497         if (!err) {
7498                 dev->features |= NETIF_F_HIGHDMA;
7499                 err = pci_set_consistent_dma_mask(pdev, dma_mask);
7500                 if (err) {
7501                         dev_err(&pdev->dev, PFX "Unable to obtain 44 bit "
7502                                 "DMA for consistent allocations, "
7503                                 "aborting.\n");
7504                         goto err_out_release_parent;
7505                 }
7506         }
7507         if (err || dma_mask == DMA_32BIT_MASK) {
7508                 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
7509                 if (err) {
7510                         dev_err(&pdev->dev, PFX "No usable DMA configuration, "
7511                                 "aborting.\n");
7512                         goto err_out_release_parent;
7513                 }
7514         }
7515
7516         dev->features |= (NETIF_F_SG | NETIF_F_HW_CSUM);
7517
7518         niureg_base = pci_resource_start(pdev, 0);
7519         niureg_len = pci_resource_len(pdev, 0);
7520
7521         np->regs = ioremap_nocache(niureg_base, niureg_len);
7522         if (!np->regs) {
7523                 dev_err(&pdev->dev, PFX "Cannot map device registers, "
7524                         "aborting.\n");
7525                 err = -ENOMEM;
7526                 goto err_out_release_parent;
7527         }
7528
7529         pci_set_master(pdev);
7530         pci_save_state(pdev);
7531
7532         dev->irq = pdev->irq;
7533
7534         niu_assign_netdev_ops(dev);
7535
7536         err = niu_get_invariants(np);
7537         if (err) {
7538                 if (err != -ENODEV)
7539                         dev_err(&pdev->dev, PFX "Problem fetching invariants "
7540                                 "of chip, aborting.\n");
7541                 goto err_out_iounmap;
7542         }
7543
7544         err = register_netdev(dev);
7545         if (err) {
7546                 dev_err(&pdev->dev, PFX "Cannot register net device, "
7547                         "aborting.\n");
7548                 goto err_out_iounmap;
7549         }
7550
7551         pci_set_drvdata(pdev, dev);
7552
7553         niu_device_announce(np);
7554
7555         return 0;
7556
7557 err_out_iounmap:
7558         if (np->regs) {
7559                 iounmap(np->regs);
7560                 np->regs = NULL;
7561         }
7562
7563 err_out_release_parent:
7564         niu_put_parent(np);
7565
7566 err_out_free_dev:
7567         free_netdev(dev);
7568
7569 err_out_free_res:
7570         pci_release_regions(pdev);
7571
7572 err_out_disable_pdev:
7573         pci_disable_device(pdev);
7574         pci_set_drvdata(pdev, NULL);
7575
7576         return err;
7577 }
7578
7579 static void __devexit niu_pci_remove_one(struct pci_dev *pdev)
7580 {
7581         struct net_device *dev = pci_get_drvdata(pdev);
7582
7583         if (dev) {
7584                 struct niu *np = netdev_priv(dev);
7585
7586                 unregister_netdev(dev);
7587                 if (np->regs) {
7588                         iounmap(np->regs);
7589                         np->regs = NULL;
7590                 }
7591
7592                 niu_ldg_free(np);
7593
7594                 niu_put_parent(np);
7595
7596                 free_netdev(dev);
7597                 pci_release_regions(pdev);
7598                 pci_disable_device(pdev);
7599                 pci_set_drvdata(pdev, NULL);
7600         }
7601 }
7602
7603 static int niu_suspend(struct pci_dev *pdev, pm_message_t state)
7604 {
7605         struct net_device *dev = pci_get_drvdata(pdev);
7606         struct niu *np = netdev_priv(dev);
7607         unsigned long flags;
7608
7609         if (!netif_running(dev))
7610                 return 0;
7611
7612         flush_scheduled_work();
7613         niu_netif_stop(np);
7614
7615         del_timer_sync(&np->timer);
7616
7617         spin_lock_irqsave(&np->lock, flags);
7618         niu_enable_interrupts(np, 0);
7619         spin_unlock_irqrestore(&np->lock, flags);
7620
7621         netif_device_detach(dev);
7622
7623         spin_lock_irqsave(&np->lock, flags);
7624         niu_stop_hw(np);
7625         spin_unlock_irqrestore(&np->lock, flags);
7626
7627         pci_save_state(pdev);
7628
7629         return 0;
7630 }
7631
7632 static int niu_resume(struct pci_dev *pdev)
7633 {
7634         struct net_device *dev = pci_get_drvdata(pdev);
7635         struct niu *np = netdev_priv(dev);
7636         unsigned long flags;
7637         int err;
7638
7639         if (!netif_running(dev))
7640                 return 0;
7641
7642         pci_restore_state(pdev);
7643
7644         netif_device_attach(dev);
7645
7646         spin_lock_irqsave(&np->lock, flags);
7647
7648         err = niu_init_hw(np);
7649         if (!err) {
7650                 np->timer.expires = jiffies + HZ;
7651                 add_timer(&np->timer);
7652                 niu_netif_start(np);
7653         }
7654
7655         spin_unlock_irqrestore(&np->lock, flags);
7656
7657         return err;
7658 }
7659
7660 static struct pci_driver niu_pci_driver = {
7661         .name           = DRV_MODULE_NAME,
7662         .id_table       = niu_pci_tbl,
7663         .probe          = niu_pci_init_one,
7664         .remove         = __devexit_p(niu_pci_remove_one),
7665         .suspend        = niu_suspend,
7666         .resume         = niu_resume,
7667 };
7668
7669 #ifdef CONFIG_SPARC64
7670 static void *niu_phys_alloc_coherent(struct device *dev, size_t size,
7671                                      u64 *dma_addr, gfp_t flag)
7672 {
7673         unsigned long order = get_order(size);
7674         unsigned long page = __get_free_pages(flag, order);
7675
7676         if (page == 0UL)
7677                 return NULL;
7678         memset((char *)page, 0, PAGE_SIZE << order);
7679         *dma_addr = __pa(page);
7680
7681         return (void *) page;
7682 }
7683
7684 static void niu_phys_free_coherent(struct device *dev, size_t size,
7685                                    void *cpu_addr, u64 handle)
7686 {
7687         unsigned long order = get_order(size);
7688
7689         free_pages((unsigned long) cpu_addr, order);
7690 }
7691
7692 static u64 niu_phys_map_page(struct device *dev, struct page *page,
7693                              unsigned long offset, size_t size,
7694                              enum dma_data_direction direction)
7695 {
7696         return page_to_phys(page) + offset;
7697 }
7698
7699 static void niu_phys_unmap_page(struct device *dev, u64 dma_address,
7700                                 size_t size, enum dma_data_direction direction)
7701 {
7702         /* Nothing to do.  */
7703 }
7704
7705 static u64 niu_phys_map_single(struct device *dev, void *cpu_addr,
7706                                size_t size,
7707                                enum dma_data_direction direction)
7708 {
7709         return __pa(cpu_addr);
7710 }
7711
7712 static void niu_phys_unmap_single(struct device *dev, u64 dma_address,
7713                                   size_t size,
7714                                   enum dma_data_direction direction)
7715 {
7716         /* Nothing to do.  */
7717 }
7718
7719 static const struct niu_ops niu_phys_ops = {
7720         .alloc_coherent = niu_phys_alloc_coherent,
7721         .free_coherent  = niu_phys_free_coherent,
7722         .map_page       = niu_phys_map_page,
7723         .unmap_page     = niu_phys_unmap_page,
7724         .map_single     = niu_phys_map_single,
7725         .unmap_single   = niu_phys_unmap_single,
7726 };
7727
7728 static unsigned long res_size(struct resource *r)
7729 {
7730         return r->end - r->start + 1UL;
7731 }
7732
7733 static int __devinit niu_of_probe(struct of_device *op,
7734                                   const struct of_device_id *match)
7735 {
7736         union niu_parent_id parent_id;
7737         struct net_device *dev;
7738         struct niu *np;
7739         const u32 *reg;
7740         int err;
7741
7742         niu_driver_version();
7743
7744         reg = of_get_property(op->node, "reg", NULL);
7745         if (!reg) {
7746                 dev_err(&op->dev, PFX "%s: No 'reg' property, aborting.\n",
7747                         op->node->full_name);
7748                 return -ENODEV;
7749         }
7750
7751         dev = niu_alloc_and_init(&op->dev, NULL, op,
7752                                  &niu_phys_ops, reg[0] & 0x1);
7753         if (!dev) {
7754                 err = -ENOMEM;
7755                 goto err_out;
7756         }
7757         np = netdev_priv(dev);
7758
7759         memset(&parent_id, 0, sizeof(parent_id));
7760         parent_id.of = of_get_parent(op->node);
7761
7762         np->parent = niu_get_parent(np, &parent_id,
7763                                     PLAT_TYPE_NIU);
7764         if (!np->parent) {
7765                 err = -ENOMEM;
7766                 goto err_out_free_dev;
7767         }
7768
7769         dev->features |= (NETIF_F_SG | NETIF_F_HW_CSUM);
7770
7771         np->regs = of_ioremap(&op->resource[1], 0,
7772                               res_size(&op->resource[1]),
7773                               "niu regs");
7774         if (!np->regs) {
7775                 dev_err(&op->dev, PFX "Cannot map device registers, "
7776                         "aborting.\n");
7777                 err = -ENOMEM;
7778                 goto err_out_release_parent;
7779         }
7780
7781         np->vir_regs_1 = of_ioremap(&op->resource[2], 0,
7782                                     res_size(&op->resource[2]),
7783                                     "niu vregs-1");
7784         if (!np->vir_regs_1) {
7785                 dev_err(&op->dev, PFX "Cannot map device vir registers 1, "
7786                         "aborting.\n");
7787                 err = -ENOMEM;
7788                 goto err_out_iounmap;
7789         }
7790
7791         np->vir_regs_2 = of_ioremap(&op->resource[3], 0,
7792                                     res_size(&op->resource[3]),
7793                                     "niu vregs-2");
7794         if (!np->vir_regs_2) {
7795                 dev_err(&op->dev, PFX "Cannot map device vir registers 2, "
7796                         "aborting.\n");
7797                 err = -ENOMEM;
7798                 goto err_out_iounmap;
7799         }
7800
7801         niu_assign_netdev_ops(dev);
7802
7803         err = niu_get_invariants(np);
7804         if (err) {
7805                 if (err != -ENODEV)
7806                         dev_err(&op->dev, PFX "Problem fetching invariants "
7807                                 "of chip, aborting.\n");
7808                 goto err_out_iounmap;
7809         }
7810
7811         err = register_netdev(dev);
7812         if (err) {
7813                 dev_err(&op->dev, PFX "Cannot register net device, "
7814                         "aborting.\n");
7815                 goto err_out_iounmap;
7816         }
7817
7818         dev_set_drvdata(&op->dev, dev);
7819
7820         niu_device_announce(np);
7821
7822         return 0;
7823
7824 err_out_iounmap:
7825         if (np->vir_regs_1) {
7826                 of_iounmap(&op->resource[2], np->vir_regs_1,
7827                            res_size(&op->resource[2]));
7828                 np->vir_regs_1 = NULL;
7829         }
7830
7831         if (np->vir_regs_2) {
7832                 of_iounmap(&op->resource[3], np->vir_regs_2,
7833                            res_size(&op->resource[3]));
7834                 np->vir_regs_2 = NULL;
7835         }
7836
7837         if (np->regs) {
7838                 of_iounmap(&op->resource[1], np->regs,
7839                            res_size(&op->resource[1]));
7840                 np->regs = NULL;
7841         }
7842
7843 err_out_release_parent:
7844         niu_put_parent(np);
7845
7846 err_out_free_dev:
7847         free_netdev(dev);
7848
7849 err_out:
7850         return err;
7851 }
7852
7853 static int __devexit niu_of_remove(struct of_device *op)
7854 {
7855         struct net_device *dev = dev_get_drvdata(&op->dev);
7856
7857         if (dev) {
7858                 struct niu *np = netdev_priv(dev);
7859
7860                 unregister_netdev(dev);
7861
7862                 if (np->vir_regs_1) {
7863                         of_iounmap(&op->resource[2], np->vir_regs_1,
7864                                    res_size(&op->resource[2]));
7865                         np->vir_regs_1 = NULL;
7866                 }
7867
7868                 if (np->vir_regs_2) {
7869                         of_iounmap(&op->resource[3], np->vir_regs_2,
7870                                    res_size(&op->resource[3]));
7871                         np->vir_regs_2 = NULL;
7872                 }
7873
7874                 if (np->regs) {
7875                         of_iounmap(&op->resource[1], np->regs,
7876                                    res_size(&op->resource[1]));
7877                         np->regs = NULL;
7878                 }
7879
7880                 niu_ldg_free(np);
7881
7882                 niu_put_parent(np);
7883
7884                 free_netdev(dev);
7885                 dev_set_drvdata(&op->dev, NULL);
7886         }
7887         return 0;
7888 }
7889
7890 static struct of_device_id niu_match[] = {
7891         {
7892                 .name = "network",
7893                 .compatible = "SUNW,niusl",
7894         },
7895         {},
7896 };
7897 MODULE_DEVICE_TABLE(of, niu_match);
7898
7899 static struct of_platform_driver niu_of_driver = {
7900         .name           = "niu",
7901         .match_table    = niu_match,
7902         .probe          = niu_of_probe,
7903         .remove         = __devexit_p(niu_of_remove),
7904 };
7905
7906 #endif /* CONFIG_SPARC64 */
7907
7908 static int __init niu_init(void)
7909 {
7910         int err = 0;
7911
7912         BUILD_BUG_ON(PAGE_SIZE < 4 * 1024);
7913
7914         niu_debug = netif_msg_init(debug, NIU_MSG_DEFAULT);
7915
7916 #ifdef CONFIG_SPARC64
7917         err = of_register_driver(&niu_of_driver, &of_bus_type);
7918 #endif
7919
7920         if (!err) {
7921                 err = pci_register_driver(&niu_pci_driver);
7922 #ifdef CONFIG_SPARC64
7923                 if (err)
7924                         of_unregister_driver(&niu_of_driver);
7925 #endif
7926         }
7927
7928         return err;
7929 }
7930
7931 static void __exit niu_exit(void)
7932 {
7933         pci_unregister_driver(&niu_pci_driver);
7934 #ifdef CONFIG_SPARC64
7935         of_unregister_driver(&niu_of_driver);
7936 #endif
7937 }
7938
7939 module_init(niu_init);
7940 module_exit(niu_exit);