1 /* niu.c: Neptune ethernet driver.
3 * Copyright (C) 2007, 2008 David S. Miller (davem@davemloft.net)
6 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
8 #include <linux/module.h>
9 #include <linux/init.h>
10 #include <linux/interrupt.h>
11 #include <linux/pci.h>
12 #include <linux/dma-mapping.h>
13 #include <linux/netdevice.h>
14 #include <linux/ethtool.h>
15 #include <linux/etherdevice.h>
16 #include <linux/platform_device.h>
17 #include <linux/delay.h>
18 #include <linux/bitops.h>
19 #include <linux/mii.h>
20 #include <linux/if_ether.h>
21 #include <linux/if_vlan.h>
24 #include <linux/ipv6.h>
25 #include <linux/log2.h>
26 #include <linux/jiffies.h>
27 #include <linux/crc32.h>
28 #include <linux/list.h>
29 #include <linux/slab.h>
32 #include <linux/of_device.h>
36 #define DRV_MODULE_NAME "niu"
37 #define DRV_MODULE_VERSION "1.1"
38 #define DRV_MODULE_RELDATE "Apr 22, 2010"
40 static char version[] __devinitdata =
41 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
43 MODULE_AUTHOR("David S. Miller (davem@davemloft.net)");
44 MODULE_DESCRIPTION("NIU ethernet driver");
45 MODULE_LICENSE("GPL");
46 MODULE_VERSION(DRV_MODULE_VERSION);
49 static u64 readq(void __iomem *reg)
51 return ((u64) readl(reg)) | (((u64) readl(reg + 4UL)) << 32);
54 static void writeq(u64 val, void __iomem *reg)
56 writel(val & 0xffffffff, reg);
57 writel(val >> 32, reg + 0x4UL);
61 static DEFINE_PCI_DEVICE_TABLE(niu_pci_tbl) = {
62 {PCI_DEVICE(PCI_VENDOR_ID_SUN, 0xabcd)},
66 MODULE_DEVICE_TABLE(pci, niu_pci_tbl);
68 #define NIU_TX_TIMEOUT (5 * HZ)
70 #define nr64(reg) readq(np->regs + (reg))
71 #define nw64(reg, val) writeq((val), np->regs + (reg))
73 #define nr64_mac(reg) readq(np->mac_regs + (reg))
74 #define nw64_mac(reg, val) writeq((val), np->mac_regs + (reg))
76 #define nr64_ipp(reg) readq(np->regs + np->ipp_off + (reg))
77 #define nw64_ipp(reg, val) writeq((val), np->regs + np->ipp_off + (reg))
79 #define nr64_pcs(reg) readq(np->regs + np->pcs_off + (reg))
80 #define nw64_pcs(reg, val) writeq((val), np->regs + np->pcs_off + (reg))
82 #define nr64_xpcs(reg) readq(np->regs + np->xpcs_off + (reg))
83 #define nw64_xpcs(reg, val) writeq((val), np->regs + np->xpcs_off + (reg))
85 #define NIU_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
88 static int debug = -1;
89 module_param(debug, int, 0);
90 MODULE_PARM_DESC(debug, "NIU debug level");
92 #define niu_lock_parent(np, flags) \
93 spin_lock_irqsave(&np->parent->lock, flags)
94 #define niu_unlock_parent(np, flags) \
95 spin_unlock_irqrestore(&np->parent->lock, flags)
97 static int serdes_init_10g_serdes(struct niu *np);
99 static int __niu_wait_bits_clear_mac(struct niu *np, unsigned long reg,
100 u64 bits, int limit, int delay)
102 while (--limit >= 0) {
103 u64 val = nr64_mac(reg);
114 static int __niu_set_and_wait_clear_mac(struct niu *np, unsigned long reg,
115 u64 bits, int limit, int delay,
116 const char *reg_name)
121 err = __niu_wait_bits_clear_mac(np, reg, bits, limit, delay);
123 netdev_err(np->dev, "bits (%llx) of register %s would not clear, val[%llx]\n",
124 (unsigned long long)bits, reg_name,
125 (unsigned long long)nr64_mac(reg));
129 #define niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
130 ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
131 __niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
134 static int __niu_wait_bits_clear_ipp(struct niu *np, unsigned long reg,
135 u64 bits, int limit, int delay)
137 while (--limit >= 0) {
138 u64 val = nr64_ipp(reg);
149 static int __niu_set_and_wait_clear_ipp(struct niu *np, unsigned long reg,
150 u64 bits, int limit, int delay,
151 const char *reg_name)
160 err = __niu_wait_bits_clear_ipp(np, reg, bits, limit, delay);
162 netdev_err(np->dev, "bits (%llx) of register %s would not clear, val[%llx]\n",
163 (unsigned long long)bits, reg_name,
164 (unsigned long long)nr64_ipp(reg));
168 #define niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
169 ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
170 __niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
173 static int __niu_wait_bits_clear(struct niu *np, unsigned long reg,
174 u64 bits, int limit, int delay)
176 while (--limit >= 0) {
188 #define niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY) \
189 ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
190 __niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY); \
193 static int __niu_set_and_wait_clear(struct niu *np, unsigned long reg,
194 u64 bits, int limit, int delay,
195 const char *reg_name)
200 err = __niu_wait_bits_clear(np, reg, bits, limit, delay);
202 netdev_err(np->dev, "bits (%llx) of register %s would not clear, val[%llx]\n",
203 (unsigned long long)bits, reg_name,
204 (unsigned long long)nr64(reg));
208 #define niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
209 ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
210 __niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
213 static void niu_ldg_rearm(struct niu *np, struct niu_ldg *lp, int on)
215 u64 val = (u64) lp->timer;
218 val |= LDG_IMGMT_ARM;
220 nw64(LDG_IMGMT(lp->ldg_num), val);
223 static int niu_ldn_irq_enable(struct niu *np, int ldn, int on)
225 unsigned long mask_reg, bits;
228 if (ldn < 0 || ldn > LDN_MAX)
232 mask_reg = LD_IM0(ldn);
235 mask_reg = LD_IM1(ldn - 64);
239 val = nr64(mask_reg);
249 static int niu_enable_ldn_in_ldg(struct niu *np, struct niu_ldg *lp, int on)
251 struct niu_parent *parent = np->parent;
254 for (i = 0; i <= LDN_MAX; i++) {
257 if (parent->ldg_map[i] != lp->ldg_num)
260 err = niu_ldn_irq_enable(np, i, on);
267 static int niu_enable_interrupts(struct niu *np, int on)
271 for (i = 0; i < np->num_ldg; i++) {
272 struct niu_ldg *lp = &np->ldg[i];
275 err = niu_enable_ldn_in_ldg(np, lp, on);
279 for (i = 0; i < np->num_ldg; i++)
280 niu_ldg_rearm(np, &np->ldg[i], on);
285 static u32 phy_encode(u32 type, int port)
287 return type << (port * 2);
290 static u32 phy_decode(u32 val, int port)
292 return (val >> (port * 2)) & PORT_TYPE_MASK;
295 static int mdio_wait(struct niu *np)
300 while (--limit > 0) {
301 val = nr64(MIF_FRAME_OUTPUT);
302 if ((val >> MIF_FRAME_OUTPUT_TA_SHIFT) & 0x1)
303 return val & MIF_FRAME_OUTPUT_DATA;
311 static int mdio_read(struct niu *np, int port, int dev, int reg)
315 nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg));
320 nw64(MIF_FRAME_OUTPUT, MDIO_READ_OP(port, dev));
321 return mdio_wait(np);
324 static int mdio_write(struct niu *np, int port, int dev, int reg, int data)
328 nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg));
333 nw64(MIF_FRAME_OUTPUT, MDIO_WRITE_OP(port, dev, data));
341 static int mii_read(struct niu *np, int port, int reg)
343 nw64(MIF_FRAME_OUTPUT, MII_READ_OP(port, reg));
344 return mdio_wait(np);
347 static int mii_write(struct niu *np, int port, int reg, int data)
351 nw64(MIF_FRAME_OUTPUT, MII_WRITE_OP(port, reg, data));
359 static int esr2_set_tx_cfg(struct niu *np, unsigned long channel, u32 val)
363 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
364 ESR2_TI_PLL_TX_CFG_L(channel),
367 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
368 ESR2_TI_PLL_TX_CFG_H(channel),
373 static int esr2_set_rx_cfg(struct niu *np, unsigned long channel, u32 val)
377 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
378 ESR2_TI_PLL_RX_CFG_L(channel),
381 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
382 ESR2_TI_PLL_RX_CFG_H(channel),
387 /* Mode is always 10G fiber. */
388 static int serdes_init_niu_10g_fiber(struct niu *np)
390 struct niu_link_config *lp = &np->link_config;
394 tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV);
395 rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
396 PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
397 PLL_RX_CFG_EQ_LP_ADAPTIVE);
399 if (lp->loopback_mode == LOOPBACK_PHY) {
400 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
402 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
403 ESR2_TI_PLL_TEST_CFG_L, test_cfg);
405 tx_cfg |= PLL_TX_CFG_ENTEST;
406 rx_cfg |= PLL_RX_CFG_ENTEST;
409 /* Initialize all 4 lanes of the SERDES. */
410 for (i = 0; i < 4; i++) {
411 int err = esr2_set_tx_cfg(np, i, tx_cfg);
416 for (i = 0; i < 4; i++) {
417 int err = esr2_set_rx_cfg(np, i, rx_cfg);
425 static int serdes_init_niu_1g_serdes(struct niu *np)
427 struct niu_link_config *lp = &np->link_config;
428 u16 pll_cfg, pll_sts;
430 u64 uninitialized_var(sig), mask, val;
435 tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV |
436 PLL_TX_CFG_RATE_HALF);
437 rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
438 PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
439 PLL_RX_CFG_RATE_HALF);
442 rx_cfg |= PLL_RX_CFG_EQ_LP_ADAPTIVE;
444 if (lp->loopback_mode == LOOPBACK_PHY) {
445 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
447 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
448 ESR2_TI_PLL_TEST_CFG_L, test_cfg);
450 tx_cfg |= PLL_TX_CFG_ENTEST;
451 rx_cfg |= PLL_RX_CFG_ENTEST;
454 /* Initialize PLL for 1G */
455 pll_cfg = (PLL_CFG_ENPLL | PLL_CFG_MPY_8X);
457 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
458 ESR2_TI_PLL_CFG_L, pll_cfg);
460 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_CFG_L failed\n",
465 pll_sts = PLL_CFG_ENPLL;
467 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
468 ESR2_TI_PLL_STS_L, pll_sts);
470 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_STS_L failed\n",
477 /* Initialize all 4 lanes of the SERDES. */
478 for (i = 0; i < 4; i++) {
479 err = esr2_set_tx_cfg(np, i, tx_cfg);
484 for (i = 0; i < 4; i++) {
485 err = esr2_set_rx_cfg(np, i, rx_cfg);
492 val = (ESR_INT_SRDY0_P0 | ESR_INT_DET0_P0);
497 val = (ESR_INT_SRDY0_P1 | ESR_INT_DET0_P1);
505 while (max_retry--) {
506 sig = nr64(ESR_INT_SIGNALS);
507 if ((sig & mask) == val)
513 if ((sig & mask) != val) {
514 netdev_err(np->dev, "Port %u signal bits [%08x] are not [%08x]\n",
515 np->port, (int)(sig & mask), (int)val);
522 static int serdes_init_niu_10g_serdes(struct niu *np)
524 struct niu_link_config *lp = &np->link_config;
525 u32 tx_cfg, rx_cfg, pll_cfg, pll_sts;
527 u64 uninitialized_var(sig), mask, val;
531 tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV);
532 rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
533 PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
534 PLL_RX_CFG_EQ_LP_ADAPTIVE);
536 if (lp->loopback_mode == LOOPBACK_PHY) {
537 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
539 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
540 ESR2_TI_PLL_TEST_CFG_L, test_cfg);
542 tx_cfg |= PLL_TX_CFG_ENTEST;
543 rx_cfg |= PLL_RX_CFG_ENTEST;
546 /* Initialize PLL for 10G */
547 pll_cfg = (PLL_CFG_ENPLL | PLL_CFG_MPY_10X);
549 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
550 ESR2_TI_PLL_CFG_L, pll_cfg & 0xffff);
552 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_CFG_L failed\n",
557 pll_sts = PLL_CFG_ENPLL;
559 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
560 ESR2_TI_PLL_STS_L, pll_sts & 0xffff);
562 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_STS_L failed\n",
569 /* Initialize all 4 lanes of the SERDES. */
570 for (i = 0; i < 4; i++) {
571 err = esr2_set_tx_cfg(np, i, tx_cfg);
576 for (i = 0; i < 4; i++) {
577 err = esr2_set_rx_cfg(np, i, rx_cfg);
582 /* check if serdes is ready */
586 mask = ESR_INT_SIGNALS_P0_BITS;
587 val = (ESR_INT_SRDY0_P0 |
597 mask = ESR_INT_SIGNALS_P1_BITS;
598 val = (ESR_INT_SRDY0_P1 |
611 while (max_retry--) {
612 sig = nr64(ESR_INT_SIGNALS);
613 if ((sig & mask) == val)
619 if ((sig & mask) != val) {
620 pr_info("NIU Port %u signal bits [%08x] are not [%08x] for 10G...trying 1G\n",
621 np->port, (int)(sig & mask), (int)val);
623 /* 10G failed, try initializing at 1G */
624 err = serdes_init_niu_1g_serdes(np);
626 np->flags &= ~NIU_FLAGS_10G;
627 np->mac_xcvr = MAC_XCVR_PCS;
629 netdev_err(np->dev, "Port %u 10G/1G SERDES Link Failed\n",
637 static int esr_read_rxtx_ctrl(struct niu *np, unsigned long chan, u32 *val)
641 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR, ESR_RXTX_CTRL_L(chan));
643 *val = (err & 0xffff);
644 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
645 ESR_RXTX_CTRL_H(chan));
647 *val |= ((err & 0xffff) << 16);
653 static int esr_read_glue0(struct niu *np, unsigned long chan, u32 *val)
657 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
658 ESR_GLUE_CTRL0_L(chan));
660 *val = (err & 0xffff);
661 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
662 ESR_GLUE_CTRL0_H(chan));
664 *val |= ((err & 0xffff) << 16);
671 static int esr_read_reset(struct niu *np, u32 *val)
675 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
676 ESR_RXTX_RESET_CTRL_L);
678 *val = (err & 0xffff);
679 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
680 ESR_RXTX_RESET_CTRL_H);
682 *val |= ((err & 0xffff) << 16);
689 static int esr_write_rxtx_ctrl(struct niu *np, unsigned long chan, u32 val)
693 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
694 ESR_RXTX_CTRL_L(chan), val & 0xffff);
696 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
697 ESR_RXTX_CTRL_H(chan), (val >> 16));
701 static int esr_write_glue0(struct niu *np, unsigned long chan, u32 val)
705 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
706 ESR_GLUE_CTRL0_L(chan), val & 0xffff);
708 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
709 ESR_GLUE_CTRL0_H(chan), (val >> 16));
713 static int esr_reset(struct niu *np)
715 u32 uninitialized_var(reset);
718 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
719 ESR_RXTX_RESET_CTRL_L, 0x0000);
722 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
723 ESR_RXTX_RESET_CTRL_H, 0xffff);
728 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
729 ESR_RXTX_RESET_CTRL_L, 0xffff);
734 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
735 ESR_RXTX_RESET_CTRL_H, 0x0000);
740 err = esr_read_reset(np, &reset);
744 netdev_err(np->dev, "Port %u ESR_RESET did not clear [%08x]\n",
752 static int serdes_init_10g(struct niu *np)
754 struct niu_link_config *lp = &np->link_config;
755 unsigned long ctrl_reg, test_cfg_reg, i;
756 u64 ctrl_val, test_cfg_val, sig, mask, val;
761 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
762 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
765 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
766 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
772 ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
773 ENET_SERDES_CTRL_SDET_1 |
774 ENET_SERDES_CTRL_SDET_2 |
775 ENET_SERDES_CTRL_SDET_3 |
776 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
777 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
778 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
779 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
780 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
781 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
782 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
783 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
786 if (lp->loopback_mode == LOOPBACK_PHY) {
787 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
788 ENET_SERDES_TEST_MD_0_SHIFT) |
789 (ENET_TEST_MD_PAD_LOOPBACK <<
790 ENET_SERDES_TEST_MD_1_SHIFT) |
791 (ENET_TEST_MD_PAD_LOOPBACK <<
792 ENET_SERDES_TEST_MD_2_SHIFT) |
793 (ENET_TEST_MD_PAD_LOOPBACK <<
794 ENET_SERDES_TEST_MD_3_SHIFT));
797 nw64(ctrl_reg, ctrl_val);
798 nw64(test_cfg_reg, test_cfg_val);
800 /* Initialize all 4 lanes of the SERDES. */
801 for (i = 0; i < 4; i++) {
802 u32 rxtx_ctrl, glue0;
804 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
807 err = esr_read_glue0(np, i, &glue0);
811 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
812 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
813 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
815 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
816 ESR_GLUE_CTRL0_THCNT |
817 ESR_GLUE_CTRL0_BLTIME);
818 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
819 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
820 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
821 (BLTIME_300_CYCLES <<
822 ESR_GLUE_CTRL0_BLTIME_SHIFT));
824 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
827 err = esr_write_glue0(np, i, glue0);
836 sig = nr64(ESR_INT_SIGNALS);
839 mask = ESR_INT_SIGNALS_P0_BITS;
840 val = (ESR_INT_SRDY0_P0 |
850 mask = ESR_INT_SIGNALS_P1_BITS;
851 val = (ESR_INT_SRDY0_P1 |
864 if ((sig & mask) != val) {
865 if (np->flags & NIU_FLAGS_HOTPLUG_PHY) {
866 np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
869 netdev_err(np->dev, "Port %u signal bits [%08x] are not [%08x]\n",
870 np->port, (int)(sig & mask), (int)val);
873 if (np->flags & NIU_FLAGS_HOTPLUG_PHY)
874 np->flags |= NIU_FLAGS_HOTPLUG_PHY_PRESENT;
878 static int serdes_init_1g(struct niu *np)
882 val = nr64(ENET_SERDES_1_PLL_CFG);
883 val &= ~ENET_SERDES_PLL_FBDIV2;
886 val |= ENET_SERDES_PLL_HRATE0;
889 val |= ENET_SERDES_PLL_HRATE1;
892 val |= ENET_SERDES_PLL_HRATE2;
895 val |= ENET_SERDES_PLL_HRATE3;
900 nw64(ENET_SERDES_1_PLL_CFG, val);
905 static int serdes_init_1g_serdes(struct niu *np)
907 struct niu_link_config *lp = &np->link_config;
908 unsigned long ctrl_reg, test_cfg_reg, pll_cfg, i;
909 u64 ctrl_val, test_cfg_val, sig, mask, val;
911 u64 reset_val, val_rd;
913 val = ENET_SERDES_PLL_HRATE0 | ENET_SERDES_PLL_HRATE1 |
914 ENET_SERDES_PLL_HRATE2 | ENET_SERDES_PLL_HRATE3 |
915 ENET_SERDES_PLL_FBDIV0;
918 reset_val = ENET_SERDES_RESET_0;
919 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
920 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
921 pll_cfg = ENET_SERDES_0_PLL_CFG;
924 reset_val = ENET_SERDES_RESET_1;
925 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
926 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
927 pll_cfg = ENET_SERDES_1_PLL_CFG;
933 ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
934 ENET_SERDES_CTRL_SDET_1 |
935 ENET_SERDES_CTRL_SDET_2 |
936 ENET_SERDES_CTRL_SDET_3 |
937 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
938 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
939 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
940 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
941 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
942 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
943 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
944 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
947 if (lp->loopback_mode == LOOPBACK_PHY) {
948 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
949 ENET_SERDES_TEST_MD_0_SHIFT) |
950 (ENET_TEST_MD_PAD_LOOPBACK <<
951 ENET_SERDES_TEST_MD_1_SHIFT) |
952 (ENET_TEST_MD_PAD_LOOPBACK <<
953 ENET_SERDES_TEST_MD_2_SHIFT) |
954 (ENET_TEST_MD_PAD_LOOPBACK <<
955 ENET_SERDES_TEST_MD_3_SHIFT));
958 nw64(ENET_SERDES_RESET, reset_val);
960 val_rd = nr64(ENET_SERDES_RESET);
961 val_rd &= ~reset_val;
963 nw64(ctrl_reg, ctrl_val);
964 nw64(test_cfg_reg, test_cfg_val);
965 nw64(ENET_SERDES_RESET, val_rd);
968 /* Initialize all 4 lanes of the SERDES. */
969 for (i = 0; i < 4; i++) {
970 u32 rxtx_ctrl, glue0;
972 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
975 err = esr_read_glue0(np, i, &glue0);
979 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
980 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
981 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
983 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
984 ESR_GLUE_CTRL0_THCNT |
985 ESR_GLUE_CTRL0_BLTIME);
986 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
987 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
988 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
989 (BLTIME_300_CYCLES <<
990 ESR_GLUE_CTRL0_BLTIME_SHIFT));
992 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
995 err = esr_write_glue0(np, i, glue0);
1001 sig = nr64(ESR_INT_SIGNALS);
1004 val = (ESR_INT_SRDY0_P0 | ESR_INT_DET0_P0);
1009 val = (ESR_INT_SRDY0_P1 | ESR_INT_DET0_P1);
1017 if ((sig & mask) != val) {
1018 netdev_err(np->dev, "Port %u signal bits [%08x] are not [%08x]\n",
1019 np->port, (int)(sig & mask), (int)val);
1026 static int link_status_1g_serdes(struct niu *np, int *link_up_p)
1028 struct niu_link_config *lp = &np->link_config;
1032 unsigned long flags;
1036 current_speed = SPEED_INVALID;
1037 current_duplex = DUPLEX_INVALID;
1039 spin_lock_irqsave(&np->lock, flags);
1041 val = nr64_pcs(PCS_MII_STAT);
1043 if (val & PCS_MII_STAT_LINK_STATUS) {
1045 current_speed = SPEED_1000;
1046 current_duplex = DUPLEX_FULL;
1049 lp->active_speed = current_speed;
1050 lp->active_duplex = current_duplex;
1051 spin_unlock_irqrestore(&np->lock, flags);
1053 *link_up_p = link_up;
1057 static int link_status_10g_serdes(struct niu *np, int *link_up_p)
1059 unsigned long flags;
1060 struct niu_link_config *lp = &np->link_config;
1067 if (!(np->flags & NIU_FLAGS_10G))
1068 return link_status_1g_serdes(np, link_up_p);
1070 current_speed = SPEED_INVALID;
1071 current_duplex = DUPLEX_INVALID;
1072 spin_lock_irqsave(&np->lock, flags);
1074 val = nr64_xpcs(XPCS_STATUS(0));
1075 val2 = nr64_mac(XMAC_INTER2);
1076 if (val2 & 0x01000000)
1079 if ((val & 0x1000ULL) && link_ok) {
1081 current_speed = SPEED_10000;
1082 current_duplex = DUPLEX_FULL;
1084 lp->active_speed = current_speed;
1085 lp->active_duplex = current_duplex;
1086 spin_unlock_irqrestore(&np->lock, flags);
1087 *link_up_p = link_up;
1091 static int link_status_mii(struct niu *np, int *link_up_p)
1093 struct niu_link_config *lp = &np->link_config;
1095 int bmsr, advert, ctrl1000, stat1000, lpa, bmcr, estatus;
1096 int supported, advertising, active_speed, active_duplex;
1098 err = mii_read(np, np->phy_addr, MII_BMCR);
1099 if (unlikely(err < 0))
1103 err = mii_read(np, np->phy_addr, MII_BMSR);
1104 if (unlikely(err < 0))
1108 err = mii_read(np, np->phy_addr, MII_ADVERTISE);
1109 if (unlikely(err < 0))
1113 err = mii_read(np, np->phy_addr, MII_LPA);
1114 if (unlikely(err < 0))
1118 if (likely(bmsr & BMSR_ESTATEN)) {
1119 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1120 if (unlikely(err < 0))
1124 err = mii_read(np, np->phy_addr, MII_CTRL1000);
1125 if (unlikely(err < 0))
1129 err = mii_read(np, np->phy_addr, MII_STAT1000);
1130 if (unlikely(err < 0))
1134 estatus = ctrl1000 = stat1000 = 0;
1137 if (bmsr & BMSR_ANEGCAPABLE)
1138 supported |= SUPPORTED_Autoneg;
1139 if (bmsr & BMSR_10HALF)
1140 supported |= SUPPORTED_10baseT_Half;
1141 if (bmsr & BMSR_10FULL)
1142 supported |= SUPPORTED_10baseT_Full;
1143 if (bmsr & BMSR_100HALF)
1144 supported |= SUPPORTED_100baseT_Half;
1145 if (bmsr & BMSR_100FULL)
1146 supported |= SUPPORTED_100baseT_Full;
1147 if (estatus & ESTATUS_1000_THALF)
1148 supported |= SUPPORTED_1000baseT_Half;
1149 if (estatus & ESTATUS_1000_TFULL)
1150 supported |= SUPPORTED_1000baseT_Full;
1151 lp->supported = supported;
1154 if (advert & ADVERTISE_10HALF)
1155 advertising |= ADVERTISED_10baseT_Half;
1156 if (advert & ADVERTISE_10FULL)
1157 advertising |= ADVERTISED_10baseT_Full;
1158 if (advert & ADVERTISE_100HALF)
1159 advertising |= ADVERTISED_100baseT_Half;
1160 if (advert & ADVERTISE_100FULL)
1161 advertising |= ADVERTISED_100baseT_Full;
1162 if (ctrl1000 & ADVERTISE_1000HALF)
1163 advertising |= ADVERTISED_1000baseT_Half;
1164 if (ctrl1000 & ADVERTISE_1000FULL)
1165 advertising |= ADVERTISED_1000baseT_Full;
1167 if (bmcr & BMCR_ANENABLE) {
1170 lp->active_autoneg = 1;
1171 advertising |= ADVERTISED_Autoneg;
1174 neg1000 = (ctrl1000 << 2) & stat1000;
1176 if (neg1000 & (LPA_1000FULL | LPA_1000HALF))
1177 active_speed = SPEED_1000;
1178 else if (neg & LPA_100)
1179 active_speed = SPEED_100;
1180 else if (neg & (LPA_10HALF | LPA_10FULL))
1181 active_speed = SPEED_10;
1183 active_speed = SPEED_INVALID;
1185 if ((neg1000 & LPA_1000FULL) || (neg & LPA_DUPLEX))
1186 active_duplex = DUPLEX_FULL;
1187 else if (active_speed != SPEED_INVALID)
1188 active_duplex = DUPLEX_HALF;
1190 active_duplex = DUPLEX_INVALID;
1192 lp->active_autoneg = 0;
1194 if ((bmcr & BMCR_SPEED1000) && !(bmcr & BMCR_SPEED100))
1195 active_speed = SPEED_1000;
1196 else if (bmcr & BMCR_SPEED100)
1197 active_speed = SPEED_100;
1199 active_speed = SPEED_10;
1201 if (bmcr & BMCR_FULLDPLX)
1202 active_duplex = DUPLEX_FULL;
1204 active_duplex = DUPLEX_HALF;
1207 lp->active_advertising = advertising;
1208 lp->active_speed = active_speed;
1209 lp->active_duplex = active_duplex;
1210 *link_up_p = !!(bmsr & BMSR_LSTATUS);
1215 static int link_status_1g_rgmii(struct niu *np, int *link_up_p)
1217 struct niu_link_config *lp = &np->link_config;
1218 u16 current_speed, bmsr;
1219 unsigned long flags;
1224 current_speed = SPEED_INVALID;
1225 current_duplex = DUPLEX_INVALID;
1227 spin_lock_irqsave(&np->lock, flags);
1231 err = mii_read(np, np->phy_addr, MII_BMSR);
1236 if (bmsr & BMSR_LSTATUS) {
1239 err = mii_read(np, np->phy_addr, MII_ADVERTISE);
1244 err = mii_read(np, np->phy_addr, MII_LPA);
1249 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1253 current_speed = SPEED_1000;
1254 current_duplex = DUPLEX_FULL;
1257 lp->active_speed = current_speed;
1258 lp->active_duplex = current_duplex;
1262 spin_unlock_irqrestore(&np->lock, flags);
1264 *link_up_p = link_up;
1268 static int link_status_1g(struct niu *np, int *link_up_p)
1270 struct niu_link_config *lp = &np->link_config;
1271 unsigned long flags;
1274 spin_lock_irqsave(&np->lock, flags);
1276 err = link_status_mii(np, link_up_p);
1277 lp->supported |= SUPPORTED_TP;
1278 lp->active_advertising |= ADVERTISED_TP;
1280 spin_unlock_irqrestore(&np->lock, flags);
1284 static int bcm8704_reset(struct niu *np)
1288 err = mdio_read(np, np->phy_addr,
1289 BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
1290 if (err < 0 || err == 0xffff)
1293 err = mdio_write(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
1299 while (--limit >= 0) {
1300 err = mdio_read(np, np->phy_addr,
1301 BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
1304 if (!(err & BMCR_RESET))
1308 netdev_err(np->dev, "Port %u PHY will not reset (bmcr=%04x)\n",
1309 np->port, (err & 0xffff));
1315 /* When written, certain PHY registers need to be read back twice
1316 * in order for the bits to settle properly.
1318 static int bcm8704_user_dev3_readback(struct niu *np, int reg)
1320 int err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg);
1323 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg);
1329 static int bcm8706_init_user_dev3(struct niu *np)
1334 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1335 BCM8704_USER_OPT_DIGITAL_CTRL);
1338 err &= ~USER_ODIG_CTRL_GPIOS;
1339 err |= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT);
1340 err |= USER_ODIG_CTRL_RESV2;
1341 err = mdio_write(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1342 BCM8704_USER_OPT_DIGITAL_CTRL, err);
1351 static int bcm8704_init_user_dev3(struct niu *np)
1355 err = mdio_write(np, np->phy_addr,
1356 BCM8704_USER_DEV3_ADDR, BCM8704_USER_CONTROL,
1357 (USER_CONTROL_OPTXRST_LVL |
1358 USER_CONTROL_OPBIASFLT_LVL |
1359 USER_CONTROL_OBTMPFLT_LVL |
1360 USER_CONTROL_OPPRFLT_LVL |
1361 USER_CONTROL_OPTXFLT_LVL |
1362 USER_CONTROL_OPRXLOS_LVL |
1363 USER_CONTROL_OPRXFLT_LVL |
1364 USER_CONTROL_OPTXON_LVL |
1365 (0x3f << USER_CONTROL_RES1_SHIFT)));
1369 err = mdio_write(np, np->phy_addr,
1370 BCM8704_USER_DEV3_ADDR, BCM8704_USER_PMD_TX_CONTROL,
1371 (USER_PMD_TX_CTL_XFP_CLKEN |
1372 (1 << USER_PMD_TX_CTL_TX_DAC_TXD_SH) |
1373 (2 << USER_PMD_TX_CTL_TX_DAC_TXCK_SH) |
1374 USER_PMD_TX_CTL_TSCK_LPWREN));
1378 err = bcm8704_user_dev3_readback(np, BCM8704_USER_CONTROL);
1381 err = bcm8704_user_dev3_readback(np, BCM8704_USER_PMD_TX_CONTROL);
1385 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1386 BCM8704_USER_OPT_DIGITAL_CTRL);
1389 err &= ~USER_ODIG_CTRL_GPIOS;
1390 err |= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT);
1391 err = mdio_write(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1392 BCM8704_USER_OPT_DIGITAL_CTRL, err);
1401 static int mrvl88x2011_act_led(struct niu *np, int val)
1405 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1406 MRVL88X2011_LED_8_TO_11_CTL);
1410 err &= ~MRVL88X2011_LED(MRVL88X2011_LED_ACT,MRVL88X2011_LED_CTL_MASK);
1411 err |= MRVL88X2011_LED(MRVL88X2011_LED_ACT,val);
1413 return mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1414 MRVL88X2011_LED_8_TO_11_CTL, err);
1417 static int mrvl88x2011_led_blink_rate(struct niu *np, int rate)
1421 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1422 MRVL88X2011_LED_BLINK_CTL);
1424 err &= ~MRVL88X2011_LED_BLKRATE_MASK;
1427 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1428 MRVL88X2011_LED_BLINK_CTL, err);
1434 static int xcvr_init_10g_mrvl88x2011(struct niu *np)
1438 /* Set LED functions */
1439 err = mrvl88x2011_led_blink_rate(np, MRVL88X2011_LED_BLKRATE_134MS);
1444 err = mrvl88x2011_act_led(np, MRVL88X2011_LED_CTL_OFF);
1448 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1449 MRVL88X2011_GENERAL_CTL);
1453 err |= MRVL88X2011_ENA_XFPREFCLK;
1455 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1456 MRVL88X2011_GENERAL_CTL, err);
1460 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1461 MRVL88X2011_PMA_PMD_CTL_1);
1465 if (np->link_config.loopback_mode == LOOPBACK_MAC)
1466 err |= MRVL88X2011_LOOPBACK;
1468 err &= ~MRVL88X2011_LOOPBACK;
1470 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1471 MRVL88X2011_PMA_PMD_CTL_1, err);
1476 return mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1477 MRVL88X2011_10G_PMD_TX_DIS, MRVL88X2011_ENA_PMDTX);
1481 static int xcvr_diag_bcm870x(struct niu *np)
1483 u16 analog_stat0, tx_alarm_status;
1487 err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
1491 pr_info("Port %u PMA_PMD(MII_STAT1000) [%04x]\n", np->port, err);
1493 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, 0x20);
1496 pr_info("Port %u USER_DEV3(0x20) [%04x]\n", np->port, err);
1498 err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
1502 pr_info("Port %u PHYXS(MII_NWAYTEST) [%04x]\n", np->port, err);
1505 /* XXX dig this out it might not be so useful XXX */
1506 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1507 BCM8704_USER_ANALOG_STATUS0);
1510 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1511 BCM8704_USER_ANALOG_STATUS0);
1516 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1517 BCM8704_USER_TX_ALARM_STATUS);
1520 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1521 BCM8704_USER_TX_ALARM_STATUS);
1524 tx_alarm_status = err;
1526 if (analog_stat0 != 0x03fc) {
1527 if ((analog_stat0 == 0x43bc) && (tx_alarm_status != 0)) {
1528 pr_info("Port %u cable not connected or bad cable\n",
1530 } else if (analog_stat0 == 0x639c) {
1531 pr_info("Port %u optical module is bad or missing\n",
1539 static int xcvr_10g_set_lb_bcm870x(struct niu *np)
1541 struct niu_link_config *lp = &np->link_config;
1544 err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
1549 err &= ~BMCR_LOOPBACK;
1551 if (lp->loopback_mode == LOOPBACK_MAC)
1552 err |= BMCR_LOOPBACK;
1554 err = mdio_write(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
1562 static int xcvr_init_10g_bcm8706(struct niu *np)
1567 if ((np->flags & NIU_FLAGS_HOTPLUG_PHY) &&
1568 (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) == 0)
1571 val = nr64_mac(XMAC_CONFIG);
1572 val &= ~XMAC_CONFIG_LED_POLARITY;
1573 val |= XMAC_CONFIG_FORCE_LED_ON;
1574 nw64_mac(XMAC_CONFIG, val);
1576 val = nr64(MIF_CONFIG);
1577 val |= MIF_CONFIG_INDIRECT_MODE;
1578 nw64(MIF_CONFIG, val);
1580 err = bcm8704_reset(np);
1584 err = xcvr_10g_set_lb_bcm870x(np);
1588 err = bcm8706_init_user_dev3(np);
1592 err = xcvr_diag_bcm870x(np);
1599 static int xcvr_init_10g_bcm8704(struct niu *np)
1603 err = bcm8704_reset(np);
1607 err = bcm8704_init_user_dev3(np);
1611 err = xcvr_10g_set_lb_bcm870x(np);
1615 err = xcvr_diag_bcm870x(np);
1622 static int xcvr_init_10g(struct niu *np)
1627 val = nr64_mac(XMAC_CONFIG);
1628 val &= ~XMAC_CONFIG_LED_POLARITY;
1629 val |= XMAC_CONFIG_FORCE_LED_ON;
1630 nw64_mac(XMAC_CONFIG, val);
1632 /* XXX shared resource, lock parent XXX */
1633 val = nr64(MIF_CONFIG);
1634 val |= MIF_CONFIG_INDIRECT_MODE;
1635 nw64(MIF_CONFIG, val);
1637 phy_id = phy_decode(np->parent->port_phy, np->port);
1638 phy_id = np->parent->phy_probe_info.phy_id[phy_id][np->port];
1640 /* handle different phy types */
1641 switch (phy_id & NIU_PHY_ID_MASK) {
1642 case NIU_PHY_ID_MRVL88X2011:
1643 err = xcvr_init_10g_mrvl88x2011(np);
1646 default: /* bcom 8704 */
1647 err = xcvr_init_10g_bcm8704(np);
1654 static int mii_reset(struct niu *np)
1658 err = mii_write(np, np->phy_addr, MII_BMCR, BMCR_RESET);
1663 while (--limit >= 0) {
1665 err = mii_read(np, np->phy_addr, MII_BMCR);
1668 if (!(err & BMCR_RESET))
1672 netdev_err(np->dev, "Port %u MII would not reset, bmcr[%04x]\n",
1680 static int xcvr_init_1g_rgmii(struct niu *np)
1684 u16 bmcr, bmsr, estat;
1686 val = nr64(MIF_CONFIG);
1687 val &= ~MIF_CONFIG_INDIRECT_MODE;
1688 nw64(MIF_CONFIG, val);
1690 err = mii_reset(np);
1694 err = mii_read(np, np->phy_addr, MII_BMSR);
1700 if (bmsr & BMSR_ESTATEN) {
1701 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1708 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1712 if (bmsr & BMSR_ESTATEN) {
1715 if (estat & ESTATUS_1000_TFULL)
1716 ctrl1000 |= ADVERTISE_1000FULL;
1717 err = mii_write(np, np->phy_addr, MII_CTRL1000, ctrl1000);
1722 bmcr = (BMCR_SPEED1000 | BMCR_FULLDPLX);
1724 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1728 err = mii_read(np, np->phy_addr, MII_BMCR);
1731 bmcr = mii_read(np, np->phy_addr, MII_BMCR);
1733 err = mii_read(np, np->phy_addr, MII_BMSR);
1740 static int mii_init_common(struct niu *np)
1742 struct niu_link_config *lp = &np->link_config;
1743 u16 bmcr, bmsr, adv, estat;
1746 err = mii_reset(np);
1750 err = mii_read(np, np->phy_addr, MII_BMSR);
1756 if (bmsr & BMSR_ESTATEN) {
1757 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1764 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1768 if (lp->loopback_mode == LOOPBACK_MAC) {
1769 bmcr |= BMCR_LOOPBACK;
1770 if (lp->active_speed == SPEED_1000)
1771 bmcr |= BMCR_SPEED1000;
1772 if (lp->active_duplex == DUPLEX_FULL)
1773 bmcr |= BMCR_FULLDPLX;
1776 if (lp->loopback_mode == LOOPBACK_PHY) {
1779 aux = (BCM5464R_AUX_CTL_EXT_LB |
1780 BCM5464R_AUX_CTL_WRITE_1);
1781 err = mii_write(np, np->phy_addr, BCM5464R_AUX_CTL, aux);
1789 adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1790 if ((bmsr & BMSR_10HALF) &&
1791 (lp->advertising & ADVERTISED_10baseT_Half))
1792 adv |= ADVERTISE_10HALF;
1793 if ((bmsr & BMSR_10FULL) &&
1794 (lp->advertising & ADVERTISED_10baseT_Full))
1795 adv |= ADVERTISE_10FULL;
1796 if ((bmsr & BMSR_100HALF) &&
1797 (lp->advertising & ADVERTISED_100baseT_Half))
1798 adv |= ADVERTISE_100HALF;
1799 if ((bmsr & BMSR_100FULL) &&
1800 (lp->advertising & ADVERTISED_100baseT_Full))
1801 adv |= ADVERTISE_100FULL;
1802 err = mii_write(np, np->phy_addr, MII_ADVERTISE, adv);
1806 if (likely(bmsr & BMSR_ESTATEN)) {
1808 if ((estat & ESTATUS_1000_THALF) &&
1809 (lp->advertising & ADVERTISED_1000baseT_Half))
1810 ctrl1000 |= ADVERTISE_1000HALF;
1811 if ((estat & ESTATUS_1000_TFULL) &&
1812 (lp->advertising & ADVERTISED_1000baseT_Full))
1813 ctrl1000 |= ADVERTISE_1000FULL;
1814 err = mii_write(np, np->phy_addr,
1815 MII_CTRL1000, ctrl1000);
1820 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1825 if (lp->duplex == DUPLEX_FULL) {
1826 bmcr |= BMCR_FULLDPLX;
1828 } else if (lp->duplex == DUPLEX_HALF)
1833 if (lp->speed == SPEED_1000) {
1834 /* if X-full requested while not supported, or
1835 X-half requested while not supported... */
1836 if ((fulldpx && !(estat & ESTATUS_1000_TFULL)) ||
1837 (!fulldpx && !(estat & ESTATUS_1000_THALF)))
1839 bmcr |= BMCR_SPEED1000;
1840 } else if (lp->speed == SPEED_100) {
1841 if ((fulldpx && !(bmsr & BMSR_100FULL)) ||
1842 (!fulldpx && !(bmsr & BMSR_100HALF)))
1844 bmcr |= BMCR_SPEED100;
1845 } else if (lp->speed == SPEED_10) {
1846 if ((fulldpx && !(bmsr & BMSR_10FULL)) ||
1847 (!fulldpx && !(bmsr & BMSR_10HALF)))
1853 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1858 err = mii_read(np, np->phy_addr, MII_BMCR);
1863 err = mii_read(np, np->phy_addr, MII_BMSR);
1868 pr_info("Port %u after MII init bmcr[%04x] bmsr[%04x]\n",
1869 np->port, bmcr, bmsr);
1875 static int xcvr_init_1g(struct niu *np)
1879 /* XXX shared resource, lock parent XXX */
1880 val = nr64(MIF_CONFIG);
1881 val &= ~MIF_CONFIG_INDIRECT_MODE;
1882 nw64(MIF_CONFIG, val);
1884 return mii_init_common(np);
1887 static int niu_xcvr_init(struct niu *np)
1889 const struct niu_phy_ops *ops = np->phy_ops;
1894 err = ops->xcvr_init(np);
1899 static int niu_serdes_init(struct niu *np)
1901 const struct niu_phy_ops *ops = np->phy_ops;
1905 if (ops->serdes_init)
1906 err = ops->serdes_init(np);
1911 static void niu_init_xif(struct niu *);
1912 static void niu_handle_led(struct niu *, int status);
1914 static int niu_link_status_common(struct niu *np, int link_up)
1916 struct niu_link_config *lp = &np->link_config;
1917 struct net_device *dev = np->dev;
1918 unsigned long flags;
1920 if (!netif_carrier_ok(dev) && link_up) {
1921 netif_info(np, link, dev, "Link is up at %s, %s duplex\n",
1922 lp->active_speed == SPEED_10000 ? "10Gb/sec" :
1923 lp->active_speed == SPEED_1000 ? "1Gb/sec" :
1924 lp->active_speed == SPEED_100 ? "100Mbit/sec" :
1926 lp->active_duplex == DUPLEX_FULL ? "full" : "half");
1928 spin_lock_irqsave(&np->lock, flags);
1930 niu_handle_led(np, 1);
1931 spin_unlock_irqrestore(&np->lock, flags);
1933 netif_carrier_on(dev);
1934 } else if (netif_carrier_ok(dev) && !link_up) {
1935 netif_warn(np, link, dev, "Link is down\n");
1936 spin_lock_irqsave(&np->lock, flags);
1937 niu_handle_led(np, 0);
1938 spin_unlock_irqrestore(&np->lock, flags);
1939 netif_carrier_off(dev);
1945 static int link_status_10g_mrvl(struct niu *np, int *link_up_p)
1947 int err, link_up, pma_status, pcs_status;
1951 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1952 MRVL88X2011_10G_PMD_STATUS_2);
1956 /* Check PMA/PMD Register: 1.0001.2 == 1 */
1957 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1958 MRVL88X2011_PMA_PMD_STATUS_1);
1962 pma_status = ((err & MRVL88X2011_LNK_STATUS_OK) ? 1 : 0);
1964 /* Check PMC Register : 3.0001.2 == 1: read twice */
1965 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1966 MRVL88X2011_PMA_PMD_STATUS_1);
1970 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1971 MRVL88X2011_PMA_PMD_STATUS_1);
1975 pcs_status = ((err & MRVL88X2011_LNK_STATUS_OK) ? 1 : 0);
1977 /* Check XGXS Register : 4.0018.[0-3,12] */
1978 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV4_ADDR,
1979 MRVL88X2011_10G_XGXS_LANE_STAT);
1983 if (err == (PHYXS_XGXS_LANE_STAT_ALINGED | PHYXS_XGXS_LANE_STAT_LANE3 |
1984 PHYXS_XGXS_LANE_STAT_LANE2 | PHYXS_XGXS_LANE_STAT_LANE1 |
1985 PHYXS_XGXS_LANE_STAT_LANE0 | PHYXS_XGXS_LANE_STAT_MAGIC |
1987 link_up = (pma_status && pcs_status) ? 1 : 0;
1989 np->link_config.active_speed = SPEED_10000;
1990 np->link_config.active_duplex = DUPLEX_FULL;
1993 mrvl88x2011_act_led(np, (link_up ?
1994 MRVL88X2011_LED_CTL_PCS_ACT :
1995 MRVL88X2011_LED_CTL_OFF));
1997 *link_up_p = link_up;
2001 static int link_status_10g_bcm8706(struct niu *np, int *link_up_p)
2006 err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
2007 BCM8704_PMD_RCV_SIGDET);
2008 if (err < 0 || err == 0xffff)
2010 if (!(err & PMD_RCV_SIGDET_GLOBAL)) {
2015 err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
2016 BCM8704_PCS_10G_R_STATUS);
2020 if (!(err & PCS_10G_R_STATUS_BLK_LOCK)) {
2025 err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
2026 BCM8704_PHYXS_XGXS_LANE_STAT);
2029 if (err != (PHYXS_XGXS_LANE_STAT_ALINGED |
2030 PHYXS_XGXS_LANE_STAT_MAGIC |
2031 PHYXS_XGXS_LANE_STAT_PATTEST |
2032 PHYXS_XGXS_LANE_STAT_LANE3 |
2033 PHYXS_XGXS_LANE_STAT_LANE2 |
2034 PHYXS_XGXS_LANE_STAT_LANE1 |
2035 PHYXS_XGXS_LANE_STAT_LANE0)) {
2037 np->link_config.active_speed = SPEED_INVALID;
2038 np->link_config.active_duplex = DUPLEX_INVALID;
2043 np->link_config.active_speed = SPEED_10000;
2044 np->link_config.active_duplex = DUPLEX_FULL;
2048 *link_up_p = link_up;
2052 static int link_status_10g_bcom(struct niu *np, int *link_up_p)
2058 err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
2059 BCM8704_PMD_RCV_SIGDET);
2062 if (!(err & PMD_RCV_SIGDET_GLOBAL)) {
2067 err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
2068 BCM8704_PCS_10G_R_STATUS);
2071 if (!(err & PCS_10G_R_STATUS_BLK_LOCK)) {
2076 err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
2077 BCM8704_PHYXS_XGXS_LANE_STAT);
2081 if (err != (PHYXS_XGXS_LANE_STAT_ALINGED |
2082 PHYXS_XGXS_LANE_STAT_MAGIC |
2083 PHYXS_XGXS_LANE_STAT_LANE3 |
2084 PHYXS_XGXS_LANE_STAT_LANE2 |
2085 PHYXS_XGXS_LANE_STAT_LANE1 |
2086 PHYXS_XGXS_LANE_STAT_LANE0)) {
2092 np->link_config.active_speed = SPEED_10000;
2093 np->link_config.active_duplex = DUPLEX_FULL;
2097 *link_up_p = link_up;
2101 static int link_status_10g(struct niu *np, int *link_up_p)
2103 unsigned long flags;
2106 spin_lock_irqsave(&np->lock, flags);
2108 if (np->link_config.loopback_mode == LOOPBACK_DISABLED) {
2111 phy_id = phy_decode(np->parent->port_phy, np->port);
2112 phy_id = np->parent->phy_probe_info.phy_id[phy_id][np->port];
2114 /* handle different phy types */
2115 switch (phy_id & NIU_PHY_ID_MASK) {
2116 case NIU_PHY_ID_MRVL88X2011:
2117 err = link_status_10g_mrvl(np, link_up_p);
2120 default: /* bcom 8704 */
2121 err = link_status_10g_bcom(np, link_up_p);
2126 spin_unlock_irqrestore(&np->lock, flags);
2131 static int niu_10g_phy_present(struct niu *np)
2135 sig = nr64(ESR_INT_SIGNALS);
2138 mask = ESR_INT_SIGNALS_P0_BITS;
2139 val = (ESR_INT_SRDY0_P0 |
2142 ESR_INT_XDP_P0_CH3 |
2143 ESR_INT_XDP_P0_CH2 |
2144 ESR_INT_XDP_P0_CH1 |
2145 ESR_INT_XDP_P0_CH0);
2149 mask = ESR_INT_SIGNALS_P1_BITS;
2150 val = (ESR_INT_SRDY0_P1 |
2153 ESR_INT_XDP_P1_CH3 |
2154 ESR_INT_XDP_P1_CH2 |
2155 ESR_INT_XDP_P1_CH1 |
2156 ESR_INT_XDP_P1_CH0);
2163 if ((sig & mask) != val)
2168 static int link_status_10g_hotplug(struct niu *np, int *link_up_p)
2170 unsigned long flags;
2173 int phy_present_prev;
2175 spin_lock_irqsave(&np->lock, flags);
2177 if (np->link_config.loopback_mode == LOOPBACK_DISABLED) {
2178 phy_present_prev = (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) ?
2180 phy_present = niu_10g_phy_present(np);
2181 if (phy_present != phy_present_prev) {
2184 /* A NEM was just plugged in */
2185 np->flags |= NIU_FLAGS_HOTPLUG_PHY_PRESENT;
2186 if (np->phy_ops->xcvr_init)
2187 err = np->phy_ops->xcvr_init(np);
2189 err = mdio_read(np, np->phy_addr,
2190 BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
2191 if (err == 0xffff) {
2192 /* No mdio, back-to-back XAUI */
2196 np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
2199 np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
2201 netif_warn(np, link, np->dev,
2202 "Hotplug PHY Removed\n");
2206 if (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) {
2207 err = link_status_10g_bcm8706(np, link_up_p);
2208 if (err == 0xffff) {
2209 /* No mdio, back-to-back XAUI: it is C10NEM */
2211 np->link_config.active_speed = SPEED_10000;
2212 np->link_config.active_duplex = DUPLEX_FULL;
2217 spin_unlock_irqrestore(&np->lock, flags);
2222 static int niu_link_status(struct niu *np, int *link_up_p)
2224 const struct niu_phy_ops *ops = np->phy_ops;
2228 if (ops->link_status)
2229 err = ops->link_status(np, link_up_p);
2234 static void niu_timer(unsigned long __opaque)
2236 struct niu *np = (struct niu *) __opaque;
2240 err = niu_link_status(np, &link_up);
2242 niu_link_status_common(np, link_up);
2244 if (netif_carrier_ok(np->dev))
2248 np->timer.expires = jiffies + off;
2250 add_timer(&np->timer);
2253 static const struct niu_phy_ops phy_ops_10g_serdes = {
2254 .serdes_init = serdes_init_10g_serdes,
2255 .link_status = link_status_10g_serdes,
2258 static const struct niu_phy_ops phy_ops_10g_serdes_niu = {
2259 .serdes_init = serdes_init_niu_10g_serdes,
2260 .link_status = link_status_10g_serdes,
2263 static const struct niu_phy_ops phy_ops_1g_serdes_niu = {
2264 .serdes_init = serdes_init_niu_1g_serdes,
2265 .link_status = link_status_1g_serdes,
2268 static const struct niu_phy_ops phy_ops_1g_rgmii = {
2269 .xcvr_init = xcvr_init_1g_rgmii,
2270 .link_status = link_status_1g_rgmii,
2273 static const struct niu_phy_ops phy_ops_10g_fiber_niu = {
2274 .serdes_init = serdes_init_niu_10g_fiber,
2275 .xcvr_init = xcvr_init_10g,
2276 .link_status = link_status_10g,
2279 static const struct niu_phy_ops phy_ops_10g_fiber = {
2280 .serdes_init = serdes_init_10g,
2281 .xcvr_init = xcvr_init_10g,
2282 .link_status = link_status_10g,
2285 static const struct niu_phy_ops phy_ops_10g_fiber_hotplug = {
2286 .serdes_init = serdes_init_10g,
2287 .xcvr_init = xcvr_init_10g_bcm8706,
2288 .link_status = link_status_10g_hotplug,
2291 static const struct niu_phy_ops phy_ops_niu_10g_hotplug = {
2292 .serdes_init = serdes_init_niu_10g_fiber,
2293 .xcvr_init = xcvr_init_10g_bcm8706,
2294 .link_status = link_status_10g_hotplug,
2297 static const struct niu_phy_ops phy_ops_10g_copper = {
2298 .serdes_init = serdes_init_10g,
2299 .link_status = link_status_10g, /* XXX */
2302 static const struct niu_phy_ops phy_ops_1g_fiber = {
2303 .serdes_init = serdes_init_1g,
2304 .xcvr_init = xcvr_init_1g,
2305 .link_status = link_status_1g,
2308 static const struct niu_phy_ops phy_ops_1g_copper = {
2309 .xcvr_init = xcvr_init_1g,
2310 .link_status = link_status_1g,
2313 struct niu_phy_template {
2314 const struct niu_phy_ops *ops;
2318 static const struct niu_phy_template phy_template_niu_10g_fiber = {
2319 .ops = &phy_ops_10g_fiber_niu,
2320 .phy_addr_base = 16,
2323 static const struct niu_phy_template phy_template_niu_10g_serdes = {
2324 .ops = &phy_ops_10g_serdes_niu,
2328 static const struct niu_phy_template phy_template_niu_1g_serdes = {
2329 .ops = &phy_ops_1g_serdes_niu,
2333 static const struct niu_phy_template phy_template_10g_fiber = {
2334 .ops = &phy_ops_10g_fiber,
2338 static const struct niu_phy_template phy_template_10g_fiber_hotplug = {
2339 .ops = &phy_ops_10g_fiber_hotplug,
2343 static const struct niu_phy_template phy_template_niu_10g_hotplug = {
2344 .ops = &phy_ops_niu_10g_hotplug,
2348 static const struct niu_phy_template phy_template_10g_copper = {
2349 .ops = &phy_ops_10g_copper,
2350 .phy_addr_base = 10,
2353 static const struct niu_phy_template phy_template_1g_fiber = {
2354 .ops = &phy_ops_1g_fiber,
2358 static const struct niu_phy_template phy_template_1g_copper = {
2359 .ops = &phy_ops_1g_copper,
2363 static const struct niu_phy_template phy_template_1g_rgmii = {
2364 .ops = &phy_ops_1g_rgmii,
2368 static const struct niu_phy_template phy_template_10g_serdes = {
2369 .ops = &phy_ops_10g_serdes,
2373 static int niu_atca_port_num[4] = {
2377 static int serdes_init_10g_serdes(struct niu *np)
2379 struct niu_link_config *lp = &np->link_config;
2380 unsigned long ctrl_reg, test_cfg_reg, pll_cfg, i;
2381 u64 ctrl_val, test_cfg_val, sig, mask, val;
2385 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
2386 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
2387 pll_cfg = ENET_SERDES_0_PLL_CFG;
2390 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
2391 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
2392 pll_cfg = ENET_SERDES_1_PLL_CFG;
2398 ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
2399 ENET_SERDES_CTRL_SDET_1 |
2400 ENET_SERDES_CTRL_SDET_2 |
2401 ENET_SERDES_CTRL_SDET_3 |
2402 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
2403 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
2404 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
2405 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
2406 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
2407 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
2408 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
2409 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
2412 if (lp->loopback_mode == LOOPBACK_PHY) {
2413 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
2414 ENET_SERDES_TEST_MD_0_SHIFT) |
2415 (ENET_TEST_MD_PAD_LOOPBACK <<
2416 ENET_SERDES_TEST_MD_1_SHIFT) |
2417 (ENET_TEST_MD_PAD_LOOPBACK <<
2418 ENET_SERDES_TEST_MD_2_SHIFT) |
2419 (ENET_TEST_MD_PAD_LOOPBACK <<
2420 ENET_SERDES_TEST_MD_3_SHIFT));
2424 nw64(pll_cfg, ENET_SERDES_PLL_FBDIV2);
2425 nw64(ctrl_reg, ctrl_val);
2426 nw64(test_cfg_reg, test_cfg_val);
2428 /* Initialize all 4 lanes of the SERDES. */
2429 for (i = 0; i < 4; i++) {
2430 u32 rxtx_ctrl, glue0;
2433 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
2436 err = esr_read_glue0(np, i, &glue0);
2440 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
2441 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
2442 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
2444 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
2445 ESR_GLUE_CTRL0_THCNT |
2446 ESR_GLUE_CTRL0_BLTIME);
2447 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
2448 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
2449 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
2450 (BLTIME_300_CYCLES <<
2451 ESR_GLUE_CTRL0_BLTIME_SHIFT));
2453 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
2456 err = esr_write_glue0(np, i, glue0);
2462 sig = nr64(ESR_INT_SIGNALS);
2465 mask = ESR_INT_SIGNALS_P0_BITS;
2466 val = (ESR_INT_SRDY0_P0 |
2469 ESR_INT_XDP_P0_CH3 |
2470 ESR_INT_XDP_P0_CH2 |
2471 ESR_INT_XDP_P0_CH1 |
2472 ESR_INT_XDP_P0_CH0);
2476 mask = ESR_INT_SIGNALS_P1_BITS;
2477 val = (ESR_INT_SRDY0_P1 |
2480 ESR_INT_XDP_P1_CH3 |
2481 ESR_INT_XDP_P1_CH2 |
2482 ESR_INT_XDP_P1_CH1 |
2483 ESR_INT_XDP_P1_CH0);
2490 if ((sig & mask) != val) {
2492 err = serdes_init_1g_serdes(np);
2494 np->flags &= ~NIU_FLAGS_10G;
2495 np->mac_xcvr = MAC_XCVR_PCS;
2497 netdev_err(np->dev, "Port %u 10G/1G SERDES Link Failed\n",
2506 static int niu_determine_phy_disposition(struct niu *np)
2508 struct niu_parent *parent = np->parent;
2509 u8 plat_type = parent->plat_type;
2510 const struct niu_phy_template *tp;
2511 u32 phy_addr_off = 0;
2513 if (plat_type == PLAT_TYPE_NIU) {
2517 NIU_FLAGS_XCVR_SERDES)) {
2518 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
2520 tp = &phy_template_niu_10g_serdes;
2522 case NIU_FLAGS_XCVR_SERDES:
2524 tp = &phy_template_niu_1g_serdes;
2526 case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
2529 if (np->flags & NIU_FLAGS_HOTPLUG_PHY) {
2530 tp = &phy_template_niu_10g_hotplug;
2536 tp = &phy_template_niu_10g_fiber;
2537 phy_addr_off += np->port;
2545 NIU_FLAGS_XCVR_SERDES)) {
2548 tp = &phy_template_1g_copper;
2549 if (plat_type == PLAT_TYPE_VF_P0)
2551 else if (plat_type == PLAT_TYPE_VF_P1)
2554 phy_addr_off += (np->port ^ 0x3);
2559 tp = &phy_template_10g_copper;
2562 case NIU_FLAGS_FIBER:
2564 tp = &phy_template_1g_fiber;
2567 case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
2569 tp = &phy_template_10g_fiber;
2570 if (plat_type == PLAT_TYPE_VF_P0 ||
2571 plat_type == PLAT_TYPE_VF_P1)
2573 phy_addr_off += np->port;
2574 if (np->flags & NIU_FLAGS_HOTPLUG_PHY) {
2575 tp = &phy_template_10g_fiber_hotplug;
2583 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
2584 case NIU_FLAGS_XCVR_SERDES | NIU_FLAGS_FIBER:
2585 case NIU_FLAGS_XCVR_SERDES:
2589 tp = &phy_template_10g_serdes;
2593 tp = &phy_template_1g_rgmii;
2599 phy_addr_off = niu_atca_port_num[np->port];
2607 np->phy_ops = tp->ops;
2608 np->phy_addr = tp->phy_addr_base + phy_addr_off;
2613 static int niu_init_link(struct niu *np)
2615 struct niu_parent *parent = np->parent;
2618 if (parent->plat_type == PLAT_TYPE_NIU) {
2619 err = niu_xcvr_init(np);
2624 err = niu_serdes_init(np);
2625 if (err && !(np->flags & NIU_FLAGS_HOTPLUG_PHY))
2628 err = niu_xcvr_init(np);
2629 if (!err || (np->flags & NIU_FLAGS_HOTPLUG_PHY))
2630 niu_link_status(np, &ignore);
2634 static void niu_set_primary_mac(struct niu *np, unsigned char *addr)
2636 u16 reg0 = addr[4] << 8 | addr[5];
2637 u16 reg1 = addr[2] << 8 | addr[3];
2638 u16 reg2 = addr[0] << 8 | addr[1];
2640 if (np->flags & NIU_FLAGS_XMAC) {
2641 nw64_mac(XMAC_ADDR0, reg0);
2642 nw64_mac(XMAC_ADDR1, reg1);
2643 nw64_mac(XMAC_ADDR2, reg2);
2645 nw64_mac(BMAC_ADDR0, reg0);
2646 nw64_mac(BMAC_ADDR1, reg1);
2647 nw64_mac(BMAC_ADDR2, reg2);
2651 static int niu_num_alt_addr(struct niu *np)
2653 if (np->flags & NIU_FLAGS_XMAC)
2654 return XMAC_NUM_ALT_ADDR;
2656 return BMAC_NUM_ALT_ADDR;
2659 static int niu_set_alt_mac(struct niu *np, int index, unsigned char *addr)
2661 u16 reg0 = addr[4] << 8 | addr[5];
2662 u16 reg1 = addr[2] << 8 | addr[3];
2663 u16 reg2 = addr[0] << 8 | addr[1];
2665 if (index >= niu_num_alt_addr(np))
2668 if (np->flags & NIU_FLAGS_XMAC) {
2669 nw64_mac(XMAC_ALT_ADDR0(index), reg0);
2670 nw64_mac(XMAC_ALT_ADDR1(index), reg1);
2671 nw64_mac(XMAC_ALT_ADDR2(index), reg2);
2673 nw64_mac(BMAC_ALT_ADDR0(index), reg0);
2674 nw64_mac(BMAC_ALT_ADDR1(index), reg1);
2675 nw64_mac(BMAC_ALT_ADDR2(index), reg2);
2681 static int niu_enable_alt_mac(struct niu *np, int index, int on)
2686 if (index >= niu_num_alt_addr(np))
2689 if (np->flags & NIU_FLAGS_XMAC) {
2690 reg = XMAC_ADDR_CMPEN;
2693 reg = BMAC_ADDR_CMPEN;
2694 mask = 1 << (index + 1);
2697 val = nr64_mac(reg);
2707 static void __set_rdc_table_num_hw(struct niu *np, unsigned long reg,
2708 int num, int mac_pref)
2710 u64 val = nr64_mac(reg);
2711 val &= ~(HOST_INFO_MACRDCTBLN | HOST_INFO_MPR);
2714 val |= HOST_INFO_MPR;
2718 static int __set_rdc_table_num(struct niu *np,
2719 int xmac_index, int bmac_index,
2720 int rdc_table_num, int mac_pref)
2724 if (rdc_table_num & ~HOST_INFO_MACRDCTBLN)
2726 if (np->flags & NIU_FLAGS_XMAC)
2727 reg = XMAC_HOST_INFO(xmac_index);
2729 reg = BMAC_HOST_INFO(bmac_index);
2730 __set_rdc_table_num_hw(np, reg, rdc_table_num, mac_pref);
2734 static int niu_set_primary_mac_rdc_table(struct niu *np, int table_num,
2737 return __set_rdc_table_num(np, 17, 0, table_num, mac_pref);
2740 static int niu_set_multicast_mac_rdc_table(struct niu *np, int table_num,
2743 return __set_rdc_table_num(np, 16, 8, table_num, mac_pref);
2746 static int niu_set_alt_mac_rdc_table(struct niu *np, int idx,
2747 int table_num, int mac_pref)
2749 if (idx >= niu_num_alt_addr(np))
2751 return __set_rdc_table_num(np, idx, idx + 1, table_num, mac_pref);
2754 static u64 vlan_entry_set_parity(u64 reg_val)
2759 port01_mask = 0x00ff;
2760 port23_mask = 0xff00;
2762 if (hweight64(reg_val & port01_mask) & 1)
2763 reg_val |= ENET_VLAN_TBL_PARITY0;
2765 reg_val &= ~ENET_VLAN_TBL_PARITY0;
2767 if (hweight64(reg_val & port23_mask) & 1)
2768 reg_val |= ENET_VLAN_TBL_PARITY1;
2770 reg_val &= ~ENET_VLAN_TBL_PARITY1;
2775 static void vlan_tbl_write(struct niu *np, unsigned long index,
2776 int port, int vpr, int rdc_table)
2778 u64 reg_val = nr64(ENET_VLAN_TBL(index));
2780 reg_val &= ~((ENET_VLAN_TBL_VPR |
2781 ENET_VLAN_TBL_VLANRDCTBLN) <<
2782 ENET_VLAN_TBL_SHIFT(port));
2784 reg_val |= (ENET_VLAN_TBL_VPR <<
2785 ENET_VLAN_TBL_SHIFT(port));
2786 reg_val |= (rdc_table << ENET_VLAN_TBL_SHIFT(port));
2788 reg_val = vlan_entry_set_parity(reg_val);
2790 nw64(ENET_VLAN_TBL(index), reg_val);
2793 static void vlan_tbl_clear(struct niu *np)
2797 for (i = 0; i < ENET_VLAN_TBL_NUM_ENTRIES; i++)
2798 nw64(ENET_VLAN_TBL(i), 0);
2801 static int tcam_wait_bit(struct niu *np, u64 bit)
2805 while (--limit > 0) {
2806 if (nr64(TCAM_CTL) & bit)
2816 static int tcam_flush(struct niu *np, int index)
2818 nw64(TCAM_KEY_0, 0x00);
2819 nw64(TCAM_KEY_MASK_0, 0xff);
2820 nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index));
2822 return tcam_wait_bit(np, TCAM_CTL_STAT);
2826 static int tcam_read(struct niu *np, int index,
2827 u64 *key, u64 *mask)
2831 nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_READ | index));
2832 err = tcam_wait_bit(np, TCAM_CTL_STAT);
2834 key[0] = nr64(TCAM_KEY_0);
2835 key[1] = nr64(TCAM_KEY_1);
2836 key[2] = nr64(TCAM_KEY_2);
2837 key[3] = nr64(TCAM_KEY_3);
2838 mask[0] = nr64(TCAM_KEY_MASK_0);
2839 mask[1] = nr64(TCAM_KEY_MASK_1);
2840 mask[2] = nr64(TCAM_KEY_MASK_2);
2841 mask[3] = nr64(TCAM_KEY_MASK_3);
2847 static int tcam_write(struct niu *np, int index,
2848 u64 *key, u64 *mask)
2850 nw64(TCAM_KEY_0, key[0]);
2851 nw64(TCAM_KEY_1, key[1]);
2852 nw64(TCAM_KEY_2, key[2]);
2853 nw64(TCAM_KEY_3, key[3]);
2854 nw64(TCAM_KEY_MASK_0, mask[0]);
2855 nw64(TCAM_KEY_MASK_1, mask[1]);
2856 nw64(TCAM_KEY_MASK_2, mask[2]);
2857 nw64(TCAM_KEY_MASK_3, mask[3]);
2858 nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index));
2860 return tcam_wait_bit(np, TCAM_CTL_STAT);
2864 static int tcam_assoc_read(struct niu *np, int index, u64 *data)
2868 nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_READ | index));
2869 err = tcam_wait_bit(np, TCAM_CTL_STAT);
2871 *data = nr64(TCAM_KEY_1);
2877 static int tcam_assoc_write(struct niu *np, int index, u64 assoc_data)
2879 nw64(TCAM_KEY_1, assoc_data);
2880 nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_WRITE | index));
2882 return tcam_wait_bit(np, TCAM_CTL_STAT);
2885 static void tcam_enable(struct niu *np, int on)
2887 u64 val = nr64(FFLP_CFG_1);
2890 val &= ~FFLP_CFG_1_TCAM_DIS;
2892 val |= FFLP_CFG_1_TCAM_DIS;
2893 nw64(FFLP_CFG_1, val);
2896 static void tcam_set_lat_and_ratio(struct niu *np, u64 latency, u64 ratio)
2898 u64 val = nr64(FFLP_CFG_1);
2900 val &= ~(FFLP_CFG_1_FFLPINITDONE |
2902 FFLP_CFG_1_CAMRATIO);
2903 val |= (latency << FFLP_CFG_1_CAMLAT_SHIFT);
2904 val |= (ratio << FFLP_CFG_1_CAMRATIO_SHIFT);
2905 nw64(FFLP_CFG_1, val);
2907 val = nr64(FFLP_CFG_1);
2908 val |= FFLP_CFG_1_FFLPINITDONE;
2909 nw64(FFLP_CFG_1, val);
2912 static int tcam_user_eth_class_enable(struct niu *np, unsigned long class,
2918 if (class < CLASS_CODE_ETHERTYPE1 ||
2919 class > CLASS_CODE_ETHERTYPE2)
2922 reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1);
2934 static int tcam_user_eth_class_set(struct niu *np, unsigned long class,
2940 if (class < CLASS_CODE_ETHERTYPE1 ||
2941 class > CLASS_CODE_ETHERTYPE2 ||
2942 (ether_type & ~(u64)0xffff) != 0)
2945 reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1);
2947 val &= ~L2_CLS_ETYPE;
2948 val |= (ether_type << L2_CLS_ETYPE_SHIFT);
2955 static int tcam_user_ip_class_enable(struct niu *np, unsigned long class,
2961 if (class < CLASS_CODE_USER_PROG1 ||
2962 class > CLASS_CODE_USER_PROG4)
2965 reg = L3_CLS(class - CLASS_CODE_USER_PROG1);
2968 val |= L3_CLS_VALID;
2970 val &= ~L3_CLS_VALID;
2976 static int tcam_user_ip_class_set(struct niu *np, unsigned long class,
2977 int ipv6, u64 protocol_id,
2978 u64 tos_mask, u64 tos_val)
2983 if (class < CLASS_CODE_USER_PROG1 ||
2984 class > CLASS_CODE_USER_PROG4 ||
2985 (protocol_id & ~(u64)0xff) != 0 ||
2986 (tos_mask & ~(u64)0xff) != 0 ||
2987 (tos_val & ~(u64)0xff) != 0)
2990 reg = L3_CLS(class - CLASS_CODE_USER_PROG1);
2992 val &= ~(L3_CLS_IPVER | L3_CLS_PID |
2993 L3_CLS_TOSMASK | L3_CLS_TOS);
2995 val |= L3_CLS_IPVER;
2996 val |= (protocol_id << L3_CLS_PID_SHIFT);
2997 val |= (tos_mask << L3_CLS_TOSMASK_SHIFT);
2998 val |= (tos_val << L3_CLS_TOS_SHIFT);
3004 static int tcam_early_init(struct niu *np)
3010 tcam_set_lat_and_ratio(np,
3011 DEFAULT_TCAM_LATENCY,
3012 DEFAULT_TCAM_ACCESS_RATIO);
3013 for (i = CLASS_CODE_ETHERTYPE1; i <= CLASS_CODE_ETHERTYPE2; i++) {
3014 err = tcam_user_eth_class_enable(np, i, 0);
3018 for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_USER_PROG4; i++) {
3019 err = tcam_user_ip_class_enable(np, i, 0);
3027 static int tcam_flush_all(struct niu *np)
3031 for (i = 0; i < np->parent->tcam_num_entries; i++) {
3032 int err = tcam_flush(np, i);
3039 static u64 hash_addr_regval(unsigned long index, unsigned long num_entries)
3041 return (u64)index | (num_entries == 1 ? HASH_TBL_ADDR_AUTOINC : 0);
3045 static int hash_read(struct niu *np, unsigned long partition,
3046 unsigned long index, unsigned long num_entries,
3049 u64 val = hash_addr_regval(index, num_entries);
3052 if (partition >= FCRAM_NUM_PARTITIONS ||
3053 index + num_entries > FCRAM_SIZE)
3056 nw64(HASH_TBL_ADDR(partition), val);
3057 for (i = 0; i < num_entries; i++)
3058 data[i] = nr64(HASH_TBL_DATA(partition));
3064 static int hash_write(struct niu *np, unsigned long partition,
3065 unsigned long index, unsigned long num_entries,
3068 u64 val = hash_addr_regval(index, num_entries);
3071 if (partition >= FCRAM_NUM_PARTITIONS ||
3072 index + (num_entries * 8) > FCRAM_SIZE)
3075 nw64(HASH_TBL_ADDR(partition), val);
3076 for (i = 0; i < num_entries; i++)
3077 nw64(HASH_TBL_DATA(partition), data[i]);
3082 static void fflp_reset(struct niu *np)
3086 nw64(FFLP_CFG_1, FFLP_CFG_1_PIO_FIO_RST);
3088 nw64(FFLP_CFG_1, 0);
3090 val = FFLP_CFG_1_FCRAMOUTDR_NORMAL | FFLP_CFG_1_FFLPINITDONE;
3091 nw64(FFLP_CFG_1, val);
3094 static void fflp_set_timings(struct niu *np)
3096 u64 val = nr64(FFLP_CFG_1);
3098 val &= ~FFLP_CFG_1_FFLPINITDONE;
3099 val |= (DEFAULT_FCRAMRATIO << FFLP_CFG_1_FCRAMRATIO_SHIFT);
3100 nw64(FFLP_CFG_1, val);
3102 val = nr64(FFLP_CFG_1);
3103 val |= FFLP_CFG_1_FFLPINITDONE;
3104 nw64(FFLP_CFG_1, val);
3106 val = nr64(FCRAM_REF_TMR);
3107 val &= ~(FCRAM_REF_TMR_MAX | FCRAM_REF_TMR_MIN);
3108 val |= (DEFAULT_FCRAM_REFRESH_MAX << FCRAM_REF_TMR_MAX_SHIFT);
3109 val |= (DEFAULT_FCRAM_REFRESH_MIN << FCRAM_REF_TMR_MIN_SHIFT);
3110 nw64(FCRAM_REF_TMR, val);
3113 static int fflp_set_partition(struct niu *np, u64 partition,
3114 u64 mask, u64 base, int enable)
3119 if (partition >= FCRAM_NUM_PARTITIONS ||
3120 (mask & ~(u64)0x1f) != 0 ||
3121 (base & ~(u64)0x1f) != 0)
3124 reg = FLW_PRT_SEL(partition);
3127 val &= ~(FLW_PRT_SEL_EXT | FLW_PRT_SEL_MASK | FLW_PRT_SEL_BASE);
3128 val |= (mask << FLW_PRT_SEL_MASK_SHIFT);
3129 val |= (base << FLW_PRT_SEL_BASE_SHIFT);
3131 val |= FLW_PRT_SEL_EXT;
3137 static int fflp_disable_all_partitions(struct niu *np)
3141 for (i = 0; i < FCRAM_NUM_PARTITIONS; i++) {
3142 int err = fflp_set_partition(np, 0, 0, 0, 0);
3149 static void fflp_llcsnap_enable(struct niu *np, int on)
3151 u64 val = nr64(FFLP_CFG_1);
3154 val |= FFLP_CFG_1_LLCSNAP;
3156 val &= ~FFLP_CFG_1_LLCSNAP;
3157 nw64(FFLP_CFG_1, val);
3160 static void fflp_errors_enable(struct niu *np, int on)
3162 u64 val = nr64(FFLP_CFG_1);
3165 val &= ~FFLP_CFG_1_ERRORDIS;
3167 val |= FFLP_CFG_1_ERRORDIS;
3168 nw64(FFLP_CFG_1, val);
3171 static int fflp_hash_clear(struct niu *np)
3173 struct fcram_hash_ipv4 ent;
3176 /* IPV4 hash entry with valid bit clear, rest is don't care. */
3177 memset(&ent, 0, sizeof(ent));
3178 ent.header = HASH_HEADER_EXT;
3180 for (i = 0; i < FCRAM_SIZE; i += sizeof(ent)) {
3181 int err = hash_write(np, 0, i, 1, (u64 *) &ent);
3188 static int fflp_early_init(struct niu *np)
3190 struct niu_parent *parent;
3191 unsigned long flags;
3194 niu_lock_parent(np, flags);
3196 parent = np->parent;
3198 if (!(parent->flags & PARENT_FLGS_CLS_HWINIT)) {
3199 if (np->parent->plat_type != PLAT_TYPE_NIU) {
3201 fflp_set_timings(np);
3202 err = fflp_disable_all_partitions(np);
3204 netif_printk(np, probe, KERN_DEBUG, np->dev,
3205 "fflp_disable_all_partitions failed, err=%d\n",
3211 err = tcam_early_init(np);
3213 netif_printk(np, probe, KERN_DEBUG, np->dev,
3214 "tcam_early_init failed, err=%d\n", err);
3217 fflp_llcsnap_enable(np, 1);
3218 fflp_errors_enable(np, 0);
3222 err = tcam_flush_all(np);
3224 netif_printk(np, probe, KERN_DEBUG, np->dev,
3225 "tcam_flush_all failed, err=%d\n", err);
3228 if (np->parent->plat_type != PLAT_TYPE_NIU) {
3229 err = fflp_hash_clear(np);
3231 netif_printk(np, probe, KERN_DEBUG, np->dev,
3232 "fflp_hash_clear failed, err=%d\n",
3240 parent->flags |= PARENT_FLGS_CLS_HWINIT;
3243 niu_unlock_parent(np, flags);
3247 static int niu_set_flow_key(struct niu *np, unsigned long class_code, u64 key)
3249 if (class_code < CLASS_CODE_USER_PROG1 ||
3250 class_code > CLASS_CODE_SCTP_IPV6)
3253 nw64(FLOW_KEY(class_code - CLASS_CODE_USER_PROG1), key);
3257 static int niu_set_tcam_key(struct niu *np, unsigned long class_code, u64 key)
3259 if (class_code < CLASS_CODE_USER_PROG1 ||
3260 class_code > CLASS_CODE_SCTP_IPV6)
3263 nw64(TCAM_KEY(class_code - CLASS_CODE_USER_PROG1), key);
3267 /* Entries for the ports are interleaved in the TCAM */
3268 static u16 tcam_get_index(struct niu *np, u16 idx)
3270 /* One entry reserved for IP fragment rule */
3271 if (idx >= (np->clas.tcam_sz - 1))
3273 return np->clas.tcam_top + ((idx+1) * np->parent->num_ports);
3276 static u16 tcam_get_size(struct niu *np)
3278 /* One entry reserved for IP fragment rule */
3279 return np->clas.tcam_sz - 1;
3282 static u16 tcam_get_valid_entry_cnt(struct niu *np)
3284 /* One entry reserved for IP fragment rule */
3285 return np->clas.tcam_valid_entries - 1;
3288 static void niu_rx_skb_append(struct sk_buff *skb, struct page *page,
3289 u32 offset, u32 size)
3291 int i = skb_shinfo(skb)->nr_frags;
3292 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3295 frag->page_offset = offset;
3299 skb->data_len += size;
3300 skb->truesize += size;
3302 skb_shinfo(skb)->nr_frags = i + 1;
3305 static unsigned int niu_hash_rxaddr(struct rx_ring_info *rp, u64 a)
3308 a ^= (a >> ilog2(MAX_RBR_RING_SIZE));
3310 return a & (MAX_RBR_RING_SIZE - 1);
3313 static struct page *niu_find_rxpage(struct rx_ring_info *rp, u64 addr,
3314 struct page ***link)
3316 unsigned int h = niu_hash_rxaddr(rp, addr);
3317 struct page *p, **pp;
3320 pp = &rp->rxhash[h];
3321 for (; (p = *pp) != NULL; pp = (struct page **) &p->mapping) {
3322 if (p->index == addr) {
3333 static void niu_hash_page(struct rx_ring_info *rp, struct page *page, u64 base)
3335 unsigned int h = niu_hash_rxaddr(rp, base);
3338 page->mapping = (struct address_space *) rp->rxhash[h];
3339 rp->rxhash[h] = page;
3342 static int niu_rbr_add_page(struct niu *np, struct rx_ring_info *rp,
3343 gfp_t mask, int start_index)
3349 page = alloc_page(mask);
3353 addr = np->ops->map_page(np->device, page, 0,
3354 PAGE_SIZE, DMA_FROM_DEVICE);
3356 niu_hash_page(rp, page, addr);
3357 if (rp->rbr_blocks_per_page > 1)
3358 atomic_add(rp->rbr_blocks_per_page - 1,
3359 &compound_head(page)->_count);
3361 for (i = 0; i < rp->rbr_blocks_per_page; i++) {
3362 __le32 *rbr = &rp->rbr[start_index + i];
3364 *rbr = cpu_to_le32(addr >> RBR_DESCR_ADDR_SHIFT);
3365 addr += rp->rbr_block_size;
3371 static void niu_rbr_refill(struct niu *np, struct rx_ring_info *rp, gfp_t mask)
3373 int index = rp->rbr_index;
3376 if ((rp->rbr_pending % rp->rbr_blocks_per_page) == 0) {
3377 int err = niu_rbr_add_page(np, rp, mask, index);
3379 if (unlikely(err)) {
3384 rp->rbr_index += rp->rbr_blocks_per_page;
3385 BUG_ON(rp->rbr_index > rp->rbr_table_size);
3386 if (rp->rbr_index == rp->rbr_table_size)
3389 if (rp->rbr_pending >= rp->rbr_kick_thresh) {
3390 nw64(RBR_KICK(rp->rx_channel), rp->rbr_pending);
3391 rp->rbr_pending = 0;
3396 static int niu_rx_pkt_ignore(struct niu *np, struct rx_ring_info *rp)
3398 unsigned int index = rp->rcr_index;
3403 struct page *page, **link;
3409 val = le64_to_cpup(&rp->rcr[index]);
3410 addr = (val & RCR_ENTRY_PKT_BUF_ADDR) <<
3411 RCR_ENTRY_PKT_BUF_ADDR_SHIFT;
3412 page = niu_find_rxpage(rp, addr, &link);
3414 rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >>
3415 RCR_ENTRY_PKTBUFSZ_SHIFT];
3416 if ((page->index + PAGE_SIZE) - rcr_size == addr) {
3417 *link = (struct page *) page->mapping;
3418 np->ops->unmap_page(np->device, page->index,
3419 PAGE_SIZE, DMA_FROM_DEVICE);
3421 page->mapping = NULL;
3423 rp->rbr_refill_pending++;
3426 index = NEXT_RCR(rp, index);
3427 if (!(val & RCR_ENTRY_MULTI))
3431 rp->rcr_index = index;
3436 static int niu_process_rx_pkt(struct napi_struct *napi, struct niu *np,
3437 struct rx_ring_info *rp)
3439 unsigned int index = rp->rcr_index;
3440 struct rx_pkt_hdr1 *rh;
3441 struct sk_buff *skb;
3444 skb = netdev_alloc_skb(np->dev, RX_SKB_ALLOC_SIZE);
3446 return niu_rx_pkt_ignore(np, rp);
3450 struct page *page, **link;
3451 u32 rcr_size, append_size;
3456 val = le64_to_cpup(&rp->rcr[index]);
3458 len = (val & RCR_ENTRY_L2_LEN) >>
3459 RCR_ENTRY_L2_LEN_SHIFT;
3462 addr = (val & RCR_ENTRY_PKT_BUF_ADDR) <<
3463 RCR_ENTRY_PKT_BUF_ADDR_SHIFT;
3464 page = niu_find_rxpage(rp, addr, &link);
3466 rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >>
3467 RCR_ENTRY_PKTBUFSZ_SHIFT];
3469 off = addr & ~PAGE_MASK;
3470 append_size = rcr_size;
3474 ptype = (val >> RCR_ENTRY_PKT_TYPE_SHIFT);
3475 if ((ptype == RCR_PKT_TYPE_TCP ||
3476 ptype == RCR_PKT_TYPE_UDP) &&
3477 !(val & (RCR_ENTRY_NOPORT |
3479 skb->ip_summed = CHECKSUM_UNNECESSARY;
3481 skb_checksum_none_assert(skb);
3482 } else if (!(val & RCR_ENTRY_MULTI))
3483 append_size = len - skb->len;
3485 niu_rx_skb_append(skb, page, off, append_size);
3486 if ((page->index + rp->rbr_block_size) - rcr_size == addr) {
3487 *link = (struct page *) page->mapping;
3488 np->ops->unmap_page(np->device, page->index,
3489 PAGE_SIZE, DMA_FROM_DEVICE);
3491 page->mapping = NULL;
3492 rp->rbr_refill_pending++;
3496 index = NEXT_RCR(rp, index);
3497 if (!(val & RCR_ENTRY_MULTI))
3501 rp->rcr_index = index;
3504 len = min_t(int, len, sizeof(*rh) + VLAN_ETH_HLEN);
3505 __pskb_pull_tail(skb, len);
3507 rh = (struct rx_pkt_hdr1 *) skb->data;
3508 if (np->dev->features & NETIF_F_RXHASH)
3509 skb->rxhash = ((u32)rh->hashval2_0 << 24 |
3510 (u32)rh->hashval2_1 << 16 |
3511 (u32)rh->hashval1_1 << 8 |
3512 (u32)rh->hashval1_2 << 0);
3513 skb_pull(skb, sizeof(*rh));
3516 rp->rx_bytes += skb->len;
3518 skb->protocol = eth_type_trans(skb, np->dev);
3519 skb_record_rx_queue(skb, rp->rx_channel);
3520 napi_gro_receive(napi, skb);
3525 static int niu_rbr_fill(struct niu *np, struct rx_ring_info *rp, gfp_t mask)
3527 int blocks_per_page = rp->rbr_blocks_per_page;
3528 int err, index = rp->rbr_index;
3531 while (index < (rp->rbr_table_size - blocks_per_page)) {
3532 err = niu_rbr_add_page(np, rp, mask, index);
3536 index += blocks_per_page;
3539 rp->rbr_index = index;
3543 static void niu_rbr_free(struct niu *np, struct rx_ring_info *rp)
3547 for (i = 0; i < MAX_RBR_RING_SIZE; i++) {
3550 page = rp->rxhash[i];
3552 struct page *next = (struct page *) page->mapping;
3553 u64 base = page->index;
3555 np->ops->unmap_page(np->device, base, PAGE_SIZE,
3558 page->mapping = NULL;
3566 for (i = 0; i < rp->rbr_table_size; i++)
3567 rp->rbr[i] = cpu_to_le32(0);
3571 static int release_tx_packet(struct niu *np, struct tx_ring_info *rp, int idx)
3573 struct tx_buff_info *tb = &rp->tx_buffs[idx];
3574 struct sk_buff *skb = tb->skb;
3575 struct tx_pkt_hdr *tp;
3579 tp = (struct tx_pkt_hdr *) skb->data;
3580 tx_flags = le64_to_cpup(&tp->flags);
3583 rp->tx_bytes += (((tx_flags & TXHDR_LEN) >> TXHDR_LEN_SHIFT) -
3584 ((tx_flags & TXHDR_PAD) / 2));
3586 len = skb_headlen(skb);
3587 np->ops->unmap_single(np->device, tb->mapping,
3588 len, DMA_TO_DEVICE);
3590 if (le64_to_cpu(rp->descr[idx]) & TX_DESC_MARK)
3595 idx = NEXT_TX(rp, idx);
3596 len -= MAX_TX_DESC_LEN;
3599 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
3600 tb = &rp->tx_buffs[idx];
3601 BUG_ON(tb->skb != NULL);
3602 np->ops->unmap_page(np->device, tb->mapping,
3603 skb_shinfo(skb)->frags[i].size,
3605 idx = NEXT_TX(rp, idx);
3613 #define NIU_TX_WAKEUP_THRESH(rp) ((rp)->pending / 4)
3615 static void niu_tx_work(struct niu *np, struct tx_ring_info *rp)
3617 struct netdev_queue *txq;
3622 index = (rp - np->tx_rings);
3623 txq = netdev_get_tx_queue(np->dev, index);
3626 if (unlikely(!(cs & (TX_CS_MK | TX_CS_MMK))))
3629 tmp = pkt_cnt = (cs & TX_CS_PKT_CNT) >> TX_CS_PKT_CNT_SHIFT;
3630 pkt_cnt = (pkt_cnt - rp->last_pkt_cnt) &
3631 (TX_CS_PKT_CNT >> TX_CS_PKT_CNT_SHIFT);
3633 rp->last_pkt_cnt = tmp;
3637 netif_printk(np, tx_done, KERN_DEBUG, np->dev,
3638 "%s() pkt_cnt[%u] cons[%d]\n", __func__, pkt_cnt, cons);
3641 cons = release_tx_packet(np, rp, cons);
3647 if (unlikely(netif_tx_queue_stopped(txq) &&
3648 (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)))) {
3649 __netif_tx_lock(txq, smp_processor_id());
3650 if (netif_tx_queue_stopped(txq) &&
3651 (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)))
3652 netif_tx_wake_queue(txq);
3653 __netif_tx_unlock(txq);
3657 static inline void niu_sync_rx_discard_stats(struct niu *np,
3658 struct rx_ring_info *rp,
3661 /* This elaborate scheme is needed for reading the RX discard
3662 * counters, as they are only 16-bit and can overflow quickly,
3663 * and because the overflow indication bit is not usable as
3664 * the counter value does not wrap, but remains at max value
3667 * In theory and in practice counters can be lost in between
3668 * reading nr64() and clearing the counter nw64(). For this
3669 * reason, the number of counter clearings nw64() is
3670 * limited/reduced though the limit parameter.
3672 int rx_channel = rp->rx_channel;
3675 /* RXMISC (Receive Miscellaneous Discard Count), covers the
3676 * following discard events: IPP (Input Port Process),
3677 * FFLP/TCAM, Full RCR (Receive Completion Ring) RBR (Receive
3678 * Block Ring) prefetch buffer is empty.
3680 misc = nr64(RXMISC(rx_channel));
3681 if (unlikely((misc & RXMISC_COUNT) > limit)) {
3682 nw64(RXMISC(rx_channel), 0);
3683 rp->rx_errors += misc & RXMISC_COUNT;
3685 if (unlikely(misc & RXMISC_OFLOW))
3686 dev_err(np->device, "rx-%d: Counter overflow RXMISC discard\n",
3689 netif_printk(np, rx_err, KERN_DEBUG, np->dev,
3690 "rx-%d: MISC drop=%u over=%u\n",
3691 rx_channel, misc, misc-limit);
3694 /* WRED (Weighted Random Early Discard) by hardware */
3695 wred = nr64(RED_DIS_CNT(rx_channel));
3696 if (unlikely((wred & RED_DIS_CNT_COUNT) > limit)) {
3697 nw64(RED_DIS_CNT(rx_channel), 0);
3698 rp->rx_dropped += wred & RED_DIS_CNT_COUNT;
3700 if (unlikely(wred & RED_DIS_CNT_OFLOW))
3701 dev_err(np->device, "rx-%d: Counter overflow WRED discard\n", rx_channel);
3703 netif_printk(np, rx_err, KERN_DEBUG, np->dev,
3704 "rx-%d: WRED drop=%u over=%u\n",
3705 rx_channel, wred, wred-limit);
3709 static int niu_rx_work(struct napi_struct *napi, struct niu *np,
3710 struct rx_ring_info *rp, int budget)
3712 int qlen, rcr_done = 0, work_done = 0;
3713 struct rxdma_mailbox *mbox = rp->mbox;
3717 stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel));
3718 qlen = nr64(RCRSTAT_A(rp->rx_channel)) & RCRSTAT_A_QLEN;
3720 stat = le64_to_cpup(&mbox->rx_dma_ctl_stat);
3721 qlen = (le64_to_cpup(&mbox->rcrstat_a) & RCRSTAT_A_QLEN);
3723 mbox->rx_dma_ctl_stat = 0;
3724 mbox->rcrstat_a = 0;
3726 netif_printk(np, rx_status, KERN_DEBUG, np->dev,
3727 "%s(chan[%d]), stat[%llx] qlen=%d\n",
3728 __func__, rp->rx_channel, (unsigned long long)stat, qlen);
3730 rcr_done = work_done = 0;
3731 qlen = min(qlen, budget);
3732 while (work_done < qlen) {
3733 rcr_done += niu_process_rx_pkt(napi, np, rp);
3737 if (rp->rbr_refill_pending >= rp->rbr_kick_thresh) {
3740 for (i = 0; i < rp->rbr_refill_pending; i++)
3741 niu_rbr_refill(np, rp, GFP_ATOMIC);
3742 rp->rbr_refill_pending = 0;
3745 stat = (RX_DMA_CTL_STAT_MEX |
3746 ((u64)work_done << RX_DMA_CTL_STAT_PKTREAD_SHIFT) |
3747 ((u64)rcr_done << RX_DMA_CTL_STAT_PTRREAD_SHIFT));
3749 nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat);
3751 /* Only sync discards stats when qlen indicate potential for drops */
3753 niu_sync_rx_discard_stats(np, rp, 0x7FFF);
3758 static int niu_poll_core(struct niu *np, struct niu_ldg *lp, int budget)
3761 u32 tx_vec = (v0 >> 32);
3762 u32 rx_vec = (v0 & 0xffffffff);
3763 int i, work_done = 0;
3765 netif_printk(np, intr, KERN_DEBUG, np->dev,
3766 "%s() v0[%016llx]\n", __func__, (unsigned long long)v0);
3768 for (i = 0; i < np->num_tx_rings; i++) {
3769 struct tx_ring_info *rp = &np->tx_rings[i];
3770 if (tx_vec & (1 << rp->tx_channel))
3771 niu_tx_work(np, rp);
3772 nw64(LD_IM0(LDN_TXDMA(rp->tx_channel)), 0);
3775 for (i = 0; i < np->num_rx_rings; i++) {
3776 struct rx_ring_info *rp = &np->rx_rings[i];
3778 if (rx_vec & (1 << rp->rx_channel)) {
3781 this_work_done = niu_rx_work(&lp->napi, np, rp,
3784 budget -= this_work_done;
3785 work_done += this_work_done;
3787 nw64(LD_IM0(LDN_RXDMA(rp->rx_channel)), 0);
3793 static int niu_poll(struct napi_struct *napi, int budget)
3795 struct niu_ldg *lp = container_of(napi, struct niu_ldg, napi);
3796 struct niu *np = lp->np;
3799 work_done = niu_poll_core(np, lp, budget);
3801 if (work_done < budget) {
3802 napi_complete(napi);
3803 niu_ldg_rearm(np, lp, 1);
3808 static void niu_log_rxchan_errors(struct niu *np, struct rx_ring_info *rp,
3811 netdev_err(np->dev, "RX channel %u errors ( ", rp->rx_channel);
3813 if (stat & RX_DMA_CTL_STAT_RBR_TMOUT)
3814 pr_cont("RBR_TMOUT ");
3815 if (stat & RX_DMA_CTL_STAT_RSP_CNT_ERR)
3816 pr_cont("RSP_CNT ");
3817 if (stat & RX_DMA_CTL_STAT_BYTE_EN_BUS)
3818 pr_cont("BYTE_EN_BUS ");
3819 if (stat & RX_DMA_CTL_STAT_RSP_DAT_ERR)
3820 pr_cont("RSP_DAT ");
3821 if (stat & RX_DMA_CTL_STAT_RCR_ACK_ERR)
3822 pr_cont("RCR_ACK ");
3823 if (stat & RX_DMA_CTL_STAT_RCR_SHA_PAR)
3824 pr_cont("RCR_SHA_PAR ");
3825 if (stat & RX_DMA_CTL_STAT_RBR_PRE_PAR)
3826 pr_cont("RBR_PRE_PAR ");
3827 if (stat & RX_DMA_CTL_STAT_CONFIG_ERR)
3829 if (stat & RX_DMA_CTL_STAT_RCRINCON)
3830 pr_cont("RCRINCON ");
3831 if (stat & RX_DMA_CTL_STAT_RCRFULL)
3832 pr_cont("RCRFULL ");
3833 if (stat & RX_DMA_CTL_STAT_RBRFULL)
3834 pr_cont("RBRFULL ");
3835 if (stat & RX_DMA_CTL_STAT_RBRLOGPAGE)
3836 pr_cont("RBRLOGPAGE ");
3837 if (stat & RX_DMA_CTL_STAT_CFIGLOGPAGE)
3838 pr_cont("CFIGLOGPAGE ");
3839 if (stat & RX_DMA_CTL_STAT_DC_FIFO_ERR)
3840 pr_cont("DC_FIDO ");
3845 static int niu_rx_error(struct niu *np, struct rx_ring_info *rp)
3847 u64 stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel));
3851 if (stat & (RX_DMA_CTL_STAT_CHAN_FATAL |
3852 RX_DMA_CTL_STAT_PORT_FATAL))
3856 netdev_err(np->dev, "RX channel %u error, stat[%llx]\n",
3858 (unsigned long long) stat);
3860 niu_log_rxchan_errors(np, rp, stat);
3863 nw64(RX_DMA_CTL_STAT(rp->rx_channel),
3864 stat & RX_DMA_CTL_WRITE_CLEAR_ERRS);
3869 static void niu_log_txchan_errors(struct niu *np, struct tx_ring_info *rp,
3872 netdev_err(np->dev, "TX channel %u errors ( ", rp->tx_channel);
3874 if (cs & TX_CS_MBOX_ERR)
3876 if (cs & TX_CS_PKT_SIZE_ERR)
3877 pr_cont("PKT_SIZE ");
3878 if (cs & TX_CS_TX_RING_OFLOW)
3879 pr_cont("TX_RING_OFLOW ");
3880 if (cs & TX_CS_PREF_BUF_PAR_ERR)
3881 pr_cont("PREF_BUF_PAR ");
3882 if (cs & TX_CS_NACK_PREF)
3883 pr_cont("NACK_PREF ");
3884 if (cs & TX_CS_NACK_PKT_RD)
3885 pr_cont("NACK_PKT_RD ");
3886 if (cs & TX_CS_CONF_PART_ERR)
3887 pr_cont("CONF_PART ");
3888 if (cs & TX_CS_PKT_PRT_ERR)
3889 pr_cont("PKT_PTR ");
3894 static int niu_tx_error(struct niu *np, struct tx_ring_info *rp)
3898 cs = nr64(TX_CS(rp->tx_channel));
3899 logh = nr64(TX_RNG_ERR_LOGH(rp->tx_channel));
3900 logl = nr64(TX_RNG_ERR_LOGL(rp->tx_channel));
3902 netdev_err(np->dev, "TX channel %u error, cs[%llx] logh[%llx] logl[%llx]\n",
3904 (unsigned long long)cs,
3905 (unsigned long long)logh,
3906 (unsigned long long)logl);
3908 niu_log_txchan_errors(np, rp, cs);
3913 static int niu_mif_interrupt(struct niu *np)
3915 u64 mif_status = nr64(MIF_STATUS);
3918 if (np->flags & NIU_FLAGS_XMAC) {
3919 u64 xrxmac_stat = nr64_mac(XRXMAC_STATUS);
3921 if (xrxmac_stat & XRXMAC_STATUS_PHY_MDINT)
3925 netdev_err(np->dev, "MIF interrupt, stat[%llx] phy_mdint(%d)\n",
3926 (unsigned long long)mif_status, phy_mdint);
3931 static void niu_xmac_interrupt(struct niu *np)
3933 struct niu_xmac_stats *mp = &np->mac_stats.xmac;
3936 val = nr64_mac(XTXMAC_STATUS);
3937 if (val & XTXMAC_STATUS_FRAME_CNT_EXP)
3938 mp->tx_frames += TXMAC_FRM_CNT_COUNT;
3939 if (val & XTXMAC_STATUS_BYTE_CNT_EXP)
3940 mp->tx_bytes += TXMAC_BYTE_CNT_COUNT;
3941 if (val & XTXMAC_STATUS_TXFIFO_XFR_ERR)
3942 mp->tx_fifo_errors++;
3943 if (val & XTXMAC_STATUS_TXMAC_OFLOW)
3944 mp->tx_overflow_errors++;
3945 if (val & XTXMAC_STATUS_MAX_PSIZE_ERR)
3946 mp->tx_max_pkt_size_errors++;
3947 if (val & XTXMAC_STATUS_TXMAC_UFLOW)
3948 mp->tx_underflow_errors++;
3950 val = nr64_mac(XRXMAC_STATUS);
3951 if (val & XRXMAC_STATUS_LCL_FLT_STATUS)
3952 mp->rx_local_faults++;
3953 if (val & XRXMAC_STATUS_RFLT_DET)
3954 mp->rx_remote_faults++;
3955 if (val & XRXMAC_STATUS_LFLT_CNT_EXP)
3956 mp->rx_link_faults += LINK_FAULT_CNT_COUNT;
3957 if (val & XRXMAC_STATUS_ALIGNERR_CNT_EXP)
3958 mp->rx_align_errors += RXMAC_ALIGN_ERR_CNT_COUNT;
3959 if (val & XRXMAC_STATUS_RXFRAG_CNT_EXP)
3960 mp->rx_frags += RXMAC_FRAG_CNT_COUNT;
3961 if (val & XRXMAC_STATUS_RXMULTF_CNT_EXP)
3962 mp->rx_mcasts += RXMAC_MC_FRM_CNT_COUNT;
3963 if (val & XRXMAC_STATUS_RXBCAST_CNT_EXP)
3964 mp->rx_bcasts += RXMAC_BC_FRM_CNT_COUNT;
3965 if (val & XRXMAC_STATUS_RXBCAST_CNT_EXP)
3966 mp->rx_bcasts += RXMAC_BC_FRM_CNT_COUNT;
3967 if (val & XRXMAC_STATUS_RXHIST1_CNT_EXP)
3968 mp->rx_hist_cnt1 += RXMAC_HIST_CNT1_COUNT;
3969 if (val & XRXMAC_STATUS_RXHIST2_CNT_EXP)
3970 mp->rx_hist_cnt2 += RXMAC_HIST_CNT2_COUNT;
3971 if (val & XRXMAC_STATUS_RXHIST3_CNT_EXP)
3972 mp->rx_hist_cnt3 += RXMAC_HIST_CNT3_COUNT;
3973 if (val & XRXMAC_STATUS_RXHIST4_CNT_EXP)
3974 mp->rx_hist_cnt4 += RXMAC_HIST_CNT4_COUNT;
3975 if (val & XRXMAC_STATUS_RXHIST5_CNT_EXP)
3976 mp->rx_hist_cnt5 += RXMAC_HIST_CNT5_COUNT;
3977 if (val & XRXMAC_STATUS_RXHIST6_CNT_EXP)
3978 mp->rx_hist_cnt6 += RXMAC_HIST_CNT6_COUNT;
3979 if (val & XRXMAC_STATUS_RXHIST7_CNT_EXP)
3980 mp->rx_hist_cnt7 += RXMAC_HIST_CNT7_COUNT;
3981 if (val & XRXMAC_STATUS_RXOCTET_CNT_EXP)
3982 mp->rx_octets += RXMAC_BT_CNT_COUNT;
3983 if (val & XRXMAC_STATUS_CVIOLERR_CNT_EXP)
3984 mp->rx_code_violations += RXMAC_CD_VIO_CNT_COUNT;
3985 if (val & XRXMAC_STATUS_LENERR_CNT_EXP)
3986 mp->rx_len_errors += RXMAC_MPSZER_CNT_COUNT;
3987 if (val & XRXMAC_STATUS_CRCERR_CNT_EXP)
3988 mp->rx_crc_errors += RXMAC_CRC_ER_CNT_COUNT;
3989 if (val & XRXMAC_STATUS_RXUFLOW)
3990 mp->rx_underflows++;
3991 if (val & XRXMAC_STATUS_RXOFLOW)
3994 val = nr64_mac(XMAC_FC_STAT);
3995 if (val & XMAC_FC_STAT_TX_MAC_NPAUSE)
3996 mp->pause_off_state++;
3997 if (val & XMAC_FC_STAT_TX_MAC_PAUSE)
3998 mp->pause_on_state++;
3999 if (val & XMAC_FC_STAT_RX_MAC_RPAUSE)
4000 mp->pause_received++;
4003 static void niu_bmac_interrupt(struct niu *np)
4005 struct niu_bmac_stats *mp = &np->mac_stats.bmac;
4008 val = nr64_mac(BTXMAC_STATUS);
4009 if (val & BTXMAC_STATUS_UNDERRUN)
4010 mp->tx_underflow_errors++;
4011 if (val & BTXMAC_STATUS_MAX_PKT_ERR)
4012 mp->tx_max_pkt_size_errors++;
4013 if (val & BTXMAC_STATUS_BYTE_CNT_EXP)
4014 mp->tx_bytes += BTXMAC_BYTE_CNT_COUNT;
4015 if (val & BTXMAC_STATUS_FRAME_CNT_EXP)
4016 mp->tx_frames += BTXMAC_FRM_CNT_COUNT;
4018 val = nr64_mac(BRXMAC_STATUS);
4019 if (val & BRXMAC_STATUS_OVERFLOW)
4021 if (val & BRXMAC_STATUS_FRAME_CNT_EXP)
4022 mp->rx_frames += BRXMAC_FRAME_CNT_COUNT;
4023 if (val & BRXMAC_STATUS_ALIGN_ERR_EXP)
4024 mp->rx_align_errors += BRXMAC_ALIGN_ERR_CNT_COUNT;
4025 if (val & BRXMAC_STATUS_CRC_ERR_EXP)
4026 mp->rx_crc_errors += BRXMAC_ALIGN_ERR_CNT_COUNT;
4027 if (val & BRXMAC_STATUS_LEN_ERR_EXP)
4028 mp->rx_len_errors += BRXMAC_CODE_VIOL_ERR_CNT_COUNT;
4030 val = nr64_mac(BMAC_CTRL_STATUS);
4031 if (val & BMAC_CTRL_STATUS_NOPAUSE)
4032 mp->pause_off_state++;
4033 if (val & BMAC_CTRL_STATUS_PAUSE)
4034 mp->pause_on_state++;
4035 if (val & BMAC_CTRL_STATUS_PAUSE_RECV)
4036 mp->pause_received++;
4039 static int niu_mac_interrupt(struct niu *np)
4041 if (np->flags & NIU_FLAGS_XMAC)
4042 niu_xmac_interrupt(np);
4044 niu_bmac_interrupt(np);
4049 static void niu_log_device_error(struct niu *np, u64 stat)
4051 netdev_err(np->dev, "Core device errors ( ");
4053 if (stat & SYS_ERR_MASK_META2)
4055 if (stat & SYS_ERR_MASK_META1)
4057 if (stat & SYS_ERR_MASK_PEU)
4059 if (stat & SYS_ERR_MASK_TXC)
4061 if (stat & SYS_ERR_MASK_RDMC)
4063 if (stat & SYS_ERR_MASK_TDMC)
4065 if (stat & SYS_ERR_MASK_ZCP)
4067 if (stat & SYS_ERR_MASK_FFLP)
4069 if (stat & SYS_ERR_MASK_IPP)
4071 if (stat & SYS_ERR_MASK_MAC)
4073 if (stat & SYS_ERR_MASK_SMX)
4079 static int niu_device_error(struct niu *np)
4081 u64 stat = nr64(SYS_ERR_STAT);
4083 netdev_err(np->dev, "Core device error, stat[%llx]\n",
4084 (unsigned long long)stat);
4086 niu_log_device_error(np, stat);
4091 static int niu_slowpath_interrupt(struct niu *np, struct niu_ldg *lp,
4092 u64 v0, u64 v1, u64 v2)
4101 if (v1 & 0x00000000ffffffffULL) {
4102 u32 rx_vec = (v1 & 0xffffffff);
4104 for (i = 0; i < np->num_rx_rings; i++) {
4105 struct rx_ring_info *rp = &np->rx_rings[i];
4107 if (rx_vec & (1 << rp->rx_channel)) {
4108 int r = niu_rx_error(np, rp);
4113 nw64(RX_DMA_CTL_STAT(rp->rx_channel),
4114 RX_DMA_CTL_STAT_MEX);
4119 if (v1 & 0x7fffffff00000000ULL) {
4120 u32 tx_vec = (v1 >> 32) & 0x7fffffff;
4122 for (i = 0; i < np->num_tx_rings; i++) {
4123 struct tx_ring_info *rp = &np->tx_rings[i];
4125 if (tx_vec & (1 << rp->tx_channel)) {
4126 int r = niu_tx_error(np, rp);
4132 if ((v0 | v1) & 0x8000000000000000ULL) {
4133 int r = niu_mif_interrupt(np);
4139 int r = niu_mac_interrupt(np);
4144 int r = niu_device_error(np);
4151 niu_enable_interrupts(np, 0);
4156 static void niu_rxchan_intr(struct niu *np, struct rx_ring_info *rp,
4159 struct rxdma_mailbox *mbox = rp->mbox;
4160 u64 stat_write, stat = le64_to_cpup(&mbox->rx_dma_ctl_stat);
4162 stat_write = (RX_DMA_CTL_STAT_RCRTHRES |
4163 RX_DMA_CTL_STAT_RCRTO);
4164 nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat_write);
4166 netif_printk(np, intr, KERN_DEBUG, np->dev,
4167 "%s() stat[%llx]\n", __func__, (unsigned long long)stat);
4170 static void niu_txchan_intr(struct niu *np, struct tx_ring_info *rp,
4173 rp->tx_cs = nr64(TX_CS(rp->tx_channel));
4175 netif_printk(np, intr, KERN_DEBUG, np->dev,
4176 "%s() cs[%llx]\n", __func__, (unsigned long long)rp->tx_cs);
4179 static void __niu_fastpath_interrupt(struct niu *np, int ldg, u64 v0)
4181 struct niu_parent *parent = np->parent;
4185 tx_vec = (v0 >> 32);
4186 rx_vec = (v0 & 0xffffffff);
4188 for (i = 0; i < np->num_rx_rings; i++) {
4189 struct rx_ring_info *rp = &np->rx_rings[i];
4190 int ldn = LDN_RXDMA(rp->rx_channel);
4192 if (parent->ldg_map[ldn] != ldg)
4195 nw64(LD_IM0(ldn), LD_IM0_MASK);
4196 if (rx_vec & (1 << rp->rx_channel))
4197 niu_rxchan_intr(np, rp, ldn);
4200 for (i = 0; i < np->num_tx_rings; i++) {
4201 struct tx_ring_info *rp = &np->tx_rings[i];
4202 int ldn = LDN_TXDMA(rp->tx_channel);
4204 if (parent->ldg_map[ldn] != ldg)
4207 nw64(LD_IM0(ldn), LD_IM0_MASK);
4208 if (tx_vec & (1 << rp->tx_channel))
4209 niu_txchan_intr(np, rp, ldn);
4213 static void niu_schedule_napi(struct niu *np, struct niu_ldg *lp,
4214 u64 v0, u64 v1, u64 v2)
4216 if (likely(napi_schedule_prep(&lp->napi))) {
4220 __niu_fastpath_interrupt(np, lp->ldg_num, v0);
4221 __napi_schedule(&lp->napi);
4225 static irqreturn_t niu_interrupt(int irq, void *dev_id)
4227 struct niu_ldg *lp = dev_id;
4228 struct niu *np = lp->np;
4229 int ldg = lp->ldg_num;
4230 unsigned long flags;
4233 if (netif_msg_intr(np))
4234 printk(KERN_DEBUG KBUILD_MODNAME ": " "%s() ldg[%p](%d)",
4237 spin_lock_irqsave(&np->lock, flags);
4239 v0 = nr64(LDSV0(ldg));
4240 v1 = nr64(LDSV1(ldg));
4241 v2 = nr64(LDSV2(ldg));
4243 if (netif_msg_intr(np))
4244 pr_cont(" v0[%llx] v1[%llx] v2[%llx]\n",
4245 (unsigned long long) v0,
4246 (unsigned long long) v1,
4247 (unsigned long long) v2);
4249 if (unlikely(!v0 && !v1 && !v2)) {
4250 spin_unlock_irqrestore(&np->lock, flags);
4254 if (unlikely((v0 & ((u64)1 << LDN_MIF)) || v1 || v2)) {
4255 int err = niu_slowpath_interrupt(np, lp, v0, v1, v2);
4259 if (likely(v0 & ~((u64)1 << LDN_MIF)))
4260 niu_schedule_napi(np, lp, v0, v1, v2);
4262 niu_ldg_rearm(np, lp, 1);
4264 spin_unlock_irqrestore(&np->lock, flags);
4269 static void niu_free_rx_ring_info(struct niu *np, struct rx_ring_info *rp)
4272 np->ops->free_coherent(np->device,
4273 sizeof(struct rxdma_mailbox),
4274 rp->mbox, rp->mbox_dma);
4278 np->ops->free_coherent(np->device,
4279 MAX_RCR_RING_SIZE * sizeof(__le64),
4280 rp->rcr, rp->rcr_dma);
4282 rp->rcr_table_size = 0;
4286 niu_rbr_free(np, rp);
4288 np->ops->free_coherent(np->device,
4289 MAX_RBR_RING_SIZE * sizeof(__le32),
4290 rp->rbr, rp->rbr_dma);
4292 rp->rbr_table_size = 0;
4299 static void niu_free_tx_ring_info(struct niu *np, struct tx_ring_info *rp)
4302 np->ops->free_coherent(np->device,
4303 sizeof(struct txdma_mailbox),
4304 rp->mbox, rp->mbox_dma);
4310 for (i = 0; i < MAX_TX_RING_SIZE; i++) {
4311 if (rp->tx_buffs[i].skb)
4312 (void) release_tx_packet(np, rp, i);
4315 np->ops->free_coherent(np->device,
4316 MAX_TX_RING_SIZE * sizeof(__le64),
4317 rp->descr, rp->descr_dma);
4326 static void niu_free_channels(struct niu *np)
4331 for (i = 0; i < np->num_rx_rings; i++) {
4332 struct rx_ring_info *rp = &np->rx_rings[i];
4334 niu_free_rx_ring_info(np, rp);
4336 kfree(np->rx_rings);
4337 np->rx_rings = NULL;
4338 np->num_rx_rings = 0;
4342 for (i = 0; i < np->num_tx_rings; i++) {
4343 struct tx_ring_info *rp = &np->tx_rings[i];
4345 niu_free_tx_ring_info(np, rp);
4347 kfree(np->tx_rings);
4348 np->tx_rings = NULL;
4349 np->num_tx_rings = 0;
4353 static int niu_alloc_rx_ring_info(struct niu *np,
4354 struct rx_ring_info *rp)
4356 BUILD_BUG_ON(sizeof(struct rxdma_mailbox) != 64);
4358 rp->rxhash = kzalloc(MAX_RBR_RING_SIZE * sizeof(struct page *),
4363 rp->mbox = np->ops->alloc_coherent(np->device,
4364 sizeof(struct rxdma_mailbox),
4365 &rp->mbox_dma, GFP_KERNEL);
4368 if ((unsigned long)rp->mbox & (64UL - 1)) {
4369 netdev_err(np->dev, "Coherent alloc gives misaligned RXDMA mailbox %p\n",
4374 rp->rcr = np->ops->alloc_coherent(np->device,
4375 MAX_RCR_RING_SIZE * sizeof(__le64),
4376 &rp->rcr_dma, GFP_KERNEL);
4379 if ((unsigned long)rp->rcr & (64UL - 1)) {
4380 netdev_err(np->dev, "Coherent alloc gives misaligned RXDMA RCR table %p\n",
4384 rp->rcr_table_size = MAX_RCR_RING_SIZE;
4387 rp->rbr = np->ops->alloc_coherent(np->device,
4388 MAX_RBR_RING_SIZE * sizeof(__le32),
4389 &rp->rbr_dma, GFP_KERNEL);
4392 if ((unsigned long)rp->rbr & (64UL - 1)) {
4393 netdev_err(np->dev, "Coherent alloc gives misaligned RXDMA RBR table %p\n",
4397 rp->rbr_table_size = MAX_RBR_RING_SIZE;
4399 rp->rbr_pending = 0;
4404 static void niu_set_max_burst(struct niu *np, struct tx_ring_info *rp)
4406 int mtu = np->dev->mtu;
4408 /* These values are recommended by the HW designers for fair
4409 * utilization of DRR amongst the rings.
4411 rp->max_burst = mtu + 32;
4412 if (rp->max_burst > 4096)
4413 rp->max_burst = 4096;
4416 static int niu_alloc_tx_ring_info(struct niu *np,
4417 struct tx_ring_info *rp)
4419 BUILD_BUG_ON(sizeof(struct txdma_mailbox) != 64);
4421 rp->mbox = np->ops->alloc_coherent(np->device,
4422 sizeof(struct txdma_mailbox),
4423 &rp->mbox_dma, GFP_KERNEL);
4426 if ((unsigned long)rp->mbox & (64UL - 1)) {
4427 netdev_err(np->dev, "Coherent alloc gives misaligned TXDMA mailbox %p\n",
4432 rp->descr = np->ops->alloc_coherent(np->device,
4433 MAX_TX_RING_SIZE * sizeof(__le64),
4434 &rp->descr_dma, GFP_KERNEL);
4437 if ((unsigned long)rp->descr & (64UL - 1)) {
4438 netdev_err(np->dev, "Coherent alloc gives misaligned TXDMA descr table %p\n",
4443 rp->pending = MAX_TX_RING_SIZE;
4448 /* XXX make these configurable... XXX */
4449 rp->mark_freq = rp->pending / 4;
4451 niu_set_max_burst(np, rp);
4456 static void niu_size_rbr(struct niu *np, struct rx_ring_info *rp)
4460 bss = min(PAGE_SHIFT, 15);
4462 rp->rbr_block_size = 1 << bss;
4463 rp->rbr_blocks_per_page = 1 << (PAGE_SHIFT-bss);
4465 rp->rbr_sizes[0] = 256;
4466 rp->rbr_sizes[1] = 1024;
4467 if (np->dev->mtu > ETH_DATA_LEN) {
4468 switch (PAGE_SIZE) {
4470 rp->rbr_sizes[2] = 4096;
4474 rp->rbr_sizes[2] = 8192;
4478 rp->rbr_sizes[2] = 2048;
4480 rp->rbr_sizes[3] = rp->rbr_block_size;
4483 static int niu_alloc_channels(struct niu *np)
4485 struct niu_parent *parent = np->parent;
4486 int first_rx_channel, first_tx_channel;
4487 int num_rx_rings, num_tx_rings;
4488 struct rx_ring_info *rx_rings;
4489 struct tx_ring_info *tx_rings;
4493 first_rx_channel = first_tx_channel = 0;
4494 for (i = 0; i < port; i++) {
4495 first_rx_channel += parent->rxchan_per_port[i];
4496 first_tx_channel += parent->txchan_per_port[i];
4499 num_rx_rings = parent->rxchan_per_port[port];
4500 num_tx_rings = parent->txchan_per_port[port];
4502 rx_rings = kcalloc(num_rx_rings, sizeof(struct rx_ring_info),
4508 np->num_rx_rings = num_rx_rings;
4510 np->rx_rings = rx_rings;
4512 netif_set_real_num_rx_queues(np->dev, num_rx_rings);
4514 for (i = 0; i < np->num_rx_rings; i++) {
4515 struct rx_ring_info *rp = &np->rx_rings[i];
4518 rp->rx_channel = first_rx_channel + i;
4520 err = niu_alloc_rx_ring_info(np, rp);
4524 niu_size_rbr(np, rp);
4526 /* XXX better defaults, configurable, etc... XXX */
4527 rp->nonsyn_window = 64;
4528 rp->nonsyn_threshold = rp->rcr_table_size - 64;
4529 rp->syn_window = 64;
4530 rp->syn_threshold = rp->rcr_table_size - 64;
4531 rp->rcr_pkt_threshold = 16;
4532 rp->rcr_timeout = 8;
4533 rp->rbr_kick_thresh = RBR_REFILL_MIN;
4534 if (rp->rbr_kick_thresh < rp->rbr_blocks_per_page)
4535 rp->rbr_kick_thresh = rp->rbr_blocks_per_page;
4537 err = niu_rbr_fill(np, rp, GFP_KERNEL);
4542 tx_rings = kcalloc(num_tx_rings, sizeof(struct tx_ring_info),
4548 np->num_tx_rings = num_tx_rings;
4550 np->tx_rings = tx_rings;
4552 netif_set_real_num_tx_queues(np->dev, num_tx_rings);
4554 for (i = 0; i < np->num_tx_rings; i++) {
4555 struct tx_ring_info *rp = &np->tx_rings[i];
4558 rp->tx_channel = first_tx_channel + i;
4560 err = niu_alloc_tx_ring_info(np, rp);
4568 niu_free_channels(np);
4572 static int niu_tx_cs_sng_poll(struct niu *np, int channel)
4576 while (--limit > 0) {
4577 u64 val = nr64(TX_CS(channel));
4578 if (val & TX_CS_SNG_STATE)
4584 static int niu_tx_channel_stop(struct niu *np, int channel)
4586 u64 val = nr64(TX_CS(channel));
4588 val |= TX_CS_STOP_N_GO;
4589 nw64(TX_CS(channel), val);
4591 return niu_tx_cs_sng_poll(np, channel);
4594 static int niu_tx_cs_reset_poll(struct niu *np, int channel)
4598 while (--limit > 0) {
4599 u64 val = nr64(TX_CS(channel));
4600 if (!(val & TX_CS_RST))
4606 static int niu_tx_channel_reset(struct niu *np, int channel)
4608 u64 val = nr64(TX_CS(channel));
4612 nw64(TX_CS(channel), val);
4614 err = niu_tx_cs_reset_poll(np, channel);
4616 nw64(TX_RING_KICK(channel), 0);
4621 static int niu_tx_channel_lpage_init(struct niu *np, int channel)
4625 nw64(TX_LOG_MASK1(channel), 0);
4626 nw64(TX_LOG_VAL1(channel), 0);
4627 nw64(TX_LOG_MASK2(channel), 0);
4628 nw64(TX_LOG_VAL2(channel), 0);
4629 nw64(TX_LOG_PAGE_RELO1(channel), 0);
4630 nw64(TX_LOG_PAGE_RELO2(channel), 0);
4631 nw64(TX_LOG_PAGE_HDL(channel), 0);
4633 val = (u64)np->port << TX_LOG_PAGE_VLD_FUNC_SHIFT;
4634 val |= (TX_LOG_PAGE_VLD_PAGE0 | TX_LOG_PAGE_VLD_PAGE1);
4635 nw64(TX_LOG_PAGE_VLD(channel), val);
4637 /* XXX TXDMA 32bit mode? XXX */
4642 static void niu_txc_enable_port(struct niu *np, int on)
4644 unsigned long flags;
4647 niu_lock_parent(np, flags);
4648 val = nr64(TXC_CONTROL);
4649 mask = (u64)1 << np->port;
4651 val |= TXC_CONTROL_ENABLE | mask;
4654 if ((val & ~TXC_CONTROL_ENABLE) == 0)
4655 val &= ~TXC_CONTROL_ENABLE;
4657 nw64(TXC_CONTROL, val);
4658 niu_unlock_parent(np, flags);
4661 static void niu_txc_set_imask(struct niu *np, u64 imask)
4663 unsigned long flags;
4666 niu_lock_parent(np, flags);
4667 val = nr64(TXC_INT_MASK);
4668 val &= ~TXC_INT_MASK_VAL(np->port);
4669 val |= (imask << TXC_INT_MASK_VAL_SHIFT(np->port));
4670 niu_unlock_parent(np, flags);
4673 static void niu_txc_port_dma_enable(struct niu *np, int on)
4680 for (i = 0; i < np->num_tx_rings; i++)
4681 val |= (1 << np->tx_rings[i].tx_channel);
4683 nw64(TXC_PORT_DMA(np->port), val);
4686 static int niu_init_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
4688 int err, channel = rp->tx_channel;
4691 err = niu_tx_channel_stop(np, channel);
4695 err = niu_tx_channel_reset(np, channel);
4699 err = niu_tx_channel_lpage_init(np, channel);
4703 nw64(TXC_DMA_MAX(channel), rp->max_burst);
4704 nw64(TX_ENT_MSK(channel), 0);
4706 if (rp->descr_dma & ~(TX_RNG_CFIG_STADDR_BASE |
4707 TX_RNG_CFIG_STADDR)) {
4708 netdev_err(np->dev, "TX ring channel %d DMA addr (%llx) is not aligned\n",
4709 channel, (unsigned long long)rp->descr_dma);
4713 /* The length field in TX_RNG_CFIG is measured in 64-byte
4714 * blocks. rp->pending is the number of TX descriptors in
4715 * our ring, 8 bytes each, thus we divide by 8 bytes more
4716 * to get the proper value the chip wants.
4718 ring_len = (rp->pending / 8);
4720 val = ((ring_len << TX_RNG_CFIG_LEN_SHIFT) |
4722 nw64(TX_RNG_CFIG(channel), val);
4724 if (((rp->mbox_dma >> 32) & ~TXDMA_MBH_MBADDR) ||
4725 ((u32)rp->mbox_dma & ~TXDMA_MBL_MBADDR)) {
4726 netdev_err(np->dev, "TX ring channel %d MBOX addr (%llx) has invalid bits\n",
4727 channel, (unsigned long long)rp->mbox_dma);
4730 nw64(TXDMA_MBH(channel), rp->mbox_dma >> 32);
4731 nw64(TXDMA_MBL(channel), rp->mbox_dma & TXDMA_MBL_MBADDR);
4733 nw64(TX_CS(channel), 0);
4735 rp->last_pkt_cnt = 0;
4740 static void niu_init_rdc_groups(struct niu *np)
4742 struct niu_rdc_tables *tp = &np->parent->rdc_group_cfg[np->port];
4743 int i, first_table_num = tp->first_table_num;
4745 for (i = 0; i < tp->num_tables; i++) {
4746 struct rdc_table *tbl = &tp->tables[i];
4747 int this_table = first_table_num + i;
4750 for (slot = 0; slot < NIU_RDC_TABLE_SLOTS; slot++)
4751 nw64(RDC_TBL(this_table, slot),
4752 tbl->rxdma_channel[slot]);
4755 nw64(DEF_RDC(np->port), np->parent->rdc_default[np->port]);
4758 static void niu_init_drr_weight(struct niu *np)
4760 int type = phy_decode(np->parent->port_phy, np->port);
4765 val = PT_DRR_WEIGHT_DEFAULT_10G;
4770 val = PT_DRR_WEIGHT_DEFAULT_1G;
4773 nw64(PT_DRR_WT(np->port), val);
4776 static int niu_init_hostinfo(struct niu *np)
4778 struct niu_parent *parent = np->parent;
4779 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
4780 int i, err, num_alt = niu_num_alt_addr(np);
4781 int first_rdc_table = tp->first_table_num;
4783 err = niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
4787 err = niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
4791 for (i = 0; i < num_alt; i++) {
4792 err = niu_set_alt_mac_rdc_table(np, i, first_rdc_table, 1);
4800 static int niu_rx_channel_reset(struct niu *np, int channel)
4802 return niu_set_and_wait_clear(np, RXDMA_CFIG1(channel),
4803 RXDMA_CFIG1_RST, 1000, 10,
4807 static int niu_rx_channel_lpage_init(struct niu *np, int channel)
4811 nw64(RX_LOG_MASK1(channel), 0);
4812 nw64(RX_LOG_VAL1(channel), 0);
4813 nw64(RX_LOG_MASK2(channel), 0);
4814 nw64(RX_LOG_VAL2(channel), 0);
4815 nw64(RX_LOG_PAGE_RELO1(channel), 0);
4816 nw64(RX_LOG_PAGE_RELO2(channel), 0);
4817 nw64(RX_LOG_PAGE_HDL(channel), 0);
4819 val = (u64)np->port << RX_LOG_PAGE_VLD_FUNC_SHIFT;
4820 val |= (RX_LOG_PAGE_VLD_PAGE0 | RX_LOG_PAGE_VLD_PAGE1);
4821 nw64(RX_LOG_PAGE_VLD(channel), val);
4826 static void niu_rx_channel_wred_init(struct niu *np, struct rx_ring_info *rp)
4830 val = (((u64)rp->nonsyn_window << RDC_RED_PARA_WIN_SHIFT) |
4831 ((u64)rp->nonsyn_threshold << RDC_RED_PARA_THRE_SHIFT) |
4832 ((u64)rp->syn_window << RDC_RED_PARA_WIN_SYN_SHIFT) |
4833 ((u64)rp->syn_threshold << RDC_RED_PARA_THRE_SYN_SHIFT));
4834 nw64(RDC_RED_PARA(rp->rx_channel), val);
4837 static int niu_compute_rbr_cfig_b(struct rx_ring_info *rp, u64 *ret)
4842 switch (rp->rbr_block_size) {
4844 val |= (RBR_BLKSIZE_4K << RBR_CFIG_B_BLKSIZE_SHIFT);
4847 val |= (RBR_BLKSIZE_8K << RBR_CFIG_B_BLKSIZE_SHIFT);
4850 val |= (RBR_BLKSIZE_16K << RBR_CFIG_B_BLKSIZE_SHIFT);
4853 val |= (RBR_BLKSIZE_32K << RBR_CFIG_B_BLKSIZE_SHIFT);
4858 val |= RBR_CFIG_B_VLD2;
4859 switch (rp->rbr_sizes[2]) {
4861 val |= (RBR_BUFSZ2_2K << RBR_CFIG_B_BUFSZ2_SHIFT);
4864 val |= (RBR_BUFSZ2_4K << RBR_CFIG_B_BUFSZ2_SHIFT);
4867 val |= (RBR_BUFSZ2_8K << RBR_CFIG_B_BUFSZ2_SHIFT);
4870 val |= (RBR_BUFSZ2_16K << RBR_CFIG_B_BUFSZ2_SHIFT);
4876 val |= RBR_CFIG_B_VLD1;
4877 switch (rp->rbr_sizes[1]) {
4879 val |= (RBR_BUFSZ1_1K << RBR_CFIG_B_BUFSZ1_SHIFT);
4882 val |= (RBR_BUFSZ1_2K << RBR_CFIG_B_BUFSZ1_SHIFT);
4885 val |= (RBR_BUFSZ1_4K << RBR_CFIG_B_BUFSZ1_SHIFT);
4888 val |= (RBR_BUFSZ1_8K << RBR_CFIG_B_BUFSZ1_SHIFT);
4894 val |= RBR_CFIG_B_VLD0;
4895 switch (rp->rbr_sizes[0]) {
4897 val |= (RBR_BUFSZ0_256 << RBR_CFIG_B_BUFSZ0_SHIFT);
4900 val |= (RBR_BUFSZ0_512 << RBR_CFIG_B_BUFSZ0_SHIFT);
4903 val |= (RBR_BUFSZ0_1K << RBR_CFIG_B_BUFSZ0_SHIFT);
4906 val |= (RBR_BUFSZ0_2K << RBR_CFIG_B_BUFSZ0_SHIFT);
4917 static int niu_enable_rx_channel(struct niu *np, int channel, int on)
4919 u64 val = nr64(RXDMA_CFIG1(channel));
4923 val |= RXDMA_CFIG1_EN;
4925 val &= ~RXDMA_CFIG1_EN;
4926 nw64(RXDMA_CFIG1(channel), val);
4929 while (--limit > 0) {
4930 if (nr64(RXDMA_CFIG1(channel)) & RXDMA_CFIG1_QST)
4939 static int niu_init_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
4941 int err, channel = rp->rx_channel;
4944 err = niu_rx_channel_reset(np, channel);
4948 err = niu_rx_channel_lpage_init(np, channel);
4952 niu_rx_channel_wred_init(np, rp);
4954 nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_RBR_EMPTY);
4955 nw64(RX_DMA_CTL_STAT(channel),
4956 (RX_DMA_CTL_STAT_MEX |
4957 RX_DMA_CTL_STAT_RCRTHRES |
4958 RX_DMA_CTL_STAT_RCRTO |
4959 RX_DMA_CTL_STAT_RBR_EMPTY));
4960 nw64(RXDMA_CFIG1(channel), rp->mbox_dma >> 32);
4961 nw64(RXDMA_CFIG2(channel),
4962 ((rp->mbox_dma & RXDMA_CFIG2_MBADDR_L) |
4963 RXDMA_CFIG2_FULL_HDR));
4964 nw64(RBR_CFIG_A(channel),
4965 ((u64)rp->rbr_table_size << RBR_CFIG_A_LEN_SHIFT) |
4966 (rp->rbr_dma & (RBR_CFIG_A_STADDR_BASE | RBR_CFIG_A_STADDR)));
4967 err = niu_compute_rbr_cfig_b(rp, &val);
4970 nw64(RBR_CFIG_B(channel), val);
4971 nw64(RCRCFIG_A(channel),
4972 ((u64)rp->rcr_table_size << RCRCFIG_A_LEN_SHIFT) |
4973 (rp->rcr_dma & (RCRCFIG_A_STADDR_BASE | RCRCFIG_A_STADDR)));
4974 nw64(RCRCFIG_B(channel),
4975 ((u64)rp->rcr_pkt_threshold << RCRCFIG_B_PTHRES_SHIFT) |
4977 ((u64)rp->rcr_timeout << RCRCFIG_B_TIMEOUT_SHIFT));
4979 err = niu_enable_rx_channel(np, channel, 1);
4983 nw64(RBR_KICK(channel), rp->rbr_index);
4985 val = nr64(RX_DMA_CTL_STAT(channel));
4986 val |= RX_DMA_CTL_STAT_RBR_EMPTY;
4987 nw64(RX_DMA_CTL_STAT(channel), val);
4992 static int niu_init_rx_channels(struct niu *np)
4994 unsigned long flags;
4995 u64 seed = jiffies_64;
4998 niu_lock_parent(np, flags);
4999 nw64(RX_DMA_CK_DIV, np->parent->rxdma_clock_divider);
5000 nw64(RED_RAN_INIT, RED_RAN_INIT_OPMODE | (seed & RED_RAN_INIT_VAL));
5001 niu_unlock_parent(np, flags);
5003 /* XXX RXDMA 32bit mode? XXX */
5005 niu_init_rdc_groups(np);
5006 niu_init_drr_weight(np);
5008 err = niu_init_hostinfo(np);
5012 for (i = 0; i < np->num_rx_rings; i++) {
5013 struct rx_ring_info *rp = &np->rx_rings[i];
5015 err = niu_init_one_rx_channel(np, rp);
5023 static int niu_set_ip_frag_rule(struct niu *np)
5025 struct niu_parent *parent = np->parent;
5026 struct niu_classifier *cp = &np->clas;
5027 struct niu_tcam_entry *tp;
5030 index = cp->tcam_top;
5031 tp = &parent->tcam[index];
5033 /* Note that the noport bit is the same in both ipv4 and
5034 * ipv6 format TCAM entries.
5036 memset(tp, 0, sizeof(*tp));
5037 tp->key[1] = TCAM_V4KEY1_NOPORT;
5038 tp->key_mask[1] = TCAM_V4KEY1_NOPORT;
5039 tp->assoc_data = (TCAM_ASSOCDATA_TRES_USE_OFFSET |
5040 ((u64)0 << TCAM_ASSOCDATA_OFFSET_SHIFT));
5041 err = tcam_write(np, index, tp->key, tp->key_mask);
5044 err = tcam_assoc_write(np, index, tp->assoc_data);
5048 cp->tcam_valid_entries++;
5053 static int niu_init_classifier_hw(struct niu *np)
5055 struct niu_parent *parent = np->parent;
5056 struct niu_classifier *cp = &np->clas;
5059 nw64(H1POLY, cp->h1_init);
5060 nw64(H2POLY, cp->h2_init);
5062 err = niu_init_hostinfo(np);
5066 for (i = 0; i < ENET_VLAN_TBL_NUM_ENTRIES; i++) {
5067 struct niu_vlan_rdc *vp = &cp->vlan_mappings[i];
5069 vlan_tbl_write(np, i, np->port,
5070 vp->vlan_pref, vp->rdc_num);
5073 for (i = 0; i < cp->num_alt_mac_mappings; i++) {
5074 struct niu_altmac_rdc *ap = &cp->alt_mac_mappings[i];
5076 err = niu_set_alt_mac_rdc_table(np, ap->alt_mac_num,
5077 ap->rdc_num, ap->mac_pref);
5082 for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_SCTP_IPV6; i++) {
5083 int index = i - CLASS_CODE_USER_PROG1;
5085 err = niu_set_tcam_key(np, i, parent->tcam_key[index]);
5088 err = niu_set_flow_key(np, i, parent->flow_key[index]);
5093 err = niu_set_ip_frag_rule(np);
5102 static int niu_zcp_write(struct niu *np, int index, u64 *data)
5104 nw64(ZCP_RAM_DATA0, data[0]);
5105 nw64(ZCP_RAM_DATA1, data[1]);
5106 nw64(ZCP_RAM_DATA2, data[2]);
5107 nw64(ZCP_RAM_DATA3, data[3]);
5108 nw64(ZCP_RAM_DATA4, data[4]);
5109 nw64(ZCP_RAM_BE, ZCP_RAM_BE_VAL);
5111 (ZCP_RAM_ACC_WRITE |
5112 (0 << ZCP_RAM_ACC_ZFCID_SHIFT) |
5113 (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT)));
5115 return niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
5119 static int niu_zcp_read(struct niu *np, int index, u64 *data)
5123 err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
5126 netdev_err(np->dev, "ZCP read busy won't clear, ZCP_RAM_ACC[%llx]\n",
5127 (unsigned long long)nr64(ZCP_RAM_ACC));
5133 (0 << ZCP_RAM_ACC_ZFCID_SHIFT) |
5134 (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT)));
5136 err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
5139 netdev_err(np->dev, "ZCP read busy2 won't clear, ZCP_RAM_ACC[%llx]\n",
5140 (unsigned long long)nr64(ZCP_RAM_ACC));
5144 data[0] = nr64(ZCP_RAM_DATA0);
5145 data[1] = nr64(ZCP_RAM_DATA1);
5146 data[2] = nr64(ZCP_RAM_DATA2);
5147 data[3] = nr64(ZCP_RAM_DATA3);
5148 data[4] = nr64(ZCP_RAM_DATA4);
5153 static void niu_zcp_cfifo_reset(struct niu *np)
5155 u64 val = nr64(RESET_CFIFO);
5157 val |= RESET_CFIFO_RST(np->port);
5158 nw64(RESET_CFIFO, val);
5161 val &= ~RESET_CFIFO_RST(np->port);
5162 nw64(RESET_CFIFO, val);
5165 static int niu_init_zcp(struct niu *np)
5167 u64 data[5], rbuf[5];
5170 if (np->parent->plat_type != PLAT_TYPE_NIU) {
5171 if (np->port == 0 || np->port == 1)
5172 max = ATLAS_P0_P1_CFIFO_ENTRIES;
5174 max = ATLAS_P2_P3_CFIFO_ENTRIES;
5176 max = NIU_CFIFO_ENTRIES;
5184 for (i = 0; i < max; i++) {
5185 err = niu_zcp_write(np, i, data);
5188 err = niu_zcp_read(np, i, rbuf);
5193 niu_zcp_cfifo_reset(np);
5194 nw64(CFIFO_ECC(np->port), 0);
5195 nw64(ZCP_INT_STAT, ZCP_INT_STAT_ALL);
5196 (void) nr64(ZCP_INT_STAT);
5197 nw64(ZCP_INT_MASK, ZCP_INT_MASK_ALL);
5202 static void niu_ipp_write(struct niu *np, int index, u64 *data)
5204 u64 val = nr64_ipp(IPP_CFIG);
5206 nw64_ipp(IPP_CFIG, val | IPP_CFIG_DFIFO_PIO_W);
5207 nw64_ipp(IPP_DFIFO_WR_PTR, index);
5208 nw64_ipp(IPP_DFIFO_WR0, data[0]);
5209 nw64_ipp(IPP_DFIFO_WR1, data[1]);
5210 nw64_ipp(IPP_DFIFO_WR2, data[2]);
5211 nw64_ipp(IPP_DFIFO_WR3, data[3]);
5212 nw64_ipp(IPP_DFIFO_WR4, data[4]);
5213 nw64_ipp(IPP_CFIG, val & ~IPP_CFIG_DFIFO_PIO_W);
5216 static void niu_ipp_read(struct niu *np, int index, u64 *data)
5218 nw64_ipp(IPP_DFIFO_RD_PTR, index);
5219 data[0] = nr64_ipp(IPP_DFIFO_RD0);
5220 data[1] = nr64_ipp(IPP_DFIFO_RD1);
5221 data[2] = nr64_ipp(IPP_DFIFO_RD2);
5222 data[3] = nr64_ipp(IPP_DFIFO_RD3);
5223 data[4] = nr64_ipp(IPP_DFIFO_RD4);
5226 static int niu_ipp_reset(struct niu *np)
5228 return niu_set_and_wait_clear_ipp(np, IPP_CFIG, IPP_CFIG_SOFT_RST,
5229 1000, 100, "IPP_CFIG");
5232 static int niu_init_ipp(struct niu *np)
5234 u64 data[5], rbuf[5], val;
5237 if (np->parent->plat_type != PLAT_TYPE_NIU) {
5238 if (np->port == 0 || np->port == 1)
5239 max = ATLAS_P0_P1_DFIFO_ENTRIES;
5241 max = ATLAS_P2_P3_DFIFO_ENTRIES;
5243 max = NIU_DFIFO_ENTRIES;
5251 for (i = 0; i < max; i++) {
5252 niu_ipp_write(np, i, data);
5253 niu_ipp_read(np, i, rbuf);
5256 (void) nr64_ipp(IPP_INT_STAT);
5257 (void) nr64_ipp(IPP_INT_STAT);
5259 err = niu_ipp_reset(np);
5263 (void) nr64_ipp(IPP_PKT_DIS);
5264 (void) nr64_ipp(IPP_BAD_CS_CNT);
5265 (void) nr64_ipp(IPP_ECC);
5267 (void) nr64_ipp(IPP_INT_STAT);
5269 nw64_ipp(IPP_MSK, ~IPP_MSK_ALL);
5271 val = nr64_ipp(IPP_CFIG);
5272 val &= ~IPP_CFIG_IP_MAX_PKT;
5273 val |= (IPP_CFIG_IPP_ENABLE |
5274 IPP_CFIG_DFIFO_ECC_EN |
5275 IPP_CFIG_DROP_BAD_CRC |
5277 (0x1ffff << IPP_CFIG_IP_MAX_PKT_SHIFT));
5278 nw64_ipp(IPP_CFIG, val);
5283 static void niu_handle_led(struct niu *np, int status)
5286 val = nr64_mac(XMAC_CONFIG);
5288 if ((np->flags & NIU_FLAGS_10G) != 0 &&
5289 (np->flags & NIU_FLAGS_FIBER) != 0) {
5291 val |= XMAC_CONFIG_LED_POLARITY;
5292 val &= ~XMAC_CONFIG_FORCE_LED_ON;
5294 val |= XMAC_CONFIG_FORCE_LED_ON;
5295 val &= ~XMAC_CONFIG_LED_POLARITY;
5299 nw64_mac(XMAC_CONFIG, val);
5302 static void niu_init_xif_xmac(struct niu *np)
5304 struct niu_link_config *lp = &np->link_config;
5307 if (np->flags & NIU_FLAGS_XCVR_SERDES) {
5308 val = nr64(MIF_CONFIG);
5309 val |= MIF_CONFIG_ATCA_GE;
5310 nw64(MIF_CONFIG, val);
5313 val = nr64_mac(XMAC_CONFIG);
5314 val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC;
5316 val |= XMAC_CONFIG_TX_OUTPUT_EN;
5318 if (lp->loopback_mode == LOOPBACK_MAC) {
5319 val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC;
5320 val |= XMAC_CONFIG_LOOPBACK;
5322 val &= ~XMAC_CONFIG_LOOPBACK;
5325 if (np->flags & NIU_FLAGS_10G) {
5326 val &= ~XMAC_CONFIG_LFS_DISABLE;
5328 val |= XMAC_CONFIG_LFS_DISABLE;
5329 if (!(np->flags & NIU_FLAGS_FIBER) &&
5330 !(np->flags & NIU_FLAGS_XCVR_SERDES))
5331 val |= XMAC_CONFIG_1G_PCS_BYPASS;
5333 val &= ~XMAC_CONFIG_1G_PCS_BYPASS;
5336 val &= ~XMAC_CONFIG_10G_XPCS_BYPASS;
5338 if (lp->active_speed == SPEED_100)
5339 val |= XMAC_CONFIG_SEL_CLK_25MHZ;
5341 val &= ~XMAC_CONFIG_SEL_CLK_25MHZ;
5343 nw64_mac(XMAC_CONFIG, val);
5345 val = nr64_mac(XMAC_CONFIG);
5346 val &= ~XMAC_CONFIG_MODE_MASK;
5347 if (np->flags & NIU_FLAGS_10G) {
5348 val |= XMAC_CONFIG_MODE_XGMII;
5350 if (lp->active_speed == SPEED_1000)
5351 val |= XMAC_CONFIG_MODE_GMII;
5353 val |= XMAC_CONFIG_MODE_MII;
5356 nw64_mac(XMAC_CONFIG, val);
5359 static void niu_init_xif_bmac(struct niu *np)
5361 struct niu_link_config *lp = &np->link_config;
5364 val = BMAC_XIF_CONFIG_TX_OUTPUT_EN;
5366 if (lp->loopback_mode == LOOPBACK_MAC)
5367 val |= BMAC_XIF_CONFIG_MII_LOOPBACK;
5369 val &= ~BMAC_XIF_CONFIG_MII_LOOPBACK;
5371 if (lp->active_speed == SPEED_1000)
5372 val |= BMAC_XIF_CONFIG_GMII_MODE;
5374 val &= ~BMAC_XIF_CONFIG_GMII_MODE;
5376 val &= ~(BMAC_XIF_CONFIG_LINK_LED |
5377 BMAC_XIF_CONFIG_LED_POLARITY);
5379 if (!(np->flags & NIU_FLAGS_10G) &&
5380 !(np->flags & NIU_FLAGS_FIBER) &&
5381 lp->active_speed == SPEED_100)
5382 val |= BMAC_XIF_CONFIG_25MHZ_CLOCK;
5384 val &= ~BMAC_XIF_CONFIG_25MHZ_CLOCK;
5386 nw64_mac(BMAC_XIF_CONFIG, val);
5389 static void niu_init_xif(struct niu *np)
5391 if (np->flags & NIU_FLAGS_XMAC)
5392 niu_init_xif_xmac(np);
5394 niu_init_xif_bmac(np);
5397 static void niu_pcs_mii_reset(struct niu *np)
5400 u64 val = nr64_pcs(PCS_MII_CTL);
5401 val |= PCS_MII_CTL_RST;
5402 nw64_pcs(PCS_MII_CTL, val);
5403 while ((--limit >= 0) && (val & PCS_MII_CTL_RST)) {
5405 val = nr64_pcs(PCS_MII_CTL);
5409 static void niu_xpcs_reset(struct niu *np)
5412 u64 val = nr64_xpcs(XPCS_CONTROL1);
5413 val |= XPCS_CONTROL1_RESET;
5414 nw64_xpcs(XPCS_CONTROL1, val);
5415 while ((--limit >= 0) && (val & XPCS_CONTROL1_RESET)) {
5417 val = nr64_xpcs(XPCS_CONTROL1);
5421 static int niu_init_pcs(struct niu *np)
5423 struct niu_link_config *lp = &np->link_config;
5426 switch (np->flags & (NIU_FLAGS_10G |
5428 NIU_FLAGS_XCVR_SERDES)) {
5429 case NIU_FLAGS_FIBER:
5431 nw64_pcs(PCS_CONF, PCS_CONF_MASK | PCS_CONF_ENABLE);
5432 nw64_pcs(PCS_DPATH_MODE, 0);
5433 niu_pcs_mii_reset(np);
5437 case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
5438 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
5440 if (!(np->flags & NIU_FLAGS_XMAC))
5443 /* 10G copper or fiber */
5444 val = nr64_mac(XMAC_CONFIG);
5445 val &= ~XMAC_CONFIG_10G_XPCS_BYPASS;
5446 nw64_mac(XMAC_CONFIG, val);
5450 val = nr64_xpcs(XPCS_CONTROL1);
5451 if (lp->loopback_mode == LOOPBACK_PHY)
5452 val |= XPCS_CONTROL1_LOOPBACK;
5454 val &= ~XPCS_CONTROL1_LOOPBACK;
5455 nw64_xpcs(XPCS_CONTROL1, val);
5457 nw64_xpcs(XPCS_DESKEW_ERR_CNT, 0);
5458 (void) nr64_xpcs(XPCS_SYMERR_CNT01);
5459 (void) nr64_xpcs(XPCS_SYMERR_CNT23);
5463 case NIU_FLAGS_XCVR_SERDES:
5465 niu_pcs_mii_reset(np);
5466 nw64_pcs(PCS_CONF, PCS_CONF_MASK | PCS_CONF_ENABLE);
5467 nw64_pcs(PCS_DPATH_MODE, 0);
5472 case NIU_FLAGS_XCVR_SERDES | NIU_FLAGS_FIBER:
5473 /* 1G RGMII FIBER */
5474 nw64_pcs(PCS_DPATH_MODE, PCS_DPATH_MODE_MII);
5475 niu_pcs_mii_reset(np);
5485 static int niu_reset_tx_xmac(struct niu *np)
5487 return niu_set_and_wait_clear_mac(np, XTXMAC_SW_RST,
5488 (XTXMAC_SW_RST_REG_RS |
5489 XTXMAC_SW_RST_SOFT_RST),
5490 1000, 100, "XTXMAC_SW_RST");
5493 static int niu_reset_tx_bmac(struct niu *np)
5497 nw64_mac(BTXMAC_SW_RST, BTXMAC_SW_RST_RESET);
5499 while (--limit >= 0) {
5500 if (!(nr64_mac(BTXMAC_SW_RST) & BTXMAC_SW_RST_RESET))
5505 dev_err(np->device, "Port %u TX BMAC would not reset, BTXMAC_SW_RST[%llx]\n",
5507 (unsigned long long) nr64_mac(BTXMAC_SW_RST));
5514 static int niu_reset_tx_mac(struct niu *np)
5516 if (np->flags & NIU_FLAGS_XMAC)
5517 return niu_reset_tx_xmac(np);
5519 return niu_reset_tx_bmac(np);
5522 static void niu_init_tx_xmac(struct niu *np, u64 min, u64 max)
5526 val = nr64_mac(XMAC_MIN);
5527 val &= ~(XMAC_MIN_TX_MIN_PKT_SIZE |
5528 XMAC_MIN_RX_MIN_PKT_SIZE);
5529 val |= (min << XMAC_MIN_RX_MIN_PKT_SIZE_SHFT);
5530 val |= (min << XMAC_MIN_TX_MIN_PKT_SIZE_SHFT);
5531 nw64_mac(XMAC_MIN, val);
5533 nw64_mac(XMAC_MAX, max);
5535 nw64_mac(XTXMAC_STAT_MSK, ~(u64)0);
5537 val = nr64_mac(XMAC_IPG);
5538 if (np->flags & NIU_FLAGS_10G) {
5539 val &= ~XMAC_IPG_IPG_XGMII;
5540 val |= (IPG_12_15_XGMII << XMAC_IPG_IPG_XGMII_SHIFT);
5542 val &= ~XMAC_IPG_IPG_MII_GMII;
5543 val |= (IPG_12_MII_GMII << XMAC_IPG_IPG_MII_GMII_SHIFT);
5545 nw64_mac(XMAC_IPG, val);
5547 val = nr64_mac(XMAC_CONFIG);
5548 val &= ~(XMAC_CONFIG_ALWAYS_NO_CRC |
5549 XMAC_CONFIG_STRETCH_MODE |
5550 XMAC_CONFIG_VAR_MIN_IPG_EN |
5551 XMAC_CONFIG_TX_ENABLE);
5552 nw64_mac(XMAC_CONFIG, val);
5554 nw64_mac(TXMAC_FRM_CNT, 0);
5555 nw64_mac(TXMAC_BYTE_CNT, 0);
5558 static void niu_init_tx_bmac(struct niu *np, u64 min, u64 max)
5562 nw64_mac(BMAC_MIN_FRAME, min);
5563 nw64_mac(BMAC_MAX_FRAME, max);
5565 nw64_mac(BTXMAC_STATUS_MASK, ~(u64)0);
5566 nw64_mac(BMAC_CTRL_TYPE, 0x8808);
5567 nw64_mac(BMAC_PREAMBLE_SIZE, 7);
5569 val = nr64_mac(BTXMAC_CONFIG);
5570 val &= ~(BTXMAC_CONFIG_FCS_DISABLE |
5571 BTXMAC_CONFIG_ENABLE);
5572 nw64_mac(BTXMAC_CONFIG, val);
5575 static void niu_init_tx_mac(struct niu *np)
5580 if (np->dev->mtu > ETH_DATA_LEN)
5585 /* The XMAC_MIN register only accepts values for TX min which
5586 * have the low 3 bits cleared.
5590 if (np->flags & NIU_FLAGS_XMAC)
5591 niu_init_tx_xmac(np, min, max);
5593 niu_init_tx_bmac(np, min, max);
5596 static int niu_reset_rx_xmac(struct niu *np)
5600 nw64_mac(XRXMAC_SW_RST,
5601 XRXMAC_SW_RST_REG_RS | XRXMAC_SW_RST_SOFT_RST);
5603 while (--limit >= 0) {
5604 if (!(nr64_mac(XRXMAC_SW_RST) & (XRXMAC_SW_RST_REG_RS |
5605 XRXMAC_SW_RST_SOFT_RST)))
5610 dev_err(np->device, "Port %u RX XMAC would not reset, XRXMAC_SW_RST[%llx]\n",
5612 (unsigned long long) nr64_mac(XRXMAC_SW_RST));
5619 static int niu_reset_rx_bmac(struct niu *np)
5623 nw64_mac(BRXMAC_SW_RST, BRXMAC_SW_RST_RESET);
5625 while (--limit >= 0) {
5626 if (!(nr64_mac(BRXMAC_SW_RST) & BRXMAC_SW_RST_RESET))
5631 dev_err(np->device, "Port %u RX BMAC would not reset, BRXMAC_SW_RST[%llx]\n",
5633 (unsigned long long) nr64_mac(BRXMAC_SW_RST));
5640 static int niu_reset_rx_mac(struct niu *np)
5642 if (np->flags & NIU_FLAGS_XMAC)
5643 return niu_reset_rx_xmac(np);
5645 return niu_reset_rx_bmac(np);
5648 static void niu_init_rx_xmac(struct niu *np)
5650 struct niu_parent *parent = np->parent;
5651 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
5652 int first_rdc_table = tp->first_table_num;
5656 nw64_mac(XMAC_ADD_FILT0, 0);
5657 nw64_mac(XMAC_ADD_FILT1, 0);
5658 nw64_mac(XMAC_ADD_FILT2, 0);
5659 nw64_mac(XMAC_ADD_FILT12_MASK, 0);
5660 nw64_mac(XMAC_ADD_FILT00_MASK, 0);
5661 for (i = 0; i < MAC_NUM_HASH; i++)
5662 nw64_mac(XMAC_HASH_TBL(i), 0);
5663 nw64_mac(XRXMAC_STAT_MSK, ~(u64)0);
5664 niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
5665 niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
5667 val = nr64_mac(XMAC_CONFIG);
5668 val &= ~(XMAC_CONFIG_RX_MAC_ENABLE |
5669 XMAC_CONFIG_PROMISCUOUS |
5670 XMAC_CONFIG_PROMISC_GROUP |
5671 XMAC_CONFIG_ERR_CHK_DIS |
5672 XMAC_CONFIG_RX_CRC_CHK_DIS |
5673 XMAC_CONFIG_RESERVED_MULTICAST |
5674 XMAC_CONFIG_RX_CODEV_CHK_DIS |
5675 XMAC_CONFIG_ADDR_FILTER_EN |
5676 XMAC_CONFIG_RCV_PAUSE_ENABLE |
5677 XMAC_CONFIG_STRIP_CRC |
5678 XMAC_CONFIG_PASS_FLOW_CTRL |
5679 XMAC_CONFIG_MAC2IPP_PKT_CNT_EN);
5680 val |= (XMAC_CONFIG_HASH_FILTER_EN);
5681 nw64_mac(XMAC_CONFIG, val);
5683 nw64_mac(RXMAC_BT_CNT, 0);
5684 nw64_mac(RXMAC_BC_FRM_CNT, 0);
5685 nw64_mac(RXMAC_MC_FRM_CNT, 0);
5686 nw64_mac(RXMAC_FRAG_CNT, 0);
5687 nw64_mac(RXMAC_HIST_CNT1, 0);
5688 nw64_mac(RXMAC_HIST_CNT2, 0);
5689 nw64_mac(RXMAC_HIST_CNT3, 0);
5690 nw64_mac(RXMAC_HIST_CNT4, 0);
5691 nw64_mac(RXMAC_HIST_CNT5, 0);
5692 nw64_mac(RXMAC_HIST_CNT6, 0);
5693 nw64_mac(RXMAC_HIST_CNT7, 0);
5694 nw64_mac(RXMAC_MPSZER_CNT, 0);
5695 nw64_mac(RXMAC_CRC_ER_CNT, 0);
5696 nw64_mac(RXMAC_CD_VIO_CNT, 0);
5697 nw64_mac(LINK_FAULT_CNT, 0);
5700 static void niu_init_rx_bmac(struct niu *np)
5702 struct niu_parent *parent = np->parent;
5703 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
5704 int first_rdc_table = tp->first_table_num;
5708 nw64_mac(BMAC_ADD_FILT0, 0);
5709 nw64_mac(BMAC_ADD_FILT1, 0);
5710 nw64_mac(BMAC_ADD_FILT2, 0);
5711 nw64_mac(BMAC_ADD_FILT12_MASK, 0);
5712 nw64_mac(BMAC_ADD_FILT00_MASK, 0);
5713 for (i = 0; i < MAC_NUM_HASH; i++)
5714 nw64_mac(BMAC_HASH_TBL(i), 0);
5715 niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
5716 niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
5717 nw64_mac(BRXMAC_STATUS_MASK, ~(u64)0);
5719 val = nr64_mac(BRXMAC_CONFIG);
5720 val &= ~(BRXMAC_CONFIG_ENABLE |
5721 BRXMAC_CONFIG_STRIP_PAD |
5722 BRXMAC_CONFIG_STRIP_FCS |
5723 BRXMAC_CONFIG_PROMISC |
5724 BRXMAC_CONFIG_PROMISC_GRP |
5725 BRXMAC_CONFIG_ADDR_FILT_EN |
5726 BRXMAC_CONFIG_DISCARD_DIS);
5727 val |= (BRXMAC_CONFIG_HASH_FILT_EN);
5728 nw64_mac(BRXMAC_CONFIG, val);
5730 val = nr64_mac(BMAC_ADDR_CMPEN);
5731 val |= BMAC_ADDR_CMPEN_EN0;
5732 nw64_mac(BMAC_ADDR_CMPEN, val);
5735 static void niu_init_rx_mac(struct niu *np)
5737 niu_set_primary_mac(np, np->dev->dev_addr);
5739 if (np->flags & NIU_FLAGS_XMAC)
5740 niu_init_rx_xmac(np);
5742 niu_init_rx_bmac(np);
5745 static void niu_enable_tx_xmac(struct niu *np, int on)
5747 u64 val = nr64_mac(XMAC_CONFIG);
5750 val |= XMAC_CONFIG_TX_ENABLE;
5752 val &= ~XMAC_CONFIG_TX_ENABLE;
5753 nw64_mac(XMAC_CONFIG, val);
5756 static void niu_enable_tx_bmac(struct niu *np, int on)
5758 u64 val = nr64_mac(BTXMAC_CONFIG);
5761 val |= BTXMAC_CONFIG_ENABLE;
5763 val &= ~BTXMAC_CONFIG_ENABLE;
5764 nw64_mac(BTXMAC_CONFIG, val);
5767 static void niu_enable_tx_mac(struct niu *np, int on)
5769 if (np->flags & NIU_FLAGS_XMAC)
5770 niu_enable_tx_xmac(np, on);
5772 niu_enable_tx_bmac(np, on);
5775 static void niu_enable_rx_xmac(struct niu *np, int on)
5777 u64 val = nr64_mac(XMAC_CONFIG);
5779 val &= ~(XMAC_CONFIG_HASH_FILTER_EN |
5780 XMAC_CONFIG_PROMISCUOUS);
5782 if (np->flags & NIU_FLAGS_MCAST)
5783 val |= XMAC_CONFIG_HASH_FILTER_EN;
5784 if (np->flags & NIU_FLAGS_PROMISC)
5785 val |= XMAC_CONFIG_PROMISCUOUS;
5788 val |= XMAC_CONFIG_RX_MAC_ENABLE;
5790 val &= ~XMAC_CONFIG_RX_MAC_ENABLE;
5791 nw64_mac(XMAC_CONFIG, val);
5794 static void niu_enable_rx_bmac(struct niu *np, int on)
5796 u64 val = nr64_mac(BRXMAC_CONFIG);
5798 val &= ~(BRXMAC_CONFIG_HASH_FILT_EN |
5799 BRXMAC_CONFIG_PROMISC);
5801 if (np->flags & NIU_FLAGS_MCAST)
5802 val |= BRXMAC_CONFIG_HASH_FILT_EN;
5803 if (np->flags & NIU_FLAGS_PROMISC)
5804 val |= BRXMAC_CONFIG_PROMISC;
5807 val |= BRXMAC_CONFIG_ENABLE;
5809 val &= ~BRXMAC_CONFIG_ENABLE;
5810 nw64_mac(BRXMAC_CONFIG, val);
5813 static void niu_enable_rx_mac(struct niu *np, int on)
5815 if (np->flags & NIU_FLAGS_XMAC)
5816 niu_enable_rx_xmac(np, on);
5818 niu_enable_rx_bmac(np, on);
5821 static int niu_init_mac(struct niu *np)
5826 err = niu_init_pcs(np);
5830 err = niu_reset_tx_mac(np);
5833 niu_init_tx_mac(np);
5834 err = niu_reset_rx_mac(np);
5837 niu_init_rx_mac(np);
5839 /* This looks hookey but the RX MAC reset we just did will
5840 * undo some of the state we setup in niu_init_tx_mac() so we
5841 * have to call it again. In particular, the RX MAC reset will
5842 * set the XMAC_MAX register back to it's default value.
5844 niu_init_tx_mac(np);
5845 niu_enable_tx_mac(np, 1);
5847 niu_enable_rx_mac(np, 1);
5852 static void niu_stop_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
5854 (void) niu_tx_channel_stop(np, rp->tx_channel);
5857 static void niu_stop_tx_channels(struct niu *np)
5861 for (i = 0; i < np->num_tx_rings; i++) {
5862 struct tx_ring_info *rp = &np->tx_rings[i];
5864 niu_stop_one_tx_channel(np, rp);
5868 static void niu_reset_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
5870 (void) niu_tx_channel_reset(np, rp->tx_channel);
5873 static void niu_reset_tx_channels(struct niu *np)
5877 for (i = 0; i < np->num_tx_rings; i++) {
5878 struct tx_ring_info *rp = &np->tx_rings[i];
5880 niu_reset_one_tx_channel(np, rp);
5884 static void niu_stop_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
5886 (void) niu_enable_rx_channel(np, rp->rx_channel, 0);
5889 static void niu_stop_rx_channels(struct niu *np)
5893 for (i = 0; i < np->num_rx_rings; i++) {
5894 struct rx_ring_info *rp = &np->rx_rings[i];
5896 niu_stop_one_rx_channel(np, rp);
5900 static void niu_reset_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
5902 int channel = rp->rx_channel;
5904 (void) niu_rx_channel_reset(np, channel);
5905 nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_ALL);
5906 nw64(RX_DMA_CTL_STAT(channel), 0);
5907 (void) niu_enable_rx_channel(np, channel, 0);
5910 static void niu_reset_rx_channels(struct niu *np)
5914 for (i = 0; i < np->num_rx_rings; i++) {
5915 struct rx_ring_info *rp = &np->rx_rings[i];
5917 niu_reset_one_rx_channel(np, rp);
5921 static void niu_disable_ipp(struct niu *np)
5926 rd = nr64_ipp(IPP_DFIFO_RD_PTR);
5927 wr = nr64_ipp(IPP_DFIFO_WR_PTR);
5929 while (--limit >= 0 && (rd != wr)) {
5930 rd = nr64_ipp(IPP_DFIFO_RD_PTR);
5931 wr = nr64_ipp(IPP_DFIFO_WR_PTR);
5934 (rd != 0 && wr != 1)) {
5935 netdev_err(np->dev, "IPP would not quiesce, rd_ptr[%llx] wr_ptr[%llx]\n",
5936 (unsigned long long)nr64_ipp(IPP_DFIFO_RD_PTR),
5937 (unsigned long long)nr64_ipp(IPP_DFIFO_WR_PTR));
5940 val = nr64_ipp(IPP_CFIG);
5941 val &= ~(IPP_CFIG_IPP_ENABLE |
5942 IPP_CFIG_DFIFO_ECC_EN |
5943 IPP_CFIG_DROP_BAD_CRC |
5945 nw64_ipp(IPP_CFIG, val);
5947 (void) niu_ipp_reset(np);
5950 static int niu_init_hw(struct niu *np)
5954 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize TXC\n");
5955 niu_txc_enable_port(np, 1);
5956 niu_txc_port_dma_enable(np, 1);
5957 niu_txc_set_imask(np, 0);
5959 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize TX channels\n");
5960 for (i = 0; i < np->num_tx_rings; i++) {
5961 struct tx_ring_info *rp = &np->tx_rings[i];
5963 err = niu_init_one_tx_channel(np, rp);
5968 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize RX channels\n");
5969 err = niu_init_rx_channels(np);
5971 goto out_uninit_tx_channels;
5973 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize classifier\n");
5974 err = niu_init_classifier_hw(np);
5976 goto out_uninit_rx_channels;
5978 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize ZCP\n");
5979 err = niu_init_zcp(np);
5981 goto out_uninit_rx_channels;
5983 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize IPP\n");
5984 err = niu_init_ipp(np);
5986 goto out_uninit_rx_channels;
5988 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize MAC\n");
5989 err = niu_init_mac(np);
5991 goto out_uninit_ipp;
5996 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Uninit IPP\n");
5997 niu_disable_ipp(np);
5999 out_uninit_rx_channels:
6000 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Uninit RX channels\n");
6001 niu_stop_rx_channels(np);
6002 niu_reset_rx_channels(np);
6004 out_uninit_tx_channels:
6005 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Uninit TX channels\n");
6006 niu_stop_tx_channels(np);
6007 niu_reset_tx_channels(np);
6012 static void niu_stop_hw(struct niu *np)
6014 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Disable interrupts\n");
6015 niu_enable_interrupts(np, 0);
6017 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Disable RX MAC\n");
6018 niu_enable_rx_mac(np, 0);
6020 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Disable IPP\n");
6021 niu_disable_ipp(np);
6023 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Stop TX channels\n");
6024 niu_stop_tx_channels(np);
6026 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Stop RX channels\n");
6027 niu_stop_rx_channels(np);
6029 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Reset TX channels\n");
6030 niu_reset_tx_channels(np);
6032 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Reset RX channels\n");
6033 niu_reset_rx_channels(np);
6036 static void niu_set_irq_name(struct niu *np)
6038 int port = np->port;
6041 sprintf(np->irq_name[0], "%s:MAC", np->dev->name);
6044 sprintf(np->irq_name[1], "%s:MIF", np->dev->name);
6045 sprintf(np->irq_name[2], "%s:SYSERR", np->dev->name);
6049 for (i = 0; i < np->num_ldg - j; i++) {
6050 if (i < np->num_rx_rings)
6051 sprintf(np->irq_name[i+j], "%s-rx-%d",
6053 else if (i < np->num_tx_rings + np->num_rx_rings)
6054 sprintf(np->irq_name[i+j], "%s-tx-%d", np->dev->name,
6055 i - np->num_rx_rings);
6059 static int niu_request_irq(struct niu *np)
6063 niu_set_irq_name(np);
6066 for (i = 0; i < np->num_ldg; i++) {
6067 struct niu_ldg *lp = &np->ldg[i];
6069 err = request_irq(lp->irq, niu_interrupt, IRQF_SHARED,
6070 np->irq_name[i], lp);
6079 for (j = 0; j < i; j++) {
6080 struct niu_ldg *lp = &np->ldg[j];
6082 free_irq(lp->irq, lp);
6087 static void niu_free_irq(struct niu *np)
6091 for (i = 0; i < np->num_ldg; i++) {
6092 struct niu_ldg *lp = &np->ldg[i];
6094 free_irq(lp->irq, lp);
6098 static void niu_enable_napi(struct niu *np)
6102 for (i = 0; i < np->num_ldg; i++)
6103 napi_enable(&np->ldg[i].napi);
6106 static void niu_disable_napi(struct niu *np)
6110 for (i = 0; i < np->num_ldg; i++)
6111 napi_disable(&np->ldg[i].napi);
6114 static int niu_open(struct net_device *dev)
6116 struct niu *np = netdev_priv(dev);
6119 netif_carrier_off(dev);
6121 err = niu_alloc_channels(np);
6125 err = niu_enable_interrupts(np, 0);
6127 goto out_free_channels;
6129 err = niu_request_irq(np);
6131 goto out_free_channels;
6133 niu_enable_napi(np);
6135 spin_lock_irq(&np->lock);
6137 err = niu_init_hw(np);
6139 init_timer(&np->timer);
6140 np->timer.expires = jiffies + HZ;
6141 np->timer.data = (unsigned long) np;
6142 np->timer.function = niu_timer;
6144 err = niu_enable_interrupts(np, 1);
6149 spin_unlock_irq(&np->lock);
6152 niu_disable_napi(np);
6156 netif_tx_start_all_queues(dev);
6158 if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
6159 netif_carrier_on(dev);
6161 add_timer(&np->timer);
6169 niu_free_channels(np);
6175 static void niu_full_shutdown(struct niu *np, struct net_device *dev)
6177 cancel_work_sync(&np->reset_task);
6179 niu_disable_napi(np);
6180 netif_tx_stop_all_queues(dev);
6182 del_timer_sync(&np->timer);
6184 spin_lock_irq(&np->lock);
6188 spin_unlock_irq(&np->lock);
6191 static int niu_close(struct net_device *dev)
6193 struct niu *np = netdev_priv(dev);
6195 niu_full_shutdown(np, dev);
6199 niu_free_channels(np);
6201 niu_handle_led(np, 0);
6206 static void niu_sync_xmac_stats(struct niu *np)
6208 struct niu_xmac_stats *mp = &np->mac_stats.xmac;
6210 mp->tx_frames += nr64_mac(TXMAC_FRM_CNT);
6211 mp->tx_bytes += nr64_mac(TXMAC_BYTE_CNT);
6213 mp->rx_link_faults += nr64_mac(LINK_FAULT_CNT);
6214 mp->rx_align_errors += nr64_mac(RXMAC_ALIGN_ERR_CNT);
6215 mp->rx_frags += nr64_mac(RXMAC_FRAG_CNT);
6216 mp->rx_mcasts += nr64_mac(RXMAC_MC_FRM_CNT);
6217 mp->rx_bcasts += nr64_mac(RXMAC_BC_FRM_CNT);
6218 mp->rx_hist_cnt1 += nr64_mac(RXMAC_HIST_CNT1);
6219 mp->rx_hist_cnt2 += nr64_mac(RXMAC_HIST_CNT2);
6220 mp->rx_hist_cnt3 += nr64_mac(RXMAC_HIST_CNT3);
6221 mp->rx_hist_cnt4 += nr64_mac(RXMAC_HIST_CNT4);
6222 mp->rx_hist_cnt5 += nr64_mac(RXMAC_HIST_CNT5);
6223 mp->rx_hist_cnt6 += nr64_mac(RXMAC_HIST_CNT6);
6224 mp->rx_hist_cnt7 += nr64_mac(RXMAC_HIST_CNT7);
6225 mp->rx_octets += nr64_mac(RXMAC_BT_CNT);
6226 mp->rx_code_violations += nr64_mac(RXMAC_CD_VIO_CNT);
6227 mp->rx_len_errors += nr64_mac(RXMAC_MPSZER_CNT);
6228 mp->rx_crc_errors += nr64_mac(RXMAC_CRC_ER_CNT);
6231 static void niu_sync_bmac_stats(struct niu *np)
6233 struct niu_bmac_stats *mp = &np->mac_stats.bmac;
6235 mp->tx_bytes += nr64_mac(BTXMAC_BYTE_CNT);
6236 mp->tx_frames += nr64_mac(BTXMAC_FRM_CNT);
6238 mp->rx_frames += nr64_mac(BRXMAC_FRAME_CNT);
6239 mp->rx_align_errors += nr64_mac(BRXMAC_ALIGN_ERR_CNT);
6240 mp->rx_crc_errors += nr64_mac(BRXMAC_ALIGN_ERR_CNT);
6241 mp->rx_len_errors += nr64_mac(BRXMAC_CODE_VIOL_ERR_CNT);
6244 static void niu_sync_mac_stats(struct niu *np)
6246 if (np->flags & NIU_FLAGS_XMAC)
6247 niu_sync_xmac_stats(np);
6249 niu_sync_bmac_stats(np);
6252 static void niu_get_rx_stats(struct niu *np,
6253 struct rtnl_link_stats64 *stats)
6255 u64 pkts, dropped, errors, bytes;
6256 struct rx_ring_info *rx_rings;
6259 pkts = dropped = errors = bytes = 0;
6261 rx_rings = ACCESS_ONCE(np->rx_rings);
6265 for (i = 0; i < np->num_rx_rings; i++) {
6266 struct rx_ring_info *rp = &rx_rings[i];
6268 niu_sync_rx_discard_stats(np, rp, 0);
6270 pkts += rp->rx_packets;
6271 bytes += rp->rx_bytes;
6272 dropped += rp->rx_dropped;
6273 errors += rp->rx_errors;
6277 stats->rx_packets = pkts;
6278 stats->rx_bytes = bytes;
6279 stats->rx_dropped = dropped;
6280 stats->rx_errors = errors;
6283 static void niu_get_tx_stats(struct niu *np,
6284 struct rtnl_link_stats64 *stats)
6286 u64 pkts, errors, bytes;
6287 struct tx_ring_info *tx_rings;
6290 pkts = errors = bytes = 0;
6292 tx_rings = ACCESS_ONCE(np->tx_rings);
6296 for (i = 0; i < np->num_tx_rings; i++) {
6297 struct tx_ring_info *rp = &tx_rings[i];
6299 pkts += rp->tx_packets;
6300 bytes += rp->tx_bytes;
6301 errors += rp->tx_errors;
6305 stats->tx_packets = pkts;
6306 stats->tx_bytes = bytes;
6307 stats->tx_errors = errors;
6310 static struct rtnl_link_stats64 *niu_get_stats(struct net_device *dev,
6311 struct rtnl_link_stats64 *stats)
6313 struct niu *np = netdev_priv(dev);
6315 if (netif_running(dev)) {
6316 niu_get_rx_stats(np, stats);
6317 niu_get_tx_stats(np, stats);
6323 static void niu_load_hash_xmac(struct niu *np, u16 *hash)
6327 for (i = 0; i < 16; i++)
6328 nw64_mac(XMAC_HASH_TBL(i), hash[i]);
6331 static void niu_load_hash_bmac(struct niu *np, u16 *hash)
6335 for (i = 0; i < 16; i++)
6336 nw64_mac(BMAC_HASH_TBL(i), hash[i]);
6339 static void niu_load_hash(struct niu *np, u16 *hash)
6341 if (np->flags & NIU_FLAGS_XMAC)
6342 niu_load_hash_xmac(np, hash);
6344 niu_load_hash_bmac(np, hash);
6347 static void niu_set_rx_mode(struct net_device *dev)
6349 struct niu *np = netdev_priv(dev);
6350 int i, alt_cnt, err;
6351 struct netdev_hw_addr *ha;
6352 unsigned long flags;
6353 u16 hash[16] = { 0, };
6355 spin_lock_irqsave(&np->lock, flags);
6356 niu_enable_rx_mac(np, 0);
6358 np->flags &= ~(NIU_FLAGS_MCAST | NIU_FLAGS_PROMISC);
6359 if (dev->flags & IFF_PROMISC)
6360 np->flags |= NIU_FLAGS_PROMISC;
6361 if ((dev->flags & IFF_ALLMULTI) || (!netdev_mc_empty(dev)))
6362 np->flags |= NIU_FLAGS_MCAST;
6364 alt_cnt = netdev_uc_count(dev);
6365 if (alt_cnt > niu_num_alt_addr(np)) {
6367 np->flags |= NIU_FLAGS_PROMISC;
6373 netdev_for_each_uc_addr(ha, dev) {
6374 err = niu_set_alt_mac(np, index, ha->addr);
6376 netdev_warn(dev, "Error %d adding alt mac %d\n",
6378 err = niu_enable_alt_mac(np, index, 1);
6380 netdev_warn(dev, "Error %d enabling alt mac %d\n",
6387 if (np->flags & NIU_FLAGS_XMAC)
6391 for (i = alt_start; i < niu_num_alt_addr(np); i++) {
6392 err = niu_enable_alt_mac(np, i, 0);
6394 netdev_warn(dev, "Error %d disabling alt mac %d\n",
6398 if (dev->flags & IFF_ALLMULTI) {
6399 for (i = 0; i < 16; i++)
6401 } else if (!netdev_mc_empty(dev)) {
6402 netdev_for_each_mc_addr(ha, dev) {
6403 u32 crc = ether_crc_le(ETH_ALEN, ha->addr);
6406 hash[crc >> 4] |= (1 << (15 - (crc & 0xf)));
6410 if (np->flags & NIU_FLAGS_MCAST)
6411 niu_load_hash(np, hash);
6413 niu_enable_rx_mac(np, 1);
6414 spin_unlock_irqrestore(&np->lock, flags);
6417 static int niu_set_mac_addr(struct net_device *dev, void *p)
6419 struct niu *np = netdev_priv(dev);
6420 struct sockaddr *addr = p;
6421 unsigned long flags;
6423 if (!is_valid_ether_addr(addr->sa_data))
6426 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
6428 if (!netif_running(dev))
6431 spin_lock_irqsave(&np->lock, flags);
6432 niu_enable_rx_mac(np, 0);
6433 niu_set_primary_mac(np, dev->dev_addr);
6434 niu_enable_rx_mac(np, 1);
6435 spin_unlock_irqrestore(&np->lock, flags);
6440 static int niu_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
6445 static void niu_netif_stop(struct niu *np)
6447 np->dev->trans_start = jiffies; /* prevent tx timeout */
6449 niu_disable_napi(np);
6451 netif_tx_disable(np->dev);
6454 static void niu_netif_start(struct niu *np)
6456 /* NOTE: unconditional netif_wake_queue is only appropriate
6457 * so long as all callers are assured to have free tx slots
6458 * (such as after niu_init_hw).
6460 netif_tx_wake_all_queues(np->dev);
6462 niu_enable_napi(np);
6464 niu_enable_interrupts(np, 1);
6467 static void niu_reset_buffers(struct niu *np)
6472 for (i = 0; i < np->num_rx_rings; i++) {
6473 struct rx_ring_info *rp = &np->rx_rings[i];
6475 for (j = 0, k = 0; j < MAX_RBR_RING_SIZE; j++) {
6478 page = rp->rxhash[j];
6481 (struct page *) page->mapping;
6482 u64 base = page->index;
6483 base = base >> RBR_DESCR_ADDR_SHIFT;
6484 rp->rbr[k++] = cpu_to_le32(base);
6488 for (; k < MAX_RBR_RING_SIZE; k++) {
6489 err = niu_rbr_add_page(np, rp, GFP_ATOMIC, k);
6494 rp->rbr_index = rp->rbr_table_size - 1;
6496 rp->rbr_pending = 0;
6497 rp->rbr_refill_pending = 0;
6501 for (i = 0; i < np->num_tx_rings; i++) {
6502 struct tx_ring_info *rp = &np->tx_rings[i];
6504 for (j = 0; j < MAX_TX_RING_SIZE; j++) {
6505 if (rp->tx_buffs[j].skb)
6506 (void) release_tx_packet(np, rp, j);
6509 rp->pending = MAX_TX_RING_SIZE;
6517 static void niu_reset_task(struct work_struct *work)
6519 struct niu *np = container_of(work, struct niu, reset_task);
6520 unsigned long flags;
6523 spin_lock_irqsave(&np->lock, flags);
6524 if (!netif_running(np->dev)) {
6525 spin_unlock_irqrestore(&np->lock, flags);
6529 spin_unlock_irqrestore(&np->lock, flags);
6531 del_timer_sync(&np->timer);
6535 spin_lock_irqsave(&np->lock, flags);
6539 spin_unlock_irqrestore(&np->lock, flags);
6541 niu_reset_buffers(np);
6543 spin_lock_irqsave(&np->lock, flags);
6545 err = niu_init_hw(np);
6547 np->timer.expires = jiffies + HZ;
6548 add_timer(&np->timer);
6549 niu_netif_start(np);
6552 spin_unlock_irqrestore(&np->lock, flags);
6555 static void niu_tx_timeout(struct net_device *dev)
6557 struct niu *np = netdev_priv(dev);
6559 dev_err(np->device, "%s: Transmit timed out, resetting\n",
6562 schedule_work(&np->reset_task);
6565 static void niu_set_txd(struct tx_ring_info *rp, int index,
6566 u64 mapping, u64 len, u64 mark,
6569 __le64 *desc = &rp->descr[index];
6571 *desc = cpu_to_le64(mark |
6572 (n_frags << TX_DESC_NUM_PTR_SHIFT) |
6573 (len << TX_DESC_TR_LEN_SHIFT) |
6574 (mapping & TX_DESC_SAD));
6577 static u64 niu_compute_tx_flags(struct sk_buff *skb, struct ethhdr *ehdr,
6578 u64 pad_bytes, u64 len)
6580 u16 eth_proto, eth_proto_inner;
6581 u64 csum_bits, l3off, ihl, ret;
6585 eth_proto = be16_to_cpu(ehdr->h_proto);
6586 eth_proto_inner = eth_proto;
6587 if (eth_proto == ETH_P_8021Q) {
6588 struct vlan_ethhdr *vp = (struct vlan_ethhdr *) ehdr;
6589 __be16 val = vp->h_vlan_encapsulated_proto;
6591 eth_proto_inner = be16_to_cpu(val);
6595 switch (skb->protocol) {
6596 case cpu_to_be16(ETH_P_IP):
6597 ip_proto = ip_hdr(skb)->protocol;
6598 ihl = ip_hdr(skb)->ihl;
6600 case cpu_to_be16(ETH_P_IPV6):
6601 ip_proto = ipv6_hdr(skb)->nexthdr;
6610 csum_bits = TXHDR_CSUM_NONE;
6611 if (skb->ip_summed == CHECKSUM_PARTIAL) {
6614 csum_bits = (ip_proto == IPPROTO_TCP ?
6616 (ip_proto == IPPROTO_UDP ?
6617 TXHDR_CSUM_UDP : TXHDR_CSUM_SCTP));
6619 start = skb_checksum_start_offset(skb) -
6620 (pad_bytes + sizeof(struct tx_pkt_hdr));
6621 stuff = start + skb->csum_offset;
6623 csum_bits |= (start / 2) << TXHDR_L4START_SHIFT;
6624 csum_bits |= (stuff / 2) << TXHDR_L4STUFF_SHIFT;
6627 l3off = skb_network_offset(skb) -
6628 (pad_bytes + sizeof(struct tx_pkt_hdr));
6630 ret = (((pad_bytes / 2) << TXHDR_PAD_SHIFT) |
6631 (len << TXHDR_LEN_SHIFT) |
6632 ((l3off / 2) << TXHDR_L3START_SHIFT) |
6633 (ihl << TXHDR_IHL_SHIFT) |
6634 ((eth_proto_inner < 1536) ? TXHDR_LLC : 0) |
6635 ((eth_proto == ETH_P_8021Q) ? TXHDR_VLAN : 0) |
6636 (ipv6 ? TXHDR_IP_VER : 0) |
6642 static netdev_tx_t niu_start_xmit(struct sk_buff *skb,
6643 struct net_device *dev)
6645 struct niu *np = netdev_priv(dev);
6646 unsigned long align, headroom;
6647 struct netdev_queue *txq;
6648 struct tx_ring_info *rp;
6649 struct tx_pkt_hdr *tp;
6650 unsigned int len, nfg;
6651 struct ethhdr *ehdr;
6655 i = skb_get_queue_mapping(skb);
6656 rp = &np->tx_rings[i];
6657 txq = netdev_get_tx_queue(dev, i);
6659 if (niu_tx_avail(rp) <= (skb_shinfo(skb)->nr_frags + 1)) {
6660 netif_tx_stop_queue(txq);
6661 dev_err(np->device, "%s: BUG! Tx ring full when queue awake!\n", dev->name);
6663 return NETDEV_TX_BUSY;
6666 if (skb->len < ETH_ZLEN) {
6667 unsigned int pad_bytes = ETH_ZLEN - skb->len;
6669 if (skb_pad(skb, pad_bytes))
6671 skb_put(skb, pad_bytes);
6674 len = sizeof(struct tx_pkt_hdr) + 15;
6675 if (skb_headroom(skb) < len) {
6676 struct sk_buff *skb_new;
6678 skb_new = skb_realloc_headroom(skb, len);
6688 align = ((unsigned long) skb->data & (16 - 1));
6689 headroom = align + sizeof(struct tx_pkt_hdr);
6691 ehdr = (struct ethhdr *) skb->data;
6692 tp = (struct tx_pkt_hdr *) skb_push(skb, headroom);
6694 len = skb->len - sizeof(struct tx_pkt_hdr);
6695 tp->flags = cpu_to_le64(niu_compute_tx_flags(skb, ehdr, align, len));
6698 len = skb_headlen(skb);
6699 mapping = np->ops->map_single(np->device, skb->data,
6700 len, DMA_TO_DEVICE);
6704 rp->tx_buffs[prod].skb = skb;
6705 rp->tx_buffs[prod].mapping = mapping;
6708 if (++rp->mark_counter == rp->mark_freq) {
6709 rp->mark_counter = 0;
6710 mrk |= TX_DESC_MARK;
6715 nfg = skb_shinfo(skb)->nr_frags;
6717 tlen -= MAX_TX_DESC_LEN;
6722 unsigned int this_len = len;
6724 if (this_len > MAX_TX_DESC_LEN)
6725 this_len = MAX_TX_DESC_LEN;
6727 niu_set_txd(rp, prod, mapping, this_len, mrk, nfg);
6730 prod = NEXT_TX(rp, prod);
6731 mapping += this_len;
6735 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
6736 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6739 mapping = np->ops->map_page(np->device, frag->page,
6740 frag->page_offset, len,
6743 rp->tx_buffs[prod].skb = NULL;
6744 rp->tx_buffs[prod].mapping = mapping;
6746 niu_set_txd(rp, prod, mapping, len, 0, 0);
6748 prod = NEXT_TX(rp, prod);
6751 if (prod < rp->prod)
6752 rp->wrap_bit ^= TX_RING_KICK_WRAP;
6755 nw64(TX_RING_KICK(rp->tx_channel), rp->wrap_bit | (prod << 3));
6757 if (unlikely(niu_tx_avail(rp) <= (MAX_SKB_FRAGS + 1))) {
6758 netif_tx_stop_queue(txq);
6759 if (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp))
6760 netif_tx_wake_queue(txq);
6764 return NETDEV_TX_OK;
6772 static int niu_change_mtu(struct net_device *dev, int new_mtu)
6774 struct niu *np = netdev_priv(dev);
6775 int err, orig_jumbo, new_jumbo;
6777 if (new_mtu < 68 || new_mtu > NIU_MAX_MTU)
6780 orig_jumbo = (dev->mtu > ETH_DATA_LEN);
6781 new_jumbo = (new_mtu > ETH_DATA_LEN);
6785 if (!netif_running(dev) ||
6786 (orig_jumbo == new_jumbo))
6789 niu_full_shutdown(np, dev);
6791 niu_free_channels(np);
6793 niu_enable_napi(np);
6795 err = niu_alloc_channels(np);
6799 spin_lock_irq(&np->lock);
6801 err = niu_init_hw(np);
6803 init_timer(&np->timer);
6804 np->timer.expires = jiffies + HZ;
6805 np->timer.data = (unsigned long) np;
6806 np->timer.function = niu_timer;
6808 err = niu_enable_interrupts(np, 1);
6813 spin_unlock_irq(&np->lock);
6816 netif_tx_start_all_queues(dev);
6817 if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
6818 netif_carrier_on(dev);
6820 add_timer(&np->timer);
6826 static void niu_get_drvinfo(struct net_device *dev,
6827 struct ethtool_drvinfo *info)
6829 struct niu *np = netdev_priv(dev);
6830 struct niu_vpd *vpd = &np->vpd;
6832 strcpy(info->driver, DRV_MODULE_NAME);
6833 strcpy(info->version, DRV_MODULE_VERSION);
6834 sprintf(info->fw_version, "%d.%d",
6835 vpd->fcode_major, vpd->fcode_minor);
6836 if (np->parent->plat_type != PLAT_TYPE_NIU)
6837 strcpy(info->bus_info, pci_name(np->pdev));
6840 static int niu_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6842 struct niu *np = netdev_priv(dev);
6843 struct niu_link_config *lp;
6845 lp = &np->link_config;
6847 memset(cmd, 0, sizeof(*cmd));
6848 cmd->phy_address = np->phy_addr;
6849 cmd->supported = lp->supported;
6850 cmd->advertising = lp->active_advertising;
6851 cmd->autoneg = lp->active_autoneg;
6852 ethtool_cmd_speed_set(cmd, lp->active_speed);
6853 cmd->duplex = lp->active_duplex;
6854 cmd->port = (np->flags & NIU_FLAGS_FIBER) ? PORT_FIBRE : PORT_TP;
6855 cmd->transceiver = (np->flags & NIU_FLAGS_XCVR_SERDES) ?
6856 XCVR_EXTERNAL : XCVR_INTERNAL;
6861 static int niu_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6863 struct niu *np = netdev_priv(dev);
6864 struct niu_link_config *lp = &np->link_config;
6866 lp->advertising = cmd->advertising;
6867 lp->speed = ethtool_cmd_speed(cmd);
6868 lp->duplex = cmd->duplex;
6869 lp->autoneg = cmd->autoneg;
6870 return niu_init_link(np);
6873 static u32 niu_get_msglevel(struct net_device *dev)
6875 struct niu *np = netdev_priv(dev);
6876 return np->msg_enable;
6879 static void niu_set_msglevel(struct net_device *dev, u32 value)
6881 struct niu *np = netdev_priv(dev);
6882 np->msg_enable = value;
6885 static int niu_nway_reset(struct net_device *dev)
6887 struct niu *np = netdev_priv(dev);
6889 if (np->link_config.autoneg)
6890 return niu_init_link(np);
6895 static int niu_get_eeprom_len(struct net_device *dev)
6897 struct niu *np = netdev_priv(dev);
6899 return np->eeprom_len;
6902 static int niu_get_eeprom(struct net_device *dev,
6903 struct ethtool_eeprom *eeprom, u8 *data)
6905 struct niu *np = netdev_priv(dev);
6906 u32 offset, len, val;
6908 offset = eeprom->offset;
6911 if (offset + len < offset)
6913 if (offset >= np->eeprom_len)
6915 if (offset + len > np->eeprom_len)
6916 len = eeprom->len = np->eeprom_len - offset;
6919 u32 b_offset, b_count;
6921 b_offset = offset & 3;
6922 b_count = 4 - b_offset;
6926 val = nr64(ESPC_NCR((offset - b_offset) / 4));
6927 memcpy(data, ((char *)&val) + b_offset, b_count);
6933 val = nr64(ESPC_NCR(offset / 4));
6934 memcpy(data, &val, 4);
6940 val = nr64(ESPC_NCR(offset / 4));
6941 memcpy(data, &val, len);
6946 static void niu_ethflow_to_l3proto(int flow_type, u8 *pid)
6948 switch (flow_type) {
6959 *pid = IPPROTO_SCTP;
6975 static int niu_class_to_ethflow(u64 class, int *flow_type)
6978 case CLASS_CODE_TCP_IPV4:
6979 *flow_type = TCP_V4_FLOW;
6981 case CLASS_CODE_UDP_IPV4:
6982 *flow_type = UDP_V4_FLOW;
6984 case CLASS_CODE_AH_ESP_IPV4:
6985 *flow_type = AH_V4_FLOW;
6987 case CLASS_CODE_SCTP_IPV4:
6988 *flow_type = SCTP_V4_FLOW;
6990 case CLASS_CODE_TCP_IPV6:
6991 *flow_type = TCP_V6_FLOW;
6993 case CLASS_CODE_UDP_IPV6:
6994 *flow_type = UDP_V6_FLOW;
6996 case CLASS_CODE_AH_ESP_IPV6:
6997 *flow_type = AH_V6_FLOW;
6999 case CLASS_CODE_SCTP_IPV6:
7000 *flow_type = SCTP_V6_FLOW;
7002 case CLASS_CODE_USER_PROG1:
7003 case CLASS_CODE_USER_PROG2:
7004 case CLASS_CODE_USER_PROG3:
7005 case CLASS_CODE_USER_PROG4:
7006 *flow_type = IP_USER_FLOW;
7015 static int niu_ethflow_to_class(int flow_type, u64 *class)
7017 switch (flow_type) {
7019 *class = CLASS_CODE_TCP_IPV4;
7022 *class = CLASS_CODE_UDP_IPV4;
7024 case AH_ESP_V4_FLOW:
7027 *class = CLASS_CODE_AH_ESP_IPV4;
7030 *class = CLASS_CODE_SCTP_IPV4;
7033 *class = CLASS_CODE_TCP_IPV6;
7036 *class = CLASS_CODE_UDP_IPV6;
7038 case AH_ESP_V6_FLOW:
7041 *class = CLASS_CODE_AH_ESP_IPV6;
7044 *class = CLASS_CODE_SCTP_IPV6;
7053 static u64 niu_flowkey_to_ethflow(u64 flow_key)
7057 if (flow_key & FLOW_KEY_L2DA)
7058 ethflow |= RXH_L2DA;
7059 if (flow_key & FLOW_KEY_VLAN)
7060 ethflow |= RXH_VLAN;
7061 if (flow_key & FLOW_KEY_IPSA)
7062 ethflow |= RXH_IP_SRC;
7063 if (flow_key & FLOW_KEY_IPDA)
7064 ethflow |= RXH_IP_DST;
7065 if (flow_key & FLOW_KEY_PROTO)
7066 ethflow |= RXH_L3_PROTO;
7067 if (flow_key & (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_0_SHIFT))
7068 ethflow |= RXH_L4_B_0_1;
7069 if (flow_key & (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_1_SHIFT))
7070 ethflow |= RXH_L4_B_2_3;
7076 static int niu_ethflow_to_flowkey(u64 ethflow, u64 *flow_key)
7080 if (ethflow & RXH_L2DA)
7081 key |= FLOW_KEY_L2DA;
7082 if (ethflow & RXH_VLAN)
7083 key |= FLOW_KEY_VLAN;
7084 if (ethflow & RXH_IP_SRC)
7085 key |= FLOW_KEY_IPSA;
7086 if (ethflow & RXH_IP_DST)
7087 key |= FLOW_KEY_IPDA;
7088 if (ethflow & RXH_L3_PROTO)
7089 key |= FLOW_KEY_PROTO;
7090 if (ethflow & RXH_L4_B_0_1)
7091 key |= (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_0_SHIFT);
7092 if (ethflow & RXH_L4_B_2_3)
7093 key |= (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_1_SHIFT);
7101 static int niu_get_hash_opts(struct niu *np, struct ethtool_rxnfc *nfc)
7107 if (!niu_ethflow_to_class(nfc->flow_type, &class))
7110 if (np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] &
7112 nfc->data = RXH_DISCARD;
7114 nfc->data = niu_flowkey_to_ethflow(np->parent->flow_key[class -
7115 CLASS_CODE_USER_PROG1]);
7119 static void niu_get_ip4fs_from_tcam_key(struct niu_tcam_entry *tp,
7120 struct ethtool_rx_flow_spec *fsp)
7125 tmp = (tp->key[3] & TCAM_V4KEY3_SADDR) >> TCAM_V4KEY3_SADDR_SHIFT;
7126 fsp->h_u.tcp_ip4_spec.ip4src = cpu_to_be32(tmp);
7128 tmp = (tp->key[3] & TCAM_V4KEY3_DADDR) >> TCAM_V4KEY3_DADDR_SHIFT;
7129 fsp->h_u.tcp_ip4_spec.ip4dst = cpu_to_be32(tmp);
7131 tmp = (tp->key_mask[3] & TCAM_V4KEY3_SADDR) >> TCAM_V4KEY3_SADDR_SHIFT;
7132 fsp->m_u.tcp_ip4_spec.ip4src = cpu_to_be32(tmp);
7134 tmp = (tp->key_mask[3] & TCAM_V4KEY3_DADDR) >> TCAM_V4KEY3_DADDR_SHIFT;
7135 fsp->m_u.tcp_ip4_spec.ip4dst = cpu_to_be32(tmp);
7137 fsp->h_u.tcp_ip4_spec.tos = (tp->key[2] & TCAM_V4KEY2_TOS) >>
7138 TCAM_V4KEY2_TOS_SHIFT;
7139 fsp->m_u.tcp_ip4_spec.tos = (tp->key_mask[2] & TCAM_V4KEY2_TOS) >>
7140 TCAM_V4KEY2_TOS_SHIFT;
7142 switch (fsp->flow_type) {
7146 prt = ((tp->key[2] & TCAM_V4KEY2_PORT_SPI) >>
7147 TCAM_V4KEY2_PORT_SPI_SHIFT) >> 16;
7148 fsp->h_u.tcp_ip4_spec.psrc = cpu_to_be16(prt);
7150 prt = ((tp->key[2] & TCAM_V4KEY2_PORT_SPI) >>
7151 TCAM_V4KEY2_PORT_SPI_SHIFT) & 0xffff;
7152 fsp->h_u.tcp_ip4_spec.pdst = cpu_to_be16(prt);
7154 prt = ((tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >>
7155 TCAM_V4KEY2_PORT_SPI_SHIFT) >> 16;
7156 fsp->m_u.tcp_ip4_spec.psrc = cpu_to_be16(prt);
7158 prt = ((tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >>
7159 TCAM_V4KEY2_PORT_SPI_SHIFT) & 0xffff;
7160 fsp->m_u.tcp_ip4_spec.pdst = cpu_to_be16(prt);
7164 tmp = (tp->key[2] & TCAM_V4KEY2_PORT_SPI) >>
7165 TCAM_V4KEY2_PORT_SPI_SHIFT;
7166 fsp->h_u.ah_ip4_spec.spi = cpu_to_be32(tmp);
7168 tmp = (tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >>
7169 TCAM_V4KEY2_PORT_SPI_SHIFT;
7170 fsp->m_u.ah_ip4_spec.spi = cpu_to_be32(tmp);
7173 tmp = (tp->key[2] & TCAM_V4KEY2_PORT_SPI) >>
7174 TCAM_V4KEY2_PORT_SPI_SHIFT;
7175 fsp->h_u.usr_ip4_spec.l4_4_bytes = cpu_to_be32(tmp);
7177 tmp = (tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >>
7178 TCAM_V4KEY2_PORT_SPI_SHIFT;
7179 fsp->m_u.usr_ip4_spec.l4_4_bytes = cpu_to_be32(tmp);
7181 fsp->h_u.usr_ip4_spec.proto =
7182 (tp->key[2] & TCAM_V4KEY2_PROTO) >>
7183 TCAM_V4KEY2_PROTO_SHIFT;
7184 fsp->m_u.usr_ip4_spec.proto =
7185 (tp->key_mask[2] & TCAM_V4KEY2_PROTO) >>
7186 TCAM_V4KEY2_PROTO_SHIFT;
7188 fsp->h_u.usr_ip4_spec.ip_ver = ETH_RX_NFC_IP4;
7195 static int niu_get_ethtool_tcam_entry(struct niu *np,
7196 struct ethtool_rxnfc *nfc)
7198 struct niu_parent *parent = np->parent;
7199 struct niu_tcam_entry *tp;
7200 struct ethtool_rx_flow_spec *fsp = &nfc->fs;
7205 idx = tcam_get_index(np, (u16)nfc->fs.location);
7207 tp = &parent->tcam[idx];
7209 netdev_info(np->dev, "niu%d: entry [%d] invalid for idx[%d]\n",
7210 parent->index, (u16)nfc->fs.location, idx);
7214 /* fill the flow spec entry */
7215 class = (tp->key[0] & TCAM_V4KEY0_CLASS_CODE) >>
7216 TCAM_V4KEY0_CLASS_CODE_SHIFT;
7217 ret = niu_class_to_ethflow(class, &fsp->flow_type);
7220 netdev_info(np->dev, "niu%d: niu_class_to_ethflow failed\n",
7226 if (fsp->flow_type == AH_V4_FLOW || fsp->flow_type == AH_V6_FLOW) {
7227 u32 proto = (tp->key[2] & TCAM_V4KEY2_PROTO) >>
7228 TCAM_V4KEY2_PROTO_SHIFT;
7229 if (proto == IPPROTO_ESP) {
7230 if (fsp->flow_type == AH_V4_FLOW)
7231 fsp->flow_type = ESP_V4_FLOW;
7233 fsp->flow_type = ESP_V6_FLOW;
7237 switch (fsp->flow_type) {
7243 niu_get_ip4fs_from_tcam_key(tp, fsp);
7250 /* Not yet implemented */
7254 niu_get_ip4fs_from_tcam_key(tp, fsp);
7264 if (tp->assoc_data & TCAM_ASSOCDATA_DISC)
7265 fsp->ring_cookie = RX_CLS_FLOW_DISC;
7267 fsp->ring_cookie = (tp->assoc_data & TCAM_ASSOCDATA_OFFSET) >>
7268 TCAM_ASSOCDATA_OFFSET_SHIFT;
7270 /* put the tcam size here */
7271 nfc->data = tcam_get_size(np);
7276 static int niu_get_ethtool_tcam_all(struct niu *np,
7277 struct ethtool_rxnfc *nfc,
7280 struct niu_parent *parent = np->parent;
7281 struct niu_tcam_entry *tp;
7283 unsigned long flags;
7286 /* put the tcam size here */
7287 nfc->data = tcam_get_size(np);
7289 niu_lock_parent(np, flags);
7290 for (cnt = 0, i = 0; i < nfc->data; i++) {
7291 idx = tcam_get_index(np, i);
7292 tp = &parent->tcam[idx];
7295 if (cnt == nfc->rule_cnt) {
7302 niu_unlock_parent(np, flags);
7307 static int niu_get_nfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
7310 struct niu *np = netdev_priv(dev);
7315 ret = niu_get_hash_opts(np, cmd);
7317 case ETHTOOL_GRXRINGS:
7318 cmd->data = np->num_rx_rings;
7320 case ETHTOOL_GRXCLSRLCNT:
7321 cmd->rule_cnt = tcam_get_valid_entry_cnt(np);
7323 case ETHTOOL_GRXCLSRULE:
7324 ret = niu_get_ethtool_tcam_entry(np, cmd);
7326 case ETHTOOL_GRXCLSRLALL:
7327 ret = niu_get_ethtool_tcam_all(np, cmd, (u32 *)rule_locs);
7337 static int niu_set_hash_opts(struct niu *np, struct ethtool_rxnfc *nfc)
7341 unsigned long flags;
7343 if (!niu_ethflow_to_class(nfc->flow_type, &class))
7346 if (class < CLASS_CODE_USER_PROG1 ||
7347 class > CLASS_CODE_SCTP_IPV6)
7350 if (nfc->data & RXH_DISCARD) {
7351 niu_lock_parent(np, flags);
7352 flow_key = np->parent->tcam_key[class -
7353 CLASS_CODE_USER_PROG1];
7354 flow_key |= TCAM_KEY_DISC;
7355 nw64(TCAM_KEY(class - CLASS_CODE_USER_PROG1), flow_key);
7356 np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] = flow_key;
7357 niu_unlock_parent(np, flags);
7360 /* Discard was set before, but is not set now */
7361 if (np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] &
7363 niu_lock_parent(np, flags);
7364 flow_key = np->parent->tcam_key[class -
7365 CLASS_CODE_USER_PROG1];
7366 flow_key &= ~TCAM_KEY_DISC;
7367 nw64(TCAM_KEY(class - CLASS_CODE_USER_PROG1),
7369 np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] =
7371 niu_unlock_parent(np, flags);
7375 if (!niu_ethflow_to_flowkey(nfc->data, &flow_key))
7378 niu_lock_parent(np, flags);
7379 nw64(FLOW_KEY(class - CLASS_CODE_USER_PROG1), flow_key);
7380 np->parent->flow_key[class - CLASS_CODE_USER_PROG1] = flow_key;
7381 niu_unlock_parent(np, flags);
7386 static void niu_get_tcamkey_from_ip4fs(struct ethtool_rx_flow_spec *fsp,
7387 struct niu_tcam_entry *tp,
7388 int l2_rdc_tab, u64 class)
7391 u32 sip, dip, sipm, dipm, spi, spim;
7392 u16 sport, dport, spm, dpm;
7394 sip = be32_to_cpu(fsp->h_u.tcp_ip4_spec.ip4src);
7395 sipm = be32_to_cpu(fsp->m_u.tcp_ip4_spec.ip4src);
7396 dip = be32_to_cpu(fsp->h_u.tcp_ip4_spec.ip4dst);
7397 dipm = be32_to_cpu(fsp->m_u.tcp_ip4_spec.ip4dst);
7399 tp->key[0] = class << TCAM_V4KEY0_CLASS_CODE_SHIFT;
7400 tp->key_mask[0] = TCAM_V4KEY0_CLASS_CODE;
7401 tp->key[1] = (u64)l2_rdc_tab << TCAM_V4KEY1_L2RDCNUM_SHIFT;
7402 tp->key_mask[1] = TCAM_V4KEY1_L2RDCNUM;
7404 tp->key[3] = (u64)sip << TCAM_V4KEY3_SADDR_SHIFT;
7407 tp->key_mask[3] = (u64)sipm << TCAM_V4KEY3_SADDR_SHIFT;
7408 tp->key_mask[3] |= dipm;
7410 tp->key[2] |= ((u64)fsp->h_u.tcp_ip4_spec.tos <<
7411 TCAM_V4KEY2_TOS_SHIFT);
7412 tp->key_mask[2] |= ((u64)fsp->m_u.tcp_ip4_spec.tos <<
7413 TCAM_V4KEY2_TOS_SHIFT);
7414 switch (fsp->flow_type) {
7418 sport = be16_to_cpu(fsp->h_u.tcp_ip4_spec.psrc);
7419 spm = be16_to_cpu(fsp->m_u.tcp_ip4_spec.psrc);
7420 dport = be16_to_cpu(fsp->h_u.tcp_ip4_spec.pdst);
7421 dpm = be16_to_cpu(fsp->m_u.tcp_ip4_spec.pdst);
7423 tp->key[2] |= (((u64)sport << 16) | dport);
7424 tp->key_mask[2] |= (((u64)spm << 16) | dpm);
7425 niu_ethflow_to_l3proto(fsp->flow_type, &pid);
7429 spi = be32_to_cpu(fsp->h_u.ah_ip4_spec.spi);
7430 spim = be32_to_cpu(fsp->m_u.ah_ip4_spec.spi);
7433 tp->key_mask[2] |= spim;
7434 niu_ethflow_to_l3proto(fsp->flow_type, &pid);
7437 spi = be32_to_cpu(fsp->h_u.usr_ip4_spec.l4_4_bytes);
7438 spim = be32_to_cpu(fsp->m_u.usr_ip4_spec.l4_4_bytes);
7441 tp->key_mask[2] |= spim;
7442 pid = fsp->h_u.usr_ip4_spec.proto;
7448 tp->key[2] |= ((u64)pid << TCAM_V4KEY2_PROTO_SHIFT);
7450 tp->key_mask[2] |= TCAM_V4KEY2_PROTO;
7454 static int niu_add_ethtool_tcam_entry(struct niu *np,
7455 struct ethtool_rxnfc *nfc)
7457 struct niu_parent *parent = np->parent;
7458 struct niu_tcam_entry *tp;
7459 struct ethtool_rx_flow_spec *fsp = &nfc->fs;
7460 struct niu_rdc_tables *rdc_table = &parent->rdc_group_cfg[np->port];
7461 int l2_rdc_table = rdc_table->first_table_num;
7464 unsigned long flags;
7469 idx = nfc->fs.location;
7470 if (idx >= tcam_get_size(np))
7473 if (fsp->flow_type == IP_USER_FLOW) {
7475 int add_usr_cls = 0;
7476 struct ethtool_usrip4_spec *uspec = &fsp->h_u.usr_ip4_spec;
7477 struct ethtool_usrip4_spec *umask = &fsp->m_u.usr_ip4_spec;
7479 if (uspec->ip_ver != ETH_RX_NFC_IP4)
7482 niu_lock_parent(np, flags);
7484 for (i = 0; i < NIU_L3_PROG_CLS; i++) {
7485 if (parent->l3_cls[i]) {
7486 if (uspec->proto == parent->l3_cls_pid[i]) {
7487 class = parent->l3_cls[i];
7488 parent->l3_cls_refcnt[i]++;
7493 /* Program new user IP class */
7496 class = CLASS_CODE_USER_PROG1;
7499 class = CLASS_CODE_USER_PROG2;
7502 class = CLASS_CODE_USER_PROG3;
7505 class = CLASS_CODE_USER_PROG4;
7510 ret = tcam_user_ip_class_set(np, class, 0,
7517 ret = tcam_user_ip_class_enable(np, class, 1);
7520 parent->l3_cls[i] = class;
7521 parent->l3_cls_pid[i] = uspec->proto;
7522 parent->l3_cls_refcnt[i]++;
7528 netdev_info(np->dev, "niu%d: %s(): Could not find/insert class for pid %d\n",
7529 parent->index, __func__, uspec->proto);
7533 niu_unlock_parent(np, flags);
7535 if (!niu_ethflow_to_class(fsp->flow_type, &class)) {
7540 niu_lock_parent(np, flags);
7542 idx = tcam_get_index(np, idx);
7543 tp = &parent->tcam[idx];
7545 memset(tp, 0, sizeof(*tp));
7547 /* fill in the tcam key and mask */
7548 switch (fsp->flow_type) {
7554 niu_get_tcamkey_from_ip4fs(fsp, tp, l2_rdc_table, class);
7561 /* Not yet implemented */
7562 netdev_info(np->dev, "niu%d: In %s(): flow %d for IPv6 not implemented\n",
7563 parent->index, __func__, fsp->flow_type);
7567 niu_get_tcamkey_from_ip4fs(fsp, tp, l2_rdc_table, class);
7570 netdev_info(np->dev, "niu%d: In %s(): Unknown flow type %d\n",
7571 parent->index, __func__, fsp->flow_type);
7576 /* fill in the assoc data */
7577 if (fsp->ring_cookie == RX_CLS_FLOW_DISC) {
7578 tp->assoc_data = TCAM_ASSOCDATA_DISC;
7580 if (fsp->ring_cookie >= np->num_rx_rings) {
7581 netdev_info(np->dev, "niu%d: In %s(): Invalid RX ring %lld\n",
7582 parent->index, __func__,
7583 (long long)fsp->ring_cookie);
7587 tp->assoc_data = (TCAM_ASSOCDATA_TRES_USE_OFFSET |
7588 (fsp->ring_cookie <<
7589 TCAM_ASSOCDATA_OFFSET_SHIFT));
7592 err = tcam_write(np, idx, tp->key, tp->key_mask);
7597 err = tcam_assoc_write(np, idx, tp->assoc_data);
7603 /* validate the entry */
7605 np->clas.tcam_valid_entries++;
7607 niu_unlock_parent(np, flags);
7612 static int niu_del_ethtool_tcam_entry(struct niu *np, u32 loc)
7614 struct niu_parent *parent = np->parent;
7615 struct niu_tcam_entry *tp;
7617 unsigned long flags;
7621 if (loc >= tcam_get_size(np))
7624 niu_lock_parent(np, flags);
7626 idx = tcam_get_index(np, loc);
7627 tp = &parent->tcam[idx];
7629 /* if the entry is of a user defined class, then update*/
7630 class = (tp->key[0] & TCAM_V4KEY0_CLASS_CODE) >>
7631 TCAM_V4KEY0_CLASS_CODE_SHIFT;
7633 if (class >= CLASS_CODE_USER_PROG1 && class <= CLASS_CODE_USER_PROG4) {
7635 for (i = 0; i < NIU_L3_PROG_CLS; i++) {
7636 if (parent->l3_cls[i] == class) {
7637 parent->l3_cls_refcnt[i]--;
7638 if (!parent->l3_cls_refcnt[i]) {
7640 ret = tcam_user_ip_class_enable(np,
7645 parent->l3_cls[i] = 0;
7646 parent->l3_cls_pid[i] = 0;
7651 if (i == NIU_L3_PROG_CLS) {
7652 netdev_info(np->dev, "niu%d: In %s(): Usr class 0x%llx not found\n",
7653 parent->index, __func__,
7654 (unsigned long long)class);
7660 ret = tcam_flush(np, idx);
7664 /* invalidate the entry */
7666 np->clas.tcam_valid_entries--;
7668 niu_unlock_parent(np, flags);
7673 static int niu_set_nfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
7675 struct niu *np = netdev_priv(dev);
7680 ret = niu_set_hash_opts(np, cmd);
7682 case ETHTOOL_SRXCLSRLINS:
7683 ret = niu_add_ethtool_tcam_entry(np, cmd);
7685 case ETHTOOL_SRXCLSRLDEL:
7686 ret = niu_del_ethtool_tcam_entry(np, cmd->fs.location);
7696 static const struct {
7697 const char string[ETH_GSTRING_LEN];
7698 } niu_xmac_stat_keys[] = {
7701 { "tx_fifo_errors" },
7702 { "tx_overflow_errors" },
7703 { "tx_max_pkt_size_errors" },
7704 { "tx_underflow_errors" },
7705 { "rx_local_faults" },
7706 { "rx_remote_faults" },
7707 { "rx_link_faults" },
7708 { "rx_align_errors" },
7720 { "rx_code_violations" },
7721 { "rx_len_errors" },
7722 { "rx_crc_errors" },
7723 { "rx_underflows" },
7725 { "pause_off_state" },
7726 { "pause_on_state" },
7727 { "pause_received" },
7730 #define NUM_XMAC_STAT_KEYS ARRAY_SIZE(niu_xmac_stat_keys)
7732 static const struct {
7733 const char string[ETH_GSTRING_LEN];
7734 } niu_bmac_stat_keys[] = {
7735 { "tx_underflow_errors" },
7736 { "tx_max_pkt_size_errors" },
7741 { "rx_align_errors" },
7742 { "rx_crc_errors" },
7743 { "rx_len_errors" },
7744 { "pause_off_state" },
7745 { "pause_on_state" },
7746 { "pause_received" },
7749 #define NUM_BMAC_STAT_KEYS ARRAY_SIZE(niu_bmac_stat_keys)
7751 static const struct {
7752 const char string[ETH_GSTRING_LEN];
7753 } niu_rxchan_stat_keys[] = {
7761 #define NUM_RXCHAN_STAT_KEYS ARRAY_SIZE(niu_rxchan_stat_keys)
7763 static const struct {
7764 const char string[ETH_GSTRING_LEN];
7765 } niu_txchan_stat_keys[] = {
7772 #define NUM_TXCHAN_STAT_KEYS ARRAY_SIZE(niu_txchan_stat_keys)
7774 static void niu_get_strings(struct net_device *dev, u32 stringset, u8 *data)
7776 struct niu *np = netdev_priv(dev);
7779 if (stringset != ETH_SS_STATS)
7782 if (np->flags & NIU_FLAGS_XMAC) {
7783 memcpy(data, niu_xmac_stat_keys,
7784 sizeof(niu_xmac_stat_keys));
7785 data += sizeof(niu_xmac_stat_keys);
7787 memcpy(data, niu_bmac_stat_keys,
7788 sizeof(niu_bmac_stat_keys));
7789 data += sizeof(niu_bmac_stat_keys);
7791 for (i = 0; i < np->num_rx_rings; i++) {
7792 memcpy(data, niu_rxchan_stat_keys,
7793 sizeof(niu_rxchan_stat_keys));
7794 data += sizeof(niu_rxchan_stat_keys);
7796 for (i = 0; i < np->num_tx_rings; i++) {
7797 memcpy(data, niu_txchan_stat_keys,
7798 sizeof(niu_txchan_stat_keys));
7799 data += sizeof(niu_txchan_stat_keys);
7803 static int niu_get_sset_count(struct net_device *dev, int stringset)
7805 struct niu *np = netdev_priv(dev);
7807 if (stringset != ETH_SS_STATS)
7810 return (np->flags & NIU_FLAGS_XMAC ?
7811 NUM_XMAC_STAT_KEYS :
7812 NUM_BMAC_STAT_KEYS) +
7813 (np->num_rx_rings * NUM_RXCHAN_STAT_KEYS) +
7814 (np->num_tx_rings * NUM_TXCHAN_STAT_KEYS);
7817 static void niu_get_ethtool_stats(struct net_device *dev,
7818 struct ethtool_stats *stats, u64 *data)
7820 struct niu *np = netdev_priv(dev);
7823 niu_sync_mac_stats(np);
7824 if (np->flags & NIU_FLAGS_XMAC) {
7825 memcpy(data, &np->mac_stats.xmac,
7826 sizeof(struct niu_xmac_stats));
7827 data += (sizeof(struct niu_xmac_stats) / sizeof(u64));
7829 memcpy(data, &np->mac_stats.bmac,
7830 sizeof(struct niu_bmac_stats));
7831 data += (sizeof(struct niu_bmac_stats) / sizeof(u64));
7833 for (i = 0; i < np->num_rx_rings; i++) {
7834 struct rx_ring_info *rp = &np->rx_rings[i];
7836 niu_sync_rx_discard_stats(np, rp, 0);
7838 data[0] = rp->rx_channel;
7839 data[1] = rp->rx_packets;
7840 data[2] = rp->rx_bytes;
7841 data[3] = rp->rx_dropped;
7842 data[4] = rp->rx_errors;
7845 for (i = 0; i < np->num_tx_rings; i++) {
7846 struct tx_ring_info *rp = &np->tx_rings[i];
7848 data[0] = rp->tx_channel;
7849 data[1] = rp->tx_packets;
7850 data[2] = rp->tx_bytes;
7851 data[3] = rp->tx_errors;
7856 static u64 niu_led_state_save(struct niu *np)
7858 if (np->flags & NIU_FLAGS_XMAC)
7859 return nr64_mac(XMAC_CONFIG);
7861 return nr64_mac(BMAC_XIF_CONFIG);
7864 static void niu_led_state_restore(struct niu *np, u64 val)
7866 if (np->flags & NIU_FLAGS_XMAC)
7867 nw64_mac(XMAC_CONFIG, val);
7869 nw64_mac(BMAC_XIF_CONFIG, val);
7872 static void niu_force_led(struct niu *np, int on)
7876 if (np->flags & NIU_FLAGS_XMAC) {
7878 bit = XMAC_CONFIG_FORCE_LED_ON;
7880 reg = BMAC_XIF_CONFIG;
7881 bit = BMAC_XIF_CONFIG_LINK_LED;
7884 val = nr64_mac(reg);
7892 static int niu_set_phys_id(struct net_device *dev,
7893 enum ethtool_phys_id_state state)
7896 struct niu *np = netdev_priv(dev);
7898 if (!netif_running(dev))
7902 case ETHTOOL_ID_ACTIVE:
7903 np->orig_led_state = niu_led_state_save(np);
7904 return 1; /* cycle on/off once per second */
7907 niu_force_led(np, 1);
7910 case ETHTOOL_ID_OFF:
7911 niu_force_led(np, 0);
7914 case ETHTOOL_ID_INACTIVE:
7915 niu_led_state_restore(np, np->orig_led_state);
7921 static const struct ethtool_ops niu_ethtool_ops = {
7922 .get_drvinfo = niu_get_drvinfo,
7923 .get_link = ethtool_op_get_link,
7924 .get_msglevel = niu_get_msglevel,
7925 .set_msglevel = niu_set_msglevel,
7926 .nway_reset = niu_nway_reset,
7927 .get_eeprom_len = niu_get_eeprom_len,
7928 .get_eeprom = niu_get_eeprom,
7929 .get_settings = niu_get_settings,
7930 .set_settings = niu_set_settings,
7931 .get_strings = niu_get_strings,
7932 .get_sset_count = niu_get_sset_count,
7933 .get_ethtool_stats = niu_get_ethtool_stats,
7934 .set_phys_id = niu_set_phys_id,
7935 .get_rxnfc = niu_get_nfc,
7936 .set_rxnfc = niu_set_nfc,
7939 static int niu_ldg_assign_ldn(struct niu *np, struct niu_parent *parent,
7942 if (ldg < NIU_LDG_MIN || ldg > NIU_LDG_MAX)
7944 if (ldn < 0 || ldn > LDN_MAX)
7947 parent->ldg_map[ldn] = ldg;
7949 if (np->parent->plat_type == PLAT_TYPE_NIU) {
7950 /* On N2 NIU, the ldn-->ldg assignments are setup and fixed by
7951 * the firmware, and we're not supposed to change them.
7952 * Validate the mapping, because if it's wrong we probably
7953 * won't get any interrupts and that's painful to debug.
7955 if (nr64(LDG_NUM(ldn)) != ldg) {
7956 dev_err(np->device, "Port %u, mis-matched LDG assignment for ldn %d, should be %d is %llu\n",
7958 (unsigned long long) nr64(LDG_NUM(ldn)));
7962 nw64(LDG_NUM(ldn), ldg);
7967 static int niu_set_ldg_timer_res(struct niu *np, int res)
7969 if (res < 0 || res > LDG_TIMER_RES_VAL)
7973 nw64(LDG_TIMER_RES, res);
7978 static int niu_set_ldg_sid(struct niu *np, int ldg, int func, int vector)
7980 if ((ldg < NIU_LDG_MIN || ldg > NIU_LDG_MAX) ||
7981 (func < 0 || func > 3) ||
7982 (vector < 0 || vector > 0x1f))
7985 nw64(SID(ldg), (func << SID_FUNC_SHIFT) | vector);
7990 static int __devinit niu_pci_eeprom_read(struct niu *np, u32 addr)
7992 u64 frame, frame_base = (ESPC_PIO_STAT_READ_START |
7993 (addr << ESPC_PIO_STAT_ADDR_SHIFT));
7996 if (addr > (ESPC_PIO_STAT_ADDR >> ESPC_PIO_STAT_ADDR_SHIFT))
8000 nw64(ESPC_PIO_STAT, frame);
8004 frame = nr64(ESPC_PIO_STAT);
8005 if (frame & ESPC_PIO_STAT_READ_END)
8008 if (!(frame & ESPC_PIO_STAT_READ_END)) {
8009 dev_err(np->device, "EEPROM read timeout frame[%llx]\n",
8010 (unsigned long long) frame);
8015 nw64(ESPC_PIO_STAT, frame);
8019 frame = nr64(ESPC_PIO_STAT);
8020 if (frame & ESPC_PIO_STAT_READ_END)
8023 if (!(frame & ESPC_PIO_STAT_READ_END)) {
8024 dev_err(np->device, "EEPROM read timeout frame[%llx]\n",
8025 (unsigned long long) frame);
8029 frame = nr64(ESPC_PIO_STAT);
8030 return (frame & ESPC_PIO_STAT_DATA) >> ESPC_PIO_STAT_DATA_SHIFT;
8033 static int __devinit niu_pci_eeprom_read16(struct niu *np, u32 off)
8035 int err = niu_pci_eeprom_read(np, off);
8041 err = niu_pci_eeprom_read(np, off + 1);
8044 val |= (err & 0xff);
8049 static int __devinit niu_pci_eeprom_read16_swp(struct niu *np, u32 off)
8051 int err = niu_pci_eeprom_read(np, off);
8058 err = niu_pci_eeprom_read(np, off + 1);
8062 val |= (err & 0xff) << 8;
8067 static int __devinit niu_pci_vpd_get_propname(struct niu *np,
8074 for (i = 0; i < namebuf_len; i++) {
8075 int err = niu_pci_eeprom_read(np, off + i);
8082 if (i >= namebuf_len)
8088 static void __devinit niu_vpd_parse_version(struct niu *np)
8090 struct niu_vpd *vpd = &np->vpd;
8091 int len = strlen(vpd->version) + 1;
8092 const char *s = vpd->version;
8095 for (i = 0; i < len - 5; i++) {
8096 if (!strncmp(s + i, "FCode ", 6))
8103 sscanf(s, "%d.%d", &vpd->fcode_major, &vpd->fcode_minor);
8105 netif_printk(np, probe, KERN_DEBUG, np->dev,
8106 "VPD_SCAN: FCODE major(%d) minor(%d)\n",
8107 vpd->fcode_major, vpd->fcode_minor);
8108 if (vpd->fcode_major > NIU_VPD_MIN_MAJOR ||
8109 (vpd->fcode_major == NIU_VPD_MIN_MAJOR &&
8110 vpd->fcode_minor >= NIU_VPD_MIN_MINOR))
8111 np->flags |= NIU_FLAGS_VPD_VALID;
8114 /* ESPC_PIO_EN_ENABLE must be set */
8115 static int __devinit niu_pci_vpd_scan_props(struct niu *np,
8118 unsigned int found_mask = 0;
8119 #define FOUND_MASK_MODEL 0x00000001
8120 #define FOUND_MASK_BMODEL 0x00000002
8121 #define FOUND_MASK_VERS 0x00000004
8122 #define FOUND_MASK_MAC 0x00000008
8123 #define FOUND_MASK_NMAC 0x00000010
8124 #define FOUND_MASK_PHY 0x00000020
8125 #define FOUND_MASK_ALL 0x0000003f
8127 netif_printk(np, probe, KERN_DEBUG, np->dev,
8128 "VPD_SCAN: start[%x] end[%x]\n", start, end);
8129 while (start < end) {
8130 int len, err, prop_len;
8135 if (found_mask == FOUND_MASK_ALL) {
8136 niu_vpd_parse_version(np);
8140 err = niu_pci_eeprom_read(np, start + 2);
8146 prop_len = niu_pci_eeprom_read(np, start + 4);
8147 err = niu_pci_vpd_get_propname(np, start + 5, namebuf, 64);
8153 if (!strcmp(namebuf, "model")) {
8154 prop_buf = np->vpd.model;
8155 max_len = NIU_VPD_MODEL_MAX;
8156 found_mask |= FOUND_MASK_MODEL;
8157 } else if (!strcmp(namebuf, "board-model")) {
8158 prop_buf = np->vpd.board_model;
8159 max_len = NIU_VPD_BD_MODEL_MAX;
8160 found_mask |= FOUND_MASK_BMODEL;
8161 } else if (!strcmp(namebuf, "version")) {
8162 prop_buf = np->vpd.version;
8163 max_len = NIU_VPD_VERSION_MAX;
8164 found_mask |= FOUND_MASK_VERS;
8165 } else if (!strcmp(namebuf, "local-mac-address")) {
8166 prop_buf = np->vpd.local_mac;
8168 found_mask |= FOUND_MASK_MAC;
8169 } else if (!strcmp(namebuf, "num-mac-addresses")) {
8170 prop_buf = &np->vpd.mac_num;
8172 found_mask |= FOUND_MASK_NMAC;
8173 } else if (!strcmp(namebuf, "phy-type")) {
8174 prop_buf = np->vpd.phy_type;
8175 max_len = NIU_VPD_PHY_TYPE_MAX;
8176 found_mask |= FOUND_MASK_PHY;
8179 if (max_len && prop_len > max_len) {
8180 dev_err(np->device, "Property '%s' length (%d) is too long\n", namebuf, prop_len);
8185 u32 off = start + 5 + err;
8188 netif_printk(np, probe, KERN_DEBUG, np->dev,
8189 "VPD_SCAN: Reading in property [%s] len[%d]\n",
8191 for (i = 0; i < prop_len; i++)
8192 *prop_buf++ = niu_pci_eeprom_read(np, off + i);
8201 /* ESPC_PIO_EN_ENABLE must be set */
8202 static void __devinit niu_pci_vpd_fetch(struct niu *np, u32 start)
8207 err = niu_pci_eeprom_read16_swp(np, start + 1);
8213 while (start + offset < ESPC_EEPROM_SIZE) {
8214 u32 here = start + offset;
8217 err = niu_pci_eeprom_read(np, here);
8221 err = niu_pci_eeprom_read16_swp(np, here + 1);
8225 here = start + offset + 3;
8226 end = start + offset + err;
8230 err = niu_pci_vpd_scan_props(np, here, end);
8231 if (err < 0 || err == 1)
8236 /* ESPC_PIO_EN_ENABLE must be set */
8237 static u32 __devinit niu_pci_vpd_offset(struct niu *np)
8239 u32 start = 0, end = ESPC_EEPROM_SIZE, ret;
8242 while (start < end) {
8245 /* ROM header signature? */
8246 err = niu_pci_eeprom_read16(np, start + 0);
8250 /* Apply offset to PCI data structure. */
8251 err = niu_pci_eeprom_read16(np, start + 23);
8256 /* Check for "PCIR" signature. */
8257 err = niu_pci_eeprom_read16(np, start + 0);
8260 err = niu_pci_eeprom_read16(np, start + 2);
8264 /* Check for OBP image type. */
8265 err = niu_pci_eeprom_read(np, start + 20);
8269 err = niu_pci_eeprom_read(np, ret + 2);
8273 start = ret + (err * 512);
8277 err = niu_pci_eeprom_read16_swp(np, start + 8);
8282 err = niu_pci_eeprom_read(np, ret + 0);
8292 static int __devinit niu_phy_type_prop_decode(struct niu *np,
8293 const char *phy_prop)
8295 if (!strcmp(phy_prop, "mif")) {
8296 /* 1G copper, MII */
8297 np->flags &= ~(NIU_FLAGS_FIBER |
8299 np->mac_xcvr = MAC_XCVR_MII;
8300 } else if (!strcmp(phy_prop, "xgf")) {
8301 /* 10G fiber, XPCS */
8302 np->flags |= (NIU_FLAGS_10G |
8304 np->mac_xcvr = MAC_XCVR_XPCS;
8305 } else if (!strcmp(phy_prop, "pcs")) {
8307 np->flags &= ~NIU_FLAGS_10G;
8308 np->flags |= NIU_FLAGS_FIBER;
8309 np->mac_xcvr = MAC_XCVR_PCS;
8310 } else if (!strcmp(phy_prop, "xgc")) {
8311 /* 10G copper, XPCS */
8312 np->flags |= NIU_FLAGS_10G;
8313 np->flags &= ~NIU_FLAGS_FIBER;
8314 np->mac_xcvr = MAC_XCVR_XPCS;
8315 } else if (!strcmp(phy_prop, "xgsd") || !strcmp(phy_prop, "gsd")) {
8316 /* 10G Serdes or 1G Serdes, default to 10G */
8317 np->flags |= NIU_FLAGS_10G;
8318 np->flags &= ~NIU_FLAGS_FIBER;
8319 np->flags |= NIU_FLAGS_XCVR_SERDES;
8320 np->mac_xcvr = MAC_XCVR_XPCS;
8327 static int niu_pci_vpd_get_nports(struct niu *np)
8331 if ((!strcmp(np->vpd.model, NIU_QGC_LP_MDL_STR)) ||
8332 (!strcmp(np->vpd.model, NIU_QGC_PEM_MDL_STR)) ||
8333 (!strcmp(np->vpd.model, NIU_MARAMBA_MDL_STR)) ||
8334 (!strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) ||
8335 (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR))) {
8337 } else if ((!strcmp(np->vpd.model, NIU_2XGF_LP_MDL_STR)) ||
8338 (!strcmp(np->vpd.model, NIU_2XGF_PEM_MDL_STR)) ||
8339 (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) ||
8340 (!strcmp(np->vpd.model, NIU_2XGF_MRVL_MDL_STR))) {
8347 static void __devinit niu_pci_vpd_validate(struct niu *np)
8349 struct net_device *dev = np->dev;
8350 struct niu_vpd *vpd = &np->vpd;
8353 if (!is_valid_ether_addr(&vpd->local_mac[0])) {
8354 dev_err(np->device, "VPD MAC invalid, falling back to SPROM\n");
8356 np->flags &= ~NIU_FLAGS_VPD_VALID;
8360 if (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR) ||
8361 !strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) {
8362 np->flags |= NIU_FLAGS_10G;
8363 np->flags &= ~NIU_FLAGS_FIBER;
8364 np->flags |= NIU_FLAGS_XCVR_SERDES;
8365 np->mac_xcvr = MAC_XCVR_PCS;
8367 np->flags |= NIU_FLAGS_FIBER;
8368 np->flags &= ~NIU_FLAGS_10G;
8370 if (np->flags & NIU_FLAGS_10G)
8371 np->mac_xcvr = MAC_XCVR_XPCS;
8372 } else if (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) {
8373 np->flags |= (NIU_FLAGS_10G | NIU_FLAGS_FIBER |
8374 NIU_FLAGS_HOTPLUG_PHY);
8375 } else if (niu_phy_type_prop_decode(np, np->vpd.phy_type)) {
8376 dev_err(np->device, "Illegal phy string [%s]\n",
8378 dev_err(np->device, "Falling back to SPROM\n");
8379 np->flags &= ~NIU_FLAGS_VPD_VALID;
8383 memcpy(dev->perm_addr, vpd->local_mac, ETH_ALEN);
8385 val8 = dev->perm_addr[5];
8386 dev->perm_addr[5] += np->port;
8387 if (dev->perm_addr[5] < val8)
8388 dev->perm_addr[4]++;
8390 memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len);
8393 static int __devinit niu_pci_probe_sprom(struct niu *np)
8395 struct net_device *dev = np->dev;
8400 val = (nr64(ESPC_VER_IMGSZ) & ESPC_VER_IMGSZ_IMGSZ);
8401 val >>= ESPC_VER_IMGSZ_IMGSZ_SHIFT;
8404 np->eeprom_len = len;
8406 netif_printk(np, probe, KERN_DEBUG, np->dev,
8407 "SPROM: Image size %llu\n", (unsigned long long)val);
8410 for (i = 0; i < len; i++) {
8411 val = nr64(ESPC_NCR(i));
8412 sum += (val >> 0) & 0xff;
8413 sum += (val >> 8) & 0xff;
8414 sum += (val >> 16) & 0xff;
8415 sum += (val >> 24) & 0xff;
8417 netif_printk(np, probe, KERN_DEBUG, np->dev,
8418 "SPROM: Checksum %x\n", (int)(sum & 0xff));
8419 if ((sum & 0xff) != 0xab) {
8420 dev_err(np->device, "Bad SPROM checksum (%x, should be 0xab)\n", (int)(sum & 0xff));
8424 val = nr64(ESPC_PHY_TYPE);
8427 val8 = (val & ESPC_PHY_TYPE_PORT0) >>
8428 ESPC_PHY_TYPE_PORT0_SHIFT;
8431 val8 = (val & ESPC_PHY_TYPE_PORT1) >>
8432 ESPC_PHY_TYPE_PORT1_SHIFT;
8435 val8 = (val & ESPC_PHY_TYPE_PORT2) >>
8436 ESPC_PHY_TYPE_PORT2_SHIFT;
8439 val8 = (val & ESPC_PHY_TYPE_PORT3) >>
8440 ESPC_PHY_TYPE_PORT3_SHIFT;
8443 dev_err(np->device, "Bogus port number %u\n",
8447 netif_printk(np, probe, KERN_DEBUG, np->dev,
8448 "SPROM: PHY type %x\n", val8);
8451 case ESPC_PHY_TYPE_1G_COPPER:
8452 /* 1G copper, MII */
8453 np->flags &= ~(NIU_FLAGS_FIBER |
8455 np->mac_xcvr = MAC_XCVR_MII;
8458 case ESPC_PHY_TYPE_1G_FIBER:
8460 np->flags &= ~NIU_FLAGS_10G;
8461 np->flags |= NIU_FLAGS_FIBER;
8462 np->mac_xcvr = MAC_XCVR_PCS;
8465 case ESPC_PHY_TYPE_10G_COPPER:
8466 /* 10G copper, XPCS */
8467 np->flags |= NIU_FLAGS_10G;
8468 np->flags &= ~NIU_FLAGS_FIBER;
8469 np->mac_xcvr = MAC_XCVR_XPCS;
8472 case ESPC_PHY_TYPE_10G_FIBER:
8473 /* 10G fiber, XPCS */
8474 np->flags |= (NIU_FLAGS_10G |
8476 np->mac_xcvr = MAC_XCVR_XPCS;
8480 dev_err(np->device, "Bogus SPROM phy type %u\n", val8);
8484 val = nr64(ESPC_MAC_ADDR0);
8485 netif_printk(np, probe, KERN_DEBUG, np->dev,
8486 "SPROM: MAC_ADDR0[%08llx]\n", (unsigned long long)val);
8487 dev->perm_addr[0] = (val >> 0) & 0xff;
8488 dev->perm_addr[1] = (val >> 8) & 0xff;
8489 dev->perm_addr[2] = (val >> 16) & 0xff;
8490 dev->perm_addr[3] = (val >> 24) & 0xff;
8492 val = nr64(ESPC_MAC_ADDR1);
8493 netif_printk(np, probe, KERN_DEBUG, np->dev,
8494 "SPROM: MAC_ADDR1[%08llx]\n", (unsigned long long)val);
8495 dev->perm_addr[4] = (val >> 0) & 0xff;
8496 dev->perm_addr[5] = (val >> 8) & 0xff;
8498 if (!is_valid_ether_addr(&dev->perm_addr[0])) {
8499 dev_err(np->device, "SPROM MAC address invalid [ %pM ]\n",
8504 val8 = dev->perm_addr[5];
8505 dev->perm_addr[5] += np->port;
8506 if (dev->perm_addr[5] < val8)
8507 dev->perm_addr[4]++;
8509 memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len);
8511 val = nr64(ESPC_MOD_STR_LEN);
8512 netif_printk(np, probe, KERN_DEBUG, np->dev,
8513 "SPROM: MOD_STR_LEN[%llu]\n", (unsigned long long)val);
8517 for (i = 0; i < val; i += 4) {
8518 u64 tmp = nr64(ESPC_NCR(5 + (i / 4)));
8520 np->vpd.model[i + 3] = (tmp >> 0) & 0xff;
8521 np->vpd.model[i + 2] = (tmp >> 8) & 0xff;
8522 np->vpd.model[i + 1] = (tmp >> 16) & 0xff;
8523 np->vpd.model[i + 0] = (tmp >> 24) & 0xff;
8525 np->vpd.model[val] = '\0';
8527 val = nr64(ESPC_BD_MOD_STR_LEN);
8528 netif_printk(np, probe, KERN_DEBUG, np->dev,
8529 "SPROM: BD_MOD_STR_LEN[%llu]\n", (unsigned long long)val);
8533 for (i = 0; i < val; i += 4) {
8534 u64 tmp = nr64(ESPC_NCR(14 + (i / 4)));
8536 np->vpd.board_model[i + 3] = (tmp >> 0) & 0xff;
8537 np->vpd.board_model[i + 2] = (tmp >> 8) & 0xff;
8538 np->vpd.board_model[i + 1] = (tmp >> 16) & 0xff;
8539 np->vpd.board_model[i + 0] = (tmp >> 24) & 0xff;
8541 np->vpd.board_model[val] = '\0';
8544 nr64(ESPC_NUM_PORTS_MACS) & ESPC_NUM_PORTS_MACS_VAL;
8545 netif_printk(np, probe, KERN_DEBUG, np->dev,
8546 "SPROM: NUM_PORTS_MACS[%d]\n", np->vpd.mac_num);
8551 static int __devinit niu_get_and_validate_port(struct niu *np)
8553 struct niu_parent *parent = np->parent;
8556 np->flags |= NIU_FLAGS_XMAC;
8558 if (!parent->num_ports) {
8559 if (parent->plat_type == PLAT_TYPE_NIU) {
8560 parent->num_ports = 2;
8562 parent->num_ports = niu_pci_vpd_get_nports(np);
8563 if (!parent->num_ports) {
8564 /* Fall back to SPROM as last resort.
8565 * This will fail on most cards.
8567 parent->num_ports = nr64(ESPC_NUM_PORTS_MACS) &
8568 ESPC_NUM_PORTS_MACS_VAL;
8570 /* All of the current probing methods fail on
8571 * Maramba on-board parts.
8573 if (!parent->num_ports)
8574 parent->num_ports = 4;
8579 if (np->port >= parent->num_ports)
8585 static int __devinit phy_record(struct niu_parent *parent,
8586 struct phy_probe_info *p,
8587 int dev_id_1, int dev_id_2, u8 phy_port,
8590 u32 id = (dev_id_1 << 16) | dev_id_2;
8593 if (dev_id_1 < 0 || dev_id_2 < 0)
8595 if (type == PHY_TYPE_PMA_PMD || type == PHY_TYPE_PCS) {
8596 if (((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM8704) &&
8597 ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_MRVL88X2011) &&
8598 ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM8706))
8601 if ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM5464R)
8605 pr_info("niu%d: Found PHY %08x type %s at phy_port %u\n",
8607 type == PHY_TYPE_PMA_PMD ? "PMA/PMD" :
8608 type == PHY_TYPE_PCS ? "PCS" : "MII",
8611 if (p->cur[type] >= NIU_MAX_PORTS) {
8612 pr_err("Too many PHY ports\n");
8616 p->phy_id[type][idx] = id;
8617 p->phy_port[type][idx] = phy_port;
8618 p->cur[type] = idx + 1;
8622 static int __devinit port_has_10g(struct phy_probe_info *p, int port)
8626 for (i = 0; i < p->cur[PHY_TYPE_PMA_PMD]; i++) {
8627 if (p->phy_port[PHY_TYPE_PMA_PMD][i] == port)
8630 for (i = 0; i < p->cur[PHY_TYPE_PCS]; i++) {
8631 if (p->phy_port[PHY_TYPE_PCS][i] == port)
8638 static int __devinit count_10g_ports(struct phy_probe_info *p, int *lowest)
8644 for (port = 8; port < 32; port++) {
8645 if (port_has_10g(p, port)) {
8655 static int __devinit count_1g_ports(struct phy_probe_info *p, int *lowest)
8658 if (p->cur[PHY_TYPE_MII])
8659 *lowest = p->phy_port[PHY_TYPE_MII][0];
8661 return p->cur[PHY_TYPE_MII];
8664 static void __devinit niu_n2_divide_channels(struct niu_parent *parent)
8666 int num_ports = parent->num_ports;
8669 for (i = 0; i < num_ports; i++) {
8670 parent->rxchan_per_port[i] = (16 / num_ports);
8671 parent->txchan_per_port[i] = (16 / num_ports);
8673 pr_info("niu%d: Port %u [%u RX chans] [%u TX chans]\n",
8675 parent->rxchan_per_port[i],
8676 parent->txchan_per_port[i]);
8680 static void __devinit niu_divide_channels(struct niu_parent *parent,
8681 int num_10g, int num_1g)
8683 int num_ports = parent->num_ports;
8684 int rx_chans_per_10g, rx_chans_per_1g;
8685 int tx_chans_per_10g, tx_chans_per_1g;
8686 int i, tot_rx, tot_tx;
8688 if (!num_10g || !num_1g) {
8689 rx_chans_per_10g = rx_chans_per_1g =
8690 (NIU_NUM_RXCHAN / num_ports);
8691 tx_chans_per_10g = tx_chans_per_1g =
8692 (NIU_NUM_TXCHAN / num_ports);
8694 rx_chans_per_1g = NIU_NUM_RXCHAN / 8;
8695 rx_chans_per_10g = (NIU_NUM_RXCHAN -
8696 (rx_chans_per_1g * num_1g)) /
8699 tx_chans_per_1g = NIU_NUM_TXCHAN / 6;
8700 tx_chans_per_10g = (NIU_NUM_TXCHAN -
8701 (tx_chans_per_1g * num_1g)) /
8705 tot_rx = tot_tx = 0;
8706 for (i = 0; i < num_ports; i++) {
8707 int type = phy_decode(parent->port_phy, i);
8709 if (type == PORT_TYPE_10G) {
8710 parent->rxchan_per_port[i] = rx_chans_per_10g;
8711 parent->txchan_per_port[i] = tx_chans_per_10g;
8713 parent->rxchan_per_port[i] = rx_chans_per_1g;
8714 parent->txchan_per_port[i] = tx_chans_per_1g;
8716 pr_info("niu%d: Port %u [%u RX chans] [%u TX chans]\n",
8718 parent->rxchan_per_port[i],
8719 parent->txchan_per_port[i]);
8720 tot_rx += parent->rxchan_per_port[i];
8721 tot_tx += parent->txchan_per_port[i];
8724 if (tot_rx > NIU_NUM_RXCHAN) {
8725 pr_err("niu%d: Too many RX channels (%d), resetting to one per port\n",
8726 parent->index, tot_rx);
8727 for (i = 0; i < num_ports; i++)
8728 parent->rxchan_per_port[i] = 1;
8730 if (tot_tx > NIU_NUM_TXCHAN) {
8731 pr_err("niu%d: Too many TX channels (%d), resetting to one per port\n",
8732 parent->index, tot_tx);
8733 for (i = 0; i < num_ports; i++)
8734 parent->txchan_per_port[i] = 1;
8736 if (tot_rx < NIU_NUM_RXCHAN || tot_tx < NIU_NUM_TXCHAN) {
8737 pr_warning("niu%d: Driver bug, wasted channels, RX[%d] TX[%d]\n",
8738 parent->index, tot_rx, tot_tx);
8742 static void __devinit niu_divide_rdc_groups(struct niu_parent *parent,
8743 int num_10g, int num_1g)
8745 int i, num_ports = parent->num_ports;
8746 int rdc_group, rdc_groups_per_port;
8747 int rdc_channel_base;
8750 rdc_groups_per_port = NIU_NUM_RDC_TABLES / num_ports;
8752 rdc_channel_base = 0;
8754 for (i = 0; i < num_ports; i++) {
8755 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[i];
8756 int grp, num_channels = parent->rxchan_per_port[i];
8757 int this_channel_offset;
8759 tp->first_table_num = rdc_group;
8760 tp->num_tables = rdc_groups_per_port;
8761 this_channel_offset = 0;
8762 for (grp = 0; grp < tp->num_tables; grp++) {
8763 struct rdc_table *rt = &tp->tables[grp];
8766 pr_info("niu%d: Port %d RDC tbl(%d) [ ",
8767 parent->index, i, tp->first_table_num + grp);
8768 for (slot = 0; slot < NIU_RDC_TABLE_SLOTS; slot++) {
8769 rt->rxdma_channel[slot] =
8770 rdc_channel_base + this_channel_offset;
8772 pr_cont("%d ", rt->rxdma_channel[slot]);
8774 if (++this_channel_offset == num_channels)
8775 this_channel_offset = 0;
8780 parent->rdc_default[i] = rdc_channel_base;
8782 rdc_channel_base += num_channels;
8783 rdc_group += rdc_groups_per_port;
8787 static int __devinit fill_phy_probe_info(struct niu *np,
8788 struct niu_parent *parent,
8789 struct phy_probe_info *info)
8791 unsigned long flags;
8794 memset(info, 0, sizeof(*info));
8796 /* Port 0 to 7 are reserved for onboard Serdes, probe the rest. */
8797 niu_lock_parent(np, flags);
8799 for (port = 8; port < 32; port++) {
8800 int dev_id_1, dev_id_2;
8802 dev_id_1 = mdio_read(np, port,
8803 NIU_PMA_PMD_DEV_ADDR, MII_PHYSID1);
8804 dev_id_2 = mdio_read(np, port,
8805 NIU_PMA_PMD_DEV_ADDR, MII_PHYSID2);
8806 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
8810 dev_id_1 = mdio_read(np, port,
8811 NIU_PCS_DEV_ADDR, MII_PHYSID1);
8812 dev_id_2 = mdio_read(np, port,
8813 NIU_PCS_DEV_ADDR, MII_PHYSID2);
8814 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
8818 dev_id_1 = mii_read(np, port, MII_PHYSID1);
8819 dev_id_2 = mii_read(np, port, MII_PHYSID2);
8820 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
8825 niu_unlock_parent(np, flags);
8830 static int __devinit walk_phys(struct niu *np, struct niu_parent *parent)
8832 struct phy_probe_info *info = &parent->phy_probe_info;
8833 int lowest_10g, lowest_1g;
8834 int num_10g, num_1g;
8838 num_10g = num_1g = 0;
8840 if (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR) ||
8841 !strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) {
8844 parent->plat_type = PLAT_TYPE_ATCA_CP3220;
8845 parent->num_ports = 4;
8846 val = (phy_encode(PORT_TYPE_1G, 0) |
8847 phy_encode(PORT_TYPE_1G, 1) |
8848 phy_encode(PORT_TYPE_1G, 2) |
8849 phy_encode(PORT_TYPE_1G, 3));
8850 } else if (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) {
8853 parent->num_ports = 2;
8854 val = (phy_encode(PORT_TYPE_10G, 0) |
8855 phy_encode(PORT_TYPE_10G, 1));
8856 } else if ((np->flags & NIU_FLAGS_XCVR_SERDES) &&
8857 (parent->plat_type == PLAT_TYPE_NIU)) {
8858 /* this is the Monza case */
8859 if (np->flags & NIU_FLAGS_10G) {
8860 val = (phy_encode(PORT_TYPE_10G, 0) |
8861 phy_encode(PORT_TYPE_10G, 1));
8863 val = (phy_encode(PORT_TYPE_1G, 0) |
8864 phy_encode(PORT_TYPE_1G, 1));
8867 err = fill_phy_probe_info(np, parent, info);
8871 num_10g = count_10g_ports(info, &lowest_10g);
8872 num_1g = count_1g_ports(info, &lowest_1g);
8874 switch ((num_10g << 4) | num_1g) {
8876 if (lowest_1g == 10)
8877 parent->plat_type = PLAT_TYPE_VF_P0;
8878 else if (lowest_1g == 26)
8879 parent->plat_type = PLAT_TYPE_VF_P1;
8881 goto unknown_vg_1g_port;
8885 val = (phy_encode(PORT_TYPE_10G, 0) |
8886 phy_encode(PORT_TYPE_10G, 1) |
8887 phy_encode(PORT_TYPE_1G, 2) |
8888 phy_encode(PORT_TYPE_1G, 3));
8892 val = (phy_encode(PORT_TYPE_10G, 0) |
8893 phy_encode(PORT_TYPE_10G, 1));
8897 val = phy_encode(PORT_TYPE_10G, np->port);
8901 if (lowest_1g == 10)
8902 parent->plat_type = PLAT_TYPE_VF_P0;
8903 else if (lowest_1g == 26)
8904 parent->plat_type = PLAT_TYPE_VF_P1;
8906 goto unknown_vg_1g_port;
8910 if ((lowest_10g & 0x7) == 0)
8911 val = (phy_encode(PORT_TYPE_10G, 0) |
8912 phy_encode(PORT_TYPE_1G, 1) |
8913 phy_encode(PORT_TYPE_1G, 2) |
8914 phy_encode(PORT_TYPE_1G, 3));
8916 val = (phy_encode(PORT_TYPE_1G, 0) |
8917 phy_encode(PORT_TYPE_10G, 1) |
8918 phy_encode(PORT_TYPE_1G, 2) |
8919 phy_encode(PORT_TYPE_1G, 3));
8923 if (lowest_1g == 10)
8924 parent->plat_type = PLAT_TYPE_VF_P0;
8925 else if (lowest_1g == 26)
8926 parent->plat_type = PLAT_TYPE_VF_P1;
8928 goto unknown_vg_1g_port;
8930 val = (phy_encode(PORT_TYPE_1G, 0) |
8931 phy_encode(PORT_TYPE_1G, 1) |
8932 phy_encode(PORT_TYPE_1G, 2) |
8933 phy_encode(PORT_TYPE_1G, 3));
8937 pr_err("Unsupported port config 10G[%d] 1G[%d]\n",
8943 parent->port_phy = val;
8945 if (parent->plat_type == PLAT_TYPE_NIU)
8946 niu_n2_divide_channels(parent);
8948 niu_divide_channels(parent, num_10g, num_1g);
8950 niu_divide_rdc_groups(parent, num_10g, num_1g);
8955 pr_err("Cannot identify platform type, 1gport=%d\n", lowest_1g);
8959 static int __devinit niu_probe_ports(struct niu *np)
8961 struct niu_parent *parent = np->parent;
8964 if (parent->port_phy == PORT_PHY_UNKNOWN) {
8965 err = walk_phys(np, parent);
8969 niu_set_ldg_timer_res(np, 2);
8970 for (i = 0; i <= LDN_MAX; i++)
8971 niu_ldn_irq_enable(np, i, 0);
8974 if (parent->port_phy == PORT_PHY_INVALID)
8980 static int __devinit niu_classifier_swstate_init(struct niu *np)
8982 struct niu_classifier *cp = &np->clas;
8984 cp->tcam_top = (u16) np->port;
8985 cp->tcam_sz = np->parent->tcam_num_entries / np->parent->num_ports;
8986 cp->h1_init = 0xffffffff;
8987 cp->h2_init = 0xffff;
8989 return fflp_early_init(np);
8992 static void __devinit niu_link_config_init(struct niu *np)
8994 struct niu_link_config *lp = &np->link_config;
8996 lp->advertising = (ADVERTISED_10baseT_Half |
8997 ADVERTISED_10baseT_Full |
8998 ADVERTISED_100baseT_Half |
8999 ADVERTISED_100baseT_Full |
9000 ADVERTISED_1000baseT_Half |
9001 ADVERTISED_1000baseT_Full |
9002 ADVERTISED_10000baseT_Full |
9003 ADVERTISED_Autoneg);
9004 lp->speed = lp->active_speed = SPEED_INVALID;
9005 lp->duplex = DUPLEX_FULL;
9006 lp->active_duplex = DUPLEX_INVALID;
9009 lp->loopback_mode = LOOPBACK_MAC;
9010 lp->active_speed = SPEED_10000;
9011 lp->active_duplex = DUPLEX_FULL;
9013 lp->loopback_mode = LOOPBACK_DISABLED;
9017 static int __devinit niu_init_mac_ipp_pcs_base(struct niu *np)
9021 np->mac_regs = np->regs + XMAC_PORT0_OFF;
9022 np->ipp_off = 0x00000;
9023 np->pcs_off = 0x04000;
9024 np->xpcs_off = 0x02000;
9028 np->mac_regs = np->regs + XMAC_PORT1_OFF;
9029 np->ipp_off = 0x08000;
9030 np->pcs_off = 0x0a000;
9031 np->xpcs_off = 0x08000;
9035 np->mac_regs = np->regs + BMAC_PORT2_OFF;
9036 np->ipp_off = 0x04000;
9037 np->pcs_off = 0x0e000;
9038 np->xpcs_off = ~0UL;
9042 np->mac_regs = np->regs + BMAC_PORT3_OFF;
9043 np->ipp_off = 0x0c000;
9044 np->pcs_off = 0x12000;
9045 np->xpcs_off = ~0UL;
9049 dev_err(np->device, "Port %u is invalid, cannot compute MAC block offset\n", np->port);
9056 static void __devinit niu_try_msix(struct niu *np, u8 *ldg_num_map)
9058 struct msix_entry msi_vec[NIU_NUM_LDG];
9059 struct niu_parent *parent = np->parent;
9060 struct pci_dev *pdev = np->pdev;
9061 int i, num_irqs, err;
9064 first_ldg = (NIU_NUM_LDG / parent->num_ports) * np->port;
9065 for (i = 0; i < (NIU_NUM_LDG / parent->num_ports); i++)
9066 ldg_num_map[i] = first_ldg + i;
9068 num_irqs = (parent->rxchan_per_port[np->port] +
9069 parent->txchan_per_port[np->port] +
9070 (np->port == 0 ? 3 : 1));
9071 BUG_ON(num_irqs > (NIU_NUM_LDG / parent->num_ports));
9074 for (i = 0; i < num_irqs; i++) {
9075 msi_vec[i].vector = 0;
9076 msi_vec[i].entry = i;
9079 err = pci_enable_msix(pdev, msi_vec, num_irqs);
9081 np->flags &= ~NIU_FLAGS_MSIX;
9089 np->flags |= NIU_FLAGS_MSIX;
9090 for (i = 0; i < num_irqs; i++)
9091 np->ldg[i].irq = msi_vec[i].vector;
9092 np->num_ldg = num_irqs;
9095 static int __devinit niu_n2_irq_init(struct niu *np, u8 *ldg_num_map)
9097 #ifdef CONFIG_SPARC64
9098 struct platform_device *op = np->op;
9099 const u32 *int_prop;
9102 int_prop = of_get_property(op->dev.of_node, "interrupts", NULL);
9106 for (i = 0; i < op->archdata.num_irqs; i++) {
9107 ldg_num_map[i] = int_prop[i];
9108 np->ldg[i].irq = op->archdata.irqs[i];
9111 np->num_ldg = op->archdata.num_irqs;
9119 static int __devinit niu_ldg_init(struct niu *np)
9121 struct niu_parent *parent = np->parent;
9122 u8 ldg_num_map[NIU_NUM_LDG];
9123 int first_chan, num_chan;
9124 int i, err, ldg_rotor;
9128 np->ldg[0].irq = np->dev->irq;
9129 if (parent->plat_type == PLAT_TYPE_NIU) {
9130 err = niu_n2_irq_init(np, ldg_num_map);
9134 niu_try_msix(np, ldg_num_map);
9137 for (i = 0; i < np->num_ldg; i++) {
9138 struct niu_ldg *lp = &np->ldg[i];
9140 netif_napi_add(np->dev, &lp->napi, niu_poll, 64);
9143 lp->ldg_num = ldg_num_map[i];
9144 lp->timer = 2; /* XXX */
9146 /* On N2 NIU the firmware has setup the SID mappings so they go
9147 * to the correct values that will route the LDG to the proper
9148 * interrupt in the NCU interrupt table.
9150 if (np->parent->plat_type != PLAT_TYPE_NIU) {
9151 err = niu_set_ldg_sid(np, lp->ldg_num, port, i);
9157 /* We adopt the LDG assignment ordering used by the N2 NIU
9158 * 'interrupt' properties because that simplifies a lot of
9159 * things. This ordering is:
9162 * MIF (if port zero)
9163 * SYSERR (if port zero)
9170 err = niu_ldg_assign_ldn(np, parent, ldg_num_map[ldg_rotor],
9176 if (ldg_rotor == np->num_ldg)
9180 err = niu_ldg_assign_ldn(np, parent,
9181 ldg_num_map[ldg_rotor],
9187 if (ldg_rotor == np->num_ldg)
9190 err = niu_ldg_assign_ldn(np, parent,
9191 ldg_num_map[ldg_rotor],
9197 if (ldg_rotor == np->num_ldg)
9203 for (i = 0; i < port; i++)
9204 first_chan += parent->rxchan_per_port[port];
9205 num_chan = parent->rxchan_per_port[port];
9207 for (i = first_chan; i < (first_chan + num_chan); i++) {
9208 err = niu_ldg_assign_ldn(np, parent,
9209 ldg_num_map[ldg_rotor],
9214 if (ldg_rotor == np->num_ldg)
9219 for (i = 0; i < port; i++)
9220 first_chan += parent->txchan_per_port[port];
9221 num_chan = parent->txchan_per_port[port];
9222 for (i = first_chan; i < (first_chan + num_chan); i++) {
9223 err = niu_ldg_assign_ldn(np, parent,
9224 ldg_num_map[ldg_rotor],
9229 if (ldg_rotor == np->num_ldg)
9236 static void __devexit niu_ldg_free(struct niu *np)
9238 if (np->flags & NIU_FLAGS_MSIX)
9239 pci_disable_msix(np->pdev);
9242 static int __devinit niu_get_of_props(struct niu *np)
9244 #ifdef CONFIG_SPARC64
9245 struct net_device *dev = np->dev;
9246 struct device_node *dp;
9247 const char *phy_type;
9252 if (np->parent->plat_type == PLAT_TYPE_NIU)
9253 dp = np->op->dev.of_node;
9255 dp = pci_device_to_OF_node(np->pdev);
9257 phy_type = of_get_property(dp, "phy-type", &prop_len);
9259 netdev_err(dev, "%s: OF node lacks phy-type property\n",
9264 if (!strcmp(phy_type, "none"))
9267 strcpy(np->vpd.phy_type, phy_type);
9269 if (niu_phy_type_prop_decode(np, np->vpd.phy_type)) {
9270 netdev_err(dev, "%s: Illegal phy string [%s]\n",
9271 dp->full_name, np->vpd.phy_type);
9275 mac_addr = of_get_property(dp, "local-mac-address", &prop_len);
9277 netdev_err(dev, "%s: OF node lacks local-mac-address property\n",
9281 if (prop_len != dev->addr_len) {
9282 netdev_err(dev, "%s: OF MAC address prop len (%d) is wrong\n",
9283 dp->full_name, prop_len);
9285 memcpy(dev->perm_addr, mac_addr, dev->addr_len);
9286 if (!is_valid_ether_addr(&dev->perm_addr[0])) {
9287 netdev_err(dev, "%s: OF MAC address is invalid\n",
9289 netdev_err(dev, "%s: [ %pM ]\n", dp->full_name, dev->perm_addr);
9293 memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len);
9295 model = of_get_property(dp, "model", &prop_len);
9298 strcpy(np->vpd.model, model);
9300 if (of_find_property(dp, "hot-swappable-phy", &prop_len)) {
9301 np->flags |= (NIU_FLAGS_10G | NIU_FLAGS_FIBER |
9302 NIU_FLAGS_HOTPLUG_PHY);
9311 static int __devinit niu_get_invariants(struct niu *np)
9313 int err, have_props;
9316 err = niu_get_of_props(np);
9322 err = niu_init_mac_ipp_pcs_base(np);
9327 err = niu_get_and_validate_port(np);
9332 if (np->parent->plat_type == PLAT_TYPE_NIU)
9335 nw64(ESPC_PIO_EN, ESPC_PIO_EN_ENABLE);
9336 offset = niu_pci_vpd_offset(np);
9337 netif_printk(np, probe, KERN_DEBUG, np->dev,
9338 "%s() VPD offset [%08x]\n", __func__, offset);
9340 niu_pci_vpd_fetch(np, offset);
9341 nw64(ESPC_PIO_EN, 0);
9343 if (np->flags & NIU_FLAGS_VPD_VALID) {
9344 niu_pci_vpd_validate(np);
9345 err = niu_get_and_validate_port(np);
9350 if (!(np->flags & NIU_FLAGS_VPD_VALID)) {
9351 err = niu_get_and_validate_port(np);
9354 err = niu_pci_probe_sprom(np);
9360 err = niu_probe_ports(np);
9366 niu_classifier_swstate_init(np);
9367 niu_link_config_init(np);
9369 err = niu_determine_phy_disposition(np);
9371 err = niu_init_link(np);
9376 static LIST_HEAD(niu_parent_list);
9377 static DEFINE_MUTEX(niu_parent_lock);
9378 static int niu_parent_index;
9380 static ssize_t show_port_phy(struct device *dev,
9381 struct device_attribute *attr, char *buf)
9383 struct platform_device *plat_dev = to_platform_device(dev);
9384 struct niu_parent *p = plat_dev->dev.platform_data;
9385 u32 port_phy = p->port_phy;
9386 char *orig_buf = buf;
9389 if (port_phy == PORT_PHY_UNKNOWN ||
9390 port_phy == PORT_PHY_INVALID)
9393 for (i = 0; i < p->num_ports; i++) {
9394 const char *type_str;
9397 type = phy_decode(port_phy, i);
9398 if (type == PORT_TYPE_10G)
9403 (i == 0) ? "%s" : " %s",
9406 buf += sprintf(buf, "\n");
9407 return buf - orig_buf;
9410 static ssize_t show_plat_type(struct device *dev,
9411 struct device_attribute *attr, char *buf)
9413 struct platform_device *plat_dev = to_platform_device(dev);
9414 struct niu_parent *p = plat_dev->dev.platform_data;
9415 const char *type_str;
9417 switch (p->plat_type) {
9418 case PLAT_TYPE_ATLAS:
9424 case PLAT_TYPE_VF_P0:
9427 case PLAT_TYPE_VF_P1:
9431 type_str = "unknown";
9435 return sprintf(buf, "%s\n", type_str);
9438 static ssize_t __show_chan_per_port(struct device *dev,
9439 struct device_attribute *attr, char *buf,
9442 struct platform_device *plat_dev = to_platform_device(dev);
9443 struct niu_parent *p = plat_dev->dev.platform_data;
9444 char *orig_buf = buf;
9448 arr = (rx ? p->rxchan_per_port : p->txchan_per_port);
9450 for (i = 0; i < p->num_ports; i++) {
9452 (i == 0) ? "%d" : " %d",
9455 buf += sprintf(buf, "\n");
9457 return buf - orig_buf;
9460 static ssize_t show_rxchan_per_port(struct device *dev,
9461 struct device_attribute *attr, char *buf)
9463 return __show_chan_per_port(dev, attr, buf, 1);
9466 static ssize_t show_txchan_per_port(struct device *dev,
9467 struct device_attribute *attr, char *buf)
9469 return __show_chan_per_port(dev, attr, buf, 1);
9472 static ssize_t show_num_ports(struct device *dev,
9473 struct device_attribute *attr, char *buf)
9475 struct platform_device *plat_dev = to_platform_device(dev);
9476 struct niu_parent *p = plat_dev->dev.platform_data;
9478 return sprintf(buf, "%d\n", p->num_ports);
9481 static struct device_attribute niu_parent_attributes[] = {
9482 __ATTR(port_phy, S_IRUGO, show_port_phy, NULL),
9483 __ATTR(plat_type, S_IRUGO, show_plat_type, NULL),
9484 __ATTR(rxchan_per_port, S_IRUGO, show_rxchan_per_port, NULL),
9485 __ATTR(txchan_per_port, S_IRUGO, show_txchan_per_port, NULL),
9486 __ATTR(num_ports, S_IRUGO, show_num_ports, NULL),
9490 static struct niu_parent * __devinit niu_new_parent(struct niu *np,
9491 union niu_parent_id *id,
9494 struct platform_device *plat_dev;
9495 struct niu_parent *p;
9498 plat_dev = platform_device_register_simple("niu-board", niu_parent_index,
9500 if (IS_ERR(plat_dev))
9503 for (i = 0; attr_name(niu_parent_attributes[i]); i++) {
9504 int err = device_create_file(&plat_dev->dev,
9505 &niu_parent_attributes[i]);
9507 goto fail_unregister;
9510 p = kzalloc(sizeof(*p), GFP_KERNEL);
9512 goto fail_unregister;
9514 p->index = niu_parent_index++;
9516 plat_dev->dev.platform_data = p;
9517 p->plat_dev = plat_dev;
9519 memcpy(&p->id, id, sizeof(*id));
9520 p->plat_type = ptype;
9521 INIT_LIST_HEAD(&p->list);
9522 atomic_set(&p->refcnt, 0);
9523 list_add(&p->list, &niu_parent_list);
9524 spin_lock_init(&p->lock);
9526 p->rxdma_clock_divider = 7500;
9528 p->tcam_num_entries = NIU_PCI_TCAM_ENTRIES;
9529 if (p->plat_type == PLAT_TYPE_NIU)
9530 p->tcam_num_entries = NIU_NONPCI_TCAM_ENTRIES;
9532 for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_SCTP_IPV6; i++) {
9533 int index = i - CLASS_CODE_USER_PROG1;
9535 p->tcam_key[index] = TCAM_KEY_TSEL;
9536 p->flow_key[index] = (FLOW_KEY_IPSA |
9539 (FLOW_KEY_L4_BYTE12 <<
9540 FLOW_KEY_L4_0_SHIFT) |
9541 (FLOW_KEY_L4_BYTE12 <<
9542 FLOW_KEY_L4_1_SHIFT));
9545 for (i = 0; i < LDN_MAX + 1; i++)
9546 p->ldg_map[i] = LDG_INVALID;
9551 platform_device_unregister(plat_dev);
9555 static struct niu_parent * __devinit niu_get_parent(struct niu *np,
9556 union niu_parent_id *id,
9559 struct niu_parent *p, *tmp;
9560 int port = np->port;
9562 mutex_lock(&niu_parent_lock);
9564 list_for_each_entry(tmp, &niu_parent_list, list) {
9565 if (!memcmp(id, &tmp->id, sizeof(*id))) {
9571 p = niu_new_parent(np, id, ptype);
9577 sprintf(port_name, "port%d", port);
9578 err = sysfs_create_link(&p->plat_dev->dev.kobj,
9582 p->ports[port] = np;
9583 atomic_inc(&p->refcnt);
9586 mutex_unlock(&niu_parent_lock);
9591 static void niu_put_parent(struct niu *np)
9593 struct niu_parent *p = np->parent;
9597 BUG_ON(!p || p->ports[port] != np);
9599 netif_printk(np, probe, KERN_DEBUG, np->dev,
9600 "%s() port[%u]\n", __func__, port);
9602 sprintf(port_name, "port%d", port);
9604 mutex_lock(&niu_parent_lock);
9606 sysfs_remove_link(&p->plat_dev->dev.kobj, port_name);
9608 p->ports[port] = NULL;
9611 if (atomic_dec_and_test(&p->refcnt)) {
9613 platform_device_unregister(p->plat_dev);
9616 mutex_unlock(&niu_parent_lock);
9619 static void *niu_pci_alloc_coherent(struct device *dev, size_t size,
9620 u64 *handle, gfp_t flag)
9625 ret = dma_alloc_coherent(dev, size, &dh, flag);
9631 static void niu_pci_free_coherent(struct device *dev, size_t size,
9632 void *cpu_addr, u64 handle)
9634 dma_free_coherent(dev, size, cpu_addr, handle);
9637 static u64 niu_pci_map_page(struct device *dev, struct page *page,
9638 unsigned long offset, size_t size,
9639 enum dma_data_direction direction)
9641 return dma_map_page(dev, page, offset, size, direction);
9644 static void niu_pci_unmap_page(struct device *dev, u64 dma_address,
9645 size_t size, enum dma_data_direction direction)
9647 dma_unmap_page(dev, dma_address, size, direction);
9650 static u64 niu_pci_map_single(struct device *dev, void *cpu_addr,
9652 enum dma_data_direction direction)
9654 return dma_map_single(dev, cpu_addr, size, direction);
9657 static void niu_pci_unmap_single(struct device *dev, u64 dma_address,
9659 enum dma_data_direction direction)
9661 dma_unmap_single(dev, dma_address, size, direction);
9664 static const struct niu_ops niu_pci_ops = {
9665 .alloc_coherent = niu_pci_alloc_coherent,
9666 .free_coherent = niu_pci_free_coherent,
9667 .map_page = niu_pci_map_page,
9668 .unmap_page = niu_pci_unmap_page,
9669 .map_single = niu_pci_map_single,
9670 .unmap_single = niu_pci_unmap_single,
9673 static void __devinit niu_driver_version(void)
9675 static int niu_version_printed;
9677 if (niu_version_printed++ == 0)
9678 pr_info("%s", version);
9681 static struct net_device * __devinit niu_alloc_and_init(
9682 struct device *gen_dev, struct pci_dev *pdev,
9683 struct platform_device *op, const struct niu_ops *ops,
9686 struct net_device *dev;
9689 dev = alloc_etherdev_mq(sizeof(struct niu), NIU_NUM_TXCHAN);
9691 dev_err(gen_dev, "Etherdev alloc failed, aborting\n");
9695 SET_NETDEV_DEV(dev, gen_dev);
9697 np = netdev_priv(dev);
9701 np->device = gen_dev;
9704 np->msg_enable = niu_debug;
9706 spin_lock_init(&np->lock);
9707 INIT_WORK(&np->reset_task, niu_reset_task);
9714 static const struct net_device_ops niu_netdev_ops = {
9715 .ndo_open = niu_open,
9716 .ndo_stop = niu_close,
9717 .ndo_start_xmit = niu_start_xmit,
9718 .ndo_get_stats64 = niu_get_stats,
9719 .ndo_set_multicast_list = niu_set_rx_mode,
9720 .ndo_validate_addr = eth_validate_addr,
9721 .ndo_set_mac_address = niu_set_mac_addr,
9722 .ndo_do_ioctl = niu_ioctl,
9723 .ndo_tx_timeout = niu_tx_timeout,
9724 .ndo_change_mtu = niu_change_mtu,
9727 static void __devinit niu_assign_netdev_ops(struct net_device *dev)
9729 dev->netdev_ops = &niu_netdev_ops;
9730 dev->ethtool_ops = &niu_ethtool_ops;
9731 dev->watchdog_timeo = NIU_TX_TIMEOUT;
9734 static void __devinit niu_device_announce(struct niu *np)
9736 struct net_device *dev = np->dev;
9738 pr_info("%s: NIU Ethernet %pM\n", dev->name, dev->dev_addr);
9740 if (np->parent->plat_type == PLAT_TYPE_ATCA_CP3220) {
9741 pr_info("%s: Port type[%s] mode[%s:%s] XCVR[%s] phy[%s]\n",
9743 (np->flags & NIU_FLAGS_XMAC ? "XMAC" : "BMAC"),
9744 (np->flags & NIU_FLAGS_10G ? "10G" : "1G"),
9745 (np->flags & NIU_FLAGS_FIBER ? "RGMII FIBER" : "SERDES"),
9746 (np->mac_xcvr == MAC_XCVR_MII ? "MII" :
9747 (np->mac_xcvr == MAC_XCVR_PCS ? "PCS" : "XPCS")),
9750 pr_info("%s: Port type[%s] mode[%s:%s] XCVR[%s] phy[%s]\n",
9752 (np->flags & NIU_FLAGS_XMAC ? "XMAC" : "BMAC"),
9753 (np->flags & NIU_FLAGS_10G ? "10G" : "1G"),
9754 (np->flags & NIU_FLAGS_FIBER ? "FIBER" :
9755 (np->flags & NIU_FLAGS_XCVR_SERDES ? "SERDES" :
9757 (np->mac_xcvr == MAC_XCVR_MII ? "MII" :
9758 (np->mac_xcvr == MAC_XCVR_PCS ? "PCS" : "XPCS")),
9763 static void __devinit niu_set_basic_features(struct net_device *dev)
9765 dev->hw_features = NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_RXHASH;
9766 dev->features |= dev->hw_features | NETIF_F_RXCSUM;
9769 static int __devinit niu_pci_init_one(struct pci_dev *pdev,
9770 const struct pci_device_id *ent)
9772 union niu_parent_id parent_id;
9773 struct net_device *dev;
9779 niu_driver_version();
9781 err = pci_enable_device(pdev);
9783 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
9787 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM) ||
9788 !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
9789 dev_err(&pdev->dev, "Cannot find proper PCI device base addresses, aborting\n");
9791 goto err_out_disable_pdev;
9794 err = pci_request_regions(pdev, DRV_MODULE_NAME);
9796 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
9797 goto err_out_disable_pdev;
9800 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
9802 dev_err(&pdev->dev, "Cannot find PCI Express capability, aborting\n");
9803 goto err_out_free_res;
9806 dev = niu_alloc_and_init(&pdev->dev, pdev, NULL,
9807 &niu_pci_ops, PCI_FUNC(pdev->devfn));
9810 goto err_out_free_res;
9812 np = netdev_priv(dev);
9814 memset(&parent_id, 0, sizeof(parent_id));
9815 parent_id.pci.domain = pci_domain_nr(pdev->bus);
9816 parent_id.pci.bus = pdev->bus->number;
9817 parent_id.pci.device = PCI_SLOT(pdev->devfn);
9819 np->parent = niu_get_parent(np, &parent_id,
9823 goto err_out_free_dev;
9826 pci_read_config_word(pdev, pos + PCI_EXP_DEVCTL, &val16);
9827 val16 &= ~PCI_EXP_DEVCTL_NOSNOOP_EN;
9828 val16 |= (PCI_EXP_DEVCTL_CERE |
9829 PCI_EXP_DEVCTL_NFERE |
9830 PCI_EXP_DEVCTL_FERE |
9831 PCI_EXP_DEVCTL_URRE |
9832 PCI_EXP_DEVCTL_RELAX_EN);
9833 pci_write_config_word(pdev, pos + PCI_EXP_DEVCTL, val16);
9835 dma_mask = DMA_BIT_MASK(44);
9836 err = pci_set_dma_mask(pdev, dma_mask);
9838 dev->features |= NETIF_F_HIGHDMA;
9839 err = pci_set_consistent_dma_mask(pdev, dma_mask);
9841 dev_err(&pdev->dev, "Unable to obtain 44 bit DMA for consistent allocations, aborting\n");
9842 goto err_out_release_parent;
9845 if (err || dma_mask == DMA_BIT_MASK(32)) {
9846 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
9848 dev_err(&pdev->dev, "No usable DMA configuration, aborting\n");
9849 goto err_out_release_parent;
9853 niu_set_basic_features(dev);
9855 np->regs = pci_ioremap_bar(pdev, 0);
9857 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
9859 goto err_out_release_parent;
9862 pci_set_master(pdev);
9863 pci_save_state(pdev);
9865 dev->irq = pdev->irq;
9867 niu_assign_netdev_ops(dev);
9869 err = niu_get_invariants(np);
9872 dev_err(&pdev->dev, "Problem fetching invariants of chip, aborting\n");
9873 goto err_out_iounmap;
9876 err = register_netdev(dev);
9878 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
9879 goto err_out_iounmap;
9882 pci_set_drvdata(pdev, dev);
9884 niu_device_announce(np);
9894 err_out_release_parent:
9901 pci_release_regions(pdev);
9903 err_out_disable_pdev:
9904 pci_disable_device(pdev);
9905 pci_set_drvdata(pdev, NULL);
9910 static void __devexit niu_pci_remove_one(struct pci_dev *pdev)
9912 struct net_device *dev = pci_get_drvdata(pdev);
9915 struct niu *np = netdev_priv(dev);
9917 unregister_netdev(dev);
9928 pci_release_regions(pdev);
9929 pci_disable_device(pdev);
9930 pci_set_drvdata(pdev, NULL);
9934 static int niu_suspend(struct pci_dev *pdev, pm_message_t state)
9936 struct net_device *dev = pci_get_drvdata(pdev);
9937 struct niu *np = netdev_priv(dev);
9938 unsigned long flags;
9940 if (!netif_running(dev))
9943 flush_work_sync(&np->reset_task);
9946 del_timer_sync(&np->timer);
9948 spin_lock_irqsave(&np->lock, flags);
9949 niu_enable_interrupts(np, 0);
9950 spin_unlock_irqrestore(&np->lock, flags);
9952 netif_device_detach(dev);
9954 spin_lock_irqsave(&np->lock, flags);
9956 spin_unlock_irqrestore(&np->lock, flags);
9958 pci_save_state(pdev);
9963 static int niu_resume(struct pci_dev *pdev)
9965 struct net_device *dev = pci_get_drvdata(pdev);
9966 struct niu *np = netdev_priv(dev);
9967 unsigned long flags;
9970 if (!netif_running(dev))
9973 pci_restore_state(pdev);
9975 netif_device_attach(dev);
9977 spin_lock_irqsave(&np->lock, flags);
9979 err = niu_init_hw(np);
9981 np->timer.expires = jiffies + HZ;
9982 add_timer(&np->timer);
9983 niu_netif_start(np);
9986 spin_unlock_irqrestore(&np->lock, flags);
9991 static struct pci_driver niu_pci_driver = {
9992 .name = DRV_MODULE_NAME,
9993 .id_table = niu_pci_tbl,
9994 .probe = niu_pci_init_one,
9995 .remove = __devexit_p(niu_pci_remove_one),
9996 .suspend = niu_suspend,
9997 .resume = niu_resume,
10000 #ifdef CONFIG_SPARC64
10001 static void *niu_phys_alloc_coherent(struct device *dev, size_t size,
10002 u64 *dma_addr, gfp_t flag)
10004 unsigned long order = get_order(size);
10005 unsigned long page = __get_free_pages(flag, order);
10009 memset((char *)page, 0, PAGE_SIZE << order);
10010 *dma_addr = __pa(page);
10012 return (void *) page;
10015 static void niu_phys_free_coherent(struct device *dev, size_t size,
10016 void *cpu_addr, u64 handle)
10018 unsigned long order = get_order(size);
10020 free_pages((unsigned long) cpu_addr, order);
10023 static u64 niu_phys_map_page(struct device *dev, struct page *page,
10024 unsigned long offset, size_t size,
10025 enum dma_data_direction direction)
10027 return page_to_phys(page) + offset;
10030 static void niu_phys_unmap_page(struct device *dev, u64 dma_address,
10031 size_t size, enum dma_data_direction direction)
10033 /* Nothing to do. */
10036 static u64 niu_phys_map_single(struct device *dev, void *cpu_addr,
10038 enum dma_data_direction direction)
10040 return __pa(cpu_addr);
10043 static void niu_phys_unmap_single(struct device *dev, u64 dma_address,
10045 enum dma_data_direction direction)
10047 /* Nothing to do. */
10050 static const struct niu_ops niu_phys_ops = {
10051 .alloc_coherent = niu_phys_alloc_coherent,
10052 .free_coherent = niu_phys_free_coherent,
10053 .map_page = niu_phys_map_page,
10054 .unmap_page = niu_phys_unmap_page,
10055 .map_single = niu_phys_map_single,
10056 .unmap_single = niu_phys_unmap_single,
10059 static int __devinit niu_of_probe(struct platform_device *op)
10061 union niu_parent_id parent_id;
10062 struct net_device *dev;
10067 niu_driver_version();
10069 reg = of_get_property(op->dev.of_node, "reg", NULL);
10071 dev_err(&op->dev, "%s: No 'reg' property, aborting\n",
10072 op->dev.of_node->full_name);
10076 dev = niu_alloc_and_init(&op->dev, NULL, op,
10077 &niu_phys_ops, reg[0] & 0x1);
10082 np = netdev_priv(dev);
10084 memset(&parent_id, 0, sizeof(parent_id));
10085 parent_id.of = of_get_parent(op->dev.of_node);
10087 np->parent = niu_get_parent(np, &parent_id,
10091 goto err_out_free_dev;
10094 niu_set_basic_features(dev);
10096 np->regs = of_ioremap(&op->resource[1], 0,
10097 resource_size(&op->resource[1]),
10100 dev_err(&op->dev, "Cannot map device registers, aborting\n");
10102 goto err_out_release_parent;
10105 np->vir_regs_1 = of_ioremap(&op->resource[2], 0,
10106 resource_size(&op->resource[2]),
10108 if (!np->vir_regs_1) {
10109 dev_err(&op->dev, "Cannot map device vir registers 1, aborting\n");
10111 goto err_out_iounmap;
10114 np->vir_regs_2 = of_ioremap(&op->resource[3], 0,
10115 resource_size(&op->resource[3]),
10117 if (!np->vir_regs_2) {
10118 dev_err(&op->dev, "Cannot map device vir registers 2, aborting\n");
10120 goto err_out_iounmap;
10123 niu_assign_netdev_ops(dev);
10125 err = niu_get_invariants(np);
10127 if (err != -ENODEV)
10128 dev_err(&op->dev, "Problem fetching invariants of chip, aborting\n");
10129 goto err_out_iounmap;
10132 err = register_netdev(dev);
10134 dev_err(&op->dev, "Cannot register net device, aborting\n");
10135 goto err_out_iounmap;
10138 dev_set_drvdata(&op->dev, dev);
10140 niu_device_announce(np);
10145 if (np->vir_regs_1) {
10146 of_iounmap(&op->resource[2], np->vir_regs_1,
10147 resource_size(&op->resource[2]));
10148 np->vir_regs_1 = NULL;
10151 if (np->vir_regs_2) {
10152 of_iounmap(&op->resource[3], np->vir_regs_2,
10153 resource_size(&op->resource[3]));
10154 np->vir_regs_2 = NULL;
10158 of_iounmap(&op->resource[1], np->regs,
10159 resource_size(&op->resource[1]));
10163 err_out_release_parent:
10164 niu_put_parent(np);
10173 static int __devexit niu_of_remove(struct platform_device *op)
10175 struct net_device *dev = dev_get_drvdata(&op->dev);
10178 struct niu *np = netdev_priv(dev);
10180 unregister_netdev(dev);
10182 if (np->vir_regs_1) {
10183 of_iounmap(&op->resource[2], np->vir_regs_1,
10184 resource_size(&op->resource[2]));
10185 np->vir_regs_1 = NULL;
10188 if (np->vir_regs_2) {
10189 of_iounmap(&op->resource[3], np->vir_regs_2,
10190 resource_size(&op->resource[3]));
10191 np->vir_regs_2 = NULL;
10195 of_iounmap(&op->resource[1], np->regs,
10196 resource_size(&op->resource[1]));
10202 niu_put_parent(np);
10205 dev_set_drvdata(&op->dev, NULL);
10210 static const struct of_device_id niu_match[] = {
10213 .compatible = "SUNW,niusl",
10217 MODULE_DEVICE_TABLE(of, niu_match);
10219 static struct platform_driver niu_of_driver = {
10222 .owner = THIS_MODULE,
10223 .of_match_table = niu_match,
10225 .probe = niu_of_probe,
10226 .remove = __devexit_p(niu_of_remove),
10229 #endif /* CONFIG_SPARC64 */
10231 static int __init niu_init(void)
10235 BUILD_BUG_ON(PAGE_SIZE < 4 * 1024);
10237 niu_debug = netif_msg_init(debug, NIU_MSG_DEFAULT);
10239 #ifdef CONFIG_SPARC64
10240 err = platform_driver_register(&niu_of_driver);
10244 err = pci_register_driver(&niu_pci_driver);
10245 #ifdef CONFIG_SPARC64
10247 platform_driver_unregister(&niu_of_driver);
10254 static void __exit niu_exit(void)
10256 pci_unregister_driver(&niu_pci_driver);
10257 #ifdef CONFIG_SPARC64
10258 platform_driver_unregister(&niu_of_driver);
10262 module_init(niu_init);
10263 module_exit(niu_exit);