drivers/net/pcnet32.c

   1 /* pcnet32.c: An AMD PCnet32 ethernet driver for linux. */
   2 /*
   3  *      Copyright 1996-1999 Thomas Bogendoerfer
   4  *
   5  *      Derived from the lance driver written 1993,1994,1995 by Donald Becker.
   6  *
   7  *      Copyright 1993 United States Government as represented by the
   8  *      Director, National Security Agency.
   9  *
  10  *      This software may be used and distributed according to the terms
  11  *      of the GNU General Public License, incorporated herein by reference.
  12  *
  13  *      This driver is for PCnet32 and PCnetPCI based ethercards
  14  */
  15 /**************************************************************************
  16  *  23 Oct, 2000.
  17  *  Fixed a few bugs, related to running the controller in 32bit mode.
  18  *
  19  *  Carsten Langgaard, carstenl@mips.com
  20  *  Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
  21  *
  22  *************************************************************************/
  23
  24 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  25
  26 #define DRV_NAME        "pcnet32"
  27 #define DRV_VERSION     "1.35"
  28 #define DRV_RELDATE     "21.Apr.2008"
  29 #define PFX             DRV_NAME ": "
  30
  31 static const char *const version =
  32     DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " tsbogend@alpha.franken.de\n";
  33
  34 #include <linux/module.h>
  35 #include <linux/kernel.h>
  36 #include <linux/sched.h>
  37 #include <linux/string.h>
  38 #include <linux/errno.h>
  39 #include <linux/ioport.h>
  40 #include <linux/slab.h>
  41 #include <linux/interrupt.h>
  42 #include <linux/pci.h>
  43 #include <linux/delay.h>
  44 #include <linux/init.h>
  45 #include <linux/ethtool.h>
  46 #include <linux/mii.h>
  47 #include <linux/crc32.h>
  48 #include <linux/netdevice.h>
  49 #include <linux/etherdevice.h>
  50 #include <linux/if_ether.h>
  51 #include <linux/skbuff.h>
  52 #include <linux/spinlock.h>
  53 #include <linux/moduleparam.h>
  54 #include <linux/bitops.h>
  55
  56 #include <asm/dma.h>
  57 #include <asm/io.h>
  58 #include <asm/uaccess.h>
  59 #include <asm/irq.h>
  60
  61 /*
  62  * PCI device identifiers for "new style" Linux PCI Device Drivers
  63  */
  64 static DEFINE_PCI_DEVICE_TABLE(pcnet32_pci_tbl) = {
  65         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE_HOME), },
  66         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE), },
  67
  68         /*
  69          * Adapters that were sold with IBM's RS/6000 or pSeries hardware have
  70          * the incorrect vendor id.
  71          */
  72         { PCI_DEVICE(PCI_VENDOR_ID_TRIDENT, PCI_DEVICE_ID_AMD_LANCE),
  73           .class = (PCI_CLASS_NETWORK_ETHERNET << 8), .class_mask = 0xffff00, },
  74
  75         { }     /* terminate list */
  76 };
  77
  78 MODULE_DEVICE_TABLE(pci, pcnet32_pci_tbl);
  79
  80 static int cards_found;
  81
  82 /*
  83  * VLB I/O addresses
  84  */
  85 static unsigned int pcnet32_portlist[] __initdata =
  86     { 0x300, 0x320, 0x340, 0x360, 0 };
  87
  88 static int pcnet32_debug = 0;
  89 static int tx_start = 1;        /* Mapping -- 0:20, 1:64, 2:128, 3:~220 (depends on chip vers) */
  90 static int pcnet32vlb;          /* check for VLB cards ? */
  91
  92 static struct net_device *pcnet32_dev;
  93
  94 static int max_interrupt_work = 2;
  95 static int rx_copybreak = 200;
  96
  97 #define PCNET32_PORT_AUI      0x00
  98 #define PCNET32_PORT_10BT     0x01
  99 #define PCNET32_PORT_GPSI     0x02
 100 #define PCNET32_PORT_MII      0x03
 101
 102 #define PCNET32_PORT_PORTSEL  0x03
 103 #define PCNET32_PORT_ASEL     0x04
 104 #define PCNET32_PORT_100      0x40
 105 #define PCNET32_PORT_FD       0x80
 106
 107 #define PCNET32_DMA_MASK 0xffffffff
 108
 109 #define PCNET32_WATCHDOG_TIMEOUT (jiffies + (2 * HZ))
 110 #define PCNET32_BLINK_TIMEOUT   (jiffies + (HZ/4))
 111
 112 /*
 113  * table to translate option values from tulip
 114  * to internal options
 115  */
 116 static const unsigned char options_mapping[] = {
 117         PCNET32_PORT_ASEL,                      /*  0 Auto-select      */
 118         PCNET32_PORT_AUI,                       /*  1 BNC/AUI          */
 119         PCNET32_PORT_AUI,                       /*  2 AUI/BNC          */
 120         PCNET32_PORT_ASEL,                      /*  3 not supported    */
 121         PCNET32_PORT_10BT | PCNET32_PORT_FD,    /*  4 10baseT-FD       */
 122         PCNET32_PORT_ASEL,                      /*  5 not supported    */
 123         PCNET32_PORT_ASEL,                      /*  6 not supported    */
 124         PCNET32_PORT_ASEL,                      /*  7 not supported    */
 125         PCNET32_PORT_ASEL,                      /*  8 not supported    */
 126         PCNET32_PORT_MII,                       /*  9 MII 10baseT      */
 127         PCNET32_PORT_MII | PCNET32_PORT_FD,     /* 10 MII 10baseT-FD   */
 128         PCNET32_PORT_MII,                       /* 11 MII (autosel)    */
 129         PCNET32_PORT_10BT,                      /* 12 10BaseT          */
 130         PCNET32_PORT_MII | PCNET32_PORT_100,    /* 13 MII 100BaseTx    */
 131                                                 /* 14 MII 100BaseTx-FD */
 132         PCNET32_PORT_MII | PCNET32_PORT_100 | PCNET32_PORT_FD,
 133         PCNET32_PORT_ASEL                       /* 15 not supported    */
 134 };
 135
 136 static const char pcnet32_gstrings_test[][ETH_GSTRING_LEN] = {
 137         "Loopback test  (offline)"
 138 };
 139
 140 #define PCNET32_TEST_LEN        ARRAY_SIZE(pcnet32_gstrings_test)
 141
 142 #define PCNET32_NUM_REGS 136
 143
 144 #define MAX_UNITS 8             /* More are supported, limit only on options */
 145 static int options[MAX_UNITS];
 146 static int full_duplex[MAX_UNITS];
 147 static int homepna[MAX_UNITS];
 148
 149 /*
 150  *                              Theory of Operation
 151  *
 152  * This driver uses the same software structure as the normal lance
 153  * driver. So look for a verbose description in lance.c. The differences
 154  * to the normal lance driver is the use of the 32bit mode of PCnet32
 155  * and PCnetPCI chips. Because these chips are 32bit chips, there is no
 156  * 16MB limitation and we don't need bounce buffers.
 157  */
 158
 159 /*
 160  * Set the number of Tx and Rx buffers, using Log_2(# buffers).
 161  * Reasonable default values are 4 Tx buffers, and 16 Rx buffers.
 162  * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4).
 163  */
 164 #ifndef PCNET32_LOG_TX_BUFFERS
 165 #define PCNET32_LOG_TX_BUFFERS          4
 166 #define PCNET32_LOG_RX_BUFFERS          5
 167 #define PCNET32_LOG_MAX_TX_BUFFERS      9       /* 2^9 == 512 */
 168 #define PCNET32_LOG_MAX_RX_BUFFERS      9
 169 #endif
 170
 171 #define TX_RING_SIZE            (1 << (PCNET32_LOG_TX_BUFFERS))
 172 #define TX_MAX_RING_SIZE        (1 << (PCNET32_LOG_MAX_TX_BUFFERS))
 173
 174 #define RX_RING_SIZE            (1 << (PCNET32_LOG_RX_BUFFERS))
 175 #define RX_MAX_RING_SIZE        (1 << (PCNET32_LOG_MAX_RX_BUFFERS))
 176
 177 #define PKT_BUF_SKB             1544
 178 /* actual buffer length after being aligned */
 179 #define PKT_BUF_SIZE            (PKT_BUF_SKB - NET_IP_ALIGN)
 180 /* chip wants twos complement of the (aligned) buffer length */
 181 #define NEG_BUF_SIZE            (NET_IP_ALIGN - PKT_BUF_SKB)
 182
 183 /* Offsets from base I/O address. */
 184 #define PCNET32_WIO_RDP         0x10
 185 #define PCNET32_WIO_RAP         0x12
 186 #define PCNET32_WIO_RESET       0x14
 187 #define PCNET32_WIO_BDP         0x16
 188
 189 #define PCNET32_DWIO_RDP        0x10
 190 #define PCNET32_DWIO_RAP        0x14
 191 #define PCNET32_DWIO_RESET      0x18
 192 #define PCNET32_DWIO_BDP        0x1C
 193
 194 #define PCNET32_TOTAL_SIZE      0x20
 195
 196 #define CSR0            0
 197 #define CSR0_INIT       0x1
 198 #define CSR0_START      0x2
 199 #define CSR0_STOP       0x4
 200 #define CSR0_TXPOLL     0x8
 201 #define CSR0_INTEN      0x40
 202 #define CSR0_IDON       0x0100
 203 #define CSR0_NORMAL     (CSR0_START | CSR0_INTEN)
 204 #define PCNET32_INIT_LOW        1
 205 #define PCNET32_INIT_HIGH       2
 206 #define CSR3            3
 207 #define CSR4            4
 208 #define CSR5            5
 209 #define CSR5_SUSPEND    0x0001
 210 #define CSR15           15
 211 #define PCNET32_MC_FILTER       8
 212
 213 #define PCNET32_79C970A 0x2621
 214
 215 /* The PCNET32 Rx and Tx ring descriptors. */
 216 struct pcnet32_rx_head {
 217         __le32  base;
 218         __le16  buf_length;     /* two`s complement of length */
 219         __le16  status;
 220         __le32  msg_length;
 221         __le32  reserved;
 222 };
 223
 224 struct pcnet32_tx_head {
 225         __le32  base;
 226         __le16  length;         /* two`s complement of length */
 227         __le16  status;
 228         __le32  misc;
 229         __le32  reserved;
 230 };
 231
 232 /* The PCNET32 32-Bit initialization block, described in databook. */
 233 struct pcnet32_init_block {
 234         __le16  mode;
 235         __le16  tlen_rlen;
 236         u8      phys_addr[6];
 237         __le16  reserved;
 238         __le32  filter[2];
 239         /* Receive and transmit ring base, along with extra bits. */
 240         __le32  rx_ring;
 241         __le32  tx_ring;
 242 };
 243
 244 /* PCnet32 access functions */
 245 struct pcnet32_access {
 246         u16     (*read_csr) (unsigned long, int);
 247         void    (*write_csr) (unsigned long, int, u16);
 248         u16     (*read_bcr) (unsigned long, int);
 249         void    (*write_bcr) (unsigned long, int, u16);
 250         u16     (*read_rap) (unsigned long);
 251         void    (*write_rap) (unsigned long, u16);
 252         void    (*reset) (unsigned long);
 253 };
 254
 255 /*
 256  * The first field of pcnet32_private is read by the ethernet device
 257  * so the structure should be allocated using pci_alloc_consistent().
 258  */
 259 struct pcnet32_private {
 260         struct pcnet32_init_block *init_block;
 261         /* The Tx and Rx ring entries must be aligned on 16-byte boundaries in 32bit mode. */
 262         struct pcnet32_rx_head  *rx_ring;
 263         struct pcnet32_tx_head  *tx_ring;
 264         dma_addr_t              init_dma_addr;/* DMA address of beginning of the init block,
 265                                    returned by pci_alloc_consistent */
 266         struct pci_dev          *pci_dev;
 267         const char              *name;
 268         /* The saved address of a sent-in-place packet/buffer, for skfree(). */
 269         struct sk_buff          **tx_skbuff;
 270         struct sk_buff          **rx_skbuff;
 271         dma_addr_t              *tx_dma_addr;
 272         dma_addr_t              *rx_dma_addr;
 273         struct pcnet32_access   a;
 274         spinlock_t              lock;           /* Guard lock */
 275         unsigned int            cur_rx, cur_tx; /* The next free ring entry */
 276         unsigned int            rx_ring_size;   /* current rx ring size */
 277         unsigned int            tx_ring_size;   /* current tx ring size */
 278         unsigned int            rx_mod_mask;    /* rx ring modular mask */
 279         unsigned int            tx_mod_mask;    /* tx ring modular mask */
 280         unsigned short          rx_len_bits;
 281         unsigned short          tx_len_bits;
 282         dma_addr_t              rx_ring_dma_addr;
 283         dma_addr_t              tx_ring_dma_addr;
 284         unsigned int            dirty_rx,       /* ring entries to be freed. */
 285                                 dirty_tx;
 286
 287         struct net_device       *dev;
 288         struct napi_struct      napi;
 289         char                    tx_full;
 290         char                    phycount;       /* number of phys found */
 291         int                     options;
 292         unsigned int            shared_irq:1,   /* shared irq possible */
 293                                 dxsuflo:1,   /* disable transmit stop on uflo */
 294                                 mii:1;          /* mii port available */
 295         struct net_device       *next;
 296         struct mii_if_info      mii_if;
 297         struct timer_list       watchdog_timer;
 298         struct timer_list       blink_timer;
 299         u32                     msg_enable;     /* debug message level */
 300
 301         /* each bit indicates an available PHY */
 302         u32                     phymask;
 303         unsigned short          chip_version;   /* which variant this is */
 304 };
 305
 306 static int pcnet32_probe_pci(struct pci_dev *, const struct pci_device_id *);
 307 static int pcnet32_probe1(unsigned long, int, struct pci_dev *);
 308 static int pcnet32_open(struct net_device *);
 309 static int pcnet32_init_ring(struct net_device *);
 310 static netdev_tx_t pcnet32_start_xmit(struct sk_buff *,
 311                                       struct net_device *);
 312 static void pcnet32_tx_timeout(struct net_device *dev);
 313 static irqreturn_t pcnet32_interrupt(int, void *);
 314 static int pcnet32_close(struct net_device *);
 315 static struct net_device_stats *pcnet32_get_stats(struct net_device *);
 316 static void pcnet32_load_multicast(struct net_device *dev);
 317 static void pcnet32_set_multicast_list(struct net_device *);
 318 static int pcnet32_ioctl(struct net_device *, struct ifreq *, int);
 319 static void pcnet32_watchdog(struct net_device *);
 320 static int mdio_read(struct net_device *dev, int phy_id, int reg_num);
 321 static void mdio_write(struct net_device *dev, int phy_id, int reg_num,
 322                        int val);
 323 static void pcnet32_restart(struct net_device *dev, unsigned int csr0_bits);
 324 static void pcnet32_ethtool_test(struct net_device *dev,
 325                                  struct ethtool_test *eth_test, u64 * data);
 326 static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1);
 327 static int pcnet32_phys_id(struct net_device *dev, u32 data);
 328 static void pcnet32_led_blink_callback(struct net_device *dev);
 329 static int pcnet32_get_regs_len(struct net_device *dev);
 330 static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs,
 331                              void *ptr);
 332 static void pcnet32_purge_tx_ring(struct net_device *dev);
 333 static int pcnet32_alloc_ring(struct net_device *dev, const char *name);
 334 static void pcnet32_free_ring(struct net_device *dev);
 335 static void pcnet32_check_media(struct net_device *dev, int verbose);
 336
 337 static u16 pcnet32_wio_read_csr(unsigned long addr, int index)
 338 {
 339         outw(index, addr + PCNET32_WIO_RAP);
 340         return inw(addr + PCNET32_WIO_RDP);
 341 }
 342
 343 static void pcnet32_wio_write_csr(unsigned long addr, int index, u16 val)
 344 {
 345         outw(index, addr + PCNET32_WIO_RAP);
 346         outw(val, addr + PCNET32_WIO_RDP);
 347 }
 348
 349 static u16 pcnet32_wio_read_bcr(unsigned long addr, int index)
 350 {
 351         outw(index, addr + PCNET32_WIO_RAP);
 352         return inw(addr + PCNET32_WIO_BDP);
 353 }
 354
 355 static void pcnet32_wio_write_bcr(unsigned long addr, int index, u16 val)
 356 {
 357         outw(index, addr + PCNET32_WIO_RAP);
 358         outw(val, addr + PCNET32_WIO_BDP);
 359 }
 360
 361 static u16 pcnet32_wio_read_rap(unsigned long addr)
 362 {
 363         return inw(addr + PCNET32_WIO_RAP);
 364 }
 365
 366 static void pcnet32_wio_write_rap(unsigned long addr, u16 val)
 367 {
 368         outw(val, addr + PCNET32_WIO_RAP);
 369 }
 370
 371 static void pcnet32_wio_reset(unsigned long addr)
 372 {
 373         inw(addr + PCNET32_WIO_RESET);
 374 }
 375
 376 static int pcnet32_wio_check(unsigned long addr)
 377 {
 378         outw(88, addr + PCNET32_WIO_RAP);
 379         return (inw(addr + PCNET32_WIO_RAP) == 88);
 380 }
 381
 382 static struct pcnet32_access pcnet32_wio = {
 383         .read_csr = pcnet32_wio_read_csr,
 384         .write_csr = pcnet32_wio_write_csr,
 385         .read_bcr = pcnet32_wio_read_bcr,
 386         .write_bcr = pcnet32_wio_write_bcr,
 387         .read_rap = pcnet32_wio_read_rap,
 388         .write_rap = pcnet32_wio_write_rap,
 389         .reset = pcnet32_wio_reset
 390 };
 391
 392 static u16 pcnet32_dwio_read_csr(unsigned long addr, int index)
 393 {
 394         outl(index, addr + PCNET32_DWIO_RAP);
 395         return (inl(addr + PCNET32_DWIO_RDP) & 0xffff);
 396 }
 397
 398 static void pcnet32_dwio_write_csr(unsigned long addr, int index, u16 val)
 399 {
 400         outl(index, addr + PCNET32_DWIO_RAP);
 401         outl(val, addr + PCNET32_DWIO_RDP);
 402 }
 403
 404 static u16 pcnet32_dwio_read_bcr(unsigned long addr, int index)
 405 {
 406         outl(index, addr + PCNET32_DWIO_RAP);
 407         return (inl(addr + PCNET32_DWIO_BDP) & 0xffff);
 408 }
 409
 410 static void pcnet32_dwio_write_bcr(unsigned long addr, int index, u16 val)
 411 {
 412         outl(index, addr + PCNET32_DWIO_RAP);
 413         outl(val, addr + PCNET32_DWIO_BDP);
 414 }
 415
 416 static u16 pcnet32_dwio_read_rap(unsigned long addr)
 417 {
 418         return (inl(addr + PCNET32_DWIO_RAP) & 0xffff);
 419 }
 420
 421 static void pcnet32_dwio_write_rap(unsigned long addr, u16 val)
 422 {
 423         outl(val, addr + PCNET32_DWIO_RAP);
 424 }
 425
 426 static void pcnet32_dwio_reset(unsigned long addr)
 427 {
 428         inl(addr + PCNET32_DWIO_RESET);
 429 }
 430
 431 static int pcnet32_dwio_check(unsigned long addr)
 432 {
 433         outl(88, addr + PCNET32_DWIO_RAP);
 434         return ((inl(addr + PCNET32_DWIO_RAP) & 0xffff) == 88);
 435 }
 436
 437 static struct pcnet32_access pcnet32_dwio = {
 438         .read_csr = pcnet32_dwio_read_csr,
 439         .write_csr = pcnet32_dwio_write_csr,
 440         .read_bcr = pcnet32_dwio_read_bcr,
 441         .write_bcr = pcnet32_dwio_write_bcr,
 442         .read_rap = pcnet32_dwio_read_rap,
 443         .write_rap = pcnet32_dwio_write_rap,
 444         .reset = pcnet32_dwio_reset
 445 };
 446
 447 static void pcnet32_netif_stop(struct net_device *dev)
 448 {
 449         struct pcnet32_private *lp = netdev_priv(dev);
 450
 451         dev->trans_start = jiffies;
 452         napi_disable(&lp->napi);
 453         netif_tx_disable(dev);
 454 }
 455
 456 static void pcnet32_netif_start(struct net_device *dev)
 457 {
 458         struct pcnet32_private *lp = netdev_priv(dev);
 459         ulong ioaddr = dev->base_addr;
 460         u16 val;
 461
 462         netif_wake_queue(dev);
 463         val = lp->a.read_csr(ioaddr, CSR3);
 464         val &= 0x00ff;
 465         lp->a.write_csr(ioaddr, CSR3, val);
 466         napi_enable(&lp->napi);
 467 }
 468
 469 /*
 470  * Allocate space for the new sized tx ring.
 471  * Free old resources
 472  * Save new resources.
 473  * Any failure keeps old resources.
 474  * Must be called with lp->lock held.
 475  */
 476 static void pcnet32_realloc_tx_ring(struct net_device *dev,
 477                                     struct pcnet32_private *lp,
 478                                     unsigned int size)
 479 {
 480         dma_addr_t new_ring_dma_addr;
 481         dma_addr_t *new_dma_addr_list;
 482         struct pcnet32_tx_head *new_tx_ring;
 483         struct sk_buff **new_skb_list;
 484
 485         pcnet32_purge_tx_ring(dev);
 486
 487         new_tx_ring = pci_alloc_consistent(lp->pci_dev,
 488                                            sizeof(struct pcnet32_tx_head) *
 489                                            (1 << size),
 490                                            &new_ring_dma_addr);
 491         if (new_tx_ring == NULL) {
 492                 netif_err(lp, drv, dev, "Consistent memory allocation failed\n");
 493                 return;
 494         }
 495         memset(new_tx_ring, 0, sizeof(struct pcnet32_tx_head) * (1 << size));
 496
 497         new_dma_addr_list = kcalloc((1 << size), sizeof(dma_addr_t),
 498                                 GFP_ATOMIC);
 499         if (!new_dma_addr_list) {
 500                 netif_err(lp, drv, dev, "Memory allocation failed\n");
 501                 goto free_new_tx_ring;
 502         }
 503
 504         new_skb_list = kcalloc((1 << size), sizeof(struct sk_buff *),
 505                                 GFP_ATOMIC);
 506         if (!new_skb_list) {
 507                 netif_err(lp, drv, dev, "Memory allocation failed\n");
 508                 goto free_new_lists;
 509         }
 510
 511         kfree(lp->tx_skbuff);
 512         kfree(lp->tx_dma_addr);
 513         pci_free_consistent(lp->pci_dev,
 514                             sizeof(struct pcnet32_tx_head) *
 515                             lp->tx_ring_size, lp->tx_ring,
 516                             lp->tx_ring_dma_addr);
 517
 518         lp->tx_ring_size = (1 << size);
 519         lp->tx_mod_mask = lp->tx_ring_size - 1;
 520         lp->tx_len_bits = (size << 12);
 521         lp->tx_ring = new_tx_ring;
 522         lp->tx_ring_dma_addr = new_ring_dma_addr;
 523         lp->tx_dma_addr = new_dma_addr_list;
 524         lp->tx_skbuff = new_skb_list;
 525         return;
 526
 527     free_new_lists:
 528         kfree(new_dma_addr_list);
 529     free_new_tx_ring:
 530         pci_free_consistent(lp->pci_dev,
 531                             sizeof(struct pcnet32_tx_head) *
 532                             (1 << size),
 533                             new_tx_ring,
 534                             new_ring_dma_addr);
 535         return;
 536 }
 537
 538 /*
 539  * Allocate space for the new sized rx ring.
 540  * Re-use old receive buffers.
 541  *   alloc extra buffers
 542  *   free unneeded buffers
 543  *   free unneeded buffers
 544  * Save new resources.
 545  * Any failure keeps old resources.
 546  * Must be called with lp->lock held.
 547  */
 548 static void pcnet32_realloc_rx_ring(struct net_device *dev,
 549                                     struct pcnet32_private *lp,
 550                                     unsigned int size)
 551 {
 552         dma_addr_t new_ring_dma_addr;
 553         dma_addr_t *new_dma_addr_list;
 554         struct pcnet32_rx_head *new_rx_ring;
 555         struct sk_buff **new_skb_list;
 556         int new, overlap;
 557
 558         new_rx_ring = pci_alloc_consistent(lp->pci_dev,
 559                                            sizeof(struct pcnet32_rx_head) *
 560                                            (1 << size),
 561                                            &new_ring_dma_addr);
 562         if (new_rx_ring == NULL) {
 563                 netif_err(lp, drv, dev, "Consistent memory allocation failed\n");
 564                 return;
 565         }
 566         memset(new_rx_ring, 0, sizeof(struct pcnet32_rx_head) * (1 << size));
 567
 568         new_dma_addr_list = kcalloc((1 << size), sizeof(dma_addr_t),
 569                                 GFP_ATOMIC);
 570         if (!new_dma_addr_list) {
 571                 netif_err(lp, drv, dev, "Memory allocation failed\n");
 572                 goto free_new_rx_ring;
 573         }
 574
 575         new_skb_list = kcalloc((1 << size), sizeof(struct sk_buff *),
 576                                 GFP_ATOMIC);
 577         if (!new_skb_list) {
 578                 netif_err(lp, drv, dev, "Memory allocation failed\n");
 579                 goto free_new_lists;
 580         }
 581
 582         /* first copy the current receive buffers */
 583         overlap = min(size, lp->rx_ring_size);
 584         for (new = 0; new < overlap; new++) {
 585                 new_rx_ring[new] = lp->rx_ring[new];
 586                 new_dma_addr_list[new] = lp->rx_dma_addr[new];
 587                 new_skb_list[new] = lp->rx_skbuff[new];
 588         }
 589         /* now allocate any new buffers needed */
 590         for (; new < size; new++ ) {
 591                 struct sk_buff *rx_skbuff;
 592                 new_skb_list[new] = dev_alloc_skb(PKT_BUF_SKB);
 593                 if (!(rx_skbuff = new_skb_list[new])) {
 594                         /* keep the original lists and buffers */
 595                         netif_err(lp, drv, dev, "%s dev_alloc_skb failed\n",
 596                                   __func__);
 597                         goto free_all_new;
 598                 }
 599                 skb_reserve(rx_skbuff, NET_IP_ALIGN);
 600
 601                 new_dma_addr_list[new] =
 602                             pci_map_single(lp->pci_dev, rx_skbuff->data,
 603                                            PKT_BUF_SIZE, PCI_DMA_FROMDEVICE);
 604                 new_rx_ring[new].base = cpu_to_le32(new_dma_addr_list[new]);
 605                 new_rx_ring[new].buf_length = cpu_to_le16(NEG_BUF_SIZE);
 606                 new_rx_ring[new].status = cpu_to_le16(0x8000);
 607         }
 608         /* and free any unneeded buffers */
 609         for (; new < lp->rx_ring_size; new++) {
 610                 if (lp->rx_skbuff[new]) {
 611                         pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[new],
 612                                          PKT_BUF_SIZE, PCI_DMA_FROMDEVICE);
 613                         dev_kfree_skb(lp->rx_skbuff[new]);
 614                 }
 615         }
 616
 617         kfree(lp->rx_skbuff);
 618         kfree(lp->rx_dma_addr);
 619         pci_free_consistent(lp->pci_dev,
 620                             sizeof(struct pcnet32_rx_head) *
 621                             lp->rx_ring_size, lp->rx_ring,
 622                             lp->rx_ring_dma_addr);
 623
 624         lp->rx_ring_size = (1 << size);
 625         lp->rx_mod_mask = lp->rx_ring_size - 1;
 626         lp->rx_len_bits = (size << 4);
 627         lp->rx_ring = new_rx_ring;
 628         lp->rx_ring_dma_addr = new_ring_dma_addr;
 629         lp->rx_dma_addr = new_dma_addr_list;
 630         lp->rx_skbuff = new_skb_list;
 631         return;
 632
 633     free_all_new:
 634         for (; --new >= lp->rx_ring_size; ) {
 635                 if (new_skb_list[new]) {
 636                         pci_unmap_single(lp->pci_dev, new_dma_addr_list[new],
 637                                          PKT_BUF_SIZE, PCI_DMA_FROMDEVICE);
 638                         dev_kfree_skb(new_skb_list[new]);
 639                 }
 640         }
 641         kfree(new_skb_list);
 642     free_new_lists:
 643         kfree(new_dma_addr_list);
 644     free_new_rx_ring:
 645         pci_free_consistent(lp->pci_dev,
 646                             sizeof(struct pcnet32_rx_head) *
 647                             (1 << size),
 648                             new_rx_ring,
 649                             new_ring_dma_addr);
 650         return;
 651 }
 652
 653 static void pcnet32_purge_rx_ring(struct net_device *dev)
 654 {
 655         struct pcnet32_private *lp = netdev_priv(dev);
 656         int i;
 657
 658         /* free all allocated skbuffs */
 659         for (i = 0; i < lp->rx_ring_size; i++) {
 660                 lp->rx_ring[i].status = 0;      /* CPU owns buffer */
 661                 wmb();          /* Make sure adapter sees owner change */
 662                 if (lp->rx_skbuff[i]) {
 663                         pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[i],
 664                                          PKT_BUF_SIZE, PCI_DMA_FROMDEVICE);
 665                         dev_kfree_skb_any(lp->rx_skbuff[i]);
 666                 }
 667                 lp->rx_skbuff[i] = NULL;
 668                 lp->rx_dma_addr[i] = 0;
 669         }
 670 }
 671
 672 #ifdef CONFIG_NET_POLL_CONTROLLER
 673 static void pcnet32_poll_controller(struct net_device *dev)
 674 {
 675         disable_irq(dev->irq);
 676         pcnet32_interrupt(0, dev);
 677         enable_irq(dev->irq);
 678 }
 679 #endif
 680
 681 static int pcnet32_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 682 {
 683         struct pcnet32_private *lp = netdev_priv(dev);
 684         unsigned long flags;
 685         int r = -EOPNOTSUPP;
 686
 687         if (lp->mii) {
 688                 spin_lock_irqsave(&lp->lock, flags);
 689                 mii_ethtool_gset(&lp->mii_if, cmd);
 690                 spin_unlock_irqrestore(&lp->lock, flags);
 691                 r = 0;
 692         }
 693         return r;
 694 }
 695
 696 static int pcnet32_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 697 {
 698         struct pcnet32_private *lp = netdev_priv(dev);
 699         unsigned long flags;
 700         int r = -EOPNOTSUPP;
 701
 702         if (lp->mii) {
 703                 spin_lock_irqsave(&lp->lock, flags);
 704                 r = mii_ethtool_sset(&lp->mii_if, cmd);
 705                 spin_unlock_irqrestore(&lp->lock, flags);
 706         }
 707         return r;
 708 }
 709
 710 static void pcnet32_get_drvinfo(struct net_device *dev,
 711                                 struct ethtool_drvinfo *info)
 712 {
 713         struct pcnet32_private *lp = netdev_priv(dev);
 714
 715         strcpy(info->driver, DRV_NAME);
 716         strcpy(info->version, DRV_VERSION);
 717         if (lp->pci_dev)
 718                 strcpy(info->bus_info, pci_name(lp->pci_dev));
 719         else
 720                 sprintf(info->bus_info, "VLB 0x%lx", dev->base_addr);
 721 }
 722
 723 static u32 pcnet32_get_link(struct net_device *dev)
 724 {
 725         struct pcnet32_private *lp = netdev_priv(dev);
 726         unsigned long flags;
 727         int r;
 728
 729         spin_lock_irqsave(&lp->lock, flags);
 730         if (lp->mii) {
 731                 r = mii_link_ok(&lp->mii_if);
 732         } else if (lp->chip_version >= PCNET32_79C970A) {
 733                 ulong ioaddr = dev->base_addr;  /* card base I/O address */
 734                 r = (lp->a.read_bcr(ioaddr, 4) != 0xc0);
 735         } else {        /* can not detect link on really old chips */
 736                 r = 1;
 737         }
 738         spin_unlock_irqrestore(&lp->lock, flags);
 739
 740         return r;
 741 }
 742
 743 static u32 pcnet32_get_msglevel(struct net_device *dev)
 744 {
 745         struct pcnet32_private *lp = netdev_priv(dev);
 746         return lp->msg_enable;
 747 }
 748
 749 static void pcnet32_set_msglevel(struct net_device *dev, u32 value)
 750 {
 751         struct pcnet32_private *lp = netdev_priv(dev);
 752         lp->msg_enable = value;
 753 }
 754
 755 static int pcnet32_nway_reset(struct net_device *dev)
 756 {
 757         struct pcnet32_private *lp = netdev_priv(dev);
 758         unsigned long flags;
 759         int r = -EOPNOTSUPP;
 760
 761         if (lp->mii) {
 762                 spin_lock_irqsave(&lp->lock, flags);
 763                 r = mii_nway_restart(&lp->mii_if);
 764                 spin_unlock_irqrestore(&lp->lock, flags);
 765         }
 766         return r;
 767 }
 768
 769 static void pcnet32_get_ringparam(struct net_device *dev,
 770                                   struct ethtool_ringparam *ering)
 771 {
 772         struct pcnet32_private *lp = netdev_priv(dev);
 773
 774         ering->tx_max_pending = TX_MAX_RING_SIZE;
 775         ering->tx_pending = lp->tx_ring_size;
 776         ering->rx_max_pending = RX_MAX_RING_SIZE;
 777         ering->rx_pending = lp->rx_ring_size;
 778 }
 779
 780 static int pcnet32_set_ringparam(struct net_device *dev,
 781                                  struct ethtool_ringparam *ering)
 782 {
 783         struct pcnet32_private *lp = netdev_priv(dev);
 784         unsigned long flags;
 785         unsigned int size;
 786         ulong ioaddr = dev->base_addr;
 787         int i;
 788
 789         if (ering->rx_mini_pending || ering->rx_jumbo_pending)
 790                 return -EINVAL;
 791
 792         if (netif_running(dev))
 793                 pcnet32_netif_stop(dev);
 794
 795         spin_lock_irqsave(&lp->lock, flags);
 796         lp->a.write_csr(ioaddr, CSR0, CSR0_STOP);       /* stop the chip */
 797
 798         size = min(ering->tx_pending, (unsigned int)TX_MAX_RING_SIZE);
 799
 800         /* set the minimum ring size to 4, to allow the loopback test to work
 801          * unchanged.
 802          */
 803         for (i = 2; i <= PCNET32_LOG_MAX_TX_BUFFERS; i++) {
 804                 if (size <= (1 << i))
 805                         break;
 806         }
 807         if ((1 << i) != lp->tx_ring_size)
 808                 pcnet32_realloc_tx_ring(dev, lp, i);
 809
 810         size = min(ering->rx_pending, (unsigned int)RX_MAX_RING_SIZE);
 811         for (i = 2; i <= PCNET32_LOG_MAX_RX_BUFFERS; i++) {
 812                 if (size <= (1 << i))
 813                         break;
 814         }
 815         if ((1 << i) != lp->rx_ring_size)
 816                 pcnet32_realloc_rx_ring(dev, lp, i);
 817
 818         lp->napi.weight = lp->rx_ring_size / 2;
 819
 820         if (netif_running(dev)) {
 821                 pcnet32_netif_start(dev);
 822                 pcnet32_restart(dev, CSR0_NORMAL);
 823         }
 824
 825         spin_unlock_irqrestore(&lp->lock, flags);
 826
 827         netif_info(lp, drv, dev, "Ring Param Settings: RX: %d, TX: %d\n",
 828                    lp->rx_ring_size, lp->tx_ring_size);
 829
 830         return 0;
 831 }
 832
 833 static void pcnet32_get_strings(struct net_device *dev, u32 stringset,
 834                                 u8 * data)
 835 {
 836         memcpy(data, pcnet32_gstrings_test, sizeof(pcnet32_gstrings_test));
 837 }
 838
 839 static int pcnet32_get_sset_count(struct net_device *dev, int sset)
 840 {
 841         switch (sset) {
 842         case ETH_SS_TEST:
 843                 return PCNET32_TEST_LEN;
 844         default:
 845                 return -EOPNOTSUPP;
 846         }
 847 }
 848
 849 static void pcnet32_ethtool_test(struct net_device *dev,
 850                                  struct ethtool_test *test, u64 * data)
 851 {
 852         struct pcnet32_private *lp = netdev_priv(dev);
 853         int rc;
 854
 855         if (test->flags == ETH_TEST_FL_OFFLINE) {
 856                 rc = pcnet32_loopback_test(dev, data);
 857                 if (rc) {
 858                         netif_printk(lp, hw, KERN_DEBUG, dev,
 859                                      "Loopback test failed\n");
 860                         test->flags |= ETH_TEST_FL_FAILED;
 861                 } else
 862                         netif_printk(lp, hw, KERN_DEBUG, dev,
 863                                      "Loopback test passed\n");
 864         } else
 865                 netif_printk(lp, hw, KERN_DEBUG, dev,
 866                              "No tests to run (specify 'Offline' on ethtool)\n");
 867 }                               /* end pcnet32_ethtool_test */
 868
 869 static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1)
 870 {
 871         struct pcnet32_private *lp = netdev_priv(dev);
 872         struct pcnet32_access *a = &lp->a;      /* access to registers */
 873         ulong ioaddr = dev->base_addr;  /* card base I/O address */
 874         struct sk_buff *skb;    /* sk buff */
 875         int x, i;               /* counters */
 876         int numbuffs = 4;       /* number of TX/RX buffers and descs */
 877         u16 status = 0x8300;    /* TX ring status */
 878         __le16 teststatus;      /* test of ring status */
 879         int rc;                 /* return code */
 880         int size;               /* size of packets */
 881         unsigned char *packet;  /* source packet data */
 882         static const int data_len = 60; /* length of source packets */
 883         unsigned long flags;
 884         unsigned long ticks;
 885
 886         rc = 1;                 /* default to fail */
 887
 888         if (netif_running(dev))
 889                 pcnet32_netif_stop(dev);
 890
 891         spin_lock_irqsave(&lp->lock, flags);
 892         lp->a.write_csr(ioaddr, CSR0, CSR0_STOP);       /* stop the chip */
 893
 894         numbuffs = min(numbuffs, (int)min(lp->rx_ring_size, lp->tx_ring_size));
 895
 896         /* Reset the PCNET32 */
 897         lp->a.reset(ioaddr);
 898         lp->a.write_csr(ioaddr, CSR4, 0x0915);  /* auto tx pad */
 899
 900         /* switch pcnet32 to 32bit mode */
 901         lp->a.write_bcr(ioaddr, 20, 2);
 902
 903         /* purge & init rings but don't actually restart */
 904         pcnet32_restart(dev, 0x0000);
 905
 906         lp->a.write_csr(ioaddr, CSR0, CSR0_STOP);       /* Set STOP bit */
 907
 908         /* Initialize Transmit buffers. */
 909         size = data_len + 15;
 910         for (x = 0; x < numbuffs; x++) {
 911                 if (!(skb = dev_alloc_skb(size))) {
 912                         netif_printk(lp, hw, KERN_DEBUG, dev,
 913                                      "Cannot allocate skb at line: %d!\n",
 914                                      __LINE__);
 915                         goto clean_up;
 916                 } else {
 917                         packet = skb->data;
 918                         skb_put(skb, size);     /* create space for data */
 919                         lp->tx_skbuff[x] = skb;
 920                         lp->tx_ring[x].length = cpu_to_le16(-skb->len);
 921                         lp->tx_ring[x].misc = 0;
 922
 923                         /* put DA and SA into the skb */
 924                         for (i = 0; i < 6; i++)
 925                                 *packet++ = dev->dev_addr[i];
 926                         for (i = 0; i < 6; i++)
 927                                 *packet++ = dev->dev_addr[i];
 928                         /* type */
 929                         *packet++ = 0x08;
 930                         *packet++ = 0x06;
 931                         /* packet number */
 932                         *packet++ = x;
 933                         /* fill packet with data */
 934                         for (i = 0; i < data_len; i++)
 935                                 *packet++ = i;
 936
 937                         lp->tx_dma_addr[x] =
 938                             pci_map_single(lp->pci_dev, skb->data, skb->len,
 939                                            PCI_DMA_TODEVICE);
 940                         lp->tx_ring[x].base = cpu_to_le32(lp->tx_dma_addr[x]);
 941                         wmb();  /* Make sure owner changes after all others are visible */
 942                         lp->tx_ring[x].status = cpu_to_le16(status);
 943                 }
 944         }
 945
 946         x = a->read_bcr(ioaddr, 32);    /* set internal loopback in BCR32 */
 947         a->write_bcr(ioaddr, 32, x | 0x0002);
 948
 949         /* set int loopback in CSR15 */
 950         x = a->read_csr(ioaddr, CSR15) & 0xfffc;
 951         lp->a.write_csr(ioaddr, CSR15, x | 0x0044);
 952
 953         teststatus = cpu_to_le16(0x8000);
 954         lp->a.write_csr(ioaddr, CSR0, CSR0_START);      /* Set STRT bit */
 955
 956         /* Check status of descriptors */
 957         for (x = 0; x < numbuffs; x++) {
 958                 ticks = 0;
 959                 rmb();
 960                 while ((lp->rx_ring[x].status & teststatus) && (ticks < 200)) {
 961                         spin_unlock_irqrestore(&lp->lock, flags);
 962                         msleep(1);
 963                         spin_lock_irqsave(&lp->lock, flags);
 964                         rmb();
 965                         ticks++;
 966                 }
 967                 if (ticks == 200) {
 968                         netif_err(lp, hw, dev, "Desc %d failed to reset!\n", x);
 969                         break;
 970                 }
 971         }
 972
 973         lp->a.write_csr(ioaddr, CSR0, CSR0_STOP);       /* Set STOP bit */
 974         wmb();
 975         if (netif_msg_hw(lp) && netif_msg_pktdata(lp)) {
 976                 netdev_printk(KERN_DEBUG, dev, "RX loopback packets:\n");
 977
 978                 for (x = 0; x < numbuffs; x++) {
 979                         netdev_printk(KERN_DEBUG, dev, "Packet %d: ", x);
 980                         skb = lp->rx_skbuff[x];
 981                         for (i = 0; i < size; i++) {
 982                                 pr_cont(" %02x", *(skb->data + i));
 983                         }
 984                         pr_cont("\n");
 985                 }
 986         }
 987
 988         x = 0;
 989         rc = 0;
 990         while (x < numbuffs && !rc) {
 991                 skb = lp->rx_skbuff[x];
 992                 packet = lp->tx_skbuff[x]->data;
 993                 for (i = 0; i < size; i++) {
 994                         if (*(skb->data + i) != packet[i]) {
 995                                 netif_printk(lp, hw, KERN_DEBUG, dev,
 996                                              "Error in compare! %2x - %02x %02x\n",
 997                                              i, *(skb->data + i), packet[i]);
 998                                 rc = 1;
 999                                 break;
1000                         }
1001                 }
1002                 x++;
1003         }
1004
1005       clean_up:
1006         *data1 = rc;
1007         pcnet32_purge_tx_ring(dev);
1008
1009         x = a->read_csr(ioaddr, CSR15);
1010         a->write_csr(ioaddr, CSR15, (x & ~0x0044));     /* reset bits 6 and 2 */
1011
1012         x = a->read_bcr(ioaddr, 32);    /* reset internal loopback */
1013         a->write_bcr(ioaddr, 32, (x & ~0x0002));
1014
1015         if (netif_running(dev)) {
1016                 pcnet32_netif_start(dev);
1017                 pcnet32_restart(dev, CSR0_NORMAL);
1018         } else {
1019                 pcnet32_purge_rx_ring(dev);
1020                 lp->a.write_bcr(ioaddr, 20, 4); /* return to 16bit mode */
1021         }
1022         spin_unlock_irqrestore(&lp->lock, flags);
1023
1024         return (rc);
1025 }                               /* end pcnet32_loopback_test  */
1026
1027 static void pcnet32_led_blink_callback(struct net_device *dev)
1028 {
1029         struct pcnet32_private *lp = netdev_priv(dev);
1030         struct pcnet32_access *a = &lp->a;
1031         ulong ioaddr = dev->base_addr;
1032         unsigned long flags;
1033         int i;
1034
1035         spin_lock_irqsave(&lp->lock, flags);
1036         for (i = 4; i < 8; i++) {
1037                 a->write_bcr(ioaddr, i, a->read_bcr(ioaddr, i) ^ 0x4000);
1038         }
1039         spin_unlock_irqrestore(&lp->lock, flags);
1040
1041         mod_timer(&lp->blink_timer, PCNET32_BLINK_TIMEOUT);
1042 }
1043
1044 static int pcnet32_phys_id(struct net_device *dev, u32 data)
1045 {
1046         struct pcnet32_private *lp = netdev_priv(dev);
1047         struct pcnet32_access *a = &lp->a;
1048         ulong ioaddr = dev->base_addr;
1049         unsigned long flags;
1050         int i, regs[4];
1051
1052         if (!lp->blink_timer.function) {
1053                 init_timer(&lp->blink_timer);
1054                 lp->blink_timer.function = (void *)pcnet32_led_blink_callback;
1055                 lp->blink_timer.data = (unsigned long)dev;
1056         }
1057
1058         /* Save the current value of the bcrs */
1059         spin_lock_irqsave(&lp->lock, flags);
1060         for (i = 4; i < 8; i++) {
1061                 regs[i - 4] = a->read_bcr(ioaddr, i);
1062         }
1063         spin_unlock_irqrestore(&lp->lock, flags);
1064
1065         mod_timer(&lp->blink_timer, jiffies);
1066         set_current_state(TASK_INTERRUPTIBLE);
1067
1068         /* AV: the limit here makes no sense whatsoever */
1069         if ((!data) || (data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ)))
1070                 data = (u32) (MAX_SCHEDULE_TIMEOUT / HZ);
1071
1072         msleep_interruptible(data * 1000);
1073         del_timer_sync(&lp->blink_timer);
1074
1075         /* Restore the original value of the bcrs */
1076         spin_lock_irqsave(&lp->lock, flags);
1077         for (i = 4; i < 8; i++) {
1078                 a->write_bcr(ioaddr, i, regs[i - 4]);
1079         }
1080         spin_unlock_irqrestore(&lp->lock, flags);
1081
1082         return 0;
1083 }
1084
1085 /*
1086  * lp->lock must be held.
1087  */
1088 static int pcnet32_suspend(struct net_device *dev, unsigned long *flags,
1089                 int can_sleep)
1090 {
1091         int csr5;
1092         struct pcnet32_private *lp = netdev_priv(dev);
1093         struct pcnet32_access *a = &lp->a;
1094         ulong ioaddr = dev->base_addr;
1095         int ticks;
1096
1097         /* really old chips have to be stopped. */
1098         if (lp->chip_version < PCNET32_79C970A)
1099                 return 0;
1100
1101         /* set SUSPEND (SPND) - CSR5 bit 0 */
1102         csr5 = a->read_csr(ioaddr, CSR5);
1103         a->write_csr(ioaddr, CSR5, csr5 | CSR5_SUSPEND);
1104
1105         /* poll waiting for bit to be set */
1106         ticks = 0;
1107         while (!(a->read_csr(ioaddr, CSR5) & CSR5_SUSPEND)) {
1108                 spin_unlock_irqrestore(&lp->lock, *flags);
1109                 if (can_sleep)
1110                         msleep(1);
1111                 else
1112                         mdelay(1);
1113                 spin_lock_irqsave(&lp->lock, *flags);
1114                 ticks++;
1115                 if (ticks > 200) {
1116                         netif_printk(lp, hw, KERN_DEBUG, dev,
1117                                      "Error getting into suspend!\n");
1118                         return 0;
1119                 }
1120         }
1121         return 1;
1122 }
1123
1124 /*
1125  * process one receive descriptor entry
1126  */
1127
1128 static void pcnet32_rx_entry(struct net_device *dev,
1129                              struct pcnet32_private *lp,
1130                              struct pcnet32_rx_head *rxp,
1131                              int entry)
1132 {
1133         int status = (short)le16_to_cpu(rxp->status) >> 8;
1134         int rx_in_place = 0;
1135         struct sk_buff *skb;
1136         short pkt_len;
1137
1138         if (status != 0x03) {   /* There was an error. */
1139                 /*
1140                  * There is a tricky error noted by John Murphy,
1141                  * <murf@perftech.com> to Russ Nelson: Even with full-sized
1142                  * buffers it's possible for a jabber packet to use two
1143                  * buffers, with only the last correctly noting the error.
1144                  */
1145                 if (status & 0x01)      /* Only count a general error at the */
1146                         dev->stats.rx_errors++; /* end of a packet. */
1147                 if (status & 0x20)
1148                         dev->stats.rx_frame_errors++;
1149                 if (status & 0x10)
1150                         dev->stats.rx_over_errors++;
1151                 if (status & 0x08)
1152                         dev->stats.rx_crc_errors++;
1153                 if (status & 0x04)
1154                         dev->stats.rx_fifo_errors++;
1155                 return;
1156         }
1157
1158         pkt_len = (le32_to_cpu(rxp->msg_length) & 0xfff) - 4;
1159
1160         /* Discard oversize frames. */
1161         if (unlikely(pkt_len > PKT_BUF_SIZE)) {
1162                 netif_err(lp, drv, dev, "Impossible packet size %d!\n",
1163                           pkt_len);
1164                 dev->stats.rx_errors++;
1165                 return;
1166         }
1167         if (pkt_len < 60) {
1168                 netif_err(lp, rx_err, dev, "Runt packet!\n");
1169                 dev->stats.rx_errors++;
1170                 return;
1171         }
1172
1173         if (pkt_len > rx_copybreak) {
1174                 struct sk_buff *newskb;
1175
1176                 if ((newskb = dev_alloc_skb(PKT_BUF_SKB))) {
1177                         skb_reserve(newskb, NET_IP_ALIGN);
1178                         skb = lp->rx_skbuff[entry];
1179                         pci_unmap_single(lp->pci_dev,
1180                                          lp->rx_dma_addr[entry],
1181                                          PKT_BUF_SIZE,
1182                                          PCI_DMA_FROMDEVICE);
1183                         skb_put(skb, pkt_len);
1184                         lp->rx_skbuff[entry] = newskb;
1185                         lp->rx_dma_addr[entry] =
1186                                             pci_map_single(lp->pci_dev,
1187                                                            newskb->data,
1188                                                            PKT_BUF_SIZE,
1189                                                            PCI_DMA_FROMDEVICE);
1190                         rxp->base = cpu_to_le32(lp->rx_dma_addr[entry]);
1191                         rx_in_place = 1;
1192                 } else
1193                         skb = NULL;
1194         } else {
1195                 skb = dev_alloc_skb(pkt_len + NET_IP_ALIGN);
1196         }
1197
1198         if (skb == NULL) {
1199                 netif_err(lp, drv, dev, "Memory squeeze, dropping packet\n");
1200                 dev->stats.rx_dropped++;
1201                 return;
1202         }
1203         if (!rx_in_place) {
1204                 skb_reserve(skb, NET_IP_ALIGN);
1205                 skb_put(skb, pkt_len);  /* Make room */
1206                 pci_dma_sync_single_for_cpu(lp->pci_dev,
1207                                             lp->rx_dma_addr[entry],
1208                                             pkt_len,
1209                                             PCI_DMA_FROMDEVICE);
1210                 skb_copy_to_linear_data(skb,
1211                                  (unsigned char *)(lp->rx_skbuff[entry]->data),
1212                                  pkt_len);
1213                 pci_dma_sync_single_for_device(lp->pci_dev,
1214                                                lp->rx_dma_addr[entry],
1215                                                pkt_len,
1216                                                PCI_DMA_FROMDEVICE);
1217         }
1218         dev->stats.rx_bytes += skb->len;
1219         skb->protocol = eth_type_trans(skb, dev);
1220         netif_receive_skb(skb);
1221         dev->stats.rx_packets++;
1222         return;
1223 }
1224
1225 static int pcnet32_rx(struct net_device *dev, int budget)
1226 {
1227         struct pcnet32_private *lp = netdev_priv(dev);
1228         int entry = lp->cur_rx & lp->rx_mod_mask;
1229         struct pcnet32_rx_head *rxp = &lp->rx_ring[entry];
1230         int npackets = 0;
1231
1232         /* If we own the next entry, it's a new packet. Send it up. */
1233         while (npackets < budget && (short)le16_to_cpu(rxp->status) >= 0) {
1234                 pcnet32_rx_entry(dev, lp, rxp, entry);
1235                 npackets += 1;
1236                 /*
1237                  * The docs say that the buffer length isn't touched, but Andrew
1238                  * Boyd of QNX reports that some revs of the 79C965 clear it.
1239                  */
1240                 rxp->buf_length = cpu_to_le16(NEG_BUF_SIZE);
1241                 wmb();  /* Make sure owner changes after others are visible */
1242                 rxp->status = cpu_to_le16(0x8000);
1243                 entry = (++lp->cur_rx) & lp->rx_mod_mask;
1244                 rxp = &lp->rx_ring[entry];
1245         }
1246
1247         return npackets;
1248 }
1249
1250 static int pcnet32_tx(struct net_device *dev)
1251 {
1252         struct pcnet32_private *lp = netdev_priv(dev);
1253         unsigned int dirty_tx = lp->dirty_tx;
1254         int delta;
1255         int must_restart = 0;
1256
1257         while (dirty_tx != lp->cur_tx) {
1258                 int entry = dirty_tx & lp->tx_mod_mask;
1259                 int status = (short)le16_to_cpu(lp->tx_ring[entry].status);
1260
1261                 if (status < 0)
1262                         break;  /* It still hasn't been Txed */
1263
1264                 lp->tx_ring[entry].base = 0;
1265
1266                 if (status & 0x4000) {
1267                         /* There was a major error, log it. */
1268                         int err_status = le32_to_cpu(lp->tx_ring[entry].misc);
1269                         dev->stats.tx_errors++;
1270                         netif_err(lp, tx_err, dev,
1271                                   "Tx error status=%04x err_status=%08x\n",
1272                                   status, err_status);
1273                         if (err_status & 0x04000000)
1274                                 dev->stats.tx_aborted_errors++;
1275                         if (err_status & 0x08000000)
1276                                 dev->stats.tx_carrier_errors++;
1277                         if (err_status & 0x10000000)
1278                                 dev->stats.tx_window_errors++;
1279 #ifndef DO_DXSUFLO
1280                         if (err_status & 0x40000000) {
1281                                 dev->stats.tx_fifo_errors++;
1282                                 /* Ackk!  On FIFO errors the Tx unit is turned off! */
1283                                 /* Remove this verbosity later! */
1284                                 netif_err(lp, tx_err, dev, "Tx FIFO error!\n");
1285                                 must_restart = 1;
1286                         }
1287 #else
1288                         if (err_status & 0x40000000) {
1289                                 dev->stats.tx_fifo_errors++;
1290                                 if (!lp->dxsuflo) {     /* If controller doesn't recover ... */
1291                                         /* Ackk!  On FIFO errors the Tx unit is turned off! */
1292                                         /* Remove this verbosity later! */
1293                                         netif_err(lp, tx_err, dev, "Tx FIFO error!\n");
1294                                         must_restart = 1;
1295                                 }
1296                         }
1297 #endif
1298                 } else {
1299                         if (status & 0x1800)
1300                                 dev->stats.collisions++;
1301                         dev->stats.tx_packets++;
1302                 }
1303
1304                 /* We must free the original skb */
1305                 if (lp->tx_skbuff[entry]) {
1306                         pci_unmap_single(lp->pci_dev,
1307                                          lp->tx_dma_addr[entry],
1308                                          lp->tx_skbuff[entry]->
1309                                          len, PCI_DMA_TODEVICE);
1310                         dev_kfree_skb_any(lp->tx_skbuff[entry]);
1311                         lp->tx_skbuff[entry] = NULL;
1312                         lp->tx_dma_addr[entry] = 0;
1313                 }
1314                 dirty_tx++;
1315         }
1316
1317         delta = (lp->cur_tx - dirty_tx) & (lp->tx_mod_mask + lp->tx_ring_size);
1318         if (delta > lp->tx_ring_size) {
1319                 netif_err(lp, drv, dev, "out-of-sync dirty pointer, %d vs. %d, full=%d\n",
1320                           dirty_tx, lp->cur_tx, lp->tx_full);
1321                 dirty_tx += lp->tx_ring_size;
1322                 delta -= lp->tx_ring_size;
1323         }
1324
1325         if (lp->tx_full &&
1326             netif_queue_stopped(dev) &&
1327             delta < lp->tx_ring_size - 2) {
1328                 /* The ring is no longer full, clear tbusy. */
1329                 lp->tx_full = 0;
1330                 netif_wake_queue(dev);
1331         }
1332         lp->dirty_tx = dirty_tx;
1333
1334         return must_restart;
1335 }
1336
1337 static int pcnet32_poll(struct napi_struct *napi, int budget)
1338 {
1339         struct pcnet32_private *lp = container_of(napi, struct pcnet32_private, napi);
1340         struct net_device *dev = lp->dev;
1341         unsigned long ioaddr = dev->base_addr;
1342         unsigned long flags;
1343         int work_done;
1344         u16 val;
1345
1346         work_done = pcnet32_rx(dev, budget);
1347
1348         spin_lock_irqsave(&lp->lock, flags);
1349         if (pcnet32_tx(dev)) {
1350                 /* reset the chip to clear the error condition, then restart */
1351                 lp->a.reset(ioaddr);
1352                 lp->a.write_csr(ioaddr, CSR4, 0x0915);  /* auto tx pad */
1353                 pcnet32_restart(dev, CSR0_START);
1354                 netif_wake_queue(dev);
1355         }
1356         spin_unlock_irqrestore(&lp->lock, flags);
1357
1358         if (work_done < budget) {
1359                 spin_lock_irqsave(&lp->lock, flags);
1360
1361                 __napi_complete(napi);
1362
1363                 /* clear interrupt masks */
1364                 val = lp->a.read_csr(ioaddr, CSR3);
1365                 val &= 0x00ff;
1366                 lp->a.write_csr(ioaddr, CSR3, val);
1367
1368                 /* Set interrupt enable. */
1369                 lp->a.write_csr(ioaddr, CSR0, CSR0_INTEN);
1370
1371                 spin_unlock_irqrestore(&lp->lock, flags);
1372         }
1373         return work_done;
1374 }
1375
1376 #define PCNET32_REGS_PER_PHY    32
1377 #define PCNET32_MAX_PHYS        32
1378 static int pcnet32_get_regs_len(struct net_device *dev)
1379 {
1380         struct pcnet32_private *lp = netdev_priv(dev);
1381         int j = lp->phycount * PCNET32_REGS_PER_PHY;
1382
1383         return ((PCNET32_NUM_REGS + j) * sizeof(u16));
1384 }
1385
1386 static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1387                              void *ptr)
1388 {
1389         int i, csr0;
1390         u16 *buff = ptr;
1391         struct pcnet32_private *lp = netdev_priv(dev);
1392         struct pcnet32_access *a = &lp->a;
1393         ulong ioaddr = dev->base_addr;
1394         unsigned long flags;
1395
1396         spin_lock_irqsave(&lp->lock, flags);
1397
1398         csr0 = a->read_csr(ioaddr, CSR0);
1399         if (!(csr0 & CSR0_STOP))        /* If not stopped */
1400                 pcnet32_suspend(dev, &flags, 1);
1401
1402         /* read address PROM */
1403         for (i = 0; i < 16; i += 2)
1404                 *buff++ = inw(ioaddr + i);
1405
1406         /* read control and status registers */
1407         for (i = 0; i < 90; i++) {
1408                 *buff++ = a->read_csr(ioaddr, i);
1409         }
1410
1411         *buff++ = a->read_csr(ioaddr, 112);
1412         *buff++ = a->read_csr(ioaddr, 114);
1413
1414         /* read bus configuration registers */
1415         for (i = 0; i < 30; i++) {
1416                 *buff++ = a->read_bcr(ioaddr, i);
1417         }
1418         *buff++ = 0;            /* skip bcr30 so as not to hang 79C976 */
1419         for (i = 31; i < 36; i++) {
1420                 *buff++ = a->read_bcr(ioaddr, i);
1421         }
1422
1423         /* read mii phy registers */
1424         if (lp->mii) {
1425                 int j;
1426                 for (j = 0; j < PCNET32_MAX_PHYS; j++) {
1427                         if (lp->phymask & (1 << j)) {
1428                                 for (i = 0; i < PCNET32_REGS_PER_PHY; i++) {
1429                                         lp->a.write_bcr(ioaddr, 33,
1430                                                         (j << 5) | i);
1431                                         *buff++ = lp->a.read_bcr(ioaddr, 34);
1432                                 }
1433                         }
1434                 }
1435         }
1436
1437         if (!(csr0 & CSR0_STOP)) {      /* If not stopped */
1438                 int csr5;
1439
1440                 /* clear SUSPEND (SPND) - CSR5 bit 0 */
1441                 csr5 = a->read_csr(ioaddr, CSR5);
1442                 a->write_csr(ioaddr, CSR5, csr5 & (~CSR5_SUSPEND));
1443         }
1444
1445         spin_unlock_irqrestore(&lp->lock, flags);
1446 }
1447
1448 static const struct ethtool_ops pcnet32_ethtool_ops = {
1449         .get_settings           = pcnet32_get_settings,
1450         .set_settings           = pcnet32_set_settings,
1451         .get_drvinfo            = pcnet32_get_drvinfo,
1452         .get_msglevel           = pcnet32_get_msglevel,
1453         .set_msglevel           = pcnet32_set_msglevel,
1454         .nway_reset             = pcnet32_nway_reset,
1455         .get_link               = pcnet32_get_link,
1456         .get_ringparam          = pcnet32_get_ringparam,
1457         .set_ringparam          = pcnet32_set_ringparam,
1458         .get_strings            = pcnet32_get_strings,
1459         .self_test              = pcnet32_ethtool_test,
1460         .phys_id                = pcnet32_phys_id,
1461         .get_regs_len           = pcnet32_get_regs_len,
1462         .get_regs               = pcnet32_get_regs,
1463         .get_sset_count         = pcnet32_get_sset_count,
1464 };
1465
1466 /* only probes for non-PCI devices, the rest are handled by
1467  * pci_register_driver via pcnet32_probe_pci */
1468
1469 static void __devinit pcnet32_probe_vlbus(unsigned int *pcnet32_portlist)
1470 {
1471         unsigned int *port, ioaddr;
1472
1473         /* search for PCnet32 VLB cards at known addresses */
1474         for (port = pcnet32_portlist; (ioaddr = *port); port++) {
1475                 if (request_region
1476                     (ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_vlbus")) {
1477                         /* check if there is really a pcnet chip on that ioaddr */
1478                         if ((inb(ioaddr + 14) == 0x57) &&
1479                             (inb(ioaddr + 15) == 0x57)) {
1480                                 pcnet32_probe1(ioaddr, 0, NULL);
1481                         } else {
1482                                 release_region(ioaddr, PCNET32_TOTAL_SIZE);
1483                         }
1484                 }
1485         }
1486 }
1487
1488 static int __devinit
1489 pcnet32_probe_pci(struct pci_dev *pdev, const struct pci_device_id *ent)
1490 {
1491         unsigned long ioaddr;
1492         int err;
1493
1494         err = pci_enable_device(pdev);
1495         if (err < 0) {
1496                 if (pcnet32_debug & NETIF_MSG_PROBE)
1497                         pr_err("failed to enable device -- err=%d\n", err);
1498                 return err;
1499         }
1500         pci_set_master(pdev);
1501
1502         ioaddr = pci_resource_start(pdev, 0);
1503         if (!ioaddr) {
1504                 if (pcnet32_debug & NETIF_MSG_PROBE)
1505                         pr_err("card has no PCI IO resources, aborting\n");
1506                 return -ENODEV;
1507         }
1508
1509         if (!pci_dma_supported(pdev, PCNET32_DMA_MASK)) {
1510                 if (pcnet32_debug & NETIF_MSG_PROBE)
1511                         pr_err("architecture does not support 32bit PCI busmaster DMA\n");
1512                 return -ENODEV;
1513         }
1514         if (request_region(ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_pci") ==
1515             NULL) {
1516                 if (pcnet32_debug & NETIF_MSG_PROBE)
1517                         pr_err("io address range already allocated\n");
1518                 return -EBUSY;
1519         }
1520
1521         err = pcnet32_probe1(ioaddr, 1, pdev);
1522         if (err < 0) {
1523                 pci_disable_device(pdev);
1524         }
1525         return err;
1526 }
1527
1528 static const struct net_device_ops pcnet32_netdev_ops = {
1529         .ndo_open               = pcnet32_open,
1530         .ndo_stop               = pcnet32_close,
1531         .ndo_start_xmit         = pcnet32_start_xmit,
1532         .ndo_tx_timeout         = pcnet32_tx_timeout,
1533         .ndo_get_stats          = pcnet32_get_stats,
1534         .ndo_set_multicast_list = pcnet32_set_multicast_list,
1535         .ndo_do_ioctl           = pcnet32_ioctl,
1536         .ndo_change_mtu         = eth_change_mtu,
1537         .ndo_set_mac_address    = eth_mac_addr,
1538         .ndo_validate_addr      = eth_validate_addr,
1539 #ifdef CONFIG_NET_POLL_CONTROLLER
1540         .ndo_poll_controller    = pcnet32_poll_controller,
1541 #endif
1542 };
1543
1544 /* pcnet32_probe1
1545  *  Called from both pcnet32_probe_vlbus and pcnet_probe_pci.
1546  *  pdev will be NULL when called from pcnet32_probe_vlbus.
1547  */
1548 static int __devinit
1549 pcnet32_probe1(unsigned long ioaddr, int shared, struct pci_dev *pdev)
1550 {
1551         struct pcnet32_private *lp;
1552         int i, media;
1553         int fdx, mii, fset, dxsuflo;
1554         int chip_version;
1555         char *chipname;
1556         struct net_device *dev;
1557         struct pcnet32_access *a = NULL;
1558         u8 promaddr[6];
1559         int ret = -ENODEV;
1560
1561         /* reset the chip */
1562         pcnet32_wio_reset(ioaddr);
1563
1564         /* NOTE: 16-bit check is first, otherwise some older PCnet chips fail */
1565         if (pcnet32_wio_read_csr(ioaddr, 0) == 4 && pcnet32_wio_check(ioaddr)) {
1566                 a = &pcnet32_wio;
1567         } else {
1568                 pcnet32_dwio_reset(ioaddr);
1569                 if (pcnet32_dwio_read_csr(ioaddr, 0) == 4 &&
1570                     pcnet32_dwio_check(ioaddr)) {
1571                         a = &pcnet32_dwio;
1572                 } else {
1573                         if (pcnet32_debug & NETIF_MSG_PROBE)
1574                                 pr_err("No access methods\n");
1575                         goto err_release_region;
1576                 }
1577         }
1578
1579         chip_version =
1580             a->read_csr(ioaddr, 88) | (a->read_csr(ioaddr, 89) << 16);
1581         if ((pcnet32_debug & NETIF_MSG_PROBE) && (pcnet32_debug & NETIF_MSG_HW))
1582                 pr_info("  PCnet chip version is %#x\n", chip_version);
1583         if ((chip_version & 0xfff) != 0x003) {
1584                 if (pcnet32_debug & NETIF_MSG_PROBE)
1585                         pr_info("Unsupported chip version\n");
1586                 goto err_release_region;
1587         }
1588
1589         /* initialize variables */
1590         fdx = mii = fset = dxsuflo = 0;
1591         chip_version = (chip_version >> 12) & 0xffff;
1592
1593         switch (chip_version) {
1594         case 0x2420:
1595                 chipname = "PCnet/PCI 79C970";  /* PCI */
1596                 break;
1597         case 0x2430:
1598                 if (shared)
1599                         chipname = "PCnet/PCI 79C970";  /* 970 gives the wrong chip id back */
1600                 else
1601                         chipname = "PCnet/32 79C965";   /* 486/VL bus */
1602                 break;
1603         case 0x2621:
1604                 chipname = "PCnet/PCI II 79C970A";      /* PCI */
1605                 fdx = 1;
1606                 break;
1607         case 0x2623:
1608                 chipname = "PCnet/FAST 79C971"; /* PCI */
1609                 fdx = 1;
1610                 mii = 1;
1611                 fset = 1;
1612                 break;
1613         case 0x2624:
1614                 chipname = "PCnet/FAST+ 79C972";        /* PCI */
1615                 fdx = 1;
1616                 mii = 1;
1617                 fset = 1;
1618                 break;
1619         case 0x2625:
1620                 chipname = "PCnet/FAST III 79C973";     /* PCI */
1621                 fdx = 1;
1622                 mii = 1;
1623                 break;
1624         case 0x2626:
1625                 chipname = "PCnet/Home 79C978"; /* PCI */
1626                 fdx = 1;
1627                 /*
1628                  * This is based on specs published at www.amd.com.  This section
1629                  * assumes that a card with a 79C978 wants to go into standard
1630                  * ethernet mode.  The 79C978 can also go into 1Mb HomePNA mode,
1631                  * and the module option homepna=1 can select this instead.
1632                  */
1633                 media = a->read_bcr(ioaddr, 49);
1634                 media &= ~3;    /* default to 10Mb ethernet */
1635                 if (cards_found < MAX_UNITS && homepna[cards_found])
1636                         media |= 1;     /* switch to home wiring mode */
1637                 if (pcnet32_debug & NETIF_MSG_PROBE)
1638                         printk(KERN_DEBUG PFX "media set to %sMbit mode\n",
1639                                (media & 1) ? "1" : "10");
1640                 a->write_bcr(ioaddr, 49, media);
1641                 break;
1642         case 0x2627:
1643                 chipname = "PCnet/FAST III 79C975";     /* PCI */
1644                 fdx = 1;
1645                 mii = 1;
1646                 break;
1647         case 0x2628:
1648                 chipname = "PCnet/PRO 79C976";
1649                 fdx = 1;
1650                 mii = 1;
1651                 break;
1652         default:
1653                 if (pcnet32_debug & NETIF_MSG_PROBE)
1654                         pr_info("PCnet version %#x, no PCnet32 chip\n",
1655                                 chip_version);
1656                 goto err_release_region;
1657         }
1658
1659         /*
1660          *  On selected chips turn on the BCR18:NOUFLO bit. This stops transmit
1661          *  starting until the packet is loaded. Strike one for reliability, lose
1662          *  one for latency - although on PCI this isnt a big loss. Older chips
1663          *  have FIFO's smaller than a packet, so you can't do this.
1664          *  Turn on BCR18:BurstRdEn and BCR18:BurstWrEn.
1665          */
1666
1667         if (fset) {
1668                 a->write_bcr(ioaddr, 18, (a->read_bcr(ioaddr, 18) | 0x0860));
1669                 a->write_csr(ioaddr, 80,
1670                              (a->read_csr(ioaddr, 80) & 0x0C00) | 0x0c00);
1671                 dxsuflo = 1;
1672         }
1673
1674         dev = alloc_etherdev(sizeof(*lp));
1675         if (!dev) {
1676                 if (pcnet32_debug & NETIF_MSG_PROBE)
1677                         pr_err("Memory allocation failed\n");
1678                 ret = -ENOMEM;
1679                 goto err_release_region;
1680         }
1681
1682         if (pdev)
1683                 SET_NETDEV_DEV(dev, &pdev->dev);
1684
1685         if (pcnet32_debug & NETIF_MSG_PROBE)
1686                 pr_info("%s at %#3lx,", chipname, ioaddr);
1687
1688         /* In most chips, after a chip reset, the ethernet address is read from the
1689          * station address PROM at the base address and programmed into the
1690          * "Physical Address Registers" CSR12-14.
1691          * As a precautionary measure, we read the PROM values and complain if
1692          * they disagree with the CSRs.  If they miscompare, and the PROM addr
1693          * is valid, then the PROM addr is used.
1694          */
1695         for (i = 0; i < 3; i++) {
1696                 unsigned int val;
1697                 val = a->read_csr(ioaddr, i + 12) & 0x0ffff;
1698                 /* There may be endianness issues here. */
1699                 dev->dev_addr[2 * i] = val & 0x0ff;
1700                 dev->dev_addr[2 * i + 1] = (val >> 8) & 0x0ff;
1701         }
1702
1703         /* read PROM address and compare with CSR address */
1704         for (i = 0; i < 6; i++)
1705                 promaddr[i] = inb(ioaddr + i);
1706
1707         if (memcmp(promaddr, dev->dev_addr, 6) ||
1708             !is_valid_ether_addr(dev->dev_addr)) {
1709                 if (is_valid_ether_addr(promaddr)) {
1710                         if (pcnet32_debug & NETIF_MSG_PROBE) {
1711                                 pr_cont(" warning: CSR address invalid,\n");
1712                                 pr_info("    using instead PROM address of");
1713                         }
1714                         memcpy(dev->dev_addr, promaddr, 6);
1715                 }
1716         }
1717         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1718
1719         /* if the ethernet address is not valid, force to 00:00:00:00:00:00 */
1720         if (!is_valid_ether_addr(dev->perm_addr))
1721                 memset(dev->dev_addr, 0, ETH_ALEN);
1722
1723         if (pcnet32_debug & NETIF_MSG_PROBE) {
1724                 pr_cont(" %pM", dev->dev_addr);
1725
1726                 /* Version 0x2623 and 0x2624 */
1727                 if (((chip_version + 1) & 0xfffe) == 0x2624) {
1728                         i = a->read_csr(ioaddr, 80) & 0x0C00;   /* Check tx_start_pt */
1729                         pr_info("    tx_start_pt(0x%04x):", i);
1730                         switch (i >> 10) {
1731                         case 0:
1732                                 pr_cont("  20 bytes,");
1733                                 break;
1734                         case 1:
1735                                 pr_cont("  64 bytes,");
1736                                 break;
1737                         case 2:
1738                                 pr_cont(" 128 bytes,");
1739                                 break;
1740                         case 3:
1741                                 pr_cont("~220 bytes,");
1742                                 break;
1743                         }
1744                         i = a->read_bcr(ioaddr, 18);    /* Check Burst/Bus control */
1745                         pr_cont(" BCR18(%x):", i & 0xffff);
1746                         if (i & (1 << 5))
1747                                 pr_cont("BurstWrEn ");
1748                         if (i & (1 << 6))
1749                                 pr_cont("BurstRdEn ");
1750                         if (i & (1 << 7))
1751                                 pr_cont("DWordIO ");
1752                         if (i & (1 << 11))
1753                                 pr_cont("NoUFlow ");
1754                         i = a->read_bcr(ioaddr, 25);
1755                         pr_info("    SRAMSIZE=0x%04x,", i << 8);
1756                         i = a->read_bcr(ioaddr, 26);
1757                         pr_cont(" SRAM_BND=0x%04x,", i << 8);
1758                         i = a->read_bcr(ioaddr, 27);
1759                         if (i & (1 << 14))
1760                                 pr_cont("LowLatRx");
1761                 }
1762         }
1763
1764         dev->base_addr = ioaddr;
1765         lp = netdev_priv(dev);
1766         /* pci_alloc_consistent returns page-aligned memory, so we do not have to check the alignment */
1767         if ((lp->init_block =
1768              pci_alloc_consistent(pdev, sizeof(*lp->init_block), &lp->init_dma_addr)) == NULL) {
1769                 if (pcnet32_debug & NETIF_MSG_PROBE)
1770                         pr_err("Consistent memory allocation failed\n");
1771                 ret = -ENOMEM;
1772                 goto err_free_netdev;
1773         }
1774         lp->pci_dev = pdev;
1775
1776         lp->dev = dev;
1777
1778         spin_lock_init(&lp->lock);
1779
1780         lp->name = chipname;
1781         lp->shared_irq = shared;
1782         lp->tx_ring_size = TX_RING_SIZE;        /* default tx ring size */
1783         lp->rx_ring_size = RX_RING_SIZE;        /* default rx ring size */
1784         lp->tx_mod_mask = lp->tx_ring_size - 1;
1785         lp->rx_mod_mask = lp->rx_ring_size - 1;
1786         lp->tx_len_bits = (PCNET32_LOG_TX_BUFFERS << 12);
1787         lp->rx_len_bits = (PCNET32_LOG_RX_BUFFERS << 4);
1788         lp->mii_if.full_duplex = fdx;
1789         lp->mii_if.phy_id_mask = 0x1f;
1790         lp->mii_if.reg_num_mask = 0x1f;
1791         lp->dxsuflo = dxsuflo;
1792         lp->mii = mii;
1793         lp->chip_version = chip_version;
1794         lp->msg_enable = pcnet32_debug;
1795         if ((cards_found >= MAX_UNITS) ||
1796             (options[cards_found] >= sizeof(options_mapping)))
1797                 lp->options = PCNET32_PORT_ASEL;
1798         else
1799                 lp->options = options_mapping[options[cards_found]];
1800         lp->mii_if.dev = dev;
1801         lp->mii_if.mdio_read = mdio_read;
1802         lp->mii_if.mdio_write = mdio_write;
1803
1804         /* napi.weight is used in both the napi and non-napi cases */
1805         lp->napi.weight = lp->rx_ring_size / 2;
1806
1807         netif_napi_add(dev, &lp->napi, pcnet32_poll, lp->rx_ring_size / 2);
1808
1809         if (fdx && !(lp->options & PCNET32_PORT_ASEL) &&
1810             ((cards_found >= MAX_UNITS) || full_duplex[cards_found]))
1811                 lp->options |= PCNET32_PORT_FD;
1812
1813         lp->a = *a;
1814
1815         /* prior to register_netdev, dev->name is not yet correct */
1816         if (pcnet32_alloc_ring(dev, pci_name(lp->pci_dev))) {
1817                 ret = -ENOMEM;
1818                 goto err_free_ring;
1819         }
1820         /* detect special T1/E1 WAN card by checking for MAC address */
1821         if (dev->dev_addr[0] == 0x00 && dev->dev_addr[1] == 0xe0 &&
1822             dev->dev_addr[2] == 0x75)
1823                 lp->options = PCNET32_PORT_FD | PCNET32_PORT_GPSI;
1824
1825         lp->init_block->mode = cpu_to_le16(0x0003);     /* Disable Rx and Tx. */
1826         lp->init_block->tlen_rlen =
1827             cpu_to_le16(lp->tx_len_bits | lp->rx_len_bits);
1828         for (i = 0; i < 6; i++)
1829                 lp->init_block->phys_addr[i] = dev->dev_addr[i];
1830         lp->init_block->filter[0] = 0x00000000;
1831         lp->init_block->filter[1] = 0x00000000;
1832         lp->init_block->rx_ring = cpu_to_le32(lp->rx_ring_dma_addr);
1833         lp->init_block->tx_ring = cpu_to_le32(lp->tx_ring_dma_addr);
1834
1835         /* switch pcnet32 to 32bit mode */
1836         a->write_bcr(ioaddr, 20, 2);
1837
1838         a->write_csr(ioaddr, 1, (lp->init_dma_addr & 0xffff));
1839         a->write_csr(ioaddr, 2, (lp->init_dma_addr >> 16));
1840
1841         if (pdev) {             /* use the IRQ provided by PCI */
1842                 dev->irq = pdev->irq;
1843                 if (pcnet32_debug & NETIF_MSG_PROBE)
1844                         pr_cont(" assigned IRQ %d\n", dev->irq);
1845         } else {
1846                 unsigned long irq_mask = probe_irq_on();
1847
1848                 /*
1849                  * To auto-IRQ we enable the initialization-done and DMA error
1850                  * interrupts. For ISA boards we get a DMA error, but VLB and PCI
1851                  * boards will work.
1852                  */
1853                 /* Trigger an initialization just for the interrupt. */
1854                 a->write_csr(ioaddr, CSR0, CSR0_INTEN | CSR0_INIT);
1855                 mdelay(1);
1856
1857                 dev->irq = probe_irq_off(irq_mask);
1858                 if (!dev->irq) {
1859                         if (pcnet32_debug & NETIF_MSG_PROBE)
1860                                 pr_cont(", failed to detect IRQ line\n");
1861                         ret = -ENODEV;
1862                         goto err_free_ring;
1863                 }
1864                 if (pcnet32_debug & NETIF_MSG_PROBE)
1865                         pr_cont(", probed IRQ %d\n", dev->irq);
1866         }
1867
1868         /* Set the mii phy_id so that we can query the link state */
1869         if (lp->mii) {
1870                 /* lp->phycount and lp->phymask are set to 0 by memset above */
1871
1872                 lp->mii_if.phy_id = ((lp->a.read_bcr(ioaddr, 33)) >> 5) & 0x1f;
1873                 /* scan for PHYs */
1874                 for (i = 0; i < PCNET32_MAX_PHYS; i++) {
1875                         unsigned short id1, id2;
1876
1877                         id1 = mdio_read(dev, i, MII_PHYSID1);
1878                         if (id1 == 0xffff)
1879                                 continue;
1880                         id2 = mdio_read(dev, i, MII_PHYSID2);
1881                         if (id2 == 0xffff)
1882                                 continue;
1883                         if (i == 31 && ((chip_version + 1) & 0xfffe) == 0x2624)
1884                                 continue;       /* 79C971 & 79C972 have phantom phy at id 31 */
1885                         lp->phycount++;
1886                         lp->phymask |= (1 << i);
1887                         lp->mii_if.phy_id = i;
1888                         if (pcnet32_debug & NETIF_MSG_PROBE)
1889                                 pr_info("Found PHY %04x:%04x at address %d\n",
1890                                         id1, id2, i);
1891                 }
1892                 lp->a.write_bcr(ioaddr, 33, (lp->mii_if.phy_id) << 5);
1893                 if (lp->phycount > 1) {
1894                         lp->options |= PCNET32_PORT_MII;
1895                 }
1896         }
1897
1898         init_timer(&lp->watchdog_timer);
1899         lp->watchdog_timer.data = (unsigned long)dev;
1900         lp->watchdog_timer.function = (void *)&pcnet32_watchdog;
1901
1902         /* The PCNET32-specific entries in the device structure. */
1903         dev->netdev_ops = &pcnet32_netdev_ops;
1904         dev->ethtool_ops = &pcnet32_ethtool_ops;
1905         dev->watchdog_timeo = (5 * HZ);
1906
1907         /* Fill in the generic fields of the device structure. */
1908         if (register_netdev(dev))
1909                 goto err_free_ring;
1910
1911         if (pdev) {
1912                 pci_set_drvdata(pdev, dev);
1913         } else {
1914                 lp->next = pcnet32_dev;
1915                 pcnet32_dev = dev;
1916         }
1917
1918         if (pcnet32_debug & NETIF_MSG_PROBE)
1919                 pr_info("%s: registered as %s\n", dev->name, lp->name);
1920         cards_found++;
1921
1922         /* enable LED writes */
1923         a->write_bcr(ioaddr, 2, a->read_bcr(ioaddr, 2) | 0x1000);
1924
1925         return 0;
1926
1927 err_free_ring:
1928         pcnet32_free_ring(dev);
1929         pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block),
1930                             lp->init_block, lp->init_dma_addr);
1931 err_free_netdev:
1932         free_netdev(dev);
1933 err_release_region:
1934         release_region(ioaddr, PCNET32_TOTAL_SIZE);
1935         return ret;
1936 }
1937
1938 /* if any allocation fails, caller must also call pcnet32_free_ring */
1939 static int pcnet32_alloc_ring(struct net_device *dev, const char *name)
1940 {
1941         struct pcnet32_private *lp = netdev_priv(dev);
1942
1943         lp->tx_ring = pci_alloc_consistent(lp->pci_dev,
1944                                            sizeof(struct pcnet32_tx_head) *
1945                                            lp->tx_ring_size,
1946                                            &lp->tx_ring_dma_addr);
1947         if (lp->tx_ring == NULL) {
1948                 netif_err(lp, drv, dev, "Consistent memory allocation failed\n");
1949                 return -ENOMEM;
1950         }
1951
1952         lp->rx_ring = pci_alloc_consistent(lp->pci_dev,
1953                                            sizeof(struct pcnet32_rx_head) *
1954                                            lp->rx_ring_size,
1955                                            &lp->rx_ring_dma_addr);
1956         if (lp->rx_ring == NULL) {
1957                 netif_err(lp, drv, dev, "Consistent memory allocation failed\n");
1958                 return -ENOMEM;
1959         }
1960
1961         lp->tx_dma_addr = kcalloc(lp->tx_ring_size, sizeof(dma_addr_t),
1962                                   GFP_ATOMIC);
1963         if (!lp->tx_dma_addr) {
1964                 netif_err(lp, drv, dev, "Memory allocation failed\n");
1965                 return -ENOMEM;
1966         }
1967
1968         lp->rx_dma_addr = kcalloc(lp->rx_ring_size, sizeof(dma_addr_t),
1969                                   GFP_ATOMIC);
1970         if (!lp->rx_dma_addr) {
1971                 netif_err(lp, drv, dev, "Memory allocation failed\n");
1972                 return -ENOMEM;
1973         }
1974
1975         lp->tx_skbuff = kcalloc(lp->tx_ring_size, sizeof(struct sk_buff *),
1976                                 GFP_ATOMIC);
1977         if (!lp->tx_skbuff) {
1978                 netif_err(lp, drv, dev, "Memory allocation failed\n");
1979                 return -ENOMEM;
1980         }
1981
1982         lp->rx_skbuff = kcalloc(lp->rx_ring_size, sizeof(struct sk_buff *),
1983                                 GFP_ATOMIC);
1984         if (!lp->rx_skbuff) {
1985                 netif_err(lp, drv, dev, "Memory allocation failed\n");
1986                 return -ENOMEM;
1987         }
1988
1989         return 0;
1990 }
1991
1992 static void pcnet32_free_ring(struct net_device *dev)
1993 {
1994         struct pcnet32_private *lp = netdev_priv(dev);
1995
1996         kfree(lp->tx_skbuff);
1997         lp->tx_skbuff = NULL;
1998
1999         kfree(lp->rx_skbuff);
2000         lp->rx_skbuff = NULL;
2001
2002         kfree(lp->tx_dma_addr);
2003         lp->tx_dma_addr = NULL;
2004
2005         kfree(lp->rx_dma_addr);
2006         lp->rx_dma_addr = NULL;
2007
2008         if (lp->tx_ring) {
2009                 pci_free_consistent(lp->pci_dev,
2010                                     sizeof(struct pcnet32_tx_head) *
2011                                     lp->tx_ring_size, lp->tx_ring,
2012                                     lp->tx_ring_dma_addr);
2013                 lp->tx_ring = NULL;
2014         }
2015
2016         if (lp->rx_ring) {
2017                 pci_free_consistent(lp->pci_dev,
2018                                     sizeof(struct pcnet32_rx_head) *
2019                                     lp->rx_ring_size, lp->rx_ring,
2020                                     lp->rx_ring_dma_addr);
2021                 lp->rx_ring = NULL;
2022         }
2023 }
2024
2025 static int pcnet32_open(struct net_device *dev)
2026 {
2027         struct pcnet32_private *lp = netdev_priv(dev);
2028         struct pci_dev *pdev = lp->pci_dev;
2029         unsigned long ioaddr = dev->base_addr;
2030         u16 val;
2031         int i;
2032         int rc;
2033         unsigned long flags;
2034
2035         if (request_irq(dev->irq, pcnet32_interrupt,
2036                         lp->shared_irq ? IRQF_SHARED : 0, dev->name,
2037                         (void *)dev)) {
2038                 return -EAGAIN;
2039         }
2040
2041         spin_lock_irqsave(&lp->lock, flags);
2042         /* Check for a valid station address */
2043         if (!is_valid_ether_addr(dev->dev_addr)) {
2044                 rc = -EINVAL;
2045                 goto err_free_irq;
2046         }
2047
2048         /* Reset the PCNET32 */
2049         lp->a.reset(ioaddr);
2050
2051         /* switch pcnet32 to 32bit mode */
2052         lp->a.write_bcr(ioaddr, 20, 2);
2053
2054         netif_printk(lp, ifup, KERN_DEBUG, dev,
2055                      "%s() irq %d tx/rx rings %#x/%#x init %#x\n",
2056                      __func__, dev->irq, (u32) (lp->tx_ring_dma_addr),
2057                      (u32) (lp->rx_ring_dma_addr),
2058                      (u32) (lp->init_dma_addr));
2059
2060         /* set/reset autoselect bit */
2061         val = lp->a.read_bcr(ioaddr, 2) & ~2;
2062         if (lp->options & PCNET32_PORT_ASEL)
2063                 val |= 2;
2064         lp->a.write_bcr(ioaddr, 2, val);
2065
2066         /* handle full duplex setting */
2067         if (lp->mii_if.full_duplex) {
2068                 val = lp->a.read_bcr(ioaddr, 9) & ~3;
2069                 if (lp->options & PCNET32_PORT_FD) {
2070                         val |= 1;
2071                         if (lp->options == (PCNET32_PORT_FD | PCNET32_PORT_AUI))
2072                                 val |= 2;
2073                 } else if (lp->options & PCNET32_PORT_ASEL) {
2074                         /* workaround of xSeries250, turn on for 79C975 only */
2075                         if (lp->chip_version == 0x2627)
2076                                 val |= 3;
2077                 }
2078                 lp->a.write_bcr(ioaddr, 9, val);
2079         }
2080
2081         /* set/reset GPSI bit in test register */
2082         val = lp->a.read_csr(ioaddr, 124) & ~0x10;
2083         if ((lp->options & PCNET32_PORT_PORTSEL) == PCNET32_PORT_GPSI)
2084                 val |= 0x10;
2085         lp->a.write_csr(ioaddr, 124, val);
2086
2087         /* Allied Telesyn AT 2700/2701 FX are 100Mbit only and do not negotiate */
2088         if (pdev && pdev->subsystem_vendor == PCI_VENDOR_ID_AT &&
2089             (pdev->subsystem_device == PCI_SUBDEVICE_ID_AT_2700FX ||
2090              pdev->subsystem_device == PCI_SUBDEVICE_ID_AT_2701FX)) {
2091                 if (lp->options & PCNET32_PORT_ASEL) {
2092                         lp->options = PCNET32_PORT_FD | PCNET32_PORT_100;
2093                         netif_printk(lp, link, KERN_DEBUG, dev,
2094                                      "Setting 100Mb-Full Duplex\n");
2095                 }
2096         }
2097         if (lp->phycount < 2) {
2098                 /*
2099                  * 24 Jun 2004 according AMD, in order to change the PHY,
2100                  * DANAS (or DISPM for 79C976) must be set; then select the speed,
2101                  * duplex, and/or enable auto negotiation, and clear DANAS
2102                  */
2103                 if (lp->mii && !(lp->options & PCNET32_PORT_ASEL)) {
2104                         lp->a.write_bcr(ioaddr, 32,
2105                                         lp->a.read_bcr(ioaddr, 32) | 0x0080);
2106                         /* disable Auto Negotiation, set 10Mpbs, HD */
2107                         val = lp->a.read_bcr(ioaddr, 32) & ~0xb8;
2108                         if (lp->options & PCNET32_PORT_FD)
2109                                 val |= 0x10;
2110                         if (lp->options & PCNET32_PORT_100)
2111                                 val |= 0x08;
2112                         lp->a.write_bcr(ioaddr, 32, val);
2113                 } else {
2114                         if (lp->options & PCNET32_PORT_ASEL) {
2115                                 lp->a.write_bcr(ioaddr, 32,
2116                                                 lp->a.read_bcr(ioaddr,
2117                                                                32) | 0x0080);
2118                                 /* enable auto negotiate, setup, disable fd */
2119                                 val = lp->a.read_bcr(ioaddr, 32) & ~0x98;
2120                                 val |= 0x20;
2121                                 lp->a.write_bcr(ioaddr, 32, val);
2122                         }
2123                 }
2124         } else {
2125                 int first_phy = -1;
2126                 u16 bmcr;
2127                 u32 bcr9;
2128                 struct ethtool_cmd ecmd;
2129
2130                 /*
2131                  * There is really no good other way to handle multiple PHYs
2132                  * other than turning off all automatics
2133                  */
2134                 val = lp->a.read_bcr(ioaddr, 2);
2135                 lp->a.write_bcr(ioaddr, 2, val & ~2);
2136                 val = lp->a.read_bcr(ioaddr, 32);
2137                 lp->a.write_bcr(ioaddr, 32, val & ~(1 << 7));   /* stop MII manager */
2138
2139                 if (!(lp->options & PCNET32_PORT_ASEL)) {
2140                         /* setup ecmd */
2141                         ecmd.port = PORT_MII;
2142                         ecmd.transceiver = XCVR_INTERNAL;
2143                         ecmd.autoneg = AUTONEG_DISABLE;
2144                         ecmd.speed =
2145                             lp->
2146                             options & PCNET32_PORT_100 ? SPEED_100 : SPEED_10;
2147                         bcr9 = lp->a.read_bcr(ioaddr, 9);
2148
2149                         if (lp->options & PCNET32_PORT_FD) {
2150                                 ecmd.duplex = DUPLEX_FULL;
2151                                 bcr9 |= (1 << 0);
2152                         } else {
2153                                 ecmd.duplex = DUPLEX_HALF;
2154                                 bcr9 |= ~(1 << 0);
2155                         }
2156                         lp->a.write_bcr(ioaddr, 9, bcr9);
2157                 }
2158
2159                 for (i = 0; i < PCNET32_MAX_PHYS; i++) {
2160                         if (lp->phymask & (1 << i)) {
2161                                 /* isolate all but the first PHY */
2162                                 bmcr = mdio_read(dev, i, MII_BMCR);
2163                                 if (first_phy == -1) {
2164                                         first_phy = i;
2165                                         mdio_write(dev, i, MII_BMCR,
2166                                                    bmcr & ~BMCR_ISOLATE);
2167                                 } else {
2168                                         mdio_write(dev, i, MII_BMCR,
2169                                                    bmcr | BMCR_ISOLATE);
2170                                 }
2171                                 /* use mii_ethtool_sset to setup PHY */
2172                                 lp->mii_if.phy_id = i;
2173                                 ecmd.phy_address = i;
2174                                 if (lp->options & PCNET32_PORT_ASEL) {
2175                                         mii_ethtool_gset(&lp->mii_if, &ecmd);
2176                                         ecmd.autoneg = AUTONEG_ENABLE;
2177                                 }
2178                                 mii_ethtool_sset(&lp->mii_if, &ecmd);
2179                         }
2180                 }
2181                 lp->mii_if.phy_id = first_phy;
2182                 netif_info(lp, link, dev, "Using PHY number %d\n", first_phy);
2183         }
2184
2185 #ifdef DO_DXSUFLO
2186         if (lp->dxsuflo) {      /* Disable transmit stop on underflow */
2187                 val = lp->a.read_csr(ioaddr, CSR3);
2188                 val |= 0x40;
2189                 lp->a.write_csr(ioaddr, CSR3, val);
2190         }
2191 #endif
2192
2193         lp->init_block->mode =
2194             cpu_to_le16((lp->options & PCNET32_PORT_PORTSEL) << 7);
2195         pcnet32_load_multicast(dev);
2196
2197         if (pcnet32_init_ring(dev)) {
2198                 rc = -ENOMEM;
2199                 goto err_free_ring;
2200         }
2201
2202         napi_enable(&lp->napi);
2203
2204         /* Re-initialize the PCNET32, and start it when done. */
2205         lp->a.write_csr(ioaddr, 1, (lp->init_dma_addr & 0xffff));
2206         lp->a.write_csr(ioaddr, 2, (lp->init_dma_addr >> 16));
2207
2208         lp->a.write_csr(ioaddr, CSR4, 0x0915);  /* auto tx pad */
2209         lp->a.write_csr(ioaddr, CSR0, CSR0_INIT);
2210
2211         netif_start_queue(dev);
2212
2213         if (lp->chip_version >= PCNET32_79C970A) {
2214                 /* Print the link status and start the watchdog */
2215                 pcnet32_check_media(dev, 1);
2216                 mod_timer(&lp->watchdog_timer, PCNET32_WATCHDOG_TIMEOUT);
2217         }
2218
2219         i = 0;
2220         while (i++ < 100)
2221                 if (lp->a.read_csr(ioaddr, CSR0) & CSR0_IDON)
2222                         break;
2223         /*
2224          * We used to clear the InitDone bit, 0x0100, here but Mark Stockton
2225          * reports that doing so triggers a bug in the '974.
2226          */
2227         lp->a.write_csr(ioaddr, CSR0, CSR0_NORMAL);
2228
2229         netif_printk(lp, ifup, KERN_DEBUG, dev,
2230                      "pcnet32 open after %d ticks, init block %#x csr0 %4.4x\n",
2231                      i,
2232                      (u32) (lp->init_dma_addr),
2233                      lp->a.read_csr(ioaddr, CSR0));
2234
2235         spin_unlock_irqrestore(&lp->lock, flags);
2236
2237         return 0;               /* Always succeed */
2238
2239       err_free_ring:
2240         /* free any allocated skbuffs */
2241         pcnet32_purge_rx_ring(dev);
2242
2243         /*
2244          * Switch back to 16bit mode to avoid problems with dumb
2245          * DOS packet driver after a warm reboot
2246          */
2247         lp->a.write_bcr(ioaddr, 20, 4);
2248
2249       err_free_irq:
2250         spin_unlock_irqrestore(&lp->lock, flags);
2251         free_irq(dev->irq, dev);
2252         return rc;
2253 }
2254
2255 /*
2256  * The LANCE has been halted for one reason or another (busmaster memory
2257  * arbitration error, Tx FIFO underflow, driver stopped it to reconfigure,
2258  * etc.).  Modern LANCE variants always reload their ring-buffer
2259  * configuration when restarted, so we must reinitialize our ring
2260  * context before restarting.  As part of this reinitialization,
2261  * find all packets still on the Tx ring and pretend that they had been
2262  * sent (in effect, drop the packets on the floor) - the higher-level
2263  * protocols will time out and retransmit.  It'd be better to shuffle
2264  * these skbs to a temp list and then actually re-Tx them after
2265  * restarting the chip, but I'm too lazy to do so right now.  dplatt@3do.com
2266  */
2267
2268 static void pcnet32_purge_tx_ring(struct net_device *dev)
2269 {
2270         struct pcnet32_private *lp = netdev_priv(dev);
2271         int i;
2272
2273         for (i = 0; i < lp->tx_ring_size; i++) {
2274                 lp->tx_ring[i].status = 0;      /* CPU owns buffer */
2275                 wmb();          /* Make sure adapter sees owner change */
2276                 if (lp->tx_skbuff[i]) {
2277                         pci_unmap_single(lp->pci_dev, lp->tx_dma_addr[i],
2278                                          lp->tx_skbuff[i]->len,
2279                                          PCI_DMA_TODEVICE);
2280                         dev_kfree_skb_any(lp->tx_skbuff[i]);
2281                 }
2282                 lp->tx_skbuff[i] = NULL;
2283                 lp->tx_dma_addr[i] = 0;
2284         }
2285 }
2286
2287 /* Initialize the PCNET32 Rx and Tx rings. */
2288 static int pcnet32_init_ring(struct net_device *dev)
2289 {
2290         struct pcnet32_private *lp = netdev_priv(dev);
2291         int i;
2292
2293         lp->tx_full = 0;
2294         lp->cur_rx = lp->cur_tx = 0;
2295         lp->dirty_rx = lp->dirty_tx = 0;
2296
2297         for (i = 0; i < lp->rx_ring_size; i++) {
2298                 struct sk_buff *rx_skbuff = lp->rx_skbuff[i];
2299                 if (rx_skbuff == NULL) {
2300                         if (!
2301                             (rx_skbuff = lp->rx_skbuff[i] =
2302                              dev_alloc_skb(PKT_BUF_SKB))) {
2303                                 /* there is not much, we can do at this point */
2304                                 netif_err(lp, drv, dev, "%s dev_alloc_skb failed\n",
2305                                           __func__);
2306                                 return -1;
2307                         }
2308                         skb_reserve(rx_skbuff, NET_IP_ALIGN);
2309                 }
2310
2311                 rmb();
2312                 if (lp->rx_dma_addr[i] == 0)
2313                         lp->rx_dma_addr[i] =
2314                             pci_map_single(lp->pci_dev, rx_skbuff->data,
2315                                            PKT_BUF_SIZE, PCI_DMA_FROMDEVICE);
2316                 lp->rx_ring[i].base = cpu_to_le32(lp->rx_dma_addr[i]);
2317                 lp->rx_ring[i].buf_length = cpu_to_le16(NEG_BUF_SIZE);
2318                 wmb();          /* Make sure owner changes after all others are visible */
2319                 lp->rx_ring[i].status = cpu_to_le16(0x8000);
2320         }
2321         /* The Tx buffer address is filled in as needed, but we do need to clear
2322          * the upper ownership bit. */
2323         for (i = 0; i < lp->tx_ring_size; i++) {
2324                 lp->tx_ring[i].status = 0;      /* CPU owns buffer */
2325                 wmb();          /* Make sure adapter sees owner change */
2326                 lp->tx_ring[i].base = 0;
2327                 lp->tx_dma_addr[i] = 0;
2328         }
2329
2330         lp->init_block->tlen_rlen =
2331             cpu_to_le16(lp->tx_len_bits | lp->rx_len_bits);
2332         for (i = 0; i < 6; i++)
2333                 lp->init_block->phys_addr[i] = dev->dev_addr[i];
2334         lp->init_block->rx_ring = cpu_to_le32(lp->rx_ring_dma_addr);
2335         lp->init_block->tx_ring = cpu_to_le32(lp->tx_ring_dma_addr);
2336         wmb();                  /* Make sure all changes are visible */
2337         return 0;
2338 }
2339
2340 /* the pcnet32 has been issued a stop or reset.  Wait for the stop bit
2341  * then flush the pending transmit operations, re-initialize the ring,
2342  * and tell the chip to initialize.
2343  */
2344 static void pcnet32_restart(struct net_device *dev, unsigned int csr0_bits)
2345 {
2346         struct pcnet32_private *lp = netdev_priv(dev);
2347         unsigned long ioaddr = dev->base_addr;
2348         int i;
2349
2350         /* wait for stop */
2351         for (i = 0; i < 100; i++)
2352                 if (lp->a.read_csr(ioaddr, CSR0) & CSR0_STOP)
2353                         break;
2354
2355         if (i >= 100)
2356                 netif_err(lp, drv, dev, "%s timed out waiting for stop\n",
2357                           __func__);
2358
2359         pcnet32_purge_tx_ring(dev);
2360         if (pcnet32_init_ring(dev))
2361                 return;
2362
2363         /* ReInit Ring */
2364         lp->a.write_csr(ioaddr, CSR0, CSR0_INIT);
2365         i = 0;
2366         while (i++ < 1000)
2367                 if (lp->a.read_csr(ioaddr, CSR0) & CSR0_IDON)
2368                         break;
2369
2370         lp->a.write_csr(ioaddr, CSR0, csr0_bits);
2371 }
2372
2373 static void pcnet32_tx_timeout(struct net_device *dev)
2374 {
2375         struct pcnet32_private *lp = netdev_priv(dev);
2376         unsigned long ioaddr = dev->base_addr, flags;
2377
2378         spin_lock_irqsave(&lp->lock, flags);
2379         /* Transmitter timeout, serious problems. */
2380         if (pcnet32_debug & NETIF_MSG_DRV)
2381                 pr_err("%s: transmit timed out, status %4.4x, resetting\n",
2382                        dev->name, lp->a.read_csr(ioaddr, CSR0));
2383         lp->a.write_csr(ioaddr, CSR0, CSR0_STOP);
2384         dev->stats.tx_errors++;
2385         if (netif_msg_tx_err(lp)) {
2386                 int i;
2387                 printk(KERN_DEBUG
2388                        " Ring data dump: dirty_tx %d cur_tx %d%s cur_rx %d.",
2389                        lp->dirty_tx, lp->cur_tx, lp->tx_full ? " (full)" : "",
2390                        lp->cur_rx);
2391                 for (i = 0; i < lp->rx_ring_size; i++)
2392                         printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ",
2393                                le32_to_cpu(lp->rx_ring[i].base),
2394                                (-le16_to_cpu(lp->rx_ring[i].buf_length)) &
2395                                0xffff, le32_to_cpu(lp->rx_ring[i].msg_length),
2396                                le16_to_cpu(lp->rx_ring[i].status));
2397                 for (i = 0; i < lp->tx_ring_size; i++)
2398                         printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ",
2399                                le32_to_cpu(lp->tx_ring[i].base),
2400                                (-le16_to_cpu(lp->tx_ring[i].length)) & 0xffff,
2401                                le32_to_cpu(lp->tx_ring[i].misc),
2402                                le16_to_cpu(lp->tx_ring[i].status));
2403                 printk("\n");
2404         }
2405         pcnet32_restart(dev, CSR0_NORMAL);
2406
2407         dev->trans_start = jiffies;
2408         netif_wake_queue(dev);
2409
2410         spin_unlock_irqrestore(&lp->lock, flags);
2411 }
2412
2413 static netdev_tx_t pcnet32_start_xmit(struct sk_buff *skb,
2414                                       struct net_device *dev)
2415 {
2416         struct pcnet32_private *lp = netdev_priv(dev);
2417         unsigned long ioaddr = dev->base_addr;
2418         u16 status;
2419         int entry;
2420         unsigned long flags;
2421
2422         spin_lock_irqsave(&lp->lock, flags);
2423
2424         netif_printk(lp, tx_queued, KERN_DEBUG, dev,
2425                      "%s() called, csr0 %4.4x\n",
2426                      __func__, lp->a.read_csr(ioaddr, CSR0));
2427
2428         /* Default status -- will not enable Successful-TxDone
2429          * interrupt when that option is available to us.
2430          */
2431         status = 0x8300;
2432
2433         /* Fill in a Tx ring entry */
2434
2435         /* Mask to ring buffer boundary. */
2436         entry = lp->cur_tx & lp->tx_mod_mask;
2437
2438         /* Caution: the write order is important here, set the status
2439          * with the "ownership" bits last. */
2440
2441         lp->tx_ring[entry].length = cpu_to_le16(-skb->len);
2442
2443         lp->tx_ring[entry].misc = 0x00000000;
2444
2445         lp->tx_skbuff[entry] = skb;
2446         lp->tx_dma_addr[entry] =
2447             pci_map_single(lp->pci_dev, skb->data, skb->len, PCI_DMA_TODEVICE);
2448         lp->tx_ring[entry].base = cpu_to_le32(lp->tx_dma_addr[entry]);
2449         wmb();                  /* Make sure owner changes after all others are visible */
2450         lp->tx_ring[entry].status = cpu_to_le16(status);
2451
2452         lp->cur_tx++;
2453         dev->stats.tx_bytes += skb->len;
2454
2455         /* Trigger an immediate send poll. */
2456         lp->a.write_csr(ioaddr, CSR0, CSR0_INTEN | CSR0_TXPOLL);
2457
2458         dev->trans_start = jiffies;
2459
2460         if (lp->tx_ring[(entry + 1) & lp->tx_mod_mask].base != 0) {
2461                 lp->tx_full = 1;
2462                 netif_stop_queue(dev);
2463         }
2464         spin_unlock_irqrestore(&lp->lock, flags);
2465         return NETDEV_TX_OK;
2466 }
2467
2468 /* The PCNET32 interrupt handler. */
2469 static irqreturn_t
2470 pcnet32_interrupt(int irq, void *dev_id)
2471 {
2472         struct net_device *dev = dev_id;
2473         struct pcnet32_private *lp;
2474         unsigned long ioaddr;
2475         u16 csr0;
2476         int boguscnt = max_interrupt_work;
2477
2478         ioaddr = dev->base_addr;
2479         lp = netdev_priv(dev);
2480
2481         spin_lock(&lp->lock);
2482
2483         csr0 = lp->a.read_csr(ioaddr, CSR0);
2484         while ((csr0 & 0x8f00) && --boguscnt >= 0) {
2485                 if (csr0 == 0xffff) {
2486                         break;  /* PCMCIA remove happened */
2487                 }
2488                 /* Acknowledge all of the current interrupt sources ASAP. */
2489                 lp->a.write_csr(ioaddr, CSR0, csr0 & ~0x004f);
2490
2491                 netif_printk(lp, intr, KERN_DEBUG, dev,
2492                              "interrupt  csr0=%#2.2x new csr=%#2.2x\n",
2493                              csr0, lp->a.read_csr(ioaddr, CSR0));
2494
2495                 /* Log misc errors. */
2496                 if (csr0 & 0x4000)
2497                         dev->stats.tx_errors++; /* Tx babble. */
2498                 if (csr0 & 0x1000) {
2499                         /*
2500                          * This happens when our receive ring is full. This
2501                          * shouldn't be a problem as we will see normal rx
2502                          * interrupts for the frames in the receive ring.  But
2503                          * there are some PCI chipsets (I can reproduce this
2504                          * on SP3G with Intel saturn chipset) which have
2505                          * sometimes problems and will fill up the receive
2506                          * ring with error descriptors.  In this situation we
2507                          * don't get a rx interrupt, but a missed frame
2508                          * interrupt sooner or later.
2509                          */
2510                         dev->stats.rx_errors++; /* Missed a Rx frame. */
2511                 }
2512                 if (csr0 & 0x0800) {
2513                         netif_err(lp, drv, dev, "Bus master arbitration failure, status %4.4x\n",
2514                                   csr0);
2515                         /* unlike for the lance, there is no restart needed */
2516                 }
2517                 if (napi_schedule_prep(&lp->napi)) {
2518                         u16 val;
2519                         /* set interrupt masks */
2520                         val = lp->a.read_csr(ioaddr, CSR3);
2521                         val |= 0x5f00;
2522                         lp->a.write_csr(ioaddr, CSR3, val);
2523
2524                         __napi_schedule(&lp->napi);
2525                         break;
2526                 }
2527                 csr0 = lp->a.read_csr(ioaddr, CSR0);
2528         }
2529
2530         netif_printk(lp, intr, KERN_DEBUG, dev,
2531                      "exiting interrupt, csr0=%#4.4x\n",
2532                      lp->a.read_csr(ioaddr, CSR0));
2533
2534         spin_unlock(&lp->lock);
2535
2536         return IRQ_HANDLED;
2537 }
2538
2539 static int pcnet32_close(struct net_device *dev)
2540 {
2541         unsigned long ioaddr = dev->base_addr;
2542         struct pcnet32_private *lp = netdev_priv(dev);
2543         unsigned long flags;
2544
2545         del_timer_sync(&lp->watchdog_timer);
2546
2547         netif_stop_queue(dev);
2548         napi_disable(&lp->napi);
2549
2550         spin_lock_irqsave(&lp->lock, flags);
2551
2552         dev->stats.rx_missed_errors = lp->a.read_csr(ioaddr, 112);
2553
2554         netif_printk(lp, ifdown, KERN_DEBUG, dev,
2555                      "Shutting down ethercard, status was %2.2x\n",
2556                      lp->a.read_csr(ioaddr, CSR0));
2557
2558         /* We stop the PCNET32 here -- it occasionally polls memory if we don't. */
2559         lp->a.write_csr(ioaddr, CSR0, CSR0_STOP);
2560
2561         /*
2562          * Switch back to 16bit mode to avoid problems with dumb
2563          * DOS packet driver after a warm reboot
2564          */
2565         lp->a.write_bcr(ioaddr, 20, 4);
2566
2567         spin_unlock_irqrestore(&lp->lock, flags);
2568
2569         free_irq(dev->irq, dev);
2570
2571         spin_lock_irqsave(&lp->lock, flags);
2572
2573         pcnet32_purge_rx_ring(dev);
2574         pcnet32_purge_tx_ring(dev);
2575
2576         spin_unlock_irqrestore(&lp->lock, flags);
2577
2578         return 0;
2579 }
2580
2581 static struct net_device_stats *pcnet32_get_stats(struct net_device *dev)
2582 {
2583         struct pcnet32_private *lp = netdev_priv(dev);
2584         unsigned long ioaddr = dev->base_addr;
2585         unsigned long flags;
2586
2587         spin_lock_irqsave(&lp->lock, flags);
2588         dev->stats.rx_missed_errors = lp->a.read_csr(ioaddr, 112);
2589         spin_unlock_irqrestore(&lp->lock, flags);
2590
2591         return &dev->stats;
2592 }
2593
2594 /* taken from the sunlance driver, which it took from the depca driver */
2595 static void pcnet32_load_multicast(struct net_device *dev)
2596 {
2597         struct pcnet32_private *lp = netdev_priv(dev);
2598         volatile struct pcnet32_init_block *ib = lp->init_block;
2599         volatile __le16 *mcast_table = (__le16 *)ib->filter;
2600         struct dev_mc_list *dmi = dev->mc_list;
2601         unsigned long ioaddr = dev->base_addr;
2602         char *addrs;
2603         int i;
2604         u32 crc;
2605
2606         /* set all multicast bits */
2607         if (dev->flags & IFF_ALLMULTI) {
2608                 ib->filter[0] = cpu_to_le32(~0U);
2609                 ib->filter[1] = cpu_to_le32(~0U);
2610                 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER, 0xffff);
2611                 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER+1, 0xffff);
2612                 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER+2, 0xffff);
2613                 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER+3, 0xffff);
2614                 return;
2615         }
2616         /* clear the multicast filter */
2617         ib->filter[0] = 0;
2618         ib->filter[1] = 0;
2619
2620         /* Add addresses */
2621         for (i = 0; i < netdev_mc_count(dev); i++) {
2622                 addrs = dmi->dmi_addr;
2623                 dmi = dmi->next;
2624
2625                 /* multicast address? */
2626                 if (!(*addrs & 1))
2627                         continue;
2628
2629                 crc = ether_crc_le(6, addrs);
2630                 crc = crc >> 26;
2631                 mcast_table[crc >> 4] |= cpu_to_le16(1 << (crc & 0xf));
2632         }
2633         for (i = 0; i < 4; i++)
2634                 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER + i,
2635                                 le16_to_cpu(mcast_table[i]));
2636         return;
2637 }
2638
2639 /*
2640  * Set or clear the multicast filter for this adaptor.
2641  */
2642 static void pcnet32_set_multicast_list(struct net_device *dev)
2643 {
2644         unsigned long ioaddr = dev->base_addr, flags;
2645         struct pcnet32_private *lp = netdev_priv(dev);
2646         int csr15, suspended;
2647
2648         spin_lock_irqsave(&lp->lock, flags);
2649         suspended = pcnet32_suspend(dev, &flags, 0);
2650         csr15 = lp->a.read_csr(ioaddr, CSR15);
2651         if (dev->flags & IFF_PROMISC) {
2652                 /* Log any net taps. */
2653                 netif_info(lp, hw, dev, "Promiscuous mode enabled\n");
2654                 lp->init_block->mode =
2655                     cpu_to_le16(0x8000 | (lp->options & PCNET32_PORT_PORTSEL) <<
2656                                 7);
2657                 lp->a.write_csr(ioaddr, CSR15, csr15 | 0x8000);
2658         } else {
2659                 lp->init_block->mode =
2660                     cpu_to_le16((lp->options & PCNET32_PORT_PORTSEL) << 7);
2661                 lp->a.write_csr(ioaddr, CSR15, csr15 & 0x7fff);
2662                 pcnet32_load_multicast(dev);
2663         }
2664
2665         if (suspended) {
2666                 int csr5;
2667                 /* clear SUSPEND (SPND) - CSR5 bit 0 */
2668                 csr5 = lp->a.read_csr(ioaddr, CSR5);
2669                 lp->a.write_csr(ioaddr, CSR5, csr5 & (~CSR5_SUSPEND));
2670         } else {
2671                 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP);
2672                 pcnet32_restart(dev, CSR0_NORMAL);
2673                 netif_wake_queue(dev);
2674         }
2675
2676         spin_unlock_irqrestore(&lp->lock, flags);
2677 }
2678
2679 /* This routine assumes that the lp->lock is held */
2680 static int mdio_read(struct net_device *dev, int phy_id, int reg_num)
2681 {
2682         struct pcnet32_private *lp = netdev_priv(dev);
2683         unsigned long ioaddr = dev->base_addr;
2684         u16 val_out;
2685
2686         if (!lp->mii)
2687                 return 0;
2688
2689         lp->a.write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f));
2690         val_out = lp->a.read_bcr(ioaddr, 34);
2691
2692         return val_out;
2693 }
2694
2695 /* This routine assumes that the lp->lock is held */
2696 static void mdio_write(struct net_device *dev, int phy_id, int reg_num, int val)
2697 {
2698         struct pcnet32_private *lp = netdev_priv(dev);
2699         unsigned long ioaddr = dev->base_addr;
2700
2701         if (!lp->mii)
2702                 return;
2703
2704         lp->a.write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f));
2705         lp->a.write_bcr(ioaddr, 34, val);
2706 }
2707
2708 static int pcnet32_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2709 {
2710         struct pcnet32_private *lp = netdev_priv(dev);
2711         int rc;
2712         unsigned long flags;
2713
2714         /* SIOC[GS]MIIxxx ioctls */
2715         if (lp->mii) {
2716                 spin_lock_irqsave(&lp->lock, flags);
2717                 rc = generic_mii_ioctl(&lp->mii_if, if_mii(rq), cmd, NULL);
2718                 spin_unlock_irqrestore(&lp->lock, flags);
2719         } else {
2720                 rc = -EOPNOTSUPP;
2721         }
2722
2723         return rc;
2724 }
2725
2726 static int pcnet32_check_otherphy(struct net_device *dev)
2727 {
2728         struct pcnet32_private *lp = netdev_priv(dev);
2729         struct mii_if_info mii = lp->mii_if;
2730         u16 bmcr;
2731         int i;
2732
2733         for (i = 0; i < PCNET32_MAX_PHYS; i++) {
2734                 if (i == lp->mii_if.phy_id)
2735                         continue;       /* skip active phy */
2736                 if (lp->phymask & (1 << i)) {
2737                         mii.phy_id = i;
2738                         if (mii_link_ok(&mii)) {
2739                                 /* found PHY with active link */
2740                                 netif_info(lp, link, dev, "Using PHY number %d\n",
2741                                            i);
2742
2743                                 /* isolate inactive phy */
2744                                 bmcr =
2745                                     mdio_read(dev, lp->mii_if.phy_id, MII_BMCR);
2746                                 mdio_write(dev, lp->mii_if.phy_id, MII_BMCR,
2747                                            bmcr | BMCR_ISOLATE);
2748
2749                                 /* de-isolate new phy */
2750                                 bmcr = mdio_read(dev, i, MII_BMCR);
2751                                 mdio_write(dev, i, MII_BMCR,
2752                                            bmcr & ~BMCR_ISOLATE);
2753
2754                                 /* set new phy address */
2755                                 lp->mii_if.phy_id = i;
2756                                 return 1;
2757                         }
2758                 }
2759         }
2760         return 0;
2761 }
2762
2763 /*
2764  * Show the status of the media.  Similar to mii_check_media however it
2765  * correctly shows the link speed for all (tested) pcnet32 variants.
2766  * Devices with no mii just report link state without speed.
2767  *
2768  * Caller is assumed to hold and release the lp->lock.
2769  */
2770
2771 static void pcnet32_check_media(struct net_device *dev, int verbose)
2772 {
2773         struct pcnet32_private *lp = netdev_priv(dev);
2774         int curr_link;
2775         int prev_link = netif_carrier_ok(dev) ? 1 : 0;
2776         u32 bcr9;
2777
2778         if (lp->mii) {
2779                 curr_link = mii_link_ok(&lp->mii_if);
2780         } else {
2781                 ulong ioaddr = dev->base_addr;  /* card base I/O address */
2782                 curr_link = (lp->a.read_bcr(ioaddr, 4) != 0xc0);
2783         }
2784         if (!curr_link) {
2785                 if (prev_link || verbose) {
2786                         netif_carrier_off(dev);
2787                         netif_info(lp, link, dev, "link down\n");
2788                 }
2789                 if (lp->phycount > 1) {
2790                         curr_link = pcnet32_check_otherphy(dev);
2791                         prev_link = 0;
2792                 }
2793         } else if (verbose || !prev_link) {
2794                 netif_carrier_on(dev);
2795                 if (lp->mii) {
2796                         if (netif_msg_link(lp)) {
2797                                 struct ethtool_cmd ecmd;
2798                                 mii_ethtool_gset(&lp->mii_if, &ecmd);
2799                                 netdev_info(dev, "link up, %sMbps, %s-duplex\n",
2800                                             (ecmd.speed == SPEED_100)
2801                                             ? "100" : "10",
2802                                             (ecmd.duplex == DUPLEX_FULL)
2803                                             ? "full" : "half");
2804                         }
2805                         bcr9 = lp->a.read_bcr(dev->base_addr, 9);
2806                         if ((bcr9 & (1 << 0)) != lp->mii_if.full_duplex) {
2807                                 if (lp->mii_if.full_duplex)
2808                                         bcr9 |= (1 << 0);
2809                                 else
2810                                         bcr9 &= ~(1 << 0);
2811                                 lp->a.write_bcr(dev->base_addr, 9, bcr9);
2812                         }
2813                 } else {
2814                         netif_info(lp, link, dev, "link up\n");
2815                 }
2816         }
2817 }
2818
2819 /*
2820  * Check for loss of link and link establishment.
2821  * Can not use mii_check_media because it does nothing if mode is forced.
2822  */
2823
2824 static void pcnet32_watchdog(struct net_device *dev)
2825 {
2826         struct pcnet32_private *lp = netdev_priv(dev);
2827         unsigned long flags;
2828
2829         /* Print the link status if it has changed */
2830         spin_lock_irqsave(&lp->lock, flags);
2831         pcnet32_check_media(dev, 0);
2832         spin_unlock_irqrestore(&lp->lock, flags);
2833
2834         mod_timer(&lp->watchdog_timer, round_jiffies(PCNET32_WATCHDOG_TIMEOUT));
2835 }
2836
2837 static int pcnet32_pm_suspend(struct pci_dev *pdev, pm_message_t state)
2838 {
2839         struct net_device *dev = pci_get_drvdata(pdev);
2840
2841         if (netif_running(dev)) {
2842                 netif_device_detach(dev);
2843                 pcnet32_close(dev);
2844         }
2845         pci_save_state(pdev);
2846         pci_set_power_state(pdev, pci_choose_state(pdev, state));
2847         return 0;
2848 }
2849
2850 static int pcnet32_pm_resume(struct pci_dev *pdev)
2851 {
2852         struct net_device *dev = pci_get_drvdata(pdev);
2853
2854         pci_set_power_state(pdev, PCI_D0);
2855         pci_restore_state(pdev);
2856
2857         if (netif_running(dev)) {
2858                 pcnet32_open(dev);
2859                 netif_device_attach(dev);
2860         }
2861         return 0;
2862 }
2863
2864 static void __devexit pcnet32_remove_one(struct pci_dev *pdev)
2865 {
2866         struct net_device *dev = pci_get_drvdata(pdev);
2867
2868         if (dev) {
2869                 struct pcnet32_private *lp = netdev_priv(dev);
2870
2871                 unregister_netdev(dev);
2872                 pcnet32_free_ring(dev);
2873                 release_region(dev->base_addr, PCNET32_TOTAL_SIZE);
2874                 pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block),
2875                                     lp->init_block, lp->init_dma_addr);
2876                 free_netdev(dev);
2877                 pci_disable_device(pdev);
2878                 pci_set_drvdata(pdev, NULL);
2879         }
2880 }
2881
2882 static struct pci_driver pcnet32_driver = {
2883         .name = DRV_NAME,
2884         .probe = pcnet32_probe_pci,
2885         .remove = __devexit_p(pcnet32_remove_one),
2886         .id_table = pcnet32_pci_tbl,
2887         .suspend = pcnet32_pm_suspend,
2888         .resume = pcnet32_pm_resume,
2889 };
2890
2891 /* An additional parameter that may be passed in... */
2892 static int debug = -1;
2893 static int tx_start_pt = -1;
2894 static int pcnet32_have_pci;
2895
2896 module_param(debug, int, 0);
2897 MODULE_PARM_DESC(debug, DRV_NAME " debug level");
2898 module_param(max_interrupt_work, int, 0);
2899 MODULE_PARM_DESC(max_interrupt_work,
2900                  DRV_NAME " maximum events handled per interrupt");
2901 module_param(rx_copybreak, int, 0);
2902 MODULE_PARM_DESC(rx_copybreak,
2903                  DRV_NAME " copy breakpoint for copy-only-tiny-frames");
2904 module_param(tx_start_pt, int, 0);
2905 MODULE_PARM_DESC(tx_start_pt, DRV_NAME " transmit start point (0-3)");
2906 module_param(pcnet32vlb, int, 0);
2907 MODULE_PARM_DESC(pcnet32vlb, DRV_NAME " Vesa local bus (VLB) support (0/1)");
2908 module_param_array(options, int, NULL, 0);
2909 MODULE_PARM_DESC(options, DRV_NAME " initial option setting(s) (0-15)");
2910 module_param_array(full_duplex, int, NULL, 0);
2911 MODULE_PARM_DESC(full_duplex, DRV_NAME " full duplex setting(s) (1)");
2912 /* Module Parameter for HomePNA cards added by Patrick Simmons, 2004 */
2913 module_param_array(homepna, int, NULL, 0);
2914 MODULE_PARM_DESC(homepna,
2915                  DRV_NAME
2916                  " mode for 79C978 cards (1 for HomePNA, 0 for Ethernet, default Ethernet");
2917
2918 MODULE_AUTHOR("Thomas Bogendoerfer");
2919 MODULE_DESCRIPTION("Driver for PCnet32 and PCnetPCI based ethercards");
2920 MODULE_LICENSE("GPL");
2921
2922 #define PCNET32_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
2923
2924 static int __init pcnet32_init_module(void)
2925 {
2926         pr_info("%s", version);
2927
2928         pcnet32_debug = netif_msg_init(debug, PCNET32_MSG_DEFAULT);
2929
2930         if ((tx_start_pt >= 0) && (tx_start_pt <= 3))
2931                 tx_start = tx_start_pt;
2932
2933         /* find the PCI devices */
2934         if (!pci_register_driver(&pcnet32_driver))
2935                 pcnet32_have_pci = 1;
2936
2937         /* should we find any remaining VLbus devices ? */
2938         if (pcnet32vlb)
2939                 pcnet32_probe_vlbus(pcnet32_portlist);
2940
2941         if (cards_found && (pcnet32_debug & NETIF_MSG_PROBE))
2942                 pr_info("%d cards_found\n", cards_found);
2943
2944         return (pcnet32_have_pci + cards_found) ? 0 : -ENODEV;
2945 }
2946
2947 static void __exit pcnet32_cleanup_module(void)
2948 {
2949         struct net_device *next_dev;
2950
2951         while (pcnet32_dev) {
2952                 struct pcnet32_private *lp = netdev_priv(pcnet32_dev);
2953                 next_dev = lp->next;
2954                 unregister_netdev(pcnet32_dev);
2955                 pcnet32_free_ring(pcnet32_dev);
2956                 release_region(pcnet32_dev->base_addr, PCNET32_TOTAL_SIZE);
2957                 pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block),
2958                                     lp->init_block, lp->init_dma_addr);
2959                 free_netdev(pcnet32_dev);
2960                 pcnet32_dev = next_dev;
2961         }
2962
2963         if (pcnet32_have_pci)
2964                 pci_unregister_driver(&pcnet32_driver);
2965 }
2966
2967 module_init(pcnet32_init_module);
2968 module_exit(pcnet32_cleanup_module);
2969
2970 /*
2971  * Local variables:
2972  *  c-indent-level: 4
2973  *  tab-width: 8
2974  * End:
2975  */