2 * AMD 10Gb Ethernet PHY driver
4 * This file is available to you under your choice of the following two
9 * Copyright (c) 2014 Advanced Micro Devices, Inc.
11 * This file is free software; you may copy, redistribute and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation, either version 2 of the License, or (at
14 * your option) any later version.
16 * This file is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program. If not, see <http://www.gnu.org/licenses/>.
25 * License 2: Modified BSD
27 * Copyright (c) 2014 Advanced Micro Devices, Inc.
28 * All rights reserved.
30 * Redistribution and use in source and binary forms, with or without
31 * modification, are permitted provided that the following conditions are met:
32 * * Redistributions of source code must retain the above copyright
33 * notice, this list of conditions and the following disclaimer.
34 * * Redistributions in binary form must reproduce the above copyright
35 * notice, this list of conditions and the following disclaimer in the
36 * documentation and/or other materials provided with the distribution.
37 * * Neither the name of Advanced Micro Devices, Inc. nor the
38 * names of its contributors may be used to endorse or promote products
39 * derived from this software without specific prior written permission.
41 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
42 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
43 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
44 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
45 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
46 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
47 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
48 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
49 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
50 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
53 #include <linux/kernel.h>
54 #include <linux/device.h>
55 #include <linux/platform_device.h>
56 #include <linux/string.h>
57 #include <linux/errno.h>
58 #include <linux/unistd.h>
59 #include <linux/slab.h>
60 #include <linux/interrupt.h>
61 #include <linux/init.h>
62 #include <linux/delay.h>
63 #include <linux/netdevice.h>
64 #include <linux/etherdevice.h>
65 #include <linux/skbuff.h>
67 #include <linux/module.h>
68 #include <linux/mii.h>
69 #include <linux/ethtool.h>
70 #include <linux/phy.h>
71 #include <linux/mdio.h>
74 #include <linux/of_platform.h>
75 #include <linux/of_device.h>
76 #include <linux/uaccess.h>
80 MODULE_AUTHOR("Tom Lendacky <thomas.lendacky@amd.com>");
81 MODULE_LICENSE("Dual BSD/GPL");
82 MODULE_VERSION("1.0.0-a");
83 MODULE_DESCRIPTION("AMD 10GbE (amd-xgbe) PHY driver");
85 #define XGBE_PHY_ID 0x000162d0
86 #define XGBE_PHY_MASK 0xfffffff0
88 #define XGBE_AN_INT_CMPLT 0x01
89 #define XGBE_AN_INC_LINK 0x02
90 #define XGBE_AN_PG_RCV 0x04
92 #define XNP_MCF_NULL_MESSAGE 0x001
93 #define XNP_ACK_PROCESSED (1 << 12)
94 #define XNP_MP_FORMATTED (1 << 13)
95 #define XNP_NP_EXCHANGE (1 << 15)
97 #ifndef MDIO_PMA_10GBR_PMD_CTRL
98 #define MDIO_PMA_10GBR_PMD_CTRL 0x0096
100 #ifndef MDIO_PMA_10GBR_FEC_CTRL
101 #define MDIO_PMA_10GBR_FEC_CTRL 0x00ab
104 #define MDIO_AN_XNP 0x0016
107 #ifndef MDIO_AN_INTMASK
108 #define MDIO_AN_INTMASK 0x8001
111 #define MDIO_AN_INT 0x8002
114 #ifndef MDIO_CTRL1_SPEED1G
115 #define MDIO_CTRL1_SPEED1G (MDIO_CTRL1_SPEED10G & ~BMCR_SPEED100)
118 /* SerDes integration register offsets */
119 #define SIR0_STATUS 0x0040
120 #define SIR1_SPEED 0x0000
122 /* SerDes integration register entry bit positions and sizes */
123 #define SIR0_STATUS_RX_READY_INDEX 0
124 #define SIR0_STATUS_RX_READY_WIDTH 1
125 #define SIR0_STATUS_TX_READY_INDEX 8
126 #define SIR0_STATUS_TX_READY_WIDTH 1
127 #define SIR1_SPEED_DATARATE_INDEX 4
128 #define SIR1_SPEED_DATARATE_WIDTH 2
129 #define SIR1_SPEED_PI_SPD_SEL_INDEX 12
130 #define SIR1_SPEED_PI_SPD_SEL_WIDTH 4
131 #define SIR1_SPEED_PLLSEL_INDEX 3
132 #define SIR1_SPEED_PLLSEL_WIDTH 1
133 #define SIR1_SPEED_RATECHANGE_INDEX 6
134 #define SIR1_SPEED_RATECHANGE_WIDTH 1
135 #define SIR1_SPEED_TXAMP_INDEX 8
136 #define SIR1_SPEED_TXAMP_WIDTH 4
137 #define SIR1_SPEED_WORDMODE_INDEX 0
138 #define SIR1_SPEED_WORDMODE_WIDTH 3
140 #define SPEED_10000_CDR 0x7
141 #define SPEED_10000_PLL 0x1
142 #define SPEED_10000_RATE 0x0
143 #define SPEED_10000_TXAMP 0xa
144 #define SPEED_10000_WORD 0x7
146 #define SPEED_2500_CDR 0x2
147 #define SPEED_2500_PLL 0x0
148 #define SPEED_2500_RATE 0x2
149 #define SPEED_2500_TXAMP 0xf
150 #define SPEED_2500_WORD 0x1
152 #define SPEED_1000_CDR 0x2
153 #define SPEED_1000_PLL 0x0
154 #define SPEED_1000_RATE 0x3
155 #define SPEED_1000_TXAMP 0xf
156 #define SPEED_1000_WORD 0x1
159 /* SerDes RxTx register offsets */
160 #define RXTX_REG20 0x0050
161 #define RXTX_REG114 0x01c8
163 /* SerDes RxTx register entry bit positions and sizes */
164 #define RXTX_REG20_BLWC_ENA_INDEX 2
165 #define RXTX_REG20_BLWC_ENA_WIDTH 1
166 #define RXTX_REG114_PQ_REG_INDEX 9
167 #define RXTX_REG114_PQ_REG_WIDTH 7
169 #define RXTX_10000_BLWC 0
170 #define RXTX_10000_PQ 0x1e
172 #define RXTX_2500_BLWC 1
173 #define RXTX_2500_PQ 0xa
175 #define RXTX_1000_BLWC 1
176 #define RXTX_1000_PQ 0xa
178 /* Bit setting and getting macros
179 * The get macro will extract the current bit field value from within
182 * The set macro will clear the current bit field value within the
183 * variable and then set the bit field of the variable to the
186 #define GET_BITS(_var, _index, _width) \
187 (((_var) >> (_index)) & ((0x1 << (_width)) - 1))
189 #define SET_BITS(_var, _index, _width, _val) \
191 (_var) &= ~(((0x1 << (_width)) - 1) << (_index)); \
192 (_var) |= (((_val) & ((0x1 << (_width)) - 1)) << (_index)); \
195 /* Macros for reading or writing SerDes integration registers
196 * The ioread macros will get bit fields or full values using the
197 * register definitions formed using the input names
199 * The iowrite macros will set bit fields or full values using the
200 * register definitions formed using the input names
202 #define XSIR0_IOREAD(_priv, _reg) \
203 ioread16((_priv)->sir0_regs + _reg)
205 #define XSIR0_IOREAD_BITS(_priv, _reg, _field) \
206 GET_BITS(XSIR0_IOREAD((_priv), _reg), \
207 _reg##_##_field##_INDEX, \
208 _reg##_##_field##_WIDTH)
210 #define XSIR0_IOWRITE(_priv, _reg, _val) \
211 iowrite16((_val), (_priv)->sir0_regs + _reg)
213 #define XSIR0_IOWRITE_BITS(_priv, _reg, _field, _val) \
215 u16 reg_val = XSIR0_IOREAD((_priv), _reg); \
217 _reg##_##_field##_INDEX, \
218 _reg##_##_field##_WIDTH, (_val)); \
219 XSIR0_IOWRITE((_priv), _reg, reg_val); \
222 #define XSIR1_IOREAD(_priv, _reg) \
223 ioread16((_priv)->sir1_regs + _reg)
225 #define XSIR1_IOREAD_BITS(_priv, _reg, _field) \
226 GET_BITS(XSIR1_IOREAD((_priv), _reg), \
227 _reg##_##_field##_INDEX, \
228 _reg##_##_field##_WIDTH)
230 #define XSIR1_IOWRITE(_priv, _reg, _val) \
231 iowrite16((_val), (_priv)->sir1_regs + _reg)
233 #define XSIR1_IOWRITE_BITS(_priv, _reg, _field, _val) \
235 u16 reg_val = XSIR1_IOREAD((_priv), _reg); \
237 _reg##_##_field##_INDEX, \
238 _reg##_##_field##_WIDTH, (_val)); \
239 XSIR1_IOWRITE((_priv), _reg, reg_val); \
243 /* Macros for reading or writing SerDes RxTx registers
244 * The ioread macros will get bit fields or full values using the
245 * register definitions formed using the input names
247 * The iowrite macros will set bit fields or full values using the
248 * register definitions formed using the input names
250 #define XRXTX_IOREAD(_priv, _reg) \
251 ioread16((_priv)->rxtx_regs + _reg)
253 #define XRXTX_IOREAD_BITS(_priv, _reg, _field) \
254 GET_BITS(XRXTX_IOREAD((_priv), _reg), \
255 _reg##_##_field##_INDEX, \
256 _reg##_##_field##_WIDTH)
258 #define XRXTX_IOWRITE(_priv, _reg, _val) \
259 iowrite16((_val), (_priv)->rxtx_regs + _reg)
261 #define XRXTX_IOWRITE_BITS(_priv, _reg, _field, _val) \
263 u16 reg_val = XRXTX_IOREAD((_priv), _reg); \
265 _reg##_##_field##_INDEX, \
266 _reg##_##_field##_WIDTH, (_val)); \
267 XRXTX_IOWRITE((_priv), _reg, reg_val); \
271 enum amd_xgbe_phy_an {
272 AMD_XGBE_AN_READY = 0,
275 AMD_XGBE_AN_PAGE_RECEIVED,
276 AMD_XGBE_AN_INCOMPAT_LINK,
277 AMD_XGBE_AN_COMPLETE,
283 enum amd_xgbe_phy_rx {
284 AMD_XGBE_RX_READY = 0,
287 AMD_XGBE_RX_COMPLETE,
290 enum amd_xgbe_phy_mode {
295 struct amd_xgbe_phy_priv {
296 struct platform_device *pdev;
299 struct phy_device *phydev;
301 /* SerDes related mmio resources */
302 struct resource *rxtx_res;
303 struct resource *sir0_res;
304 struct resource *sir1_res;
306 /* SerDes related mmio registers */
307 void __iomem *rxtx_regs; /* SerDes Rx/Tx CSRs */
308 void __iomem *sir0_regs; /* SerDes integration registers (1/2) */
309 void __iomem *sir1_regs; /* SerDes integration registers (2/2) */
311 /* Maintain link status for re-starting auto-negotiation */
313 enum amd_xgbe_phy_mode mode;
315 /* Auto-negotiation state machine support */
316 struct mutex an_mutex;
317 enum amd_xgbe_phy_an an_result;
318 enum amd_xgbe_phy_an an_state;
319 enum amd_xgbe_phy_rx kr_state;
320 enum amd_xgbe_phy_rx kx_state;
321 struct work_struct an_work;
322 struct workqueue_struct *an_workqueue;
325 static int amd_xgbe_an_enable_kr_training(struct phy_device *phydev)
329 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL);
334 phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, ret);
339 static int amd_xgbe_an_disable_kr_training(struct phy_device *phydev)
343 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL);
348 phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, ret);
353 static int amd_xgbe_phy_pcs_power_cycle(struct phy_device *phydev)
357 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1);
361 ret |= MDIO_CTRL1_LPOWER;
362 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, ret);
364 usleep_range(75, 100);
366 ret &= ~MDIO_CTRL1_LPOWER;
367 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, ret);
372 static void amd_xgbe_phy_serdes_start_ratechange(struct phy_device *phydev)
374 struct amd_xgbe_phy_priv *priv = phydev->priv;
376 /* Assert Rx and Tx ratechange */
377 XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, RATECHANGE, 1);
380 static void amd_xgbe_phy_serdes_complete_ratechange(struct phy_device *phydev)
382 struct amd_xgbe_phy_priv *priv = phydev->priv;
384 /* Release Rx and Tx ratechange */
385 XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, RATECHANGE, 0);
387 /* Wait for Rx and Tx ready */
388 while (!XSIR0_IOREAD_BITS(priv, SIR0_STATUS, RX_READY) &&
389 !XSIR0_IOREAD_BITS(priv, SIR0_STATUS, TX_READY))
390 usleep_range(10, 20);
393 static int amd_xgbe_phy_xgmii_mode(struct phy_device *phydev)
395 struct amd_xgbe_phy_priv *priv = phydev->priv;
398 /* Enable KR training */
399 ret = amd_xgbe_an_enable_kr_training(phydev);
403 /* Set PCS to KR/10G speed */
404 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL2);
408 ret &= ~MDIO_PCS_CTRL2_TYPE;
409 ret |= MDIO_PCS_CTRL2_10GBR;
410 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL2, ret);
412 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1);
416 ret &= ~MDIO_CTRL1_SPEEDSEL;
417 ret |= MDIO_CTRL1_SPEED10G;
418 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, ret);
420 ret = amd_xgbe_phy_pcs_power_cycle(phydev);
424 /* Set SerDes to 10G speed */
425 amd_xgbe_phy_serdes_start_ratechange(phydev);
427 XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, DATARATE, SPEED_10000_RATE);
428 XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, WORDMODE, SPEED_10000_WORD);
429 XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, TXAMP, SPEED_10000_TXAMP);
430 XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, PLLSEL, SPEED_10000_PLL);
431 XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, PI_SPD_SEL, SPEED_10000_CDR);
433 XRXTX_IOWRITE_BITS(priv, RXTX_REG20, BLWC_ENA, RXTX_10000_BLWC);
434 XRXTX_IOWRITE_BITS(priv, RXTX_REG114, PQ_REG, RXTX_10000_PQ);
436 amd_xgbe_phy_serdes_complete_ratechange(phydev);
438 priv->mode = AMD_XGBE_MODE_KR;
443 static int amd_xgbe_phy_gmii_2500_mode(struct phy_device *phydev)
445 struct amd_xgbe_phy_priv *priv = phydev->priv;
448 /* Disable KR training */
449 ret = amd_xgbe_an_disable_kr_training(phydev);
453 /* Set PCS to KX/1G speed */
454 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL2);
458 ret &= ~MDIO_PCS_CTRL2_TYPE;
459 ret |= MDIO_PCS_CTRL2_10GBX;
460 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL2, ret);
462 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1);
466 ret &= ~MDIO_CTRL1_SPEEDSEL;
467 ret |= MDIO_CTRL1_SPEED1G;
468 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, ret);
470 ret = amd_xgbe_phy_pcs_power_cycle(phydev);
474 /* Set SerDes to 2.5G speed */
475 amd_xgbe_phy_serdes_start_ratechange(phydev);
477 XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, DATARATE, SPEED_2500_RATE);
478 XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, WORDMODE, SPEED_2500_WORD);
479 XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, TXAMP, SPEED_2500_TXAMP);
480 XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, PLLSEL, SPEED_2500_PLL);
481 XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, PI_SPD_SEL, SPEED_2500_CDR);
483 XRXTX_IOWRITE_BITS(priv, RXTX_REG20, BLWC_ENA, RXTX_2500_BLWC);
484 XRXTX_IOWRITE_BITS(priv, RXTX_REG114, PQ_REG, RXTX_2500_PQ);
486 amd_xgbe_phy_serdes_complete_ratechange(phydev);
488 priv->mode = AMD_XGBE_MODE_KX;
493 static int amd_xgbe_phy_gmii_mode(struct phy_device *phydev)
495 struct amd_xgbe_phy_priv *priv = phydev->priv;
498 /* Disable KR training */
499 ret = amd_xgbe_an_disable_kr_training(phydev);
503 /* Set PCS to KX/1G speed */
504 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL2);
508 ret &= ~MDIO_PCS_CTRL2_TYPE;
509 ret |= MDIO_PCS_CTRL2_10GBX;
510 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL2, ret);
512 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1);
516 ret &= ~MDIO_CTRL1_SPEEDSEL;
517 ret |= MDIO_CTRL1_SPEED1G;
518 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, ret);
520 ret = amd_xgbe_phy_pcs_power_cycle(phydev);
524 /* Set SerDes to 1G speed */
525 amd_xgbe_phy_serdes_start_ratechange(phydev);
527 XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, DATARATE, SPEED_1000_RATE);
528 XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, WORDMODE, SPEED_1000_WORD);
529 XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, TXAMP, SPEED_1000_TXAMP);
530 XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, PLLSEL, SPEED_1000_PLL);
531 XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, PI_SPD_SEL, SPEED_1000_CDR);
533 XRXTX_IOWRITE_BITS(priv, RXTX_REG20, BLWC_ENA, RXTX_1000_BLWC);
534 XRXTX_IOWRITE_BITS(priv, RXTX_REG114, PQ_REG, RXTX_1000_PQ);
536 amd_xgbe_phy_serdes_complete_ratechange(phydev);
538 priv->mode = AMD_XGBE_MODE_KX;
543 static int amd_xgbe_phy_switch_mode(struct phy_device *phydev)
545 struct amd_xgbe_phy_priv *priv = phydev->priv;
548 /* If we are in KR switch to KX, and vice-versa */
549 if (priv->mode == AMD_XGBE_MODE_KR)
550 ret = amd_xgbe_phy_gmii_mode(phydev);
552 ret = amd_xgbe_phy_xgmii_mode(phydev);
557 static enum amd_xgbe_phy_an amd_xgbe_an_switch_mode(struct phy_device *phydev)
561 ret = amd_xgbe_phy_switch_mode(phydev);
563 return AMD_XGBE_AN_ERROR;
565 return AMD_XGBE_AN_START;
568 static enum amd_xgbe_phy_an amd_xgbe_an_tx_training(struct phy_device *phydev,
569 enum amd_xgbe_phy_rx *state)
571 struct amd_xgbe_phy_priv *priv = phydev->priv;
572 int ad_reg, lp_reg, ret;
574 *state = AMD_XGBE_RX_COMPLETE;
576 /* If we're in KX mode then we're done */
577 if (priv->mode == AMD_XGBE_MODE_KX)
578 return AMD_XGBE_AN_EVENT;
580 /* Enable/Disable FEC */
581 ad_reg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
583 return AMD_XGBE_AN_ERROR;
585 lp_reg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_LPA + 2);
587 return AMD_XGBE_AN_ERROR;
589 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FEC_CTRL);
591 return AMD_XGBE_AN_ERROR;
593 if ((ad_reg & 0xc000) && (lp_reg & 0xc000))
598 phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FEC_CTRL, ret);
600 /* Start KR training */
601 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL);
603 return AMD_XGBE_AN_ERROR;
606 phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, ret);
608 return AMD_XGBE_AN_EVENT;
611 static enum amd_xgbe_phy_an amd_xgbe_an_tx_xnp(struct phy_device *phydev,
612 enum amd_xgbe_phy_rx *state)
616 *state = AMD_XGBE_RX_XNP;
618 msg = XNP_MCF_NULL_MESSAGE;
619 msg |= XNP_MP_FORMATTED;
621 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_XNP + 2, 0);
622 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_XNP + 1, 0);
623 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_XNP, msg);
625 return AMD_XGBE_AN_EVENT;
628 static enum amd_xgbe_phy_an amd_xgbe_an_rx_bpa(struct phy_device *phydev,
629 enum amd_xgbe_phy_rx *state)
631 struct amd_xgbe_phy_priv *priv = phydev->priv;
632 unsigned int link_support;
633 int ret, ad_reg, lp_reg;
635 /* Read Base Ability register 2 first */
636 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_LPA + 1);
638 return AMD_XGBE_AN_ERROR;
640 /* Check for a supported mode, otherwise restart in a different one */
641 link_support = (priv->mode == AMD_XGBE_MODE_KR) ? 0x80 : 0x20;
642 if (!(ret & link_support))
643 return amd_xgbe_an_switch_mode(phydev);
645 /* Check Extended Next Page support */
646 ad_reg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
648 return AMD_XGBE_AN_ERROR;
650 lp_reg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_LPA);
652 return AMD_XGBE_AN_ERROR;
654 return ((ad_reg & XNP_NP_EXCHANGE) || (lp_reg & XNP_NP_EXCHANGE)) ?
655 amd_xgbe_an_tx_xnp(phydev, state) :
656 amd_xgbe_an_tx_training(phydev, state);
659 static enum amd_xgbe_phy_an amd_xgbe_an_rx_xnp(struct phy_device *phydev,
660 enum amd_xgbe_phy_rx *state)
664 /* Check Extended Next Page support */
665 ad_reg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
667 return AMD_XGBE_AN_ERROR;
669 lp_reg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_LPA);
671 return AMD_XGBE_AN_ERROR;
673 return ((ad_reg & XNP_NP_EXCHANGE) || (lp_reg & XNP_NP_EXCHANGE)) ?
674 amd_xgbe_an_tx_xnp(phydev, state) :
675 amd_xgbe_an_tx_training(phydev, state);
678 static enum amd_xgbe_phy_an amd_xgbe_an_start(struct phy_device *phydev)
680 struct amd_xgbe_phy_priv *priv = phydev->priv;
683 /* Be sure we aren't looping trying to negotiate */
684 if (priv->mode == AMD_XGBE_MODE_KR) {
685 if (priv->kr_state != AMD_XGBE_RX_READY)
686 return AMD_XGBE_AN_NO_LINK;
687 priv->kr_state = AMD_XGBE_RX_BPA;
689 if (priv->kx_state != AMD_XGBE_RX_READY)
690 return AMD_XGBE_AN_NO_LINK;
691 priv->kx_state = AMD_XGBE_RX_BPA;
694 /* Set up Advertisement register 3 first */
695 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
697 return AMD_XGBE_AN_ERROR;
699 if (phydev->supported & SUPPORTED_10000baseR_FEC)
704 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2, ret);
706 /* Set up Advertisement register 2 next */
707 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1);
709 return AMD_XGBE_AN_ERROR;
711 if (phydev->supported & SUPPORTED_10000baseKR_Full)
716 if (phydev->supported & SUPPORTED_1000baseKX_Full)
721 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1, ret);
723 /* Set up Advertisement register 1 last */
724 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
726 return AMD_XGBE_AN_ERROR;
728 if (phydev->supported & SUPPORTED_Pause)
733 if (phydev->supported & SUPPORTED_Asym_Pause)
738 /* We don't intend to perform XNP */
739 ret &= ~XNP_NP_EXCHANGE;
741 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE, ret);
743 /* Enable and start auto-negotiation */
744 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_INT, 0);
746 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1);
748 return AMD_XGBE_AN_ERROR;
750 ret |= MDIO_AN_CTRL1_ENABLE;
751 ret |= MDIO_AN_CTRL1_RESTART;
752 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1, ret);
754 return AMD_XGBE_AN_EVENT;
757 static enum amd_xgbe_phy_an amd_xgbe_an_event(struct phy_device *phydev)
759 enum amd_xgbe_phy_an new_state;
762 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_INT);
764 return AMD_XGBE_AN_ERROR;
766 new_state = AMD_XGBE_AN_EVENT;
767 if (ret & XGBE_AN_PG_RCV)
768 new_state = AMD_XGBE_AN_PAGE_RECEIVED;
769 else if (ret & XGBE_AN_INC_LINK)
770 new_state = AMD_XGBE_AN_INCOMPAT_LINK;
771 else if (ret & XGBE_AN_INT_CMPLT)
772 new_state = AMD_XGBE_AN_COMPLETE;
774 if (new_state != AMD_XGBE_AN_EVENT)
775 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_INT, 0);
780 static enum amd_xgbe_phy_an amd_xgbe_an_page_received(struct phy_device *phydev)
782 struct amd_xgbe_phy_priv *priv = phydev->priv;
783 enum amd_xgbe_phy_rx *state;
786 state = (priv->mode == AMD_XGBE_MODE_KR) ? &priv->kr_state
790 case AMD_XGBE_RX_BPA:
791 ret = amd_xgbe_an_rx_bpa(phydev, state);
794 case AMD_XGBE_RX_XNP:
795 ret = amd_xgbe_an_rx_xnp(phydev, state);
799 ret = AMD_XGBE_AN_ERROR;
805 static enum amd_xgbe_phy_an amd_xgbe_an_incompat_link(struct phy_device *phydev)
807 return amd_xgbe_an_switch_mode(phydev);
810 static void amd_xgbe_an_state_machine(struct work_struct *work)
812 struct amd_xgbe_phy_priv *priv = container_of(work,
813 struct amd_xgbe_phy_priv,
815 struct phy_device *phydev = priv->phydev;
816 enum amd_xgbe_phy_an cur_state;
820 mutex_lock(&priv->an_mutex);
822 cur_state = priv->an_state;
824 switch (priv->an_state) {
825 case AMD_XGBE_AN_START:
826 priv->an_state = amd_xgbe_an_start(phydev);
829 case AMD_XGBE_AN_EVENT:
830 priv->an_state = amd_xgbe_an_event(phydev);
833 case AMD_XGBE_AN_PAGE_RECEIVED:
834 priv->an_state = amd_xgbe_an_page_received(phydev);
837 case AMD_XGBE_AN_INCOMPAT_LINK:
838 priv->an_state = amd_xgbe_an_incompat_link(phydev);
841 case AMD_XGBE_AN_COMPLETE:
842 case AMD_XGBE_AN_NO_LINK:
843 case AMD_XGBE_AN_EXIT:
847 priv->an_state = AMD_XGBE_AN_ERROR;
850 if (priv->an_state == AMD_XGBE_AN_ERROR) {
851 netdev_err(phydev->attached_dev,
852 "error during auto-negotiation, state=%u\n",
857 sleep = (priv->an_state == AMD_XGBE_AN_EVENT) ? 1 : 0;
859 mutex_unlock(&priv->an_mutex);
862 usleep_range(20, 50);
866 priv->an_result = priv->an_state;
867 priv->an_state = AMD_XGBE_AN_READY;
869 mutex_unlock(&priv->an_mutex);
872 static int amd_xgbe_phy_soft_reset(struct phy_device *phydev)
876 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1);
880 ret |= MDIO_CTRL1_RESET;
881 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, ret);
886 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1);
889 } while ((ret & MDIO_CTRL1_RESET) && --count);
891 if (ret & MDIO_CTRL1_RESET)
897 static int amd_xgbe_phy_config_init(struct phy_device *phydev)
899 /* Initialize supported features */
900 phydev->supported = SUPPORTED_Autoneg;
901 phydev->supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
902 phydev->supported |= SUPPORTED_Backplane;
903 phydev->supported |= SUPPORTED_1000baseKX_Full |
904 SUPPORTED_2500baseX_Full;
905 phydev->supported |= SUPPORTED_10000baseKR_Full |
906 SUPPORTED_10000baseR_FEC;
907 phydev->advertising = phydev->supported;
909 /* Turn off and clear interrupts */
910 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_INTMASK, 0);
911 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_INT, 0);
916 static int amd_xgbe_phy_setup_forced(struct phy_device *phydev)
920 /* Disable auto-negotiation */
921 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1);
925 ret &= ~MDIO_AN_CTRL1_ENABLE;
926 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1, ret);
928 /* Validate/Set specified speed */
929 switch (phydev->speed) {
931 ret = amd_xgbe_phy_xgmii_mode(phydev);
935 ret = amd_xgbe_phy_gmii_2500_mode(phydev);
939 ret = amd_xgbe_phy_gmii_mode(phydev);
949 /* Validate duplex mode */
950 if (phydev->duplex != DUPLEX_FULL)
954 phydev->asym_pause = 0;
959 static int amd_xgbe_phy_config_aneg(struct phy_device *phydev)
961 struct amd_xgbe_phy_priv *priv = phydev->priv;
962 u32 mmd_mask = phydev->c45_ids.devices_in_package;
965 if (phydev->autoneg != AUTONEG_ENABLE)
966 return amd_xgbe_phy_setup_forced(phydev);
968 /* Make sure we have the AN MMD present */
969 if (!(mmd_mask & MDIO_DEVS_AN))
972 /* Get the current speed mode */
973 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL2);
977 /* Start/Restart the auto-negotiation state machine */
978 mutex_lock(&priv->an_mutex);
979 priv->an_result = AMD_XGBE_AN_READY;
980 priv->an_state = AMD_XGBE_AN_START;
981 priv->kr_state = AMD_XGBE_RX_READY;
982 priv->kx_state = AMD_XGBE_RX_READY;
983 mutex_unlock(&priv->an_mutex);
985 queue_work(priv->an_workqueue, &priv->an_work);
990 static int amd_xgbe_phy_aneg_done(struct phy_device *phydev)
992 struct amd_xgbe_phy_priv *priv = phydev->priv;
993 enum amd_xgbe_phy_an state;
995 mutex_lock(&priv->an_mutex);
996 state = priv->an_result;
997 mutex_unlock(&priv->an_mutex);
999 return (state == AMD_XGBE_AN_COMPLETE);
1002 static int amd_xgbe_phy_update_link(struct phy_device *phydev)
1004 struct amd_xgbe_phy_priv *priv = phydev->priv;
1005 enum amd_xgbe_phy_an state;
1006 unsigned int check_again, autoneg;
1009 /* If we're doing auto-negotiation don't report link down */
1010 mutex_lock(&priv->an_mutex);
1011 state = priv->an_state;
1012 mutex_unlock(&priv->an_mutex);
1014 if (state != AMD_XGBE_AN_READY) {
1019 /* Since the device can be in the wrong mode when a link is
1020 * (re-)established (cable connected after the interface is
1021 * up, etc.), the link status may report no link. If there
1022 * is no link, try switching modes and checking the status
1027 /* Link status is latched low, so read once to clear
1028 * and then read again to get current state
1030 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_STAT1);
1034 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_STAT1);
1038 phydev->link = (ret & MDIO_STAT1_LSTATUS) ? 1 : 0;
1040 if (!phydev->link) {
1041 ret = amd_xgbe_phy_switch_mode(phydev);
1048 autoneg = (phydev->link && !priv->link) ? 1 : 0;
1049 priv->link = phydev->link;
1051 /* Link is (back) up, re-start auto-negotiation */
1052 ret = amd_xgbe_phy_config_aneg(phydev);
1060 static int amd_xgbe_phy_read_status(struct phy_device *phydev)
1062 u32 mmd_mask = phydev->c45_ids.devices_in_package;
1063 int ret, mode, ad_ret, lp_ret;
1065 ret = amd_xgbe_phy_update_link(phydev);
1069 mode = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL2);
1072 mode &= MDIO_PCS_CTRL2_TYPE;
1074 if (phydev->autoneg == AUTONEG_ENABLE) {
1075 if (!(mmd_mask & MDIO_DEVS_AN))
1078 if (!amd_xgbe_phy_aneg_done(phydev))
1081 /* Compare Advertisement and Link Partner register 1 */
1082 ad_ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
1085 lp_ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_LPA);
1090 phydev->pause = (ad_ret & 0x400) ? 1 : 0;
1091 phydev->asym_pause = (ad_ret & 0x800) ? 1 : 0;
1093 /* Compare Advertisement and Link Partner register 2 */
1094 ad_ret = phy_read_mmd(phydev, MDIO_MMD_AN,
1095 MDIO_AN_ADVERTISE + 1);
1098 lp_ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_LPA + 1);
1103 if (ad_ret & 0x80) {
1104 phydev->speed = SPEED_10000;
1105 if (mode != MDIO_PCS_CTRL2_10GBR) {
1106 ret = amd_xgbe_phy_xgmii_mode(phydev);
1111 phydev->speed = SPEED_1000;
1112 if (mode == MDIO_PCS_CTRL2_10GBR) {
1113 ret = amd_xgbe_phy_gmii_mode(phydev);
1119 phydev->duplex = DUPLEX_FULL;
1121 phydev->speed = (mode == MDIO_PCS_CTRL2_10GBR) ? SPEED_10000
1123 phydev->duplex = DUPLEX_FULL;
1125 phydev->asym_pause = 0;
1131 static int amd_xgbe_phy_suspend(struct phy_device *phydev)
1135 mutex_lock(&phydev->lock);
1137 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1);
1141 ret |= MDIO_CTRL1_LPOWER;
1142 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, ret);
1147 mutex_unlock(&phydev->lock);
1152 static int amd_xgbe_phy_resume(struct phy_device *phydev)
1156 mutex_lock(&phydev->lock);
1158 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1);
1162 ret &= ~MDIO_CTRL1_LPOWER;
1163 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, ret);
1168 mutex_unlock(&phydev->lock);
1173 static int amd_xgbe_phy_probe(struct phy_device *phydev)
1175 struct amd_xgbe_phy_priv *priv;
1176 struct platform_device *pdev;
1181 if (!phydev->dev.of_node)
1184 pdev = of_find_device_by_node(phydev->dev.of_node);
1189 wq_name = kasprintf(GFP_KERNEL, "%s-amd-xgbe-phy", phydev->bus->name);
1195 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1203 priv->phydev = phydev;
1205 /* Get the device mmio areas */
1206 priv->rxtx_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1207 priv->rxtx_regs = devm_ioremap_resource(dev, priv->rxtx_res);
1208 if (IS_ERR(priv->rxtx_regs)) {
1209 dev_err(dev, "rxtx ioremap failed\n");
1210 ret = PTR_ERR(priv->rxtx_regs);
1214 priv->sir0_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1215 priv->sir0_regs = devm_ioremap_resource(dev, priv->sir0_res);
1216 if (IS_ERR(priv->sir0_regs)) {
1217 dev_err(dev, "sir0 ioremap failed\n");
1218 ret = PTR_ERR(priv->sir0_regs);
1222 priv->sir1_res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
1223 priv->sir1_regs = devm_ioremap_resource(dev, priv->sir1_res);
1224 if (IS_ERR(priv->sir1_regs)) {
1225 dev_err(dev, "sir1 ioremap failed\n");
1226 ret = PTR_ERR(priv->sir1_regs);
1232 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL2);
1235 if ((ret & MDIO_PCS_CTRL2_TYPE) == MDIO_PCS_CTRL2_10GBR)
1236 priv->mode = AMD_XGBE_MODE_KR;
1238 priv->mode = AMD_XGBE_MODE_KX;
1240 mutex_init(&priv->an_mutex);
1241 INIT_WORK(&priv->an_work, amd_xgbe_an_state_machine);
1242 priv->an_workqueue = create_singlethread_workqueue(wq_name);
1243 if (!priv->an_workqueue) {
1248 phydev->priv = priv;
1256 devm_iounmap(dev, priv->sir1_regs);
1257 devm_release_mem_region(dev, priv->sir1_res->start,
1258 resource_size(priv->sir1_res));
1261 devm_iounmap(dev, priv->sir0_regs);
1262 devm_release_mem_region(dev, priv->sir0_res->start,
1263 resource_size(priv->sir0_res));
1266 devm_iounmap(dev, priv->rxtx_regs);
1267 devm_release_mem_region(dev, priv->rxtx_res->start,
1268 resource_size(priv->rxtx_res));
1271 devm_kfree(dev, priv);
1282 static void amd_xgbe_phy_remove(struct phy_device *phydev)
1284 struct amd_xgbe_phy_priv *priv = phydev->priv;
1285 struct device *dev = priv->dev;
1287 /* Stop any in process auto-negotiation */
1288 mutex_lock(&priv->an_mutex);
1289 priv->an_state = AMD_XGBE_AN_EXIT;
1290 mutex_unlock(&priv->an_mutex);
1292 flush_workqueue(priv->an_workqueue);
1293 destroy_workqueue(priv->an_workqueue);
1295 /* Release resources */
1296 devm_iounmap(dev, priv->sir1_regs);
1297 devm_release_mem_region(dev, priv->sir1_res->start,
1298 resource_size(priv->sir1_res));
1300 devm_iounmap(dev, priv->sir0_regs);
1301 devm_release_mem_region(dev, priv->sir0_res->start,
1302 resource_size(priv->sir0_res));
1304 devm_iounmap(dev, priv->rxtx_regs);
1305 devm_release_mem_region(dev, priv->rxtx_res->start,
1306 resource_size(priv->rxtx_res));
1308 devm_kfree(dev, priv);
1311 static int amd_xgbe_match_phy_device(struct phy_device *phydev)
1313 return phydev->c45_ids.device_ids[MDIO_MMD_PCS] == XGBE_PHY_ID;
1316 static struct phy_driver amd_xgbe_phy_driver[] = {
1318 .phy_id = XGBE_PHY_ID,
1319 .phy_id_mask = XGBE_PHY_MASK,
1320 .name = "AMD XGBE PHY",
1322 .probe = amd_xgbe_phy_probe,
1323 .remove = amd_xgbe_phy_remove,
1324 .soft_reset = amd_xgbe_phy_soft_reset,
1325 .config_init = amd_xgbe_phy_config_init,
1326 .suspend = amd_xgbe_phy_suspend,
1327 .resume = amd_xgbe_phy_resume,
1328 .config_aneg = amd_xgbe_phy_config_aneg,
1329 .aneg_done = amd_xgbe_phy_aneg_done,
1330 .read_status = amd_xgbe_phy_read_status,
1331 .match_phy_device = amd_xgbe_match_phy_device,
1333 .owner = THIS_MODULE,
1338 static int __init amd_xgbe_phy_init(void)
1340 return phy_drivers_register(amd_xgbe_phy_driver,
1341 ARRAY_SIZE(amd_xgbe_phy_driver));
1344 static void __exit amd_xgbe_phy_exit(void)
1346 phy_drivers_unregister(amd_xgbe_phy_driver,
1347 ARRAY_SIZE(amd_xgbe_phy_driver));
1350 module_init(amd_xgbe_phy_init);
1351 module_exit(amd_xgbe_phy_exit);
1353 static struct mdio_device_id amd_xgbe_phy_ids[] = {
1354 { XGBE_PHY_ID, XGBE_PHY_MASK },
1357 MODULE_DEVICE_TABLE(mdio, amd_xgbe_phy_ids);