2 * drivers/net/phy/micrel.c
4 * Driver for Micrel PHYs
6 * Author: David J. Choi
8 * Copyright (c) 2010-2013 Micrel, Inc.
9 * Copyright (c) 2014 Johan Hovold <johan@kernel.org>
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
16 * Support : Micrel Phys:
17 * Giga phys: ksz9021, ksz9031
18 * 100/10 Phys : ksz8001, ksz8721, ksz8737, ksz8041
19 * ksz8021, ksz8031, ksz8051,
22 * Switch : ksz8873, ksz886x
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/phy.h>
28 #include <linux/micrel_phy.h>
30 #include <linux/clk.h>
32 /* Operation Mode Strap Override */
33 #define MII_KSZPHY_OMSO 0x16
34 #define KSZPHY_OMSO_B_CAST_OFF BIT(9)
35 #define KSZPHY_OMSO_NAND_TREE_ON BIT(5)
36 #define KSZPHY_OMSO_RMII_OVERRIDE BIT(1)
37 #define KSZPHY_OMSO_MII_OVERRIDE BIT(0)
39 /* general Interrupt control/status reg in vendor specific block. */
40 #define MII_KSZPHY_INTCS 0x1B
41 #define KSZPHY_INTCS_JABBER BIT(15)
42 #define KSZPHY_INTCS_RECEIVE_ERR BIT(14)
43 #define KSZPHY_INTCS_PAGE_RECEIVE BIT(13)
44 #define KSZPHY_INTCS_PARELLEL BIT(12)
45 #define KSZPHY_INTCS_LINK_PARTNER_ACK BIT(11)
46 #define KSZPHY_INTCS_LINK_DOWN BIT(10)
47 #define KSZPHY_INTCS_REMOTE_FAULT BIT(9)
48 #define KSZPHY_INTCS_LINK_UP BIT(8)
49 #define KSZPHY_INTCS_ALL (KSZPHY_INTCS_LINK_UP |\
50 KSZPHY_INTCS_LINK_DOWN)
53 #define MII_KSZPHY_CTRL_1 0x1e
55 /* PHY Control 2 / PHY Control (if no PHY Control 1) */
56 #define MII_KSZPHY_CTRL_2 0x1f
57 #define MII_KSZPHY_CTRL MII_KSZPHY_CTRL_2
58 /* bitmap of PHY register to set interrupt mode */
59 #define KSZPHY_CTRL_INT_ACTIVE_HIGH BIT(9)
60 #define KSZPHY_RMII_REF_CLK_SEL BIT(7)
62 /* Write/read to/from extended registers */
63 #define MII_KSZPHY_EXTREG 0x0b
64 #define KSZPHY_EXTREG_WRITE 0x8000
66 #define MII_KSZPHY_EXTREG_WRITE 0x0c
67 #define MII_KSZPHY_EXTREG_READ 0x0d
69 /* Extended registers */
70 #define MII_KSZPHY_CLK_CONTROL_PAD_SKEW 0x104
71 #define MII_KSZPHY_RX_DATA_PAD_SKEW 0x105
72 #define MII_KSZPHY_TX_DATA_PAD_SKEW 0x106
78 u16 interrupt_level_mask;
79 bool has_broadcast_disable;
80 bool has_nand_tree_disable;
81 bool has_rmii_ref_clk_sel;
85 const struct kszphy_type *type;
87 bool rmii_ref_clk_sel;
88 bool rmii_ref_clk_sel_val;
91 static const struct kszphy_type ksz8021_type = {
92 .led_mode_reg = MII_KSZPHY_CTRL_2,
93 .has_broadcast_disable = true,
94 .has_nand_tree_disable = true,
95 .has_rmii_ref_clk_sel = true,
98 static const struct kszphy_type ksz8041_type = {
99 .led_mode_reg = MII_KSZPHY_CTRL_1,
102 static const struct kszphy_type ksz8051_type = {
103 .led_mode_reg = MII_KSZPHY_CTRL_2,
104 .has_nand_tree_disable = true,
107 static const struct kszphy_type ksz8081_type = {
108 .led_mode_reg = MII_KSZPHY_CTRL_2,
109 .has_broadcast_disable = true,
110 .has_nand_tree_disable = true,
111 .has_rmii_ref_clk_sel = true,
114 static const struct kszphy_type ks8737_type = {
115 .interrupt_level_mask = BIT(14),
118 static const struct kszphy_type ksz9021_type = {
119 .interrupt_level_mask = BIT(14),
122 static int kszphy_extended_write(struct phy_device *phydev,
125 phy_write(phydev, MII_KSZPHY_EXTREG, KSZPHY_EXTREG_WRITE | regnum);
126 return phy_write(phydev, MII_KSZPHY_EXTREG_WRITE, val);
129 static int kszphy_extended_read(struct phy_device *phydev,
132 phy_write(phydev, MII_KSZPHY_EXTREG, regnum);
133 return phy_read(phydev, MII_KSZPHY_EXTREG_READ);
136 static int kszphy_ack_interrupt(struct phy_device *phydev)
138 /* bit[7..0] int status, which is a read and clear register. */
141 rc = phy_read(phydev, MII_KSZPHY_INTCS);
143 return (rc < 0) ? rc : 0;
146 static int kszphy_config_intr(struct phy_device *phydev)
148 const struct kszphy_type *type = phydev->drv->driver_data;
152 if (type && type->interrupt_level_mask)
153 mask = type->interrupt_level_mask;
155 mask = KSZPHY_CTRL_INT_ACTIVE_HIGH;
157 /* set the interrupt pin active low */
158 temp = phy_read(phydev, MII_KSZPHY_CTRL);
162 phy_write(phydev, MII_KSZPHY_CTRL, temp);
164 /* enable / disable interrupts */
165 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
166 temp = KSZPHY_INTCS_ALL;
170 return phy_write(phydev, MII_KSZPHY_INTCS, temp);
173 static int kszphy_rmii_clk_sel(struct phy_device *phydev, bool val)
177 ctrl = phy_read(phydev, MII_KSZPHY_CTRL);
182 ctrl |= KSZPHY_RMII_REF_CLK_SEL;
184 ctrl &= ~KSZPHY_RMII_REF_CLK_SEL;
186 return phy_write(phydev, MII_KSZPHY_CTRL, ctrl);
189 static int kszphy_setup_led(struct phy_device *phydev, u32 reg, int val)
194 case MII_KSZPHY_CTRL_1:
197 case MII_KSZPHY_CTRL_2:
204 temp = phy_read(phydev, reg);
210 temp &= ~(3 << shift);
211 temp |= val << shift;
212 rc = phy_write(phydev, reg, temp);
215 dev_err(&phydev->dev, "failed to set led mode\n");
220 /* Disable PHY address 0 as the broadcast address, so that it can be used as a
221 * unique (non-broadcast) address on a shared bus.
223 static int kszphy_broadcast_disable(struct phy_device *phydev)
227 ret = phy_read(phydev, MII_KSZPHY_OMSO);
231 ret = phy_write(phydev, MII_KSZPHY_OMSO, ret | KSZPHY_OMSO_B_CAST_OFF);
234 dev_err(&phydev->dev, "failed to disable broadcast address\n");
239 static int kszphy_nand_tree_disable(struct phy_device *phydev)
243 ret = phy_read(phydev, MII_KSZPHY_OMSO);
247 if (!(ret & KSZPHY_OMSO_NAND_TREE_ON))
250 ret = phy_write(phydev, MII_KSZPHY_OMSO,
251 ret & ~KSZPHY_OMSO_NAND_TREE_ON);
254 dev_err(&phydev->dev, "failed to disable NAND tree mode\n");
259 static int kszphy_config_init(struct phy_device *phydev)
261 struct kszphy_priv *priv = phydev->priv;
262 const struct kszphy_type *type;
270 if (type->has_broadcast_disable)
271 kszphy_broadcast_disable(phydev);
273 if (type->has_nand_tree_disable)
274 kszphy_nand_tree_disable(phydev);
276 if (priv->rmii_ref_clk_sel) {
277 ret = kszphy_rmii_clk_sel(phydev, priv->rmii_ref_clk_sel_val);
279 dev_err(&phydev->dev, "failed to set rmii reference clock\n");
284 if (priv->led_mode >= 0)
285 kszphy_setup_led(phydev, type->led_mode_reg, priv->led_mode);
290 static int ksz9021_load_values_from_of(struct phy_device *phydev,
291 const struct device_node *of_node,
293 const char *field1, const char *field2,
294 const char *field3, const char *field4)
303 if (!of_property_read_u32(of_node, field1, &val1))
306 if (!of_property_read_u32(of_node, field2, &val2))
309 if (!of_property_read_u32(of_node, field3, &val3))
312 if (!of_property_read_u32(of_node, field4, &val4))
319 newval = kszphy_extended_read(phydev, reg);
324 newval = ((newval & 0xfff0) | ((val1 / PS_TO_REG) & 0xf) << 0);
327 newval = ((newval & 0xff0f) | ((val2 / PS_TO_REG) & 0xf) << 4);
330 newval = ((newval & 0xf0ff) | ((val3 / PS_TO_REG) & 0xf) << 8);
333 newval = ((newval & 0x0fff) | ((val4 / PS_TO_REG) & 0xf) << 12);
335 return kszphy_extended_write(phydev, reg, newval);
338 static int ksz9021_config_init(struct phy_device *phydev)
340 const struct device *dev = &phydev->dev;
341 const struct device_node *of_node = dev->of_node;
342 const struct device *dev_walker;
344 /* The Micrel driver has a deprecated option to place phy OF
345 * properties in the MAC node. Walk up the tree of devices to
346 * find a device with an OF node.
348 dev_walker = &phydev->dev;
350 of_node = dev_walker->of_node;
351 dev_walker = dev_walker->parent;
353 } while (!of_node && dev_walker);
356 ksz9021_load_values_from_of(phydev, of_node,
357 MII_KSZPHY_CLK_CONTROL_PAD_SKEW,
358 "txen-skew-ps", "txc-skew-ps",
359 "rxdv-skew-ps", "rxc-skew-ps");
360 ksz9021_load_values_from_of(phydev, of_node,
361 MII_KSZPHY_RX_DATA_PAD_SKEW,
362 "rxd0-skew-ps", "rxd1-skew-ps",
363 "rxd2-skew-ps", "rxd3-skew-ps");
364 ksz9021_load_values_from_of(phydev, of_node,
365 MII_KSZPHY_TX_DATA_PAD_SKEW,
366 "txd0-skew-ps", "txd1-skew-ps",
367 "txd2-skew-ps", "txd3-skew-ps");
372 #define MII_KSZ9031RN_MMD_CTRL_REG 0x0d
373 #define MII_KSZ9031RN_MMD_REGDATA_REG 0x0e
375 #define KSZ9031_PS_TO_REG 60
377 /* Extended registers */
378 /* MMD Address 0x0 */
379 #define MII_KSZ9031RN_FLP_BURST_TX_LO 3
380 #define MII_KSZ9031RN_FLP_BURST_TX_HI 4
382 /* MMD Address 0x2 */
383 #define MII_KSZ9031RN_CONTROL_PAD_SKEW 4
384 #define MII_KSZ9031RN_RX_DATA_PAD_SKEW 5
385 #define MII_KSZ9031RN_TX_DATA_PAD_SKEW 6
386 #define MII_KSZ9031RN_CLK_PAD_SKEW 8
388 static int ksz9031_extended_write(struct phy_device *phydev,
389 u8 mode, u32 dev_addr, u32 regnum, u16 val)
391 phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, dev_addr);
392 phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, regnum);
393 phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, (mode << 14) | dev_addr);
394 return phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, val);
397 static int ksz9031_extended_read(struct phy_device *phydev,
398 u8 mode, u32 dev_addr, u32 regnum)
400 phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, dev_addr);
401 phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, regnum);
402 phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, (mode << 14) | dev_addr);
403 return phy_read(phydev, MII_KSZ9031RN_MMD_REGDATA_REG);
406 static int ksz9031_of_load_skew_values(struct phy_device *phydev,
407 const struct device_node *of_node,
408 u16 reg, size_t field_sz,
409 const char *field[], u8 numfields)
411 int val[4] = {-1, -2, -3, -4};
418 for (i = 0; i < numfields; i++)
419 if (!of_property_read_u32(of_node, field[i], val + i))
425 if (matches < numfields)
426 newval = ksz9031_extended_read(phydev, OP_DATA, 2, reg);
430 maxval = (field_sz == 4) ? 0xf : 0x1f;
431 for (i = 0; i < numfields; i++)
432 if (val[i] != -(i + 1)) {
434 mask ^= maxval << (field_sz * i);
435 newval = (newval & mask) |
436 (((val[i] / KSZ9031_PS_TO_REG) & maxval)
440 return ksz9031_extended_write(phydev, OP_DATA, 2, reg, newval);
443 static int ksz9031_center_flp_timing(struct phy_device *phydev)
447 /* Center KSZ9031RNX FLP timing at 16ms. */
448 result = ksz9031_extended_write(phydev, OP_DATA, 0,
449 MII_KSZ9031RN_FLP_BURST_TX_HI, 0x0006);
450 result = ksz9031_extended_write(phydev, OP_DATA, 0,
451 MII_KSZ9031RN_FLP_BURST_TX_LO, 0x1A80);
456 return genphy_restart_aneg(phydev);
459 static int ksz9031_config_init(struct phy_device *phydev)
461 const struct device *dev = &phydev->dev;
462 const struct device_node *of_node = dev->of_node;
463 static const char *clk_skews[2] = {"rxc-skew-ps", "txc-skew-ps"};
464 static const char *rx_data_skews[4] = {
465 "rxd0-skew-ps", "rxd1-skew-ps",
466 "rxd2-skew-ps", "rxd3-skew-ps"
468 static const char *tx_data_skews[4] = {
469 "txd0-skew-ps", "txd1-skew-ps",
470 "txd2-skew-ps", "txd3-skew-ps"
472 static const char *control_skews[2] = {"txen-skew-ps", "rxdv-skew-ps"};
474 if (!of_node && dev->parent->of_node)
475 of_node = dev->parent->of_node;
478 ksz9031_of_load_skew_values(phydev, of_node,
479 MII_KSZ9031RN_CLK_PAD_SKEW, 5,
482 ksz9031_of_load_skew_values(phydev, of_node,
483 MII_KSZ9031RN_CONTROL_PAD_SKEW, 4,
486 ksz9031_of_load_skew_values(phydev, of_node,
487 MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4,
490 ksz9031_of_load_skew_values(phydev, of_node,
491 MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4,
495 return ksz9031_center_flp_timing(phydev);
498 #define KSZ8873MLL_GLOBAL_CONTROL_4 0x06
499 #define KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX BIT(6)
500 #define KSZ8873MLL_GLOBAL_CONTROL_4_SPEED BIT(4)
501 static int ksz8873mll_read_status(struct phy_device *phydev)
506 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
508 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
510 if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX)
511 phydev->duplex = DUPLEX_HALF;
513 phydev->duplex = DUPLEX_FULL;
515 if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_SPEED)
516 phydev->speed = SPEED_10;
518 phydev->speed = SPEED_100;
521 phydev->pause = phydev->asym_pause = 0;
526 static int ksz9031_read_status(struct phy_device *phydev)
531 err = genphy_read_status(phydev);
535 /* Make sure the PHY is not broken. Read idle error count,
536 * and reset the PHY if it is maxed out.
538 regval = phy_read(phydev, MII_STAT1000);
539 if ((regval & 0xFF) == 0xFF) {
547 static int ksz8873mll_config_aneg(struct phy_device *phydev)
552 /* This routine returns -1 as an indication to the caller that the
553 * Micrel ksz9021 10/100/1000 PHY does not support standard IEEE
554 * MMD extended PHY registers.
557 ksz9021_rd_mmd_phyreg(struct phy_device *phydev, int ptrad, int devnum,
563 /* This routine does nothing since the Micrel ksz9021 does not support
564 * standard IEEE MMD extended PHY registers.
567 ksz9021_wr_mmd_phyreg(struct phy_device *phydev, int ptrad, int devnum,
572 static int kszphy_probe(struct phy_device *phydev)
574 const struct kszphy_type *type = phydev->drv->driver_data;
575 const struct device_node *np = phydev->dev.of_node;
576 struct kszphy_priv *priv;
580 priv = devm_kzalloc(&phydev->dev, sizeof(*priv), GFP_KERNEL);
588 if (type->led_mode_reg) {
589 ret = of_property_read_u32(np, "micrel,led-mode",
594 if (priv->led_mode > 3) {
595 dev_err(&phydev->dev, "invalid led mode: 0x%02x\n",
603 clk = devm_clk_get(&phydev->dev, "rmii-ref");
604 /* NOTE: clk may be NULL if building without CONFIG_HAVE_CLK */
605 if (!IS_ERR_OR_NULL(clk)) {
606 unsigned long rate = clk_get_rate(clk);
607 bool rmii_ref_clk_sel_25_mhz;
609 priv->rmii_ref_clk_sel = type->has_rmii_ref_clk_sel;
610 rmii_ref_clk_sel_25_mhz = of_property_read_bool(np,
611 "micrel,rmii-reference-clock-select-25-mhz");
613 if (rate > 24500000 && rate < 25500000) {
614 priv->rmii_ref_clk_sel_val = rmii_ref_clk_sel_25_mhz;
615 } else if (rate > 49500000 && rate < 50500000) {
616 priv->rmii_ref_clk_sel_val = !rmii_ref_clk_sel_25_mhz;
618 dev_err(&phydev->dev, "Clock rate out of range: %ld\n", rate);
623 /* Support legacy board-file configuration */
624 if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK) {
625 priv->rmii_ref_clk_sel = true;
626 priv->rmii_ref_clk_sel_val = true;
632 static struct phy_driver ksphy_driver[] = {
634 .phy_id = PHY_ID_KS8737,
635 .phy_id_mask = 0x00fffff0,
636 .name = "Micrel KS8737",
637 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
638 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
639 .driver_data = &ks8737_type,
640 .config_init = kszphy_config_init,
641 .config_aneg = genphy_config_aneg,
642 .read_status = genphy_read_status,
643 .ack_interrupt = kszphy_ack_interrupt,
644 .config_intr = kszphy_config_intr,
645 .suspend = genphy_suspend,
646 .resume = genphy_resume,
647 .driver = { .owner = THIS_MODULE,},
649 .phy_id = PHY_ID_KSZ8021,
650 .phy_id_mask = 0x00ffffff,
651 .name = "Micrel KSZ8021 or KSZ8031",
652 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause |
653 SUPPORTED_Asym_Pause),
654 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
655 .driver_data = &ksz8021_type,
656 .probe = kszphy_probe,
657 .config_init = kszphy_config_init,
658 .config_aneg = genphy_config_aneg,
659 .read_status = genphy_read_status,
660 .ack_interrupt = kszphy_ack_interrupt,
661 .config_intr = kszphy_config_intr,
662 .suspend = genphy_suspend,
663 .resume = genphy_resume,
664 .driver = { .owner = THIS_MODULE,},
666 .phy_id = PHY_ID_KSZ8031,
667 .phy_id_mask = 0x00ffffff,
668 .name = "Micrel KSZ8031",
669 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause |
670 SUPPORTED_Asym_Pause),
671 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
672 .driver_data = &ksz8021_type,
673 .probe = kszphy_probe,
674 .config_init = kszphy_config_init,
675 .config_aneg = genphy_config_aneg,
676 .read_status = genphy_read_status,
677 .ack_interrupt = kszphy_ack_interrupt,
678 .config_intr = kszphy_config_intr,
679 .suspend = genphy_suspend,
680 .resume = genphy_resume,
681 .driver = { .owner = THIS_MODULE,},
683 .phy_id = PHY_ID_KSZ8041,
684 .phy_id_mask = 0x00fffff0,
685 .name = "Micrel KSZ8041",
686 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause
687 | SUPPORTED_Asym_Pause),
688 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
689 .driver_data = &ksz8041_type,
690 .probe = kszphy_probe,
691 .config_init = kszphy_config_init,
692 .config_aneg = genphy_config_aneg,
693 .read_status = genphy_read_status,
694 .ack_interrupt = kszphy_ack_interrupt,
695 .config_intr = kszphy_config_intr,
696 .suspend = genphy_suspend,
697 .resume = genphy_resume,
698 .driver = { .owner = THIS_MODULE,},
700 .phy_id = PHY_ID_KSZ8041RNLI,
701 .phy_id_mask = 0x00fffff0,
702 .name = "Micrel KSZ8041RNLI",
703 .features = PHY_BASIC_FEATURES |
704 SUPPORTED_Pause | SUPPORTED_Asym_Pause,
705 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
706 .driver_data = &ksz8041_type,
707 .probe = kszphy_probe,
708 .config_init = kszphy_config_init,
709 .config_aneg = genphy_config_aneg,
710 .read_status = genphy_read_status,
711 .ack_interrupt = kszphy_ack_interrupt,
712 .config_intr = kszphy_config_intr,
713 .suspend = genphy_suspend,
714 .resume = genphy_resume,
715 .driver = { .owner = THIS_MODULE,},
717 .phy_id = PHY_ID_KSZ8051,
718 .phy_id_mask = 0x00fffff0,
719 .name = "Micrel KSZ8051",
720 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause
721 | SUPPORTED_Asym_Pause),
722 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
723 .driver_data = &ksz8051_type,
724 .probe = kszphy_probe,
725 .config_init = kszphy_config_init,
726 .config_aneg = genphy_config_aneg,
727 .read_status = genphy_read_status,
728 .ack_interrupt = kszphy_ack_interrupt,
729 .config_intr = kszphy_config_intr,
730 .suspend = genphy_suspend,
731 .resume = genphy_resume,
732 .driver = { .owner = THIS_MODULE,},
734 .phy_id = PHY_ID_KSZ8001,
735 .name = "Micrel KSZ8001 or KS8721",
736 .phy_id_mask = 0x00ffffff,
737 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
738 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
739 .driver_data = &ksz8041_type,
740 .probe = kszphy_probe,
741 .config_init = kszphy_config_init,
742 .config_aneg = genphy_config_aneg,
743 .read_status = genphy_read_status,
744 .ack_interrupt = kszphy_ack_interrupt,
745 .config_intr = kszphy_config_intr,
746 .suspend = genphy_suspend,
747 .resume = genphy_resume,
748 .driver = { .owner = THIS_MODULE,},
750 .phy_id = PHY_ID_KSZ8081,
751 .name = "Micrel KSZ8081 or KSZ8091",
752 .phy_id_mask = 0x00fffff0,
753 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
754 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
755 .driver_data = &ksz8081_type,
756 .probe = kszphy_probe,
757 .config_init = kszphy_config_init,
758 .config_aneg = genphy_config_aneg,
759 .read_status = genphy_read_status,
760 .ack_interrupt = kszphy_ack_interrupt,
761 .config_intr = kszphy_config_intr,
762 .suspend = genphy_suspend,
763 .resume = genphy_resume,
764 .driver = { .owner = THIS_MODULE,},
766 .phy_id = PHY_ID_KSZ8061,
767 .name = "Micrel KSZ8061",
768 .phy_id_mask = 0x00fffff0,
769 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
770 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
771 .config_init = kszphy_config_init,
772 .config_aneg = genphy_config_aneg,
773 .read_status = genphy_read_status,
774 .ack_interrupt = kszphy_ack_interrupt,
775 .config_intr = kszphy_config_intr,
776 .suspend = genphy_suspend,
777 .resume = genphy_resume,
778 .driver = { .owner = THIS_MODULE,},
780 .phy_id = PHY_ID_KSZ9021,
781 .phy_id_mask = 0x000ffffe,
782 .name = "Micrel KSZ9021 Gigabit PHY",
783 .features = (PHY_GBIT_FEATURES | SUPPORTED_Pause),
784 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
785 .driver_data = &ksz9021_type,
786 .config_init = ksz9021_config_init,
787 .config_aneg = genphy_config_aneg,
788 .read_status = genphy_read_status,
789 .ack_interrupt = kszphy_ack_interrupt,
790 .config_intr = kszphy_config_intr,
791 .suspend = genphy_suspend,
792 .resume = genphy_resume,
793 .read_mmd_indirect = ksz9021_rd_mmd_phyreg,
794 .write_mmd_indirect = ksz9021_wr_mmd_phyreg,
795 .driver = { .owner = THIS_MODULE, },
797 .phy_id = PHY_ID_KSZ9031,
798 .phy_id_mask = 0x00fffff0,
799 .name = "Micrel KSZ9031 Gigabit PHY",
800 .features = (PHY_GBIT_FEATURES | SUPPORTED_Pause),
801 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
802 .driver_data = &ksz9021_type,
803 .config_init = ksz9031_config_init,
804 .config_aneg = genphy_config_aneg,
805 .read_status = ksz9031_read_status,
806 .ack_interrupt = kszphy_ack_interrupt,
807 .config_intr = kszphy_config_intr,
808 .suspend = genphy_suspend,
809 .resume = genphy_resume,
810 .driver = { .owner = THIS_MODULE, },
812 .phy_id = PHY_ID_KSZ8873MLL,
813 .phy_id_mask = 0x00fffff0,
814 .name = "Micrel KSZ8873MLL Switch",
815 .features = (SUPPORTED_Pause | SUPPORTED_Asym_Pause),
816 .flags = PHY_HAS_MAGICANEG,
817 .config_init = kszphy_config_init,
818 .config_aneg = ksz8873mll_config_aneg,
819 .read_status = ksz8873mll_read_status,
820 .suspend = genphy_suspend,
821 .resume = genphy_resume,
822 .driver = { .owner = THIS_MODULE, },
824 .phy_id = PHY_ID_KSZ886X,
825 .phy_id_mask = 0x00fffff0,
826 .name = "Micrel KSZ886X Switch",
827 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
828 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
829 .config_init = kszphy_config_init,
830 .config_aneg = genphy_config_aneg,
831 .read_status = genphy_read_status,
832 .suspend = genphy_suspend,
833 .resume = genphy_resume,
834 .driver = { .owner = THIS_MODULE, },
837 module_phy_driver(ksphy_driver);
839 MODULE_DESCRIPTION("Micrel PHY driver");
840 MODULE_AUTHOR("David J. Choi");
841 MODULE_LICENSE("GPL");
843 static struct mdio_device_id __maybe_unused micrel_tbl[] = {
844 { PHY_ID_KSZ9021, 0x000ffffe },
845 { PHY_ID_KSZ9031, 0x00fffff0 },
846 { PHY_ID_KSZ8001, 0x00ffffff },
847 { PHY_ID_KS8737, 0x00fffff0 },
848 { PHY_ID_KSZ8021, 0x00ffffff },
849 { PHY_ID_KSZ8031, 0x00ffffff },
850 { PHY_ID_KSZ8041, 0x00fffff0 },
851 { PHY_ID_KSZ8051, 0x00fffff0 },
852 { PHY_ID_KSZ8061, 0x00fffff0 },
853 { PHY_ID_KSZ8081, 0x00fffff0 },
854 { PHY_ID_KSZ8873MLL, 0x00fffff0 },
855 { PHY_ID_KSZ886X, 0x00fffff0 },
859 MODULE_DEVICE_TABLE(mdio, micrel_tbl);