drivers/net/qla3xxx.c

   1 /*
   2  * QLogic QLA3xxx NIC HBA Driver
   3  * Copyright (c)  2003-2006 QLogic Corporation
   4  *
   5  * See LICENSE.qla3xxx for copyright and licensing details.
   6  */
   7
   8 #include <linux/kernel.h>
   9 #include <linux/init.h>
  10 #include <linux/types.h>
  11 #include <linux/module.h>
  12 #include <linux/list.h>
  13 #include <linux/pci.h>
  14 #include <linux/dma-mapping.h>
  15 #include <linux/sched.h>
  16 #include <linux/slab.h>
  17 #include <linux/dmapool.h>
  18 #include <linux/mempool.h>
  19 #include <linux/spinlock.h>
  20 #include <linux/kthread.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/errno.h>
  23 #include <linux/ioport.h>
  24 #include <linux/ip.h>
  25 #include <linux/in.h>
  26 #include <linux/if_arp.h>
  27 #include <linux/if_ether.h>
  28 #include <linux/netdevice.h>
  29 #include <linux/etherdevice.h>
  30 #include <linux/ethtool.h>
  31 #include <linux/skbuff.h>
  32 #include <linux/rtnetlink.h>
  33 #include <linux/if_vlan.h>
  34 #include <linux/init.h>
  35 #include <linux/delay.h>
  36 #include <linux/mm.h>
  37
  38 #include "qla3xxx.h"
  39
  40 #define DRV_NAME        "qla3xxx"
  41 #define DRV_STRING      "QLogic ISP3XXX Network Driver"
  42 #define DRV_VERSION     "v2.02.00-k36"
  43 #define PFX             DRV_NAME " "
  44
  45 static const char ql3xxx_driver_name[] = DRV_NAME;
  46 static const char ql3xxx_driver_version[] = DRV_VERSION;
  47
  48 MODULE_AUTHOR("QLogic Corporation");
  49 MODULE_DESCRIPTION("QLogic ISP3XXX Network Driver " DRV_VERSION " ");
  50 MODULE_LICENSE("GPL");
  51 MODULE_VERSION(DRV_VERSION);
  52
  53 static const u32 default_msg
  54     = NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
  55     | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
  56
  57 static int debug = -1;          /* defaults above */
  58 module_param(debug, int, 0);
  59 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
  60
  61 static int msi;
  62 module_param(msi, int, 0);
  63 MODULE_PARM_DESC(msi, "Turn on Message Signaled Interrupts.");
  64
  65 static struct pci_device_id ql3xxx_pci_tbl[] __devinitdata = {
  66         {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QL3022_DEVICE_ID)},
  67         {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QL3032_DEVICE_ID)},
  68         /* required last entry */
  69         {0,}
  70 };
  71
  72 MODULE_DEVICE_TABLE(pci, ql3xxx_pci_tbl);
  73
  74 /*
  75  * Caller must take hw_lock.
  76  */
  77 static int ql_sem_spinlock(struct ql3_adapter *qdev,
  78                             u32 sem_mask, u32 sem_bits)
  79 {
  80         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
  81         u32 value;
  82         unsigned int seconds = 3;
  83
  84         do {
  85                 writel((sem_mask | sem_bits),
  86                        &port_regs->CommonRegs.semaphoreReg);
  87                 value = readl(&port_regs->CommonRegs.semaphoreReg);
  88                 if ((value & (sem_mask >> 16)) == sem_bits)
  89                         return 0;
  90                 ssleep(1);
  91         } while(--seconds);
  92         return -1;
  93 }
  94
  95 static void ql_sem_unlock(struct ql3_adapter *qdev, u32 sem_mask)
  96 {
  97         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
  98         writel(sem_mask, &port_regs->CommonRegs.semaphoreReg);
  99         readl(&port_regs->CommonRegs.semaphoreReg);
 100 }
 101
 102 static int ql_sem_lock(struct ql3_adapter *qdev, u32 sem_mask, u32 sem_bits)
 103 {
 104         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
 105         u32 value;
 106
 107         writel((sem_mask | sem_bits), &port_regs->CommonRegs.semaphoreReg);
 108         value = readl(&port_regs->CommonRegs.semaphoreReg);
 109         return ((value & (sem_mask >> 16)) == sem_bits);
 110 }
 111
 112 /*
 113  * Caller holds hw_lock.
 114  */
 115 static int ql_wait_for_drvr_lock(struct ql3_adapter *qdev)
 116 {
 117         int i = 0;
 118
 119         while (1) {
 120                 if (!ql_sem_lock(qdev,
 121                                  QL_DRVR_SEM_MASK,
 122                                  (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index)
 123                                   * 2) << 1)) {
 124                         if (i < 10) {
 125                                 ssleep(1);
 126                                 i++;
 127                         } else {
 128                                 printk(KERN_ERR PFX "%s: Timed out waiting for "
 129                                        "driver lock...\n",
 130                                        qdev->ndev->name);
 131                                 return 0;
 132                         }
 133                 } else {
 134                         printk(KERN_DEBUG PFX
 135                                "%s: driver lock acquired.\n",
 136                                qdev->ndev->name);
 137                         return 1;
 138                 }
 139         }
 140 }
 141
 142 static void ql_set_register_page(struct ql3_adapter *qdev, u32 page)
 143 {
 144         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
 145
 146         writel(((ISP_CONTROL_NP_MASK << 16) | page),
 147                         &port_regs->CommonRegs.ispControlStatus);
 148         readl(&port_regs->CommonRegs.ispControlStatus);
 149         qdev->current_page = page;
 150 }
 151
 152 static u32 ql_read_common_reg_l(struct ql3_adapter *qdev,
 153                               u32 __iomem * reg)
 154 {
 155         u32 value;
 156         unsigned long hw_flags;
 157
 158         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
 159         value = readl(reg);
 160         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
 161
 162         return value;
 163 }
 164
 165 static u32 ql_read_common_reg(struct ql3_adapter *qdev,
 166                               u32 __iomem * reg)
 167 {
 168         return readl(reg);
 169 }
 170
 171 static u32 ql_read_page0_reg_l(struct ql3_adapter *qdev, u32 __iomem *reg)
 172 {
 173         u32 value;
 174         unsigned long hw_flags;
 175
 176         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
 177
 178         if (qdev->current_page != 0)
 179                 ql_set_register_page(qdev,0);
 180         value = readl(reg);
 181
 182         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
 183         return value;
 184 }
 185
 186 static u32 ql_read_page0_reg(struct ql3_adapter *qdev, u32 __iomem *reg)
 187 {
 188         if (qdev->current_page != 0)
 189                 ql_set_register_page(qdev,0);
 190         return readl(reg);
 191 }
 192
 193 static void ql_write_common_reg_l(struct ql3_adapter *qdev,
 194                                 u32 __iomem *reg, u32 value)
 195 {
 196         unsigned long hw_flags;
 197
 198         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
 199         writel(value, reg);
 200         readl(reg);
 201         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
 202         return;
 203 }
 204
 205 static void ql_write_common_reg(struct ql3_adapter *qdev,
 206                                 u32 __iomem *reg, u32 value)
 207 {
 208         writel(value, reg);
 209         readl(reg);
 210         return;
 211 }
 212
 213 static void ql_write_nvram_reg(struct ql3_adapter *qdev,
 214                                 u32 __iomem *reg, u32 value)
 215 {
 216         writel(value, reg);
 217         readl(reg);
 218         udelay(1);
 219         return;
 220 }
 221
 222 static void ql_write_page0_reg(struct ql3_adapter *qdev,
 223                                u32 __iomem *reg, u32 value)
 224 {
 225         if (qdev->current_page != 0)
 226                 ql_set_register_page(qdev,0);
 227         writel(value, reg);
 228         readl(reg);
 229         return;
 230 }
 231
 232 /*
 233  * Caller holds hw_lock. Only called during init.
 234  */
 235 static void ql_write_page1_reg(struct ql3_adapter *qdev,
 236                                u32 __iomem *reg, u32 value)
 237 {
 238         if (qdev->current_page != 1)
 239                 ql_set_register_page(qdev,1);
 240         writel(value, reg);
 241         readl(reg);
 242         return;
 243 }
 244
 245 /*
 246  * Caller holds hw_lock. Only called during init.
 247  */
 248 static void ql_write_page2_reg(struct ql3_adapter *qdev,
 249                                u32 __iomem *reg, u32 value)
 250 {
 251         if (qdev->current_page != 2)
 252                 ql_set_register_page(qdev,2);
 253         writel(value, reg);
 254         readl(reg);
 255         return;
 256 }
 257
 258 static void ql_disable_interrupts(struct ql3_adapter *qdev)
 259 {
 260         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
 261
 262         ql_write_common_reg_l(qdev, &port_regs->CommonRegs.ispInterruptMaskReg,
 263                             (ISP_IMR_ENABLE_INT << 16));
 264
 265 }
 266
 267 static void ql_enable_interrupts(struct ql3_adapter *qdev)
 268 {
 269         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
 270
 271         ql_write_common_reg_l(qdev, &port_regs->CommonRegs.ispInterruptMaskReg,
 272                             ((0xff << 16) | ISP_IMR_ENABLE_INT));
 273
 274 }
 275
 276 static void ql_release_to_lrg_buf_free_list(struct ql3_adapter *qdev,
 277                                             struct ql_rcv_buf_cb *lrg_buf_cb)
 278 {
 279         u64 map;
 280         lrg_buf_cb->next = NULL;
 281
 282         if (qdev->lrg_buf_free_tail == NULL) {  /* The list is empty  */
 283                 qdev->lrg_buf_free_head = qdev->lrg_buf_free_tail = lrg_buf_cb;
 284         } else {
 285                 qdev->lrg_buf_free_tail->next = lrg_buf_cb;
 286                 qdev->lrg_buf_free_tail = lrg_buf_cb;
 287         }
 288
 289         if (!lrg_buf_cb->skb) {
 290                 lrg_buf_cb->skb = netdev_alloc_skb(qdev->ndev,
 291                                                    qdev->lrg_buffer_len);
 292                 if (unlikely(!lrg_buf_cb->skb)) {
 293                         printk(KERN_ERR PFX "%s: failed netdev_alloc_skb().\n",
 294                                qdev->ndev->name);
 295                         qdev->lrg_buf_skb_check++;
 296                 } else {
 297                         /*
 298                          * We save some space to copy the ethhdr from first
 299                          * buffer
 300                          */
 301                         skb_reserve(lrg_buf_cb->skb, QL_HEADER_SPACE);
 302                         map = pci_map_single(qdev->pdev,
 303                                              lrg_buf_cb->skb->data,
 304                                              qdev->lrg_buffer_len -
 305                                              QL_HEADER_SPACE,
 306                                              PCI_DMA_FROMDEVICE);
 307                         lrg_buf_cb->buf_phy_addr_low =
 308                             cpu_to_le32(LS_64BITS(map));
 309                         lrg_buf_cb->buf_phy_addr_high =
 310                             cpu_to_le32(MS_64BITS(map));
 311                         pci_unmap_addr_set(lrg_buf_cb, mapaddr, map);
 312                         pci_unmap_len_set(lrg_buf_cb, maplen,
 313                                           qdev->lrg_buffer_len -
 314                                           QL_HEADER_SPACE);
 315                 }
 316         }
 317
 318         qdev->lrg_buf_free_count++;
 319 }
 320
 321 static struct ql_rcv_buf_cb *ql_get_from_lrg_buf_free_list(struct ql3_adapter
 322                                                            *qdev)
 323 {
 324         struct ql_rcv_buf_cb *lrg_buf_cb;
 325
 326         if ((lrg_buf_cb = qdev->lrg_buf_free_head) != NULL) {
 327                 if ((qdev->lrg_buf_free_head = lrg_buf_cb->next) == NULL)
 328                         qdev->lrg_buf_free_tail = NULL;
 329                 qdev->lrg_buf_free_count--;
 330         }
 331
 332         return lrg_buf_cb;
 333 }
 334
 335 static u32 addrBits = EEPROM_NO_ADDR_BITS;
 336 static u32 dataBits = EEPROM_NO_DATA_BITS;
 337
 338 static void fm93c56a_deselect(struct ql3_adapter *qdev);
 339 static void eeprom_readword(struct ql3_adapter *qdev, u32 eepromAddr,
 340                             unsigned short *value);
 341
 342 /*
 343  * Caller holds hw_lock.
 344  */
 345 static void fm93c56a_select(struct ql3_adapter *qdev)
 346 {
 347         struct ql3xxx_port_registers __iomem *port_regs =
 348                         qdev->mem_map_registers;
 349
 350         qdev->eeprom_cmd_data = AUBURN_EEPROM_CS_1;
 351         ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
 352                             ISP_NVRAM_MASK | qdev->eeprom_cmd_data);
 353         ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
 354                             ((ISP_NVRAM_MASK << 16) | qdev->eeprom_cmd_data));
 355 }
 356
 357 /*
 358  * Caller holds hw_lock.
 359  */
 360 static void fm93c56a_cmd(struct ql3_adapter *qdev, u32 cmd, u32 eepromAddr)
 361 {
 362         int i;
 363         u32 mask;
 364         u32 dataBit;
 365         u32 previousBit;
 366         struct ql3xxx_port_registers __iomem *port_regs =
 367                         qdev->mem_map_registers;
 368
 369         /* Clock in a zero, then do the start bit */
 370         ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
 371                             ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
 372                             AUBURN_EEPROM_DO_1);
 373         ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
 374                             ISP_NVRAM_MASK | qdev->
 375                             eeprom_cmd_data | AUBURN_EEPROM_DO_1 |
 376                             AUBURN_EEPROM_CLK_RISE);
 377         ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
 378                             ISP_NVRAM_MASK | qdev->
 379                             eeprom_cmd_data | AUBURN_EEPROM_DO_1 |
 380                             AUBURN_EEPROM_CLK_FALL);
 381
 382         mask = 1 << (FM93C56A_CMD_BITS - 1);
 383         /* Force the previous data bit to be different */
 384         previousBit = 0xffff;
 385         for (i = 0; i < FM93C56A_CMD_BITS; i++) {
 386                 dataBit =
 387                     (cmd & mask) ? AUBURN_EEPROM_DO_1 : AUBURN_EEPROM_DO_0;
 388                 if (previousBit != dataBit) {
 389                         /*
 390                          * If the bit changed, then change the DO state to
 391                          * match
 392                          */
 393                         ql_write_nvram_reg(qdev,
 394                                             &port_regs->CommonRegs.
 395                                             serialPortInterfaceReg,
 396                                             ISP_NVRAM_MASK | qdev->
 397                                             eeprom_cmd_data | dataBit);
 398                         previousBit = dataBit;
 399                 }
 400                 ql_write_nvram_reg(qdev,
 401                                     &port_regs->CommonRegs.
 402                                     serialPortInterfaceReg,
 403                                     ISP_NVRAM_MASK | qdev->
 404                                     eeprom_cmd_data | dataBit |
 405                                     AUBURN_EEPROM_CLK_RISE);
 406                 ql_write_nvram_reg(qdev,
 407                                     &port_regs->CommonRegs.
 408                                     serialPortInterfaceReg,
 409                                     ISP_NVRAM_MASK | qdev->
 410                                     eeprom_cmd_data | dataBit |
 411                                     AUBURN_EEPROM_CLK_FALL);
 412                 cmd = cmd << 1;
 413         }
 414
 415         mask = 1 << (addrBits - 1);
 416         /* Force the previous data bit to be different */
 417         previousBit = 0xffff;
 418         for (i = 0; i < addrBits; i++) {
 419                 dataBit =
 420                     (eepromAddr & mask) ? AUBURN_EEPROM_DO_1 :
 421                     AUBURN_EEPROM_DO_0;
 422                 if (previousBit != dataBit) {
 423                         /*
 424                          * If the bit changed, then change the DO state to
 425                          * match
 426                          */
 427                         ql_write_nvram_reg(qdev,
 428                                             &port_regs->CommonRegs.
 429                                             serialPortInterfaceReg,
 430                                             ISP_NVRAM_MASK | qdev->
 431                                             eeprom_cmd_data | dataBit);
 432                         previousBit = dataBit;
 433                 }
 434                 ql_write_nvram_reg(qdev,
 435                                     &port_regs->CommonRegs.
 436                                     serialPortInterfaceReg,
 437                                     ISP_NVRAM_MASK | qdev->
 438                                     eeprom_cmd_data | dataBit |
 439                                     AUBURN_EEPROM_CLK_RISE);
 440                 ql_write_nvram_reg(qdev,
 441                                     &port_regs->CommonRegs.
 442                                     serialPortInterfaceReg,
 443                                     ISP_NVRAM_MASK | qdev->
 444                                     eeprom_cmd_data | dataBit |
 445                                     AUBURN_EEPROM_CLK_FALL);
 446                 eepromAddr = eepromAddr << 1;
 447         }
 448 }
 449
 450 /*
 451  * Caller holds hw_lock.
 452  */
 453 static void fm93c56a_deselect(struct ql3_adapter *qdev)
 454 {
 455         struct ql3xxx_port_registers __iomem *port_regs =
 456                         qdev->mem_map_registers;
 457         qdev->eeprom_cmd_data = AUBURN_EEPROM_CS_0;
 458         ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
 459                             ISP_NVRAM_MASK | qdev->eeprom_cmd_data);
 460 }
 461
 462 /*
 463  * Caller holds hw_lock.
 464  */
 465 static void fm93c56a_datain(struct ql3_adapter *qdev, unsigned short *value)
 466 {
 467         int i;
 468         u32 data = 0;
 469         u32 dataBit;
 470         struct ql3xxx_port_registers __iomem *port_regs =
 471                         qdev->mem_map_registers;
 472
 473         /* Read the data bits */
 474         /* The first bit is a dummy.  Clock right over it. */
 475         for (i = 0; i < dataBits; i++) {
 476                 ql_write_nvram_reg(qdev,
 477                                     &port_regs->CommonRegs.
 478                                     serialPortInterfaceReg,
 479                                     ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
 480                                     AUBURN_EEPROM_CLK_RISE);
 481                 ql_write_nvram_reg(qdev,
 482                                     &port_regs->CommonRegs.
 483                                     serialPortInterfaceReg,
 484                                     ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
 485                                     AUBURN_EEPROM_CLK_FALL);
 486                 dataBit =
 487                     (ql_read_common_reg
 488                      (qdev,
 489                       &port_regs->CommonRegs.
 490                       serialPortInterfaceReg) & AUBURN_EEPROM_DI_1) ? 1 : 0;
 491                 data = (data << 1) | dataBit;
 492         }
 493         *value = (u16) data;
 494 }
 495
 496 /*
 497  * Caller holds hw_lock.
 498  */
 499 static void eeprom_readword(struct ql3_adapter *qdev,
 500                             u32 eepromAddr, unsigned short *value)
 501 {
 502         fm93c56a_select(qdev);
 503         fm93c56a_cmd(qdev, (int)FM93C56A_READ, eepromAddr);
 504         fm93c56a_datain(qdev, value);
 505         fm93c56a_deselect(qdev);
 506 }
 507
 508 static void ql_swap_mac_addr(u8 * macAddress)
 509 {
 510 #ifdef __BIG_ENDIAN
 511         u8 temp;
 512         temp = macAddress[0];
 513         macAddress[0] = macAddress[1];
 514         macAddress[1] = temp;
 515         temp = macAddress[2];
 516         macAddress[2] = macAddress[3];
 517         macAddress[3] = temp;
 518         temp = macAddress[4];
 519         macAddress[4] = macAddress[5];
 520         macAddress[5] = temp;
 521 #endif
 522 }
 523
 524 static int ql_get_nvram_params(struct ql3_adapter *qdev)
 525 {
 526         u16 *pEEPROMData;
 527         u16 checksum = 0;
 528         u32 index;
 529         unsigned long hw_flags;
 530
 531         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
 532
 533         pEEPROMData = (u16 *) & qdev->nvram_data;
 534         qdev->eeprom_cmd_data = 0;
 535         if(ql_sem_spinlock(qdev, QL_NVRAM_SEM_MASK,
 536                         (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
 537                          2) << 10)) {
 538                 printk(KERN_ERR PFX"%s: Failed ql_sem_spinlock().\n",
 539                         __func__);
 540                 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
 541                 return -1;
 542         }
 543
 544         for (index = 0; index < EEPROM_SIZE; index++) {
 545                 eeprom_readword(qdev, index, pEEPROMData);
 546                 checksum += *pEEPROMData;
 547                 pEEPROMData++;
 548         }
 549         ql_sem_unlock(qdev, QL_NVRAM_SEM_MASK);
 550
 551         if (checksum != 0) {
 552                 printk(KERN_ERR PFX "%s: checksum should be zero, is %x!!\n",
 553                        qdev->ndev->name, checksum);
 554                 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
 555                 return -1;
 556         }
 557
 558         /*
 559          * We have a problem with endianness for the MAC addresses
 560          * and the two 8-bit values version, and numPorts.  We
 561          * have to swap them on big endian systems.
 562          */
 563         ql_swap_mac_addr(qdev->nvram_data.funcCfg_fn0.macAddress);
 564         ql_swap_mac_addr(qdev->nvram_data.funcCfg_fn1.macAddress);
 565         ql_swap_mac_addr(qdev->nvram_data.funcCfg_fn2.macAddress);
 566         ql_swap_mac_addr(qdev->nvram_data.funcCfg_fn3.macAddress);
 567         pEEPROMData = (u16 *) & qdev->nvram_data.version;
 568         *pEEPROMData = le16_to_cpu(*pEEPROMData);
 569
 570         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
 571         return checksum;
 572 }
 573
 574 static const u32 PHYAddr[2] = {
 575         PORT0_PHY_ADDRESS, PORT1_PHY_ADDRESS
 576 };
 577
 578 static int ql_wait_for_mii_ready(struct ql3_adapter *qdev)
 579 {
 580         struct ql3xxx_port_registers __iomem *port_regs =
 581                         qdev->mem_map_registers;
 582         u32 temp;
 583         int count = 1000;
 584
 585         while (count) {
 586                 temp = ql_read_page0_reg(qdev, &port_regs->macMIIStatusReg);
 587                 if (!(temp & MAC_MII_STATUS_BSY))
 588                         return 0;
 589                 udelay(10);
 590                 count--;
 591         }
 592         return -1;
 593 }
 594
 595 static void ql_mii_enable_scan_mode(struct ql3_adapter *qdev)
 596 {
 597         struct ql3xxx_port_registers __iomem *port_regs =
 598                         qdev->mem_map_registers;
 599         u32 scanControl;
 600
 601         if (qdev->numPorts > 1) {
 602                 /* Auto scan will cycle through multiple ports */
 603                 scanControl = MAC_MII_CONTROL_AS | MAC_MII_CONTROL_SC;
 604         } else {
 605                 scanControl = MAC_MII_CONTROL_SC;
 606         }
 607
 608         /*
 609          * Scan register 1 of PHY/PETBI,
 610          * Set up to scan both devices
 611          * The autoscan starts from the first register, completes
 612          * the last one before rolling over to the first
 613          */
 614         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
 615                            PHYAddr[0] | MII_SCAN_REGISTER);
 616
 617         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
 618                            (scanControl) |
 619                            ((MAC_MII_CONTROL_SC | MAC_MII_CONTROL_AS) << 16));
 620 }
 621
 622 static u8 ql_mii_disable_scan_mode(struct ql3_adapter *qdev)
 623 {
 624         u8 ret;
 625         struct ql3xxx_port_registers __iomem *port_regs =
 626                                         qdev->mem_map_registers;
 627
 628         /* See if scan mode is enabled before we turn it off */
 629         if (ql_read_page0_reg(qdev, &port_regs->macMIIMgmtControlReg) &
 630             (MAC_MII_CONTROL_AS | MAC_MII_CONTROL_SC)) {
 631                 /* Scan is enabled */
 632                 ret = 1;
 633         } else {
 634                 /* Scan is disabled */
 635                 ret = 0;
 636         }
 637
 638         /*
 639          * When disabling scan mode you must first change the MII register
 640          * address
 641          */
 642         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
 643                            PHYAddr[0] | MII_SCAN_REGISTER);
 644
 645         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
 646                            ((MAC_MII_CONTROL_SC | MAC_MII_CONTROL_AS |
 647                              MAC_MII_CONTROL_RC) << 16));
 648
 649         return ret;
 650 }
 651
 652 static int ql_mii_write_reg_ex(struct ql3_adapter *qdev,
 653                                u16 regAddr, u16 value, u32 mac_index)
 654 {
 655         struct ql3xxx_port_registers __iomem *port_regs =
 656                         qdev->mem_map_registers;
 657         u8 scanWasEnabled;
 658
 659         scanWasEnabled = ql_mii_disable_scan_mode(qdev);
 660
 661         if (ql_wait_for_mii_ready(qdev)) {
 662                 if (netif_msg_link(qdev))
 663                         printk(KERN_WARNING PFX
 664                                "%s Timed out waiting for management port to "
 665                                "get free before issuing command.\n",
 666                                qdev->ndev->name);
 667                 return -1;
 668         }
 669
 670         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
 671                            PHYAddr[mac_index] | regAddr);
 672
 673         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtDataReg, value);
 674
 675         /* Wait for write to complete 9/10/04 SJP */
 676         if (ql_wait_for_mii_ready(qdev)) {
 677                 if (netif_msg_link(qdev))
 678                         printk(KERN_WARNING PFX
 679                                "%s: Timed out waiting for management port to"
 680                                "get free before issuing command.\n",
 681                                qdev->ndev->name);
 682                 return -1;
 683         }
 684
 685         if (scanWasEnabled)
 686                 ql_mii_enable_scan_mode(qdev);
 687
 688         return 0;
 689 }
 690
 691 static int ql_mii_read_reg_ex(struct ql3_adapter *qdev, u16 regAddr,
 692                               u16 * value, u32 mac_index)
 693 {
 694         struct ql3xxx_port_registers __iomem *port_regs =
 695                         qdev->mem_map_registers;
 696         u8 scanWasEnabled;
 697         u32 temp;
 698
 699         scanWasEnabled = ql_mii_disable_scan_mode(qdev);
 700
 701         if (ql_wait_for_mii_ready(qdev)) {
 702                 if (netif_msg_link(qdev))
 703                         printk(KERN_WARNING PFX
 704                                "%s: Timed out waiting for management port to "
 705                                "get free before issuing command.\n",
 706                                qdev->ndev->name);
 707                 return -1;
 708         }
 709
 710         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
 711                            PHYAddr[mac_index] | regAddr);
 712
 713         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
 714                            (MAC_MII_CONTROL_RC << 16));
 715
 716         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
 717                            (MAC_MII_CONTROL_RC << 16) | MAC_MII_CONTROL_RC);
 718
 719         /* Wait for the read to complete */
 720         if (ql_wait_for_mii_ready(qdev)) {
 721                 if (netif_msg_link(qdev))
 722                         printk(KERN_WARNING PFX
 723                                "%s: Timed out waiting for management port to "
 724                                "get free after issuing command.\n",
 725                                qdev->ndev->name);
 726                 return -1;
 727         }
 728
 729         temp = ql_read_page0_reg(qdev, &port_regs->macMIIMgmtDataReg);
 730         *value = (u16) temp;
 731
 732         if (scanWasEnabled)
 733                 ql_mii_enable_scan_mode(qdev);
 734
 735         return 0;
 736 }
 737
 738 static int ql_mii_write_reg(struct ql3_adapter *qdev, u16 regAddr, u16 value)
 739 {
 740         struct ql3xxx_port_registers __iomem *port_regs =
 741                         qdev->mem_map_registers;
 742
 743         ql_mii_disable_scan_mode(qdev);
 744
 745         if (ql_wait_for_mii_ready(qdev)) {
 746                 if (netif_msg_link(qdev))
 747                         printk(KERN_WARNING PFX
 748                                "%s: Timed out waiting for management port to "
 749                                "get free before issuing command.\n",
 750                                qdev->ndev->name);
 751                 return -1;
 752         }
 753
 754         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
 755                            qdev->PHYAddr | regAddr);
 756
 757         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtDataReg, value);
 758
 759         /* Wait for write to complete. */
 760         if (ql_wait_for_mii_ready(qdev)) {
 761                 if (netif_msg_link(qdev))
 762                         printk(KERN_WARNING PFX
 763                                "%s: Timed out waiting for management port to "
 764                                "get free before issuing command.\n",
 765                                qdev->ndev->name);
 766                 return -1;
 767         }
 768
 769         ql_mii_enable_scan_mode(qdev);
 770
 771         return 0;
 772 }
 773
 774 static int ql_mii_read_reg(struct ql3_adapter *qdev, u16 regAddr, u16 *value)
 775 {
 776         u32 temp;
 777         struct ql3xxx_port_registers __iomem *port_regs =
 778                         qdev->mem_map_registers;
 779
 780         ql_mii_disable_scan_mode(qdev);
 781
 782         if (ql_wait_for_mii_ready(qdev)) {
 783                 if (netif_msg_link(qdev))
 784                         printk(KERN_WARNING PFX
 785                                "%s: Timed out waiting for management port to "
 786                                "get free before issuing command.\n",
 787                                qdev->ndev->name);
 788                 return -1;
 789         }
 790
 791         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
 792                            qdev->PHYAddr | regAddr);
 793
 794         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
 795                            (MAC_MII_CONTROL_RC << 16));
 796
 797         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
 798                            (MAC_MII_CONTROL_RC << 16) | MAC_MII_CONTROL_RC);
 799
 800         /* Wait for the read to complete */
 801         if (ql_wait_for_mii_ready(qdev)) {
 802                 if (netif_msg_link(qdev))
 803                         printk(KERN_WARNING PFX
 804                                "%s: Timed out waiting for management port to "
 805                                "get free before issuing command.\n",
 806                                qdev->ndev->name);
 807                 return -1;
 808         }
 809
 810         temp = ql_read_page0_reg(qdev, &port_regs->macMIIMgmtDataReg);
 811         *value = (u16) temp;
 812
 813         ql_mii_enable_scan_mode(qdev);
 814
 815         return 0;
 816 }
 817
 818 static void ql_petbi_reset(struct ql3_adapter *qdev)
 819 {
 820         ql_mii_write_reg(qdev, PETBI_CONTROL_REG, PETBI_CTRL_SOFT_RESET);
 821 }
 822
 823 static void ql_petbi_start_neg(struct ql3_adapter *qdev)
 824 {
 825         u16 reg;
 826
 827         /* Enable Auto-negotiation sense */
 828         ql_mii_read_reg(qdev, PETBI_TBI_CTRL, &reg);
 829         reg |= PETBI_TBI_AUTO_SENSE;
 830         ql_mii_write_reg(qdev, PETBI_TBI_CTRL, reg);
 831
 832         ql_mii_write_reg(qdev, PETBI_NEG_ADVER,
 833                          PETBI_NEG_PAUSE | PETBI_NEG_DUPLEX);
 834
 835         ql_mii_write_reg(qdev, PETBI_CONTROL_REG,
 836                          PETBI_CTRL_AUTO_NEG | PETBI_CTRL_RESTART_NEG |
 837                          PETBI_CTRL_FULL_DUPLEX | PETBI_CTRL_SPEED_1000);
 838
 839 }
 840
 841 static void ql_petbi_reset_ex(struct ql3_adapter *qdev, u32 mac_index)
 842 {
 843         ql_mii_write_reg_ex(qdev, PETBI_CONTROL_REG, PETBI_CTRL_SOFT_RESET,
 844                             mac_index);
 845 }
 846
 847 static void ql_petbi_start_neg_ex(struct ql3_adapter *qdev, u32 mac_index)
 848 {
 849         u16 reg;
 850
 851         /* Enable Auto-negotiation sense */
 852         ql_mii_read_reg_ex(qdev, PETBI_TBI_CTRL, &reg, mac_index);
 853         reg |= PETBI_TBI_AUTO_SENSE;
 854         ql_mii_write_reg_ex(qdev, PETBI_TBI_CTRL, reg, mac_index);
 855
 856         ql_mii_write_reg_ex(qdev, PETBI_NEG_ADVER,
 857                             PETBI_NEG_PAUSE | PETBI_NEG_DUPLEX, mac_index);
 858
 859         ql_mii_write_reg_ex(qdev, PETBI_CONTROL_REG,
 860                             PETBI_CTRL_AUTO_NEG | PETBI_CTRL_RESTART_NEG |
 861                             PETBI_CTRL_FULL_DUPLEX | PETBI_CTRL_SPEED_1000,
 862                             mac_index);
 863 }
 864
 865 static void ql_petbi_init(struct ql3_adapter *qdev)
 866 {
 867         ql_petbi_reset(qdev);
 868         ql_petbi_start_neg(qdev);
 869 }
 870
 871 static void ql_petbi_init_ex(struct ql3_adapter *qdev, u32 mac_index)
 872 {
 873         ql_petbi_reset_ex(qdev, mac_index);
 874         ql_petbi_start_neg_ex(qdev, mac_index);
 875 }
 876
 877 static int ql_is_petbi_neg_pause(struct ql3_adapter *qdev)
 878 {
 879         u16 reg;
 880
 881         if (ql_mii_read_reg(qdev, PETBI_NEG_PARTNER, &reg) < 0)
 882                 return 0;
 883
 884         return (reg & PETBI_NEG_PAUSE_MASK) == PETBI_NEG_PAUSE;
 885 }
 886
 887 static int ql_phy_get_speed(struct ql3_adapter *qdev)
 888 {
 889         u16 reg;
 890
 891         if (ql_mii_read_reg(qdev, AUX_CONTROL_STATUS, &reg) < 0)
 892                 return 0;
 893
 894         reg = (((reg & 0x18) >> 3) & 3);
 895
 896         if (reg == 2)
 897                 return SPEED_1000;
 898         else if (reg == 1)
 899                 return SPEED_100;
 900         else if (reg == 0)
 901                 return SPEED_10;
 902         else
 903                 return -1;
 904 }
 905
 906 static int ql_is_full_dup(struct ql3_adapter *qdev)
 907 {
 908         u16 reg;
 909
 910         if (ql_mii_read_reg(qdev, AUX_CONTROL_STATUS, &reg) < 0)
 911                 return 0;
 912
 913         return (reg & PHY_AUX_DUPLEX_STAT) != 0;
 914 }
 915
 916 static int ql_is_phy_neg_pause(struct ql3_adapter *qdev)
 917 {
 918         u16 reg;
 919
 920         if (ql_mii_read_reg(qdev, PHY_NEG_PARTNER, &reg) < 0)
 921                 return 0;
 922
 923         return (reg & PHY_NEG_PAUSE) != 0;
 924 }
 925
 926 /*
 927  * Caller holds hw_lock.
 928  */
 929 static void ql_mac_enable(struct ql3_adapter *qdev, u32 enable)
 930 {
 931         struct ql3xxx_port_registers __iomem *port_regs =
 932                         qdev->mem_map_registers;
 933         u32 value;
 934
 935         if (enable)
 936                 value = (MAC_CONFIG_REG_PE | (MAC_CONFIG_REG_PE << 16));
 937         else
 938                 value = (MAC_CONFIG_REG_PE << 16);
 939
 940         if (qdev->mac_index)
 941                 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
 942         else
 943                 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
 944 }
 945
 946 /*
 947  * Caller holds hw_lock.
 948  */
 949 static void ql_mac_cfg_soft_reset(struct ql3_adapter *qdev, u32 enable)
 950 {
 951         struct ql3xxx_port_registers __iomem *port_regs =
 952                         qdev->mem_map_registers;
 953         u32 value;
 954
 955         if (enable)
 956                 value = (MAC_CONFIG_REG_SR | (MAC_CONFIG_REG_SR << 16));
 957         else
 958                 value = (MAC_CONFIG_REG_SR << 16);
 959
 960         if (qdev->mac_index)
 961                 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
 962         else
 963                 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
 964 }
 965
 966 /*
 967  * Caller holds hw_lock.
 968  */
 969 static void ql_mac_cfg_gig(struct ql3_adapter *qdev, u32 enable)
 970 {
 971         struct ql3xxx_port_registers __iomem *port_regs =
 972                         qdev->mem_map_registers;
 973         u32 value;
 974
 975         if (enable)
 976                 value = (MAC_CONFIG_REG_GM | (MAC_CONFIG_REG_GM << 16));
 977         else
 978                 value = (MAC_CONFIG_REG_GM << 16);
 979
 980         if (qdev->mac_index)
 981                 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
 982         else
 983                 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
 984 }
 985
 986 /*
 987  * Caller holds hw_lock.
 988  */
 989 static void ql_mac_cfg_full_dup(struct ql3_adapter *qdev, u32 enable)
 990 {
 991         struct ql3xxx_port_registers __iomem *port_regs =
 992                         qdev->mem_map_registers;
 993         u32 value;
 994
 995         if (enable)
 996                 value = (MAC_CONFIG_REG_FD | (MAC_CONFIG_REG_FD << 16));
 997         else
 998                 value = (MAC_CONFIG_REG_FD << 16);
 999
1000         if (qdev->mac_index)
1001                 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1002         else
1003                 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1004 }
1005
1006 /*
1007  * Caller holds hw_lock.
1008  */
1009 static void ql_mac_cfg_pause(struct ql3_adapter *qdev, u32 enable)
1010 {
1011         struct ql3xxx_port_registers __iomem *port_regs =
1012                         qdev->mem_map_registers;
1013         u32 value;
1014
1015         if (enable)
1016                 value =
1017                     ((MAC_CONFIG_REG_TF | MAC_CONFIG_REG_RF) |
1018                      ((MAC_CONFIG_REG_TF | MAC_CONFIG_REG_RF) << 16));
1019         else
1020                 value = ((MAC_CONFIG_REG_TF | MAC_CONFIG_REG_RF) << 16);
1021
1022         if (qdev->mac_index)
1023                 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1024         else
1025                 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1026 }
1027
1028 /*
1029  * Caller holds hw_lock.
1030  */
1031 static int ql_is_fiber(struct ql3_adapter *qdev)
1032 {
1033         struct ql3xxx_port_registers __iomem *port_regs =
1034                         qdev->mem_map_registers;
1035         u32 bitToCheck = 0;
1036         u32 temp;
1037
1038         switch (qdev->mac_index) {
1039         case 0:
1040                 bitToCheck = PORT_STATUS_SM0;
1041                 break;
1042         case 1:
1043                 bitToCheck = PORT_STATUS_SM1;
1044                 break;
1045         }
1046
1047         temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1048         return (temp & bitToCheck) != 0;
1049 }
1050
1051 static int ql_is_auto_cfg(struct ql3_adapter *qdev)
1052 {
1053         u16 reg;
1054         ql_mii_read_reg(qdev, 0x00, &reg);
1055         return (reg & 0x1000) != 0;
1056 }
1057
1058 /*
1059  * Caller holds hw_lock.
1060  */
1061 static int ql_is_auto_neg_complete(struct ql3_adapter *qdev)
1062 {
1063         struct ql3xxx_port_registers __iomem *port_regs =
1064                         qdev->mem_map_registers;
1065         u32 bitToCheck = 0;
1066         u32 temp;
1067
1068         switch (qdev->mac_index) {
1069         case 0:
1070                 bitToCheck = PORT_STATUS_AC0;
1071                 break;
1072         case 1:
1073                 bitToCheck = PORT_STATUS_AC1;
1074                 break;
1075         }
1076
1077         temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1078         if (temp & bitToCheck) {
1079                 if (netif_msg_link(qdev))
1080                         printk(KERN_INFO PFX
1081                                "%s: Auto-Negotiate complete.\n",
1082                                qdev->ndev->name);
1083                 return 1;
1084         } else {
1085                 if (netif_msg_link(qdev))
1086                         printk(KERN_WARNING PFX
1087                                "%s: Auto-Negotiate incomplete.\n",
1088                                qdev->ndev->name);
1089                 return 0;
1090         }
1091 }
1092
1093 /*
1094  *  ql_is_neg_pause() returns 1 if pause was negotiated to be on
1095  */
1096 static int ql_is_neg_pause(struct ql3_adapter *qdev)
1097 {
1098         if (ql_is_fiber(qdev))
1099                 return ql_is_petbi_neg_pause(qdev);
1100         else
1101                 return ql_is_phy_neg_pause(qdev);
1102 }
1103
1104 static int ql_auto_neg_error(struct ql3_adapter *qdev)
1105 {
1106         struct ql3xxx_port_registers __iomem *port_regs =
1107                         qdev->mem_map_registers;
1108         u32 bitToCheck = 0;
1109         u32 temp;
1110
1111         switch (qdev->mac_index) {
1112         case 0:
1113                 bitToCheck = PORT_STATUS_AE0;
1114                 break;
1115         case 1:
1116                 bitToCheck = PORT_STATUS_AE1;
1117                 break;
1118         }
1119         temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1120         return (temp & bitToCheck) != 0;
1121 }
1122
1123 static u32 ql_get_link_speed(struct ql3_adapter *qdev)
1124 {
1125         if (ql_is_fiber(qdev))
1126                 return SPEED_1000;
1127         else
1128                 return ql_phy_get_speed(qdev);
1129 }
1130
1131 static int ql_is_link_full_dup(struct ql3_adapter *qdev)
1132 {
1133         if (ql_is_fiber(qdev))
1134                 return 1;
1135         else
1136                 return ql_is_full_dup(qdev);
1137 }
1138
1139 /*
1140  * Caller holds hw_lock.
1141  */
1142 static int ql_link_down_detect(struct ql3_adapter *qdev)
1143 {
1144         struct ql3xxx_port_registers __iomem *port_regs =
1145                         qdev->mem_map_registers;
1146         u32 bitToCheck = 0;
1147         u32 temp;
1148
1149         switch (qdev->mac_index) {
1150         case 0:
1151                 bitToCheck = ISP_CONTROL_LINK_DN_0;
1152                 break;
1153         case 1:
1154                 bitToCheck = ISP_CONTROL_LINK_DN_1;
1155                 break;
1156         }
1157
1158         temp =
1159             ql_read_common_reg(qdev, &port_regs->CommonRegs.ispControlStatus);
1160         return (temp & bitToCheck) != 0;
1161 }
1162
1163 /*
1164  * Caller holds hw_lock.
1165  */
1166 static int ql_link_down_detect_clear(struct ql3_adapter *qdev)
1167 {
1168         struct ql3xxx_port_registers __iomem *port_regs =
1169                         qdev->mem_map_registers;
1170
1171         switch (qdev->mac_index) {
1172         case 0:
1173                 ql_write_common_reg(qdev,
1174                                     &port_regs->CommonRegs.ispControlStatus,
1175                                     (ISP_CONTROL_LINK_DN_0) |
1176                                     (ISP_CONTROL_LINK_DN_0 << 16));
1177                 break;
1178
1179         case 1:
1180                 ql_write_common_reg(qdev,
1181                                     &port_regs->CommonRegs.ispControlStatus,
1182                                     (ISP_CONTROL_LINK_DN_1) |
1183                                     (ISP_CONTROL_LINK_DN_1 << 16));
1184                 break;
1185
1186         default:
1187                 return 1;
1188         }
1189
1190         return 0;
1191 }
1192
1193 /*
1194  * Caller holds hw_lock.
1195  */
1196 static int ql_this_adapter_controls_port(struct ql3_adapter *qdev,
1197                                          u32 mac_index)
1198 {
1199         struct ql3xxx_port_registers __iomem *port_regs =
1200                         qdev->mem_map_registers;
1201         u32 bitToCheck = 0;
1202         u32 temp;
1203
1204         switch (mac_index) {
1205         case 0:
1206                 bitToCheck = PORT_STATUS_F1_ENABLED;
1207                 break;
1208         case 1:
1209                 bitToCheck = PORT_STATUS_F3_ENABLED;
1210                 break;
1211         default:
1212                 break;
1213         }
1214
1215         temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1216         if (temp & bitToCheck) {
1217                 if (netif_msg_link(qdev))
1218                         printk(KERN_DEBUG PFX
1219                                "%s: is not link master.\n", qdev->ndev->name);
1220                 return 0;
1221         } else {
1222                 if (netif_msg_link(qdev))
1223                         printk(KERN_DEBUG PFX
1224                                "%s: is link master.\n", qdev->ndev->name);
1225                 return 1;
1226         }
1227 }
1228
1229 static void ql_phy_reset_ex(struct ql3_adapter *qdev, u32 mac_index)
1230 {
1231         ql_mii_write_reg_ex(qdev, CONTROL_REG, PHY_CTRL_SOFT_RESET, mac_index);
1232 }
1233
1234 static void ql_phy_start_neg_ex(struct ql3_adapter *qdev, u32 mac_index)
1235 {
1236         u16 reg;
1237
1238         ql_mii_write_reg_ex(qdev, PHY_NEG_ADVER,
1239                             PHY_NEG_PAUSE | PHY_NEG_ADV_SPEED | 1, mac_index);
1240
1241         ql_mii_read_reg_ex(qdev, CONTROL_REG, &reg, mac_index);
1242         ql_mii_write_reg_ex(qdev, CONTROL_REG, reg | PHY_CTRL_RESTART_NEG,
1243                             mac_index);
1244 }
1245
1246 static void ql_phy_init_ex(struct ql3_adapter *qdev, u32 mac_index)
1247 {
1248         ql_phy_reset_ex(qdev, mac_index);
1249         ql_phy_start_neg_ex(qdev, mac_index);
1250 }
1251
1252 /*
1253  * Caller holds hw_lock.
1254  */
1255 static u32 ql_get_link_state(struct ql3_adapter *qdev)
1256 {
1257         struct ql3xxx_port_registers __iomem *port_regs =
1258                         qdev->mem_map_registers;
1259         u32 bitToCheck = 0;
1260         u32 temp, linkState;
1261
1262         switch (qdev->mac_index) {
1263         case 0:
1264                 bitToCheck = PORT_STATUS_UP0;
1265                 break;
1266         case 1:
1267                 bitToCheck = PORT_STATUS_UP1;
1268                 break;
1269         }
1270         temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1271         if (temp & bitToCheck) {
1272                 linkState = LS_UP;
1273         } else {
1274                 linkState = LS_DOWN;
1275                 if (netif_msg_link(qdev))
1276                         printk(KERN_WARNING PFX
1277                                "%s: Link is down.\n", qdev->ndev->name);
1278         }
1279         return linkState;
1280 }
1281
1282 static int ql_port_start(struct ql3_adapter *qdev)
1283 {
1284         if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1285                 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1286                          2) << 7))
1287                 return -1;
1288
1289         if (ql_is_fiber(qdev)) {
1290                 ql_petbi_init(qdev);
1291         } else {
1292                 /* Copper port */
1293                 ql_phy_init_ex(qdev, qdev->mac_index);
1294         }
1295
1296         ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1297         return 0;
1298 }
1299
1300 static int ql_finish_auto_neg(struct ql3_adapter *qdev)
1301 {
1302
1303         if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1304                 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1305                          2) << 7))
1306                 return -1;
1307
1308         if (!ql_auto_neg_error(qdev)) {
1309                 if (test_bit(QL_LINK_MASTER,&qdev->flags)) {
1310                         /* configure the MAC */
1311                         if (netif_msg_link(qdev))
1312                                 printk(KERN_DEBUG PFX
1313                                        "%s: Configuring link.\n",
1314                                        qdev->ndev->
1315                                        name);
1316                         ql_mac_cfg_soft_reset(qdev, 1);
1317                         ql_mac_cfg_gig(qdev,
1318                                        (ql_get_link_speed
1319                                         (qdev) ==
1320                                         SPEED_1000));
1321                         ql_mac_cfg_full_dup(qdev,
1322                                             ql_is_link_full_dup
1323                                             (qdev));
1324                         ql_mac_cfg_pause(qdev,
1325                                          ql_is_neg_pause
1326                                          (qdev));
1327                         ql_mac_cfg_soft_reset(qdev, 0);
1328
1329                         /* enable the MAC */
1330                         if (netif_msg_link(qdev))
1331                                 printk(KERN_DEBUG PFX
1332                                        "%s: Enabling mac.\n",
1333                                        qdev->ndev->
1334                                                name);
1335                         ql_mac_enable(qdev, 1);
1336                 }
1337
1338                 if (netif_msg_link(qdev))
1339                         printk(KERN_DEBUG PFX
1340                                "%s: Change port_link_state LS_DOWN to LS_UP.\n",
1341                                qdev->ndev->name);
1342                 qdev->port_link_state = LS_UP;
1343                 netif_start_queue(qdev->ndev);
1344                 netif_carrier_on(qdev->ndev);
1345                 if (netif_msg_link(qdev))
1346                         printk(KERN_INFO PFX
1347                                "%s: Link is up at %d Mbps, %s duplex.\n",
1348                                qdev->ndev->name,
1349                                ql_get_link_speed(qdev),
1350                                ql_is_link_full_dup(qdev)
1351                                ? "full" : "half");
1352
1353         } else {        /* Remote error detected */
1354
1355                 if (test_bit(QL_LINK_MASTER,&qdev->flags)) {
1356                         if (netif_msg_link(qdev))
1357                                 printk(KERN_DEBUG PFX
1358                                        "%s: Remote error detected. "
1359                                        "Calling ql_port_start().\n",
1360                                        qdev->ndev->
1361                                        name);
1362                         /*
1363                          * ql_port_start() is shared code and needs
1364                          * to lock the PHY on it's own.
1365                          */
1366                         ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1367                         if(ql_port_start(qdev)) {/* Restart port */
1368                                 return -1;
1369                         } else
1370                                 return 0;
1371                 }
1372         }
1373         ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1374         return 0;
1375 }
1376
1377 static void ql_link_state_machine(struct ql3_adapter *qdev)
1378 {
1379         u32 curr_link_state;
1380         unsigned long hw_flags;
1381
1382         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1383
1384         curr_link_state = ql_get_link_state(qdev);
1385
1386         if (test_bit(QL_RESET_ACTIVE,&qdev->flags)) {
1387                 if (netif_msg_link(qdev))
1388                         printk(KERN_INFO PFX
1389                                "%s: Reset in progress, skip processing link "
1390                                "state.\n", qdev->ndev->name);
1391
1392                 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1393                 return;
1394         }
1395
1396         switch (qdev->port_link_state) {
1397         default:
1398                 if (test_bit(QL_LINK_MASTER,&qdev->flags)) {
1399                         ql_port_start(qdev);
1400                 }
1401                 qdev->port_link_state = LS_DOWN;
1402                 /* Fall Through */
1403
1404         case LS_DOWN:
1405                 if (netif_msg_link(qdev))
1406                         printk(KERN_DEBUG PFX
1407                                "%s: port_link_state = LS_DOWN.\n",
1408                                qdev->ndev->name);
1409                 if (curr_link_state == LS_UP) {
1410                         if (netif_msg_link(qdev))
1411                                 printk(KERN_DEBUG PFX
1412                                        "%s: curr_link_state = LS_UP.\n",
1413                                        qdev->ndev->name);
1414                         if (ql_is_auto_neg_complete(qdev))
1415                                 ql_finish_auto_neg(qdev);
1416
1417                         if (qdev->port_link_state == LS_UP)
1418                                 ql_link_down_detect_clear(qdev);
1419
1420                 }
1421                 break;
1422
1423         case LS_UP:
1424                 /*
1425                  * See if the link is currently down or went down and came
1426                  * back up
1427                  */
1428                 if ((curr_link_state == LS_DOWN) || ql_link_down_detect(qdev)) {
1429                         if (netif_msg_link(qdev))
1430                                 printk(KERN_INFO PFX "%s: Link is down.\n",
1431                                        qdev->ndev->name);
1432                         qdev->port_link_state = LS_DOWN;
1433                 }
1434                 break;
1435         }
1436         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1437 }
1438
1439 /*
1440  * Caller must take hw_lock and QL_PHY_GIO_SEM.
1441  */
1442 static void ql_get_phy_owner(struct ql3_adapter *qdev)
1443 {
1444         if (ql_this_adapter_controls_port(qdev, qdev->mac_index))
1445                 set_bit(QL_LINK_MASTER,&qdev->flags);
1446         else
1447                 clear_bit(QL_LINK_MASTER,&qdev->flags);
1448 }
1449
1450 /*
1451  * Caller must take hw_lock and QL_PHY_GIO_SEM.
1452  */
1453 static void ql_init_scan_mode(struct ql3_adapter *qdev)
1454 {
1455         ql_mii_enable_scan_mode(qdev);
1456
1457         if (test_bit(QL_LINK_OPTICAL,&qdev->flags)) {
1458                 if (ql_this_adapter_controls_port(qdev, qdev->mac_index))
1459                         ql_petbi_init_ex(qdev, qdev->mac_index);
1460         } else {
1461                 if (ql_this_adapter_controls_port(qdev, qdev->mac_index))
1462                         ql_phy_init_ex(qdev, qdev->mac_index);
1463         }
1464 }
1465
1466 /*
1467  * MII_Setup needs to be called before taking the PHY out of reset so that the
1468  * management interface clock speed can be set properly.  It would be better if
1469  * we had a way to disable MDC until after the PHY is out of reset, but we
1470  * don't have that capability.
1471  */
1472 static int ql_mii_setup(struct ql3_adapter *qdev)
1473 {
1474         u32 reg;
1475         struct ql3xxx_port_registers __iomem *port_regs =
1476                         qdev->mem_map_registers;
1477
1478         if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1479                         (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1480                          2) << 7))
1481                 return -1;
1482
1483         if (qdev->device_id == QL3032_DEVICE_ID)
1484                 ql_write_page0_reg(qdev,
1485                         &port_regs->macMIIMgmtControlReg, 0x0f00000);
1486
1487         /* Divide 125MHz clock by 28 to meet PHY timing requirements */
1488         reg = MAC_MII_CONTROL_CLK_SEL_DIV28;
1489
1490         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
1491                            reg | ((MAC_MII_CONTROL_CLK_SEL_MASK) << 16));
1492
1493         ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1494         return 0;
1495 }
1496
1497 static u32 ql_supported_modes(struct ql3_adapter *qdev)
1498 {
1499         u32 supported;
1500
1501         if (test_bit(QL_LINK_OPTICAL,&qdev->flags)) {
1502                 supported = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
1503                     | SUPPORTED_Autoneg;
1504         } else {
1505                 supported = SUPPORTED_10baseT_Half
1506                     | SUPPORTED_10baseT_Full
1507                     | SUPPORTED_100baseT_Half
1508                     | SUPPORTED_100baseT_Full
1509                     | SUPPORTED_1000baseT_Half
1510                     | SUPPORTED_1000baseT_Full
1511                     | SUPPORTED_Autoneg | SUPPORTED_TP;
1512         }
1513
1514         return supported;
1515 }
1516
1517 static int ql_get_auto_cfg_status(struct ql3_adapter *qdev)
1518 {
1519         int status;
1520         unsigned long hw_flags;
1521         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1522         if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1523                 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1524                          2) << 7)) {
1525                 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1526                 return 0;
1527         }
1528         status = ql_is_auto_cfg(qdev);
1529         ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1530         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1531         return status;
1532 }
1533
1534 static u32 ql_get_speed(struct ql3_adapter *qdev)
1535 {
1536         u32 status;
1537         unsigned long hw_flags;
1538         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1539         if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1540                 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1541                          2) << 7)) {
1542                 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1543                 return 0;
1544         }
1545         status = ql_get_link_speed(qdev);
1546         ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1547         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1548         return status;
1549 }
1550
1551 static int ql_get_full_dup(struct ql3_adapter *qdev)
1552 {
1553         int status;
1554         unsigned long hw_flags;
1555         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1556         if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1557                 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1558                          2) << 7)) {
1559                 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1560                 return 0;
1561         }
1562         status = ql_is_link_full_dup(qdev);
1563         ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1564         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1565         return status;
1566 }
1567
1568
1569 static int ql_get_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
1570 {
1571         struct ql3_adapter *qdev = netdev_priv(ndev);
1572
1573         ecmd->transceiver = XCVR_INTERNAL;
1574         ecmd->supported = ql_supported_modes(qdev);
1575
1576         if (test_bit(QL_LINK_OPTICAL,&qdev->flags)) {
1577                 ecmd->port = PORT_FIBRE;
1578         } else {
1579                 ecmd->port = PORT_TP;
1580                 ecmd->phy_address = qdev->PHYAddr;
1581         }
1582         ecmd->advertising = ql_supported_modes(qdev);
1583         ecmd->autoneg = ql_get_auto_cfg_status(qdev);
1584         ecmd->speed = ql_get_speed(qdev);
1585         ecmd->duplex = ql_get_full_dup(qdev);
1586         return 0;
1587 }
1588
1589 static void ql_get_drvinfo(struct net_device *ndev,
1590                            struct ethtool_drvinfo *drvinfo)
1591 {
1592         struct ql3_adapter *qdev = netdev_priv(ndev);
1593         strncpy(drvinfo->driver, ql3xxx_driver_name, 32);
1594         strncpy(drvinfo->version, ql3xxx_driver_version, 32);
1595         strncpy(drvinfo->fw_version, "N/A", 32);
1596         strncpy(drvinfo->bus_info, pci_name(qdev->pdev), 32);
1597         drvinfo->n_stats = 0;
1598         drvinfo->testinfo_len = 0;
1599         drvinfo->regdump_len = 0;
1600         drvinfo->eedump_len = 0;
1601 }
1602
1603 static u32 ql_get_msglevel(struct net_device *ndev)
1604 {
1605         struct ql3_adapter *qdev = netdev_priv(ndev);
1606         return qdev->msg_enable;
1607 }
1608
1609 static void ql_set_msglevel(struct net_device *ndev, u32 value)
1610 {
1611         struct ql3_adapter *qdev = netdev_priv(ndev);
1612         qdev->msg_enable = value;
1613 }
1614
1615 static const struct ethtool_ops ql3xxx_ethtool_ops = {
1616         .get_settings = ql_get_settings,
1617         .get_drvinfo = ql_get_drvinfo,
1618         .get_perm_addr = ethtool_op_get_perm_addr,
1619         .get_link = ethtool_op_get_link,
1620         .get_msglevel = ql_get_msglevel,
1621         .set_msglevel = ql_set_msglevel,
1622 };
1623
1624 static int ql_populate_free_queue(struct ql3_adapter *qdev)
1625 {
1626         struct ql_rcv_buf_cb *lrg_buf_cb = qdev->lrg_buf_free_head;
1627         u64 map;
1628
1629         while (lrg_buf_cb) {
1630                 if (!lrg_buf_cb->skb) {
1631                         lrg_buf_cb->skb = netdev_alloc_skb(qdev->ndev,
1632                                                            qdev->lrg_buffer_len);
1633                         if (unlikely(!lrg_buf_cb->skb)) {
1634                                 printk(KERN_DEBUG PFX
1635                                        "%s: Failed netdev_alloc_skb().\n",
1636                                        qdev->ndev->name);
1637                                 break;
1638                         } else {
1639                                 /*
1640                                  * We save some space to copy the ethhdr from
1641                                  * first buffer
1642                                  */
1643                                 skb_reserve(lrg_buf_cb->skb, QL_HEADER_SPACE);
1644                                 map = pci_map_single(qdev->pdev,
1645                                                      lrg_buf_cb->skb->data,
1646                                                      qdev->lrg_buffer_len -
1647                                                      QL_HEADER_SPACE,
1648                                                      PCI_DMA_FROMDEVICE);
1649                                 lrg_buf_cb->buf_phy_addr_low =
1650                                     cpu_to_le32(LS_64BITS(map));
1651                                 lrg_buf_cb->buf_phy_addr_high =
1652                                     cpu_to_le32(MS_64BITS(map));
1653                                 pci_unmap_addr_set(lrg_buf_cb, mapaddr, map);
1654                                 pci_unmap_len_set(lrg_buf_cb, maplen,
1655                                                   qdev->lrg_buffer_len -
1656                                                   QL_HEADER_SPACE);
1657                                 --qdev->lrg_buf_skb_check;
1658                                 if (!qdev->lrg_buf_skb_check)
1659                                         return 1;
1660                         }
1661                 }
1662                 lrg_buf_cb = lrg_buf_cb->next;
1663         }
1664         return 0;
1665 }
1666
1667 /*
1668  * Caller holds hw_lock.
1669  */
1670 static void ql_update_lrg_bufq_prod_index(struct ql3_adapter *qdev)
1671 {
1672         struct bufq_addr_element *lrg_buf_q_ele;
1673         int i;
1674         struct ql_rcv_buf_cb *lrg_buf_cb;
1675         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
1676
1677         if ((qdev->lrg_buf_free_count >= 8)
1678             && (qdev->lrg_buf_release_cnt >= 16)) {
1679
1680                 if (qdev->lrg_buf_skb_check)
1681                         if (!ql_populate_free_queue(qdev))
1682                                 return;
1683
1684                 lrg_buf_q_ele = qdev->lrg_buf_next_free;
1685
1686                 while ((qdev->lrg_buf_release_cnt >= 16)
1687                        && (qdev->lrg_buf_free_count >= 8)) {
1688
1689                         for (i = 0; i < 8; i++) {
1690                                 lrg_buf_cb =
1691                                     ql_get_from_lrg_buf_free_list(qdev);
1692                                 lrg_buf_q_ele->addr_high =
1693                                     lrg_buf_cb->buf_phy_addr_high;
1694                                 lrg_buf_q_ele->addr_low =
1695                                     lrg_buf_cb->buf_phy_addr_low;
1696                                 lrg_buf_q_ele++;
1697
1698                                 qdev->lrg_buf_release_cnt--;
1699                         }
1700
1701                         qdev->lrg_buf_q_producer_index++;
1702
1703                         if (qdev->lrg_buf_q_producer_index == qdev->num_lbufq_entries)
1704                                 qdev->lrg_buf_q_producer_index = 0;
1705
1706                         if (qdev->lrg_buf_q_producer_index ==
1707                             (qdev->num_lbufq_entries - 1)) {
1708                                 lrg_buf_q_ele = qdev->lrg_buf_q_virt_addr;
1709                         }
1710                 }
1711
1712                 qdev->lrg_buf_next_free = lrg_buf_q_ele;
1713
1714                 ql_write_common_reg(qdev,
1715                                     &port_regs->CommonRegs.
1716                                     rxLargeQProducerIndex,
1717                                     qdev->lrg_buf_q_producer_index);
1718         }
1719 }
1720
1721 static void ql_process_mac_tx_intr(struct ql3_adapter *qdev,
1722                                    struct ob_mac_iocb_rsp *mac_rsp)
1723 {
1724         struct ql_tx_buf_cb *tx_cb;
1725         int i;
1726
1727         tx_cb = &qdev->tx_buf[mac_rsp->transaction_id];
1728         pci_unmap_single(qdev->pdev,
1729                          pci_unmap_addr(&tx_cb->map[0], mapaddr),
1730                          pci_unmap_len(&tx_cb->map[0], maplen),
1731                          PCI_DMA_TODEVICE);
1732         tx_cb->seg_count--;
1733         if (tx_cb->seg_count) {
1734                 for (i = 1; i < tx_cb->seg_count; i++) {
1735                         pci_unmap_page(qdev->pdev,
1736                                        pci_unmap_addr(&tx_cb->map[i],
1737                                                       mapaddr),
1738                                        pci_unmap_len(&tx_cb->map[i], maplen),
1739                                        PCI_DMA_TODEVICE);
1740                 }
1741         }
1742         qdev->stats.tx_packets++;
1743         qdev->stats.tx_bytes += tx_cb->skb->len;
1744         dev_kfree_skb_irq(tx_cb->skb);
1745         tx_cb->skb = NULL;
1746         atomic_inc(&qdev->tx_count);
1747 }
1748
1749 /*
1750  * The difference between 3022 and 3032 for inbound completions:
1751  * 3022 uses two buffers per completion.  The first buffer contains
1752  * (some) header info, the second the remainder of the headers plus
1753  * the data.  For this chip we reserve some space at the top of the
1754  * receive buffer so that the header info in buffer one can be
1755  * prepended to the buffer two.  Buffer two is the sent up while
1756  * buffer one is returned to the hardware to be reused.
1757  * 3032 receives all of it's data and headers in one buffer for a
1758  * simpler process.  3032 also supports checksum verification as
1759  * can be seen in ql_process_macip_rx_intr().
1760  */
1761 static void ql_process_mac_rx_intr(struct ql3_adapter *qdev,
1762                                    struct ib_mac_iocb_rsp *ib_mac_rsp_ptr)
1763 {
1764         long int offset;
1765         u32 lrg_buf_phy_addr_low = 0;
1766         struct ql_rcv_buf_cb *lrg_buf_cb1 = NULL;
1767         struct ql_rcv_buf_cb *lrg_buf_cb2 = NULL;
1768         u32 *curr_ial_ptr;
1769         struct sk_buff *skb;
1770         u16 length = le16_to_cpu(ib_mac_rsp_ptr->length);
1771
1772         /*
1773          * Get the inbound address list (small buffer).
1774          */
1775         offset = qdev->small_buf_index * QL_SMALL_BUFFER_SIZE;
1776         if (++qdev->small_buf_index == NUM_SMALL_BUFFERS)
1777                 qdev->small_buf_index = 0;
1778
1779         curr_ial_ptr = (u32 *) (qdev->small_buf_virt_addr + offset);
1780         qdev->last_rsp_offset = qdev->small_buf_phy_addr_low + offset;
1781         qdev->small_buf_release_cnt++;
1782
1783         if (qdev->device_id == QL3022_DEVICE_ID) {
1784                 /* start of first buffer (3022 only) */
1785                 lrg_buf_phy_addr_low = le32_to_cpu(*curr_ial_ptr);
1786                 lrg_buf_cb1 = &qdev->lrg_buf[qdev->lrg_buf_index];
1787                 qdev->lrg_buf_release_cnt++;
1788                 if (++qdev->lrg_buf_index == qdev->num_large_buffers) {
1789                         qdev->lrg_buf_index = 0;
1790                 }
1791                 curr_ial_ptr++; /* 64-bit pointers require two incs. */
1792                 curr_ial_ptr++;
1793         }
1794
1795         /* start of second buffer */
1796         lrg_buf_phy_addr_low = le32_to_cpu(*curr_ial_ptr);
1797         lrg_buf_cb2 = &qdev->lrg_buf[qdev->lrg_buf_index];
1798
1799         /*
1800          * Second buffer gets sent up the stack.
1801          */
1802         qdev->lrg_buf_release_cnt++;
1803         if (++qdev->lrg_buf_index == qdev->num_large_buffers)
1804                 qdev->lrg_buf_index = 0;
1805         skb = lrg_buf_cb2->skb;
1806
1807         qdev->stats.rx_packets++;
1808         qdev->stats.rx_bytes += length;
1809
1810         skb_put(skb, length);
1811         pci_unmap_single(qdev->pdev,
1812                          pci_unmap_addr(lrg_buf_cb2, mapaddr),
1813                          pci_unmap_len(lrg_buf_cb2, maplen),
1814                          PCI_DMA_FROMDEVICE);
1815         prefetch(skb->data);
1816         skb->dev = qdev->ndev;
1817         skb->ip_summed = CHECKSUM_NONE;
1818         skb->protocol = eth_type_trans(skb, qdev->ndev);
1819
1820         netif_receive_skb(skb);
1821         qdev->ndev->last_rx = jiffies;
1822         lrg_buf_cb2->skb = NULL;
1823
1824         if (qdev->device_id == QL3022_DEVICE_ID)
1825                 ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb1);
1826         ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb2);
1827 }
1828
1829 static void ql_process_macip_rx_intr(struct ql3_adapter *qdev,
1830                                      struct ib_ip_iocb_rsp *ib_ip_rsp_ptr)
1831 {
1832         long int offset;
1833         u32 lrg_buf_phy_addr_low = 0;
1834         struct ql_rcv_buf_cb *lrg_buf_cb1 = NULL;
1835         struct ql_rcv_buf_cb *lrg_buf_cb2 = NULL;
1836         u32 *curr_ial_ptr;
1837         struct sk_buff *skb1 = NULL, *skb2;
1838         struct net_device *ndev = qdev->ndev;
1839         u16 length = le16_to_cpu(ib_ip_rsp_ptr->length);
1840         u16 size = 0;
1841
1842         /*
1843          * Get the inbound address list (small buffer).
1844          */
1845
1846         offset = qdev->small_buf_index * QL_SMALL_BUFFER_SIZE;
1847         if (++qdev->small_buf_index == NUM_SMALL_BUFFERS)
1848                 qdev->small_buf_index = 0;
1849         curr_ial_ptr = (u32 *) (qdev->small_buf_virt_addr + offset);
1850         qdev->last_rsp_offset = qdev->small_buf_phy_addr_low + offset;
1851         qdev->small_buf_release_cnt++;
1852
1853         if (qdev->device_id == QL3022_DEVICE_ID) {
1854                 /* start of first buffer on 3022 */
1855                 lrg_buf_phy_addr_low = le32_to_cpu(*curr_ial_ptr);
1856                 lrg_buf_cb1 = &qdev->lrg_buf[qdev->lrg_buf_index];
1857                 qdev->lrg_buf_release_cnt++;
1858                 if (++qdev->lrg_buf_index == qdev->num_large_buffers)
1859                         qdev->lrg_buf_index = 0;
1860                 skb1 = lrg_buf_cb1->skb;
1861                 curr_ial_ptr++; /* 64-bit pointers require two incs. */
1862                 curr_ial_ptr++;
1863                 size = ETH_HLEN;
1864                 if (*((u16 *) skb1->data) != 0xFFFF)
1865                         size += VLAN_ETH_HLEN - ETH_HLEN;
1866         }
1867
1868         /* start of second buffer */
1869         lrg_buf_phy_addr_low = le32_to_cpu(*curr_ial_ptr);
1870         lrg_buf_cb2 = &qdev->lrg_buf[qdev->lrg_buf_index];
1871         skb2 = lrg_buf_cb2->skb;
1872         qdev->lrg_buf_release_cnt++;
1873         if (++qdev->lrg_buf_index == qdev->num_large_buffers)
1874                 qdev->lrg_buf_index = 0;
1875
1876         skb_put(skb2, length);  /* Just the second buffer length here. */
1877         pci_unmap_single(qdev->pdev,
1878                          pci_unmap_addr(lrg_buf_cb2, mapaddr),
1879                          pci_unmap_len(lrg_buf_cb2, maplen),
1880                          PCI_DMA_FROMDEVICE);
1881         prefetch(skb2->data);
1882
1883         skb2->ip_summed = CHECKSUM_NONE;
1884         if (qdev->device_id == QL3022_DEVICE_ID) {
1885                 /*
1886                  * Copy the ethhdr from first buffer to second. This
1887                  * is necessary for 3022 IP completions.
1888                  */
1889                 memcpy(skb_push(skb2, size), skb1->data + VLAN_ID_LEN, size);
1890         } else {
1891                 u16 checksum = le16_to_cpu(ib_ip_rsp_ptr->checksum);
1892                 if (checksum &
1893                         (IB_IP_IOCB_RSP_3032_ICE |
1894                          IB_IP_IOCB_RSP_3032_CE |
1895                          IB_IP_IOCB_RSP_3032_NUC)) {
1896                         printk(KERN_ERR
1897                                "%s: Bad checksum for this %s packet, checksum = %x.\n",
1898                                __func__,
1899                                ((checksum &
1900                                 IB_IP_IOCB_RSP_3032_TCP) ? "TCP" :
1901                                 "UDP"),checksum);
1902                 } else if (checksum & IB_IP_IOCB_RSP_3032_TCP) {
1903                         skb2->ip_summed = CHECKSUM_UNNECESSARY;
1904                 }
1905         }
1906         skb2->dev = qdev->ndev;
1907         skb2->protocol = eth_type_trans(skb2, qdev->ndev);
1908
1909         netif_receive_skb(skb2);
1910         qdev->stats.rx_packets++;
1911         qdev->stats.rx_bytes += length;
1912         ndev->last_rx = jiffies;
1913         lrg_buf_cb2->skb = NULL;
1914
1915         if (qdev->device_id == QL3022_DEVICE_ID)
1916                 ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb1);
1917         ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb2);
1918 }
1919
1920 static int ql_tx_rx_clean(struct ql3_adapter *qdev,
1921                           int *tx_cleaned, int *rx_cleaned, int work_to_do)
1922 {
1923         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
1924         struct net_rsp_iocb *net_rsp;
1925         struct net_device *ndev = qdev->ndev;
1926         unsigned long hw_flags;
1927
1928         /* While there are entries in the completion queue. */
1929         while ((cpu_to_le32(*(qdev->prsp_producer_index)) !=
1930                 qdev->rsp_consumer_index) && (*rx_cleaned < work_to_do)) {
1931
1932                 net_rsp = qdev->rsp_current;
1933                 switch (net_rsp->opcode) {
1934
1935                 case OPCODE_OB_MAC_IOCB_FN0:
1936                 case OPCODE_OB_MAC_IOCB_FN2:
1937                         ql_process_mac_tx_intr(qdev, (struct ob_mac_iocb_rsp *)
1938                                                net_rsp);
1939                         (*tx_cleaned)++;
1940                         break;
1941
1942                 case OPCODE_IB_MAC_IOCB:
1943                 case OPCODE_IB_3032_MAC_IOCB:
1944                         ql_process_mac_rx_intr(qdev, (struct ib_mac_iocb_rsp *)
1945                                                net_rsp);
1946                         (*rx_cleaned)++;
1947                         break;
1948
1949                 case OPCODE_IB_IP_IOCB:
1950                 case OPCODE_IB_3032_IP_IOCB:
1951                         ql_process_macip_rx_intr(qdev, (struct ib_ip_iocb_rsp *)
1952                                                  net_rsp);
1953                         (*rx_cleaned)++;
1954                         break;
1955                 default:
1956                         {
1957                                 u32 *tmp = (u32 *) net_rsp;
1958                                 printk(KERN_ERR PFX
1959                                        "%s: Hit default case, not "
1960                                        "handled!\n"
1961                                        "        dropping the packet, opcode = "
1962                                        "%x.\n",
1963                                        ndev->name, net_rsp->opcode);
1964                                 printk(KERN_ERR PFX
1965                                        "0x%08lx 0x%08lx 0x%08lx 0x%08lx \n",
1966                                        (unsigned long int)tmp[0],
1967                                        (unsigned long int)tmp[1],
1968                                        (unsigned long int)tmp[2],
1969                                        (unsigned long int)tmp[3]);
1970                         }
1971                 }
1972
1973                 qdev->rsp_consumer_index++;
1974
1975                 if (qdev->rsp_consumer_index == NUM_RSP_Q_ENTRIES) {
1976                         qdev->rsp_consumer_index = 0;
1977                         qdev->rsp_current = qdev->rsp_q_virt_addr;
1978                 } else {
1979                         qdev->rsp_current++;
1980                 }
1981         }
1982
1983         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1984
1985         ql_update_lrg_bufq_prod_index(qdev);
1986
1987         if (qdev->small_buf_release_cnt >= 16) {
1988                 while (qdev->small_buf_release_cnt >= 16) {
1989                         qdev->small_buf_q_producer_index++;
1990
1991                         if (qdev->small_buf_q_producer_index ==
1992                             NUM_SBUFQ_ENTRIES)
1993                                 qdev->small_buf_q_producer_index = 0;
1994                         qdev->small_buf_release_cnt -= 8;
1995                 }
1996
1997                 ql_write_common_reg(qdev,
1998                                     &port_regs->CommonRegs.
1999                                     rxSmallQProducerIndex,
2000                                     qdev->small_buf_q_producer_index);
2001         }
2002
2003         ql_write_common_reg(qdev,
2004                             &port_regs->CommonRegs.rspQConsumerIndex,
2005                             qdev->rsp_consumer_index);
2006         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
2007
2008         if (unlikely(netif_queue_stopped(qdev->ndev))) {
2009                 if (netif_queue_stopped(qdev->ndev) &&
2010                     (atomic_read(&qdev->tx_count) > (NUM_REQ_Q_ENTRIES / 4)))
2011                         netif_wake_queue(qdev->ndev);
2012         }
2013
2014         return *tx_cleaned + *rx_cleaned;
2015 }
2016
2017 static int ql_poll(struct net_device *ndev, int *budget)
2018 {
2019         struct ql3_adapter *qdev = netdev_priv(ndev);
2020         int work_to_do = min(*budget, ndev->quota);
2021         int rx_cleaned = 0, tx_cleaned = 0;
2022
2023         if (!netif_carrier_ok(ndev))
2024                 goto quit_polling;
2025
2026         ql_tx_rx_clean(qdev, &tx_cleaned, &rx_cleaned, work_to_do);
2027         *budget -= rx_cleaned;
2028         ndev->quota -= rx_cleaned;
2029
2030         if ((!tx_cleaned && !rx_cleaned) || !netif_running(ndev)) {
2031 quit_polling:
2032                 netif_rx_complete(ndev);
2033                 ql_enable_interrupts(qdev);
2034                 return 0;
2035         }
2036         return 1;
2037 }
2038
2039 static irqreturn_t ql3xxx_isr(int irq, void *dev_id)
2040 {
2041
2042         struct net_device *ndev = dev_id;
2043         struct ql3_adapter *qdev = netdev_priv(ndev);
2044         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
2045         u32 value;
2046         int handled = 1;
2047         u32 var;
2048
2049         port_regs = qdev->mem_map_registers;
2050
2051         value =
2052             ql_read_common_reg_l(qdev, &port_regs->CommonRegs.ispControlStatus);
2053
2054         if (value & (ISP_CONTROL_FE | ISP_CONTROL_RI)) {
2055                 spin_lock(&qdev->adapter_lock);
2056                 netif_stop_queue(qdev->ndev);
2057                 netif_carrier_off(qdev->ndev);
2058                 ql_disable_interrupts(qdev);
2059                 qdev->port_link_state = LS_DOWN;
2060                 set_bit(QL_RESET_ACTIVE,&qdev->flags) ;
2061
2062                 if (value & ISP_CONTROL_FE) {
2063                         /*
2064                          * Chip Fatal Error.
2065                          */
2066                         var =
2067                             ql_read_page0_reg_l(qdev,
2068                                               &port_regs->PortFatalErrStatus);
2069                         printk(KERN_WARNING PFX
2070                                "%s: Resetting chip. PortFatalErrStatus "
2071                                "register = 0x%x\n", ndev->name, var);
2072                         set_bit(QL_RESET_START,&qdev->flags) ;
2073                 } else {
2074                         /*
2075                          * Soft Reset Requested.
2076                          */
2077                         set_bit(QL_RESET_PER_SCSI,&qdev->flags) ;
2078                         printk(KERN_ERR PFX
2079                                "%s: Another function issued a reset to the "
2080                                "chip. ISR value = %x.\n", ndev->name, value);
2081                 }
2082                 queue_delayed_work(qdev->workqueue, &qdev->reset_work, 0);
2083                 spin_unlock(&qdev->adapter_lock);
2084         } else if (value & ISP_IMR_DISABLE_CMPL_INT) {
2085                 ql_disable_interrupts(qdev);
2086                 if (likely(netif_rx_schedule_prep(ndev)))
2087                         __netif_rx_schedule(ndev);
2088                 else
2089                         ql_enable_interrupts(qdev);
2090         } else {
2091                 return IRQ_NONE;
2092         }
2093
2094         return IRQ_RETVAL(handled);
2095 }
2096
2097 /*
2098  * Get the total number of segments needed for the
2099  * given number of fragments.  This is necessary because
2100  * outbound address lists (OAL) will be used when more than
2101  * two frags are given.  Each address list has 5 addr/len
2102  * pairs.  The 5th pair in each AOL is used to  point to
2103  * the next AOL if more frags are coming.
2104  * That is why the frags:segment count  ratio is not linear.
2105  */
2106 static int ql_get_seg_count(unsigned short frags)
2107 {
2108         switch(frags) {
2109         case 0: return 1;       /* just the skb->data seg */
2110         case 1: return 2;       /* skb->data + 1 frag */
2111         case 2: return 3;       /* skb->data + 2 frags */
2112         case 3: return 5;       /* skb->data + 1 frag + 1 AOL containting 2 frags */
2113         case 4: return 6;
2114         case 5: return 7;
2115         case 6: return 8;
2116         case 7: return 10;
2117         case 8: return 11;
2118         case 9: return 12;
2119         case 10: return 13;
2120         case 11: return 15;
2121         case 12: return 16;
2122         case 13: return 17;
2123         case 14: return 18;
2124         case 15: return 20;
2125         case 16: return 21;
2126         case 17: return 22;
2127         case 18: return 23;
2128         }
2129         return -1;
2130 }
2131
2132 static void ql_hw_csum_setup(struct sk_buff *skb,
2133                              struct ob_mac_iocb_req *mac_iocb_ptr)
2134 {
2135         struct ethhdr *eth;
2136         struct iphdr *ip = NULL;
2137         u8 offset = ETH_HLEN;
2138
2139         eth = (struct ethhdr *)(skb->data);
2140
2141         if (eth->h_proto == __constant_htons(ETH_P_IP)) {
2142                 ip = (struct iphdr *)&skb->data[ETH_HLEN];
2143         } else if (eth->h_proto == htons(ETH_P_8021Q) &&
2144                    ((struct vlan_ethhdr *)skb->data)->
2145                    h_vlan_encapsulated_proto == __constant_htons(ETH_P_IP)) {
2146                 ip = (struct iphdr *)&skb->data[VLAN_ETH_HLEN];
2147                 offset = VLAN_ETH_HLEN;
2148         }
2149
2150         if (ip) {
2151                 if (ip->protocol == IPPROTO_TCP) {
2152                         mac_iocb_ptr->flags1 |= OB_3032MAC_IOCB_REQ_TC;
2153                         mac_iocb_ptr->ip_hdr_off = offset;
2154                         mac_iocb_ptr->ip_hdr_len = ip->ihl;
2155                 } else if (ip->protocol == IPPROTO_UDP) {
2156                         mac_iocb_ptr->flags1 |= OB_3032MAC_IOCB_REQ_UC;
2157                         mac_iocb_ptr->ip_hdr_off = offset;
2158                         mac_iocb_ptr->ip_hdr_len = ip->ihl;
2159                 }
2160         }
2161 }
2162
2163 /*
2164  * The difference between 3022 and 3032 sends:
2165  * 3022 only supports a simple single segment transmission.
2166  * 3032 supports checksumming and scatter/gather lists (fragments).
2167  * The 3032 supports sglists by using the 3 addr/len pairs (ALP)
2168  * in the IOCB plus a chain of outbound address lists (OAL) that
2169  * each contain 5 ALPs.  The last ALP of the IOCB (3rd) or OAL (5th)
2170  * will used to point to an OAL when more ALP entries are required.
2171  * The IOCB is always the top of the chain followed by one or more
2172  * OALs (when necessary).
2173  */
2174 static int ql3xxx_send(struct sk_buff *skb, struct net_device *ndev)
2175 {
2176         struct ql3_adapter *qdev = (struct ql3_adapter *)netdev_priv(ndev);
2177         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
2178         struct ql_tx_buf_cb *tx_cb;
2179         u32 tot_len = skb->len;
2180         struct oal *oal;
2181         struct oal_entry *oal_entry;
2182         int len;
2183         struct ob_mac_iocb_req *mac_iocb_ptr;
2184         u64 map;
2185         int seg_cnt, seg = 0;
2186         int frag_cnt = (int)skb_shinfo(skb)->nr_frags;
2187
2188         if (unlikely(atomic_read(&qdev->tx_count) < 2)) {
2189                 if (!netif_queue_stopped(ndev))
2190                         netif_stop_queue(ndev);
2191                 return NETDEV_TX_BUSY;
2192         }
2193         tx_cb = &qdev->tx_buf[qdev->req_producer_index] ;
2194         seg_cnt = tx_cb->seg_count = ql_get_seg_count((skb_shinfo(skb)->nr_frags));
2195         if(seg_cnt == -1) {
2196                 printk(KERN_ERR PFX"%s: invalid segment count!\n",__func__);
2197                 return NETDEV_TX_OK;
2198
2199         }
2200         mac_iocb_ptr = tx_cb->queue_entry;
2201         mac_iocb_ptr->opcode = qdev->mac_ob_opcode;
2202         mac_iocb_ptr->flags |= qdev->mb_bit_mask;
2203         mac_iocb_ptr->transaction_id = qdev->req_producer_index;
2204         mac_iocb_ptr->data_len = cpu_to_le16((u16) tot_len);
2205         tx_cb->skb = skb;
2206         if (skb->ip_summed == CHECKSUM_PARTIAL)
2207                 ql_hw_csum_setup(skb, mac_iocb_ptr);
2208         len = skb_headlen(skb);
2209         map = pci_map_single(qdev->pdev, skb->data, len, PCI_DMA_TODEVICE);
2210         oal_entry = (struct oal_entry *)&mac_iocb_ptr->buf_addr0_low;
2211         oal_entry->dma_lo = cpu_to_le32(LS_64BITS(map));
2212         oal_entry->dma_hi = cpu_to_le32(MS_64BITS(map));
2213         oal_entry->len = cpu_to_le32(len);
2214         pci_unmap_addr_set(&tx_cb->map[seg], mapaddr, map);
2215         pci_unmap_len_set(&tx_cb->map[seg], maplen, len);
2216         seg++;
2217
2218         if (!skb_shinfo(skb)->nr_frags) {
2219                 /* Terminate the last segment. */
2220                 oal_entry->len =
2221                     cpu_to_le32(le32_to_cpu(oal_entry->len) | OAL_LAST_ENTRY);
2222         } else {
2223                 int i;
2224                 oal = tx_cb->oal;
2225                 for (i=0; i<frag_cnt; i++,seg++) {
2226                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2227                         oal_entry++;
2228                         if ((seg == 2 && seg_cnt > 3) ||        /* Check for continuation */
2229                             (seg == 7 && seg_cnt > 8) ||        /* requirements. It's strange */
2230                             (seg == 12 && seg_cnt > 13) ||      /* but necessary. */
2231                             (seg == 17 && seg_cnt > 18)) {
2232                                 /* Continuation entry points to outbound address list. */
2233                                 map = pci_map_single(qdev->pdev, oal,
2234                                                      sizeof(struct oal),
2235                                                      PCI_DMA_TODEVICE);
2236                                 oal_entry->dma_lo = cpu_to_le32(LS_64BITS(map));
2237                                 oal_entry->dma_hi = cpu_to_le32(MS_64BITS(map));
2238                                 oal_entry->len =
2239                                     cpu_to_le32(sizeof(struct oal) |
2240                                                 OAL_CONT_ENTRY);
2241                                 pci_unmap_addr_set(&tx_cb->map[seg], mapaddr,
2242                                                    map);
2243                                 pci_unmap_len_set(&tx_cb->map[seg], maplen,
2244                                                   len);
2245                                 oal_entry = (struct oal_entry *)oal;
2246                                 oal++;
2247                                 seg++;
2248                         }
2249
2250                         map =
2251                             pci_map_page(qdev->pdev, frag->page,
2252                                          frag->page_offset, frag->size,
2253                                          PCI_DMA_TODEVICE);
2254                         oal_entry->dma_lo = cpu_to_le32(LS_64BITS(map));
2255                         oal_entry->dma_hi = cpu_to_le32(MS_64BITS(map));
2256                         oal_entry->len = cpu_to_le32(frag->size);
2257                         pci_unmap_addr_set(&tx_cb->map[seg], mapaddr, map);
2258                         pci_unmap_len_set(&tx_cb->map[seg], maplen,
2259                                           frag->size);
2260                 }
2261                 /* Terminate the last segment. */
2262                 oal_entry->len =
2263                     cpu_to_le32(le32_to_cpu(oal_entry->len) | OAL_LAST_ENTRY);
2264         }
2265         wmb();
2266         qdev->req_producer_index++;
2267         if (qdev->req_producer_index == NUM_REQ_Q_ENTRIES)
2268                 qdev->req_producer_index = 0;
2269         wmb();
2270         ql_write_common_reg_l(qdev,
2271                             &port_regs->CommonRegs.reqQProducerIndex,
2272                             qdev->req_producer_index);
2273
2274         ndev->trans_start = jiffies;
2275         if (netif_msg_tx_queued(qdev))
2276                 printk(KERN_DEBUG PFX "%s: tx queued, slot %d, len %d\n",
2277                        ndev->name, qdev->req_producer_index, skb->len);
2278
2279         atomic_dec(&qdev->tx_count);
2280         return NETDEV_TX_OK;
2281 }
2282
2283 static int ql_alloc_net_req_rsp_queues(struct ql3_adapter *qdev)
2284 {
2285         qdev->req_q_size =
2286             (u32) (NUM_REQ_Q_ENTRIES * sizeof(struct ob_mac_iocb_req));
2287
2288         qdev->req_q_virt_addr =
2289             pci_alloc_consistent(qdev->pdev,
2290                                  (size_t) qdev->req_q_size,
2291                                  &qdev->req_q_phy_addr);
2292
2293         if ((qdev->req_q_virt_addr == NULL) ||
2294             LS_64BITS(qdev->req_q_phy_addr) & (qdev->req_q_size - 1)) {
2295                 printk(KERN_ERR PFX "%s: reqQ failed.\n",
2296                        qdev->ndev->name);
2297                 return -ENOMEM;
2298         }
2299
2300         qdev->rsp_q_size = NUM_RSP_Q_ENTRIES * sizeof(struct net_rsp_iocb);
2301
2302         qdev->rsp_q_virt_addr =
2303             pci_alloc_consistent(qdev->pdev,
2304                                  (size_t) qdev->rsp_q_size,
2305                                  &qdev->rsp_q_phy_addr);
2306
2307         if ((qdev->rsp_q_virt_addr == NULL) ||
2308             LS_64BITS(qdev->rsp_q_phy_addr) & (qdev->rsp_q_size - 1)) {
2309                 printk(KERN_ERR PFX
2310                        "%s: rspQ allocation failed\n",
2311                        qdev->ndev->name);
2312                 pci_free_consistent(qdev->pdev, (size_t) qdev->req_q_size,
2313                                     qdev->req_q_virt_addr,
2314                                     qdev->req_q_phy_addr);
2315                 return -ENOMEM;
2316         }
2317
2318         set_bit(QL_ALLOC_REQ_RSP_Q_DONE,&qdev->flags);
2319
2320         return 0;
2321 }
2322
2323 static void ql_free_net_req_rsp_queues(struct ql3_adapter *qdev)
2324 {
2325         if (!test_bit(QL_ALLOC_REQ_RSP_Q_DONE,&qdev->flags)) {
2326                 printk(KERN_INFO PFX
2327                        "%s: Already done.\n", qdev->ndev->name);
2328                 return;
2329         }
2330
2331         pci_free_consistent(qdev->pdev,
2332                             qdev->req_q_size,
2333                             qdev->req_q_virt_addr, qdev->req_q_phy_addr);
2334
2335         qdev->req_q_virt_addr = NULL;
2336
2337         pci_free_consistent(qdev->pdev,
2338                             qdev->rsp_q_size,
2339                             qdev->rsp_q_virt_addr, qdev->rsp_q_phy_addr);
2340
2341         qdev->rsp_q_virt_addr = NULL;
2342
2343         clear_bit(QL_ALLOC_REQ_RSP_Q_DONE,&qdev->flags);
2344 }
2345
2346 static int ql_alloc_buffer_queues(struct ql3_adapter *qdev)
2347 {
2348         /* Create Large Buffer Queue */
2349         qdev->lrg_buf_q_size =
2350             qdev->num_lbufq_entries * sizeof(struct lrg_buf_q_entry);
2351         if (qdev->lrg_buf_q_size < PAGE_SIZE)
2352                 qdev->lrg_buf_q_alloc_size = PAGE_SIZE;
2353         else
2354                 qdev->lrg_buf_q_alloc_size = qdev->lrg_buf_q_size * 2;
2355
2356         qdev->lrg_buf = kmalloc(qdev->num_large_buffers * sizeof(struct ql_rcv_buf_cb),GFP_KERNEL);
2357         if (qdev->lrg_buf == NULL) {
2358                 printk(KERN_ERR PFX
2359                        "%s: qdev->lrg_buf alloc failed.\n", qdev->ndev->name);
2360                 return -ENOMEM;
2361         }
2362
2363         qdev->lrg_buf_q_alloc_virt_addr =
2364             pci_alloc_consistent(qdev->pdev,
2365                                  qdev->lrg_buf_q_alloc_size,
2366                                  &qdev->lrg_buf_q_alloc_phy_addr);
2367
2368         if (qdev->lrg_buf_q_alloc_virt_addr == NULL) {
2369                 printk(KERN_ERR PFX
2370                        "%s: lBufQ failed\n", qdev->ndev->name);
2371                 return -ENOMEM;
2372         }
2373         qdev->lrg_buf_q_virt_addr = qdev->lrg_buf_q_alloc_virt_addr;
2374         qdev->lrg_buf_q_phy_addr = qdev->lrg_buf_q_alloc_phy_addr;
2375
2376         /* Create Small Buffer Queue */
2377         qdev->small_buf_q_size =
2378             NUM_SBUFQ_ENTRIES * sizeof(struct lrg_buf_q_entry);
2379         if (qdev->small_buf_q_size < PAGE_SIZE)
2380                 qdev->small_buf_q_alloc_size = PAGE_SIZE;
2381         else
2382                 qdev->small_buf_q_alloc_size = qdev->small_buf_q_size * 2;
2383
2384         qdev->small_buf_q_alloc_virt_addr =
2385             pci_alloc_consistent(qdev->pdev,
2386                                  qdev->small_buf_q_alloc_size,
2387                                  &qdev->small_buf_q_alloc_phy_addr);
2388
2389         if (qdev->small_buf_q_alloc_virt_addr == NULL) {
2390                 printk(KERN_ERR PFX
2391                        "%s: Small Buffer Queue allocation failed.\n",
2392                        qdev->ndev->name);
2393                 pci_free_consistent(qdev->pdev, qdev->lrg_buf_q_alloc_size,
2394                                     qdev->lrg_buf_q_alloc_virt_addr,
2395                                     qdev->lrg_buf_q_alloc_phy_addr);
2396                 return -ENOMEM;
2397         }
2398
2399         qdev->small_buf_q_virt_addr = qdev->small_buf_q_alloc_virt_addr;
2400         qdev->small_buf_q_phy_addr = qdev->small_buf_q_alloc_phy_addr;
2401         set_bit(QL_ALLOC_BUFQS_DONE,&qdev->flags);
2402         return 0;
2403 }
2404
2405 static void ql_free_buffer_queues(struct ql3_adapter *qdev)
2406 {
2407         if (!test_bit(QL_ALLOC_BUFQS_DONE,&qdev->flags)) {
2408                 printk(KERN_INFO PFX
2409                        "%s: Already done.\n", qdev->ndev->name);
2410                 return;
2411         }
2412         if(qdev->lrg_buf) kfree(qdev->lrg_buf);
2413
2414         pci_free_consistent(qdev->pdev,
2415                             qdev->lrg_buf_q_alloc_size,
2416                             qdev->lrg_buf_q_alloc_virt_addr,
2417                             qdev->lrg_buf_q_alloc_phy_addr);
2418
2419         qdev->lrg_buf_q_virt_addr = NULL;
2420
2421         pci_free_consistent(qdev->pdev,
2422                             qdev->small_buf_q_alloc_size,
2423                             qdev->small_buf_q_alloc_virt_addr,
2424                             qdev->small_buf_q_alloc_phy_addr);
2425
2426         qdev->small_buf_q_virt_addr = NULL;
2427
2428         clear_bit(QL_ALLOC_BUFQS_DONE,&qdev->flags);
2429 }
2430
2431 static int ql_alloc_small_buffers(struct ql3_adapter *qdev)
2432 {
2433         int i;
2434         struct bufq_addr_element *small_buf_q_entry;
2435
2436         /* Currently we allocate on one of memory and use it for smallbuffers */
2437         qdev->small_buf_total_size =
2438             (QL_ADDR_ELE_PER_BUFQ_ENTRY * NUM_SBUFQ_ENTRIES *
2439              QL_SMALL_BUFFER_SIZE);
2440
2441         qdev->small_buf_virt_addr =
2442             pci_alloc_consistent(qdev->pdev,
2443                                  qdev->small_buf_total_size,
2444                                  &qdev->small_buf_phy_addr);
2445
2446         if (qdev->small_buf_virt_addr == NULL) {
2447                 printk(KERN_ERR PFX
2448                        "%s: Failed to get small buffer memory.\n",
2449                        qdev->ndev->name);
2450                 return -ENOMEM;
2451         }
2452
2453         qdev->small_buf_phy_addr_low = LS_64BITS(qdev->small_buf_phy_addr);
2454         qdev->small_buf_phy_addr_high = MS_64BITS(qdev->small_buf_phy_addr);
2455
2456         small_buf_q_entry = qdev->small_buf_q_virt_addr;
2457
2458         qdev->last_rsp_offset = qdev->small_buf_phy_addr_low;
2459
2460         /* Initialize the small buffer queue. */
2461         for (i = 0; i < (QL_ADDR_ELE_PER_BUFQ_ENTRY * NUM_SBUFQ_ENTRIES); i++) {
2462                 small_buf_q_entry->addr_high =
2463                     cpu_to_le32(qdev->small_buf_phy_addr_high);
2464                 small_buf_q_entry->addr_low =
2465                     cpu_to_le32(qdev->small_buf_phy_addr_low +
2466                                 (i * QL_SMALL_BUFFER_SIZE));
2467                 small_buf_q_entry++;
2468         }
2469         qdev->small_buf_index = 0;
2470         set_bit(QL_ALLOC_SMALL_BUF_DONE,&qdev->flags);
2471         return 0;
2472 }
2473
2474 static void ql_free_small_buffers(struct ql3_adapter *qdev)
2475 {
2476         if (!test_bit(QL_ALLOC_SMALL_BUF_DONE,&qdev->flags)) {
2477                 printk(KERN_INFO PFX
2478                        "%s: Already done.\n", qdev->ndev->name);
2479                 return;
2480         }
2481         if (qdev->small_buf_virt_addr != NULL) {
2482                 pci_free_consistent(qdev->pdev,
2483                                     qdev->small_buf_total_size,
2484                                     qdev->small_buf_virt_addr,
2485                                     qdev->small_buf_phy_addr);
2486
2487                 qdev->small_buf_virt_addr = NULL;
2488         }
2489 }
2490
2491 static void ql_free_large_buffers(struct ql3_adapter *qdev)
2492 {
2493         int i = 0;
2494         struct ql_rcv_buf_cb *lrg_buf_cb;
2495
2496         for (i = 0; i < qdev->num_large_buffers; i++) {
2497                 lrg_buf_cb = &qdev->lrg_buf[i];
2498                 if (lrg_buf_cb->skb) {
2499                         dev_kfree_skb(lrg_buf_cb->skb);
2500                         pci_unmap_single(qdev->pdev,
2501                                          pci_unmap_addr(lrg_buf_cb, mapaddr),
2502                                          pci_unmap_len(lrg_buf_cb, maplen),
2503                                          PCI_DMA_FROMDEVICE);
2504                         memset(lrg_buf_cb, 0, sizeof(struct ql_rcv_buf_cb));
2505                 } else {
2506                         break;
2507                 }
2508         }
2509 }
2510
2511 static void ql_init_large_buffers(struct ql3_adapter *qdev)
2512 {
2513         int i;
2514         struct ql_rcv_buf_cb *lrg_buf_cb;
2515         struct bufq_addr_element *buf_addr_ele = qdev->lrg_buf_q_virt_addr;
2516
2517         for (i = 0; i < qdev->num_large_buffers; i++) {
2518                 lrg_buf_cb = &qdev->lrg_buf[i];
2519                 buf_addr_ele->addr_high = lrg_buf_cb->buf_phy_addr_high;
2520                 buf_addr_ele->addr_low = lrg_buf_cb->buf_phy_addr_low;
2521                 buf_addr_ele++;
2522         }
2523         qdev->lrg_buf_index = 0;
2524         qdev->lrg_buf_skb_check = 0;
2525 }
2526
2527 static int ql_alloc_large_buffers(struct ql3_adapter *qdev)
2528 {
2529         int i;
2530         struct ql_rcv_buf_cb *lrg_buf_cb;
2531         struct sk_buff *skb;
2532         u64 map;
2533
2534         for (i = 0; i < qdev->num_large_buffers; i++) {
2535                 skb = netdev_alloc_skb(qdev->ndev,
2536                                        qdev->lrg_buffer_len);
2537                 if (unlikely(!skb)) {
2538                         /* Better luck next round */
2539                         printk(KERN_ERR PFX
2540                                "%s: large buff alloc failed, "
2541                                "for %d bytes at index %d.\n",
2542                                qdev->ndev->name,
2543                                qdev->lrg_buffer_len * 2, i);
2544                         ql_free_large_buffers(qdev);
2545                         return -ENOMEM;
2546                 } else {
2547
2548                         lrg_buf_cb = &qdev->lrg_buf[i];
2549                         memset(lrg_buf_cb, 0, sizeof(struct ql_rcv_buf_cb));
2550                         lrg_buf_cb->index = i;
2551                         lrg_buf_cb->skb = skb;
2552                         /*
2553                          * We save some space to copy the ethhdr from first
2554                          * buffer
2555                          */
2556                         skb_reserve(skb, QL_HEADER_SPACE);
2557                         map = pci_map_single(qdev->pdev,
2558                                              skb->data,
2559                                              qdev->lrg_buffer_len -
2560                                              QL_HEADER_SPACE,
2561                                              PCI_DMA_FROMDEVICE);
2562                         pci_unmap_addr_set(lrg_buf_cb, mapaddr, map);
2563                         pci_unmap_len_set(lrg_buf_cb, maplen,
2564                                           qdev->lrg_buffer_len -
2565                                           QL_HEADER_SPACE);
2566                         lrg_buf_cb->buf_phy_addr_low =
2567                             cpu_to_le32(LS_64BITS(map));
2568                         lrg_buf_cb->buf_phy_addr_high =
2569                             cpu_to_le32(MS_64BITS(map));
2570                 }
2571         }
2572         return 0;
2573 }
2574
2575 static void ql_free_send_free_list(struct ql3_adapter *qdev)
2576 {
2577         struct ql_tx_buf_cb *tx_cb;
2578         int i;
2579
2580         tx_cb = &qdev->tx_buf[0];
2581         for (i = 0; i < NUM_REQ_Q_ENTRIES; i++) {
2582                 if (tx_cb->oal) {
2583                         kfree(tx_cb->oal);
2584                         tx_cb->oal = NULL;
2585                 }
2586                 tx_cb++;
2587         }
2588 }
2589
2590 static int ql_create_send_free_list(struct ql3_adapter *qdev)
2591 {
2592         struct ql_tx_buf_cb *tx_cb;
2593         int i;
2594         struct ob_mac_iocb_req *req_q_curr =
2595                                         qdev->req_q_virt_addr;
2596
2597         /* Create free list of transmit buffers */
2598         for (i = 0; i < NUM_REQ_Q_ENTRIES; i++) {
2599
2600                 tx_cb = &qdev->tx_buf[i];
2601                 tx_cb->skb = NULL;
2602                 tx_cb->queue_entry = req_q_curr;
2603                 req_q_curr++;
2604                 tx_cb->oal = kmalloc(512, GFP_KERNEL);
2605                 if (tx_cb->oal == NULL)
2606                         return -1;
2607         }
2608         return 0;
2609 }
2610
2611 static int ql_alloc_mem_resources(struct ql3_adapter *qdev)
2612 {
2613         if (qdev->ndev->mtu == NORMAL_MTU_SIZE) {
2614                 qdev->num_lbufq_entries = NUM_LBUFQ_ENTRIES;
2615                 qdev->lrg_buffer_len = NORMAL_MTU_SIZE;
2616         }
2617         else if (qdev->ndev->mtu == JUMBO_MTU_SIZE) {
2618                 /*
2619                  * Bigger buffers, so less of them.
2620                  */
2621                 qdev->num_lbufq_entries = JUMBO_NUM_LBUFQ_ENTRIES;
2622                 qdev->lrg_buffer_len = JUMBO_MTU_SIZE;
2623         } else {
2624                 printk(KERN_ERR PFX
2625                        "%s: Invalid mtu size.  Only 1500 and 9000 are accepted.\n",
2626                        qdev->ndev->name);
2627                 return -ENOMEM;
2628         }
2629         qdev->num_large_buffers = qdev->num_lbufq_entries * QL_ADDR_ELE_PER_BUFQ_ENTRY;
2630         qdev->lrg_buffer_len += VLAN_ETH_HLEN + VLAN_ID_LEN + QL_HEADER_SPACE;
2631         qdev->max_frame_size =
2632             (qdev->lrg_buffer_len - QL_HEADER_SPACE) + ETHERNET_CRC_SIZE;
2633
2634         /*
2635          * First allocate a page of shared memory and use it for shadow
2636          * locations of Network Request Queue Consumer Address Register and
2637          * Network Completion Queue Producer Index Register
2638          */
2639         qdev->shadow_reg_virt_addr =
2640             pci_alloc_consistent(qdev->pdev,
2641                                  PAGE_SIZE, &qdev->shadow_reg_phy_addr);
2642
2643         if (qdev->shadow_reg_virt_addr != NULL) {
2644                 qdev->preq_consumer_index = (u16 *) qdev->shadow_reg_virt_addr;
2645                 qdev->req_consumer_index_phy_addr_high =
2646                     MS_64BITS(qdev->shadow_reg_phy_addr);
2647                 qdev->req_consumer_index_phy_addr_low =
2648                     LS_64BITS(qdev->shadow_reg_phy_addr);
2649
2650                 qdev->prsp_producer_index =
2651                     (u32 *) (((u8 *) qdev->preq_consumer_index) + 8);
2652                 qdev->rsp_producer_index_phy_addr_high =
2653                     qdev->req_consumer_index_phy_addr_high;
2654                 qdev->rsp_producer_index_phy_addr_low =
2655                     qdev->req_consumer_index_phy_addr_low + 8;
2656         } else {
2657                 printk(KERN_ERR PFX
2658                        "%s: shadowReg Alloc failed.\n", qdev->ndev->name);
2659                 return -ENOMEM;
2660         }
2661
2662         if (ql_alloc_net_req_rsp_queues(qdev) != 0) {
2663                 printk(KERN_ERR PFX
2664                        "%s: ql_alloc_net_req_rsp_queues failed.\n",
2665                        qdev->ndev->name);
2666                 goto err_req_rsp;
2667         }
2668
2669         if (ql_alloc_buffer_queues(qdev) != 0) {
2670                 printk(KERN_ERR PFX
2671                        "%s: ql_alloc_buffer_queues failed.\n",
2672                        qdev->ndev->name);
2673                 goto err_buffer_queues;
2674         }
2675
2676         if (ql_alloc_small_buffers(qdev) != 0) {
2677                 printk(KERN_ERR PFX
2678                        "%s: ql_alloc_small_buffers failed\n", qdev->ndev->name);
2679                 goto err_small_buffers;
2680         }
2681
2682         if (ql_alloc_large_buffers(qdev) != 0) {
2683                 printk(KERN_ERR PFX
2684                        "%s: ql_alloc_large_buffers failed\n", qdev->ndev->name);
2685                 goto err_small_buffers;
2686         }
2687
2688         /* Initialize the large buffer queue. */
2689         ql_init_large_buffers(qdev);
2690         if (ql_create_send_free_list(qdev))
2691                 goto err_free_list;
2692
2693         qdev->rsp_current = qdev->rsp_q_virt_addr;
2694
2695         return 0;
2696 err_free_list:
2697         ql_free_send_free_list(qdev);
2698 err_small_buffers:
2699         ql_free_buffer_queues(qdev);
2700 err_buffer_queues:
2701         ql_free_net_req_rsp_queues(qdev);
2702 err_req_rsp:
2703         pci_free_consistent(qdev->pdev,
2704                             PAGE_SIZE,
2705                             qdev->shadow_reg_virt_addr,
2706                             qdev->shadow_reg_phy_addr);
2707
2708         return -ENOMEM;
2709 }
2710
2711 static void ql_free_mem_resources(struct ql3_adapter *qdev)
2712 {
2713         ql_free_send_free_list(qdev);
2714         ql_free_large_buffers(qdev);
2715         ql_free_small_buffers(qdev);
2716         ql_free_buffer_queues(qdev);
2717         ql_free_net_req_rsp_queues(qdev);
2718         if (qdev->shadow_reg_virt_addr != NULL) {
2719                 pci_free_consistent(qdev->pdev,
2720                                     PAGE_SIZE,
2721                                     qdev->shadow_reg_virt_addr,
2722                                     qdev->shadow_reg_phy_addr);
2723                 qdev->shadow_reg_virt_addr = NULL;
2724         }
2725 }
2726
2727 static int ql_init_misc_registers(struct ql3_adapter *qdev)
2728 {
2729         struct ql3xxx_local_ram_registers __iomem *local_ram =
2730             (void __iomem *)qdev->mem_map_registers;
2731
2732         if(ql_sem_spinlock(qdev, QL_DDR_RAM_SEM_MASK,
2733                         (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
2734                          2) << 4))
2735                 return -1;
2736
2737         ql_write_page2_reg(qdev,
2738                            &local_ram->bufletSize, qdev->nvram_data.bufletSize);
2739
2740         ql_write_page2_reg(qdev,
2741                            &local_ram->maxBufletCount,
2742                            qdev->nvram_data.bufletCount);
2743
2744         ql_write_page2_reg(qdev,
2745                            &local_ram->freeBufletThresholdLow,
2746                            (qdev->nvram_data.tcpWindowThreshold25 << 16) |
2747                            (qdev->nvram_data.tcpWindowThreshold0));
2748
2749         ql_write_page2_reg(qdev,
2750                            &local_ram->freeBufletThresholdHigh,
2751                            qdev->nvram_data.tcpWindowThreshold50);
2752
2753         ql_write_page2_reg(qdev,
2754                            &local_ram->ipHashTableBase,
2755                            (qdev->nvram_data.ipHashTableBaseHi << 16) |
2756                            qdev->nvram_data.ipHashTableBaseLo);
2757         ql_write_page2_reg(qdev,
2758                            &local_ram->ipHashTableCount,
2759                            qdev->nvram_data.ipHashTableSize);
2760         ql_write_page2_reg(qdev,
2761                            &local_ram->tcpHashTableBase,
2762                            (qdev->nvram_data.tcpHashTableBaseHi << 16) |
2763                            qdev->nvram_data.tcpHashTableBaseLo);
2764         ql_write_page2_reg(qdev,
2765                            &local_ram->tcpHashTableCount,
2766                            qdev->nvram_data.tcpHashTableSize);
2767         ql_write_page2_reg(qdev,
2768                            &local_ram->ncbBase,
2769                            (qdev->nvram_data.ncbTableBaseHi << 16) |
2770                            qdev->nvram_data.ncbTableBaseLo);
2771         ql_write_page2_reg(qdev,
2772                            &local_ram->maxNcbCount,
2773                            qdev->nvram_data.ncbTableSize);
2774         ql_write_page2_reg(qdev,
2775                            &local_ram->drbBase,
2776                            (qdev->nvram_data.drbTableBaseHi << 16) |
2777                            qdev->nvram_data.drbTableBaseLo);
2778         ql_write_page2_reg(qdev,
2779                            &local_ram->maxDrbCount,
2780                            qdev->nvram_data.drbTableSize);
2781         ql_sem_unlock(qdev, QL_DDR_RAM_SEM_MASK);
2782         return 0;
2783 }
2784
2785 static int ql_adapter_initialize(struct ql3_adapter *qdev)
2786 {
2787         u32 value;
2788         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
2789         struct ql3xxx_host_memory_registers __iomem *hmem_regs =
2790                                                 (void __iomem *)port_regs;
2791         u32 delay = 10;
2792         int status = 0;
2793
2794         if(ql_mii_setup(qdev))
2795                 return -1;
2796
2797         /* Bring out PHY out of reset */
2798         ql_write_common_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
2799                             (ISP_SERIAL_PORT_IF_WE |
2800                              (ISP_SERIAL_PORT_IF_WE << 16)));
2801
2802         qdev->port_link_state = LS_DOWN;
2803         netif_carrier_off(qdev->ndev);
2804
2805         /* V2 chip fix for ARS-39168. */
2806         ql_write_common_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
2807                             (ISP_SERIAL_PORT_IF_SDE |
2808                              (ISP_SERIAL_PORT_IF_SDE << 16)));
2809
2810         /* Request Queue Registers */
2811         *((u32 *) (qdev->preq_consumer_index)) = 0;
2812         atomic_set(&qdev->tx_count,NUM_REQ_Q_ENTRIES);
2813         qdev->req_producer_index = 0;
2814
2815         ql_write_page1_reg(qdev,
2816                            &hmem_regs->reqConsumerIndexAddrHigh,
2817                            qdev->req_consumer_index_phy_addr_high);
2818         ql_write_page1_reg(qdev,
2819                            &hmem_regs->reqConsumerIndexAddrLow,
2820                            qdev->req_consumer_index_phy_addr_low);
2821
2822         ql_write_page1_reg(qdev,
2823                            &hmem_regs->reqBaseAddrHigh,
2824                            MS_64BITS(qdev->req_q_phy_addr));
2825         ql_write_page1_reg(qdev,
2826                            &hmem_regs->reqBaseAddrLow,
2827                            LS_64BITS(qdev->req_q_phy_addr));
2828         ql_write_page1_reg(qdev, &hmem_regs->reqLength, NUM_REQ_Q_ENTRIES);
2829
2830         /* Response Queue Registers */
2831         *((u16 *) (qdev->prsp_producer_index)) = 0;
2832         qdev->rsp_consumer_index = 0;
2833         qdev->rsp_current = qdev->rsp_q_virt_addr;
2834
2835         ql_write_page1_reg(qdev,
2836                            &hmem_regs->rspProducerIndexAddrHigh,
2837                            qdev->rsp_producer_index_phy_addr_high);
2838
2839         ql_write_page1_reg(qdev,
2840                            &hmem_regs->rspProducerIndexAddrLow,
2841                            qdev->rsp_producer_index_phy_addr_low);
2842
2843         ql_write_page1_reg(qdev,
2844                            &hmem_regs->rspBaseAddrHigh,
2845                            MS_64BITS(qdev->rsp_q_phy_addr));
2846
2847         ql_write_page1_reg(qdev,
2848                            &hmem_regs->rspBaseAddrLow,
2849                            LS_64BITS(qdev->rsp_q_phy_addr));
2850
2851         ql_write_page1_reg(qdev, &hmem_regs->rspLength, NUM_RSP_Q_ENTRIES);
2852
2853         /* Large Buffer Queue */
2854         ql_write_page1_reg(qdev,
2855                            &hmem_regs->rxLargeQBaseAddrHigh,
2856                            MS_64BITS(qdev->lrg_buf_q_phy_addr));
2857
2858         ql_write_page1_reg(qdev,
2859                            &hmem_regs->rxLargeQBaseAddrLow,
2860                            LS_64BITS(qdev->lrg_buf_q_phy_addr));
2861
2862         ql_write_page1_reg(qdev, &hmem_regs->rxLargeQLength, qdev->num_lbufq_entries);
2863
2864         ql_write_page1_reg(qdev,
2865                            &hmem_regs->rxLargeBufferLength,
2866                            qdev->lrg_buffer_len);
2867
2868         /* Small Buffer Queue */
2869         ql_write_page1_reg(qdev,
2870                            &hmem_regs->rxSmallQBaseAddrHigh,
2871                            MS_64BITS(qdev->small_buf_q_phy_addr));
2872
2873         ql_write_page1_reg(qdev,
2874                            &hmem_regs->rxSmallQBaseAddrLow,
2875                            LS_64BITS(qdev->small_buf_q_phy_addr));
2876
2877         ql_write_page1_reg(qdev, &hmem_regs->rxSmallQLength, NUM_SBUFQ_ENTRIES);
2878         ql_write_page1_reg(qdev,
2879                            &hmem_regs->rxSmallBufferLength,
2880                            QL_SMALL_BUFFER_SIZE);
2881
2882         qdev->small_buf_q_producer_index = NUM_SBUFQ_ENTRIES - 1;
2883         qdev->small_buf_release_cnt = 8;
2884         qdev->lrg_buf_q_producer_index = qdev->num_lbufq_entries - 1;
2885         qdev->lrg_buf_release_cnt = 8;
2886         qdev->lrg_buf_next_free =
2887             (struct bufq_addr_element *)qdev->lrg_buf_q_virt_addr;
2888         qdev->small_buf_index = 0;
2889         qdev->lrg_buf_index = 0;
2890         qdev->lrg_buf_free_count = 0;
2891         qdev->lrg_buf_free_head = NULL;
2892         qdev->lrg_buf_free_tail = NULL;
2893
2894         ql_write_common_reg(qdev,
2895                             &port_regs->CommonRegs.
2896                             rxSmallQProducerIndex,
2897                             qdev->small_buf_q_producer_index);
2898         ql_write_common_reg(qdev,
2899                             &port_regs->CommonRegs.
2900                             rxLargeQProducerIndex,
2901                             qdev->lrg_buf_q_producer_index);
2902
2903         /*
2904          * Find out if the chip has already been initialized.  If it has, then
2905          * we skip some of the initialization.
2906          */
2907         clear_bit(QL_LINK_MASTER, &qdev->flags);
2908         value = ql_read_page0_reg(qdev, &port_regs->portStatus);
2909         if ((value & PORT_STATUS_IC) == 0) {
2910
2911                 /* Chip has not been configured yet, so let it rip. */
2912                 if(ql_init_misc_registers(qdev)) {
2913                         status = -1;
2914                         goto out;
2915                 }
2916
2917                 if (qdev->mac_index)
2918                         ql_write_page0_reg(qdev,
2919                                            &port_regs->mac1MaxFrameLengthReg,
2920                                            qdev->max_frame_size);
2921                 else
2922                         ql_write_page0_reg(qdev,
2923                                            &port_regs->mac0MaxFrameLengthReg,
2924                                            qdev->max_frame_size);
2925
2926                 value = qdev->nvram_data.tcpMaxWindowSize;
2927                 ql_write_page0_reg(qdev, &port_regs->tcpMaxWindow, value);
2928
2929                 value = (0xFFFF << 16) | qdev->nvram_data.extHwConfig;
2930
2931                 if(ql_sem_spinlock(qdev, QL_FLASH_SEM_MASK,
2932                                 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index)
2933                                  * 2) << 13)) {
2934                         status = -1;
2935                         goto out;
2936                 }
2937                 ql_write_page0_reg(qdev, &port_regs->ExternalHWConfig, value);
2938                 ql_write_page0_reg(qdev, &port_regs->InternalChipConfig,
2939                                    (((INTERNAL_CHIP_SD | INTERNAL_CHIP_WE) <<
2940                                      16) | (INTERNAL_CHIP_SD |
2941                                             INTERNAL_CHIP_WE)));
2942                 ql_sem_unlock(qdev, QL_FLASH_SEM_MASK);
2943         }
2944
2945
2946         if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
2947                         (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
2948                          2) << 7)) {
2949                 status = -1;
2950                 goto out;
2951         }
2952
2953         ql_init_scan_mode(qdev);
2954         ql_get_phy_owner(qdev);
2955
2956         /* Load the MAC Configuration */
2957
2958         /* Program lower 32 bits of the MAC address */
2959         ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
2960                            (MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16));
2961         ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
2962                            ((qdev->ndev->dev_addr[2] << 24)
2963                             | (qdev->ndev->dev_addr[3] << 16)
2964                             | (qdev->ndev->dev_addr[4] << 8)
2965                             | qdev->ndev->dev_addr[5]));
2966
2967         /* Program top 16 bits of the MAC address */
2968         ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
2969                            ((MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16) | 1));
2970         ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
2971                            ((qdev->ndev->dev_addr[0] << 8)
2972                             | qdev->ndev->dev_addr[1]));
2973
2974         /* Enable Primary MAC */
2975         ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
2976                            ((MAC_ADDR_INDIRECT_PTR_REG_PE << 16) |
2977                             MAC_ADDR_INDIRECT_PTR_REG_PE));
2978
2979         /* Clear Primary and Secondary IP addresses */
2980         ql_write_page0_reg(qdev, &port_regs->ipAddrIndexReg,
2981                            ((IP_ADDR_INDEX_REG_MASK << 16) |
2982                             (qdev->mac_index << 2)));
2983         ql_write_page0_reg(qdev, &port_regs->ipAddrDataReg, 0);
2984
2985         ql_write_page0_reg(qdev, &port_regs->ipAddrIndexReg,
2986                            ((IP_ADDR_INDEX_REG_MASK << 16) |
2987                             ((qdev->mac_index << 2) + 1)));
2988         ql_write_page0_reg(qdev, &port_regs->ipAddrDataReg, 0);
2989
2990         ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
2991
2992         /* Indicate Configuration Complete */
2993         ql_write_page0_reg(qdev,
2994                            &port_regs->portControl,
2995                            ((PORT_CONTROL_CC << 16) | PORT_CONTROL_CC));
2996
2997         do {
2998                 value = ql_read_page0_reg(qdev, &port_regs->portStatus);
2999                 if (value & PORT_STATUS_IC)
3000                         break;
3001                 msleep(500);
3002         } while (--delay);
3003
3004         if (delay == 0) {
3005                 printk(KERN_ERR PFX
3006                        "%s: Hw Initialization timeout.\n", qdev->ndev->name);
3007                 status = -1;
3008                 goto out;
3009         }
3010
3011         /* Enable Ethernet Function */
3012         if (qdev->device_id == QL3032_DEVICE_ID) {
3013                 value =
3014                     (QL3032_PORT_CONTROL_EF | QL3032_PORT_CONTROL_KIE |
3015                      QL3032_PORT_CONTROL_EIv6 | QL3032_PORT_CONTROL_EIv4);
3016                 ql_write_page0_reg(qdev, &port_regs->functionControl,
3017                                    ((value << 16) | value));
3018         } else {
3019                 value =
3020                     (PORT_CONTROL_EF | PORT_CONTROL_ET | PORT_CONTROL_EI |
3021                      PORT_CONTROL_HH);
3022                 ql_write_page0_reg(qdev, &port_regs->portControl,
3023                                    ((value << 16) | value));
3024         }
3025
3026
3027 out:
3028         return status;
3029 }
3030
3031 /*
3032  * Caller holds hw_lock.
3033  */
3034 static int ql_adapter_reset(struct ql3_adapter *qdev)
3035 {
3036         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
3037         int status = 0;
3038         u16 value;
3039         int max_wait_time;
3040
3041         set_bit(QL_RESET_ACTIVE, &qdev->flags);
3042         clear_bit(QL_RESET_DONE, &qdev->flags);
3043
3044         /*
3045          * Issue soft reset to chip.
3046          */
3047         printk(KERN_DEBUG PFX
3048                "%s: Issue soft reset to chip.\n",
3049                qdev->ndev->name);
3050         ql_write_common_reg(qdev,
3051                             &port_regs->CommonRegs.ispControlStatus,
3052                             ((ISP_CONTROL_SR << 16) | ISP_CONTROL_SR));
3053
3054         /* Wait 3 seconds for reset to complete. */
3055         printk(KERN_DEBUG PFX
3056                "%s: Wait 10 milliseconds for reset to complete.\n",
3057                qdev->ndev->name);
3058
3059         /* Wait until the firmware tells us the Soft Reset is done */
3060         max_wait_time = 5;
3061         do {
3062                 value =
3063                     ql_read_common_reg(qdev,
3064                                        &port_regs->CommonRegs.ispControlStatus);
3065                 if ((value & ISP_CONTROL_SR) == 0)
3066                         break;
3067
3068                 ssleep(1);
3069         } while ((--max_wait_time));
3070
3071         /*
3072          * Also, make sure that the Network Reset Interrupt bit has been
3073          * cleared after the soft reset has taken place.
3074          */
3075         value =
3076             ql_read_common_reg(qdev, &port_regs->CommonRegs.ispControlStatus);
3077         if (value & ISP_CONTROL_RI) {
3078                 printk(KERN_DEBUG PFX
3079                        "ql_adapter_reset: clearing RI after reset.\n");
3080                 ql_write_common_reg(qdev,
3081                                     &port_regs->CommonRegs.
3082                                     ispControlStatus,
3083                                     ((ISP_CONTROL_RI << 16) | ISP_CONTROL_RI));
3084         }
3085
3086         if (max_wait_time == 0) {
3087                 /* Issue Force Soft Reset */
3088                 ql_write_common_reg(qdev,
3089                                     &port_regs->CommonRegs.
3090                                     ispControlStatus,
3091                                     ((ISP_CONTROL_FSR << 16) |
3092                                      ISP_CONTROL_FSR));
3093                 /*
3094                  * Wait until the firmware tells us the Force Soft Reset is
3095                  * done
3096                  */
3097                 max_wait_time = 5;
3098                 do {
3099                         value =
3100                             ql_read_common_reg(qdev,
3101                                                &port_regs->CommonRegs.
3102                                                ispControlStatus);
3103                         if ((value & ISP_CONTROL_FSR) == 0) {
3104                                 break;
3105                         }
3106                         ssleep(1);
3107                 } while ((--max_wait_time));
3108         }
3109         if (max_wait_time == 0)
3110                 status = 1;
3111
3112         clear_bit(QL_RESET_ACTIVE, &qdev->flags);
3113         set_bit(QL_RESET_DONE, &qdev->flags);
3114         return status;
3115 }
3116
3117 static void ql_set_mac_info(struct ql3_adapter *qdev)
3118 {
3119         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
3120         u32 value, port_status;
3121         u8 func_number;
3122
3123         /* Get the function number */
3124         value =
3125             ql_read_common_reg_l(qdev, &port_regs->CommonRegs.ispControlStatus);
3126         func_number = (u8) ((value >> 4) & OPCODE_FUNC_ID_MASK);
3127         port_status = ql_read_page0_reg(qdev, &port_regs->portStatus);
3128         switch (value & ISP_CONTROL_FN_MASK) {
3129         case ISP_CONTROL_FN0_NET:
3130                 qdev->mac_index = 0;
3131                 qdev->mac_ob_opcode = OUTBOUND_MAC_IOCB | func_number;
3132                 qdev->tcp_ob_opcode = OUTBOUND_TCP_IOCB | func_number;
3133                 qdev->update_ob_opcode = UPDATE_NCB_IOCB | func_number;
3134                 qdev->mb_bit_mask = FN0_MA_BITS_MASK;
3135                 qdev->PHYAddr = PORT0_PHY_ADDRESS;
3136                 if (port_status & PORT_STATUS_SM0)
3137                         set_bit(QL_LINK_OPTICAL,&qdev->flags);
3138                 else
3139                         clear_bit(QL_LINK_OPTICAL,&qdev->flags);
3140                 break;
3141
3142         case ISP_CONTROL_FN1_NET:
3143                 qdev->mac_index = 1;
3144                 qdev->mac_ob_opcode = OUTBOUND_MAC_IOCB | func_number;
3145                 qdev->tcp_ob_opcode = OUTBOUND_TCP_IOCB | func_number;
3146                 qdev->update_ob_opcode = UPDATE_NCB_IOCB | func_number;
3147                 qdev->mb_bit_mask = FN1_MA_BITS_MASK;
3148                 qdev->PHYAddr = PORT1_PHY_ADDRESS;
3149                 if (port_status & PORT_STATUS_SM1)
3150                         set_bit(QL_LINK_OPTICAL,&qdev->flags);
3151                 else
3152                         clear_bit(QL_LINK_OPTICAL,&qdev->flags);
3153                 break;
3154
3155         case ISP_CONTROL_FN0_SCSI:
3156         case ISP_CONTROL_FN1_SCSI:
3157         default:
3158                 printk(KERN_DEBUG PFX
3159                        "%s: Invalid function number, ispControlStatus = 0x%x\n",
3160                        qdev->ndev->name,value);
3161                 break;
3162         }
3163         qdev->numPorts = qdev->nvram_data.numPorts;
3164 }
3165
3166 static void ql_display_dev_info(struct net_device *ndev)
3167 {
3168         struct ql3_adapter *qdev = (struct ql3_adapter *)netdev_priv(ndev);
3169         struct pci_dev *pdev = qdev->pdev;
3170
3171         printk(KERN_INFO PFX
3172                "\n%s Adapter %d RevisionID %d found %s on PCI slot %d.\n",
3173                DRV_NAME, qdev->index, qdev->chip_rev_id,
3174                (qdev->device_id == QL3032_DEVICE_ID) ? "QLA3032" : "QLA3022",
3175                qdev->pci_slot);
3176         printk(KERN_INFO PFX
3177                "%s Interface.\n",
3178                test_bit(QL_LINK_OPTICAL,&qdev->flags) ? "OPTICAL" : "COPPER");
3179
3180         /*
3181          * Print PCI bus width/type.
3182          */
3183         printk(KERN_INFO PFX
3184                "Bus interface is %s %s.\n",
3185                ((qdev->pci_width == 64) ? "64-bit" : "32-bit"),
3186                ((qdev->pci_x) ? "PCI-X" : "PCI"));
3187
3188         printk(KERN_INFO PFX
3189                "mem  IO base address adjusted = 0x%p\n",
3190                qdev->mem_map_registers);
3191         printk(KERN_INFO PFX "Interrupt number = %d\n", pdev->irq);
3192
3193         if (netif_msg_probe(qdev))
3194                 printk(KERN_INFO PFX
3195                        "%s: MAC address %02x:%02x:%02x:%02x:%02x:%02x\n",
3196                        ndev->name, ndev->dev_addr[0], ndev->dev_addr[1],
3197                        ndev->dev_addr[2], ndev->dev_addr[3], ndev->dev_addr[4],
3198                        ndev->dev_addr[5]);
3199 }
3200
3201 static int ql_adapter_down(struct ql3_adapter *qdev, int do_reset)
3202 {
3203         struct net_device *ndev = qdev->ndev;
3204         int retval = 0;
3205
3206         netif_stop_queue(ndev);
3207         netif_carrier_off(ndev);
3208
3209         clear_bit(QL_ADAPTER_UP,&qdev->flags);
3210         clear_bit(QL_LINK_MASTER,&qdev->flags);
3211
3212         ql_disable_interrupts(qdev);
3213
3214         free_irq(qdev->pdev->irq, ndev);
3215
3216         if (qdev->msi && test_bit(QL_MSI_ENABLED,&qdev->flags)) {
3217                 printk(KERN_INFO PFX
3218                        "%s: calling pci_disable_msi().\n", qdev->ndev->name);
3219                 clear_bit(QL_MSI_ENABLED,&qdev->flags);
3220                 pci_disable_msi(qdev->pdev);
3221         }
3222
3223         del_timer_sync(&qdev->adapter_timer);
3224
3225         netif_poll_disable(ndev);
3226
3227         if (do_reset) {
3228                 int soft_reset;
3229                 unsigned long hw_flags;
3230
3231                 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3232                 if (ql_wait_for_drvr_lock(qdev)) {
3233                         if ((soft_reset = ql_adapter_reset(qdev))) {
3234                                 printk(KERN_ERR PFX
3235                                        "%s: ql_adapter_reset(%d) FAILED!\n",
3236                                        ndev->name, qdev->index);
3237                         }
3238                         printk(KERN_ERR PFX
3239                                 "%s: Releaseing driver lock via chip reset.\n",ndev->name);
3240                 } else {
3241                         printk(KERN_ERR PFX
3242                                "%s: Could not acquire driver lock to do "
3243                                "reset!\n", ndev->name);
3244                         retval = -1;
3245                 }
3246                 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3247         }
3248         ql_free_mem_resources(qdev);
3249         return retval;
3250 }
3251
3252 static int ql_adapter_up(struct ql3_adapter *qdev)
3253 {
3254         struct net_device *ndev = qdev->ndev;
3255         int err;
3256         unsigned long irq_flags = IRQF_SAMPLE_RANDOM | IRQF_SHARED;
3257         unsigned long hw_flags;
3258
3259         if (ql_alloc_mem_resources(qdev)) {
3260                 printk(KERN_ERR PFX
3261                        "%s Unable to  allocate buffers.\n", ndev->name);
3262                 return -ENOMEM;
3263         }
3264
3265         if (qdev->msi) {
3266                 if (pci_enable_msi(qdev->pdev)) {
3267                         printk(KERN_ERR PFX
3268                                "%s: User requested MSI, but MSI failed to "
3269                                "initialize.  Continuing without MSI.\n",
3270                                qdev->ndev->name);
3271                         qdev->msi = 0;
3272                 } else {
3273                         printk(KERN_INFO PFX "%s: MSI Enabled...\n", qdev->ndev->name);
3274                         set_bit(QL_MSI_ENABLED,&qdev->flags);
3275                         irq_flags &= ~IRQF_SHARED;
3276                 }
3277         }
3278
3279         if ((err = request_irq(qdev->pdev->irq,
3280                                ql3xxx_isr,
3281                                irq_flags, ndev->name, ndev))) {
3282                 printk(KERN_ERR PFX
3283                        "%s: Failed to reserve interrupt %d already in use.\n",
3284                        ndev->name, qdev->pdev->irq);
3285                 goto err_irq;
3286         }
3287
3288         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3289
3290         if ((err = ql_wait_for_drvr_lock(qdev))) {
3291                 if ((err = ql_adapter_initialize(qdev))) {
3292                         printk(KERN_ERR PFX
3293                                "%s: Unable to initialize adapter.\n",
3294                                ndev->name);
3295                         goto err_init;
3296                 }
3297                 printk(KERN_ERR PFX
3298                                 "%s: Releaseing driver lock.\n",ndev->name);
3299                 ql_sem_unlock(qdev, QL_DRVR_SEM_MASK);
3300         } else {
3301                 printk(KERN_ERR PFX
3302                        "%s: Could not aquire driver lock.\n",
3303                        ndev->name);
3304                 goto err_lock;
3305         }
3306
3307         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3308
3309         set_bit(QL_ADAPTER_UP,&qdev->flags);
3310
3311         mod_timer(&qdev->adapter_timer, jiffies + HZ * 1);
3312
3313         netif_poll_enable(ndev);
3314         ql_enable_interrupts(qdev);
3315         return 0;
3316
3317 err_init:
3318         ql_sem_unlock(qdev, QL_DRVR_SEM_MASK);
3319 err_lock:
3320         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3321         free_irq(qdev->pdev->irq, ndev);
3322 err_irq:
3323         if (qdev->msi && test_bit(QL_MSI_ENABLED,&qdev->flags)) {
3324                 printk(KERN_INFO PFX
3325                        "%s: calling pci_disable_msi().\n",
3326                        qdev->ndev->name);
3327                 clear_bit(QL_MSI_ENABLED,&qdev->flags);
3328                 pci_disable_msi(qdev->pdev);
3329         }
3330         return err;
3331 }
3332
3333 static int ql_cycle_adapter(struct ql3_adapter *qdev, int reset)
3334 {
3335         if( ql_adapter_down(qdev,reset) || ql_adapter_up(qdev)) {
3336                 printk(KERN_ERR PFX
3337                                 "%s: Driver up/down cycle failed, "
3338                                 "closing device\n",qdev->ndev->name);
3339                 dev_close(qdev->ndev);
3340                 return -1;
3341         }
3342         return 0;
3343 }
3344
3345 static int ql3xxx_close(struct net_device *ndev)
3346 {
3347         struct ql3_adapter *qdev = netdev_priv(ndev);
3348
3349         /*
3350          * Wait for device to recover from a reset.
3351          * (Rarely happens, but possible.)
3352          */
3353         while (!test_bit(QL_ADAPTER_UP,&qdev->flags))
3354                 msleep(50);
3355
3356         ql_adapter_down(qdev,QL_DO_RESET);
3357         return 0;
3358 }
3359
3360 static int ql3xxx_open(struct net_device *ndev)
3361 {
3362         struct ql3_adapter *qdev = netdev_priv(ndev);
3363         return (ql_adapter_up(qdev));
3364 }
3365
3366 static struct net_device_stats *ql3xxx_get_stats(struct net_device *dev)
3367 {
3368         struct ql3_adapter *qdev = (struct ql3_adapter *)dev->priv;
3369         return &qdev->stats;
3370 }
3371
3372 static void ql3xxx_set_multicast_list(struct net_device *ndev)
3373 {
3374         /*
3375          * We are manually parsing the list in the net_device structure.
3376          */
3377         return;
3378 }
3379
3380 static int ql3xxx_set_mac_address(struct net_device *ndev, void *p)
3381 {
3382         struct ql3_adapter *qdev = (struct ql3_adapter *)netdev_priv(ndev);
3383         struct ql3xxx_port_registers __iomem *port_regs =
3384                         qdev->mem_map_registers;
3385         struct sockaddr *addr = p;
3386         unsigned long hw_flags;
3387
3388         if (netif_running(ndev))
3389                 return -EBUSY;
3390
3391         if (!is_valid_ether_addr(addr->sa_data))
3392                 return -EADDRNOTAVAIL;
3393
3394         memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
3395
3396         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3397         /* Program lower 32 bits of the MAC address */
3398         ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3399                            (MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16));
3400         ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3401                            ((ndev->dev_addr[2] << 24) | (ndev->
3402                                                          dev_addr[3] << 16) |
3403                             (ndev->dev_addr[4] << 8) | ndev->dev_addr[5]));
3404
3405         /* Program top 16 bits of the MAC address */
3406         ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3407                            ((MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16) | 1));
3408         ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3409                            ((ndev->dev_addr[0] << 8) | ndev->dev_addr[1]));
3410         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3411
3412         return 0;
3413 }
3414
3415 static void ql3xxx_tx_timeout(struct net_device *ndev)
3416 {
3417         struct ql3_adapter *qdev = (struct ql3_adapter *)netdev_priv(ndev);
3418
3419         printk(KERN_ERR PFX "%s: Resetting...\n", ndev->name);
3420         /*
3421          * Stop the queues, we've got a problem.
3422          */
3423         netif_stop_queue(ndev);
3424
3425         /*
3426          * Wake up the worker to process this event.
3427          */
3428         queue_delayed_work(qdev->workqueue, &qdev->tx_timeout_work, 0);
3429 }
3430
3431 static void ql_reset_work(struct work_struct *work)
3432 {
3433         struct ql3_adapter *qdev =
3434                 container_of(work, struct ql3_adapter, reset_work.work);
3435         struct net_device *ndev = qdev->ndev;
3436         u32 value;
3437         struct ql_tx_buf_cb *tx_cb;
3438         int max_wait_time, i;
3439         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
3440         unsigned long hw_flags;
3441
3442         if (test_bit((QL_RESET_PER_SCSI | QL_RESET_START),&qdev->flags)) {
3443                 clear_bit(QL_LINK_MASTER,&qdev->flags);
3444
3445                 /*
3446                  * Loop through the active list and return the skb.
3447                  */
3448                 for (i = 0; i < NUM_REQ_Q_ENTRIES; i++) {
3449                         int j;
3450                         tx_cb = &qdev->tx_buf[i];
3451                         if (tx_cb->skb) {
3452                                 printk(KERN_DEBUG PFX
3453                                        "%s: Freeing lost SKB.\n",
3454                                        qdev->ndev->name);
3455                                 pci_unmap_single(qdev->pdev,
3456                                          pci_unmap_addr(&tx_cb->map[0], mapaddr),
3457                                          pci_unmap_len(&tx_cb->map[0], maplen),
3458                                          PCI_DMA_TODEVICE);
3459                                 for(j=1;j<tx_cb->seg_count;j++) {
3460                                         pci_unmap_page(qdev->pdev,
3461                                                pci_unmap_addr(&tx_cb->map[j],mapaddr),
3462                                                pci_unmap_len(&tx_cb->map[j],maplen),
3463                                                PCI_DMA_TODEVICE);
3464                                 }
3465                                 dev_kfree_skb(tx_cb->skb);
3466                                 tx_cb->skb = NULL;
3467                         }
3468                 }
3469
3470                 printk(KERN_ERR PFX
3471                        "%s: Clearing NRI after reset.\n", qdev->ndev->name);
3472                 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3473                 ql_write_common_reg(qdev,
3474                                     &port_regs->CommonRegs.
3475                                     ispControlStatus,
3476                                     ((ISP_CONTROL_RI << 16) | ISP_CONTROL_RI));
3477                 /*
3478                  * Wait the for Soft Reset to Complete.
3479                  */
3480                 max_wait_time = 10;
3481                 do {
3482                         value = ql_read_common_reg(qdev,
3483                                                    &port_regs->CommonRegs.
3484
3485                                                    ispControlStatus);
3486                         if ((value & ISP_CONTROL_SR) == 0) {
3487                                 printk(KERN_DEBUG PFX
3488                                        "%s: reset completed.\n",
3489                                        qdev->ndev->name);
3490                                 break;
3491                         }
3492
3493                         if (value & ISP_CONTROL_RI) {
3494                                 printk(KERN_DEBUG PFX
3495                                        "%s: clearing NRI after reset.\n",
3496                                        qdev->ndev->name);
3497                                 ql_write_common_reg(qdev,
3498                                                     &port_regs->
3499                                                     CommonRegs.
3500                                                     ispControlStatus,
3501                                                     ((ISP_CONTROL_RI <<
3502                                                       16) | ISP_CONTROL_RI));
3503                         }
3504
3505                         ssleep(1);
3506                 } while (--max_wait_time);
3507                 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3508
3509                 if (value & ISP_CONTROL_SR) {
3510
3511                         /*
3512                          * Set the reset flags and clear the board again.
3513                          * Nothing else to do...
3514                          */
3515                         printk(KERN_ERR PFX
3516                                "%s: Timed out waiting for reset to "
3517                                "complete.\n", ndev->name);
3518                         printk(KERN_ERR PFX
3519                                "%s: Do a reset.\n", ndev->name);
3520                         clear_bit(QL_RESET_PER_SCSI,&qdev->flags);
3521                         clear_bit(QL_RESET_START,&qdev->flags);
3522                         ql_cycle_adapter(qdev,QL_DO_RESET);
3523                         return;
3524                 }
3525
3526                 clear_bit(QL_RESET_ACTIVE,&qdev->flags);
3527                 clear_bit(QL_RESET_PER_SCSI,&qdev->flags);
3528                 clear_bit(QL_RESET_START,&qdev->flags);
3529                 ql_cycle_adapter(qdev,QL_NO_RESET);
3530         }
3531 }
3532
3533 static void ql_tx_timeout_work(struct work_struct *work)
3534 {
3535         struct ql3_adapter *qdev =
3536                 container_of(work, struct ql3_adapter, tx_timeout_work.work);
3537
3538         ql_cycle_adapter(qdev, QL_DO_RESET);
3539 }
3540
3541 static void ql_get_board_info(struct ql3_adapter *qdev)
3542 {
3543         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
3544         u32 value;
3545
3546         value = ql_read_page0_reg_l(qdev, &port_regs->portStatus);
3547
3548         qdev->chip_rev_id = ((value & PORT_STATUS_REV_ID_MASK) >> 12);
3549         if (value & PORT_STATUS_64)
3550                 qdev->pci_width = 64;
3551         else
3552                 qdev->pci_width = 32;
3553         if (value & PORT_STATUS_X)
3554                 qdev->pci_x = 1;
3555         else
3556                 qdev->pci_x = 0;
3557         qdev->pci_slot = (u8) PCI_SLOT(qdev->pdev->devfn);
3558 }
3559
3560 static void ql3xxx_timer(unsigned long ptr)
3561 {
3562         struct ql3_adapter *qdev = (struct ql3_adapter *)ptr;
3563
3564         if (test_bit(QL_RESET_ACTIVE,&qdev->flags)) {
3565                 printk(KERN_DEBUG PFX
3566                        "%s: Reset in progress.\n",
3567                        qdev->ndev->name);
3568                 goto end;
3569         }
3570
3571         ql_link_state_machine(qdev);
3572
3573         /* Restart timer on 2 second interval. */
3574 end:
3575         mod_timer(&qdev->adapter_timer, jiffies + HZ * 1);
3576 }
3577
3578 static int __devinit ql3xxx_probe(struct pci_dev *pdev,
3579                                   const struct pci_device_id *pci_entry)
3580 {
3581         struct net_device *ndev = NULL;
3582         struct ql3_adapter *qdev = NULL;
3583         static int cards_found = 0;
3584         int pci_using_dac, err;
3585
3586         err = pci_enable_device(pdev);
3587         if (err) {
3588                 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3589                        pci_name(pdev));
3590                 goto err_out;
3591         }
3592
3593         err = pci_request_regions(pdev, DRV_NAME);
3594         if (err) {
3595                 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3596                        pci_name(pdev));
3597                 goto err_out_disable_pdev;
3598         }
3599
3600         pci_set_master(pdev);
3601
3602         if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
3603                 pci_using_dac = 1;
3604                 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3605         } else if (!(err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) {
3606                 pci_using_dac = 0;
3607                 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3608         }
3609
3610         if (err) {
3611                 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3612                        pci_name(pdev));
3613                 goto err_out_free_regions;
3614         }
3615
3616         ndev = alloc_etherdev(sizeof(struct ql3_adapter));
3617         if (!ndev) {
3618                 printk(KERN_ERR PFX "%s could not alloc etherdev\n",
3619                        pci_name(pdev));
3620                 err = -ENOMEM;
3621                 goto err_out_free_regions;
3622         }
3623
3624         SET_MODULE_OWNER(ndev);
3625         SET_NETDEV_DEV(ndev, &pdev->dev);
3626
3627         pci_set_drvdata(pdev, ndev);
3628
3629         qdev = netdev_priv(ndev);
3630         qdev->index = cards_found;
3631         qdev->ndev = ndev;
3632         qdev->pdev = pdev;
3633         qdev->device_id = pci_entry->device;
3634         qdev->port_link_state = LS_DOWN;
3635         if (msi)
3636                 qdev->msi = 1;
3637
3638         qdev->msg_enable = netif_msg_init(debug, default_msg);
3639
3640         if (pci_using_dac)
3641                 ndev->features |= NETIF_F_HIGHDMA;
3642         if (qdev->device_id == QL3032_DEVICE_ID)
3643                 ndev->features |= (NETIF_F_HW_CSUM | NETIF_F_SG);
3644
3645         qdev->mem_map_registers =
3646             ioremap_nocache(pci_resource_start(pdev, 1),
3647                             pci_resource_len(qdev->pdev, 1));
3648         if (!qdev->mem_map_registers) {
3649                 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3650                        pci_name(pdev));
3651                 err = -EIO;
3652                 goto err_out_free_ndev;
3653         }
3654
3655         spin_lock_init(&qdev->adapter_lock);
3656         spin_lock_init(&qdev->hw_lock);
3657
3658         /* Set driver entry points */
3659         ndev->open = ql3xxx_open;
3660         ndev->hard_start_xmit = ql3xxx_send;
3661         ndev->stop = ql3xxx_close;
3662         ndev->get_stats = ql3xxx_get_stats;
3663         ndev->set_multicast_list = ql3xxx_set_multicast_list;
3664         SET_ETHTOOL_OPS(ndev, &ql3xxx_ethtool_ops);
3665         ndev->set_mac_address = ql3xxx_set_mac_address;
3666         ndev->tx_timeout = ql3xxx_tx_timeout;
3667         ndev->watchdog_timeo = 5 * HZ;
3668
3669         ndev->poll = &ql_poll;
3670         ndev->weight = 64;
3671
3672         ndev->irq = pdev->irq;
3673
3674         /* make sure the EEPROM is good */
3675         if (ql_get_nvram_params(qdev)) {
3676                 printk(KERN_ALERT PFX
3677                        "ql3xxx_probe: Adapter #%d, Invalid NVRAM parameters.\n",
3678                        qdev->index);
3679                 err = -EIO;
3680                 goto err_out_iounmap;
3681         }
3682
3683         ql_set_mac_info(qdev);
3684
3685         /* Validate and set parameters */
3686         if (qdev->mac_index) {
3687                 ndev->mtu = qdev->nvram_data.macCfg_port1.etherMtu_mac ;
3688                 memcpy(ndev->dev_addr, &qdev->nvram_data.funcCfg_fn2.macAddress,
3689                        ETH_ALEN);
3690         } else {
3691                 ndev->mtu = qdev->nvram_data.macCfg_port0.etherMtu_mac ;
3692                 memcpy(ndev->dev_addr, &qdev->nvram_data.funcCfg_fn0.macAddress,
3693                        ETH_ALEN);
3694         }
3695         memcpy(ndev->perm_addr, ndev->dev_addr, ndev->addr_len);
3696
3697         ndev->tx_queue_len = NUM_REQ_Q_ENTRIES;
3698
3699         /* Turn off support for multicasting */
3700         ndev->flags &= ~IFF_MULTICAST;
3701
3702         /* Record PCI bus information. */
3703         ql_get_board_info(qdev);
3704
3705         /*
3706          * Set the Maximum Memory Read Byte Count value. We do this to handle
3707          * jumbo frames.
3708          */
3709         if (qdev->pci_x) {
3710                 pci_write_config_word(pdev, (int)0x4e, (u16) 0x0036);
3711         }
3712
3713         err = register_netdev(ndev);
3714         if (err) {
3715                 printk(KERN_ERR PFX "%s: cannot register net device\n",
3716                        pci_name(pdev));
3717                 goto err_out_iounmap;
3718         }
3719
3720         /* we're going to reset, so assume we have no link for now */
3721
3722         netif_carrier_off(ndev);
3723         netif_stop_queue(ndev);
3724
3725         qdev->workqueue = create_singlethread_workqueue(ndev->name);
3726         INIT_DELAYED_WORK(&qdev->reset_work, ql_reset_work);
3727         INIT_DELAYED_WORK(&qdev->tx_timeout_work, ql_tx_timeout_work);
3728
3729         init_timer(&qdev->adapter_timer);
3730         qdev->adapter_timer.function = ql3xxx_timer;
3731         qdev->adapter_timer.expires = jiffies + HZ * 2; /* two second delay */
3732         qdev->adapter_timer.data = (unsigned long)qdev;
3733
3734         if(!cards_found) {
3735                 printk(KERN_ALERT PFX "%s\n", DRV_STRING);
3736                 printk(KERN_ALERT PFX "Driver name: %s, Version: %s.\n",
3737                    DRV_NAME, DRV_VERSION);
3738         }
3739         ql_display_dev_info(ndev);
3740
3741         cards_found++;
3742         return 0;
3743
3744 err_out_iounmap:
3745         iounmap(qdev->mem_map_registers);
3746 err_out_free_ndev:
3747         free_netdev(ndev);
3748 err_out_free_regions:
3749         pci_release_regions(pdev);
3750 err_out_disable_pdev:
3751         pci_disable_device(pdev);
3752         pci_set_drvdata(pdev, NULL);
3753 err_out:
3754         return err;
3755 }
3756
3757 static void __devexit ql3xxx_remove(struct pci_dev *pdev)
3758 {
3759         struct net_device *ndev = pci_get_drvdata(pdev);
3760         struct ql3_adapter *qdev = netdev_priv(ndev);
3761
3762         unregister_netdev(ndev);
3763         qdev = netdev_priv(ndev);
3764
3765         ql_disable_interrupts(qdev);
3766
3767         if (qdev->workqueue) {
3768                 cancel_delayed_work(&qdev->reset_work);
3769                 cancel_delayed_work(&qdev->tx_timeout_work);
3770                 destroy_workqueue(qdev->workqueue);
3771                 qdev->workqueue = NULL;
3772         }
3773
3774         iounmap(qdev->mem_map_registers);
3775         pci_release_regions(pdev);
3776         pci_set_drvdata(pdev, NULL);
3777         free_netdev(ndev);
3778 }
3779
3780 static struct pci_driver ql3xxx_driver = {
3781
3782         .name = DRV_NAME,
3783         .id_table = ql3xxx_pci_tbl,
3784         .probe = ql3xxx_probe,
3785         .remove = __devexit_p(ql3xxx_remove),
3786 };
3787
3788 static int __init ql3xxx_init_module(void)
3789 {
3790         return pci_register_driver(&ql3xxx_driver);
3791 }
3792
3793 static void __exit ql3xxx_exit(void)
3794 {
3795         pci_unregister_driver(&ql3xxx_driver);
3796 }
3797
3798 module_init(ql3xxx_init_module);
3799 module_exit(ql3xxx_exit);