drivers/net/qlcnic/qlcnic_hw.c

   1 /*
   2  * Copyright (C) 2009 - QLogic Corporation.
   3  * All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License
   7  * as published by the Free Software Foundation; either version 2
   8  * of the License, or (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
  18  * MA  02111-1307, USA.
  19  *
  20  * The full GNU General Public License is included in this distribution
  21  * in the file called "COPYING".
  22  *
  23  */
  24
  25 #include "qlcnic.h"
  26
  27 #include <linux/slab.h>
  28 #include <net/ip.h>
  29
  30 #define MASK(n) ((1ULL<<(n))-1)
  31 #define OCM_WIN_P3P(addr) (addr & 0xffc0000)
  32
  33 #define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
  34
  35 #define CRB_BLK(off)    ((off >> 20) & 0x3f)
  36 #define CRB_SUBBLK(off) ((off >> 16) & 0xf)
  37 #define CRB_WINDOW_2M   (0x130060)
  38 #define CRB_HI(off)     ((crb_hub_agt[CRB_BLK(off)] << 20) | ((off) & 0xf0000))
  39 #define CRB_INDIRECT_2M (0x1e0000UL)
  40
  41
  42 #ifndef readq
  43 static inline u64 readq(void __iomem *addr)
  44 {
  45         return readl(addr) | (((u64) readl(addr + 4)) << 32LL);
  46 }
  47 #endif
  48
  49 #ifndef writeq
  50 static inline void writeq(u64 val, void __iomem *addr)
  51 {
  52         writel(((u32) (val)), (addr));
  53         writel(((u32) (val >> 32)), (addr + 4));
  54 }
  55 #endif
  56
  57 static const struct crb_128M_2M_block_map
  58 crb_128M_2M_map[64] __cacheline_aligned_in_smp = {
  59     {{{0, 0,         0,         0} } },         /* 0: PCI */
  60     {{{1, 0x0100000, 0x0102000, 0x120000},      /* 1: PCIE */
  61           {1, 0x0110000, 0x0120000, 0x130000},
  62           {1, 0x0120000, 0x0122000, 0x124000},
  63           {1, 0x0130000, 0x0132000, 0x126000},
  64           {1, 0x0140000, 0x0142000, 0x128000},
  65           {1, 0x0150000, 0x0152000, 0x12a000},
  66           {1, 0x0160000, 0x0170000, 0x110000},
  67           {1, 0x0170000, 0x0172000, 0x12e000},
  68           {0, 0x0000000, 0x0000000, 0x000000},
  69           {0, 0x0000000, 0x0000000, 0x000000},
  70           {0, 0x0000000, 0x0000000, 0x000000},
  71           {0, 0x0000000, 0x0000000, 0x000000},
  72           {0, 0x0000000, 0x0000000, 0x000000},
  73           {0, 0x0000000, 0x0000000, 0x000000},
  74           {1, 0x01e0000, 0x01e0800, 0x122000},
  75           {0, 0x0000000, 0x0000000, 0x000000} } },
  76         {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */
  77     {{{0, 0,         0,         0} } },     /* 3: */
  78     {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */
  79     {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE   */
  80     {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU   */
  81     {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM    */
  82     {{{1, 0x0800000, 0x0802000, 0x170000},  /* 8: SQM0  */
  83       {0, 0x0000000, 0x0000000, 0x000000},
  84       {0, 0x0000000, 0x0000000, 0x000000},
  85       {0, 0x0000000, 0x0000000, 0x000000},
  86       {0, 0x0000000, 0x0000000, 0x000000},
  87       {0, 0x0000000, 0x0000000, 0x000000},
  88       {0, 0x0000000, 0x0000000, 0x000000},
  89       {0, 0x0000000, 0x0000000, 0x000000},
  90       {0, 0x0000000, 0x0000000, 0x000000},
  91       {0, 0x0000000, 0x0000000, 0x000000},
  92       {0, 0x0000000, 0x0000000, 0x000000},
  93       {0, 0x0000000, 0x0000000, 0x000000},
  94       {0, 0x0000000, 0x0000000, 0x000000},
  95       {0, 0x0000000, 0x0000000, 0x000000},
  96       {0, 0x0000000, 0x0000000, 0x000000},
  97       {1, 0x08f0000, 0x08f2000, 0x172000} } },
  98     {{{1, 0x0900000, 0x0902000, 0x174000},      /* 9: SQM1*/
  99       {0, 0x0000000, 0x0000000, 0x000000},
 100       {0, 0x0000000, 0x0000000, 0x000000},
 101       {0, 0x0000000, 0x0000000, 0x000000},
 102       {0, 0x0000000, 0x0000000, 0x000000},
 103       {0, 0x0000000, 0x0000000, 0x000000},
 104       {0, 0x0000000, 0x0000000, 0x000000},
 105       {0, 0x0000000, 0x0000000, 0x000000},
 106       {0, 0x0000000, 0x0000000, 0x000000},
 107       {0, 0x0000000, 0x0000000, 0x000000},
 108       {0, 0x0000000, 0x0000000, 0x000000},
 109       {0, 0x0000000, 0x0000000, 0x000000},
 110       {0, 0x0000000, 0x0000000, 0x000000},
 111       {0, 0x0000000, 0x0000000, 0x000000},
 112       {0, 0x0000000, 0x0000000, 0x000000},
 113       {1, 0x09f0000, 0x09f2000, 0x176000} } },
 114     {{{0, 0x0a00000, 0x0a02000, 0x178000},      /* 10: SQM2*/
 115       {0, 0x0000000, 0x0000000, 0x000000},
 116       {0, 0x0000000, 0x0000000, 0x000000},
 117       {0, 0x0000000, 0x0000000, 0x000000},
 118       {0, 0x0000000, 0x0000000, 0x000000},
 119       {0, 0x0000000, 0x0000000, 0x000000},
 120       {0, 0x0000000, 0x0000000, 0x000000},
 121       {0, 0x0000000, 0x0000000, 0x000000},
 122       {0, 0x0000000, 0x0000000, 0x000000},
 123       {0, 0x0000000, 0x0000000, 0x000000},
 124       {0, 0x0000000, 0x0000000, 0x000000},
 125       {0, 0x0000000, 0x0000000, 0x000000},
 126       {0, 0x0000000, 0x0000000, 0x000000},
 127       {0, 0x0000000, 0x0000000, 0x000000},
 128       {0, 0x0000000, 0x0000000, 0x000000},
 129       {1, 0x0af0000, 0x0af2000, 0x17a000} } },
 130     {{{0, 0x0b00000, 0x0b02000, 0x17c000},      /* 11: SQM3*/
 131       {0, 0x0000000, 0x0000000, 0x000000},
 132       {0, 0x0000000, 0x0000000, 0x000000},
 133       {0, 0x0000000, 0x0000000, 0x000000},
 134       {0, 0x0000000, 0x0000000, 0x000000},
 135       {0, 0x0000000, 0x0000000, 0x000000},
 136       {0, 0x0000000, 0x0000000, 0x000000},
 137       {0, 0x0000000, 0x0000000, 0x000000},
 138       {0, 0x0000000, 0x0000000, 0x000000},
 139       {0, 0x0000000, 0x0000000, 0x000000},
 140       {0, 0x0000000, 0x0000000, 0x000000},
 141       {0, 0x0000000, 0x0000000, 0x000000},
 142       {0, 0x0000000, 0x0000000, 0x000000},
 143       {0, 0x0000000, 0x0000000, 0x000000},
 144       {0, 0x0000000, 0x0000000, 0x000000},
 145       {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
 146         {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */
 147         {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */
 148         {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */
 149         {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */
 150         {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */
 151         {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */
 152         {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */
 153         {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */
 154         {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */
 155         {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */
 156         {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */
 157         {{{0, 0,         0,         0} } },     /* 23: */
 158         {{{0, 0,         0,         0} } },     /* 24: */
 159         {{{0, 0,         0,         0} } },     /* 25: */
 160         {{{0, 0,         0,         0} } },     /* 26: */
 161         {{{0, 0,         0,         0} } },     /* 27: */
 162         {{{0, 0,         0,         0} } },     /* 28: */
 163         {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */
 164     {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */
 165     {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */
 166         {{{0} } },                              /* 32: PCI */
 167         {{{1, 0x2100000, 0x2102000, 0x120000},  /* 33: PCIE */
 168           {1, 0x2110000, 0x2120000, 0x130000},
 169           {1, 0x2120000, 0x2122000, 0x124000},
 170           {1, 0x2130000, 0x2132000, 0x126000},
 171           {1, 0x2140000, 0x2142000, 0x128000},
 172           {1, 0x2150000, 0x2152000, 0x12a000},
 173           {1, 0x2160000, 0x2170000, 0x110000},
 174           {1, 0x2170000, 0x2172000, 0x12e000},
 175           {0, 0x0000000, 0x0000000, 0x000000},
 176           {0, 0x0000000, 0x0000000, 0x000000},
 177           {0, 0x0000000, 0x0000000, 0x000000},
 178           {0, 0x0000000, 0x0000000, 0x000000},
 179           {0, 0x0000000, 0x0000000, 0x000000},
 180           {0, 0x0000000, 0x0000000, 0x000000},
 181           {0, 0x0000000, 0x0000000, 0x000000},
 182           {0, 0x0000000, 0x0000000, 0x000000} } },
 183         {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */
 184         {{{0} } },                              /* 35: */
 185         {{{0} } },                              /* 36: */
 186         {{{0} } },                              /* 37: */
 187         {{{0} } },                              /* 38: */
 188         {{{0} } },                              /* 39: */
 189         {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */
 190         {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */
 191         {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */
 192         {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */
 193         {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */
 194         {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */
 195         {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */
 196         {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */
 197         {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */
 198         {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */
 199         {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */
 200         {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */
 201         {{{0} } },                              /* 52: */
 202         {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */
 203         {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */
 204         {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */
 205         {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */
 206         {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */
 207         {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */
 208         {{{0} } },                              /* 59: I2C0 */
 209         {{{0} } },                              /* 60: I2C1 */
 210         {{{1, 0x3d00000, 0x3d04000, 0x1d8000} } },/* 61: LPC */
 211         {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */
 212         {{{1, 0x3f00000, 0x3f01000, 0x168000} } }       /* 63: P2NR0 */
 213 };
 214
 215 /*
 216  * top 12 bits of crb internal address (hub, agent)
 217  */
 218 static const unsigned crb_hub_agt[64] = {
 219         0,
 220         QLCNIC_HW_CRB_HUB_AGT_ADR_PS,
 221         QLCNIC_HW_CRB_HUB_AGT_ADR_MN,
 222         QLCNIC_HW_CRB_HUB_AGT_ADR_MS,
 223         0,
 224         QLCNIC_HW_CRB_HUB_AGT_ADR_SRE,
 225         QLCNIC_HW_CRB_HUB_AGT_ADR_NIU,
 226         QLCNIC_HW_CRB_HUB_AGT_ADR_QMN,
 227         QLCNIC_HW_CRB_HUB_AGT_ADR_SQN0,
 228         QLCNIC_HW_CRB_HUB_AGT_ADR_SQN1,
 229         QLCNIC_HW_CRB_HUB_AGT_ADR_SQN2,
 230         QLCNIC_HW_CRB_HUB_AGT_ADR_SQN3,
 231         QLCNIC_HW_CRB_HUB_AGT_ADR_I2Q,
 232         QLCNIC_HW_CRB_HUB_AGT_ADR_TIMR,
 233         QLCNIC_HW_CRB_HUB_AGT_ADR_ROMUSB,
 234         QLCNIC_HW_CRB_HUB_AGT_ADR_PGN4,
 235         QLCNIC_HW_CRB_HUB_AGT_ADR_XDMA,
 236         QLCNIC_HW_CRB_HUB_AGT_ADR_PGN0,
 237         QLCNIC_HW_CRB_HUB_AGT_ADR_PGN1,
 238         QLCNIC_HW_CRB_HUB_AGT_ADR_PGN2,
 239         QLCNIC_HW_CRB_HUB_AGT_ADR_PGN3,
 240         QLCNIC_HW_CRB_HUB_AGT_ADR_PGND,
 241         QLCNIC_HW_CRB_HUB_AGT_ADR_PGNI,
 242         QLCNIC_HW_CRB_HUB_AGT_ADR_PGS0,
 243         QLCNIC_HW_CRB_HUB_AGT_ADR_PGS1,
 244         QLCNIC_HW_CRB_HUB_AGT_ADR_PGS2,
 245         QLCNIC_HW_CRB_HUB_AGT_ADR_PGS3,
 246         0,
 247         QLCNIC_HW_CRB_HUB_AGT_ADR_PGSI,
 248         QLCNIC_HW_CRB_HUB_AGT_ADR_SN,
 249         0,
 250         QLCNIC_HW_CRB_HUB_AGT_ADR_EG,
 251         0,
 252         QLCNIC_HW_CRB_HUB_AGT_ADR_PS,
 253         QLCNIC_HW_CRB_HUB_AGT_ADR_CAM,
 254         0,
 255         0,
 256         0,
 257         0,
 258         0,
 259         QLCNIC_HW_CRB_HUB_AGT_ADR_TIMR,
 260         0,
 261         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX1,
 262         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX2,
 263         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX3,
 264         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX4,
 265         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX5,
 266         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX6,
 267         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX7,
 268         QLCNIC_HW_CRB_HUB_AGT_ADR_XDMA,
 269         QLCNIC_HW_CRB_HUB_AGT_ADR_I2Q,
 270         QLCNIC_HW_CRB_HUB_AGT_ADR_ROMUSB,
 271         0,
 272         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX0,
 273         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX8,
 274         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX9,
 275         QLCNIC_HW_CRB_HUB_AGT_ADR_OCM0,
 276         0,
 277         QLCNIC_HW_CRB_HUB_AGT_ADR_SMB,
 278         QLCNIC_HW_CRB_HUB_AGT_ADR_I2C0,
 279         QLCNIC_HW_CRB_HUB_AGT_ADR_I2C1,
 280         0,
 281         QLCNIC_HW_CRB_HUB_AGT_ADR_PGNC,
 282         0,
 283 };
 284
 285 /*  PCI Windowing for DDR regions.  */
 286
 287 #define QLCNIC_PCIE_SEM_TIMEOUT 10000
 288
 289 int
 290 qlcnic_pcie_sem_lock(struct qlcnic_adapter *adapter, int sem, u32 id_reg)
 291 {
 292         int done = 0, timeout = 0;
 293
 294         while (!done) {
 295                 done = QLCRD32(adapter, QLCNIC_PCIE_REG(PCIE_SEM_LOCK(sem)));
 296                 if (done == 1)
 297                         break;
 298                 if (++timeout >= QLCNIC_PCIE_SEM_TIMEOUT) {
 299                         dev_err(&adapter->pdev->dev,
 300                                 "Failed to acquire sem=%d lock; holdby=%d\n",
 301                                 sem, id_reg ? QLCRD32(adapter, id_reg) : -1);
 302                         return -EIO;
 303                 }
 304                 msleep(1);
 305         }
 306
 307         if (id_reg)
 308                 QLCWR32(adapter, id_reg, adapter->portnum);
 309
 310         return 0;
 311 }
 312
 313 void
 314 qlcnic_pcie_sem_unlock(struct qlcnic_adapter *adapter, int sem)
 315 {
 316         QLCRD32(adapter, QLCNIC_PCIE_REG(PCIE_SEM_UNLOCK(sem)));
 317 }
 318
 319 static int
 320 qlcnic_send_cmd_descs(struct qlcnic_adapter *adapter,
 321                 struct cmd_desc_type0 *cmd_desc_arr, int nr_desc)
 322 {
 323         u32 i, producer, consumer;
 324         struct qlcnic_cmd_buffer *pbuf;
 325         struct cmd_desc_type0 *cmd_desc;
 326         struct qlcnic_host_tx_ring *tx_ring;
 327
 328         i = 0;
 329
 330         if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state))
 331                 return -EIO;
 332
 333         tx_ring = adapter->tx_ring;
 334         __netif_tx_lock_bh(tx_ring->txq);
 335
 336         producer = tx_ring->producer;
 337         consumer = tx_ring->sw_consumer;
 338
 339         if (nr_desc >= qlcnic_tx_avail(tx_ring)) {
 340                 netif_tx_stop_queue(tx_ring->txq);
 341                 smp_mb();
 342                 if (qlcnic_tx_avail(tx_ring) > nr_desc) {
 343                         if (qlcnic_tx_avail(tx_ring) > TX_STOP_THRESH)
 344                                 netif_tx_wake_queue(tx_ring->txq);
 345                 } else {
 346                         adapter->stats.xmit_off++;
 347                         __netif_tx_unlock_bh(tx_ring->txq);
 348                         return -EBUSY;
 349                 }
 350         }
 351
 352         do {
 353                 cmd_desc = &cmd_desc_arr[i];
 354
 355                 pbuf = &tx_ring->cmd_buf_arr[producer];
 356                 pbuf->skb = NULL;
 357                 pbuf->frag_count = 0;
 358
 359                 memcpy(&tx_ring->desc_head[producer],
 360                         &cmd_desc_arr[i], sizeof(struct cmd_desc_type0));
 361
 362                 producer = get_next_index(producer, tx_ring->num_desc);
 363                 i++;
 364
 365         } while (i != nr_desc);
 366
 367         tx_ring->producer = producer;
 368
 369         qlcnic_update_cmd_producer(adapter, tx_ring);
 370
 371         __netif_tx_unlock_bh(tx_ring->txq);
 372
 373         return 0;
 374 }
 375
 376 static int
 377 qlcnic_sre_macaddr_change(struct qlcnic_adapter *adapter, u8 *addr,
 378                                 unsigned op)
 379 {
 380         struct qlcnic_nic_req req;
 381         struct qlcnic_mac_req *mac_req;
 382         u64 word;
 383
 384         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 385         req.qhdr = cpu_to_le64(QLCNIC_REQUEST << 23);
 386
 387         word = QLCNIC_MAC_EVENT | ((u64)adapter->portnum << 16);
 388         req.req_hdr = cpu_to_le64(word);
 389
 390         mac_req = (struct qlcnic_mac_req *)&req.words[0];
 391         mac_req->op = op;
 392         memcpy(mac_req->mac_addr, addr, 6);
 393
 394         return qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 395 }
 396
 397 static int qlcnic_nic_add_mac(struct qlcnic_adapter *adapter, u8 *addr)
 398 {
 399         struct list_head *head;
 400         struct qlcnic_mac_list_s *cur;
 401
 402         /* look up if already exists */
 403         list_for_each(head, &adapter->mac_list) {
 404                 cur = list_entry(head, struct qlcnic_mac_list_s, list);
 405                 if (memcmp(addr, cur->mac_addr, ETH_ALEN) == 0)
 406                         return 0;
 407         }
 408
 409         cur = kzalloc(sizeof(struct qlcnic_mac_list_s), GFP_ATOMIC);
 410         if (cur == NULL) {
 411                 dev_err(&adapter->netdev->dev,
 412                         "failed to add mac address filter\n");
 413                 return -ENOMEM;
 414         }
 415         memcpy(cur->mac_addr, addr, ETH_ALEN);
 416
 417         if (qlcnic_sre_macaddr_change(adapter,
 418                                 cur->mac_addr, QLCNIC_MAC_ADD)) {
 419                 kfree(cur);
 420                 return -EIO;
 421         }
 422
 423         list_add_tail(&cur->list, &adapter->mac_list);
 424         return 0;
 425 }
 426
 427 void qlcnic_set_multi(struct net_device *netdev)
 428 {
 429         struct qlcnic_adapter *adapter = netdev_priv(netdev);
 430         struct netdev_hw_addr *ha;
 431         u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
 432         u32 mode = VPORT_MISS_MODE_DROP;
 433
 434         if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state))
 435                 return;
 436
 437         qlcnic_nic_add_mac(adapter, adapter->mac_addr);
 438         qlcnic_nic_add_mac(adapter, bcast_addr);
 439
 440         if (netdev->flags & IFF_PROMISC) {
 441                 mode = VPORT_MISS_MODE_ACCEPT_ALL;
 442                 goto send_fw_cmd;
 443         }
 444
 445         if ((netdev->flags & IFF_ALLMULTI) ||
 446             (netdev_mc_count(netdev) > adapter->max_mc_count)) {
 447                 mode = VPORT_MISS_MODE_ACCEPT_MULTI;
 448                 goto send_fw_cmd;
 449         }
 450
 451         if (!netdev_mc_empty(netdev)) {
 452                 netdev_for_each_mc_addr(ha, netdev) {
 453                         qlcnic_nic_add_mac(adapter, ha->addr);
 454                 }
 455         }
 456
 457 send_fw_cmd:
 458         qlcnic_nic_set_promisc(adapter, mode);
 459 }
 460
 461 int qlcnic_nic_set_promisc(struct qlcnic_adapter *adapter, u32 mode)
 462 {
 463         struct qlcnic_nic_req req;
 464         u64 word;
 465
 466         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 467
 468         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 469
 470         word = QLCNIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE |
 471                         ((u64)adapter->portnum << 16);
 472         req.req_hdr = cpu_to_le64(word);
 473
 474         req.words[0] = cpu_to_le64(mode);
 475
 476         return qlcnic_send_cmd_descs(adapter,
 477                                 (struct cmd_desc_type0 *)&req, 1);
 478 }
 479
 480 void qlcnic_free_mac_list(struct qlcnic_adapter *adapter)
 481 {
 482         struct qlcnic_mac_list_s *cur;
 483         struct list_head *head = &adapter->mac_list;
 484
 485         while (!list_empty(head)) {
 486                 cur = list_entry(head->next, struct qlcnic_mac_list_s, list);
 487                 qlcnic_sre_macaddr_change(adapter,
 488                                 cur->mac_addr, QLCNIC_MAC_DEL);
 489                 list_del(&cur->list);
 490                 kfree(cur);
 491         }
 492 }
 493
 494 void qlcnic_prune_lb_filters(struct qlcnic_adapter *adapter)
 495 {
 496         struct qlcnic_filter *tmp_fil;
 497         struct hlist_node *tmp_hnode, *n;
 498         struct hlist_head *head;
 499         int i;
 500
 501         for (i = 0; i < adapter->fhash.fmax; i++) {
 502                 head = &(adapter->fhash.fhead[i]);
 503
 504                 hlist_for_each_entry_safe(tmp_fil, tmp_hnode, n, head, fnode)
 505                 {
 506                         if (jiffies >
 507                                 (QLCNIC_FILTER_AGE * HZ + tmp_fil->ftime)) {
 508                                 qlcnic_sre_macaddr_change(adapter,
 509                                         tmp_fil->faddr, QLCNIC_MAC_DEL);
 510                                 spin_lock_bh(&adapter->mac_learn_lock);
 511                                 adapter->fhash.fnum--;
 512                                 hlist_del(&tmp_fil->fnode);
 513                                 spin_unlock_bh(&adapter->mac_learn_lock);
 514                                 kfree(tmp_fil);
 515                         }
 516                 }
 517         }
 518 }
 519
 520 void qlcnic_delete_lb_filters(struct qlcnic_adapter *adapter)
 521 {
 522         struct qlcnic_filter *tmp_fil;
 523         struct hlist_node *tmp_hnode, *n;
 524         struct hlist_head *head;
 525         int i;
 526
 527         for (i = 0; i < adapter->fhash.fmax; i++) {
 528                 head = &(adapter->fhash.fhead[i]);
 529
 530                 hlist_for_each_entry_safe(tmp_fil, tmp_hnode, n, head, fnode) {
 531                         qlcnic_sre_macaddr_change(adapter,
 532                                         tmp_fil->faddr, QLCNIC_MAC_DEL);
 533                         spin_lock_bh(&adapter->mac_learn_lock);
 534                         adapter->fhash.fnum--;
 535                         hlist_del(&tmp_fil->fnode);
 536                         spin_unlock_bh(&adapter->mac_learn_lock);
 537                         kfree(tmp_fil);
 538                 }
 539         }
 540 }
 541
 542 #define QLCNIC_CONFIG_INTR_COALESCE     3
 543
 544 /*
 545  * Send the interrupt coalescing parameter set by ethtool to the card.
 546  */
 547 int qlcnic_config_intr_coalesce(struct qlcnic_adapter *adapter)
 548 {
 549         struct qlcnic_nic_req req;
 550         u64 word[6];
 551         int rv, i;
 552
 553         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 554
 555         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 556
 557         word[0] = QLCNIC_CONFIG_INTR_COALESCE | ((u64)adapter->portnum << 16);
 558         req.req_hdr = cpu_to_le64(word[0]);
 559
 560         memcpy(&word[0], &adapter->coal, sizeof(adapter->coal));
 561         for (i = 0; i < 6; i++)
 562                 req.words[i] = cpu_to_le64(word[i]);
 563
 564         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 565         if (rv != 0)
 566                 dev_err(&adapter->netdev->dev,
 567                         "Could not send interrupt coalescing parameters\n");
 568
 569         return rv;
 570 }
 571
 572 int qlcnic_config_hw_lro(struct qlcnic_adapter *adapter, int enable)
 573 {
 574         struct qlcnic_nic_req req;
 575         u64 word;
 576         int rv;
 577
 578         if ((adapter->flags & QLCNIC_LRO_ENABLED) == enable)
 579                 return 0;
 580
 581         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 582
 583         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 584
 585         word = QLCNIC_H2C_OPCODE_CONFIG_HW_LRO | ((u64)adapter->portnum << 16);
 586         req.req_hdr = cpu_to_le64(word);
 587
 588         req.words[0] = cpu_to_le64(enable);
 589
 590         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 591         if (rv != 0)
 592                 dev_err(&adapter->netdev->dev,
 593                         "Could not send configure hw lro request\n");
 594
 595         adapter->flags ^= QLCNIC_LRO_ENABLED;
 596
 597         return rv;
 598 }
 599
 600 int qlcnic_config_bridged_mode(struct qlcnic_adapter *adapter, u32 enable)
 601 {
 602         struct qlcnic_nic_req req;
 603         u64 word;
 604         int rv;
 605
 606         if (!!(adapter->flags & QLCNIC_BRIDGE_ENABLED) == enable)
 607                 return 0;
 608
 609         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 610
 611         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 612
 613         word = QLCNIC_H2C_OPCODE_CONFIG_BRIDGING |
 614                 ((u64)adapter->portnum << 16);
 615         req.req_hdr = cpu_to_le64(word);
 616
 617         req.words[0] = cpu_to_le64(enable);
 618
 619         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 620         if (rv != 0)
 621                 dev_err(&adapter->netdev->dev,
 622                         "Could not send configure bridge mode request\n");
 623
 624         adapter->flags ^= QLCNIC_BRIDGE_ENABLED;
 625
 626         return rv;
 627 }
 628
 629
 630 #define RSS_HASHTYPE_IP_TCP     0x3
 631
 632 int qlcnic_config_rss(struct qlcnic_adapter *adapter, int enable)
 633 {
 634         struct qlcnic_nic_req req;
 635         u64 word;
 636         int i, rv;
 637
 638         const u64 key[] = { 0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL,
 639                         0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL,
 640                         0x255b0ec26d5a56daULL };
 641
 642
 643         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 644         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 645
 646         word = QLCNIC_H2C_OPCODE_CONFIG_RSS | ((u64)adapter->portnum << 16);
 647         req.req_hdr = cpu_to_le64(word);
 648
 649         /*
 650          * RSS request:
 651          * bits 3-0: hash_method
 652          *      5-4: hash_type_ipv4
 653          *      7-6: hash_type_ipv6
 654          *        8: enable
 655          *        9: use indirection table
 656          *    47-10: reserved
 657          *    63-48: indirection table mask
 658          */
 659         word =  ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 4) |
 660                 ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 6) |
 661                 ((u64)(enable & 0x1) << 8) |
 662                 ((0x7ULL) << 48);
 663         req.words[0] = cpu_to_le64(word);
 664         for (i = 0; i < 5; i++)
 665                 req.words[i+1] = cpu_to_le64(key[i]);
 666
 667         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 668         if (rv != 0)
 669                 dev_err(&adapter->netdev->dev, "could not configure RSS\n");
 670
 671         return rv;
 672 }
 673
 674 int qlcnic_config_ipaddr(struct qlcnic_adapter *adapter, u32 ip, int cmd)
 675 {
 676         struct qlcnic_nic_req req;
 677         u64 word;
 678         int rv;
 679
 680         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 681         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 682
 683         word = QLCNIC_H2C_OPCODE_CONFIG_IPADDR | ((u64)adapter->portnum << 16);
 684         req.req_hdr = cpu_to_le64(word);
 685
 686         req.words[0] = cpu_to_le64(cmd);
 687         req.words[1] = cpu_to_le64(ip);
 688
 689         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 690         if (rv != 0)
 691                 dev_err(&adapter->netdev->dev,
 692                                 "could not notify %s IP 0x%x reuqest\n",
 693                                 (cmd == QLCNIC_IP_UP) ? "Add" : "Remove", ip);
 694
 695         return rv;
 696 }
 697
 698 int qlcnic_linkevent_request(struct qlcnic_adapter *adapter, int enable)
 699 {
 700         struct qlcnic_nic_req req;
 701         u64 word;
 702         int rv;
 703
 704         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 705         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 706
 707         word = QLCNIC_H2C_OPCODE_GET_LINKEVENT | ((u64)adapter->portnum << 16);
 708         req.req_hdr = cpu_to_le64(word);
 709         req.words[0] = cpu_to_le64(enable | (enable << 8));
 710
 711         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 712         if (rv != 0)
 713                 dev_err(&adapter->netdev->dev,
 714                                 "could not configure link notification\n");
 715
 716         return rv;
 717 }
 718
 719 int qlcnic_send_lro_cleanup(struct qlcnic_adapter *adapter)
 720 {
 721         struct qlcnic_nic_req req;
 722         u64 word;
 723         int rv;
 724
 725         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 726         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 727
 728         word = QLCNIC_H2C_OPCODE_LRO_REQUEST |
 729                 ((u64)adapter->portnum << 16) |
 730                 ((u64)QLCNIC_LRO_REQUEST_CLEANUP << 56) ;
 731
 732         req.req_hdr = cpu_to_le64(word);
 733
 734         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 735         if (rv != 0)
 736                 dev_err(&adapter->netdev->dev,
 737                                  "could not cleanup lro flows\n");
 738
 739         return rv;
 740 }
 741
 742 /*
 743  * qlcnic_change_mtu - Change the Maximum Transfer Unit
 744  * @returns 0 on success, negative on failure
 745  */
 746
 747 int qlcnic_change_mtu(struct net_device *netdev, int mtu)
 748 {
 749         struct qlcnic_adapter *adapter = netdev_priv(netdev);
 750         int rc = 0;
 751
 752         if (mtu > P3_MAX_MTU) {
 753                 dev_err(&adapter->netdev->dev, "mtu > %d bytes unsupported\n",
 754                                                 P3_MAX_MTU);
 755                 return -EINVAL;
 756         }
 757
 758         rc = qlcnic_fw_cmd_set_mtu(adapter, mtu);
 759
 760         if (!rc)
 761                 netdev->mtu = mtu;
 762
 763         return rc;
 764 }
 765
 766 /*
 767  * Changes the CRB window to the specified window.
 768  */
 769  /* Returns < 0 if off is not valid,
 770  *       1 if window access is needed. 'off' is set to offset from
 771  *         CRB space in 128M pci map
 772  *       0 if no window access is needed. 'off' is set to 2M addr
 773  * In: 'off' is offset from base in 128M pci map
 774  */
 775 static int
 776 qlcnic_pci_get_crb_addr_2M(struct qlcnic_adapter *adapter,
 777                 ulong off, void __iomem **addr)
 778 {
 779         const struct crb_128M_2M_sub_block_map *m;
 780
 781         if ((off >= QLCNIC_CRB_MAX) || (off < QLCNIC_PCI_CRBSPACE))
 782                 return -EINVAL;
 783
 784         off -= QLCNIC_PCI_CRBSPACE;
 785
 786         /*
 787          * Try direct map
 788          */
 789         m = &crb_128M_2M_map[CRB_BLK(off)].sub_block[CRB_SUBBLK(off)];
 790
 791         if (m->valid && (m->start_128M <= off) && (m->end_128M > off)) {
 792                 *addr = adapter->ahw.pci_base0 + m->start_2M +
 793                         (off - m->start_128M);
 794                 return 0;
 795         }
 796
 797         /*
 798          * Not in direct map, use crb window
 799          */
 800         *addr = adapter->ahw.pci_base0 + CRB_INDIRECT_2M + (off & MASK(16));
 801         return 1;
 802 }
 803
 804 /*
 805  * In: 'off' is offset from CRB space in 128M pci map
 806  * Out: 'off' is 2M pci map addr
 807  * side effect: lock crb window
 808  */
 809 static int
 810 qlcnic_pci_set_crbwindow_2M(struct qlcnic_adapter *adapter, ulong off)
 811 {
 812         u32 window;
 813         void __iomem *addr = adapter->ahw.pci_base0 + CRB_WINDOW_2M;
 814
 815         off -= QLCNIC_PCI_CRBSPACE;
 816
 817         window = CRB_HI(off);
 818         if (window == 0) {
 819                 dev_err(&adapter->pdev->dev, "Invalid offset 0x%lx\n", off);
 820                 return -EIO;
 821         }
 822
 823         writel(window, addr);
 824         if (readl(addr) != window) {
 825                 if (printk_ratelimit())
 826                         dev_warn(&adapter->pdev->dev,
 827                                 "failed to set CRB window to %d off 0x%lx\n",
 828                                 window, off);
 829                 return -EIO;
 830         }
 831         return 0;
 832 }
 833
 834 int
 835 qlcnic_hw_write_wx_2M(struct qlcnic_adapter *adapter, ulong off, u32 data)
 836 {
 837         unsigned long flags;
 838         int rv;
 839         void __iomem *addr = NULL;
 840
 841         rv = qlcnic_pci_get_crb_addr_2M(adapter, off, &addr);
 842
 843         if (rv == 0) {
 844                 writel(data, addr);
 845                 return 0;
 846         }
 847
 848         if (rv > 0) {
 849                 /* indirect access */
 850                 write_lock_irqsave(&adapter->ahw.crb_lock, flags);
 851                 crb_win_lock(adapter);
 852                 rv = qlcnic_pci_set_crbwindow_2M(adapter, off);
 853                 if (!rv)
 854                         writel(data, addr);
 855                 crb_win_unlock(adapter);
 856                 write_unlock_irqrestore(&adapter->ahw.crb_lock, flags);
 857                 return rv;
 858         }
 859
 860         dev_err(&adapter->pdev->dev,
 861                         "%s: invalid offset: 0x%016lx\n", __func__, off);
 862         dump_stack();
 863         return -EIO;
 864 }
 865
 866 u32
 867 qlcnic_hw_read_wx_2M(struct qlcnic_adapter *adapter, ulong off)
 868 {
 869         unsigned long flags;
 870         int rv;
 871         u32 data = -1;
 872         void __iomem *addr = NULL;
 873
 874         rv = qlcnic_pci_get_crb_addr_2M(adapter, off, &addr);
 875
 876         if (rv == 0)
 877                 return readl(addr);
 878
 879         if (rv > 0) {
 880                 /* indirect access */
 881                 write_lock_irqsave(&adapter->ahw.crb_lock, flags);
 882                 crb_win_lock(adapter);
 883                 if (!qlcnic_pci_set_crbwindow_2M(adapter, off))
 884                         data = readl(addr);
 885                 crb_win_unlock(adapter);
 886                 write_unlock_irqrestore(&adapter->ahw.crb_lock, flags);
 887                 return data;
 888         }
 889
 890         dev_err(&adapter->pdev->dev,
 891                         "%s: invalid offset: 0x%016lx\n", __func__, off);
 892         dump_stack();
 893         return -1;
 894 }
 895
 896
 897 void __iomem *
 898 qlcnic_get_ioaddr(struct qlcnic_adapter *adapter, u32 offset)
 899 {
 900         void __iomem *addr = NULL;
 901
 902         WARN_ON(qlcnic_pci_get_crb_addr_2M(adapter, offset, &addr));
 903
 904         return addr;
 905 }
 906
 907
 908 static int
 909 qlcnic_pci_set_window_2M(struct qlcnic_adapter *adapter,
 910                 u64 addr, u32 *start)
 911 {
 912         u32 window;
 913
 914         window = OCM_WIN_P3P(addr);
 915
 916         writel(window, adapter->ahw.ocm_win_crb);
 917         /* read back to flush */
 918         readl(adapter->ahw.ocm_win_crb);
 919
 920         *start = QLCNIC_PCI_OCM0_2M + GET_MEM_OFFS_2M(addr);
 921         return 0;
 922 }
 923
 924 static int
 925 qlcnic_pci_mem_access_direct(struct qlcnic_adapter *adapter, u64 off,
 926                 u64 *data, int op)
 927 {
 928         void __iomem *addr;
 929         int ret;
 930         u32 start;
 931
 932         mutex_lock(&adapter->ahw.mem_lock);
 933
 934         ret = qlcnic_pci_set_window_2M(adapter, off, &start);
 935         if (ret != 0)
 936                 goto unlock;
 937
 938         addr = adapter->ahw.pci_base0 + start;
 939
 940         if (op == 0)    /* read */
 941                 *data = readq(addr);
 942         else            /* write */
 943                 writeq(*data, addr);
 944
 945 unlock:
 946         mutex_unlock(&adapter->ahw.mem_lock);
 947
 948         return ret;
 949 }
 950
 951 void
 952 qlcnic_pci_camqm_read_2M(struct qlcnic_adapter *adapter, u64 off, u64 *data)
 953 {
 954         void __iomem *addr = adapter->ahw.pci_base0 +
 955                 QLCNIC_PCI_CAMQM_2M_BASE + (off - QLCNIC_PCI_CAMQM);
 956
 957         mutex_lock(&adapter->ahw.mem_lock);
 958         *data = readq(addr);
 959         mutex_unlock(&adapter->ahw.mem_lock);
 960 }
 961
 962 void
 963 qlcnic_pci_camqm_write_2M(struct qlcnic_adapter *adapter, u64 off, u64 data)
 964 {
 965         void __iomem *addr = adapter->ahw.pci_base0 +
 966                 QLCNIC_PCI_CAMQM_2M_BASE + (off - QLCNIC_PCI_CAMQM);
 967
 968         mutex_lock(&adapter->ahw.mem_lock);
 969         writeq(data, addr);
 970         mutex_unlock(&adapter->ahw.mem_lock);
 971 }
 972
 973 #define MAX_CTL_CHECK   1000
 974
 975 int
 976 qlcnic_pci_mem_write_2M(struct qlcnic_adapter *adapter,
 977                 u64 off, u64 data)
 978 {
 979         int i, j, ret;
 980         u32 temp, off8;
 981         void __iomem *mem_crb;
 982
 983         /* Only 64-bit aligned access */
 984         if (off & 7)
 985                 return -EIO;
 986
 987         /* P3 onward, test agent base for MIU and SIU is same */
 988         if (ADDR_IN_RANGE(off, QLCNIC_ADDR_QDR_NET,
 989                                 QLCNIC_ADDR_QDR_NET_MAX)) {
 990                 mem_crb = qlcnic_get_ioaddr(adapter,
 991                                 QLCNIC_CRB_QDR_NET+MIU_TEST_AGT_BASE);
 992                 goto correct;
 993         }
 994
 995         if (ADDR_IN_RANGE(off, QLCNIC_ADDR_DDR_NET, QLCNIC_ADDR_DDR_NET_MAX)) {
 996                 mem_crb = qlcnic_get_ioaddr(adapter,
 997                                 QLCNIC_CRB_DDR_NET+MIU_TEST_AGT_BASE);
 998                 goto correct;
 999         }
1000
1001         if (ADDR_IN_RANGE(off, QLCNIC_ADDR_OCM0, QLCNIC_ADDR_OCM0_MAX))
1002                 return qlcnic_pci_mem_access_direct(adapter, off, &data, 1);
1003
1004         return -EIO;
1005
1006 correct:
1007         off8 = off & ~0xf;
1008
1009         mutex_lock(&adapter->ahw.mem_lock);
1010
1011         writel(off8, (mem_crb + MIU_TEST_AGT_ADDR_LO));
1012         writel(0, (mem_crb + MIU_TEST_AGT_ADDR_HI));
1013
1014         i = 0;
1015         writel(TA_CTL_ENABLE, (mem_crb + TEST_AGT_CTRL));
1016         writel((TA_CTL_START | TA_CTL_ENABLE),
1017                         (mem_crb + TEST_AGT_CTRL));
1018
1019         for (j = 0; j < MAX_CTL_CHECK; j++) {
1020                 temp = readl(mem_crb + TEST_AGT_CTRL);
1021                 if ((temp & TA_CTL_BUSY) == 0)
1022                         break;
1023         }
1024
1025         if (j >= MAX_CTL_CHECK) {
1026                 ret = -EIO;
1027                 goto done;
1028         }
1029
1030         i = (off & 0xf) ? 0 : 2;
1031         writel(readl(mem_crb + MIU_TEST_AGT_RDDATA(i)),
1032                         mem_crb + MIU_TEST_AGT_WRDATA(i));
1033         writel(readl(mem_crb + MIU_TEST_AGT_RDDATA(i+1)),
1034                         mem_crb + MIU_TEST_AGT_WRDATA(i+1));
1035         i = (off & 0xf) ? 2 : 0;
1036
1037         writel(data & 0xffffffff,
1038                         mem_crb + MIU_TEST_AGT_WRDATA(i));
1039         writel((data >> 32) & 0xffffffff,
1040                         mem_crb + MIU_TEST_AGT_WRDATA(i+1));
1041
1042         writel((TA_CTL_ENABLE | TA_CTL_WRITE), (mem_crb + TEST_AGT_CTRL));
1043         writel((TA_CTL_START | TA_CTL_ENABLE | TA_CTL_WRITE),
1044                         (mem_crb + TEST_AGT_CTRL));
1045
1046         for (j = 0; j < MAX_CTL_CHECK; j++) {
1047                 temp = readl(mem_crb + TEST_AGT_CTRL);
1048                 if ((temp & TA_CTL_BUSY) == 0)
1049                         break;
1050         }
1051
1052         if (j >= MAX_CTL_CHECK) {
1053                 if (printk_ratelimit())
1054                         dev_err(&adapter->pdev->dev,
1055                                         "failed to write through agent\n");
1056                 ret = -EIO;
1057         } else
1058                 ret = 0;
1059
1060 done:
1061         mutex_unlock(&adapter->ahw.mem_lock);
1062
1063         return ret;
1064 }
1065
1066 int
1067 qlcnic_pci_mem_read_2M(struct qlcnic_adapter *adapter,
1068                 u64 off, u64 *data)
1069 {
1070         int j, ret;
1071         u32 temp, off8;
1072         u64 val;
1073         void __iomem *mem_crb;
1074
1075         /* Only 64-bit aligned access */
1076         if (off & 7)
1077                 return -EIO;
1078
1079         /* P3 onward, test agent base for MIU and SIU is same */
1080         if (ADDR_IN_RANGE(off, QLCNIC_ADDR_QDR_NET,
1081                                 QLCNIC_ADDR_QDR_NET_MAX)) {
1082                 mem_crb = qlcnic_get_ioaddr(adapter,
1083                                 QLCNIC_CRB_QDR_NET+MIU_TEST_AGT_BASE);
1084                 goto correct;
1085         }
1086
1087         if (ADDR_IN_RANGE(off, QLCNIC_ADDR_DDR_NET, QLCNIC_ADDR_DDR_NET_MAX)) {
1088                 mem_crb = qlcnic_get_ioaddr(adapter,
1089                                 QLCNIC_CRB_DDR_NET+MIU_TEST_AGT_BASE);
1090                 goto correct;
1091         }
1092
1093         if (ADDR_IN_RANGE(off, QLCNIC_ADDR_OCM0, QLCNIC_ADDR_OCM0_MAX)) {
1094                 return qlcnic_pci_mem_access_direct(adapter,
1095                                 off, data, 0);
1096         }
1097
1098         return -EIO;
1099
1100 correct:
1101         off8 = off & ~0xf;
1102
1103         mutex_lock(&adapter->ahw.mem_lock);
1104
1105         writel(off8, (mem_crb + MIU_TEST_AGT_ADDR_LO));
1106         writel(0, (mem_crb + MIU_TEST_AGT_ADDR_HI));
1107         writel(TA_CTL_ENABLE, (mem_crb + TEST_AGT_CTRL));
1108         writel((TA_CTL_START | TA_CTL_ENABLE), (mem_crb + TEST_AGT_CTRL));
1109
1110         for (j = 0; j < MAX_CTL_CHECK; j++) {
1111                 temp = readl(mem_crb + TEST_AGT_CTRL);
1112                 if ((temp & TA_CTL_BUSY) == 0)
1113                         break;
1114         }
1115
1116         if (j >= MAX_CTL_CHECK) {
1117                 if (printk_ratelimit())
1118                         dev_err(&adapter->pdev->dev,
1119                                         "failed to read through agent\n");
1120                 ret = -EIO;
1121         } else {
1122                 off8 = MIU_TEST_AGT_RDDATA_LO;
1123                 if (off & 0xf)
1124                         off8 = MIU_TEST_AGT_RDDATA_UPPER_LO;
1125
1126                 temp = readl(mem_crb + off8 + 4);
1127                 val = (u64)temp << 32;
1128                 val |= readl(mem_crb + off8);
1129                 *data = val;
1130                 ret = 0;
1131         }
1132
1133         mutex_unlock(&adapter->ahw.mem_lock);
1134
1135         return ret;
1136 }
1137
1138 int qlcnic_get_board_info(struct qlcnic_adapter *adapter)
1139 {
1140         int offset, board_type, magic;
1141         struct pci_dev *pdev = adapter->pdev;
1142
1143         offset = QLCNIC_FW_MAGIC_OFFSET;
1144         if (qlcnic_rom_fast_read(adapter, offset, &magic))
1145                 return -EIO;
1146
1147         if (magic != QLCNIC_BDINFO_MAGIC) {
1148                 dev_err(&pdev->dev, "invalid board config, magic=%08x\n",
1149                         magic);
1150                 return -EIO;
1151         }
1152
1153         offset = QLCNIC_BRDTYPE_OFFSET;
1154         if (qlcnic_rom_fast_read(adapter, offset, &board_type))
1155                 return -EIO;
1156
1157         adapter->ahw.board_type = board_type;
1158
1159         if (board_type == QLCNIC_BRDTYPE_P3_4_GB_MM) {
1160                 u32 gpio = QLCRD32(adapter, QLCNIC_ROMUSB_GLB_PAD_GPIO_I);
1161                 if ((gpio & 0x8000) == 0)
1162                         board_type = QLCNIC_BRDTYPE_P3_10G_TP;
1163         }
1164
1165         switch (board_type) {
1166         case QLCNIC_BRDTYPE_P3_HMEZ:
1167         case QLCNIC_BRDTYPE_P3_XG_LOM:
1168         case QLCNIC_BRDTYPE_P3_10G_CX4:
1169         case QLCNIC_BRDTYPE_P3_10G_CX4_LP:
1170         case QLCNIC_BRDTYPE_P3_IMEZ:
1171         case QLCNIC_BRDTYPE_P3_10G_SFP_PLUS:
1172         case QLCNIC_BRDTYPE_P3_10G_SFP_CT:
1173         case QLCNIC_BRDTYPE_P3_10G_SFP_QT:
1174         case QLCNIC_BRDTYPE_P3_10G_XFP:
1175         case QLCNIC_BRDTYPE_P3_10000_BASE_T:
1176                 adapter->ahw.port_type = QLCNIC_XGBE;
1177                 break;
1178         case QLCNIC_BRDTYPE_P3_REF_QG:
1179         case QLCNIC_BRDTYPE_P3_4_GB:
1180         case QLCNIC_BRDTYPE_P3_4_GB_MM:
1181                 adapter->ahw.port_type = QLCNIC_GBE;
1182                 break;
1183         case QLCNIC_BRDTYPE_P3_10G_TP:
1184                 adapter->ahw.port_type = (adapter->portnum < 2) ?
1185                         QLCNIC_XGBE : QLCNIC_GBE;
1186                 break;
1187         default:
1188                 dev_err(&pdev->dev, "unknown board type %x\n", board_type);
1189                 adapter->ahw.port_type = QLCNIC_XGBE;
1190                 break;
1191         }
1192
1193         return 0;
1194 }
1195
1196 int
1197 qlcnic_wol_supported(struct qlcnic_adapter *adapter)
1198 {
1199         u32 wol_cfg;
1200
1201         wol_cfg = QLCRD32(adapter, QLCNIC_WOL_CONFIG_NV);
1202         if (wol_cfg & (1UL << adapter->portnum)) {
1203                 wol_cfg = QLCRD32(adapter, QLCNIC_WOL_CONFIG);
1204                 if (wol_cfg & (1 << adapter->portnum))
1205                         return 1;
1206         }
1207
1208         return 0;
1209 }
1210
1211 int qlcnic_config_led(struct qlcnic_adapter *adapter, u32 state, u32 rate)
1212 {
1213         struct qlcnic_nic_req   req;
1214         int rv;
1215         u64 word;
1216
1217         memset(&req, 0, sizeof(struct qlcnic_nic_req));
1218         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
1219
1220         word = QLCNIC_H2C_OPCODE_CONFIG_LED | ((u64)adapter->portnum << 16);
1221         req.req_hdr = cpu_to_le64(word);
1222
1223         req.words[0] = cpu_to_le64((u64)rate << 32);
1224         req.words[1] = cpu_to_le64(state);
1225
1226         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
1227         if (rv)
1228                 dev_err(&adapter->pdev->dev, "LED configuration failed.\n");
1229
1230         return rv;
1231 }
1232
1233 static int qlcnic_set_fw_loopback(struct qlcnic_adapter *adapter, u32 flag)
1234 {
1235         struct qlcnic_nic_req   req;
1236         int                     rv;
1237         u64                     word;
1238
1239         memset(&req, 0, sizeof(struct qlcnic_nic_req));
1240         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
1241
1242         word = QLCNIC_H2C_OPCODE_CONFIG_LOOPBACK |
1243                         ((u64)adapter->portnum << 16);
1244         req.req_hdr = cpu_to_le64(word);
1245         req.words[0] = cpu_to_le64(flag);
1246
1247         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
1248         if (rv)
1249                 dev_err(&adapter->pdev->dev,
1250                         "%sting loopback mode failed.\n",
1251                                         flag ? "Set" : "Reset");
1252         return rv;
1253 }
1254
1255 int qlcnic_set_ilb_mode(struct qlcnic_adapter *adapter)
1256 {
1257         if (qlcnic_set_fw_loopback(adapter, 1))
1258                 return -EIO;
1259
1260         if (qlcnic_nic_set_promisc(adapter,
1261                                 VPORT_MISS_MODE_ACCEPT_ALL)) {
1262                 qlcnic_set_fw_loopback(adapter, 0);
1263                 return -EIO;
1264         }
1265
1266         msleep(1000);
1267         return 0;
1268 }
1269
1270 void qlcnic_clear_ilb_mode(struct qlcnic_adapter *adapter)
1271 {
1272         int mode = VPORT_MISS_MODE_DROP;
1273         struct net_device *netdev = adapter->netdev;
1274
1275         qlcnic_set_fw_loopback(adapter, 0);
1276
1277         if (netdev->flags & IFF_PROMISC)
1278                 mode = VPORT_MISS_MODE_ACCEPT_ALL;
1279         else if (netdev->flags & IFF_ALLMULTI)
1280                 mode = VPORT_MISS_MODE_ACCEPT_MULTI;
1281
1282         qlcnic_nic_set_promisc(adapter, mode);
1283         msleep(1000);
1284 }