2 * QLogic QLA41xx NIC HBA Driver
3 * Copyright (c) 2003-2006 QLogic Corporation
5 * See LICENSE.qlge for copyright and licensing details.
10 #include <linux/pci.h>
11 #include <linux/netdevice.h>
12 #include <linux/rtnetlink.h>
15 * General definitions...
17 #define DRV_NAME "qlge"
18 #define DRV_STRING "QLogic 10 Gigabit PCI-E Ethernet Driver "
19 #define DRV_VERSION "v1.00.00.23.00.00-01"
22 #define QPRINTK(qdev, nlevel, klevel, fmt, args...) \
24 if (!((qdev)->msg_enable & NETIF_MSG_##nlevel)) \
27 dev_printk(KERN_##klevel, &((qdev)->pdev->dev), \
28 "%s: " fmt, __func__, ##args); \
31 #define WQ_ADDR_ALIGN 0x3 /* 4 byte alignment */
33 #define QLGE_VENDOR_ID 0x1077
34 #define QLGE_DEVICE_ID_8012 0x8012
35 #define QLGE_DEVICE_ID_8000 0x8000
37 #define MAX_TX_RINGS MAX_CPUS
38 #define MAX_RX_RINGS ((MAX_CPUS * 2) + 1)
40 #define NUM_TX_RING_ENTRIES 256
41 #define NUM_RX_RING_ENTRIES 256
43 #define NUM_SMALL_BUFFERS 512
44 #define NUM_LARGE_BUFFERS 512
45 #define DB_PAGE_SIZE 4096
47 /* Calculate the number of (4k) pages required to
48 * contain a buffer queue of the given length.
50 #define MAX_DB_PAGES_PER_BQ(x) \
51 (((x * sizeof(u64)) / DB_PAGE_SIZE) + \
52 (((x * sizeof(u64)) % DB_PAGE_SIZE) ? 1 : 0))
54 #define RX_RING_SHADOW_SPACE (sizeof(u64) + \
55 MAX_DB_PAGES_PER_BQ(NUM_SMALL_BUFFERS) * sizeof(u64) + \
56 MAX_DB_PAGES_PER_BQ(NUM_LARGE_BUFFERS) * sizeof(u64))
57 #define LARGE_BUFFER_MAX_SIZE 8192
58 #define LARGE_BUFFER_MIN_SIZE 2048
61 #define DFLT_COALESCE_WAIT 100 /* 100 usec wait for coalescing */
62 #define MAX_INTER_FRAME_WAIT 10 /* 10 usec max interframe-wait for coalescing */
63 #define DFLT_INTER_FRAME_WAIT (MAX_INTER_FRAME_WAIT/2)
64 #define UDELAY_COUNT 3
65 #define UDELAY_DELAY 100
68 #define TX_DESC_PER_IOCB 8
69 /* The maximum number of frags we handle is based
72 #if (PAGE_SHIFT == 12) || (PAGE_SHIFT == 13) /* 4k & 8k pages */
73 #define TX_DESC_PER_OAL ((MAX_SKB_FRAGS - TX_DESC_PER_IOCB) + 2)
74 #else /* all other page sizes */
75 #define TX_DESC_PER_OAL 0
78 /* Word shifting for converting 64-bit
79 * address to a series of 16-bit words.
80 * This is used for some MPI firmware
83 #define LSW(x) ((u16)(x))
84 #define MSW(x) ((u16)((u32)(x) >> 16))
85 #define LSD(x) ((u32)((u64)(x)))
86 #define MSD(x) ((u32)((((u64)(x)) >> 32)))
88 /* MPI test register definitions. This register
89 * is used for determining alternate NIC function's
93 MPI_TEST_FUNC_PORT_CFG = 0x1002,
94 MPI_TEST_FUNC_PRB_CTL = 0x100e,
95 MPI_TEST_FUNC_PRB_EN = 0x18a20000,
96 MPI_TEST_FUNC_RST_STS = 0x100a,
97 MPI_TEST_FUNC_RST_FRC = 0x00000003,
98 MPI_TEST_NIC_FUNC_MASK = 0x00000007,
99 MPI_TEST_NIC1_FUNCTION_ENABLE = (1 << 0),
100 MPI_TEST_NIC1_FUNCTION_MASK = 0x0000000e,
101 MPI_TEST_NIC1_FUNC_SHIFT = 1,
102 MPI_TEST_NIC2_FUNCTION_ENABLE = (1 << 4),
103 MPI_TEST_NIC2_FUNCTION_MASK = 0x000000e0,
104 MPI_TEST_NIC2_FUNC_SHIFT = 5,
105 MPI_TEST_FC1_FUNCTION_ENABLE = (1 << 8),
106 MPI_TEST_FC1_FUNCTION_MASK = 0x00000e00,
107 MPI_TEST_FC1_FUNCTION_SHIFT = 9,
108 MPI_TEST_FC2_FUNCTION_ENABLE = (1 << 12),
109 MPI_TEST_FC2_FUNCTION_MASK = 0x0000e000,
110 MPI_TEST_FC2_FUNCTION_SHIFT = 13,
112 MPI_NIC_READ = 0x00000000,
113 MPI_NIC_REG_BLOCK = 0x00020000,
114 MPI_NIC_FUNCTION_SHIFT = 6,
118 * Processor Address Register (PROC_ADDR) bit definitions.
126 PROC_ADDR_RDY = (1 << 31),
127 PROC_ADDR_R = (1 << 30),
128 PROC_ADDR_ERR = (1 << 29),
129 PROC_ADDR_DA = (1 << 28),
130 PROC_ADDR_FUNC0_MBI = 0x00001180,
131 PROC_ADDR_FUNC0_MBO = (PROC_ADDR_FUNC0_MBI + MAILBOX_COUNT),
132 PROC_ADDR_FUNC0_CTL = 0x000011a1,
133 PROC_ADDR_FUNC2_MBI = 0x00001280,
134 PROC_ADDR_FUNC2_MBO = (PROC_ADDR_FUNC2_MBI + MAILBOX_COUNT),
135 PROC_ADDR_FUNC2_CTL = 0x000012a1,
136 PROC_ADDR_MPI_RISC = 0x00000000,
137 PROC_ADDR_MDE = 0x00010000,
138 PROC_ADDR_REGBLOCK = 0x00020000,
139 PROC_ADDR_RISC_REG = 0x00030000,
143 * System Register (SYS) bit definitions.
152 SYS_OMP_DLY_MASK = 0x3f000000,
154 * There are no values defined as of edit #15.
160 * Reset/Failover Register (RST_FO) bit definitions.
163 RST_FO_TFO = (1 << 0),
164 RST_FO_RR_MASK = 0x00060000,
165 RST_FO_RR_CQ_CAM = 0x00000000,
166 RST_FO_RR_DROP = 0x00000002,
167 RST_FO_RR_DQ = 0x00000004,
168 RST_FO_RR_RCV_FUNC_CQ = 0x00000006,
169 RST_FO_FRB = (1 << 12),
170 RST_FO_MOP = (1 << 13),
171 RST_FO_REG = (1 << 14),
172 RST_FO_FR = (1 << 15),
176 * Function Specific Control Register (FSC) bit definitions.
179 FSC_DBRST_MASK = 0x00070000,
180 FSC_DBRST_256 = 0x00000000,
181 FSC_DBRST_512 = 0x00000001,
182 FSC_DBRST_768 = 0x00000002,
183 FSC_DBRST_1024 = 0x00000003,
184 FSC_DBL_MASK = 0x00180000,
185 FSC_DBL_DBRST = 0x00000000,
186 FSC_DBL_MAX_PLD = 0x00000008,
187 FSC_DBL_MAX_BRST = 0x00000010,
188 FSC_DBL_128_BYTES = 0x00000018,
190 FSC_EPC_MASK = 0x00c00000,
191 FSC_EPC_INBOUND = (1 << 6),
192 FSC_EPC_OUTBOUND = (1 << 7),
193 FSC_VM_PAGESIZE_MASK = 0x07000000,
194 FSC_VM_PAGE_2K = 0x00000100,
195 FSC_VM_PAGE_4K = 0x00000200,
196 FSC_VM_PAGE_8K = 0x00000300,
197 FSC_VM_PAGE_64K = 0x00000600,
205 * Host Command Status Register (CSR) bit definitions.
208 CSR_ERR_STS_MASK = 0x0000003f,
210 * There are no valued defined as of edit #15.
215 CSR_CMD_PARM_SHIFT = 22,
216 CSR_CMD_NOP = 0x00000000,
217 CSR_CMD_SET_RST = 0x10000000,
218 CSR_CMD_CLR_RST = 0x20000000,
219 CSR_CMD_SET_PAUSE = 0x30000000,
220 CSR_CMD_CLR_PAUSE = 0x40000000,
221 CSR_CMD_SET_H2R_INT = 0x50000000,
222 CSR_CMD_CLR_H2R_INT = 0x60000000,
223 CSR_CMD_PAR_EN = 0x70000000,
224 CSR_CMD_SET_BAD_PAR = 0x80000000,
225 CSR_CMD_CLR_BAD_PAR = 0x90000000,
226 CSR_CMD_CLR_R2PCI_INT = 0xa0000000,
230 * Configuration Register (CFG) bit definitions.
241 CFG_Q_MASK = 0x7f000000,
245 * Status Register (STS) bit definitions.
254 STS_FUNC_ID_MASK = 0x000000c0,
255 STS_FUNC_ID_SHIFT = 6,
264 * Interrupt Enable Register (INTR_EN) bit definitions.
267 INTR_EN_INTR_MASK = 0x007f0000,
268 INTR_EN_TYPE_MASK = 0x03000000,
269 INTR_EN_TYPE_ENABLE = 0x00000100,
270 INTR_EN_TYPE_DISABLE = 0x00000200,
271 INTR_EN_TYPE_READ = 0x00000300,
272 INTR_EN_IHD = (1 << 13),
273 INTR_EN_IHD_MASK = (INTR_EN_IHD << 16),
274 INTR_EN_EI = (1 << 14),
275 INTR_EN_EN = (1 << 15),
279 * Interrupt Mask Register (INTR_MASK) bit definitions.
282 INTR_MASK_PI = (1 << 0),
283 INTR_MASK_HL0 = (1 << 1),
284 INTR_MASK_LH0 = (1 << 2),
285 INTR_MASK_HL1 = (1 << 3),
286 INTR_MASK_LH1 = (1 << 4),
287 INTR_MASK_SE = (1 << 5),
288 INTR_MASK_LSC = (1 << 6),
289 INTR_MASK_MC = (1 << 7),
290 INTR_MASK_LINK_IRQS = INTR_MASK_LSC | INTR_MASK_SE | INTR_MASK_MC,
294 * Register (REV_ID) bit definitions.
297 REV_ID_MASK = 0x0000000f,
298 REV_ID_NICROLL_SHIFT = 0,
299 REV_ID_NICREV_SHIFT = 4,
300 REV_ID_XGROLL_SHIFT = 8,
301 REV_ID_XGREV_SHIFT = 12,
302 REV_ID_CHIPREV_SHIFT = 28,
306 * Force ECC Error Register (FRC_ECC_ERR) bit definitions.
309 FRC_ECC_ERR_VW = (1 << 12),
310 FRC_ECC_ERR_VB = (1 << 13),
311 FRC_ECC_ERR_NI = (1 << 14),
312 FRC_ECC_ERR_NO = (1 << 15),
313 FRC_ECC_PFE_SHIFT = 16,
314 FRC_ECC_ERR_DO = (1 << 18),
315 FRC_ECC_P14 = (1 << 19),
319 * Error Status Register (ERR_STS) bit definitions.
322 ERR_STS_NOF = (1 << 0),
323 ERR_STS_NIF = (1 << 1),
324 ERR_STS_DRP = (1 << 2),
325 ERR_STS_XGP = (1 << 3),
326 ERR_STS_FOU = (1 << 4),
327 ERR_STS_FOC = (1 << 5),
328 ERR_STS_FOF = (1 << 6),
329 ERR_STS_FIU = (1 << 7),
330 ERR_STS_FIC = (1 << 8),
331 ERR_STS_FIF = (1 << 9),
332 ERR_STS_MOF = (1 << 10),
333 ERR_STS_TA = (1 << 11),
334 ERR_STS_MA = (1 << 12),
335 ERR_STS_MPE = (1 << 13),
336 ERR_STS_SCE = (1 << 14),
337 ERR_STS_STE = (1 << 15),
338 ERR_STS_FOW = (1 << 16),
339 ERR_STS_UE = (1 << 17),
340 ERR_STS_MCH = (1 << 26),
341 ERR_STS_LOC_SHIFT = 27,
345 * RAM Debug Address Register (RAM_DBG_ADDR) bit definitions.
348 RAM_DBG_ADDR_FW = (1 << 30),
349 RAM_DBG_ADDR_FR = (1 << 31),
353 * Semaphore Register (SEM) bit definitions.
358 * reg = SEM_XGMAC0_MASK | (SEM_SET << SEM_XGMAC0_SHIFT)
363 SEM_XGMAC0_SHIFT = 0,
364 SEM_XGMAC1_SHIFT = 2,
366 SEM_MAC_ADDR_SHIFT = 6,
368 SEM_PROBE_SHIFT = 10,
369 SEM_RT_IDX_SHIFT = 12,
370 SEM_PROC_REG_SHIFT = 14,
371 SEM_XGMAC0_MASK = 0x00030000,
372 SEM_XGMAC1_MASK = 0x000c0000,
373 SEM_ICB_MASK = 0x00300000,
374 SEM_MAC_ADDR_MASK = 0x00c00000,
375 SEM_FLASH_MASK = 0x03000000,
376 SEM_PROBE_MASK = 0x0c000000,
377 SEM_RT_IDX_MASK = 0x30000000,
378 SEM_PROC_REG_MASK = 0xc0000000,
382 * 10G MAC Address Register (XGMAC_ADDR) bit definitions.
385 XGMAC_ADDR_RDY = (1 << 31),
386 XGMAC_ADDR_R = (1 << 30),
387 XGMAC_ADDR_XME = (1 << 29),
389 /* XGMAC control registers */
390 PAUSE_SRC_LO = 0x00000100,
391 PAUSE_SRC_HI = 0x00000104,
392 GLOBAL_CFG = 0x00000108,
393 GLOBAL_CFG_RESET = (1 << 0),
394 GLOBAL_CFG_JUMBO = (1 << 6),
395 GLOBAL_CFG_TX_STAT_EN = (1 << 10),
396 GLOBAL_CFG_RX_STAT_EN = (1 << 11),
398 TX_CFG_RESET = (1 << 0),
399 TX_CFG_EN = (1 << 1),
400 TX_CFG_PREAM = (1 << 2),
402 RX_CFG_RESET = (1 << 0),
403 RX_CFG_EN = (1 << 1),
404 RX_CFG_PREAM = (1 << 2),
405 FLOW_CTL = 0x0000011c,
406 PAUSE_OPCODE = 0x00000120,
407 PAUSE_TIMER = 0x00000124,
408 PAUSE_FRM_DEST_LO = 0x00000128,
409 PAUSE_FRM_DEST_HI = 0x0000012c,
410 MAC_TX_PARAMS = 0x00000134,
411 MAC_TX_PARAMS_JUMBO = (1 << 31),
412 MAC_TX_PARAMS_SIZE_SHIFT = 16,
413 MAC_RX_PARAMS = 0x00000138,
414 MAC_SYS_INT = 0x00000144,
415 MAC_SYS_INT_MASK = 0x00000148,
416 MAC_MGMT_INT = 0x0000014c,
417 MAC_MGMT_IN_MASK = 0x00000150,
418 EXT_ARB_MODE = 0x000001fc,
420 /* XGMAC TX statistics registers */
421 TX_PKTS = 0x00000200,
422 TX_BYTES = 0x00000208,
423 TX_MCAST_PKTS = 0x00000210,
424 TX_BCAST_PKTS = 0x00000218,
425 TX_UCAST_PKTS = 0x00000220,
426 TX_CTL_PKTS = 0x00000228,
427 TX_PAUSE_PKTS = 0x00000230,
428 TX_64_PKT = 0x00000238,
429 TX_65_TO_127_PKT = 0x00000240,
430 TX_128_TO_255_PKT = 0x00000248,
431 TX_256_511_PKT = 0x00000250,
432 TX_512_TO_1023_PKT = 0x00000258,
433 TX_1024_TO_1518_PKT = 0x00000260,
434 TX_1519_TO_MAX_PKT = 0x00000268,
435 TX_UNDERSIZE_PKT = 0x00000270,
436 TX_OVERSIZE_PKT = 0x00000278,
438 /* XGMAC statistics control registers */
439 RX_HALF_FULL_DET = 0x000002a0,
440 TX_HALF_FULL_DET = 0x000002a4,
441 RX_OVERFLOW_DET = 0x000002a8,
442 TX_OVERFLOW_DET = 0x000002ac,
443 RX_HALF_FULL_MASK = 0x000002b0,
444 TX_HALF_FULL_MASK = 0x000002b4,
445 RX_OVERFLOW_MASK = 0x000002b8,
446 TX_OVERFLOW_MASK = 0x000002bc,
447 STAT_CNT_CTL = 0x000002c0,
448 STAT_CNT_CTL_CLEAR_TX = (1 << 0),
449 STAT_CNT_CTL_CLEAR_RX = (1 << 1),
450 AUX_RX_HALF_FULL_DET = 0x000002d0,
451 AUX_TX_HALF_FULL_DET = 0x000002d4,
452 AUX_RX_OVERFLOW_DET = 0x000002d8,
453 AUX_TX_OVERFLOW_DET = 0x000002dc,
454 AUX_RX_HALF_FULL_MASK = 0x000002f0,
455 AUX_TX_HALF_FULL_MASK = 0x000002f4,
456 AUX_RX_OVERFLOW_MASK = 0x000002f8,
457 AUX_TX_OVERFLOW_MASK = 0x000002fc,
459 /* XGMAC RX statistics registers */
460 RX_BYTES = 0x00000300,
461 RX_BYTES_OK = 0x00000308,
462 RX_PKTS = 0x00000310,
463 RX_PKTS_OK = 0x00000318,
464 RX_BCAST_PKTS = 0x00000320,
465 RX_MCAST_PKTS = 0x00000328,
466 RX_UCAST_PKTS = 0x00000330,
467 RX_UNDERSIZE_PKTS = 0x00000338,
468 RX_OVERSIZE_PKTS = 0x00000340,
469 RX_JABBER_PKTS = 0x00000348,
470 RX_UNDERSIZE_FCERR_PKTS = 0x00000350,
471 RX_DROP_EVENTS = 0x00000358,
472 RX_FCERR_PKTS = 0x00000360,
473 RX_ALIGN_ERR = 0x00000368,
474 RX_SYMBOL_ERR = 0x00000370,
475 RX_MAC_ERR = 0x00000378,
476 RX_CTL_PKTS = 0x00000380,
477 RX_PAUSE_PKTS = 0x00000388,
478 RX_64_PKTS = 0x00000390,
479 RX_65_TO_127_PKTS = 0x00000398,
480 RX_128_255_PKTS = 0x000003a0,
481 RX_256_511_PKTS = 0x000003a8,
482 RX_512_TO_1023_PKTS = 0x000003b0,
483 RX_1024_TO_1518_PKTS = 0x000003b8,
484 RX_1519_TO_MAX_PKTS = 0x000003c0,
485 RX_LEN_ERR_PKTS = 0x000003c8,
487 /* XGMAC MDIO control registers */
488 MDIO_TX_DATA = 0x00000400,
489 MDIO_RX_DATA = 0x00000410,
490 MDIO_CMD = 0x00000420,
491 MDIO_PHY_ADDR = 0x00000430,
492 MDIO_PORT = 0x00000440,
493 MDIO_STATUS = 0x00000450,
495 XGMAC_REGISTER_END = 0x00000740,
499 * Enhanced Transmission Schedule Registers (NIC_ETS,CNA_ETS) bit definitions.
502 ETS_QUEUE_SHIFT = 29,
506 ETS_FC_COS_SHIFT = 23,
510 * Flash Address Register (FLASH_ADDR) bit definitions.
513 FLASH_ADDR_RDY = (1 << 31),
514 FLASH_ADDR_R = (1 << 30),
515 FLASH_ADDR_ERR = (1 << 29),
519 * Stop CQ Processing Register (CQ_STOP) bit definitions.
522 CQ_STOP_QUEUE_MASK = (0x007f0000),
523 CQ_STOP_TYPE_MASK = (0x03000000),
524 CQ_STOP_TYPE_START = 0x00000100,
525 CQ_STOP_TYPE_STOP = 0x00000200,
526 CQ_STOP_TYPE_READ = 0x00000300,
527 CQ_STOP_EN = (1 << 15),
531 * MAC Protocol Address Index Register (MAC_ADDR_IDX) bit definitions.
534 MAC_ADDR_IDX_SHIFT = 4,
535 MAC_ADDR_TYPE_SHIFT = 16,
536 MAC_ADDR_TYPE_COUNT = 10,
537 MAC_ADDR_TYPE_MASK = 0x000f0000,
538 MAC_ADDR_TYPE_CAM_MAC = 0x00000000,
539 MAC_ADDR_TYPE_MULTI_MAC = 0x00010000,
540 MAC_ADDR_TYPE_VLAN = 0x00020000,
541 MAC_ADDR_TYPE_MULTI_FLTR = 0x00030000,
542 MAC_ADDR_TYPE_FC_MAC = 0x00040000,
543 MAC_ADDR_TYPE_MGMT_MAC = 0x00050000,
544 MAC_ADDR_TYPE_MGMT_VLAN = 0x00060000,
545 MAC_ADDR_TYPE_MGMT_V4 = 0x00070000,
546 MAC_ADDR_TYPE_MGMT_V6 = 0x00080000,
547 MAC_ADDR_TYPE_MGMT_TU_DP = 0x00090000,
548 MAC_ADDR_ADR = (1 << 25),
549 MAC_ADDR_RS = (1 << 26),
550 MAC_ADDR_E = (1 << 27),
551 MAC_ADDR_MR = (1 << 30),
552 MAC_ADDR_MW = (1 << 31),
553 MAX_MULTICAST_ENTRIES = 32,
555 /* Entry count and words per entry
556 * for each address type in the filter.
558 MAC_ADDR_MAX_CAM_ENTRIES = 512,
559 MAC_ADDR_MAX_CAM_WCOUNT = 3,
560 MAC_ADDR_MAX_MULTICAST_ENTRIES = 32,
561 MAC_ADDR_MAX_MULTICAST_WCOUNT = 2,
562 MAC_ADDR_MAX_VLAN_ENTRIES = 4096,
563 MAC_ADDR_MAX_VLAN_WCOUNT = 1,
564 MAC_ADDR_MAX_MCAST_FLTR_ENTRIES = 4096,
565 MAC_ADDR_MAX_MCAST_FLTR_WCOUNT = 1,
566 MAC_ADDR_MAX_FC_MAC_ENTRIES = 4,
567 MAC_ADDR_MAX_FC_MAC_WCOUNT = 2,
568 MAC_ADDR_MAX_MGMT_MAC_ENTRIES = 8,
569 MAC_ADDR_MAX_MGMT_MAC_WCOUNT = 2,
570 MAC_ADDR_MAX_MGMT_VLAN_ENTRIES = 16,
571 MAC_ADDR_MAX_MGMT_VLAN_WCOUNT = 1,
572 MAC_ADDR_MAX_MGMT_V4_ENTRIES = 4,
573 MAC_ADDR_MAX_MGMT_V4_WCOUNT = 1,
574 MAC_ADDR_MAX_MGMT_V6_ENTRIES = 4,
575 MAC_ADDR_MAX_MGMT_V6_WCOUNT = 4,
576 MAC_ADDR_MAX_MGMT_TU_DP_ENTRIES = 4,
577 MAC_ADDR_MAX_MGMT_TU_DP_WCOUNT = 1,
581 * MAC Protocol Address Index Register (SPLT_HDR) bit definitions.
584 SPLT_HDR_EP = (1 << 31),
588 * FCoE Receive Configuration Register (FC_RCV_CFG) bit definitions.
591 FC_RCV_CFG_ECT = (1 << 15),
592 FC_RCV_CFG_DFH = (1 << 20),
593 FC_RCV_CFG_DVF = (1 << 21),
594 FC_RCV_CFG_RCE = (1 << 27),
595 FC_RCV_CFG_RFE = (1 << 28),
596 FC_RCV_CFG_TEE = (1 << 29),
597 FC_RCV_CFG_TCE = (1 << 30),
598 FC_RCV_CFG_TFE = (1 << 31),
602 * NIC Receive Configuration Register (NIC_RCV_CFG) bit definitions.
605 NIC_RCV_CFG_PPE = (1 << 0),
606 NIC_RCV_CFG_VLAN_MASK = 0x00060000,
607 NIC_RCV_CFG_VLAN_ALL = 0x00000000,
608 NIC_RCV_CFG_VLAN_MATCH_ONLY = 0x00000002,
609 NIC_RCV_CFG_VLAN_MATCH_AND_NON = 0x00000004,
610 NIC_RCV_CFG_VLAN_NONE_AND_NON = 0x00000006,
611 NIC_RCV_CFG_RV = (1 << 3),
612 NIC_RCV_CFG_DFQ_MASK = (0x7f000000),
613 NIC_RCV_CFG_DFQ_SHIFT = 8,
614 NIC_RCV_CFG_DFQ = 0, /* HARDCODE default queue to 0. */
618 * Mgmt Receive Configuration Register (MGMT_RCV_CFG) bit definitions.
621 MGMT_RCV_CFG_ARP = (1 << 0),
622 MGMT_RCV_CFG_DHC = (1 << 1),
623 MGMT_RCV_CFG_DHS = (1 << 2),
624 MGMT_RCV_CFG_NP = (1 << 3),
625 MGMT_RCV_CFG_I6N = (1 << 4),
626 MGMT_RCV_CFG_I6R = (1 << 5),
627 MGMT_RCV_CFG_DH6 = (1 << 6),
628 MGMT_RCV_CFG_UD1 = (1 << 7),
629 MGMT_RCV_CFG_UD0 = (1 << 8),
630 MGMT_RCV_CFG_BCT = (1 << 9),
631 MGMT_RCV_CFG_MCT = (1 << 10),
632 MGMT_RCV_CFG_DM = (1 << 11),
633 MGMT_RCV_CFG_RM = (1 << 12),
634 MGMT_RCV_CFG_STL = (1 << 13),
635 MGMT_RCV_CFG_VLAN_MASK = 0xc0000000,
636 MGMT_RCV_CFG_VLAN_ALL = 0x00000000,
637 MGMT_RCV_CFG_VLAN_MATCH_ONLY = 0x00004000,
638 MGMT_RCV_CFG_VLAN_MATCH_AND_NON = 0x00008000,
639 MGMT_RCV_CFG_VLAN_NONE_AND_NON = 0x0000c000,
643 * Routing Index Register (RT_IDX) bit definitions.
646 RT_IDX_IDX_SHIFT = 8,
647 RT_IDX_TYPE_MASK = 0x000f0000,
648 RT_IDX_TYPE_SHIFT = 16,
649 RT_IDX_TYPE_RT = 0x00000000,
650 RT_IDX_TYPE_RT_INV = 0x00010000,
651 RT_IDX_TYPE_NICQ = 0x00020000,
652 RT_IDX_TYPE_NICQ_INV = 0x00030000,
653 RT_IDX_DST_MASK = 0x00700000,
654 RT_IDX_DST_RSS = 0x00000000,
655 RT_IDX_DST_CAM_Q = 0x00100000,
656 RT_IDX_DST_COS_Q = 0x00200000,
657 RT_IDX_DST_DFLT_Q = 0x00300000,
658 RT_IDX_DST_DEST_Q = 0x00400000,
659 RT_IDX_RS = (1 << 26),
660 RT_IDX_E = (1 << 27),
661 RT_IDX_MR = (1 << 30),
662 RT_IDX_MW = (1 << 31),
664 /* Nic Queue format - type 2 bits */
665 RT_IDX_BCAST = (1 << 0),
666 RT_IDX_MCAST = (1 << 1),
667 RT_IDX_MCAST_MATCH = (1 << 2),
668 RT_IDX_MCAST_REG_MATCH = (1 << 3),
669 RT_IDX_MCAST_HASH_MATCH = (1 << 4),
670 RT_IDX_FC_MACH = (1 << 5),
671 RT_IDX_ETH_FCOE = (1 << 6),
672 RT_IDX_CAM_HIT = (1 << 7),
673 RT_IDX_CAM_BIT0 = (1 << 8),
674 RT_IDX_CAM_BIT1 = (1 << 9),
675 RT_IDX_VLAN_TAG = (1 << 10),
676 RT_IDX_VLAN_MATCH = (1 << 11),
677 RT_IDX_VLAN_FILTER = (1 << 12),
678 RT_IDX_ETH_SKIP1 = (1 << 13),
679 RT_IDX_ETH_SKIP2 = (1 << 14),
680 RT_IDX_BCAST_MCAST_MATCH = (1 << 15),
681 RT_IDX_802_3 = (1 << 16),
682 RT_IDX_LLDP = (1 << 17),
683 RT_IDX_UNUSED018 = (1 << 18),
684 RT_IDX_UNUSED019 = (1 << 19),
685 RT_IDX_UNUSED20 = (1 << 20),
686 RT_IDX_UNUSED21 = (1 << 21),
687 RT_IDX_ERR = (1 << 22),
688 RT_IDX_VALID = (1 << 23),
689 RT_IDX_TU_CSUM_ERR = (1 << 24),
690 RT_IDX_IP_CSUM_ERR = (1 << 25),
691 RT_IDX_MAC_ERR = (1 << 26),
692 RT_IDX_RSS_TCP6 = (1 << 27),
693 RT_IDX_RSS_TCP4 = (1 << 28),
694 RT_IDX_RSS_IPV6 = (1 << 29),
695 RT_IDX_RSS_IPV4 = (1 << 30),
696 RT_IDX_RSS_MATCH = (1 << 31),
698 /* Hierarchy for the NIC Queue Mask */
699 RT_IDX_ALL_ERR_SLOT = 0,
700 RT_IDX_MAC_ERR_SLOT = 0,
701 RT_IDX_IP_CSUM_ERR_SLOT = 1,
702 RT_IDX_TCP_UDP_CSUM_ERR_SLOT = 2,
703 RT_IDX_BCAST_SLOT = 3,
704 RT_IDX_MCAST_MATCH_SLOT = 4,
705 RT_IDX_ALLMULTI_SLOT = 5,
706 RT_IDX_UNUSED6_SLOT = 6,
707 RT_IDX_UNUSED7_SLOT = 7,
708 RT_IDX_RSS_MATCH_SLOT = 8,
709 RT_IDX_RSS_IPV4_SLOT = 8,
710 RT_IDX_RSS_IPV6_SLOT = 9,
711 RT_IDX_RSS_TCP4_SLOT = 10,
712 RT_IDX_RSS_TCP6_SLOT = 11,
713 RT_IDX_CAM_HIT_SLOT = 12,
714 RT_IDX_UNUSED013 = 13,
715 RT_IDX_UNUSED014 = 14,
716 RT_IDX_PROMISCUOUS_SLOT = 15,
717 RT_IDX_MAX_RT_SLOTS = 8,
718 RT_IDX_MAX_NIC_SLOTS = 16,
722 * Serdes Address Register (XG_SERDES_ADDR) bit definitions.
725 XG_SERDES_ADDR_RDY = (1 << 31),
726 XG_SERDES_ADDR_R = (1 << 30),
728 XG_SERDES_ADDR_STS = 0x00001E06,
729 XG_SERDES_ADDR_XFI1_PWR_UP = 0x00000005,
730 XG_SERDES_ADDR_XFI2_PWR_UP = 0x0000000a,
731 XG_SERDES_ADDR_XAUI_PWR_DOWN = 0x00000001,
733 /* Serdes coredump definitions. */
734 XG_SERDES_XAUI_AN_START = 0x00000000,
735 XG_SERDES_XAUI_AN_END = 0x00000034,
736 XG_SERDES_XAUI_HSS_PCS_START = 0x00000800,
737 XG_SERDES_XAUI_HSS_PCS_END = 0x0000880,
738 XG_SERDES_XFI_AN_START = 0x00001000,
739 XG_SERDES_XFI_AN_END = 0x00001034,
740 XG_SERDES_XFI_TRAIN_START = 0x10001050,
741 XG_SERDES_XFI_TRAIN_END = 0x1000107C,
742 XG_SERDES_XFI_HSS_PCS_START = 0x00001800,
743 XG_SERDES_XFI_HSS_PCS_END = 0x00001838,
744 XG_SERDES_XFI_HSS_TX_START = 0x00001c00,
745 XG_SERDES_XFI_HSS_TX_END = 0x00001c1f,
746 XG_SERDES_XFI_HSS_RX_START = 0x00001c40,
747 XG_SERDES_XFI_HSS_RX_END = 0x00001c5f,
748 XG_SERDES_XFI_HSS_PLL_START = 0x00001e00,
749 XG_SERDES_XFI_HSS_PLL_END = 0x00001e1f,
753 * NIC Probe Mux Address Register (PRB_MX_ADDR) bit definitions.
756 PRB_MX_ADDR_ARE = (1 << 16),
757 PRB_MX_ADDR_UP = (1 << 15),
758 PRB_MX_ADDR_SWP = (1 << 14),
760 /* Module select values. */
761 PRB_MX_ADDR_MAX_MODS = 21,
762 PRB_MX_ADDR_MOD_SEL_SHIFT = 9,
763 PRB_MX_ADDR_MOD_SEL_TBD = 0,
764 PRB_MX_ADDR_MOD_SEL_IDE1 = 1,
765 PRB_MX_ADDR_MOD_SEL_IDE2 = 2,
766 PRB_MX_ADDR_MOD_SEL_FRB = 3,
767 PRB_MX_ADDR_MOD_SEL_ODE1 = 4,
768 PRB_MX_ADDR_MOD_SEL_ODE2 = 5,
769 PRB_MX_ADDR_MOD_SEL_DA1 = 6,
770 PRB_MX_ADDR_MOD_SEL_DA2 = 7,
771 PRB_MX_ADDR_MOD_SEL_IMP1 = 8,
772 PRB_MX_ADDR_MOD_SEL_IMP2 = 9,
773 PRB_MX_ADDR_MOD_SEL_OMP1 = 10,
774 PRB_MX_ADDR_MOD_SEL_OMP2 = 11,
775 PRB_MX_ADDR_MOD_SEL_ORS1 = 12,
776 PRB_MX_ADDR_MOD_SEL_ORS2 = 13,
777 PRB_MX_ADDR_MOD_SEL_REG = 14,
778 PRB_MX_ADDR_MOD_SEL_MAC1 = 16,
779 PRB_MX_ADDR_MOD_SEL_MAC2 = 17,
780 PRB_MX_ADDR_MOD_SEL_VQM1 = 18,
781 PRB_MX_ADDR_MOD_SEL_VQM2 = 19,
782 PRB_MX_ADDR_MOD_SEL_MOP = 20,
783 /* Bit fields indicating which modules
784 * are valid for each clock domain.
786 PRB_MX_ADDR_VALID_SYS_MOD = 0x000f7ff7,
787 PRB_MX_ADDR_VALID_PCI_MOD = 0x000040c1,
788 PRB_MX_ADDR_VALID_XGM_MOD = 0x00037309,
789 PRB_MX_ADDR_VALID_FC_MOD = 0x00003001,
790 PRB_MX_ADDR_VALID_TOTAL = 34,
792 /* Clock domain values. */
793 PRB_MX_ADDR_CLOCK_SHIFT = 6,
794 PRB_MX_ADDR_SYS_CLOCK = 0,
795 PRB_MX_ADDR_PCI_CLOCK = 2,
796 PRB_MX_ADDR_FC_CLOCK = 5,
797 PRB_MX_ADDR_XGM_CLOCK = 6,
799 PRB_MX_ADDR_MAX_MUX = 64,
803 * Control Register Set Map
806 PROC_ADDR = 0, /* Use semaphore */
807 PROC_DATA = 0x04, /* Use semaphore */
813 ICB_RID = 0x1c, /* Use semaphore */
814 ICB_L = 0x20, /* Use semaphore */
815 ICB_H = 0x24, /* Use semaphore */
832 GPIO_1 = 0x68, /* Use semaphore */
833 GPIO_2 = 0x6c, /* Use semaphore */
834 GPIO_3 = 0x70, /* Use semaphore */
836 XGMAC_ADDR = 0x78, /* Use semaphore */
837 XGMAC_DATA = 0x7c, /* Use semaphore */
840 FLASH_ADDR = 0x88, /* Use semaphore */
841 FLASH_DATA = 0x8c, /* Use semaphore */
844 WQ_PAGE_TBL_LO = 0x98,
845 WQ_PAGE_TBL_HI = 0x9c,
846 CQ_PAGE_TBL_LO = 0xa0,
847 CQ_PAGE_TBL_HI = 0xa4,
848 MAC_ADDR_IDX = 0xa8, /* Use semaphore */
849 MAC_ADDR_DATA = 0xac, /* Use semaphore */
855 FC_PAUSE_THRES = 0xc4,
856 NIC_PAUSE_THRES = 0xc8,
866 XG_SERDES_ADDR = 0xf0,
867 XG_SERDES_DATA = 0xf4,
868 PRB_MX_ADDR = 0xf8, /* Use semaphore */
869 PRB_MX_DATA = 0xfc, /* Use semaphore */
872 #ifdef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
873 #define SMALL_BUFFER_SIZE 256
874 #define SMALL_BUF_MAP_SIZE SMALL_BUFFER_SIZE
875 #define SPLT_SETTING FSC_DBRST_1024
877 #define QLGE_SB_PAD 0
879 #define SMALL_BUFFER_SIZE 512
880 #define SMALL_BUF_MAP_SIZE (SMALL_BUFFER_SIZE / 2)
881 #define SPLT_SETTING FSC_SH
882 #define SPLT_LEN (SPLT_HDR_EP | \
883 min(SMALL_BUF_MAP_SIZE, 1023))
884 #define QLGE_SB_PAD 32
891 CAM_OUT_ROUTE_FC = 0,
892 CAM_OUT_ROUTE_NIC = 1,
893 CAM_OUT_FUNC_SHIFT = 2,
894 CAM_OUT_RV = (1 << 4),
895 CAM_OUT_SH = (1 << 15),
896 CAM_OUT_CQ_ID_SHIFT = 5,
900 * Mailbox definitions
903 /* Asynchronous Event Notifications */
904 AEN_SYS_ERR = 0x00008002,
905 AEN_LINK_UP = 0x00008011,
906 AEN_LINK_DOWN = 0x00008012,
907 AEN_IDC_CMPLT = 0x00008100,
908 AEN_IDC_REQ = 0x00008101,
909 AEN_IDC_EXT = 0x00008102,
910 AEN_DCBX_CHG = 0x00008110,
911 AEN_AEN_LOST = 0x00008120,
912 AEN_AEN_SFP_IN = 0x00008130,
913 AEN_AEN_SFP_OUT = 0x00008131,
914 AEN_FW_INIT_DONE = 0x00008400,
915 AEN_FW_INIT_FAIL = 0x00008401,
917 /* Mailbox Command Opcodes. */
918 MB_CMD_NOP = 0x00000000,
919 MB_CMD_EX_FW = 0x00000002,
920 MB_CMD_MB_TEST = 0x00000006,
921 MB_CMD_CSUM_TEST = 0x00000007, /* Verify Checksum */
922 MB_CMD_ABOUT_FW = 0x00000008,
923 MB_CMD_COPY_RISC_RAM = 0x0000000a,
924 MB_CMD_LOAD_RISC_RAM = 0x0000000b,
925 MB_CMD_DUMP_RISC_RAM = 0x0000000c,
926 MB_CMD_WRITE_RAM = 0x0000000d,
927 MB_CMD_INIT_RISC_RAM = 0x0000000e,
928 MB_CMD_READ_RAM = 0x0000000f,
929 MB_CMD_STOP_FW = 0x00000014,
930 MB_CMD_MAKE_SYS_ERR = 0x0000002a,
931 MB_CMD_WRITE_SFP = 0x00000030,
932 MB_CMD_READ_SFP = 0x00000031,
933 MB_CMD_INIT_FW = 0x00000060,
934 MB_CMD_GET_IFCB = 0x00000061,
935 MB_CMD_GET_FW_STATE = 0x00000069,
936 MB_CMD_IDC_REQ = 0x00000100, /* Inter-Driver Communication */
937 MB_CMD_IDC_ACK = 0x00000101, /* Inter-Driver Communication */
938 MB_CMD_SET_WOL_MODE = 0x00000110, /* Wake On Lan */
940 MB_WOL_MAGIC_PKT = (1 << 1),
941 MB_WOL_FLTR = (1 << 2),
942 MB_WOL_UCAST = (1 << 3),
943 MB_WOL_MCAST = (1 << 4),
944 MB_WOL_BCAST = (1 << 5),
945 MB_WOL_LINK_UP = (1 << 6),
946 MB_WOL_LINK_DOWN = (1 << 7),
947 MB_WOL_MODE_ON = (1 << 16), /* Wake on Lan Mode on */
948 MB_CMD_SET_WOL_FLTR = 0x00000111, /* Wake On Lan Filter */
949 MB_CMD_CLEAR_WOL_FLTR = 0x00000112, /* Wake On Lan Filter */
950 MB_CMD_SET_WOL_MAGIC = 0x00000113, /* Wake On Lan Magic Packet */
951 MB_CMD_CLEAR_WOL_MAGIC = 0x00000114,/* Wake On Lan Magic Packet */
952 MB_CMD_SET_WOL_IMMED = 0x00000115,
953 MB_CMD_PORT_RESET = 0x00000120,
954 MB_CMD_SET_PORT_CFG = 0x00000122,
955 MB_CMD_GET_PORT_CFG = 0x00000123,
956 MB_CMD_GET_LINK_STS = 0x00000124,
957 MB_CMD_SET_LED_CFG = 0x00000125, /* Set LED Configuration Register */
958 QL_LED_BLINK = 0x03e803e8,
959 MB_CMD_GET_LED_CFG = 0x00000126, /* Get LED Configuration Register */
960 MB_CMD_SET_MGMNT_TFK_CTL = 0x00000160, /* Set Mgmnt Traffic Control */
961 MB_SET_MPI_TFK_STOP = (1 << 0),
962 MB_SET_MPI_TFK_RESUME = (1 << 1),
963 MB_CMD_GET_MGMNT_TFK_CTL = 0x00000161, /* Get Mgmnt Traffic Control */
964 MB_GET_MPI_TFK_STOPPED = (1 << 0),
965 MB_GET_MPI_TFK_FIFO_EMPTY = (1 << 1),
966 /* Sub-commands for IDC request.
967 * This describes the reason for the
970 MB_CMD_IOP_NONE = 0x0000,
971 MB_CMD_IOP_PREP_UPDATE_MPI = 0x0001,
972 MB_CMD_IOP_COMP_UPDATE_MPI = 0x0002,
973 MB_CMD_IOP_PREP_LINK_DOWN = 0x0010,
974 MB_CMD_IOP_DVR_START = 0x0100,
975 MB_CMD_IOP_FLASH_ACC = 0x0101,
976 MB_CMD_IOP_RESTART_MPI = 0x0102,
977 MB_CMD_IOP_CORE_DUMP_MPI = 0x0103,
979 /* Mailbox Command Status. */
980 MB_CMD_STS_GOOD = 0x00004000, /* Success. */
981 MB_CMD_STS_INTRMDT = 0x00001000, /* Intermediate Complete. */
982 MB_CMD_STS_INVLD_CMD = 0x00004001, /* Invalid. */
983 MB_CMD_STS_XFC_ERR = 0x00004002, /* Interface Error. */
984 MB_CMD_STS_CSUM_ERR = 0x00004003, /* Csum Error. */
985 MB_CMD_STS_ERR = 0x00004005, /* System Error. */
986 MB_CMD_STS_PARAM_ERR = 0x00004006, /* Parameter Error. */
990 u32 mbox_in[MAILBOX_COUNT];
991 u32 mbox_out[MAILBOX_COUNT];
996 struct flash_params_8012 {
1006 /* 8000 device's flash is a different structure
1007 * at a different offset in flash.
1009 #define FUNC0_FLASH_OFFSET 0x140200
1010 #define FUNC1_FLASH_OFFSET 0x140600
1012 /* Flash related data structures. */
1013 struct flash_params_8000 {
1014 u8 dev_id_str[4]; /* "8000" */
1034 __le16 subsys_ven_id;
1035 __le16 subsys_dev_id;
1039 union flash_params {
1040 struct flash_params_8012 flash_params_8012;
1041 struct flash_params_8000 flash_params_8000;
1045 * doorbell space for the rx ring context
1047 struct rx_doorbell_context {
1048 u32 cnsmr_idx; /* 0x00 */
1049 u32 valid; /* 0x04 */
1050 u32 reserved[4]; /* 0x08-0x14 */
1051 u32 lbq_prod_idx; /* 0x18 */
1052 u32 sbq_prod_idx; /* 0x1c */
1056 * doorbell space for the tx ring context
1058 struct tx_doorbell_context {
1059 u32 prod_idx; /* 0x00 */
1060 u32 valid; /* 0x04 */
1061 u32 reserved[4]; /* 0x08-0x14 */
1062 u32 lbq_prod_idx; /* 0x18 */
1063 u32 sbq_prod_idx; /* 0x1c */
1066 /* DATA STRUCTURES SHARED WITH HARDWARE. */
1067 struct tx_buf_desc {
1070 #define TX_DESC_LEN_MASK 0x000fffff
1071 #define TX_DESC_C 0x40000000
1072 #define TX_DESC_E 0x80000000
1073 } __attribute((packed));
1076 * IOCB Definitions...
1079 #define OPCODE_OB_MAC_IOCB 0x01
1080 #define OPCODE_OB_MAC_TSO_IOCB 0x02
1081 #define OPCODE_IB_MAC_IOCB 0x20
1082 #define OPCODE_IB_MPI_IOCB 0x21
1083 #define OPCODE_IB_AE_IOCB 0x3f
1085 struct ob_mac_iocb_req {
1088 #define OB_MAC_IOCB_REQ_OI 0x01
1089 #define OB_MAC_IOCB_REQ_I 0x02
1090 #define OB_MAC_IOCB_REQ_D 0x08
1091 #define OB_MAC_IOCB_REQ_F 0x10
1094 #define OB_MAC_IOCB_DFP 0x02
1095 #define OB_MAC_IOCB_V 0x04
1096 __le32 reserved1[2];
1098 #define OB_MAC_IOCB_LEN_MASK 0x3ffff
1105 struct tx_buf_desc tbd[TX_DESC_PER_IOCB];
1106 } __attribute((packed));
1108 struct ob_mac_iocb_rsp {
1111 #define OB_MAC_IOCB_RSP_OI 0x01 /* */
1112 #define OB_MAC_IOCB_RSP_I 0x02 /* */
1113 #define OB_MAC_IOCB_RSP_E 0x08 /* */
1114 #define OB_MAC_IOCB_RSP_S 0x10 /* too Short */
1115 #define OB_MAC_IOCB_RSP_L 0x20 /* too Large */
1116 #define OB_MAC_IOCB_RSP_P 0x40 /* Padded */
1119 #define OB_MAC_IOCB_RSP_B 0x80 /* */
1122 __le32 reserved[13];
1123 } __attribute((packed));
1125 struct ob_mac_tso_iocb_req {
1128 #define OB_MAC_TSO_IOCB_OI 0x01
1129 #define OB_MAC_TSO_IOCB_I 0x02
1130 #define OB_MAC_TSO_IOCB_D 0x08
1131 #define OB_MAC_TSO_IOCB_IP4 0x40
1132 #define OB_MAC_TSO_IOCB_IP6 0x80
1134 #define OB_MAC_TSO_IOCB_LSO 0x20
1135 #define OB_MAC_TSO_IOCB_UC 0x40
1136 #define OB_MAC_TSO_IOCB_TC 0x80
1138 #define OB_MAC_TSO_IOCB_IC 0x01
1139 #define OB_MAC_TSO_IOCB_DFP 0x02
1140 #define OB_MAC_TSO_IOCB_V 0x04
1141 __le32 reserved1[2];
1145 __le16 total_hdrs_len;
1146 __le16 net_trans_offset;
1147 #define OB_MAC_TRANSPORT_HDR_SHIFT 6
1150 struct tx_buf_desc tbd[TX_DESC_PER_IOCB];
1151 } __attribute((packed));
1153 struct ob_mac_tso_iocb_rsp {
1156 #define OB_MAC_TSO_IOCB_RSP_OI 0x01
1157 #define OB_MAC_TSO_IOCB_RSP_I 0x02
1158 #define OB_MAC_TSO_IOCB_RSP_E 0x08
1159 #define OB_MAC_TSO_IOCB_RSP_S 0x10
1160 #define OB_MAC_TSO_IOCB_RSP_L 0x20
1161 #define OB_MAC_TSO_IOCB_RSP_P 0x40
1164 #define OB_MAC_TSO_IOCB_RSP_B 0x8000
1167 __le32 reserved2[13];
1168 } __attribute((packed));
1170 struct ib_mac_iocb_rsp {
1171 u8 opcode; /* 0x20 */
1173 #define IB_MAC_IOCB_RSP_OI 0x01 /* Overide intr delay */
1174 #define IB_MAC_IOCB_RSP_I 0x02 /* Disble Intr Generation */
1175 #define IB_MAC_CSUM_ERR_MASK 0x1c /* A mask to use for csum errs */
1176 #define IB_MAC_IOCB_RSP_TE 0x04 /* Checksum error */
1177 #define IB_MAC_IOCB_RSP_NU 0x08 /* No checksum rcvd */
1178 #define IB_MAC_IOCB_RSP_IE 0x10 /* IPv4 checksum error */
1179 #define IB_MAC_IOCB_RSP_M_MASK 0x60 /* Multicast info */
1180 #define IB_MAC_IOCB_RSP_M_NONE 0x00 /* Not mcast frame */
1181 #define IB_MAC_IOCB_RSP_M_HASH 0x20 /* HASH mcast frame */
1182 #define IB_MAC_IOCB_RSP_M_REG 0x40 /* Registered mcast frame */
1183 #define IB_MAC_IOCB_RSP_M_PROM 0x60 /* Promiscuous mcast frame */
1184 #define IB_MAC_IOCB_RSP_B 0x80 /* Broadcast frame */
1186 #define IB_MAC_IOCB_RSP_P 0x01 /* Promiscuous frame */
1187 #define IB_MAC_IOCB_RSP_V 0x02 /* Vlan tag present */
1188 #define IB_MAC_IOCB_RSP_ERR_MASK 0x1c /* */
1189 #define IB_MAC_IOCB_RSP_ERR_CODE_ERR 0x04
1190 #define IB_MAC_IOCB_RSP_ERR_OVERSIZE 0x08
1191 #define IB_MAC_IOCB_RSP_ERR_UNDERSIZE 0x10
1192 #define IB_MAC_IOCB_RSP_ERR_PREAMBLE 0x14
1193 #define IB_MAC_IOCB_RSP_ERR_FRAME_LEN 0x18
1194 #define IB_MAC_IOCB_RSP_ERR_CRC 0x1c
1195 #define IB_MAC_IOCB_RSP_U 0x20 /* UDP packet */
1196 #define IB_MAC_IOCB_RSP_T 0x40 /* TCP packet */
1197 #define IB_MAC_IOCB_RSP_FO 0x80 /* Failover port */
1199 #define IB_MAC_IOCB_RSP_RSS_MASK 0x07 /* RSS mask */
1200 #define IB_MAC_IOCB_RSP_M_NONE 0x00 /* No RSS match */
1201 #define IB_MAC_IOCB_RSP_M_IPV4 0x04 /* IPv4 RSS match */
1202 #define IB_MAC_IOCB_RSP_M_IPV6 0x02 /* IPv6 RSS match */
1203 #define IB_MAC_IOCB_RSP_M_TCP_V4 0x05 /* TCP with IPv4 */
1204 #define IB_MAC_IOCB_RSP_M_TCP_V6 0x03 /* TCP with IPv6 */
1205 #define IB_MAC_IOCB_RSP_V4 0x08 /* IPV4 */
1206 #define IB_MAC_IOCB_RSP_V6 0x10 /* IPV6 */
1207 #define IB_MAC_IOCB_RSP_IH 0x20 /* Split after IP header */
1208 #define IB_MAC_IOCB_RSP_DS 0x40 /* data is in small buffer */
1209 #define IB_MAC_IOCB_RSP_DL 0x80 /* data is in large buffer */
1210 __le32 data_len; /* */
1211 __le64 data_addr; /* */
1213 __le16 vlan_id; /* 12 bits */
1214 #define IB_MAC_IOCB_RSP_C 0x1000 /* VLAN CFI bit */
1215 #define IB_MAC_IOCB_RSP_COS_SHIFT 12 /* class of service value */
1216 #define IB_MAC_IOCB_RSP_VLAN_MASK 0x0ffff
1219 __le32 reserved2[6];
1222 #define IB_MAC_IOCB_RSP_HV 0x20
1223 #define IB_MAC_IOCB_RSP_HS 0x40
1224 #define IB_MAC_IOCB_RSP_HL 0x80
1225 __le32 hdr_len; /* */
1226 __le64 hdr_addr; /* */
1227 } __attribute((packed));
1229 struct ib_ae_iocb_rsp {
1232 #define IB_AE_IOCB_RSP_OI 0x01
1233 #define IB_AE_IOCB_RSP_I 0x02
1235 #define LINK_UP_EVENT 0x00
1236 #define LINK_DOWN_EVENT 0x01
1237 #define CAM_LOOKUP_ERR_EVENT 0x06
1238 #define SOFT_ECC_ERROR_EVENT 0x07
1239 #define MGMT_ERR_EVENT 0x08
1240 #define TEN_GIG_MAC_EVENT 0x09
1241 #define GPI0_H2L_EVENT 0x10
1242 #define GPI0_L2H_EVENT 0x20
1243 #define GPI1_H2L_EVENT 0x11
1244 #define GPI1_L2H_EVENT 0x21
1245 #define PCI_ERR_ANON_BUF_RD 0x40
1247 __le32 reserved[15];
1248 } __attribute((packed));
1251 * These three structures are for generic
1252 * handling of ib and ob iocbs.
1254 struct ql_net_rsp_iocb {
1259 __le32 reserved[14];
1260 } __attribute((packed));
1262 struct net_req_iocb {
1267 __le32 reserved1[30];
1268 } __attribute((packed));
1271 * tx ring initialization control block for chip.
1273 * "Work Queue Initialization Control Block"
1277 #define Q_LEN_V (1 << 4)
1278 #define Q_LEN_CPP_CONT 0x0000
1279 #define Q_LEN_CPP_16 0x0001
1280 #define Q_LEN_CPP_32 0x0002
1281 #define Q_LEN_CPP_64 0x0003
1282 #define Q_LEN_CPP_512 0x0006
1284 #define Q_PRI_SHIFT 1
1285 #define Q_FLAGS_LC 0x1000
1286 #define Q_FLAGS_LB 0x2000
1287 #define Q_FLAGS_LI 0x4000
1288 #define Q_FLAGS_LO 0x8000
1290 #define Q_CQ_ID_RSS_RV 0x8000
1293 __le64 cnsmr_idx_addr;
1294 } __attribute((packed));
1297 * rx ring initialization control block for chip.
1299 * "Completion Queue Initialization Control Block"
1306 #define FLAGS_LV 0x08
1307 #define FLAGS_LS 0x10
1308 #define FLAGS_LL 0x20
1309 #define FLAGS_LI 0x40
1310 #define FLAGS_LC 0x80
1312 #define LEN_V (1 << 4)
1313 #define LEN_CPP_CONT 0x0000
1314 #define LEN_CPP_32 0x0001
1315 #define LEN_CPP_64 0x0002
1316 #define LEN_CPP_128 0x0003
1319 __le64 prod_idx_addr;
1323 __le16 lbq_buf_size;
1324 __le16 lbq_len; /* entry count */
1326 __le16 sbq_buf_size;
1327 __le16 sbq_len; /* entry count */
1328 } __attribute((packed));
1332 #define RSS_L4K 0x80
1334 #define RSS_L6K 0x01
1338 #define RSS_RI4 0x10
1339 #define RSS_RT4 0x20
1340 #define RSS_RI6 0x40
1341 #define RSS_RT6 0x80
1343 u8 hash_cq_id[1024];
1344 __le32 ipv6_hash_key[10];
1345 __le32 ipv4_hash_key[4];
1346 } __attribute((packed));
1348 /* SOFTWARE/DRIVER DATA STRUCTURES. */
1351 struct tx_buf_desc oal[TX_DESC_PER_OAL];
1355 DECLARE_PCI_UNMAP_ADDR(mapaddr);
1356 DECLARE_PCI_UNMAP_LEN(maplen);
1359 struct tx_ring_desc {
1360 struct sk_buff *skb;
1361 struct ob_mac_iocb_req *queue_entry;
1364 struct map_list map[MAX_SKB_FRAGS + 1];
1366 struct tx_ring_desc *next;
1370 struct page *page; /* master page */
1371 char *va; /* virt addr for this chunk */
1372 u64 map; /* mapping for master */
1373 unsigned int offset; /* offset for this chunk */
1374 unsigned int last_flag; /* flag set for last chunk in page */
1379 struct page_chunk pg_chunk;
1380 struct sk_buff *skb;
1384 DECLARE_PCI_UNMAP_ADDR(mapaddr);
1385 DECLARE_PCI_UNMAP_LEN(maplen);
1388 #define QL_TXQ_IDX(qdev, skb) (smp_processor_id()%(qdev->tx_ring_count))
1394 struct wqicb wqicb; /* structure used to inform chip of new queue */
1395 void *wq_base; /* pci_alloc:virtual addr for tx */
1396 dma_addr_t wq_base_dma; /* pci_alloc:dma addr for tx */
1397 __le32 *cnsmr_idx_sh_reg; /* shadow copy of consumer idx */
1398 dma_addr_t cnsmr_idx_sh_reg_dma; /* dma-shadow copy of consumer */
1399 u32 wq_size; /* size in bytes of queue area */
1400 u32 wq_len; /* number of entries in queue */
1401 void __iomem *prod_idx_db_reg; /* doorbell area index reg at offset 0x00 */
1402 void __iomem *valid_db_reg; /* doorbell area valid reg at offset 0x04 */
1403 u16 prod_idx; /* current value for prod idx */
1404 u16 cq_id; /* completion (rx) queue for tx completions */
1405 u8 wq_id; /* queue id for this entry */
1407 struct tx_ring_desc *q; /* descriptor list for the queue */
1409 atomic_t tx_count; /* counts down for every outstanding IO */
1410 atomic_t queue_stopped; /* Turns queue off when full. */
1411 struct delayed_work tx_work;
1412 struct ql_adapter *qdev;
1419 * Type of inbound queue.
1422 DEFAULT_Q = 2, /* Handles slow queue and chip/MPI events. */
1423 TX_Q = 3, /* Handles outbound completions. */
1424 RX_Q = 4, /* Handles inbound completions. */
1428 struct cqicb cqicb; /* The chip's completion queue init control block. */
1430 /* Completion queue elements. */
1432 dma_addr_t cq_base_dma;
1436 __le32 *prod_idx_sh_reg; /* Shadowed producer register. */
1437 dma_addr_t prod_idx_sh_reg_dma;
1438 void __iomem *cnsmr_idx_db_reg; /* PCI doorbell mem area + 0 */
1439 u32 cnsmr_idx; /* current sw idx */
1440 struct ql_net_rsp_iocb *curr_entry; /* next entry on queue */
1441 void __iomem *valid_db_reg; /* PCI doorbell mem area + 0x04 */
1443 /* Large buffer queue elements. */
1444 u32 lbq_len; /* entry count */
1445 u32 lbq_size; /* size in bytes of queue */
1448 dma_addr_t lbq_base_dma;
1449 void *lbq_base_indirect;
1450 dma_addr_t lbq_base_indirect_dma;
1451 struct page_chunk pg_chunk; /* current page for chunks */
1452 struct bq_desc *lbq; /* array of control blocks */
1453 void __iomem *lbq_prod_idx_db_reg; /* PCI doorbell mem area + 0x18 */
1454 u32 lbq_prod_idx; /* current sw prod idx */
1455 u32 lbq_curr_idx; /* next entry we expect */
1456 u32 lbq_clean_idx; /* beginning of new descs */
1457 u32 lbq_free_cnt; /* free buffer desc cnt */
1459 /* Small buffer queue elements. */
1460 u32 sbq_len; /* entry count */
1461 u32 sbq_size; /* size in bytes of queue */
1464 dma_addr_t sbq_base_dma;
1465 void *sbq_base_indirect;
1466 dma_addr_t sbq_base_indirect_dma;
1467 struct bq_desc *sbq; /* array of control blocks */
1468 void __iomem *sbq_prod_idx_db_reg; /* PCI doorbell mem area + 0x1c */
1469 u32 sbq_prod_idx; /* current sw prod idx */
1470 u32 sbq_curr_idx; /* next entry we expect */
1471 u32 sbq_clean_idx; /* beginning of new descs */
1472 u32 sbq_free_cnt; /* free buffer desc cnt */
1474 /* Misc. handler elements. */
1475 u32 type; /* Type of queue, tx, rx. */
1476 u32 irq; /* Which vector this ring is assigned. */
1477 u32 cpu; /* Which CPU this should run on. */
1478 char name[IFNAMSIZ + 5];
1479 struct napi_struct napi;
1481 struct ql_adapter *qdev;
1490 * RSS Initialization Control Block
1498 * These stats come from offset 200h to 278h
1499 * in the XGMAC register.
1509 u64 tx_65_to_127_pkt;
1510 u64 tx_128_to_255_pkt;
1512 u64 tx_512_to_1023_pkt;
1513 u64 tx_1024_to_1518_pkt;
1514 u64 tx_1519_to_max_pkt;
1515 u64 tx_undersize_pkt;
1516 u64 tx_oversize_pkt;
1519 * These stats come from offset 300h to 3C8h
1520 * in the XGMAC register.
1529 u64 rx_undersize_pkts;
1530 u64 rx_oversize_pkts;
1532 u64 rx_undersize_fcerr_pkts;
1541 u64 rx_65_to_127_pkts;
1542 u64 rx_128_255_pkts;
1543 u64 rx_256_511_pkts;
1544 u64 rx_512_to_1023_pkts;
1545 u64 rx_1024_to_1518_pkts;
1546 u64 rx_1519_to_max_pkts;
1547 u64 rx_len_err_pkts;
1549 * These stats come from offset 500h to 5C8h
1550 * in the XGMAC register.
1552 u64 tx_cbfc_pause_frames0;
1553 u64 tx_cbfc_pause_frames1;
1554 u64 tx_cbfc_pause_frames2;
1555 u64 tx_cbfc_pause_frames3;
1556 u64 tx_cbfc_pause_frames4;
1557 u64 tx_cbfc_pause_frames5;
1558 u64 tx_cbfc_pause_frames6;
1559 u64 tx_cbfc_pause_frames7;
1560 u64 rx_cbfc_pause_frames0;
1561 u64 rx_cbfc_pause_frames1;
1562 u64 rx_cbfc_pause_frames2;
1563 u64 rx_cbfc_pause_frames3;
1564 u64 rx_cbfc_pause_frames4;
1565 u64 rx_cbfc_pause_frames5;
1566 u64 rx_cbfc_pause_frames6;
1567 u64 rx_cbfc_pause_frames7;
1568 u64 rx_nic_fifo_drop;
1571 /* Firmware coredump internal register address/length pairs. */
1573 MPI_CORE_REGS_ADDR = 0x00030000,
1574 MPI_CORE_REGS_CNT = 127,
1575 MPI_CORE_SH_REGS_CNT = 16,
1576 TEST_REGS_ADDR = 0x00001000,
1578 RMII_REGS_ADDR = 0x00001040,
1580 FCMAC1_REGS_ADDR = 0x00001080,
1581 FCMAC2_REGS_ADDR = 0x000010c0,
1582 FCMAC_REGS_CNT = 64,
1583 FC1_MBX_REGS_ADDR = 0x00001100,
1584 FC2_MBX_REGS_ADDR = 0x00001240,
1585 FC_MBX_REGS_CNT = 64,
1586 IDE_REGS_ADDR = 0x00001140,
1588 NIC1_MBX_REGS_ADDR = 0x00001180,
1589 NIC2_MBX_REGS_ADDR = 0x00001280,
1590 NIC_MBX_REGS_CNT = 64,
1591 SMBUS_REGS_ADDR = 0x00001200,
1592 SMBUS_REGS_CNT = 64,
1593 I2C_REGS_ADDR = 0x00001fc0,
1595 MEMC_REGS_ADDR = 0x00003000,
1596 MEMC_REGS_CNT = 256,
1597 PBUS_REGS_ADDR = 0x00007c00,
1598 PBUS_REGS_CNT = 256,
1599 MDE_REGS_ADDR = 0x00010000,
1601 CODE_RAM_ADDR = 0x00020000,
1602 CODE_RAM_CNT = 0x2000,
1603 MEMC_RAM_ADDR = 0x00100000,
1604 MEMC_RAM_CNT = 0x2000,
1607 #define MPI_COREDUMP_COOKIE 0x5555aaaa
1608 struct mpi_coredump_global_header {
1618 struct mpi_coredump_segment_header {
1626 /* Firmware coredump header segment numbers. */
1629 TEST_LOGIC_SEG_NUM = 2,
1633 FC1_MBOX_SEG_NUM = 6,
1635 NIC1_MBOX_SEG_NUM = 8,
1637 FC2_MBOX_SEG_NUM = 10,
1638 NIC2_MBOX_SEG_NUM = 11,
1643 NIC1_CONTROL_SEG_NUM = 16,
1644 NIC2_CONTROL_SEG_NUM = 17,
1645 NIC1_XGMAC_SEG_NUM = 18,
1646 NIC2_XGMAC_SEG_NUM = 19,
1647 WCS_RAM_SEG_NUM = 20,
1648 MEMC_RAM_SEG_NUM = 21,
1649 XAUI_AN_SEG_NUM = 22,
1650 XAUI_HSS_PCS_SEG_NUM = 23,
1651 XFI_AN_SEG_NUM = 24,
1652 XFI_TRAIN_SEG_NUM = 25,
1653 XFI_HSS_PCS_SEG_NUM = 26,
1654 XFI_HSS_TX_SEG_NUM = 27,
1655 XFI_HSS_RX_SEG_NUM = 28,
1656 XFI_HSS_PLL_SEG_NUM = 29,
1657 MISC_NIC_INFO_SEG_NUM = 30,
1658 INTR_STATES_SEG_NUM = 31,
1659 CAM_ENTRIES_SEG_NUM = 32,
1660 ROUTING_WORDS_SEG_NUM = 33,
1662 PROBE_DUMP_SEG_NUM = 35,
1663 ROUTING_INDEX_SEG_NUM = 36,
1664 MAC_PROTOCOL_SEG_NUM = 37,
1665 XAUI2_AN_SEG_NUM = 38,
1666 XAUI2_HSS_PCS_SEG_NUM = 39,
1667 XFI2_AN_SEG_NUM = 40,
1668 XFI2_TRAIN_SEG_NUM = 41,
1669 XFI2_HSS_PCS_SEG_NUM = 42,
1670 XFI2_HSS_TX_SEG_NUM = 43,
1671 XFI2_HSS_RX_SEG_NUM = 44,
1672 XFI2_HSS_PLL_SEG_NUM = 45,
1673 SEM_REGS_SEG_NUM = 50
1677 /* There are 64 generic NIC registers. */
1678 #define NIC_REGS_DUMP_WORD_COUNT 64
1679 /* XGMAC word count. */
1680 #define XGMAC_DUMP_WORD_COUNT (XGMAC_REGISTER_END / 4)
1681 /* Word counts for the SERDES blocks. */
1682 #define XG_SERDES_XAUI_AN_COUNT 14
1683 #define XG_SERDES_XAUI_HSS_PCS_COUNT 33
1684 #define XG_SERDES_XFI_AN_COUNT 14
1685 #define XG_SERDES_XFI_TRAIN_COUNT 12
1686 #define XG_SERDES_XFI_HSS_PCS_COUNT 15
1687 #define XG_SERDES_XFI_HSS_TX_COUNT 32
1688 #define XG_SERDES_XFI_HSS_RX_COUNT 32
1689 #define XG_SERDES_XFI_HSS_PLL_COUNT 32
1691 /* There are 2 CNA ETS and 8 NIC ETS registers. */
1692 #define ETS_REGS_DUMP_WORD_COUNT 10
1694 /* Each probe mux entry stores the probe type plus 64 entries
1695 * that are each each 64-bits in length. There are a total of
1696 * 34 (PRB_MX_ADDR_VALID_TOTAL) valid probes.
1698 #define PRB_MX_ADDR_PRB_WORD_COUNT (1 + (PRB_MX_ADDR_MAX_MUX * 2))
1699 #define PRB_MX_DUMP_TOT_COUNT (PRB_MX_ADDR_PRB_WORD_COUNT * \
1700 PRB_MX_ADDR_VALID_TOTAL)
1701 /* Each routing entry consists of 4 32-bit words.
1702 * They are route type, index, index word, and result.
1703 * There are 2 route blocks with 8 entries each and
1704 * 2 NIC blocks with 16 entries each.
1705 * The totol entries is 48 with 4 words each.
1707 #define RT_IDX_DUMP_ENTRIES 48
1708 #define RT_IDX_DUMP_WORDS_PER_ENTRY 4
1709 #define RT_IDX_DUMP_TOT_WORDS (RT_IDX_DUMP_ENTRIES * \
1710 RT_IDX_DUMP_WORDS_PER_ENTRY)
1711 /* There are 10 address blocks in filter, each with
1712 * different entry counts and different word-count-per-entry.
1714 #define MAC_ADDR_DUMP_ENTRIES \
1715 ((MAC_ADDR_MAX_CAM_ENTRIES * MAC_ADDR_MAX_CAM_WCOUNT) + \
1716 (MAC_ADDR_MAX_MULTICAST_ENTRIES * MAC_ADDR_MAX_MULTICAST_WCOUNT) + \
1717 (MAC_ADDR_MAX_VLAN_ENTRIES * MAC_ADDR_MAX_VLAN_WCOUNT) + \
1718 (MAC_ADDR_MAX_MCAST_FLTR_ENTRIES * MAC_ADDR_MAX_MCAST_FLTR_WCOUNT) + \
1719 (MAC_ADDR_MAX_FC_MAC_ENTRIES * MAC_ADDR_MAX_FC_MAC_WCOUNT) + \
1720 (MAC_ADDR_MAX_MGMT_MAC_ENTRIES * MAC_ADDR_MAX_MGMT_MAC_WCOUNT) + \
1721 (MAC_ADDR_MAX_MGMT_VLAN_ENTRIES * MAC_ADDR_MAX_MGMT_VLAN_WCOUNT) + \
1722 (MAC_ADDR_MAX_MGMT_V4_ENTRIES * MAC_ADDR_MAX_MGMT_V4_WCOUNT) + \
1723 (MAC_ADDR_MAX_MGMT_V6_ENTRIES * MAC_ADDR_MAX_MGMT_V6_WCOUNT) + \
1724 (MAC_ADDR_MAX_MGMT_TU_DP_ENTRIES * MAC_ADDR_MAX_MGMT_TU_DP_WCOUNT))
1725 #define MAC_ADDR_DUMP_WORDS_PER_ENTRY 2
1726 #define MAC_ADDR_DUMP_TOT_WORDS (MAC_ADDR_DUMP_ENTRIES * \
1727 MAC_ADDR_DUMP_WORDS_PER_ENTRY)
1728 /* Maximum of 4 functions whose semaphore registeres are
1731 #define MAX_SEMAPHORE_FUNCTIONS 4
1732 /* Defines for access the MPI shadow registers. */
1733 #define RISC_124 0x0003007c
1734 #define RISC_127 0x0003007f
1735 #define SHADOW_OFFSET 0xb0000000
1736 #define SHADOW_REG_SHIFT 20
1738 struct ql_nic_misc {
1745 struct ql_reg_dump {
1748 struct mpi_coredump_global_header mpi_global_header;
1751 struct mpi_coredump_segment_header nic_regs_seg_hdr;
1755 struct mpi_coredump_segment_header misc_nic_seg_hdr;
1756 struct ql_nic_misc misc_nic_info;
1759 /* one interrupt state for each CQ */
1760 struct mpi_coredump_segment_header intr_states_seg_hdr;
1761 u32 intr_states[MAX_CPUS];
1764 /* 3 cam words each for 16 unicast,
1765 * 2 cam words for each of 32 multicast.
1767 struct mpi_coredump_segment_header cam_entries_seg_hdr;
1768 u32 cam_entries[(16 * 3) + (32 * 3)];
1771 struct mpi_coredump_segment_header nic_routing_words_seg_hdr;
1772 u32 nic_routing_words[16];
1775 struct mpi_coredump_segment_header ets_seg_hdr;
1779 struct ql_mpi_coredump {
1781 struct mpi_coredump_global_header mpi_global_header;
1784 struct mpi_coredump_segment_header core_regs_seg_hdr;
1785 u32 mpi_core_regs[MPI_CORE_REGS_CNT];
1786 u32 mpi_core_sh_regs[MPI_CORE_SH_REGS_CNT];
1789 struct mpi_coredump_segment_header test_logic_regs_seg_hdr;
1790 u32 test_logic_regs[TEST_REGS_CNT];
1793 struct mpi_coredump_segment_header rmii_regs_seg_hdr;
1794 u32 rmii_regs[RMII_REGS_CNT];
1797 struct mpi_coredump_segment_header fcmac1_regs_seg_hdr;
1798 u32 fcmac1_regs[FCMAC_REGS_CNT];
1801 struct mpi_coredump_segment_header fcmac2_regs_seg_hdr;
1802 u32 fcmac2_regs[FCMAC_REGS_CNT];
1805 struct mpi_coredump_segment_header fc1_mbx_regs_seg_hdr;
1806 u32 fc1_mbx_regs[FC_MBX_REGS_CNT];
1809 struct mpi_coredump_segment_header ide_regs_seg_hdr;
1810 u32 ide_regs[IDE_REGS_CNT];
1813 struct mpi_coredump_segment_header nic1_mbx_regs_seg_hdr;
1814 u32 nic1_mbx_regs[NIC_MBX_REGS_CNT];
1817 struct mpi_coredump_segment_header smbus_regs_seg_hdr;
1818 u32 smbus_regs[SMBUS_REGS_CNT];
1821 struct mpi_coredump_segment_header fc2_mbx_regs_seg_hdr;
1822 u32 fc2_mbx_regs[FC_MBX_REGS_CNT];
1825 struct mpi_coredump_segment_header nic2_mbx_regs_seg_hdr;
1826 u32 nic2_mbx_regs[NIC_MBX_REGS_CNT];
1829 struct mpi_coredump_segment_header i2c_regs_seg_hdr;
1830 u32 i2c_regs[I2C_REGS_CNT];
1832 struct mpi_coredump_segment_header memc_regs_seg_hdr;
1833 u32 memc_regs[MEMC_REGS_CNT];
1836 struct mpi_coredump_segment_header pbus_regs_seg_hdr;
1837 u32 pbus_regs[PBUS_REGS_CNT];
1840 struct mpi_coredump_segment_header mde_regs_seg_hdr;
1841 u32 mde_regs[MDE_REGS_CNT];
1844 struct mpi_coredump_segment_header nic_regs_seg_hdr;
1845 u32 nic_regs[NIC_REGS_DUMP_WORD_COUNT];
1848 struct mpi_coredump_segment_header nic2_regs_seg_hdr;
1849 u32 nic2_regs[NIC_REGS_DUMP_WORD_COUNT];
1852 struct mpi_coredump_segment_header xgmac1_seg_hdr;
1853 u32 xgmac1[XGMAC_DUMP_WORD_COUNT];
1856 struct mpi_coredump_segment_header xgmac2_seg_hdr;
1857 u32 xgmac2[XGMAC_DUMP_WORD_COUNT];
1860 struct mpi_coredump_segment_header code_ram_seg_hdr;
1861 u32 code_ram[CODE_RAM_CNT];
1864 struct mpi_coredump_segment_header memc_ram_seg_hdr;
1865 u32 memc_ram[MEMC_RAM_CNT];
1868 struct mpi_coredump_segment_header xaui_an_hdr;
1869 u32 serdes_xaui_an[XG_SERDES_XAUI_AN_COUNT];
1872 struct mpi_coredump_segment_header xaui_hss_pcs_hdr;
1873 u32 serdes_xaui_hss_pcs[XG_SERDES_XAUI_HSS_PCS_COUNT];
1876 struct mpi_coredump_segment_header xfi_an_hdr;
1877 u32 serdes_xfi_an[XG_SERDES_XFI_AN_COUNT];
1880 struct mpi_coredump_segment_header xfi_train_hdr;
1881 u32 serdes_xfi_train[XG_SERDES_XFI_TRAIN_COUNT];
1884 struct mpi_coredump_segment_header xfi_hss_pcs_hdr;
1885 u32 serdes_xfi_hss_pcs[XG_SERDES_XFI_HSS_PCS_COUNT];
1888 struct mpi_coredump_segment_header xfi_hss_tx_hdr;
1889 u32 serdes_xfi_hss_tx[XG_SERDES_XFI_HSS_TX_COUNT];
1892 struct mpi_coredump_segment_header xfi_hss_rx_hdr;
1893 u32 serdes_xfi_hss_rx[XG_SERDES_XFI_HSS_RX_COUNT];
1896 struct mpi_coredump_segment_header xfi_hss_pll_hdr;
1897 u32 serdes_xfi_hss_pll[XG_SERDES_XFI_HSS_PLL_COUNT];
1900 struct mpi_coredump_segment_header misc_nic_seg_hdr;
1901 struct ql_nic_misc misc_nic_info;
1904 /* one interrupt state for each CQ */
1905 struct mpi_coredump_segment_header intr_states_seg_hdr;
1906 u32 intr_states[MAX_RX_RINGS];
1909 /* 3 cam words each for 16 unicast,
1910 * 2 cam words for each of 32 multicast.
1912 struct mpi_coredump_segment_header cam_entries_seg_hdr;
1913 u32 cam_entries[(16 * 3) + (32 * 3)];
1916 struct mpi_coredump_segment_header nic_routing_words_seg_hdr;
1917 u32 nic_routing_words[16];
1919 struct mpi_coredump_segment_header ets_seg_hdr;
1920 u32 ets[ETS_REGS_DUMP_WORD_COUNT];
1923 struct mpi_coredump_segment_header probe_dump_seg_hdr;
1924 u32 probe_dump[PRB_MX_DUMP_TOT_COUNT];
1927 struct mpi_coredump_segment_header routing_reg_seg_hdr;
1928 u32 routing_regs[RT_IDX_DUMP_TOT_WORDS];
1931 struct mpi_coredump_segment_header mac_prot_reg_seg_hdr;
1932 u32 mac_prot_regs[MAC_ADDR_DUMP_TOT_WORDS];
1935 struct mpi_coredump_segment_header xaui2_an_hdr;
1936 u32 serdes2_xaui_an[XG_SERDES_XAUI_AN_COUNT];
1939 struct mpi_coredump_segment_header xaui2_hss_pcs_hdr;
1940 u32 serdes2_xaui_hss_pcs[XG_SERDES_XAUI_HSS_PCS_COUNT];
1943 struct mpi_coredump_segment_header xfi2_an_hdr;
1944 u32 serdes2_xfi_an[XG_SERDES_XFI_AN_COUNT];
1947 struct mpi_coredump_segment_header xfi2_train_hdr;
1948 u32 serdes2_xfi_train[XG_SERDES_XFI_TRAIN_COUNT];
1951 struct mpi_coredump_segment_header xfi2_hss_pcs_hdr;
1952 u32 serdes2_xfi_hss_pcs[XG_SERDES_XFI_HSS_PCS_COUNT];
1955 struct mpi_coredump_segment_header xfi2_hss_tx_hdr;
1956 u32 serdes2_xfi_hss_tx[XG_SERDES_XFI_HSS_TX_COUNT];
1959 struct mpi_coredump_segment_header xfi2_hss_rx_hdr;
1960 u32 serdes2_xfi_hss_rx[XG_SERDES_XFI_HSS_RX_COUNT];
1963 struct mpi_coredump_segment_header xfi2_hss_pll_hdr;
1964 u32 serdes2_xfi_hss_pll[XG_SERDES_XFI_HSS_PLL_COUNT];
1967 /* semaphore register for all 5 functions */
1968 struct mpi_coredump_segment_header sem_regs_seg_hdr;
1969 u32 sem_regs[MAX_SEMAPHORE_FUNCTIONS];
1973 * intr_context structure is used during initialization
1974 * to hook the interrupts. It is also used in a single
1975 * irq environment as a context to the ISR.
1977 struct intr_context {
1978 struct ql_adapter *qdev;
1980 u32 irq_mask; /* Mask of which rings the vector services. */
1982 u32 intr_en_mask; /* value/mask used to enable this intr */
1983 u32 intr_dis_mask; /* value/mask used to disable this intr */
1984 u32 intr_read_mask; /* value/mask used to read this intr */
1985 char name[IFNAMSIZ * 2];
1986 atomic_t irq_cnt; /* irq_cnt is used in single vector
1987 * environment. It's incremented for each
1988 * irq handler that is scheduled. When each
1989 * handler finishes it decrements irq_cnt and
1990 * enables interrupts if it's zero. */
1991 irq_handler_t handler;
1994 /* adapter flags definitions. */
1996 QL_ADAPTER_UP = 0, /* Adapter has been brought up. */
1997 QL_LEGACY_ENABLED = 1,
1999 QL_MSIX_ENABLED = 3,
2007 QL_FRC_COREDUMP = 11,
2010 /* link_status bit definitions */
2012 STS_LOOPBACK_MASK = 0x00000700,
2013 STS_LOOPBACK_PCS = 0x00000100,
2014 STS_LOOPBACK_HSS = 0x00000200,
2015 STS_LOOPBACK_EXT = 0x00000300,
2016 STS_PAUSE_MASK = 0x000000c0,
2017 STS_PAUSE_STD = 0x00000040,
2018 STS_PAUSE_PRI = 0x00000080,
2019 STS_SPEED_MASK = 0x00000038,
2020 STS_SPEED_100Mb = 0x00000000,
2021 STS_SPEED_1Gb = 0x00000008,
2022 STS_SPEED_10Gb = 0x00000010,
2023 STS_LINK_TYPE_MASK = 0x00000007,
2024 STS_LINK_TYPE_XFI = 0x00000001,
2025 STS_LINK_TYPE_XAUI = 0x00000002,
2026 STS_LINK_TYPE_XFI_BP = 0x00000003,
2027 STS_LINK_TYPE_XAUI_BP = 0x00000004,
2028 STS_LINK_TYPE_10GBASET = 0x00000005,
2031 /* link_config bit definitions */
2033 CFG_JUMBO_FRAME_SIZE = 0x00010000,
2034 CFG_PAUSE_MASK = 0x00000060,
2035 CFG_PAUSE_STD = 0x00000020,
2036 CFG_PAUSE_PRI = 0x00000040,
2037 CFG_DCBX = 0x00000010,
2038 CFG_LOOPBACK_MASK = 0x00000007,
2039 CFG_LOOPBACK_PCS = 0x00000002,
2040 CFG_LOOPBACK_HSS = 0x00000004,
2041 CFG_LOOPBACK_EXT = 0x00000006,
2042 CFG_DEFAULT_MAX_FRAME_SIZE = 0x00002580,
2045 struct nic_operations {
2047 int (*get_flash) (struct ql_adapter *);
2048 int (*port_initialize) (struct ql_adapter *);
2052 * The main Adapter structure definition.
2053 * This structure has all fields relevant to the hardware.
2057 unsigned long flags;
2060 struct nic_stats nic_stats;
2062 struct vlan_group *vlgrp;
2064 /* PCI Configuration information for this device */
2065 struct pci_dev *pdev;
2066 struct net_device *ndev; /* Parent NET device */
2068 /* Hardware information */
2071 u32 func; /* PCI function for this adapter */
2072 u32 alt_func; /* PCI function for alternate adapter */
2073 u32 port; /* Port number this adapter */
2075 spinlock_t adapter_lock;
2077 spinlock_t stats_lock;
2079 /* PCI Bus Relative Register Addresses */
2080 void __iomem *reg_base;
2081 void __iomem *doorbell_area;
2082 u32 doorbell_area_size;
2086 /* Page for Shadow Registers */
2087 void *rx_ring_shadow_reg_area;
2088 dma_addr_t rx_ring_shadow_reg_dma;
2089 void *tx_ring_shadow_reg_area;
2090 dma_addr_t tx_ring_shadow_reg_dma;
2094 struct mbox_params idc_mbc;
2099 struct msix_entry *msi_x_entry;
2100 struct intr_context intr_context[MAX_RX_RINGS];
2102 int tx_ring_count; /* One per online CPU. */
2103 u32 rss_ring_count; /* One per irq vector. */
2106 * (CPU count * outbound completion rx_ring) +
2107 * (irq_vector_cnt * inbound (RSS) completion rx_ring)
2113 struct rx_ring rx_ring[MAX_RX_RINGS];
2114 struct tx_ring tx_ring[MAX_TX_RINGS];
2115 unsigned int lbq_buf_order;
2118 u32 default_rx_queue;
2120 u16 rx_coalesce_usecs; /* cqicb->int_delay */
2121 u16 rx_max_coalesced_frames; /* cqicb->pkt_int_delay */
2122 u16 tx_coalesce_usecs; /* cqicb->int_delay */
2123 u16 tx_max_coalesced_frames; /* cqicb->pkt_int_delay */
2129 struct ql_mpi_coredump *mpi_coredump;
2135 union flash_params flash;
2137 struct workqueue_struct *workqueue;
2138 struct delayed_work asic_reset_work;
2139 struct delayed_work mpi_reset_work;
2140 struct delayed_work mpi_work;
2141 struct delayed_work mpi_port_cfg_work;
2142 struct delayed_work mpi_idc_work;
2143 struct delayed_work mpi_core_to_log;
2144 struct completion ide_completion;
2145 struct nic_operations *nic_ops;
2151 * Typical Register accessor for memory mapped device.
2153 static inline u32 ql_read32(const struct ql_adapter *qdev, int reg)
2155 return readl(qdev->reg_base + reg);
2159 * Typical Register accessor for memory mapped device.
2161 static inline void ql_write32(const struct ql_adapter *qdev, int reg, u32 val)
2163 writel(val, qdev->reg_base + reg);
2167 * Doorbell Registers:
2168 * Doorbell registers are virtual registers in the PCI memory space.
2169 * The space is allocated by the chip during PCI initialization. The
2170 * device driver finds the doorbell address in BAR 3 in PCI config space.
2171 * The registers are used to control outbound and inbound queues. For
2172 * example, the producer index for an outbound queue. Each queue uses
2173 * 1 4k chunk of memory. The lower half of the space is for outbound
2174 * queues. The upper half is for inbound queues.
2176 static inline void ql_write_db_reg(u32 val, void __iomem *addr)
2184 * Outbound queues have a consumer index that is maintained by the chip.
2185 * Inbound queues have a producer index that is maintained by the chip.
2186 * For lower overhead, these registers are "shadowed" to host memory
2187 * which allows the device driver to track the queue progress without
2188 * PCI reads. When an entry is placed on an inbound queue, the chip will
2189 * update the relevant index register and then copy the value to the
2190 * shadow register in host memory.
2192 static inline u32 ql_read_sh_reg(__le32 *addr)
2195 reg = le32_to_cpu(*addr);
2200 extern char qlge_driver_name[];
2201 extern const char qlge_driver_version[];
2202 extern const struct ethtool_ops qlge_ethtool_ops;
2204 extern int ql_sem_spinlock(struct ql_adapter *qdev, u32 sem_mask);
2205 extern void ql_sem_unlock(struct ql_adapter *qdev, u32 sem_mask);
2206 extern int ql_read_xgmac_reg(struct ql_adapter *qdev, u32 reg, u32 *data);
2207 extern int ql_get_mac_addr_reg(struct ql_adapter *qdev, u32 type, u16 index,
2209 extern int ql_get_routing_reg(struct ql_adapter *qdev, u32 index, u32 *value);
2210 extern int ql_write_cfg(struct ql_adapter *qdev, void *ptr, int size, u32 bit,
2212 void ql_queue_fw_error(struct ql_adapter *qdev);
2213 void ql_mpi_work(struct work_struct *work);
2214 void ql_mpi_reset_work(struct work_struct *work);
2215 void ql_mpi_core_to_log(struct work_struct *work);
2216 int ql_wait_reg_rdy(struct ql_adapter *qdev, u32 reg, u32 bit, u32 ebit);
2217 void ql_queue_asic_error(struct ql_adapter *qdev);
2218 u32 ql_enable_completion_interrupt(struct ql_adapter *qdev, u32 intr);
2219 void ql_set_ethtool_ops(struct net_device *ndev);
2220 int ql_read_xgmac_reg64(struct ql_adapter *qdev, u32 reg, u64 *data);
2221 void ql_mpi_idc_work(struct work_struct *work);
2222 void ql_mpi_port_cfg_work(struct work_struct *work);
2223 int ql_mb_get_fw_state(struct ql_adapter *qdev);
2224 int ql_cam_route_initialize(struct ql_adapter *qdev);
2225 int ql_read_mpi_reg(struct ql_adapter *qdev, u32 reg, u32 *data);
2226 int ql_write_mpi_reg(struct ql_adapter *qdev, u32 reg, u32 data);
2227 int ql_unpause_mpi_risc(struct ql_adapter *qdev);
2228 int ql_pause_mpi_risc(struct ql_adapter *qdev);
2229 int ql_hard_reset_mpi_risc(struct ql_adapter *qdev);
2230 int ql_dump_risc_ram_area(struct ql_adapter *qdev, void *buf,
2231 u32 ram_addr, int word_count);
2232 int ql_core_dump(struct ql_adapter *qdev,
2233 struct ql_mpi_coredump *mpi_coredump);
2234 int ql_mb_sys_err(struct ql_adapter *qdev);
2235 int ql_mb_about_fw(struct ql_adapter *qdev);
2236 int ql_wol(struct ql_adapter *qdev);
2237 int ql_mb_wol_set_magic(struct ql_adapter *qdev, u32 enable_wol);
2238 int ql_mb_wol_mode(struct ql_adapter *qdev, u32 wol);
2239 int ql_mb_set_led_cfg(struct ql_adapter *qdev, u32 led_config);
2240 int ql_mb_get_led_cfg(struct ql_adapter *qdev);
2241 void ql_link_on(struct ql_adapter *qdev);
2242 void ql_link_off(struct ql_adapter *qdev);
2243 int ql_mb_set_mgmnt_traffic_ctl(struct ql_adapter *qdev, u32 control);
2244 int ql_mb_get_port_cfg(struct ql_adapter *qdev);
2245 int ql_mb_set_port_cfg(struct ql_adapter *qdev);
2246 int ql_wait_fifo_empty(struct ql_adapter *qdev);
2247 void ql_gen_reg_dump(struct ql_adapter *qdev,
2248 struct ql_reg_dump *mpi_coredump);
2249 netdev_tx_t ql_lb_send(struct sk_buff *skb, struct net_device *ndev);
2250 void ql_check_lb_frame(struct ql_adapter *, struct sk_buff *);
2251 int ql_own_firmware(struct ql_adapter *qdev);
2252 int ql_clean_lb_rx_ring(struct rx_ring *rx_ring, int budget);
2259 /* #define QL_IB_DUMP */
2260 /* #define QL_OB_DUMP */
2264 extern void ql_dump_xgmac_control_regs(struct ql_adapter *qdev);
2265 extern void ql_dump_routing_entries(struct ql_adapter *qdev);
2266 extern void ql_dump_regs(struct ql_adapter *qdev);
2267 #define QL_DUMP_REGS(qdev) ql_dump_regs(qdev)
2268 #define QL_DUMP_ROUTE(qdev) ql_dump_routing_entries(qdev)
2269 #define QL_DUMP_XGMAC_CONTROL_REGS(qdev) ql_dump_xgmac_control_regs(qdev)
2271 #define QL_DUMP_REGS(qdev)
2272 #define QL_DUMP_ROUTE(qdev)
2273 #define QL_DUMP_XGMAC_CONTROL_REGS(qdev)
2277 extern void ql_dump_stat(struct ql_adapter *qdev);
2278 #define QL_DUMP_STAT(qdev) ql_dump_stat(qdev)
2280 #define QL_DUMP_STAT(qdev)
2284 extern void ql_dump_qdev(struct ql_adapter *qdev);
2285 #define QL_DUMP_QDEV(qdev) ql_dump_qdev(qdev)
2287 #define QL_DUMP_QDEV(qdev)
2291 extern void ql_dump_wqicb(struct wqicb *wqicb);
2292 extern void ql_dump_tx_ring(struct tx_ring *tx_ring);
2293 extern void ql_dump_ricb(struct ricb *ricb);
2294 extern void ql_dump_cqicb(struct cqicb *cqicb);
2295 extern void ql_dump_rx_ring(struct rx_ring *rx_ring);
2296 extern void ql_dump_hw_cb(struct ql_adapter *qdev, int size, u32 bit, u16 q_id);
2297 #define QL_DUMP_RICB(ricb) ql_dump_ricb(ricb)
2298 #define QL_DUMP_WQICB(wqicb) ql_dump_wqicb(wqicb)
2299 #define QL_DUMP_TX_RING(tx_ring) ql_dump_tx_ring(tx_ring)
2300 #define QL_DUMP_CQICB(cqicb) ql_dump_cqicb(cqicb)
2301 #define QL_DUMP_RX_RING(rx_ring) ql_dump_rx_ring(rx_ring)
2302 #define QL_DUMP_HW_CB(qdev, size, bit, q_id) \
2303 ql_dump_hw_cb(qdev, size, bit, q_id)
2305 #define QL_DUMP_RICB(ricb)
2306 #define QL_DUMP_WQICB(wqicb)
2307 #define QL_DUMP_TX_RING(tx_ring)
2308 #define QL_DUMP_CQICB(cqicb)
2309 #define QL_DUMP_RX_RING(rx_ring)
2310 #define QL_DUMP_HW_CB(qdev, size, bit, q_id)
2314 extern void ql_dump_tx_desc(struct tx_buf_desc *tbd);
2315 extern void ql_dump_ob_mac_iocb(struct ob_mac_iocb_req *ob_mac_iocb);
2316 extern void ql_dump_ob_mac_rsp(struct ob_mac_iocb_rsp *ob_mac_rsp);
2317 #define QL_DUMP_OB_MAC_IOCB(ob_mac_iocb) ql_dump_ob_mac_iocb(ob_mac_iocb)
2318 #define QL_DUMP_OB_MAC_RSP(ob_mac_rsp) ql_dump_ob_mac_rsp(ob_mac_rsp)
2320 #define QL_DUMP_OB_MAC_IOCB(ob_mac_iocb)
2321 #define QL_DUMP_OB_MAC_RSP(ob_mac_rsp)
2325 extern void ql_dump_ib_mac_rsp(struct ib_mac_iocb_rsp *ib_mac_rsp);
2326 #define QL_DUMP_IB_MAC_RSP(ib_mac_rsp) ql_dump_ib_mac_rsp(ib_mac_rsp)
2328 #define QL_DUMP_IB_MAC_RSP(ib_mac_rsp)
2332 extern void ql_dump_all(struct ql_adapter *qdev);
2333 #define QL_DUMP_ALL(qdev) ql_dump_all(qdev)
2335 #define QL_DUMP_ALL(qdev)
2338 #endif /* _QLGE_H_ */